[Mlir-commits] [mlir] [mlir][mem2reg] Promote whole-buffer memref to a vector SSA value (PR #211880)

[Renato Golin]

https://github.com/rengolin commented:

> Such a buffer is effectively an SSA vector spilled to the stack, and it blocks downstream vectorization and register allocation.

Yes, this may be another effect of the one-shot bufferization that @matthias-springer was looking into a while ago. We are seeing this in Lighthouse and I keep leaving it "for later", but we do need to fix it.

IIUC, there are two ways to fix this: 1. write a cleanup pass that removes the alloca/read/write (which is what you propose here, and I support); and 2. Vectorize at tensor level before bufferization, which bypasses some bufferization stages, and is easier to reason about because it's still in value semantics.

The latter is what we do in Lighthouse, mostly because of the value semantics bit, but there are still left over buffers, for instance, with mixed precision (we need to allocate the temporary high precision accumulators), so it gets harder to match tensor/memref/vector patterns all together.

What I also see is the `zero` tile being propagated inside the loop, so you have a `linalg.fill` _outside_ of the loop on the entire shape (using only subviews) and another inside, using the tile alloca + copy inside. Totally unnecessary.

https://github.com/llvm/llvm-project/pull/211880