[Mlir-commits] [mlir] [mlir][Vector] Reject invalid inline yields (PR #206218)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Fri Jul 24 07:36:56 PDT 2026
================
@@ -794,3 +794,18 @@ llvm.func @caller_cf_br_terminator(%arg0 : i64) -> i64 {
%0 = llvm.call @callee_cf_br_terminator(%arg0) : (i64) -> i64
llvm.return %0 : i64
}
+
+// -----
+// Skip callees with non-LLVM function exits.
+
+llvm.func @callee_vector_yield_terminator(%arg0 : vector<8xf32>) {
+ %0 = math.atanh %arg0 : vector<8xf32>
+ vector.yield %0 : vector<8xf32>
+}
+
----------------
PragmaTwice wrote:
I don't think this is the correct way to solve the problem. I think in the original issue (likely produced by a fuzzer) the input IR is just invalid. There is no real IR that use `vector.yield` as a terminator of a `llvm.func` region.
https://github.com/llvm/llvm-project/pull/206218
More information about the Mlir-commits
mailing list