[Mlir-commits] [mlir] [mlir][SPIRV] Add SPIRVToLLVM conversion for selection with yielding values (PR #210600)
Vito Secona
llvmlistbot at llvm.org
Mon Jul 20 06:05:55 PDT 2026
https://github.com/secona updated https://github.com/llvm/llvm-project/pull/210600
>From 8aa7d419ee5c0751b557f46e2881d94e902ea37e Mon Sep 17 00:00:00 2001
From: Vito Secona <secona00 at gmail.com>
Date: Sun, 19 Jul 2026 20:57:19 +0700
Subject: [PATCH 1/4] [mlir][SPIRV] Add SPIRVToLLVM conversion for selection
with yielding values
---
.../Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp | 8 +++
.../SPIRVToLLVM/control-flow-ops-to-llvm.mlir | 56 +++++++++++++++++++
2 files changed, 64 insertions(+)
diff --git a/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp b/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
index c5f9305a5c226..2982061c957e0 100644
--- a/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+++ b/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
@@ -1470,6 +1470,14 @@ class SelectionPattern : public SPIRVToLLVMConversion<spirv::SelectionOp> {
auto position = rewriter.getInsertionPoint();
auto *continueBlock = rewriter.splitBlock(currentBlock, position);
+ // Add arguments to the continue block for selections that yield values.
+ for (auto ty : op.getResultTypes()) {
+ Type dstTy = getTypeConverter()->convertType(ty);
+ if (!dstTy)
+ return rewriter.notifyMatchFailure(op, "failed to convert type");
+ continueBlock->addArgument(dstTy, loc);
+ }
+
// Extract conditional branch information from the header block. By SPIR-V
// dialect spec, it should contain `spirv.BranchConditional` or
// `spirv.Switch` op. Note that `spirv.Switch op` is not supported at the
diff --git a/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir b/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
index ec47dd31cc637..389a21681bafb 100644
--- a/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
+++ b/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
@@ -214,6 +214,62 @@ spirv.module Logical GLSL450 {
%one = spirv.Constant 1 : i32
spirv.ReturnValue %one : i32
}
+
+ spirv.func @selection_with_yielding_value(%cond: i1) -> i32 "None" {
+ // CHECK: llvm.cond_br %{{.*}}, ^bb1, ^bb2
+ %0 = spirv.mlir.selection -> i32 {
+ spirv.BranchConditional %cond, ^true, ^false
+ // CHECK: ^bb1:
+ ^true:
+ // CHECK: %[[C1:.*]] = llvm.mlir.constant(1 : i32) : i32
+ %cst1 = spirv.Constant 1 : i32
+ // CHECK: llvm.br ^bb3(%[[C1]] : i32)
+ spirv.Branch ^merge(%cst1 : i32)
+ // CHECK: ^bb2:
+ ^false:
+ // CHECK: %[[C2:.*]] = llvm.mlir.constant(2 : i32) : i32
+ %cst2 = spirv.Constant 2 : i32
+ // CHECK: llvm.br ^bb3(%[[C2]] : i32)
+ spirv.Branch ^merge(%cst2 : i32)
+ // CHECK: ^bb3(%[[ARG:.*]]: i32):
+ ^merge(%1: i32):
+ // CHECK: llvm.br ^bb4(%[[ARG]] : i32)
+ spirv.mlir.merge %1 : i32
+ }
+ // CHECK: ^bb4({{.*}}):
+ %one = spirv.Constant 1 : i32
+ spirv.ReturnValue %one : i32
+ }
+
+ spirv.func @selection_with_multiple_yielding_values(%cond: i1) -> i32 "None" {
+ // CHECK: llvm.cond_br %{{.*}}, ^bb1, ^bb2
+ %0:2 = spirv.mlir.selection -> i32, i32 {
+ spirv.BranchConditional %cond, ^true, ^false
+ // CHECK: ^bb1:
+ ^true:
+ // CHECK: %[[C1:.*]] = llvm.mlir.constant(1 : i32) : i32
+ %cst1 = spirv.Constant 1 : i32
+ // CHECK: %[[C3:.*]] = llvm.mlir.constant(3 : i32) : i32
+ %cst3 = spirv.Constant 3 : i32
+ // CHECK: llvm.br ^bb3(%[[C1]], %[[C3]] : i32, i32)
+ spirv.Branch ^merge(%cst1, %cst3 : i32, i32)
+ // CHECK: ^bb2:
+ ^false:
+ // CHECK: %[[C2:.*]] = llvm.mlir.constant(2 : i32) : i32
+ %cst2 = spirv.Constant 2 : i32
+ // CHECK: %[[C4:.*]] = llvm.mlir.constant(4 : i32) : i32
+ %cst4 = spirv.Constant 4 : i32
+ // CHECK: llvm.br ^bb3(%[[C2]], %[[C4]] : i32, i32)
+ spirv.Branch ^merge(%cst2, %cst4 : i32, i32)
+ // CHECK: ^bb3(%[[ARG:.*]]: i32, %[[ARG1:.*]]: i32):
+ ^merge(%1: i32, %2: i32):
+ // CHECK: llvm.br ^bb4(%[[ARG]], %[[ARG1]] : i32, i32)
+ spirv.mlir.merge %1, %2 : i32, i32
+ }
+ // CHECK: ^bb4({{.*}}):
+ %one = spirv.Constant 1 : i32
+ spirv.ReturnValue %one : i32
+ }
}
// -----
>From edb194920ba746b10ee7f900cd75871e053801ab Mon Sep 17 00:00:00 2001
From: Vito Secona <secona00 at gmail.com>
Date: Mon, 20 Jul 2026 19:52:25 +0700
Subject: [PATCH 2/4] test: clearer 1 value and 2 values
---
.../test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir b/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
index 389a21681bafb..769e9a0c61c20 100644
--- a/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
+++ b/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
@@ -236,7 +236,7 @@ spirv.module Logical GLSL450 {
// CHECK: llvm.br ^bb4(%[[ARG]] : i32)
spirv.mlir.merge %1 : i32
}
- // CHECK: ^bb4({{.*}}):
+ // CHECK: ^bb4({{.*}}: i32):
%one = spirv.Constant 1 : i32
spirv.ReturnValue %one : i32
}
@@ -266,7 +266,7 @@ spirv.module Logical GLSL450 {
// CHECK: llvm.br ^bb4(%[[ARG]], %[[ARG1]] : i32, i32)
spirv.mlir.merge %1, %2 : i32, i32
}
- // CHECK: ^bb4({{.*}}):
+ // CHECK: ^bb4({{.*}}: i32, {{.*}}: i32):
%one = spirv.Constant 1 : i32
spirv.ReturnValue %one : i32
}
>From 82837f0c3afd8b41035dd093319dfd59140d780f Mon Sep 17 00:00:00 2001
From: Vito Secona <secona00 at gmail.com>
Date: Mon, 20 Jul 2026 20:03:19 +0700
Subject: [PATCH 3/4] test: return %0 in selection_with_yielding_value
---
mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir b/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
index 769e9a0c61c20..a043dafac6341 100644
--- a/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
+++ b/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
@@ -237,8 +237,7 @@ spirv.module Logical GLSL450 {
spirv.mlir.merge %1 : i32
}
// CHECK: ^bb4({{.*}}: i32):
- %one = spirv.Constant 1 : i32
- spirv.ReturnValue %one : i32
+ spirv.ReturnValue %0 : i32
}
spirv.func @selection_with_multiple_yielding_values(%cond: i1) -> i32 "None" {
>From 26692812ded5658eea4eacc49d105cc0978e732a Mon Sep 17 00:00:00 2001
From: Vito Secona <secona00 at gmail.com>
Date: Mon, 20 Jul 2026 20:05:28 +0700
Subject: [PATCH 4/4] test: use both values in
selection_with_multiple_yielding_values
---
.../Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir b/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
index a043dafac6341..1a946dd5df9ac 100644
--- a/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
+++ b/mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
@@ -266,8 +266,9 @@ spirv.module Logical GLSL450 {
spirv.mlir.merge %1, %2 : i32, i32
}
// CHECK: ^bb4({{.*}}: i32, {{.*}}: i32):
- %one = spirv.Constant 1 : i32
- spirv.ReturnValue %one : i32
+ // Makes sure both values are used.
+ %sum = spirv.IAdd %0#0, %0#1 : i32
+ spirv.ReturnValue %sum : i32
}
}
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