[Mlir-commits] [mlir] [MLIR][NVGPU] Add convert.fpext and convert.fptrunc Ops (PR #199700)

[Srinivasa Ravi]

================
@@ -671,4 +671,78 @@ def NVGPU_RcpOp : NVGPU_Op<"rcp", [Pure,
   let hasVerifier = 1;
 }
 
+//===----------------------------------------------------------------------===//
+// NVGPU Conversion Ops
+//===----------------------------------------------------------------------===//
+
+def AnyI32Like : TypeOrValueSemanticsContainer<I32, "scalar i32 or vector of i32">;
+
+// nvgpu.convert.fptrunc only supports the satfinite and none saturation modes.
+def NVGPU_SaturationModeSatfiniteOrNone :
+  ConfinedAttr<SaturationModeAttr, [EnumAttrIsOneOf<SaturationModeAttr,
+                [SaturationModeNone, SaturationModeFinite]>]>;
+
+def NVGPU_ConvertFPTruncOp : NVGPU_Op<"convert.fptrunc", [Pure]> {
+  let summary = "Truncate floating-point to narrower floating-point";
+  let description = [{
+    Truncate a floating-point value to a smaller floating-point type.
+    Destination must be strictly narrower than source.
+
+    Supported paths:
+      f64 -> f32, f16, bf16
+      f32 -> f16, bf16, f8, f6, f4
+      f16 -> f8, f6, f4
+      bf16 -> f8, f6, f4
+
+    The `random_bits` operand enables stochastic rounding (RS mode) for
+    f32->f16/bf16 conversions; when provided, `rnd` must be RS.
+
+    Example:
+    ```mlir
+    %r = nvgpu.convert.fptrunc %in : vector<8xf32> to vector<8xf8E4M3FN>
+    %r = nvgpu.convert.fptrunc %in : vector<8xf32> to vector<8xf6E2M3FN>
+    %r = nvgpu.convert.fptrunc %in : f32 to f16
+    %r = nvgpu.convert.fptrunc %in : vector<2x4xf16> to vector<2x4xf8E5M2>
+    ```
+  }];
+  let arguments = (ins FloatLike:$in,
+                       DefaultValuedAttr<FPRoundingModeAttr, "NVVM::FPRoundingMode::RN">:$rnd,
+                       DefaultValuedAttr<NVGPU_SaturationModeSatfiniteOrNone, "NVVM::SaturationMode::SATFINITE">:$sat,
----------------
Wolfram70 wrote:

Makes sense, fixed!

https://github.com/llvm/llvm-project/pull/199700