[Mlir-commits] [flang] [llvm] [mlir] [NFC] Fix typo `instrinsic` -> `intrinsic` (PR #177627)

[Rahul Joshi]

https://github.com/jurahul created https://github.com/llvm/llvm-project/pull/177627

None

>From 99fa20a8bcbc2061ee141ad7e5bdab740fe3eefb Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Fri, 23 Jan 2026 09:39:53 -0800
Subject: [PATCH] [NFC] Fix typo `instrinsic` -> `intrinsic`

---
 flang/test/Lower/CUDA/cuda-synchronization.cuf      | 2 +-
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h | 2 +-
 llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp  | 2 +-
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp     | 2 +-
 mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td       | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/flang/test/Lower/CUDA/cuda-synchronization.cuf b/flang/test/Lower/CUDA/cuda-synchronization.cuf
index 6e2e23423c360..d98c7a3a321c0 100644
--- a/flang/test/Lower/CUDA/cuda-synchronization.cuf
+++ b/flang/test/Lower/CUDA/cuda-synchronization.cuf
@@ -1,6 +1,6 @@
 ! RUN: bbc -emit-hlfir -fcuda %s -o - | FileCheck %s
 
-! Test CUDA Fortran instrinsics lowerings for synchronization.
+! Test CUDA Fortran intrinsics lowerings for synchronization.
 
 attributes(global) subroutine sync()
   call threadfence()
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index 3b4be7ff4cb83..ff87df25e227c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -312,7 +312,7 @@ class SetOfRulesForOpcode {
 class RegBankLegalizeRules {
   const GCNSubtarget *ST;
   MachineRegisterInfo *MRI;
-  // Separate maps for G-opcodes and instrinsics since they are in different
+  // Separate maps for G-opcodes and intrinsics since they are in different
   // enums. Multiple opcodes can share same set of rules.
   // RulesAlias = map<Opcode, KeyOpcode>
   // Rules = map<KeyOpcode, SetOfRulesForOpcode>
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 23cfb326bc8d9..fbc37e968b289 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -524,7 +524,7 @@ static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) {
 // or reduce our dependence on the global registry, so we can remove this
 // function. It can easily be missed when new intrinsics are added.
 
-// Most SPIR-V instrinsics are considered to have side-effects in their tablegen
+// Most SPIR-V intrinsics are considered to have side-effects in their tablegen
 // definition because they are referenced in the global registry. This is a list
 // of intrinsics that have no side effects other than their references in the
 // global registry.
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 22b8ea481f2c3..bb0c01806cec7 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -607,7 +607,7 @@ static bool isCommutableOperand(Instruction *I, Value *ValWithUses, unsigned Op,
 static bool isCommutative(Instruction *I) { return isCommutative(I, I); }
 
 /// \returns number of operands of \p I, considering commutativity. Returns 2
-/// for commutative instrinsics.
+/// for commutative intrinsics.
 /// \param I The instruction to check for commutativity
 static unsigned getNumberOfPotentiallyCommutativeOps(Instruction *I) {
   if (isa<IntrinsicInst>(I) && isCommutative(I)) {
diff --git a/mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td b/mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
index d055bb4da09f8..38cfb3474f2f1 100644
--- a/mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
+++ b/mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
@@ -590,7 +590,7 @@ def DupQLaneOp : ArmSVE_Op<"dupq_lane", [Pure, AllTypesMatch<["src", "dst"]>]> {
     // %V = [A B C D E F H A B C D E F H]
     ```
 
-    Note: The semantics of the operation match those of the `svdupq_lane` instrinsics.
+    Note: The semantics of the operation match those of the `svdupq_lane` intrinsics.
     [Source](https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=svdupq_lane)
   }];