[Mlir-commits] [mlir] [MLIR][XeGPU] Add uArch limitation to scatter load store (PR #172845)

[Jianhui Li]

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@@ -153,3 +153,47 @@ func.func @scatter_ops_chunksize(%src: memref<256xf16>) {
   return
 }
 }
+
+// -----
+
+gpu.module @test {
----------------
Jianhui-Li wrote:

Can you add the test to cover the slice attribute propagation? 
1) reducing dim 0. in this case inst_data can still be [8, 16]
    %6 = xegpu.load %5[%4], %cst  {layout_result_0 = #xegpu.slice<#xegpu.layout<sg_layout = [8, 8], sg_data = [32, 32], inst_data = [8, 16]>, dims = [0]>} : i64, vector<256xindex>, vector<256xi1> -> vector<256xf32>
    %7 = vector.broadcast %6 {layout_result_0 = #xegpu.layout<sg_layout = [8, 8], sg_data = [32, 32], inst_data = [8, 16]>} : vector<256xf32> to vector<256x256xf32>

2) reducing dim 1, in this case inst_data should be [1, 16]. meaning the xegpu.load would be split to 8 separate load. 
    %6 = xegpu.load %5[%4], %cst  {layout_result_0 = #xegpu.slice<#xegpu.layout<sg_layout = [8, 8], sg_data = [32, 32], inst_data = [**1**, 16]>, dims = [1]>} : i64, vector<256xindex>, vector<256xi1> -> vector<256xf32>
    %7 = vector.broadcast %6 {layout_result_0 = #xegpu.layout<sg_layout = [8, 8], sg_data = [32, 32], inst_data = [8, 16]>} : vector<256xf32> to vector<256x256xf32>

https://github.com/llvm/llvm-project/pull/172845