[Mlir-commits] [clang] [llvm] [mlir] [AArch64][llvm] Improve codegen for svldr_vnum_za/svstr_vnum_za (PR #175785)

[llvmlistbot at llvm.org]

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@@ -6099,7 +6099,7 @@ SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
   SDValue TileSlice = N->getOperand(2);
   SDValue Base = N->getOperand(3);
   SDValue VecNum = N->getOperand(4);
-  int32_t ConstAddend = 0;
+  int64_t ConstAddend = 0;
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Lukacma wrote:

I hope it will not be too much bother, but I think that since we are fixing these intrinsics, we should fix them properly. Emitting necessary add and mul instructions for this instruction only in backend prevents optimization opportunities in middle end leading to suboptimal codegen as can be seen [here](https://godbolt.org/z/o5418379j) . As you can see other sme ld/st vnum intrinsics emit these operations when lowering to LLVM IR, enabling them to see that  MUL+RDSVL sequence needs to be emitted only once. We should follow the same procedure for these intrinsics. 

https://github.com/llvm/llvm-project/pull/175785