[Mlir-commits] [mlir] [mlir][amdgpu] Remove redundant barriers (PR #175436)

[Krzysztof Drewniak]

krzysz00 wrote:

I'd like to make a higher-level point: since it seems like https://discourse.llvm.org/t/rfc-add-memory-scope-to-gpu-barrier/81021 got driven to a rough conclusion (the default semantics or a barrier are the glpbal+local syncthreads ones - though note that my points aren't phrased in terms of MMRAs because those didn't work during that discussion) but the PR was abandoned. I'll also note that said annotations capture OpenCL semantics pretty well.

I think a good long-term solution would be to pick up that barrier memory space PR (and implementing that for AMDGPU), swapping IREE/Wave to that form (where we have barriers called out as workgroup-only at construction time), and then achieving this caninicalizarion by improving the GPU barrier elimination pass that already exists upstream.

(I think the main difference between an enhanced gpu.barrier lowering and amdgpu.lds_barrier would be losing the inline assembly workaround for MI-100, which is fine)

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Now, as to this PR ... do we have other examples of (caninicalizarion) patterns peeking at the next IR node? That feels suspicious from a pattern-matching perspective

https://github.com/llvm/llvm-project/pull/175436