[Mlir-commits] [mlir] [mlir] Consolidate patterns into `RegionBranchOpInterface` patterns (PR #174094)

[Matthias Springer]

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@@ -2229,3 +2227,39 @@ func.func @dead_index_switch_result(%arg0 : index, %arg1 : memref<i32>) -> index
   }
   return %live : index
 }
+
+// -----
+
+func.func private @side_effect()
+
+// CHECK-LABEL: func @iter_args_cycles
+//  CHECK-SAME:   (%[[LB:.*]]: index, %[[UB:.*]]: index, %[[STEP:.*]]: index, %[[A:.*]]: i32, %[[B:.*]]: i64, %[[C:.*]]: f32)
+//       CHECK:   scf.for %[[IV:.*]] = %[[LB]] to %[[UB]] step %[[STEP]] {
+//       CHECK:   func.call @side_effect()
+//   CHECK-NOT:   yield
+//       CHECK:   return %[[A]], %[[B]], %[[A]], %[[B]], %[[B]], %[[C]] : i32, i64, i32, i64, i64, f32
+func.func @iter_args_cycles(%lb : index, %ub : index, %step : index, %a : i32, %b : i64, %c : f32) -> (i32, i64, i32, i64, i64, f32) {
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matthias-springer wrote:

Note: These two new test cases were taken from #174098.


https://github.com/llvm/llvm-project/pull/174094