[Mlir-commits] [mlir] 6cdcce5 - [MLIR][NVVM] Fix crash on invalid optimization level in NVVMTargetAttr (#173280)

[llvmlistbot at llvm.org]

Author: Akimasa Watanuki
Date: 2026-01-09T18:27:49+05:30
New Revision: 6cdcce5612e745751f3b2790d682177688bd9c6f

URL: https://github.com/llvm/llvm-project/commit/6cdcce5612e745751f3b2790d682177688bd9c6f
DIFF: https://github.com/llvm/llvm-project/commit/6cdcce5612e745751f3b2790d682177688bd9c6f.diff

LOG: [MLIR][NVVM] Fix crash on invalid optimization level in NVVMTargetAttr (#173280)

Update `NVVMTargetAttr` builder in `NVVMOps.td` to use `$_get` instead
of `Base::get`.

Now the auto-generated parser calls `getChecked`, allowing graceful
error handling for invalid parameters (e.g., `O=4`) instead of crashing
with an assertion failure.

Add a regression test in
`mlir/test/Dialect/LLVMIR/nvvm-target-invalid.mlir`.

Fixes: https://github.com/llvm/llvm-project/issues/130014

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
    mlir/test/Dialect/LLVMIR/nvvm-target-invalid.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
index 853b2800bc0ff..7a45604dcc7e1 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
@@ -6201,7 +6201,7 @@ def NVVM_TargetAttr : NVVM_Attr<"NVVMTarget", "target",
                      CArg<"DictionaryAttr", "nullptr">:$targetFlags,
                      CArg<"ArrayAttr", "nullptr">:$linkFiles,
                      CArg<"bool", "true">:$verifyTarget), [{
-      return Base::get($_ctxt, optLevel, triple, chip, features, targetFlags, linkFiles, verifyTarget);
+      return $_get($_ctxt, optLevel, triple, chip, features, targetFlags, linkFiles, verifyTarget);
     }]>
   ];
   let skipDefaultBuilders = 1;

diff  --git a/mlir/test/Dialect/LLVMIR/nvvm-target-invalid.mlir b/mlir/test/Dialect/LLVMIR/nvvm-target-invalid.mlir
index c2cfa7689978b..0f20e66dd2019 100644
--- a/mlir/test/Dialect/LLVMIR/nvvm-target-invalid.mlir
+++ b/mlir/test/Dialect/LLVMIR/nvvm-target-invalid.mlir
@@ -1,11 +1,19 @@
-// RUN: not mlir-opt %s 2>&1 | FileCheck %s
-// CHECK: 'nvvm.tcgen05.alloc' op is not supported on sm_90
+// RUN: mlir-opt -verify-diagnostics -split-input-file %s
 
 module {
-    gpu.module @mod [#nvvm.target<chip = "sm_90">] {
-        func.func @tcgen05_alloc(%arg0: !llvm.ptr<7>, %arg1: i32) {
-             nvvm.tcgen05.alloc %arg0, %arg1 : !llvm.ptr<7>, i32
-             return
-        }
+  gpu.module @tcgen05_unsupported_sm90 [#nvvm.target<chip = "sm_90">] {
+    func.func @tcgen05_alloc(%arg0: !llvm.ptr<7>, %arg1: i32) {
+      // expected-error @+1 {{'nvvm.tcgen05.alloc' op is not supported on sm_90}}
+      nvvm.tcgen05.alloc %arg0, %arg1 : !llvm.ptr<7>, i32
+      return
     }
+  }
+}
+
+// -----
+
+module attributes {gpu.container_module} {
+  // expected-error @+1 {{The optimization level must be a number between 0 and 3}}
+  gpu.module @nvvm_target_invalid_opt_level [#nvvm.target<chip = "sm_90", O = 4>] {
+  }
 }