[Mlir-commits] [mlir] [MLIR][XeGPU] Add uArch limitation to scatter load store (PR #172845)
Artem Kroviakov
llvmlistbot at llvm.org
Thu Jan 8 07:19:19 PST 2026
https://github.com/akroviakov updated https://github.com/llvm/llvm-project/pull/172845
>From 2970ef37c677866d693651082fbce8bede731089 Mon Sep 17 00:00:00 2001
From: Artem Kroviakov <artem.kroviakov at intel.com>
Date: Thu, 18 Dec 2025 12:30:40 +0000
Subject: [PATCH 1/2] [MLIR][XeGPU] Add uArch limitation to scatter load store
---
.../mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h | 34 +++++++++++++--
.../mlir/Dialect/XeGPU/uArch/uArchBase.h | 8 +++-
.../XeGPU/Transforms/XeGPUPropagateLayout.cpp | 41 +++++++++++++------
.../XeGPU/propagate-layout-inst-data.mlir | 22 ++++++++++
4 files changed, 87 insertions(+), 18 deletions(-)
diff --git a/mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h b/mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
index b3231a173f33a..055c10ab50652 100644
--- a/mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
+++ b/mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
@@ -215,6 +215,26 @@ struct SubgroupMatrixMultiplyAcc : public Instruction,
const unsigned packedFormatBitSizeB;
};
+struct StoreScatterInstruction : public Instruction {
+ StoreScatterInstruction()
+ : Instruction(InstructionKind::StoreScatter, InstructionScope::Lane) {}
+ static bool classof(const Instruction *B) {
+ return B->getInstructionKind() == InstructionKind::StoreScatter;
+ }
+
+ int32_t getMaxBitSize() const { return 128; }
+};
+
+struct LoadGatherInstruction : public Instruction {
+ LoadGatherInstruction()
+ : Instruction(InstructionKind::LoadGather, InstructionScope::Lane) {}
+ static bool classof(const Instruction *B) {
+ return B->getInstructionKind() == InstructionKind::LoadGather;
+ }
+
+ int32_t getMaxBitSize() const { return 128; }
+};
+
//===----------------------------------------------------------------------===//
// uArch instances
//===----------------------------------------------------------------------===//
@@ -225,8 +245,11 @@ struct PVCuArch final : public Xe2Plus {
static const Subgroup2DBlockLoadInstruction loadNdInst;
static const Subgroup2DBlockStoreInstruction storeNdInst;
static const Subgroup2DBlockPrefetchInstruction prefetchNdInst;
- static const Instruction *arr[] = {&dpasInst, &loadNdInst, &storeNdInst,
- &prefetchNdInst};
+ static const StoreScatterInstruction storeScatterInst;
+ static const LoadGatherInstruction loadGatherInst;
+ static const Instruction *arr[] = {&dpasInst, &loadNdInst,
+ &storeNdInst, &prefetchNdInst,
+ &storeScatterInst, &loadGatherInst};
return arr;
}
@@ -248,8 +271,11 @@ struct BMGuArch : public Xe2Plus {
static const Subgroup2DBlockLoadInstruction loadNdInst;
static const Subgroup2DBlockStoreInstruction storeNdInst;
static const Subgroup2DBlockPrefetchInstruction prefetchNdInst;
- static const Instruction *arr[] = {&dpasInst, &loadNdInst, &storeNdInst,
- &prefetchNdInst};
+ static const StoreScatterInstruction storeScatterInst;
+ static const LoadGatherInstruction loadGatherInst;
+ static const Instruction *arr[] = {&dpasInst, &loadNdInst,
+ &storeNdInst, &prefetchNdInst,
+ &storeScatterInst, &loadGatherInst};
return arr;
}
diff --git a/mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h b/mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h
index 8f23b89134773..db1984b2edb1d 100644
--- a/mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h
+++ b/mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h
@@ -38,7 +38,9 @@ enum class InstructionKind {
// matrix multiply-add operation
Subgroup2DBlockStore, // Subgroup-level 2D block write instruction
Subgroup2DBlockLoad, // Subgroup-level 2D block load instruction
- Subgroup2DBlockPrefetch // Subgroup-level 2D block prefetch instruction
+ Subgroup2DBlockPrefetch, // Subgroup-level 2D block prefetch instruction
+ StoreScatter, // Lane-level store (scalar, vector)
+ LoadGather // Lane-level load (scalar, vector)
// @TODO: Add more instructions as needed
};
@@ -65,6 +67,10 @@ struct Instruction {
return "load_nd";
case InstructionKind::Subgroup2DBlockPrefetch:
return "prefetch_nd";
+ case InstructionKind::StoreScatter:
+ return "store";
+ case InstructionKind::LoadGather:
+ return "load";
}
llvm_unreachable("Unknown InstructionKind");
}
diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
index 3ac23f348f8a9..76fa7c0e2698d 100644
--- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
@@ -986,15 +986,21 @@ void LayoutInfoPropagation::visitLoadGatherOp(
return;
}
auto uArch = getUArch(getChipStr(load).value_or(""));
+ const auto *uArchInstruction =
+ dyn_cast<xegpu::uArch::LoadGatherInstruction>(
+ uArch->getInstruction(xegpu::uArch::InstructionKind::LoadGather));
+ const int maxElemsPerInst =
+ uArchInstruction->getMaxBitSize() /
+ payloadTy.getElementType().getIntOrFloatBitWidth();
+
const int subgroupSize = uArch->getSubgroupSize();
SmallVector<int> instData{subgroupSize};
- if (auto chunkSize = load.getChunkSize().value_or(0); chunkSize > 1)
- instData.push_back(chunkSize);
- else if (auto srcTdescTy =
- dyn_cast<xegpu::TensorDescType>(load.getSourceType())) {
- if (srcTdescTy.getChunkSizeAsInt() > 1)
- instData.push_back(chunkSize);
+ auto chunkSize = load.getChunkSize().value_or(0);
+ if (auto srcTdescTy = dyn_cast<xegpu::TensorDescType>(load.getSourceType());
+ !chunkSize && srcTdescTy) {
+ chunkSize = srcTdescTy.getChunkSizeAsInt();
}
+ instData.push_back(std::min(static_cast<int>(chunkSize), maxElemsPerInst));
if (layoutKind == LayoutKind::InstData)
loadLayout =
@@ -1060,15 +1066,24 @@ void LayoutInfoPropagation::visitStoreScatterOp(
const int subgroupSize = uArch->getSubgroupSize();
if (layoutKind == LayoutKind::InstData) {
+ const auto *uArchInstruction =
+ dyn_cast<xegpu::uArch::LoadGatherInstruction>(
+ uArch->getInstruction(xegpu::uArch::InstructionKind::LoadGather));
+ const int maxElemsPerInst =
+ uArchInstruction->getMaxBitSize() /
+ payloadTy.getElementType().getIntOrFloatBitWidth();
+
+ const int subgroupSize = uArch->getSubgroupSize();
SmallVector<int> instData{subgroupSize};
- if (auto chunkSize = storeScatter.getChunkSize().value_or(0);
- chunkSize > 1)
- instData.push_back(chunkSize);
- else if (auto dstTdescTy = dyn_cast<xegpu::TensorDescType>(
- storeScatter.getDestType())) {
- if (dstTdescTy.getChunkSizeAsInt() > 1)
- instData.push_back(chunkSize);
+ auto chunkSize = storeScatter.getChunkSize().value_or(0);
+ if (auto srcTdescTy =
+ dyn_cast<xegpu::TensorDescType>(storeScatter.getDestType());
+ !chunkSize && srcTdescTy) {
+ chunkSize = srcTdescTy.getChunkSizeAsInt();
}
+ instData.push_back(
+ std::min(static_cast<int>(chunkSize), maxElemsPerInst));
+
payloadLayout = LayoutInfo(
xegpu::LayoutAttr::get(storeScatter.getContext(), instData));
} else {
diff --git a/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir b/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
index 5f70831f45e97..f2b270ab16218 100644
--- a/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
+++ b/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
@@ -153,3 +153,25 @@ func.func @scatter_ops_chunksize(%src: memref<256xf16>) {
return
}
}
+
+// -----
+
+gpu.module @test {
+// CHECK-LABEL: func.func @scatter_ops_chunksize_excessive(
+// CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<1024xf32>) {
+// CHECK: %{{.*}} = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<true> : vector<16xi1>
+// CHECK: %{{.*}} = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<12> : vector<16xindex>
+// CHECK: %{{.*}} = xegpu.load %[[ARG0]][%{{.*}}], %{{.*}} <{chunk_size = 16 : i64, layout = #xegpu.layout<inst_data = [16, 4]>}>
+// CHECK-SAME: {layout_result_0 = #xegpu.layout<inst_data = [16, 4]>} : memref<1024xf32>, vector<16xindex>, vector<16xi1> -> vector<16x16xf32>
+// CHECK: xegpu.store %0, %[[ARG0]][%{{.*}}], %{{.*}} <{chunk_size = 16 : i64, layout = #xegpu.layout<inst_data = [16, 4]>}> :
+// CHECK-SAME: vector<16x16xf32>, memref<1024xf32>, vector<16xindex>, vector<16xi1>
+func.func @scatter_ops_chunksize_excessive(%src: memref<1024xf32>) {
+ %1 = arith.constant dense<1>: vector<16xi1>
+ %offset = arith.constant dense<12> : vector<16xindex>
+ %3 = xegpu.load %src[%offset], %1 <{chunk_size=16}>
+ : memref<1024xf32>, vector<16xindex>, vector<16xi1> -> vector<16x16xf32>
+ xegpu.store %3, %src[%offset], %1 <{chunk_size=16}>
+ : vector<16x16xf32>, memref<1024xf32>, vector<16xindex>, vector<16xi1>
+ return
+}
+}
>From e80cad1faec06e5dabf39388343248d3047211a0 Mon Sep 17 00:00:00 2001
From: Artem Kroviakov <artem.kroviakov at intel.com>
Date: Fri, 19 Dec 2025 12:30:18 +0000
Subject: [PATCH 2/2] LoadGather to modify its inst_data
---
.../XeGPU/Transforms/XeGPUPropagateLayout.cpp | 72 +++++++++++++------
.../XeGPU/propagate-layout-inst-data.mlir | 26 ++++++-
2 files changed, 75 insertions(+), 23 deletions(-)
diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
index 76fa7c0e2698d..ef57278662cb0 100644
--- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
@@ -978,8 +978,19 @@ void LayoutInfoPropagation::visitLoadGatherOp(
loadLayout = LayoutInfo(anchorLayout);
maskLayout = loadLayout;
} else {
+ LayoutInfo valueLayout = results[0]->getValue();
+ // Need the layout of the value to propagate to the tensor descriptor.
+ if (!valueLayout.isAssigned())
+ return;
+
+ auto resAttr = dyn_cast<xegpu::DistributeLayoutAttr>(valueLayout.get());
+ auto instDataIncoming = resAttr.getEffectiveInstDataAsInt();
+ if (auto sliceAttr = dyn_cast<xegpu::SliceAttr>(resAttr))
+ instDataIncoming = SmallVector<int64_t>(
+ cast<xegpu::LayoutAttr>(sliceAttr.flatten().getParent())
+ .getInstData()
+ .asArrayRef());
- // The layout is strictly determined by the payload type.
VectorType payloadTy = load.getValueType();
if (!payloadTy) {
load.emitWarning("Not propagating, non-vector payload supplied.");
@@ -989,30 +1000,48 @@ void LayoutInfoPropagation::visitLoadGatherOp(
const auto *uArchInstruction =
dyn_cast<xegpu::uArch::LoadGatherInstruction>(
uArch->getInstruction(xegpu::uArch::InstructionKind::LoadGather));
- const int maxElemsPerInst =
- uArchInstruction->getMaxBitSize() /
- payloadTy.getElementType().getIntOrFloatBitWidth();
const int subgroupSize = uArch->getSubgroupSize();
- SmallVector<int> instData{subgroupSize};
- auto chunkSize = load.getChunkSize().value_or(0);
- if (auto srcTdescTy = dyn_cast<xegpu::TensorDescType>(load.getSourceType());
- !chunkSize && srcTdescTy) {
- chunkSize = srcTdescTy.getChunkSizeAsInt();
- }
- instData.push_back(std::min(static_cast<int>(chunkSize), maxElemsPerInst));
-
- if (layoutKind == LayoutKind::InstData)
- loadLayout =
- LayoutInfo(xegpu::LayoutAttr::get(load.getContext(), instData));
- else
- loadLayout = getDefaultSIMTLayoutInfo(
- payloadTy, uArch, uArch->getGeneralPackedFormatBitSize(),
- /*scattered*/ true);
-
// Mask operand should have 1D default layout.
maskLayout = getDefaultSIMTLayoutInfo(load->getContext(), 1, subgroupSize);
+ // Check if value inst_data complies with uArch
+ if (!instDataIncoming.empty()) {
+ const int maxElemsPerInst =
+ uArchInstruction->getMaxBitSize() /
+ payloadTy.getElementType().getIntOrFloatBitWidth();
+
+ xegpu::LayoutAttr sourceAttr;
+ // Each lane loads either one element
+ SmallVector<int> instDataUarch(instDataIncoming.size(), 1);
+ // Or multiple elements as 2D with lane's elements in the inner dimension
+ if (payloadTy.getRank() == 1) {
+ instDataUarch.back() = subgroupSize;
+ } else {
+ *std::prev(instDataUarch.end(), 2) = subgroupSize;
+ instDataUarch.back() = (std::min(
+ static_cast<int>(payloadTy.getShape().back()), maxElemsPerInst));
+ }
+ // If inst data does not match, enforce the uArch-based one
+ if (!llvm::equal(instDataIncoming, instDataUarch)) {
+ xegpu::LayoutAttr sourceAttr = dyn_cast<xegpu::LayoutAttr>(resAttr);
+ if (auto sliceAttr = dyn_cast<xegpu::SliceAttr>(resAttr)) {
+ sourceAttr = cast<xegpu::LayoutAttr>(sliceAttr.flatten().getParent());
+ }
+ assert(sourceAttr);
+ xegpu::DistributeLayoutAttr updatedLayoutAttr = xegpu::LayoutAttr::get(
+ load.getContext(), sourceAttr.getSgLayout(), sourceAttr.getSgData(),
+ DenseI32ArrayAttr::get(load.getContext(), instDataUarch),
+ sourceAttr.getLaneLayout(), sourceAttr.getLaneData(),
+ sourceAttr.getOrder());
+
+ if (auto sliceAttr = dyn_cast<xegpu::SliceAttr>(resAttr))
+ updatedLayoutAttr = xegpu::SliceAttr::get(
+ load.getContext(), updatedLayoutAttr, sliceAttr.getDims());
+ valueLayout = LayoutInfo(updatedLayoutAttr);
+ }
+ }
+ loadLayout = valueLayout;
load.setLayoutAttr(dyn_cast<xegpu::DistributeLayoutAttr>(loadLayout.get()));
}
// Propagate the new layout to the tensor descriptor operand.
@@ -1235,7 +1264,8 @@ static LogicalResult updateOp(mlir::OpBuilder &builder, mlir::Operation *op,
}
// If the result is a vector type, add a temporary layout attribute to the
// op.
- xegpu::setDistributeLayoutAttr(result, layout);
+ if (!isa<xegpu::LoadGatherOp>(op))
+ xegpu::setDistributeLayoutAttr(result, layout);
}
return success();
}
diff --git a/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir b/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
index f2b270ab16218..1fe32d380eafc 100644
--- a/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
+++ b/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
@@ -161,8 +161,8 @@ gpu.module @test {
// CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<1024xf32>) {
// CHECK: %{{.*}} = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<true> : vector<16xi1>
// CHECK: %{{.*}} = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<12> : vector<16xindex>
-// CHECK: %{{.*}} = xegpu.load %[[ARG0]][%{{.*}}], %{{.*}} <{chunk_size = 16 : i64, layout = #xegpu.layout<inst_data = [16, 4]>}>
-// CHECK-SAME: {layout_result_0 = #xegpu.layout<inst_data = [16, 4]>} : memref<1024xf32>, vector<16xindex>, vector<16xi1> -> vector<16x16xf32>
+// CHECK: %{{.*}} = xegpu.load %[[ARG0]][%{{.*}}], %{{.*}} <{chunk_size = 16 : i64, layout = #xegpu.layout<inst_data = [16, 4]>}> :
+// CHECK-SAME: memref<1024xf32>, vector<16xindex>, vector<16xi1> -> vector<16x16xf32>
// CHECK: xegpu.store %0, %[[ARG0]][%{{.*}}], %{{.*}} <{chunk_size = 16 : i64, layout = #xegpu.layout<inst_data = [16, 4]>}> :
// CHECK-SAME: vector<16x16xf32>, memref<1024xf32>, vector<16xindex>, vector<16xi1>
func.func @scatter_ops_chunksize_excessive(%src: memref<1024xf32>) {
@@ -175,3 +175,25 @@ func.func @scatter_ops_chunksize_excessive(%src: memref<1024xf32>) {
return
}
}
+
+// -----
+
+gpu.module @test {
+// CHECK-LABEL: func.func @scatter_ops_chunksize_excessive_slice(
+// CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<1024xf32>) {
+// CHECK: %{{.*}} = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<true> : vector<16xi1>
+// CHECK: %{{.*}} = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<12> : vector<16xindex>
+// CHECK: %{{.*}} = xegpu.load %[[ARG0]][%{{.*}}], %{{.*}} <{chunk_size = 16 : i64, layout = #xegpu.slice<#xegpu.layout<inst_data = [1, 16, 4]>, dims = [0]>}> :
+// CHECK-SAME: memref<1024xf32>, vector<16xindex>, vector<16xi1> -> vector<16x16xf32>
+// CHECK: xegpu.store %0, %[[ARG0]][%{{.*}}], %{{.*}} <{chunk_size = 16 : i64, layout = #xegpu.slice<#xegpu.layout<inst_data = [1, 16, 16]>, dims = [0]>}> :
+// CHECK-SAME: vector<16x16xf32>, memref<1024xf32>, vector<16xindex>, vector<16xi1>
+func.func @scatter_ops_chunksize_excessive_slice(%src: memref<1024xf32>) {
+ %1 = arith.constant dense<1>: vector<16xi1>
+ %offset = arith.constant dense<12> : vector<16xindex>
+ %3 = xegpu.load %src[%offset], %1 <{chunk_size=16}>
+ : memref<1024xf32>, vector<16xindex>, vector<16xi1> -> vector<16x16xf32>
+ xegpu.store %3, %src[%offset], %1 <{chunk_size=16, layout = #xegpu.slice<#xegpu.layout<inst_data = [1, 16, 16]>, dims = [0]>}>
+ : vector<16x16xf32>, memref<1024xf32>, vector<16xindex>, vector<16xi1>
+ return
+}
+}
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