[Mlir-commits] [mlir] [mlir][NVVM] Set SpecialRangeableRegisterOp default int range to max (PR #174544)

[Longsheng Du]

https://github.com/LongshengDu updated https://github.com/llvm/llvm-project/pull/174544

>From 42b330cb8b33c518a05c3bf5fdef1404dbf40862 Mon Sep 17 00:00:00 2001
From: Longsheng Du <longshengd at nvidia.com>
Date: Mon, 5 Jan 2026 23:53:07 -0800
Subject: [PATCH 1/2] add default max int range for nvvm ops

---
 mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
index 331d7a244310f..59f9acf140074 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
@@ -4544,6 +4544,8 @@ static void nvvmInferResultRanges(Operation *op, Value result,
   if (auto rangeAttr = op->getAttrOfType<LLVM::ConstantRangeAttr>("range")) {
     setResultRanges(result, {rangeAttr.getLower(), rangeAttr.getUpper(),
                              rangeAttr.getLower(), rangeAttr.getUpper()});
+  } else {
+    setResultRanges(result, IntegerValueRange::getMaxRange(result).getValue());
   }
 }
 

>From 5a7ecce6230a8e42ab563ceb779f834eee8cf60e Mon Sep 17 00:00:00 2001
From: Longsheng Du <longshengd at nvidia.com>
Date: Thu, 8 Jan 2026 02:46:07 -0800
Subject: [PATCH 2/2] add test

---
 mlir/test/Dialect/LLVMIR/nvvm-test-range.mlir | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/mlir/test/Dialect/LLVMIR/nvvm-test-range.mlir b/mlir/test/Dialect/LLVMIR/nvvm-test-range.mlir
index fae40dc7806ba..9b04839a05a95 100644
--- a/mlir/test/Dialect/LLVMIR/nvvm-test-range.mlir
+++ b/mlir/test/Dialect/LLVMIR/nvvm-test-range.mlir
@@ -4,6 +4,8 @@ gpu.module @module{
         %tidx = nvvm.read.ptx.sreg.tid.x range <i32, 0, 32> : i32
         %tidy = nvvm.read.ptx.sreg.tid.y range <i32, 0, 128> : i32
         %tidz = nvvm.read.ptx.sreg.tid.z range <i32, 0, 4> : i32
+        %ctaid = nvvm.read.ptx.sreg.cluster.ctaid.x : i32 // unspecified range
+        %cond = ub.poison : i1
         %c64 = arith.constant 64 : i32
         
         %1 = arith.cmpi sgt, %tidx, %c64 : i32
@@ -18,6 +20,9 @@ gpu.module @module{
         scf.if %3 {
             gpu.printf "threadidz"
         }
+        %4 = arith.select %cond, %ctaid, %c64 : i32
+        gpu.printf "ctaid", %4 : i32
+
         gpu.return
     }
 }
@@ -33,3 +38,4 @@ gpu.module @module{
 // CHECK: gpu.printf "threadidy"
 // CHECK: scf.if %[[false]] {
 // CHECK: gpu.printf "threadidz"
+// CHECK: arith.select