[Mlir-commits] [mlir] [mlir][vector] Fix masked load/store emulation for rank-0 memrefs (PR #173325)

[Andrzej Warzyński]

================
@@ -123,3 +123,16 @@ func.func @vector_maskedstore_with_alignment(%arg0 : memref<4x5xf32>, %arg1 : ve
   vector.maskedstore %arg0[%idx_0, %idx_4], %mask, %arg1 { alignment = 8 } : memref<4x5xf32>, vector<4xi1>, vector<4xf32>
   return
 }
+
+// CHECK-LABEL:  @vector_masked_load_store_rank0
+// CHECK: %[[SUBVIEW:.*]] = memref.subview
+// CHECK: memref.load %[[SUBVIEW]][]
+// CHECK: memref.store %{{.*}}, %[[SUBVIEW]][]
+func.func @vector_masked_load_store_rank0(%arg0: memref<12x32xf32>, %arg1: index,
+                                   %arg2: index, %arg3: vector<1xi1>,
+                                   %arg4: vector<1xf32>) -> vector<1xf32> {
+  %subview = memref.subview %arg0[%arg1, %arg2] [1, 1] [1, 1] : memref<12x32xf32> to memref<f32, strided<[], offset: ?>>
+  %0 = vector.maskedload %subview[], %arg3, %arg4 : memref<f32, strided<[], offset: ?>>, vector<1xi1>, vector<1xf32> into vector<1xf32>
+  vector.maskedstore %subview[], %arg3, %arg4 : memref<f32, strided<[], offset: ?>>, vector<1xi1>, vector<1xf32>
+  return %0: vector<1xf32>
+}
----------------
banach-space wrote:

[nit] Right now it's not clear where the rank-0 input is. I presume it's this:
```mlir
%subview = memref.subview %arg0[%arg1, %arg2] [1, 1] [1, 1] : memref<12x32xf32> to memref<f32, strided<[], offset: ?>>
```
Is `memref.subview` required here? Why not adjust the input MemRef? Note from https://mlir.llvm.org/getting_started/TestingGuide/#filecheck-best-practices:
> Tests should be minimal, and only check what is absolutely necessary.

Would it be possible to further reducd this? 

Also, please note that we test load and store operations separately. Again, to keep tests minimal.

https://github.com/llvm/llvm-project/pull/173325