[Mlir-commits] [mlir] [mlir] Graceful handling of non-multiple bit widths for AMDGPU swizzle bitmode lowering (PR #183580)

Arjun Bhamra llvmlistbot at llvm.org
Fri Feb 27 18:15:45 PST 2026

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abhamra wrote:

> Yeah, let's close this, sorry about sniping you

No worries at all; lots of new issues to tackle every day

https://github.com/llvm/llvm-project/pull/183580

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Next message: [Mlir-commits] [mlir] [MLIR][Arith][Vector] Reject i0 integer type in arith and vector ops (PR #183589)
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