[Mlir-commits] [mlir] [mlir] Graceful handling of non-multiple bit widths for AMDGPU swizzle bitmode lowering (PR #183580)

[Arjun Bhamra]

abhamra wrote:

> I think the better approach is to handle the case over in decomposeValues, probably after #183405 , by adding a zext to toijd ul where needed

Just to clarify, did you mean zext to i32/the nearest multiple of i32? Besides that clarification, I agree and will wait for your PR to be confirmed before I move forward. Thank you!

https://github.com/llvm/llvm-project/pull/183580