[Mlir-commits] [mlir] [mlir][LLVM] Let decomposeValue/composeValue handle aggregates (PR #183405)

[Erick Ochoa Lopez]

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@@ -410,7 +455,8 @@ SmallVector<Value> mlir::LLVM::decomposeValue(OpBuilder &builder, Location loc,
 
     auto largerInt = builder.getIntegerType(dstBitWidth);
     Value res = LLVM::ZExtOp::create(builder, loc, largerInt, src);
-    return {res};
+    result.push_back(res);
+    return;
   }
   assert(srcBitWidth % dstBitWidth == 0 &&
          "src bit width must be a multiple of dst bit width");
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amd-eochoalo wrote:

Can this assert be avoided by checking in `isFixedSizeAggregate` that this assumption will hold?

https://github.com/llvm/llvm-project/pull/183405