[Mlir-commits] [mlir] [mlir][arith] Add `exact` to `index_cast{, ui}` (PR #183395)

Erick Ochoa Lopez llvmlistbot at llvm.org
Thu Feb 26 06:33:56 PST 2026


================
@@ -290,28 +290,30 @@ def SelectI1ToNot :
 
 // index_cast(index_cast(x)) -> x, if dstType == srcType.
 def IndexCastOfIndexCast :
-    Pat<(Arith_IndexCastOp:$res (Arith_IndexCastOp $x)),
+    Pat<(Arith_IndexCastOp:$res (Arith_IndexCastOp $x, $exact1), $exact2),
         (replaceWithValue $x),
         [(Constraint<CPred<"$0.getType() == $1.getType()">> $res, $x)]>;
 
 // index_cast(extsi(x)) -> index_cast(x)
 def IndexCastOfExtSI :
-    Pat<(Arith_IndexCastOp (Arith_ExtSIOp $x)), (Arith_IndexCastOp $x)>;
+    Pat<(Arith_IndexCastOp (Arith_ExtSIOp $x), $exact),
+        (Arith_IndexCastOp $x, $exact)>;
 
 //===----------------------------------------------------------------------===//
 // IndexCastUIOp
 //===----------------------------------------------------------------------===//
 
 // index_castui(index_castui(x)) -> x, if dstType == srcType.
 def IndexCastUIOfIndexCastUI :
-    Pat<(Arith_IndexCastUIOp:$res (Arith_IndexCastUIOp $x)),
+    Pat<(Arith_IndexCastUIOp:$res
+          (Arith_IndexCastUIOp $x, $nneg1, $exact1), $nneg2, $exact2),
----------------
amd-eochoalo wrote:

Yes, I think for both:

```
index_cast(index_cast(x)), srcType = T, dstType = T, at least one exact
-------------------------------------------------------
       x
```

```
index_castui(index_castui(x)), srcType = T, dstType = T, at least one exact
-------------------------------------------------------
       x
```

hold. I think if we added `nneg` to index_cast it would enable this other one:

```
index_castui(index_cast(x, nneg, exact)), srcType = T, dstType = T, 
----------------------------------------------------------------
   x
```

Assuming index_cast had a nneg flag.
1. %0 = arith.index_cast 1 nneg exact : i32 to index (i64) // widening
2. we know sext is equivalent to zext. no information loss
3. %1 = arith.index_castui %0 exact : index (i64) to i32 // narrowing
4. truncation just removes zeros. no information loss.


But at the moment index_cast doesn't have nneg. We can however express the symmetric pattern:

```
index_cast(index_castui(x, nneg, exact)), srcType = T, dstType = T
-----------------------------------------------------------------------
    x
```

I won't add this pattern at the moment, but can add it if requested.

https://github.com/llvm/llvm-project/pull/183395


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