[Mlir-commits] [mlir] [mlir][vector] Wrapping `populateFlattenVectorTransferPatterns` as a transform pass. (PR #178134)
Arun Thangamani
llvmlistbot at llvm.org
Mon Feb 9 00:03:15 PST 2026
https://github.com/arun-thmn updated https://github.com/llvm/llvm-project/pull/178134
>From a782e6fd890175a999f04e0f135403535c8fe26c Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Mon, 26 Jan 2026 23:58:24 -0800
Subject: [PATCH 1/8] Wrapping populateFlattenVectorTransferPatterns as a
transform pass
---
.../X86Vector/TransformOps/X86VectorTransformOps.td | 11 +++++++++++
mlir/include/mlir/Dialect/X86Vector/Transforms.h | 5 +++++
.../X86Vector/TransformOps/X86VectorTransformOps.cpp | 7 +++++++
3 files changed, 23 insertions(+)
diff --git a/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td b/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
index 891829fca017f..4c953abc125bc 100644
--- a/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
+++ b/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
@@ -71,6 +71,17 @@ def ApplyShuffleVectorFMAOpsPatternsOp : Op<Transform_Dialect,
let assemblyFormat = "attr-dict";
}
+def ApplyFlattenVectorTransferOpsPatternsOp : Op<Transform_Dialect,
+ "apply_patterns.x86vector.flatten_vector_transfer_ops",
+ [DeclareOpInterfaceMethods<PatternDescriptorOpInterface>]> {
+ let description = [{
+ Collect patterns to rewrite contiguous row-major vector.transfer_read or
+ vector.transfer_write operations to a 1D operation.
+ }];
+
+ let assemblyFormat = "attr-dict";
+}
+
#endif // X86VECTOR_TRANSFORM_OPS
diff --git a/mlir/include/mlir/Dialect/X86Vector/Transforms.h b/mlir/include/mlir/Dialect/X86Vector/Transforms.h
index aadca92708908..3c73a2e172487 100644
--- a/mlir/include/mlir/Dialect/X86Vector/Transforms.h
+++ b/mlir/include/mlir/Dialect/X86Vector/Transforms.h
@@ -104,6 +104,11 @@ void populateSinkVectorProducerOpsPatterns(RewritePatternSet &patterns);
// grouped with respect to odd/even packed index.
void populateShuffleVectorFMAOpsPatterns(RewritePatternSet &patterns);
+// Rewrites contiguous row-major vector.transfer_read or vector.transfer_write
+// operations by inserting a memref.collapse_shape on the source,
+// transforming the operation to use a 1D source.
+void populateFlattenVectorTransferOpsPatterns(RewritePatternSet &patterns);
+
//===----------------------------------------------------------------------===//
/// Helpers extracted from:
/// - clang/lib/Headers/avxintrin.h
diff --git a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
index c6be69305da50..57b0cfc162b8d 100644
--- a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
+++ b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
@@ -12,6 +12,7 @@
#include "mlir/Dialect/Transform/IR/TransformDialect.h"
#include "mlir/Dialect/Transform/Interfaces/TransformInterfaces.h"
#include "mlir/Dialect/Vector/IR/VectorOps.h"
+#include "mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h"
#include "mlir/Dialect/X86Vector/Transforms.h"
#include "mlir/Dialect/X86Vector/X86VectorDialect.h"
@@ -21,6 +22,7 @@
using namespace mlir;
using namespace mlir::x86vector;
using namespace mlir::transform;
+using namespace mlir::vector;
void mlir::transform::ApplyVectorContractToFMAPatternsOp::populatePatterns(
RewritePatternSet &patterns) {
@@ -47,6 +49,11 @@ void mlir::transform::ApplyShuffleVectorFMAOpsPatternsOp::populatePatterns(
x86vector::populateShuffleVectorFMAOpsPatterns(patterns);
}
+void mlir::transform::ApplyFlattenVectorTransferOpsPatternsOp::
+ populatePatterns(RewritePatternSet &patterns) {
+ vector::populateFlattenVectorTransferPatterns(patterns);
+}
+
//===----------------------------------------------------------------------===//
// Transform op registration
//===----------------------------------------------------------------------===//
>From 1887de8f1f9e8dc33654ae545e0e309ea385a09a Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Tue, 27 Jan 2026 00:07:31 -0800
Subject: [PATCH 2/8] fixing a clang-format error
---
.../Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
index 57b0cfc162b8d..cfc6c4194f5af 100644
--- a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
+++ b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
@@ -49,8 +49,8 @@ void mlir::transform::ApplyShuffleVectorFMAOpsPatternsOp::populatePatterns(
x86vector::populateShuffleVectorFMAOpsPatterns(patterns);
}
-void mlir::transform::ApplyFlattenVectorTransferOpsPatternsOp::
- populatePatterns(RewritePatternSet &patterns) {
+void mlir::transform::ApplyFlattenVectorTransferOpsPatternsOp::populatePatterns(
+ RewritePatternSet &patterns) {
vector::populateFlattenVectorTransferPatterns(patterns);
}
>From 32eeea8f5f1d5858ff0149dc0270c6fdf7e1b7e8 Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Tue, 27 Jan 2026 07:20:54 -0800
Subject: [PATCH 3/8] added an argument + one test-case for validation
---
.../X86Vector/TransformOps/X86VectorTransformOps.td | 10 ++++++++--
mlir/include/mlir/Dialect/X86Vector/Transforms.h | 4 +++-
.../X86Vector/TransformOps/X86VectorTransformOps.cpp | 3 ++-
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td b/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
index 4c953abc125bc..f41caa87f7375 100644
--- a/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
+++ b/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
@@ -79,9 +79,15 @@ def ApplyFlattenVectorTransferOpsPatternsOp : Op<Transform_Dialect,
vector.transfer_write operations to a 1D operation.
}];
- let assemblyFormat = "attr-dict";
-}
+ let arguments = (ins
+ DefaultValuedAttr<UI32Attr,
+ "std::numeric_limits<unsigned>::max()">:$target_vector_bitwidth
+ );
+ let assemblyFormat = [{
+ (`target_vector_bitwidth` `=` $target_vector_bitwidth^)? attr-dict
+ }];
+}
#endif // X86VECTOR_TRANSFORM_OPS
diff --git a/mlir/include/mlir/Dialect/X86Vector/Transforms.h b/mlir/include/mlir/Dialect/X86Vector/Transforms.h
index 3c73a2e172487..f2a1d58f42c1f 100644
--- a/mlir/include/mlir/Dialect/X86Vector/Transforms.h
+++ b/mlir/include/mlir/Dialect/X86Vector/Transforms.h
@@ -107,7 +107,9 @@ void populateShuffleVectorFMAOpsPatterns(RewritePatternSet &patterns);
// Rewrites contiguous row-major vector.transfer_read or vector.transfer_write
// operations by inserting a memref.collapse_shape on the source,
// transforming the operation to use a 1D source.
-void populateFlattenVectorTransferOpsPatterns(RewritePatternSet &patterns);
+void populateFlattenVectorTransferOpsPatterns(
+ RewritePatternSet &patterns,
+ unsigned targetVectorBitwidth = std::numeric_limits<unsigned>::max());
//===----------------------------------------------------------------------===//
/// Helpers extracted from:
diff --git a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
index cfc6c4194f5af..7601966a4652c 100644
--- a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
+++ b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
@@ -51,7 +51,8 @@ void mlir::transform::ApplyShuffleVectorFMAOpsPatternsOp::populatePatterns(
void mlir::transform::ApplyFlattenVectorTransferOpsPatternsOp::populatePatterns(
RewritePatternSet &patterns) {
- vector::populateFlattenVectorTransferPatterns(patterns);
+ vector::populateFlattenVectorTransferPatterns(patterns,
+ getTargetVectorBitwidth());
}
//===----------------------------------------------------------------------===//
>From ad9384d161233bec3cf9e977d2ce68913ff0be62 Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Tue, 27 Jan 2026 07:21:58 -0800
Subject: [PATCH 4/8] added an argument + one test-case for validation
---
.../flatten-vector-transfer-ops.mlir | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 mlir/test/Dialect/X86Vector/flatten-vector-transfer-ops.mlir
diff --git a/mlir/test/Dialect/X86Vector/flatten-vector-transfer-ops.mlir b/mlir/test/Dialect/X86Vector/flatten-vector-transfer-ops.mlir
new file mode 100644
index 0000000000000..40c39c5f51c2a
--- /dev/null
+++ b/mlir/test/Dialect/X86Vector/flatten-vector-transfer-ops.mlir
@@ -0,0 +1,31 @@
+// RUN: mlir-opt %s -transform-interpreter -cse -split-input-file | FileCheck %s
+
+func.func @flatten_transfer_ops(%arg0: memref<16x16xf32>, %arg1: vector<8xf32>) -> vector<8xf32> {
+ %c0 = arith.constant 0 : index
+ %c8 = arith.constant 8 : index
+ %b0 = ub.poison : f32
+ %0 = vector.transfer_read %arg0[%c0, %c0], %b0 {in_bounds = [true, true]} : memref<16x16xf32>, vector<1x8xf32>
+ %1 = vector.transfer_read %arg0[%c0, %c8], %b0 {in_bounds = [true, true]} : memref<16x16xf32>, vector<1x8xf32>
+ %2 = vector.shape_cast %0 : vector<1x8xf32> to vector<8xf32>
+ %3 = vector.shape_cast %1 : vector<1x8xf32> to vector<8xf32>
+ %4 = vector.fma %2, %3, %arg1 : vector<8xf32>
+ return %4 : vector<8xf32>
+}
+
+// CHECK-LABEL: @flatten_transfer_ops
+// CHECK-NOT: vector.transfer_read {{.*}}, vector<1x8xf32>
+// CHECK-NOT: vector.transfer_read {{.*}}, vector<1x8xf32>
+// CHECK: vector.transfer_read {{.*}}, vector<8xf32>
+// CHECK-NEXT: vector.transfer_read {{.*}}, vector<8xf32>
+// CHECK-NOT: vector.shape_cast
+// CHECK-NOT: vector.shape_cast
+
+module attributes {transform.with_named_sequence} {
+ transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
+ %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
+ transform.apply_patterns to %func {
+ transform.apply_patterns.x86vector.flatten_vector_transfer_ops
+ } : !transform.any_op
+ transform.yield
+ }
+}
>From 3daa0e9c9b786fa1509b222542833960a39911f5 Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Fri, 30 Jan 2026 19:33:41 -0800
Subject: [PATCH 5/8] moving the schedule to vector dialect
---
.../Vector/TransformOps/VectorTransformOps.td | 18 ++++++++++++++++++
.../TransformOps/X86VectorTransformOps.td | 18 ------------------
.../mlir/Dialect/X86Vector/Transforms.h | 7 -------
.../Vector/TransformOps/VectorTransformOps.cpp | 6 ++++++
.../TransformOps/X86VectorTransformOps.cpp | 7 -------
.../flatten-vector-transfer-ops.mlir | 2 +-
.../python/dialects/transform_vector_ext.py | 2 ++
7 files changed, 27 insertions(+), 33 deletions(-)
rename mlir/test/Dialect/{X86Vector => Vector}/flatten-vector-transfer-ops.mlir (95%)
diff --git a/mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td b/mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
index 03d25505dc65c..c9668fe30e648 100644
--- a/mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
+++ b/mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
@@ -539,4 +539,22 @@ def ApplySinkVectorMemPatternsOp : Op<Transform_Dialect,
let assemblyFormat = "attr-dict";
}
+def ApplyFlattenVectorTransferOpsPatternsOp : Op<Transform_Dialect,
+ "apply_patterns.vector.flatten_vector_transfer_ops",
+ [DeclareOpInterfaceMethods<PatternDescriptorOpInterface>]> {
+ let description = [{
+ Collect patterns to rewrite contiguous row-major vector.transfer_read or
+ vector.transfer_write operations to a 1D operation.
+ }];
+
+ let arguments = (ins
+ DefaultValuedAttr<UI32Attr,
+ "std::numeric_limits<unsigned>::max()">:$target_vector_bitwidth
+ );
+
+ let assemblyFormat = [{
+ (`target_vector_bitwidth` `=` $target_vector_bitwidth^)? attr-dict
+ }];
+}
+
#endif // VECTOR_TRANSFORM_OPS
diff --git a/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td b/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
index f41caa87f7375..1fb663ec27325 100644
--- a/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
+++ b/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
@@ -71,23 +71,5 @@ def ApplyShuffleVectorFMAOpsPatternsOp : Op<Transform_Dialect,
let assemblyFormat = "attr-dict";
}
-def ApplyFlattenVectorTransferOpsPatternsOp : Op<Transform_Dialect,
- "apply_patterns.x86vector.flatten_vector_transfer_ops",
- [DeclareOpInterfaceMethods<PatternDescriptorOpInterface>]> {
- let description = [{
- Collect patterns to rewrite contiguous row-major vector.transfer_read or
- vector.transfer_write operations to a 1D operation.
- }];
-
- let arguments = (ins
- DefaultValuedAttr<UI32Attr,
- "std::numeric_limits<unsigned>::max()">:$target_vector_bitwidth
- );
-
- let assemblyFormat = [{
- (`target_vector_bitwidth` `=` $target_vector_bitwidth^)? attr-dict
- }];
-}
-
#endif // X86VECTOR_TRANSFORM_OPS
diff --git a/mlir/include/mlir/Dialect/X86Vector/Transforms.h b/mlir/include/mlir/Dialect/X86Vector/Transforms.h
index f2a1d58f42c1f..aadca92708908 100644
--- a/mlir/include/mlir/Dialect/X86Vector/Transforms.h
+++ b/mlir/include/mlir/Dialect/X86Vector/Transforms.h
@@ -104,13 +104,6 @@ void populateSinkVectorProducerOpsPatterns(RewritePatternSet &patterns);
// grouped with respect to odd/even packed index.
void populateShuffleVectorFMAOpsPatterns(RewritePatternSet &patterns);
-// Rewrites contiguous row-major vector.transfer_read or vector.transfer_write
-// operations by inserting a memref.collapse_shape on the source,
-// transforming the operation to use a 1D source.
-void populateFlattenVectorTransferOpsPatterns(
- RewritePatternSet &patterns,
- unsigned targetVectorBitwidth = std::numeric_limits<unsigned>::max());
-
//===----------------------------------------------------------------------===//
/// Helpers extracted from:
/// - clang/lib/Headers/avxintrin.h
diff --git a/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp b/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
index 7faa222a9e574..985f1598b8656 100644
--- a/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
+++ b/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
@@ -227,6 +227,12 @@ void transform::ApplySinkVectorMemPatternsOp::populatePatterns(
vector::populateSinkVectorMemOpsPatterns(patterns);
}
+void mlir::transform::ApplyFlattenVectorTransferOpsPatternsOp::populatePatterns(
+ RewritePatternSet &patterns) {
+ vector::populateFlattenVectorTransferPatterns(patterns,
+ getTargetVectorBitwidth());
+}
+
//===----------------------------------------------------------------------===//
// Transform op registration
//===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
index 7601966a4652c..46af62ea36958 100644
--- a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
+++ b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
@@ -12,7 +12,6 @@
#include "mlir/Dialect/Transform/IR/TransformDialect.h"
#include "mlir/Dialect/Transform/Interfaces/TransformInterfaces.h"
#include "mlir/Dialect/Vector/IR/VectorOps.h"
-#include "mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h"
#include "mlir/Dialect/X86Vector/Transforms.h"
#include "mlir/Dialect/X86Vector/X86VectorDialect.h"
@@ -49,12 +48,6 @@ void mlir::transform::ApplyShuffleVectorFMAOpsPatternsOp::populatePatterns(
x86vector::populateShuffleVectorFMAOpsPatterns(patterns);
}
-void mlir::transform::ApplyFlattenVectorTransferOpsPatternsOp::populatePatterns(
- RewritePatternSet &patterns) {
- vector::populateFlattenVectorTransferPatterns(patterns,
- getTargetVectorBitwidth());
-}
-
//===----------------------------------------------------------------------===//
// Transform op registration
//===----------------------------------------------------------------------===//
diff --git a/mlir/test/Dialect/X86Vector/flatten-vector-transfer-ops.mlir b/mlir/test/Dialect/Vector/flatten-vector-transfer-ops.mlir
similarity index 95%
rename from mlir/test/Dialect/X86Vector/flatten-vector-transfer-ops.mlir
rename to mlir/test/Dialect/Vector/flatten-vector-transfer-ops.mlir
index 40c39c5f51c2a..01bf325cdb103 100644
--- a/mlir/test/Dialect/X86Vector/flatten-vector-transfer-ops.mlir
+++ b/mlir/test/Dialect/Vector/flatten-vector-transfer-ops.mlir
@@ -24,7 +24,7 @@ module attributes {transform.with_named_sequence} {
transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
%func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
transform.apply_patterns to %func {
- transform.apply_patterns.x86vector.flatten_vector_transfer_ops
+ transform.apply_patterns.vector.flatten_vector_transfer_ops
} : !transform.any_op
transform.yield
}
diff --git a/mlir/test/python/dialects/transform_vector_ext.py b/mlir/test/python/dialects/transform_vector_ext.py
index 0cd9333dc1218..868d7848eee8f 100644
--- a/mlir/test/python/dialects/transform_vector_ext.py
+++ b/mlir/test/python/dialects/transform_vector_ext.py
@@ -54,6 +54,8 @@ def non_configurable_patterns():
vector.ApplyLowerScanPatternsOp()
# CHECK: transform.apply_patterns.vector.lower_shape_cast
vector.ApplyLowerShapeCastPatternsOp()
+ # CHECK: transform.apply_patterns.vector.flatten_vector_transfer_ops
+ vector.ApplyFlattenVectorTransferOpsPatternsOp()
@run_apply_patterns
>From 639724a89feb78e0e4380cc0493ce3e34a7d6169 Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Wed, 4 Feb 2026 20:35:29 -0800
Subject: [PATCH 6/8] moved the unit-test into an existing test file
---
.../Vector/flatten-vector-transfer-ops.mlir | 31 ------------------
.../test/Dialect/Vector/transform-vector.mlir | 32 +++++++++++++++++++
2 files changed, 32 insertions(+), 31 deletions(-)
delete mode 100644 mlir/test/Dialect/Vector/flatten-vector-transfer-ops.mlir
diff --git a/mlir/test/Dialect/Vector/flatten-vector-transfer-ops.mlir b/mlir/test/Dialect/Vector/flatten-vector-transfer-ops.mlir
deleted file mode 100644
index 01bf325cdb103..0000000000000
--- a/mlir/test/Dialect/Vector/flatten-vector-transfer-ops.mlir
+++ /dev/null
@@ -1,31 +0,0 @@
-// RUN: mlir-opt %s -transform-interpreter -cse -split-input-file | FileCheck %s
-
-func.func @flatten_transfer_ops(%arg0: memref<16x16xf32>, %arg1: vector<8xf32>) -> vector<8xf32> {
- %c0 = arith.constant 0 : index
- %c8 = arith.constant 8 : index
- %b0 = ub.poison : f32
- %0 = vector.transfer_read %arg0[%c0, %c0], %b0 {in_bounds = [true, true]} : memref<16x16xf32>, vector<1x8xf32>
- %1 = vector.transfer_read %arg0[%c0, %c8], %b0 {in_bounds = [true, true]} : memref<16x16xf32>, vector<1x8xf32>
- %2 = vector.shape_cast %0 : vector<1x8xf32> to vector<8xf32>
- %3 = vector.shape_cast %1 : vector<1x8xf32> to vector<8xf32>
- %4 = vector.fma %2, %3, %arg1 : vector<8xf32>
- return %4 : vector<8xf32>
-}
-
-// CHECK-LABEL: @flatten_transfer_ops
-// CHECK-NOT: vector.transfer_read {{.*}}, vector<1x8xf32>
-// CHECK-NOT: vector.transfer_read {{.*}}, vector<1x8xf32>
-// CHECK: vector.transfer_read {{.*}}, vector<8xf32>
-// CHECK-NEXT: vector.transfer_read {{.*}}, vector<8xf32>
-// CHECK-NOT: vector.shape_cast
-// CHECK-NOT: vector.shape_cast
-
-module attributes {transform.with_named_sequence} {
- transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
- %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
- transform.apply_patterns to %func {
- transform.apply_patterns.vector.flatten_vector_transfer_ops
- } : !transform.any_op
- transform.yield
- }
-}
diff --git a/mlir/test/Dialect/Vector/transform-vector.mlir b/mlir/test/Dialect/Vector/transform-vector.mlir
index 524a4f429211b..9b22c383aa225 100644
--- a/mlir/test/Dialect/Vector/transform-vector.mlir
+++ b/mlir/test/Dialect/Vector/transform-vector.mlir
@@ -137,3 +137,35 @@ module attributes {transform.with_named_sequence} {
transform.yield
}
}
+
+// -----
+
+func.func @flatten_transfer_ops(%arg0: memref<16x16xf32>, %arg1: vector<8xf32>) -> vector<8xf32> {
+ %c0 = arith.constant 0 : index
+ %c8 = arith.constant 8 : index
+ %b0 = ub.poison : f32
+ %0 = vector.transfer_read %arg0[%c0, %c0], %b0 {in_bounds = [true, true]} : memref<16x16xf32>, vector<1x8xf32>
+ %1 = vector.transfer_read %arg0[%c0, %c8], %b0 {in_bounds = [true, true]} : memref<16x16xf32>, vector<1x8xf32>
+ %2 = vector.shape_cast %0 : vector<1x8xf32> to vector<8xf32>
+ %3 = vector.shape_cast %1 : vector<1x8xf32> to vector<8xf32>
+ %4 = vector.fma %2, %3, %arg1 : vector<8xf32>
+ return %4 : vector<8xf32>
+}
+
+// CHECK-LABEL: @flatten_transfer_ops
+// CHECK-NOT: vector.transfer_read {{.*}}, vector<1x8xf32>
+// CHECK-NOT: vector.transfer_read {{.*}}, vector<1x8xf32>
+// CHECK: vector.transfer_read {{.*}}, vector<8xf32>
+// CHECK-NEXT: vector.transfer_read {{.*}}, vector<8xf32>
+// CHECK-NOT: vector.shape_cast
+// CHECK-NOT: vector.shape_cast
+
+module attributes {transform.with_named_sequence} {
+ transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
+ %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
+ transform.apply_patterns to %func {
+ transform.apply_patterns.vector.flatten_vector_transfer_ops
+ } : !transform.any_op
+ transform.yield
+ }
+}
>From e642f2434698c660ec5b0f0d6bf480fd4e29f85f Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Sun, 8 Feb 2026 23:37:11 -0800
Subject: [PATCH 7/8] minor formatting changes
---
.../Dialect/X86Vector/TransformOps/X86VectorTransformOps.td | 1 +
mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp | 2 +-
.../Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp | 1 -
mlir/test/python/dialects/transform_vector_ext.py | 5 +++--
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td b/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
index 1fb663ec27325..891829fca017f 100644
--- a/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
+++ b/mlir/include/mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td
@@ -71,5 +71,6 @@ def ApplyShuffleVectorFMAOpsPatternsOp : Op<Transform_Dialect,
let assemblyFormat = "attr-dict";
}
+
#endif // X86VECTOR_TRANSFORM_OPS
diff --git a/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp b/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
index 985f1598b8656..ab85b92920f32 100644
--- a/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
+++ b/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
@@ -227,7 +227,7 @@ void transform::ApplySinkVectorMemPatternsOp::populatePatterns(
vector::populateSinkVectorMemOpsPatterns(patterns);
}
-void mlir::transform::ApplyFlattenVectorTransferOpsPatternsOp::populatePatterns(
+void transform::ApplyFlattenVectorTransferOpsPatternsOp::populatePatterns(
RewritePatternSet &patterns) {
vector::populateFlattenVectorTransferPatterns(patterns,
getTargetVectorBitwidth());
diff --git a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
index 46af62ea36958..c6be69305da50 100644
--- a/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
+++ b/mlir/lib/Dialect/X86Vector/TransformOps/X86VectorTransformOps.cpp
@@ -21,7 +21,6 @@
using namespace mlir;
using namespace mlir::x86vector;
using namespace mlir::transform;
-using namespace mlir::vector;
void mlir::transform::ApplyVectorContractToFMAPatternsOp::populatePatterns(
RewritePatternSet &patterns) {
diff --git a/mlir/test/python/dialects/transform_vector_ext.py b/mlir/test/python/dialects/transform_vector_ext.py
index 868d7848eee8f..bc8aa3de31ec7 100644
--- a/mlir/test/python/dialects/transform_vector_ext.py
+++ b/mlir/test/python/dialects/transform_vector_ext.py
@@ -54,8 +54,6 @@ def non_configurable_patterns():
vector.ApplyLowerScanPatternsOp()
# CHECK: transform.apply_patterns.vector.lower_shape_cast
vector.ApplyLowerShapeCastPatternsOp()
- # CHECK: transform.apply_patterns.vector.flatten_vector_transfer_ops
- vector.ApplyFlattenVectorTransferOpsPatternsOp()
@run_apply_patterns
@@ -69,6 +67,9 @@ def configurable_patterns():
# CHECK-SAME: max_transfer_rank = 3
# CHECK-SAME: full_unroll = true
vector.ApplyTransferToScfPatternsOp(max_transfer_rank=3, full_unroll=True)
+ # CHECK-SAME: target_vector_bitwidth = 1
+ # CHECK: transform.apply_patterns.vector.flatten_vector_transfer_ops
+ vector.ApplyFlattenVectorTransferOpsPatternsOp(target_vector_bitwidth=1)
@run_apply_patterns
>From 28ef063838f4c58181099aff4652521082a4c5b5 Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Mon, 9 Feb 2026 00:02:58 -0800
Subject: [PATCH 8/8] moving the width size option
---
mlir/test/python/dialects/transform_vector_ext.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mlir/test/python/dialects/transform_vector_ext.py b/mlir/test/python/dialects/transform_vector_ext.py
index bc8aa3de31ec7..2bcb2a2ac5812 100644
--- a/mlir/test/python/dialects/transform_vector_ext.py
+++ b/mlir/test/python/dialects/transform_vector_ext.py
@@ -67,8 +67,8 @@ def configurable_patterns():
# CHECK-SAME: max_transfer_rank = 3
# CHECK-SAME: full_unroll = true
vector.ApplyTransferToScfPatternsOp(max_transfer_rank=3, full_unroll=True)
- # CHECK-SAME: target_vector_bitwidth = 1
# CHECK: transform.apply_patterns.vector.flatten_vector_transfer_ops
+ # CHECK-SAME: target_vector_bitwidth = 1
vector.ApplyFlattenVectorTransferOpsPatternsOp(target_vector_bitwidth=1)
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