[Mlir-commits] [mlir] [mlir][Linalg] Promote lhs/rhs when vectorizing conv1D as outerproduct (PR #179883)

[Han-Chung Wang]

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@@ -3848,8 +3848,12 @@ struct Conv1DGenerator
 
     const int64_t srcWidth = srcElementType.getIntOrFloatBitWidth();
     const int64_t dstWidth = dstElementType.getIntOrFloatBitWidth();
-    const Type dstType =
-        cast<ShapedType>(val.getType()).cloneWith(std::nullopt, dstElementType);
+    // Handle both shaped as well as scalar types.
+    Type dstType;
+    if (auto shapedType = dyn_cast<ShapedType>(val.getType()))
+      dstType = shapedType.cloneWith(std::nullopt, dstElementType);
+    else
+      dstType = dstElementType;
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hanhanW wrote:

I see, thanks

https://github.com/llvm/llvm-project/pull/179883