[Mlir-commits] [mlir] [MLIR][NVVM] Add nvvm.addf and nvvm.subf Ops (PR #179162)

[Srinivasa Ravi]

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@@ -0,0 +1,400 @@
+// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
+
+// f16 + f16 -> f32
+llvm.func @fadd_f16_f16_rn(%a : f16, %b : f16) -> f32 {
+  // CHECK-LABEL: define float @fadd_f16_f16_rn(half %0, half %1) {
+  // CHECK-NEXT: %3 = fpext half %0 to float
+  // CHECK-NEXT: %4 = fpext half %1 to float
+  // CHECK-NEXT: %5 = call float @llvm.nvvm.add.rn.f(float %3, float %4)
+  // CHECK-NEXT: ret float %5
+  // CHECK-NEXT: }
+  %f1 = nvvm.fadd %a, %b {rnd = #nvvm.fp_rnd_mode<rn>} : f16, f16 -> f32
+  llvm.return %f1 : f32
+}
+
+llvm.func @fadd_f16_f16_rn_sat(%a : f16, %b : f16) -> f32 {
+  // CHECK-LABEL: define float @fadd_f16_f16_rn_sat(half %0, half %1) {
+  // CHECK-NEXT: %3 = fpext half %0 to float
+  // CHECK-NEXT: %4 = fpext half %1 to float
+  // CHECK-NEXT: %5 = call float @llvm.nvvm.add.rn.sat.f(float %3, float %4)
+  // CHECK-NEXT: ret float %5
+  // CHECK-NEXT: }
+  %f1 = nvvm.fadd %a, %b {rnd = #nvvm.fp_rnd_mode<rn>, sat = #nvvm.sat_mode<sat>} : f16, f16 -> f32
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Wolfram70 wrote:

I couldn't find a way to do it here since we support mixed operand types. I also think it's better if we these are explicitly mentioned in our case to reduce any confusion when it comes to the conversions for mixed precision cases.

https://github.com/llvm/llvm-project/pull/179162