[Mlir-commits] [clang] [llvm] [mlir] [AMDGPU] Fix missing cache bypass scope on seq_cst buffer fat pointer atomics (PR #213585)

[Arseniy Obolenskiy]

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@@ -1556,6 +1556,9 @@ class SplitPtrStructs : public InstVisitor<SplitPtrStructs, PtrParts> {
   void setAlign(CallInst *Intr, Align A, unsigned RsrcArgIdx);
   void insertPreMemOpFence(AtomicOrdering Order, SyncScope::ID SSID);
   void insertPostMemOpFence(AtomicOrdering Order, SyncScope::ID SSID);
+  // Empty when the access is not atomic.
+  SmallVector<OperandBundleDef, 1> getAtomicityBundle(AtomicOrdering Order,
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aobolensk wrote:

Instead of speculating I decided to just perform this change. Actually it is not that difficult. As for fundamental parts that were affected, it involved `Instruction::isAtomic` and `Instruction::hasAtomicLoad/Store` and a method was added in `CallBase` class

https://github.com/llvm/llvm-project/pull/213585