[Mlir-commits] [mlir] [mlir][tosa] Add support for mxfp in TRANSPOSE_CONV2D (PR #218953)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Thu Aug 27 04:33:36 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir
Author: Jeremy Johnson (jjohnson-arm)
<details>
<summary>Changes</summary>
TOSA Speicifcation changes:
* https://github.com/arm/tosa-specification/pull/65
* https://github.com/arm/tosa-specification/pull/77
---
Patch is 77.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218953.diff
6 Files Affected:
- (modified) mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc (+1343-2)
- (modified) mlir/test/Dialect/Tosa/invalid_extension.mlir (+9)
- (modified) mlir/test/Dialect/Tosa/ops.mlir (+9)
- (modified) mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir (+10)
- (modified) mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir (+18)
- (modified) mlir/test/Dialect/Tosa/verifier.mlir (+20)
``````````diff
diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
index 3ee7833ee4e1e..de54b5b6be16e 100644
--- a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
@@ -99,7 +99,13 @@ profileComplianceMap = {
{{fp16T, fp16T, fp16T, fp16T, fp16T, fp32T, fp16T},
SpecificationVersion::V_1_0},
{{fp32T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
- SpecificationVersion::V_1_0}}}}},
+ SpecificationVersion::V_1_0},
+ {{fp16T, fp16T, fp32T, fp16T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp32T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}}}}},
{"tosa.clamp",
{{{Profile::pro_int}, {{{i8T, i8T}, SpecificationVersion::V_1_0}}},
{{Profile::pro_fp},
@@ -2697,15 +2703,1350 @@ extensionComplianceMap = {
{{{fp8e4m3T, fp8e4m3T, fp16T, fp8e4m3T, fp8e4m3T, fp16T, fp16T},
SpecificationVersion::V_1_0},
{{fp8e4m3T, fp8e4m3T, fp32T, fp8e4m3T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e4m3T, fp16T, fp8e4m3T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp32T, fp16T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T, fp32T},
SpecificationVersion::V_1_1_DRAFT}}},
{{Extension::fp8e5m2},
{{{fp8e5m2T, fp8e5m2T, fp16T, fp8e5m2T, fp8e5m2T, fp16T, fp16T},
SpecificationVersion::V_1_0},
{{fp8e5m2T, fp8e5m2T, fp32T, fp8e5m2T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e5m2T, fp16T, fp8e5m2T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp32T, fp16T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T, fp32T},
SpecificationVersion::V_1_1_DRAFT}}},
{{Extension::bf16},
{{{bf16T, bf16T, bf16T, bf16T, bf16T, fp32T, bf16T},
- SpecificationVersion::V_1_0}}}}},
+ SpecificationVersion::V_1_0},
+ {{bf16T, bf16T, bf16T, bf16T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bf16T, fp32T, fp16T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp16T, fp32T, bf16T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bf16T, fp32T, bf16T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp32T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}}},
+ {{Extension::fp8e4m3, Extension::fp8e5m2},
+ {{{fp8e4m3T, fp8e5m2T, fp16T, fp8e4m3T, fp8e5m2T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e5m2T, fp16T, fp8e4m3T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp16T, fp8e5m2T, fp8e4m3T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp16T, fp8e5m2T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e5m2T, fp32T, fp8e4m3T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp32T, fp8e5m2T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp6e2m3},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp4e2m1},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_int8},
+ {{{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp6e2m3},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp4e2m1},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_int8},
+ {{{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp16T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/218953
More information about the Mlir-commits
mailing list