[Mlir-commits] [mlir] [mlir][tosa] Add support for mxfp in TRANSPOSE_CONV2D (PR #218953)
Jeremy Johnson
llvmlistbot at llvm.org
Wed Aug 26 08:18:13 PDT 2026
https://github.com/jjohnson-arm created https://github.com/llvm/llvm-project/pull/218953
TOSA Speicifcation changes:
* https://github.com/arm/tosa-specification/pull/65
* https://github.com/arm/tosa-specification/pull/77
>From 69fb9fca97ea05dd63a1826d83887443edaeee06 Mon Sep 17 00:00:00 2001
From: Jeremy Johnson <jeremy.johnson at arm.com>
Date: Mon, 24 Aug 2026 13:42:21 +0100
Subject: [PATCH] [mlir][tosa] Add support for mxfp in TRANSPOSE_CONV2D
TOSA Speicifcation changes:
* https://github.com/arm/tosa-specification/pull/65
* https://github.com/arm/tosa-specification/pull/77
Signed-off-by: Jeremy Johnson <jeremy.johnson at arm.com>
Change-Id: If0b2522800d857bee2f5b1dcc2c75213b438ae62
---
.../Dialect/Tosa/IR/TosaComplianceData.h.inc | 1345 ++++++++++++++++-
mlir/test/Dialect/Tosa/invalid_extension.mlir | 9 +
mlir/test/Dialect/Tosa/ops.mlir | 9 +
.../tosa-validation-version-1p0-invalid.mlir | 10 +
.../tosa-validation-version-1p1-valid.mlir | 18 +
mlir/test/Dialect/Tosa/verifier.mlir | 20 +
6 files changed, 1409 insertions(+), 2 deletions(-)
diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
index 010cca48b336b..d3ae2b8f0336c 100644
--- a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
@@ -99,7 +99,13 @@ profileComplianceMap = {
{{fp16T, fp16T, fp16T, fp16T, fp16T, fp32T, fp16T},
SpecificationVersion::V_1_0},
{{fp32T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
- SpecificationVersion::V_1_0}}}}},
+ SpecificationVersion::V_1_0},
+ {{fp16T, fp16T, fp32T, fp16T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp32T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}}}}},
{"tosa.clamp",
{{{Profile::pro_int}, {{{i8T, i8T}, SpecificationVersion::V_1_0}}},
{{Profile::pro_fp},
@@ -2697,15 +2703,1350 @@ extensionComplianceMap = {
{{{fp8e4m3T, fp8e4m3T, fp16T, fp8e4m3T, fp8e4m3T, fp16T, fp16T},
SpecificationVersion::V_1_0},
{{fp8e4m3T, fp8e4m3T, fp32T, fp8e4m3T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e4m3T, fp16T, fp8e4m3T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp32T, fp16T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T, fp32T},
SpecificationVersion::V_1_1_DRAFT}}},
{{Extension::fp8e5m2},
{{{fp8e5m2T, fp8e5m2T, fp16T, fp8e5m2T, fp8e5m2T, fp16T, fp16T},
SpecificationVersion::V_1_0},
{{fp8e5m2T, fp8e5m2T, fp32T, fp8e5m2T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e5m2T, fp16T, fp8e5m2T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp32T, fp16T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T, fp32T},
SpecificationVersion::V_1_1_DRAFT}}},
{{Extension::bf16},
{{{bf16T, bf16T, bf16T, bf16T, bf16T, fp32T, bf16T},
- SpecificationVersion::V_1_0}}}}},
+ SpecificationVersion::V_1_0},
+ {{bf16T, bf16T, bf16T, bf16T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bf16T, fp32T, fp16T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp16T, fp32T, bf16T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bf16T, fp32T, bf16T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp32T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}}},
+ {{Extension::fp8e4m3, Extension::fp8e5m2},
+ {{{fp8e4m3T, fp8e5m2T, fp16T, fp8e4m3T, fp8e5m2T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e5m2T, fp16T, fp8e4m3T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp16T, fp8e5m2T, fp8e4m3T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp16T, fp8e5m2T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e5m2T, fp32T, fp8e4m3T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp32T, fp8e5m2T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp6e2m3},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp4e2m1},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_int8},
+ {{{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp6e2m3},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp4e2m1},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_int8},
+ {{{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp16T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e2m3},
+ {{{fp16T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp4e2m1},
+ {{{fp16T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_int8},
+ {{{fp16T, bs32_fp8ue8m0_mxint8T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_mxint8T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_mxint8T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_mxint8T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_mxint8T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e4m3, Extension::mx_fp8e5m2},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e3m2, Extension::mx_fp8e4m3},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e2m3, Extension::mx_fp8e4m3},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp4e2m1, Extension::mx_fp8e4m3},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e4m3, Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e3m2, Extension::mx_fp8e5m2},
+ {{{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e2m3, Extension::mx_fp8e5m2},
+ {{{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp4e2m1, Extension::mx_fp8e5m2},
+ {{{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e5m2, Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e2m3, Extension::mx_fp6e3m2},
+ {{{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp4e2m1, Extension::mx_fp6e3m2},
+ {{{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e3m2, Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_mxint8T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp4e2m1, Extension::mx_fp6e2m3},
+ {{{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e2m3, Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_mxint8T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp4e2m1, Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_mxint8T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_mxint8T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e4m3},
+ {{{fp8e4m3T, fp8e4m3T, bf16T, fp8e4m3T, fp8e4m3T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e4m3T, bf16T, fp8e4m3T, fp8e4m3T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bf16T, bf16T, fp8e4m3T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bf16T, bf16T, fp8e4m3T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp8e4m3T, bf16T, bf16T, fp8e4m3T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp8e4m3T, bf16T, bf16T, fp8e4m3T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bf16T, fp32T, fp8e4m3T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp8e4m3T, fp32T, bf16T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e4m3, Extension::fp8e5m2},
+ {{{fp8e4m3T, fp8e5m2T, bf16T, fp8e4m3T, fp8e5m2T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e5m2T, bf16T, fp8e4m3T, fp8e5m2T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, bf16T, fp8e5m2T, fp8e4m3T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, bf16T, fp8e5m2T, fp8e4m3T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e4m3, Extension::mx_common,
+ Extension::mx_fp8e4m3},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp8e4m3T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp8e4m3T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e4m3, Extension::mx_common,
+ Extension::mx_fp8e5m2},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp8e4m3T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp8e4m3T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e4m3, Extension::mx_common,
+ Extension::mx_fp6e3m2},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp8e4m3T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp8e4m3T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e4m3, Extension::mx_common,
+ Extension::mx_fp6e2m3},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp8e4m3T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp8e4m3T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e4m3, Extension::mx_common,
+ Extension::mx_fp4e2m1},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp8e4m3T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp8e4m3T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e4m3, Extension::mx_common,
+ Extension::mx_int8},
+ {{{fp8e4m3T, bs32_fp8ue8m0_mxint8T, bf16T, fp8e4m3T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_mxint8T, bf16T, fp8e4m3T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, bf16T, fp32T, fp8e4m3T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e5m2},
+ {{{fp8e5m2T, fp8e5m2T, bf16T, fp8e5m2T, fp8e5m2T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e5m2T, bf16T, fp8e5m2T, fp8e5m2T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bf16T, bf16T, fp8e5m2T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bf16T, bf16T, fp8e5m2T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp8e5m2T, bf16T, bf16T, fp8e5m2T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp8e5m2T, bf16T, bf16T, fp8e5m2T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bf16T, fp32T, fp8e5m2T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp8e5m2T, fp32T, bf16T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e5m2, Extension::mx_common,
+ Extension::mx_fp8e4m3},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp8e5m2T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp8e5m2T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e5m2, Extension::mx_common,
+ Extension::mx_fp8e5m2},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp8e5m2T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp8e5m2T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e5m2, Extension::mx_common,
+ Extension::mx_fp6e3m2},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp8e5m2T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp8e5m2T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e5m2, Extension::mx_common,
+ Extension::mx_fp6e2m3},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp8e5m2T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp8e5m2T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e5m2, Extension::mx_common,
+ Extension::mx_fp4e2m1},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp8e5m2T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp8e5m2T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::fp8e5m2, Extension::mx_common,
+ Extension::mx_int8},
+ {{{fp8e5m2T, bs32_fp8ue8m0_mxint8T, bf16T, fp8e5m2T, fp32T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_mxint8T, bf16T, fp8e5m2T, fp32T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, bf16T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, bf16T, fp32T, fp8e5m2T, fp32T,
+ bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{bf16T, bs32_fp8ue8m0_fp8e4m3T, bf16T, bf16T, fp32T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp8e4m3T, bf16T, bf16T, fp32T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bf16T, bf16T, fp32T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bf16T, bf16T, fp32T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp8e4m3T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{bf16T, bs32_fp8ue8m0_fp8e5m2T, bf16T, bf16T, fp32T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp8e5m2T, bf16T, bf16T, fp32T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bf16T, bf16T, fp32T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bf16T, bf16T, fp32T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp8e5m2T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{bf16T, bs32_fp8ue8m0_fp6e3m2T, bf16T, bf16T, fp32T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp6e3m2T, bf16T, bf16T, fp32T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bf16T, bf16T, fp32T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bf16T, bf16T, fp32T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp6e3m2T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e2m3},
+ {{{bf16T, bs32_fp8ue8m0_fp6e2m3T, bf16T, bf16T, fp32T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp6e2m3T, bf16T, bf16T, fp32T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bf16T, bf16T, fp32T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bf16T, bf16T, fp32T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp6e2m3T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp4e2m1},
+ {{{bf16T, bs32_fp8ue8m0_fp4e2m1T, bf16T, bf16T, fp32T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp4e2m1T, bf16T, bf16T, fp32T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bf16T, bf16T, fp32T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bf16T, bf16T, fp32T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_fp4e2m1T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_int8},
+ {{{bf16T, bs32_fp8ue8m0_mxint8T, bf16T, bf16T, fp32T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_mxint8T, bf16T, bf16T, fp32T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bf16T, bf16T, fp32T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bf16T, bf16T, fp32T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bs32_fp8ue8m0_mxint8T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp8e4m3,
+ Extension::mx_fp8e5m2},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e3m2,
+ Extension::mx_fp8e4m3},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e2m3,
+ Extension::mx_fp8e4m3},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp4e2m1,
+ Extension::mx_fp8e4m3},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp8e4m3,
+ Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e4m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e3m2,
+ Extension::mx_fp8e5m2},
+ {{{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e2m3,
+ Extension::mx_fp8e5m2},
+ {{{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp4e2m1,
+ Extension::mx_fp8e5m2},
+ {{{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp8e5m2,
+ Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp8e5m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e2m3,
+ Extension::mx_fp6e3m2},
+ {{{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp4e2m1,
+ Extension::mx_fp6e3m2},
+ {{{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e3m2,
+ Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e3m2T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp4e2m1,
+ Extension::mx_fp6e2m3},
+ {{{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp6e2m3,
+ Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp6e2m3T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::bf16, Extension::mx_common, Extension::mx_fp4e2m1,
+ Extension::mx_int8},
+ {{{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, bs32_fp8ue8m0_mxint8T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, bs32_fp8ue8m0_fp4e2m1T, bf16T, fp32T, fp32T,
+ fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf}}},
{"tosa.clamp",
{{{Extension::int16}, {{{i16T, i16T}, SpecificationVersion::V_1_0}}},
{{Extension::bf16}, {{{bf16T, bf16T}, SpecificationVersion::V_1_0}}}}},
diff --git a/mlir/test/Dialect/Tosa/invalid_extension.mlir b/mlir/test/Dialect/Tosa/invalid_extension.mlir
index e7d76459897ea..1d03a9d5e0aab 100644
--- a/mlir/test/Dialect/Tosa/invalid_extension.mlir
+++ b/mlir/test/Dialect/Tosa/invalid_extension.mlir
@@ -34,6 +34,15 @@ func.func @test_conv2d_mxfp(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAP
return %0 : tensor<1x4x4x8xbf16>
}
+// -----
+func.func @test_transpose_conv2d_mxfp(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg1: tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg2: tensor<8xbf16>) -> tensor<1x4x4x8xbf16> {
+ %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.transpose_conv2d' op illegal: requires all of [bf16, mx_common, mx_fp4e2m1] profiles/extensions to be specified in the target environment}}
+ %0 = tosa.transpose_conv2d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = bf16, out_pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true} : (tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8xbf16>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xbf16>
+ return %0 : tensor<1x4x4x8xbf16>
+}
+
// -----
func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xi16>, %arg1: tensor<34x1x1x1x17xi8>, %arg2: tensor<34xi48>, %arg3: tensor<1xi16>, %arg4: tensor<1xi8>) -> tensor<1x4x8x21x34xi48> {
// expected-error at +1 {{'tosa.conv3d' op illegal: requires any of [int16] profiles/extensions to be specified in the target environment}}
diff --git a/mlir/test/Dialect/Tosa/ops.mlir b/mlir/test/Dialect/Tosa/ops.mlir
index a2a7ca043bda2..9f4fab74054d4 100644
--- a/mlir/test/Dialect/Tosa/ops.mlir
+++ b/mlir/test/Dialect/Tosa/ops.mlir
@@ -445,6 +445,15 @@ func.func @test_transpose_conv2d(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<16x
return %0 : tensor<1x32x32x16xf32>
}
+// -----
+// CHECK-LABEL: transpose_conv2d_mxfp
+func.func @test_transpose_conv2d_mxfp(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg1: tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg2: tensor<8xf16>) -> tensor<1x4x4x8xf16> {
+ %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %0 = tosa.transpose_conv2d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = bf16, out_pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true} : (tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8xf16>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf16>
+ return %0 : tensor<1x4x4x8xf16>
+}
+
// -----
// CHECK-LABEL: transpose_conv2d_unranked_input
func.func @test_transpose_conv2d_unranked_input(%arg0: tensor<*xf32>, %arg1: tensor<16x1x1x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x16xf32> {
diff --git a/mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir b/mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
index 1a8aedf8d3c62..00b7c616470c4 100644
--- a/mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
+++ b/mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
@@ -82,6 +82,16 @@ func.func @test_transpose_conv2d_fp8_acc32(%arg0: tensor<1x32x32x8xf8E5M2>, %arg
// -----
+func.func @test_transpose_conv2d_mxfp(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg1: tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg2: tensor<8xbf16>) -> tensor<1x4x4x8xbf16> {
+ %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.transpose_conv2d' op illegal: requires specification version compatible with 1.1.draft (got 1.0) and requires all of [bf16, mx_common, mx_fp4e2m1] profiles/extensions to be specified in the target environment}}
+ %0 = tosa.transpose_conv2d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = bf16, out_pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true} : (tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8xbf16>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xbf16>
+ return %0 : tensor<1x4x4x8xbf16>
+}
+
+// -----
+
func.func @test_gather_bool_i64(%arg0: tensor<13x21x3xi1>, %arg1: tensor<13x26xi64>) -> tensor<13x26x3xi1> {
// expected-error at +1 {{'tosa.gather' op illegal: requires specification version compatible with 1.1.draft (got 1.0) and requires any of [int64] profiles/extensions to be specified in the target environment}}
%0 = tosa.gather %arg0, %arg1 : (tensor<13x21x3xi1>, tensor<13x26xi64>) -> tensor<13x26x3xi1>
diff --git a/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir b/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
index 0de49d17de282..b9b26931be65a 100644
--- a/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+++ b/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
@@ -120,6 +120,24 @@ func.func @test_transpose_conv2d_fp8_acc32(%arg0: tensor<1x32x32x8xf8E5M2>, %arg
// -----
+// CHECK-LABEL: test_transpose_conv2d_mxfp
+func.func @test_transpose_conv2d_mxfp(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg1: tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg2: tensor<8xf16>) -> tensor<1x4x4x8xf16> {
+ %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %0 = tosa.transpose_conv2d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = f16, out_pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true} : (tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8xf16>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf16>
+ return %0 : tensor<1x4x4x8xf16>
+}
+
+// CHECK-LABEL: test_transpose_conv2d_mxfp_acc32
+func.func @test_transpose_conv2d_mxfp_acc32(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg1: tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg2: tensor<8xf16>) -> tensor<1x4x4x8xf16> {
+ %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %0 = tosa.transpose_conv2d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = f32, out_pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true} : (tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8xf16>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf16>
+ return %0 : tensor<1x4x4x8xf16>
+}
+
+// -----
+
// CHECK-LABEL: test_matmul_t_block_scaled_fp6e2m3
func.func @test_matmul_t_block_scaled_fp6e2m3(%arg0: tensor<4x8x32xf6E2M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf6E2M3FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> {
%0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = BLOCK_SIZE_32} : (tensor<4x8x32xf6E2M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf6E2M3FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32>
diff --git a/mlir/test/Dialect/Tosa/verifier.mlir b/mlir/test/Dialect/Tosa/verifier.mlir
index b64c7e6cffa54..1bb5671c4fba2 100644
--- a/mlir/test/Dialect/Tosa/verifier.mlir
+++ b/mlir/test/Dialect/Tosa/verifier.mlir
@@ -427,6 +427,26 @@ func.func @test_conv3d_wholly_divisible_output_width(%arg0: tensor<1x4x8x21x19xf
// -----
+func.func @test_transpose_conv2d_mxfp_invalid_weight_zp(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg1: tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg2: tensor<8xf16>) -> tensor<1x4x4x8xf16> {
+ %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf16>}> : () -> tensor<1xf16>
+ // expected-error at +1 {{'tosa.transpose_conv2d' op expect block scaled weight to have fp32 zero point}}
+ %0 = tosa.transpose_conv2d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = bf16, out_pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true} : (tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8xf16>, tensor<1xf32>, tensor<1xf16>) -> tensor<1x4x4x8xf16>
+ return %0 : tensor<1x4x4x8xf16>
+}
+
+// -----
+
+func.func @test_transpose_conv2d_mxfp_invalid_input_zp(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg1: tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg2: tensor<8xf16>) -> tensor<1x4x4x8xf16> {
+ %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf16>}> : () -> tensor<1xf16>
+ %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.transpose_conv2d' op expect block scaled input to have fp32 zero point}}
+ %0 = tosa.transpose_conv2d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = bf16, out_pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true} : (tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, tensor<8xf16>, tensor<1xf16>, tensor<1xf32>) -> tensor<1x4x4x8xf16>
+ return %0 : tensor<1x4x4x8xf16>
+}
+
+// -----
+
func.func @test_concat_element_type_mismatch(%arg0 : tensor<1x2xf32>, %arg1 : tensor<2x2xf32>) -> tensor<?x?xi8> {
// expected-error at +1 {{'tosa.concat' op expect input and output to have same element type, got 'f32' and 'i8'}}
%0 = tosa.concat %arg0, %arg1 {axis = 0 : i32} : (tensor<1x2xf32>, tensor<2x2xf32>) -> tensor<?x?xi8>
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