[Mlir-commits] [mlir] [MLIR][RFC] MIR dialects: model pre-RA AArch64 MachineIR generated from LLVM TableGen (PR #218476)
Maksim Levental
llvmlistbot at llvm.org
Mon Aug 24 12:02:00 PDT 2026
https://github.com/makslevental updated https://github.com/llvm/llvm-project/pull/218476
>From b45db44db6a6bb1c70e0969428ea84492552d5b5 Mon Sep 17 00:00:00 2001
From: makslevental <maksim.levental at gmail.com>
Date: Mon, 24 Aug 2026 10:33:34 -0700
Subject: [PATCH 1/7] [MLIR] Add MIR dialect skeleton with LLT type/attr system
Introduces the `mir` dialect: a faithful, SSA-form MLIR representation of
pre-register-allocation LLVM MachineIR (the GlobalISel generic-opcode layer).
This first step establishes the shared foundation reused by future target
dialects (e.g. aarch64_mir):
- LLT-modeled types: !mir.scalar<N>, !mir.pointer<AS, N>, !mir.vector<N x elt>.
- Attributes: #mir.regbank, #mir.physreg, #mir.mmo (MachineMemOperand).
- A representative hand-written subset of generic (G_*) opcodes (g_add,
g_constant, g_load, g_store, copy), the mir.func container, and the
ABI-boundary physical-register copies (copy_from_phys / copy_to_phys) that
keep physical registers as attributes rather than SSA values.
The full ~279 generic opcodes will be generated from GenericOpcodes.td by a
subsequent -gen-mir-generic-ops mlir-tblgen backend.
Verified by a parse/print round-trip lit test (Dialect/MIR/roundtrip.mlir).
---
mlir/include/mlir/Dialect/CMakeLists.txt | 1 +
mlir/include/mlir/Dialect/MIR/CMakeLists.txt | 1 +
.../mlir/Dialect/MIR/IR/CMakeLists.txt | 5 +
mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.h | 17 +++
mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.td | 69 ++++++++++++
mlir/include/mlir/Dialect/MIR/IR/MIRBase.td | 71 ++++++++++++
mlir/include/mlir/Dialect/MIR/IR/MIRDialect.h | 16 +++
mlir/include/mlir/Dialect/MIR/IR/MIROps.h | 24 ++++
mlir/include/mlir/Dialect/MIR/IR/MIROps.td | 105 ++++++++++++++++++
mlir/include/mlir/Dialect/MIR/IR/MIRTypes.h | 17 +++
mlir/include/mlir/Dialect/MIR/IR/MIRTypes.td | 69 ++++++++++++
mlir/lib/Dialect/CMakeLists.txt | 1 +
mlir/lib/Dialect/MIR/CMakeLists.txt | 1 +
mlir/lib/Dialect/MIR/IR/CMakeLists.txt | 14 +++
mlir/lib/Dialect/MIR/IR/MIRDialect.cpp | 57 ++++++++++
mlir/lib/RegisterAllDialects.cpp | 2 +
mlir/test/Dialect/MIR/roundtrip.mlir | 32 ++++++
17 files changed, 502 insertions(+)
create mode 100644 mlir/include/mlir/Dialect/MIR/CMakeLists.txt
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/CMakeLists.txt
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.h
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.td
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIRBase.td
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIRDialect.h
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIROps.h
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIROps.td
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIRTypes.h
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIRTypes.td
create mode 100644 mlir/lib/Dialect/MIR/CMakeLists.txt
create mode 100644 mlir/lib/Dialect/MIR/IR/CMakeLists.txt
create mode 100644 mlir/lib/Dialect/MIR/IR/MIRDialect.cpp
create mode 100644 mlir/test/Dialect/MIR/roundtrip.mlir
diff --git a/mlir/include/mlir/Dialect/CMakeLists.txt b/mlir/include/mlir/Dialect/CMakeLists.txt
index d7ea0cc3df267..dd1926c4cd3a5 100644
--- a/mlir/include/mlir/Dialect/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/CMakeLists.txt
@@ -18,6 +18,7 @@ add_subdirectory(Linalg)
add_subdirectory(LLVMIR)
add_subdirectory(Math)
add_subdirectory(MemRef)
+add_subdirectory(MIR)
add_subdirectory(Shard)
add_subdirectory(MLProgram)
add_subdirectory(MPI)
diff --git a/mlir/include/mlir/Dialect/MIR/CMakeLists.txt b/mlir/include/mlir/Dialect/MIR/CMakeLists.txt
new file mode 100644
index 0000000000000..f33061b2d87cf
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory(IR)
diff --git a/mlir/include/mlir/Dialect/MIR/IR/CMakeLists.txt b/mlir/include/mlir/Dialect/MIR/IR/CMakeLists.txt
new file mode 100644
index 0000000000000..9cb08b93b698e
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/CMakeLists.txt
@@ -0,0 +1,5 @@
+set(LLVM_TARGET_DEFINITIONS MIROps.td)
+mlir_tablegen(MIROpsAttributes.h.inc -gen-attrdef-decls -attrdefs-dialect=mir)
+mlir_tablegen(MIROpsAttributes.cpp.inc -gen-attrdef-defs -attrdefs-dialect=mir)
+add_mlir_dialect(MIROps mir)
+add_mlir_doc(MIROps MIROps Dialects/ -gen-dialect-doc)
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.h b/mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.h
new file mode 100644
index 0000000000000..2c46e5cabda4a
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.h
@@ -0,0 +1,17 @@
+//===- MIRAttrs.h - MIR dialect attributes --------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MIR_IR_MIRATTRS_H
+#define MLIR_DIALECT_MIR_IR_MIRATTRS_H
+
+#include "mlir/IR/Attributes.h"
+
+#define GET_ATTRDEF_CLASSES
+#include "mlir/Dialect/MIR/IR/MIROpsAttributes.h.inc"
+
+#endif // MLIR_DIALECT_MIR_IR_MIRATTRS_H
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.td b/mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.td
new file mode 100644
index 0000000000000..0ba5c53a663f5
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIRAttrs.td
@@ -0,0 +1,69 @@
+//===- MIRAttrs.td - MIR dialect attributes ----------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Attributes carrying MachineIR metadata that is not naturally an SSA operand:
+// register banks, physical registers, memory operands, and MI flags.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MIR_IR_MIRATTRS_TD
+#define MLIR_DIALECT_MIR_IR_MIRATTRS_TD
+
+include "mlir/Dialect/MIR/IR/MIRBase.td"
+
+//===----------------------------------------------------------------------===//
+// RegBankAttr : the register bank assigned by RegBankSelect
+//===----------------------------------------------------------------------===//
+
+def MIR_RegBankAttr : MIR_Attr<"RegBank", "regbank"> {
+ let summary = "Register bank of a generic virtual register";
+ let description = [{
+ The register bank a generic virtual register was assigned to by
+ RegBankSelect, e.g. `#mir.regbank<"GPR">`. Carried as an optional attribute
+ because it is only present after regbankselect.
+ }];
+ let parameters = (ins StringRefParameter<"bank name">:$name);
+ let assemblyFormat = "`<` $name `>`";
+}
+
+//===----------------------------------------------------------------------===//
+// PhysRegAttr : a named physical register
+//===----------------------------------------------------------------------===//
+
+def MIR_PhysRegAttr : MIR_Attr<"PhysReg", "physreg"> {
+ let summary = "A named physical register";
+ let description = [{
+ A physical register named by the target, e.g. `#mir.physreg<"x0">`. Used
+ only on the ABI-boundary copy operations; physical registers are never
+ modeled as SSA values.
+ }];
+ let parameters = (ins StringRefParameter<"physical register name">:$name);
+ let assemblyFormat = "`<` $name `>`";
+}
+
+//===----------------------------------------------------------------------===//
+// MMOAttr : a MachineMemOperand
+//===----------------------------------------------------------------------===//
+
+def MIR_MMOAttr : MIR_Attr<"MMO", "mmo"> {
+ let summary = "A MachineMemOperand";
+ let description = [{
+ Describes a memory access attached to a memory-touching operation: the
+ access size in bytes, alignment in bytes, and whether it is volatile, e.g.
+ `#mir.mmo<size = 4, align = 4>`.
+ }];
+ let parameters = (ins
+ "uint64_t":$size,
+ "uint64_t":$alignment,
+ DefaultValuedParameter<"bool", "false">:$isVolatile);
+ let assemblyFormat =
+ "`<` `size` `=` $size `,` `align` `=` $alignment"
+ "(`,` `volatile` $isVolatile^)? `>`";
+}
+
+#endif // MLIR_DIALECT_MIR_IR_MIRATTRS_TD
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIRBase.td b/mlir/include/mlir/Dialect/MIR/IR/MIRBase.td
new file mode 100644
index 0000000000000..92598f3b55b06
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIRBase.td
@@ -0,0 +1,71 @@
+//===- MIRBase.td - MIR dialect base definitions -----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MIR dialect, a faithful, SSA-form MLIR representation
+// of pre-register-allocation LLVM MachineIR (the GlobalISel generic opcode
+// layer). Shared types and attributes defined here are reused by target
+// dialects such as `aarch64_mir`.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MIR_IR_MIRBASE_TD
+#define MLIR_DIALECT_MIR_IR_MIRBASE_TD
+
+include "mlir/IR/AttrTypeBase.td"
+include "mlir/IR/DialectBase.td"
+include "mlir/IR/OpBase.td"
+
+//===----------------------------------------------------------------------===//
+// MIR dialect definition
+//===----------------------------------------------------------------------===//
+
+def MIR_Dialect : Dialect {
+ let name = "mir";
+ let cppNamespace = "::mlir::mir";
+ let summary = "Pre-register-allocation LLVM MachineIR, in SSA form";
+ let description = [{
+ The `mir` dialect models the target-independent (GlobalISel generic opcode)
+ layer of LLVM MachineIR at a point in the pipeline before register
+ allocation, where virtual registers are still in SSA form. Generic virtual
+ registers map onto MLIR SSA values whose type is the register's Low Level
+ Type (LLT): a scalar `sN`, a pointer `pN`, or a vector.
+
+ Physical registers only appear pre-RA at ABI boundaries (argument, return,
+ and call copies). They are modeled as attributes on dedicated side-effecting
+ copy operations rather than as SSA values, keeping the value graph pure SSA.
+ }];
+
+ let useDefaultTypePrinterParser = 1;
+ let useDefaultAttributePrinterParser = 1;
+
+ let extraClassDeclaration = [{
+ /// Register the dialect's types.
+ void registerTypes();
+ /// Register the dialect's attributes.
+ void registerAttributes();
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Base classes
+//===----------------------------------------------------------------------===//
+
+class MIR_Op<string mnemonic, list<Trait> traits = []>
+ : Op<MIR_Dialect, mnemonic, traits>;
+
+class MIR_Type<string name, string typeMnemonic, list<Trait> traits = []>
+ : TypeDef<MIR_Dialect, name, traits> {
+ let mnemonic = typeMnemonic;
+}
+
+class MIR_Attr<string name, string attrMnemonic, list<Trait> traits = []>
+ : AttrDef<MIR_Dialect, name, traits> {
+ let mnemonic = attrMnemonic;
+}
+
+#endif // MLIR_DIALECT_MIR_IR_MIRBASE_TD
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIRDialect.h b/mlir/include/mlir/Dialect/MIR/IR/MIRDialect.h
new file mode 100644
index 0000000000000..d5e49e63ae4c0
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIRDialect.h
@@ -0,0 +1,16 @@
+//===- MIRDialect.h - MIR dialect declaration -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MIR_IR_MIRDIALECT_H
+#define MLIR_DIALECT_MIR_IR_MIRDIALECT_H
+
+#include "mlir/IR/Dialect.h"
+
+#include "mlir/Dialect/MIR/IR/MIROpsDialect.h.inc"
+
+#endif // MLIR_DIALECT_MIR_IR_MIRDIALECT_H
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIROps.h b/mlir/include/mlir/Dialect/MIR/IR/MIROps.h
new file mode 100644
index 0000000000000..2513b1153ddcb
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIROps.h
@@ -0,0 +1,24 @@
+//===- MIROps.h - MIR dialect operations ----------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MIR_IR_MIROPS_H
+#define MLIR_DIALECT_MIR_IR_MIROPS_H
+
+#include "mlir/Bytecode/BytecodeOpInterface.h"
+#include "mlir/Dialect/MIR/IR/MIRAttrs.h"
+#include "mlir/Dialect/MIR/IR/MIRDialect.h"
+#include "mlir/Dialect/MIR/IR/MIRTypes.h"
+#include "mlir/IR/OpImplementation.h"
+#include "mlir/IR/SymbolTable.h"
+#include "mlir/Interfaces/InferTypeOpInterface.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/MIR/IR/MIROps.h.inc"
+
+#endif // MLIR_DIALECT_MIR_IR_MIROPS_H
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIROps.td b/mlir/include/mlir/Dialect/MIR/IR/MIROps.td
new file mode 100644
index 0000000000000..96244b1a08772
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIROps.td
@@ -0,0 +1,105 @@
+//===- MIROps.td - MIR dialect operations ------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Operations for the MIR dialect. This file currently hand-defines a
+// representative subset of the generic (G_*) opcodes plus the structural and
+// ABI-boundary operations. The full set of ~279 generic opcodes will be
+// generated from `llvm/include/llvm/Target/GenericOpcodes.td` by the
+// `-gen-mir-generic-ops` mlir-tblgen backend and included here.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MIR_IR_MIROPS_TD
+#define MLIR_DIALECT_MIR_IR_MIROPS_TD
+
+include "mlir/Dialect/MIR/IR/MIRBase.td"
+include "mlir/Dialect/MIR/IR/MIRTypes.td"
+include "mlir/Dialect/MIR/IR/MIRAttrs.td"
+include "mlir/Interfaces/SideEffectInterfaces.td"
+include "mlir/Interfaces/InferTypeOpInterface.td"
+include "mlir/IR/SymbolInterfaces.td"
+
+//===----------------------------------------------------------------------===//
+// FuncOp : a MachineFunction container
+//===----------------------------------------------------------------------===//
+
+def MIR_FuncOp : MIR_Op<"func", [IsolatedFromAbove, NoTerminator]> {
+ let summary = "A MachineFunction";
+ let description = [{
+ Container for a machine function body. Its single region is an SSACFG region
+ whose blocks correspond to MachineBasicBlocks; block successors are expressed
+ through terminator operations.
+ }];
+ let arguments = (ins SymbolNameAttr:$sym_name);
+ let regions = (region AnyRegion:$body);
+ let assemblyFormat = "$sym_name attr-dict-with-keyword $body";
+}
+
+//===----------------------------------------------------------------------===//
+// Generic (G_*) opcodes — representative hand-written subset
+//===----------------------------------------------------------------------===//
+
+def MIR_GAddOp : MIR_Op<"g_add", [Pure, Commutative, SameOperandsAndResultType]> {
+ let summary = "G_ADD: integer addition";
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+ let assemblyFormat = "$src1 `,` $src2 attr-dict `:` type($dst)";
+}
+
+def MIR_GConstantOp : MIR_Op<"g_constant", [Pure]> {
+ let summary = "G_CONSTANT: a scalar integer constant";
+ let arguments = (ins I64Attr:$value);
+ let results = (outs MIR_ScalarType:$dst);
+ let assemblyFormat = "$value attr-dict `:` qualified(type($dst))";
+}
+
+def MIR_GLoadOp : MIR_Op<"g_load"> {
+ let summary = "G_LOAD: a generic load";
+ let arguments = (ins MIR_PointerType:$addr, MIR_MMOAttr:$mmo);
+ let results = (outs MIR_AnyLLT:$dst);
+ let assemblyFormat =
+ "$addr attr-dict `:` qualified(type($addr)) `->` type($dst)";
+}
+
+def MIR_GStoreOp : MIR_Op<"g_store"> {
+ let summary = "G_STORE: a generic store";
+ let arguments = (ins MIR_AnyLLT:$value, MIR_PointerType:$addr, MIR_MMOAttr:$mmo);
+ let assemblyFormat =
+ "$value `,` $addr attr-dict `:` type($value) `,` qualified(type($addr))";
+}
+
+//===----------------------------------------------------------------------===//
+// COPY and ABI-boundary physical-register copies
+//===----------------------------------------------------------------------===//
+
+def MIR_CopyOp : MIR_Op<"copy", [Pure, SameOperandsAndResultType]> {
+ let summary = "COPY between virtual registers";
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+ let assemblyFormat = "$src attr-dict `:` type($dst)";
+}
+
+def MIR_CopyFromPhysOp : MIR_Op<"copy_from_phys"> {
+ let summary = "Define a virtual register from a physical register (ABI in)";
+ let description = [{
+ Materializes a virtual register from an incoming physical register at an ABI
+ boundary (function argument or call result). The physical register is an
+ attribute, not an operand, so the value graph stays SSA.
+ }];
+ let arguments = (ins MIR_PhysRegAttr:$reg);
+ let results = (outs MIR_AnyLLT:$dst);
+ let assemblyFormat = "qualified($reg) attr-dict `->` type($dst)";
+}
+
+def MIR_CopyToPhysOp : MIR_Op<"copy_to_phys"> {
+ let summary = "Copy a virtual register to a physical register (ABI out)";
+ let arguments = (ins MIR_AnyLLT:$src, MIR_PhysRegAttr:$reg);
+ let assemblyFormat = "$src `:` type($src) `to` qualified($reg) attr-dict";
+}
+
+#endif // MLIR_DIALECT_MIR_IR_MIROPS_TD
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIRTypes.h b/mlir/include/mlir/Dialect/MIR/IR/MIRTypes.h
new file mode 100644
index 0000000000000..3f35abc8c697a
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIRTypes.h
@@ -0,0 +1,17 @@
+//===- MIRTypes.h - MIR dialect types -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MIR_IR_MIRTYPES_H
+#define MLIR_DIALECT_MIR_IR_MIRTYPES_H
+
+#include "mlir/IR/Types.h"
+
+#define GET_TYPEDEF_CLASSES
+#include "mlir/Dialect/MIR/IR/MIROpsTypes.h.inc"
+
+#endif // MLIR_DIALECT_MIR_IR_MIRTYPES_H
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIRTypes.td b/mlir/include/mlir/Dialect/MIR/IR/MIRTypes.td
new file mode 100644
index 0000000000000..e2ff235300f79
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIRTypes.td
@@ -0,0 +1,69 @@
+//===- MIRTypes.td - MIR dialect types ---------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// LLT (Low Level Type) modeling. The type of an SSA value in the MIR dialect
+// is the LLT of the generic virtual register it represents.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_MIR_IR_MIRTYPES_TD
+#define MLIR_DIALECT_MIR_IR_MIRTYPES_TD
+
+include "mlir/Dialect/MIR/IR/MIRBase.td"
+
+//===----------------------------------------------------------------------===//
+// ScalarType : LLT sN
+//===----------------------------------------------------------------------===//
+
+def MIR_ScalarType : MIR_Type<"Scalar", "scalar"> {
+ let summary = "LLT scalar type (sN)";
+ let description = [{
+ A scalar Low Level Type of a given bit width, e.g. `!mir.scalar<32>` for the
+ LLT `s32`.
+ }];
+ let parameters = (ins "unsigned":$width);
+ let assemblyFormat = "`<` $width `>`";
+}
+
+//===----------------------------------------------------------------------===//
+// PointerType : LLT pN
+//===----------------------------------------------------------------------===//
+
+def MIR_PointerType : MIR_Type<"Pointer", "pointer"> {
+ let summary = "LLT pointer type (pN)";
+ let description = [{
+ A pointer Low Level Type carrying an address space and a size in bits, e.g.
+ `!mir.pointer<0, 64>` for the LLT `p0` on a 64-bit target.
+ }];
+ let parameters = (ins "unsigned":$addressSpace, "unsigned":$sizeInBits);
+ let assemblyFormat = "`<` $addressSpace `,` $sizeInBits `>`";
+}
+
+//===----------------------------------------------------------------------===//
+// VectorType : LLT <N x sM>
+//===----------------------------------------------------------------------===//
+
+def MIR_VectorType : MIR_Type<"Vector", "vector"> {
+ let summary = "LLT fixed-length vector type";
+ let description = [{
+ A fixed-length vector Low Level Type of a scalar element, e.g.
+ `!mir.vector<4 x !mir.scalar<32>>` for the LLT `<4 x s32>`.
+ }];
+ let parameters = (ins "unsigned":$numElements, "::mlir::mir::ScalarType":$elementType);
+ let assemblyFormat = "`<` $numElements `x` qualified($elementType) `>`";
+}
+
+//===----------------------------------------------------------------------===//
+// Aggregate constraint : any LLT-typed value
+//===----------------------------------------------------------------------===//
+
+def MIR_AnyLLT
+ : AnyTypeOf<[MIR_ScalarType, MIR_PointerType, MIR_VectorType],
+ "any MIR LLT type">;
+
+#endif // MLIR_DIALECT_MIR_IR_MIRTYPES_TD
diff --git a/mlir/lib/Dialect/CMakeLists.txt b/mlir/lib/Dialect/CMakeLists.txt
index 55e75f3f0b9ce..1a10351744f4d 100644
--- a/mlir/lib/Dialect/CMakeLists.txt
+++ b/mlir/lib/Dialect/CMakeLists.txt
@@ -18,6 +18,7 @@ add_subdirectory(Linalg)
add_subdirectory(LLVMIR)
add_subdirectory(Math)
add_subdirectory(MemRef)
+add_subdirectory(MIR)
add_subdirectory(Shard)
add_subdirectory(MLProgram)
add_subdirectory(MPI)
diff --git a/mlir/lib/Dialect/MIR/CMakeLists.txt b/mlir/lib/Dialect/MIR/CMakeLists.txt
new file mode 100644
index 0000000000000..f33061b2d87cf
--- /dev/null
+++ b/mlir/lib/Dialect/MIR/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory(IR)
diff --git a/mlir/lib/Dialect/MIR/IR/CMakeLists.txt b/mlir/lib/Dialect/MIR/IR/CMakeLists.txt
new file mode 100644
index 0000000000000..e9db5b9b6818b
--- /dev/null
+++ b/mlir/lib/Dialect/MIR/IR/CMakeLists.txt
@@ -0,0 +1,14 @@
+add_mlir_dialect_library(MLIRMIRDialect
+ MIRDialect.cpp
+
+ ADDITIONAL_HEADER_DIRS
+ ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/MIR
+
+ DEPENDS
+ MLIRMIROpsIncGen
+
+ LINK_LIBS PUBLIC
+ MLIRIR
+ MLIRInferTypeOpInterface
+ MLIRSideEffectInterfaces
+ )
diff --git a/mlir/lib/Dialect/MIR/IR/MIRDialect.cpp b/mlir/lib/Dialect/MIR/IR/MIRDialect.cpp
new file mode 100644
index 0000000000000..ed19d7d4d35f8
--- /dev/null
+++ b/mlir/lib/Dialect/MIR/IR/MIRDialect.cpp
@@ -0,0 +1,57 @@
+//===- MIRDialect.cpp - MIR dialect implementation ------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/MIR/IR/MIROps.h"
+#include "mlir/IR/Builders.h"
+#include "mlir/IR/DialectImplementation.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+#include "mlir/Dialect/MIR/IR/MIROpsDialect.cpp.inc"
+
+using namespace mlir;
+using namespace mlir::mir;
+
+//===----------------------------------------------------------------------===//
+// MIRDialect
+//===----------------------------------------------------------------------===//
+
+void MIRDialect::initialize() {
+ registerTypes();
+ registerAttributes();
+ addOperations<
+#define GET_OP_LIST
+#include "mlir/Dialect/MIR/IR/MIROps.cpp.inc"
+ >();
+}
+
+void MIRDialect::registerTypes() {
+ addTypes<
+#define GET_TYPEDEF_LIST
+#include "mlir/Dialect/MIR/IR/MIROpsTypes.cpp.inc"
+ >();
+}
+
+void MIRDialect::registerAttributes() {
+ addAttributes<
+#define GET_ATTRDEF_LIST
+#include "mlir/Dialect/MIR/IR/MIROpsAttributes.cpp.inc"
+ >();
+}
+
+//===----------------------------------------------------------------------===//
+// Generated definitions
+//===----------------------------------------------------------------------===//
+
+#define GET_TYPEDEF_CLASSES
+#include "mlir/Dialect/MIR/IR/MIROpsTypes.cpp.inc"
+
+#define GET_ATTRDEF_CLASSES
+#include "mlir/Dialect/MIR/IR/MIROpsAttributes.cpp.inc"
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/MIR/IR/MIROps.cpp.inc"
diff --git a/mlir/lib/RegisterAllDialects.cpp b/mlir/lib/RegisterAllDialects.cpp
index ebc48a4bfc836..b9cd1cc177e5b 100644
--- a/mlir/lib/RegisterAllDialects.cpp
+++ b/mlir/lib/RegisterAllDialects.cpp
@@ -52,6 +52,7 @@
#include "mlir/Dialect/Linalg/IR/Linalg.h"
#include "mlir/Dialect/Linalg/Transforms/AllInterfaces.h"
#include "mlir/Dialect/Linalg/Transforms/RuntimeOpVerification.h"
+#include "mlir/Dialect/MIR/IR/MIRDialect.h"
#include "mlir/Dialect/MLProgram/IR/MLProgram.h"
#include "mlir/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.h"
#include "mlir/Dialect/MPI/IR/MPI.h"
@@ -135,6 +136,7 @@ void mlir::registerAllDialects(DialectRegistry ®istry) {
LLVM::LLVMDialect,
math::MathDialect,
memref::MemRefDialect,
+ mir::MIRDialect,
shard::ShardDialect,
ml_program::MLProgramDialect,
mpi::MPIDialect,
diff --git a/mlir/test/Dialect/MIR/roundtrip.mlir b/mlir/test/Dialect/MIR/roundtrip.mlir
new file mode 100644
index 0000000000000..aa2f43b5108a8
--- /dev/null
+++ b/mlir/test/Dialect/MIR/roundtrip.mlir
@@ -0,0 +1,32 @@
+// RUN: mlir-opt %s | mlir-opt | FileCheck %s
+
+// Exercises the MIR dialect LLT type system, attributes, generic-opcode stubs,
+// and the ABI-boundary physical-register copies. This is a parse/print
+// round-trip (idempotence) check.
+
+// CHECK-LABEL: mir.func @scalar_flow
+mir.func @scalar_flow {
+ // CHECK: %[[C:.*]] = mir.g_constant 42 : !mir.scalar<32>
+ %c = mir.g_constant 42 : !mir.scalar<32>
+ // CHECK: %{{.*}} = mir.g_add %[[C]], %[[C]] : !mir.scalar<32>
+ %s = mir.g_add %c, %c : !mir.scalar<32>
+
+ // CHECK: %[[P:.*]] = mir.copy_from_phys #mir.physreg<"x0"> -> !mir.pointer<0, 64>
+ %p = mir.copy_from_phys #mir.physreg<"x0"> -> !mir.pointer<0, 64>
+ // CHECK: %[[L:.*]] = mir.g_load %[[P]] {mmo = #mir.mmo<size = 4, align = 4>} : !mir.pointer<0, 64> -> !mir.scalar<32>
+ %l = mir.g_load %p {mmo = #mir.mmo<size = 4, align = 4>} : !mir.pointer<0, 64> -> !mir.scalar<32>
+ // CHECK: mir.g_store %[[L]], %[[P]] {mmo = #mir.mmo<size = 8, align = 8, volatile true>} : !mir.scalar<32>, !mir.pointer<0, 64>
+ mir.g_store %l, %p {mmo = #mir.mmo<size = 8, align = 8, volatile true>} : !mir.scalar<32>, !mir.pointer<0, 64>
+
+ // CHECK: %[[CP:.*]] = mir.copy %[[L]] : !mir.scalar<32>
+ %cp = mir.copy %l : !mir.scalar<32>
+ // CHECK: mir.copy_to_phys %[[CP]] : !mir.scalar<32> to #mir.physreg<"x0">
+ mir.copy_to_phys %cp : !mir.scalar<32> to #mir.physreg<"x0">
+}
+
+// CHECK-LABEL: mir.func @vector_type
+mir.func @vector_type {
+ // CHECK: mir.copy %{{.*}} : !mir.vector<4 x !mir.scalar<32>>
+ %v = mir.copy_from_phys #mir.physreg<"q0"> -> !mir.vector<4 x !mir.scalar<32>>
+ %w = mir.copy %v : !mir.vector<4 x !mir.scalar<32>>
+}
>From c28826a9fab776fe2c1892cee37dcb88ab12479b Mon Sep 17 00:00:00 2001
From: makslevental <maksim.levental at gmail.com>
Date: Mon, 24 Aug 2026 10:43:35 -0700
Subject: [PATCH 2/7] [MLIR] Add -gen-mir-generic-ops backend generating all
279 G_* ops
Adds the MIRGenericOpGen mlir-tblgen backend (modeled on LLVMIRIntrinsicGen)
that reads GenericInstruction records from GenericOpcodes.td and emits MLIR ODS
for the mir dialect:
- Generic type variables (type0/ptype0/...) -> MIR_AnyLLT values.
- variable_ops -> Variadic<MIR_AnyLLT> (operands or results).
- Immediate/opaque placeholders -> attributes; C++-keyword names sanitized.
- hasSideEffects/mayLoad/mayStore -> Pure; isCommutable -> Commutative.
All 279 generic opcodes are emitted (none skipped) into the checked-in,
tool-generated MIRGenericOps.td, which MIROps.td includes; the four hand-stubbed
generic ops are removed in favor of the generated set. A uniform
functional-type assembly format (on the MIR_GenericOp base class) handles every
operand/result/attribute shape.
Verified by mlir-tblgen/mir-generic-ops.td (checks emitted ODS and that it
feeds cleanly into -gen-op-decls) and the updated dialect round-trip test.
---
mlir/include/mlir/Dialect/MIR/IR/MIRBase.td | 11 +
.../mlir/Dialect/MIR/IR/MIRGenericOps.td | 1408 +++++++++++++++++
mlir/include/mlir/Dialect/MIR/IR/MIROps.td | 39 +-
mlir/test/Dialect/MIR/roundtrip.mlir | 37 +-
mlir/test/mlir-tblgen/mir-generic-ops.td | 46 +
mlir/tools/mlir-tblgen/CMakeLists.txt | 1 +
mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp | 185 +++
7 files changed, 1680 insertions(+), 47 deletions(-)
create mode 100644 mlir/include/mlir/Dialect/MIR/IR/MIRGenericOps.td
create mode 100644 mlir/test/mlir-tblgen/mir-generic-ops.td
create mode 100644 mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIRBase.td b/mlir/include/mlir/Dialect/MIR/IR/MIRBase.td
index 92598f3b55b06..086fc1607a1eb 100644
--- a/mlir/include/mlir/Dialect/MIR/IR/MIRBase.td
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIRBase.td
@@ -58,6 +58,17 @@ def MIR_Dialect : Dialect {
class MIR_Op<string mnemonic, list<Trait> traits = []>
: Op<MIR_Dialect, mnemonic, traits>;
+// Base class for generated generic (G_*) opcodes. Uses a uniform assembly
+// format that works for any operand/result/attribute shape: operands, then the
+// attribute dictionary (which carries immediates and MachineIR metadata), then
+// the functional type. This avoids per-op custom formats while the generated
+// op set is filled in from GenericOpcodes.td.
+class MIR_GenericOp<string mnemonic, list<Trait> traits = []>
+ : MIR_Op<mnemonic, traits> {
+ let assemblyFormat =
+ "operands attr-dict `:` functional-type(operands, results)";
+}
+
class MIR_Type<string name, string typeMnemonic, list<Trait> traits = []>
: TypeDef<MIR_Dialect, name, traits> {
let mnemonic = typeMnemonic;
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIRGenericOps.td b/mlir/include/mlir/Dialect/MIR/IR/MIRGenericOps.td
new file mode 100644
index 0000000000000..9f53587408f93
--- /dev/null
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIRGenericOps.td
@@ -0,0 +1,1408 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* MIR dialect generic (G_*) operations *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* From: mir_gen.td *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+include "mlir/Dialect/MIR/IR/MIRTypes.td"
+include "mlir/Interfaces/SideEffectInterfaces.td"
+
+def MIR_G_ABDS : MIR_GenericOp<"g_abds", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ABDU : MIR_GenericOp<"g_abdu", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ABS : MIR_GenericOp<"g_abs", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ADD : MIR_GenericOp<"g_add", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ADDRSPACE_CAST : MIR_GenericOp<"g_addrspace_cast", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_AND : MIR_GenericOp<"g_and", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ANYEXT : MIR_GenericOp<"g_anyext", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ASHR : MIR_GenericOp<"g_ashr", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ASSERT_ALIGN : MIR_GenericOp<"g_assert_align", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, AnyAttr:$align);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ASSERT_SEXT : MIR_GenericOp<"g_assert_sext", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, AnyAttr:$sz);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ASSERT_ZEXT : MIR_GenericOp<"g_assert_zext", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, AnyAttr:$sz);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ATOMICRMW_ADD : MIR_GenericOp<"g_atomicrmw_add", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_AND : MIR_GenericOp<"g_atomicrmw_and", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_FADD : MIR_GenericOp<"g_atomicrmw_fadd", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_FMAX : MIR_GenericOp<"g_atomicrmw_fmax", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_FMAXIMUM : MIR_GenericOp<"g_atomicrmw_fmaximum", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_FMAXIMUMNUM : MIR_GenericOp<"g_atomicrmw_fmaximumnum", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_FMIN : MIR_GenericOp<"g_atomicrmw_fmin", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_FMINIMUM : MIR_GenericOp<"g_atomicrmw_fminimum", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_FMINIMUMNUM : MIR_GenericOp<"g_atomicrmw_fminimumnum", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_FSUB : MIR_GenericOp<"g_atomicrmw_fsub", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_MAX : MIR_GenericOp<"g_atomicrmw_max", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_MIN : MIR_GenericOp<"g_atomicrmw_min", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_NAND : MIR_GenericOp<"g_atomicrmw_nand", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_OR : MIR_GenericOp<"g_atomicrmw_or", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_SUB : MIR_GenericOp<"g_atomicrmw_sub", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_UDEC_WRAP : MIR_GenericOp<"g_atomicrmw_udec_wrap", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_UINC_WRAP : MIR_GenericOp<"g_atomicrmw_uinc_wrap", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_UMAX : MIR_GenericOp<"g_atomicrmw_umax", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_UMIN : MIR_GenericOp<"g_atomicrmw_umin", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_USUB_COND : MIR_GenericOp<"g_atomicrmw_usub_cond", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_USUB_SAT : MIR_GenericOp<"g_atomicrmw_usub_sat", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_XCHG : MIR_GenericOp<"g_atomicrmw_xchg", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMICRMW_XOR : MIR_GenericOp<"g_atomicrmw_xor", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMIC_CMPXCHG : MIR_GenericOp<"g_atomic_cmpxchg", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$cmpval, MIR_AnyLLT:$newval);
+ let results = (outs MIR_AnyLLT:$oldval);
+}
+
+def MIR_G_ATOMIC_CMPXCHG_WITH_SUCCESS : MIR_GenericOp<"g_atomic_cmpxchg_with_success", []> {
+ let arguments = (ins MIR_AnyLLT:$addr, MIR_AnyLLT:$cmpval, MIR_AnyLLT:$newval);
+ let results = (outs MIR_AnyLLT:$oldval, MIR_AnyLLT:$success);
+}
+
+def MIR_G_BITCAST : MIR_GenericOp<"g_bitcast", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_BITREVERSE : MIR_GenericOp<"g_bitreverse", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_BLOCK_ADDR : MIR_GenericOp<"g_block_addr", [Pure]> {
+ let arguments = (ins AnyAttr:$ba);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_BR : MIR_GenericOp<"g_br", [Pure]> {
+ let arguments = (ins AnyAttr:$src1);
+ let results = (outs);
+}
+
+def MIR_G_BRCOND : MIR_GenericOp<"g_brcond", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$tst, AnyAttr:$truebb);
+ let results = (outs);
+}
+
+def MIR_G_BRINDIRECT : MIR_GenericOp<"g_brindirect", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs);
+}
+
+def MIR_G_BRJT : MIR_GenericOp<"g_brjt", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$tbl, MIR_AnyLLT:$idx, AnyAttr:$jti);
+ let results = (outs);
+}
+
+def MIR_G_BSWAP : MIR_GenericOp<"g_bswap", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_BUILD_VECTOR : MIR_GenericOp<"g_build_vector", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, Variadic<MIR_AnyLLT>:$varargs);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_BUILD_VECTOR_TRUNC : MIR_GenericOp<"g_build_vector_trunc", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, Variadic<MIR_AnyLLT>:$varargs);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_BZERO : MIR_GenericOp<"g_bzero", []> {
+ let arguments = (ins MIR_AnyLLT:$dst_addr, MIR_AnyLLT:$size, AnyAttr:$tailcall);
+ let results = (outs);
+}
+
+def MIR_G_CLMUL : MIR_GenericOp<"g_clmul", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CONCAT_VECTORS : MIR_GenericOp<"g_concat_vectors", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, Variadic<MIR_AnyLLT>:$varargs);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CONSTANT : MIR_GenericOp<"g_constant", [Pure]> {
+ let arguments = (ins AnyAttr:$imm);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CONSTANT_FOLD_BARRIER : MIR_GenericOp<"g_constant_fold_barrier", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CONSTANT_POOL : MIR_GenericOp<"g_constant_pool", [Pure]> {
+ let arguments = (ins AnyAttr:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CTLS : MIR_GenericOp<"g_ctls", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CTLZ : MIR_GenericOp<"g_ctlz", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CTLZ_ZERO_POISON : MIR_GenericOp<"g_ctlz_zero_poison", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CTPOP : MIR_GenericOp<"g_ctpop", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CTTZ : MIR_GenericOp<"g_cttz", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_CTTZ_ZERO_POISON : MIR_GenericOp<"g_cttz_zero_poison", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_DEBUGTRAP : MIR_GenericOp<"g_debugtrap", []> {
+ let arguments = (ins);
+ let results = (outs);
+}
+
+def MIR_G_DYN_STACKALLOC : MIR_GenericOp<"g_dyn_stackalloc", []> {
+ let arguments = (ins MIR_AnyLLT:$size, AnyAttr:$align);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_EXTRACT : MIR_GenericOp<"g_extract", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, AnyAttr:$offset);
+ let results = (outs MIR_AnyLLT:$res);
+}
+
+def MIR_G_EXTRACT_SUBVECTOR : MIR_GenericOp<"g_extract_subvector", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, AnyAttr:$idx);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_EXTRACT_VECTOR_ELT : MIR_GenericOp<"g_extract_vector_elt", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$idx);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FABS : MIR_GenericOp<"g_fabs", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FACOS : MIR_GenericOp<"g_facos", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FADD : MIR_GenericOp<"g_fadd", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FASIN : MIR_GenericOp<"g_fasin", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FATAN : MIR_GenericOp<"g_fatan", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FATAN2 : MIR_GenericOp<"g_fatan2", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FCANONICALIZE : MIR_GenericOp<"g_fcanonicalize", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FCEIL : MIR_GenericOp<"g_fceil", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FCMP : MIR_GenericOp<"g_fcmp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, AnyAttr:$tst);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FCONSTANT : MIR_GenericOp<"g_fconstant", [Pure]> {
+ let arguments = (ins AnyAttr:$imm);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FCOPYSIGN : MIR_GenericOp<"g_fcopysign", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FCOS : MIR_GenericOp<"g_fcos", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FCOSH : MIR_GenericOp<"g_fcosh", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FDIV : MIR_GenericOp<"g_fdiv", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FENCE : MIR_GenericOp<"g_fence", []> {
+ let arguments = (ins AnyAttr:$ordering, AnyAttr:$scope);
+ let results = (outs);
+}
+
+def MIR_G_FEXP : MIR_GenericOp<"g_fexp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FEXP2 : MIR_GenericOp<"g_fexp2", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FEXP10 : MIR_GenericOp<"g_fexp10", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FFLOOR : MIR_GenericOp<"g_ffloor", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FFREXP : MIR_GenericOp<"g_ffrexp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0);
+ let results = (outs MIR_AnyLLT:$dst0, MIR_AnyLLT:$dst1);
+}
+
+def MIR_G_FLDEXP : MIR_GenericOp<"g_fldexp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FLOG : MIR_GenericOp<"g_flog", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FLOG2 : MIR_GenericOp<"g_flog2", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FLOG10 : MIR_GenericOp<"g_flog10", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMA : MIR_GenericOp<"g_fma", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$src3);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMAD : MIR_GenericOp<"g_fmad", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$src3);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMAXIMUM : MIR_GenericOp<"g_fmaximum", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMAXIMUMNUM : MIR_GenericOp<"g_fmaximumnum", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMAXNUM : MIR_GenericOp<"g_fmaxnum", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMAXNUM_IEEE : MIR_GenericOp<"g_fmaxnum_ieee", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMINIMUM : MIR_GenericOp<"g_fminimum", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMINIMUMNUM : MIR_GenericOp<"g_fminimumnum", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMINNUM : MIR_GenericOp<"g_fminnum", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMINNUM_IEEE : MIR_GenericOp<"g_fminnum_ieee", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FMODF : MIR_GenericOp<"g_fmodf", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst1, MIR_AnyLLT:$dst2);
+}
+
+def MIR_G_FMUL : MIR_GenericOp<"g_fmul", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FNEARBYINT : MIR_GenericOp<"g_fnearbyint", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FNEG : MIR_GenericOp<"g_fneg", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPEXT : MIR_GenericOp<"g_fpext", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPEXTLOAD : MIR_GenericOp<"g_fpextload", []> {
+ let arguments = (ins MIR_AnyLLT:$addr);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPOW : MIR_GenericOp<"g_fpow", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPOWI : MIR_GenericOp<"g_fpowi", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPTOSI : MIR_GenericOp<"g_fptosi", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPTOSI_SAT : MIR_GenericOp<"g_fptosi_sat", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPTOUI : MIR_GenericOp<"g_fptoui", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPTOUI_SAT : MIR_GenericOp<"g_fptoui_sat", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPTRUNC : MIR_GenericOp<"g_fptrunc", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FPTRUNCSTORE : MIR_GenericOp<"g_fptruncstore", []> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$addr);
+ let results = (outs);
+}
+
+def MIR_G_FRAME_INDEX : MIR_GenericOp<"g_frame_index", [Pure]> {
+ let arguments = (ins AnyAttr:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FREEZE : MIR_GenericOp<"g_freeze", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FREM : MIR_GenericOp<"g_frem", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FRINT : MIR_GenericOp<"g_frint", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FSHL : MIR_GenericOp<"g_fshl", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$src3);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FSHR : MIR_GenericOp<"g_fshr", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$src3);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FSIN : MIR_GenericOp<"g_fsin", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FSINCOS : MIR_GenericOp<"g_fsincos", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst1, MIR_AnyLLT:$dst2);
+}
+
+def MIR_G_FSINH : MIR_GenericOp<"g_fsinh", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FSQRT : MIR_GenericOp<"g_fsqrt", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FSUB : MIR_GenericOp<"g_fsub", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FTAN : MIR_GenericOp<"g_ftan", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_FTANH : MIR_GenericOp<"g_ftanh", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_GET_FPENV : MIR_GenericOp<"g_get_fpenv", []> {
+ let arguments = (ins);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_GET_FPMODE : MIR_GenericOp<"g_get_fpmode", []> {
+ let arguments = (ins);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_GET_ROUNDING : MIR_GenericOp<"g_get_rounding", []> {
+ let arguments = (ins);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_GLOBAL_VALUE : MIR_GenericOp<"g_global_value", [Pure]> {
+ let arguments = (ins AnyAttr:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ICMP : MIR_GenericOp<"g_icmp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, AnyAttr:$tst);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_IMPLICIT_DEF : MIR_GenericOp<"g_implicit_def", [Pure]> {
+ let arguments = (ins);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INDEXED_LOAD : MIR_GenericOp<"g_indexed_load", []> {
+ let arguments = (ins MIR_AnyLLT:$base, MIR_AnyLLT:$offset, AnyAttr:$am);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$newaddr);
+}
+
+def MIR_G_INDEXED_SEXTLOAD : MIR_GenericOp<"g_indexed_sextload", []> {
+ let arguments = (ins MIR_AnyLLT:$base, MIR_AnyLLT:$offset, AnyAttr:$am);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$newaddr);
+}
+
+def MIR_G_INDEXED_STORE : MIR_GenericOp<"g_indexed_store", []> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$base, MIR_AnyLLT:$offset, AnyAttr:$am);
+ let results = (outs MIR_AnyLLT:$newaddr);
+}
+
+def MIR_G_INDEXED_ZEXTLOAD : MIR_GenericOp<"g_indexed_zextload", []> {
+ let arguments = (ins MIR_AnyLLT:$base, MIR_AnyLLT:$offset, AnyAttr:$am);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$newaddr);
+}
+
+def MIR_G_INSERT : MIR_GenericOp<"g_insert", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$op, AnyAttr:$offset);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INSERT_SUBVECTOR : MIR_GenericOp<"g_insert_subvector", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$idx);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INSERT_VECTOR_ELT : MIR_GenericOp<"g_insert_vector_elt", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$elt, MIR_AnyLLT:$idx);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INTRINSIC : MIR_GenericOp<"g_intrinsic", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$varargs, AnyAttr:$intrin);
+ let results = (outs);
+}
+
+def MIR_G_INTRINSIC_CONVERGENT : MIR_GenericOp<"g_intrinsic_convergent", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$varargs, AnyAttr:$intrin);
+ let results = (outs);
+}
+
+def MIR_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS : MIR_GenericOp<"g_intrinsic_convergent_w_side_effects", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$varargs, AnyAttr:$intrin);
+ let results = (outs);
+}
+
+def MIR_G_INTRINSIC_FPTRUNC_ROUND : MIR_GenericOp<"g_intrinsic_fptrunc_round", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, AnyAttr:$round_mode);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INTRINSIC_LLRINT : MIR_GenericOp<"g_intrinsic_llrint", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INTRINSIC_LRINT : MIR_GenericOp<"g_intrinsic_lrint", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INTRINSIC_ROUND : MIR_GenericOp<"g_intrinsic_round", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INTRINSIC_ROUNDEVEN : MIR_GenericOp<"g_intrinsic_roundeven", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INTRINSIC_TRUNC : MIR_GenericOp<"g_intrinsic_trunc", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INTRINSIC_W_SIDE_EFFECTS : MIR_GenericOp<"g_intrinsic_w_side_effects", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$varargs, AnyAttr:$intrin);
+ let results = (outs);
+}
+
+def MIR_G_INTTOPTR : MIR_GenericOp<"g_inttoptr", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_INVOKE_REGION_START : MIR_GenericOp<"g_invoke_region_start", [Pure]> {
+ let arguments = (ins);
+ let results = (outs);
+}
+
+def MIR_G_IS_FPCLASS : MIR_GenericOp<"g_is_fpclass", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, AnyAttr:$test);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_JUMP_TABLE : MIR_GenericOp<"g_jump_table", [Pure]> {
+ let arguments = (ins AnyAttr:$jti);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_LLROUND : MIR_GenericOp<"g_llround", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_LOAD : MIR_GenericOp<"g_load", []> {
+ let arguments = (ins MIR_AnyLLT:$addr);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_LROUND : MIR_GenericOp<"g_lround", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_LSHR : MIR_GenericOp<"g_lshr", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_MEMCPY : MIR_GenericOp<"g_memcpy", []> {
+ let arguments = (ins MIR_AnyLLT:$dst_addr, MIR_AnyLLT:$src_addr, MIR_AnyLLT:$size, AnyAttr:$tailcall);
+ let results = (outs);
+}
+
+def MIR_G_MEMCPY_INLINE : MIR_GenericOp<"g_memcpy_inline", []> {
+ let arguments = (ins MIR_AnyLLT:$dst_addr, MIR_AnyLLT:$src_addr, MIR_AnyLLT:$size);
+ let results = (outs);
+}
+
+def MIR_G_MEMMOVE : MIR_GenericOp<"g_memmove", []> {
+ let arguments = (ins MIR_AnyLLT:$dst_addr, MIR_AnyLLT:$src_addr, MIR_AnyLLT:$size, AnyAttr:$tailcall);
+ let results = (outs);
+}
+
+def MIR_G_MEMSET : MIR_GenericOp<"g_memset", []> {
+ let arguments = (ins MIR_AnyLLT:$dst_addr, MIR_AnyLLT:$value, MIR_AnyLLT:$size, AnyAttr:$tailcall);
+ let results = (outs);
+}
+
+def MIR_G_MEMSET_INLINE : MIR_GenericOp<"g_memset_inline", []> {
+ let arguments = (ins MIR_AnyLLT:$dst_addr, MIR_AnyLLT:$value, MIR_AnyLLT:$size);
+ let results = (outs);
+}
+
+def MIR_G_MERGE_VALUES : MIR_GenericOp<"g_merge_values", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, Variadic<MIR_AnyLLT>:$varargs);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_MUL : MIR_GenericOp<"g_mul", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_OR : MIR_GenericOp<"g_or", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_PHI : MIR_GenericOp<"g_phi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$varargs);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_PREFETCH : MIR_GenericOp<"g_prefetch", []> {
+ let arguments = (ins MIR_AnyLLT:$address, AnyAttr:$rw, AnyAttr:$locality, AnyAttr:$cachetype);
+ let results = (outs);
+}
+
+def MIR_G_PTRAUTH_GLOBAL_VALUE : MIR_GenericOp<"g_ptrauth_global_value", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$addrdisc, AnyAttr:$addr, AnyAttr:$key, AnyAttr:$disc);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_PTRMASK : MIR_GenericOp<"g_ptrmask", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$bits);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_PTRTOINT : MIR_GenericOp<"g_ptrtoint", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_PTR_ADD : MIR_GenericOp<"g_ptr_add", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_READCYCLECOUNTER : MIR_GenericOp<"g_readcyclecounter", []> {
+ let arguments = (ins);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_READSTEADYCOUNTER : MIR_GenericOp<"g_readsteadycounter", []> {
+ let arguments = (ins);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_READ_REGISTER : MIR_GenericOp<"g_read_register", []> {
+ let arguments = (ins AnyAttr:$register_);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_RESET_FPENV : MIR_GenericOp<"g_reset_fpenv", []> {
+ let arguments = (ins);
+ let results = (outs);
+}
+
+def MIR_G_RESET_FPMODE : MIR_GenericOp<"g_reset_fpmode", []> {
+ let arguments = (ins);
+ let results = (outs);
+}
+
+def MIR_G_ROTL : MIR_GenericOp<"g_rotl", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ROTR : MIR_GenericOp<"g_rotr", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SADDE : MIR_GenericOp<"g_sadde", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$carry_in);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_SADDO : MIR_GenericOp<"g_saddo", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_SADDSAT : MIR_GenericOp<"g_saddsat", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SAVGCEIL : MIR_GenericOp<"g_savgceil", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SAVGFLOOR : MIR_GenericOp<"g_savgfloor", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SBFX : MIR_GenericOp<"g_sbfx", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$lsb, MIR_AnyLLT:$width);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SCMP : MIR_GenericOp<"g_scmp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SDIV : MIR_GenericOp<"g_sdiv", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SDIVFIX : MIR_GenericOp<"g_sdivfix", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$scale);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SDIVFIXSAT : MIR_GenericOp<"g_sdivfixsat", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$scale);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SDIVREM : MIR_GenericOp<"g_sdivrem", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$div, MIR_AnyLLT:$rem);
+}
+
+def MIR_G_SELECT : MIR_GenericOp<"g_select", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$tst, MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SET_FPENV : MIR_GenericOp<"g_set_fpenv", []> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs);
+}
+
+def MIR_G_SET_FPMODE : MIR_GenericOp<"g_set_fpmode", []> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs);
+}
+
+def MIR_G_SET_ROUNDING : MIR_GenericOp<"g_set_rounding", []> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs);
+}
+
+def MIR_G_SEXT : MIR_GenericOp<"g_sext", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SEXTLOAD : MIR_GenericOp<"g_sextload", []> {
+ let arguments = (ins MIR_AnyLLT:$addr);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SEXT_INREG : MIR_GenericOp<"g_sext_inreg", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, AnyAttr:$sz);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SHL : MIR_GenericOp<"g_shl", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SHUFFLE_VECTOR : MIR_GenericOp<"g_shuffle_vector", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v1, MIR_AnyLLT:$v2, AnyAttr:$mask);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SITOFP : MIR_GenericOp<"g_sitofp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SMAX : MIR_GenericOp<"g_smax", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SMIN : MIR_GenericOp<"g_smin", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SMULFIX : MIR_GenericOp<"g_smulfix", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$scale);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SMULFIXSAT : MIR_GenericOp<"g_smulfixsat", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$scale);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SMULH : MIR_GenericOp<"g_smulh", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SMULO : MIR_GenericOp<"g_smulo", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_SPLAT_VECTOR : MIR_GenericOp<"g_splat_vector", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$val);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SREM : MIR_GenericOp<"g_srem", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SSHLSAT : MIR_GenericOp<"g_sshlsat", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SSUBE : MIR_GenericOp<"g_ssube", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$carry_in);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_SSUBO : MIR_GenericOp<"g_ssubo", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_SSUBSAT : MIR_GenericOp<"g_ssubsat", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STACKRESTORE : MIR_GenericOp<"g_stackrestore", []> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs);
+}
+
+def MIR_G_STACKSAVE : MIR_GenericOp<"g_stacksave", []> {
+ let arguments = (ins);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STEP_VECTOR : MIR_GenericOp<"g_step_vector", [Pure]> {
+ let arguments = (ins AnyAttr:$step);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STORE : MIR_GenericOp<"g_store", []> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$addr);
+ let results = (outs);
+}
+
+def MIR_G_STRICT_FADD : MIR_GenericOp<"g_strict_fadd", [Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FCMP : MIR_GenericOp<"g_strict_fcmp", []> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, AnyAttr:$tst);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FCMPS : MIR_GenericOp<"g_strict_fcmps", []> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, AnyAttr:$tst);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FDIV : MIR_GenericOp<"g_strict_fdiv", []> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FLDEXP : MIR_GenericOp<"g_strict_fldexp", []> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FMA : MIR_GenericOp<"g_strict_fma", []> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$src3);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FMUL : MIR_GenericOp<"g_strict_fmul", [Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FREM : MIR_GenericOp<"g_strict_frem", []> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FSQRT : MIR_GenericOp<"g_strict_fsqrt", []> {
+ let arguments = (ins MIR_AnyLLT:$src1);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_STRICT_FSUB : MIR_GenericOp<"g_strict_fsub", []> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_SUB : MIR_GenericOp<"g_sub", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_TRAP : MIR_GenericOp<"g_trap", []> {
+ let arguments = (ins);
+ let results = (outs);
+}
+
+def MIR_G_TRUNC : MIR_GenericOp<"g_trunc", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_TRUNC_SSAT_S : MIR_GenericOp<"g_trunc_ssat_s", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_TRUNC_SSAT_U : MIR_GenericOp<"g_trunc_ssat_u", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_TRUNC_USAT_U : MIR_GenericOp<"g_trunc_usat_u", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UADDE : MIR_GenericOp<"g_uadde", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$carry_in);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_UADDO : MIR_GenericOp<"g_uaddo", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_UADDSAT : MIR_GenericOp<"g_uaddsat", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UAVGCEIL : MIR_GenericOp<"g_uavgceil", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UAVGFLOOR : MIR_GenericOp<"g_uavgfloor", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UBFX : MIR_GenericOp<"g_ubfx", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src, MIR_AnyLLT:$lsb, MIR_AnyLLT:$width);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UBSANTRAP : MIR_GenericOp<"g_ubsantrap", []> {
+ let arguments = (ins AnyAttr:$kind);
+ let results = (outs);
+}
+
+def MIR_G_UCMP : MIR_GenericOp<"g_ucmp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UDIV : MIR_GenericOp<"g_udiv", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UDIVFIX : MIR_GenericOp<"g_udivfix", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$scale);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UDIVFIXSAT : MIR_GenericOp<"g_udivfixsat", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$scale);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UDIVREM : MIR_GenericOp<"g_udivrem", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$div, MIR_AnyLLT:$rem);
+}
+
+def MIR_G_UITOFP : MIR_GenericOp<"g_uitofp", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UMAX : MIR_GenericOp<"g_umax", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UMIN : MIR_GenericOp<"g_umin", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UMULFIX : MIR_GenericOp<"g_umulfix", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$scale);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UMULFIXSAT : MIR_GenericOp<"g_umulfixsat", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src0, MIR_AnyLLT:$src1, AnyAttr:$scale);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UMULH : MIR_GenericOp<"g_umulh", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_UMULO : MIR_GenericOp<"g_umulo", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_UNMERGE_VALUES : MIR_GenericOp<"g_unmerge_values", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst0, Variadic<MIR_AnyLLT>:$outs);
+}
+
+def MIR_G_UREM : MIR_GenericOp<"g_urem", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_USHLSAT : MIR_GenericOp<"g_ushlsat", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_USUBE : MIR_GenericOp<"g_usube", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2, MIR_AnyLLT:$carry_in);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_USUBO : MIR_GenericOp<"g_usubo", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst, MIR_AnyLLT:$carry_out);
+}
+
+def MIR_G_USUBSAT : MIR_GenericOp<"g_usubsat", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VAARG : MIR_GenericOp<"g_vaarg", []> {
+ let arguments = (ins MIR_AnyLLT:$list, AnyAttr:$align);
+ let results = (outs MIR_AnyLLT:$val);
+}
+
+def MIR_G_VASTART : MIR_GenericOp<"g_vastart", []> {
+ let arguments = (ins MIR_AnyLLT:$list);
+ let results = (outs);
+}
+
+def MIR_G_VECREDUCE_ADD : MIR_GenericOp<"g_vecreduce_add", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_AND : MIR_GenericOp<"g_vecreduce_and", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_FADD : MIR_GenericOp<"g_vecreduce_fadd", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_FMAX : MIR_GenericOp<"g_vecreduce_fmax", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_FMAXIMUM : MIR_GenericOp<"g_vecreduce_fmaximum", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_FMIN : MIR_GenericOp<"g_vecreduce_fmin", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_FMINIMUM : MIR_GenericOp<"g_vecreduce_fminimum", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_FMUL : MIR_GenericOp<"g_vecreduce_fmul", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_MUL : MIR_GenericOp<"g_vecreduce_mul", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_OR : MIR_GenericOp<"g_vecreduce_or", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_SEQ_FADD : MIR_GenericOp<"g_vecreduce_seq_fadd", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$acc, MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_SEQ_FMUL : MIR_GenericOp<"g_vecreduce_seq_fmul", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$acc, MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_SMAX : MIR_GenericOp<"g_vecreduce_smax", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_SMIN : MIR_GenericOp<"g_vecreduce_smin", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_UMAX : MIR_GenericOp<"g_vecreduce_umax", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_UMIN : MIR_GenericOp<"g_vecreduce_umin", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECREDUCE_XOR : MIR_GenericOp<"g_vecreduce_xor", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$v);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VECTOR_COMPRESS : MIR_GenericOp<"g_vector_compress", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$vec, MIR_AnyLLT:$mask, MIR_AnyLLT:$passthru);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_VSCALE : MIR_GenericOp<"g_vscale", [Pure]> {
+ let arguments = (ins AnyAttr:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_WRITE_REGISTER : MIR_GenericOp<"g_write_register", []> {
+ let arguments = (ins MIR_AnyLLT:$value, AnyAttr:$register_);
+ let results = (outs);
+}
+
+def MIR_G_XOR : MIR_GenericOp<"g_xor", [Pure, Commutative]> {
+ let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ZEXT : MIR_GenericOp<"g_zext", [Pure]> {
+ let arguments = (ins MIR_AnyLLT:$src);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+def MIR_G_ZEXTLOAD : MIR_GenericOp<"g_zextload", []> {
+ let arguments = (ins MIR_AnyLLT:$addr);
+ let results = (outs MIR_AnyLLT:$dst);
+}
+
+// Emitted 279 ops, skipped 0.
diff --git a/mlir/include/mlir/Dialect/MIR/IR/MIROps.td b/mlir/include/mlir/Dialect/MIR/IR/MIROps.td
index 96244b1a08772..7b73a4c49b771 100644
--- a/mlir/include/mlir/Dialect/MIR/IR/MIROps.td
+++ b/mlir/include/mlir/Dialect/MIR/IR/MIROps.td
@@ -41,40 +41,21 @@ def MIR_FuncOp : MIR_Op<"func", [IsolatedFromAbove, NoTerminator]> {
}
//===----------------------------------------------------------------------===//
-// Generic (G_*) opcodes — representative hand-written subset
+// Generic (G_*) opcodes
+//
+// The full set of generic opcodes is generated from
+// llvm/include/llvm/Target/GenericOpcodes.td by the `-gen-mir-generic-ops`
+// mlir-tblgen backend and checked in as MIRGenericOps.td.
//===----------------------------------------------------------------------===//
-def MIR_GAddOp : MIR_Op<"g_add", [Pure, Commutative, SameOperandsAndResultType]> {
- let summary = "G_ADD: integer addition";
- let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
- let results = (outs MIR_AnyLLT:$dst);
- let assemblyFormat = "$src1 `,` $src2 attr-dict `:` type($dst)";
-}
-
-def MIR_GConstantOp : MIR_Op<"g_constant", [Pure]> {
- let summary = "G_CONSTANT: a scalar integer constant";
- let arguments = (ins I64Attr:$value);
- let results = (outs MIR_ScalarType:$dst);
- let assemblyFormat = "$value attr-dict `:` qualified(type($dst))";
-}
-
-def MIR_GLoadOp : MIR_Op<"g_load"> {
- let summary = "G_LOAD: a generic load";
- let arguments = (ins MIR_PointerType:$addr, MIR_MMOAttr:$mmo);
- let results = (outs MIR_AnyLLT:$dst);
- let assemblyFormat =
- "$addr attr-dict `:` qualified(type($addr)) `->` type($dst)";
-}
-
-def MIR_GStoreOp : MIR_Op<"g_store"> {
- let summary = "G_STORE: a generic store";
- let arguments = (ins MIR_AnyLLT:$value, MIR_PointerType:$addr, MIR_MMOAttr:$mmo);
- let assemblyFormat =
- "$value `,` $addr attr-dict `:` type($value) `,` qualified(type($addr))";
-}
+include "mlir/Dialect/MIR/IR/MIRGenericOps.td"
//===----------------------------------------------------------------------===//
// COPY and ABI-boundary physical-register copies
+//
+// COPY is a shared TargetOpcode (not a GenericInstruction), and the physical
+// register copies are specific to this dialect's SSA modeling, so these are
+// defined by hand rather than generated.
//===----------------------------------------------------------------------===//
def MIR_CopyOp : MIR_Op<"copy", [Pure, SameOperandsAndResultType]> {
diff --git a/mlir/test/Dialect/MIR/roundtrip.mlir b/mlir/test/Dialect/MIR/roundtrip.mlir
index aa2f43b5108a8..15ee1a372730a 100644
--- a/mlir/test/Dialect/MIR/roundtrip.mlir
+++ b/mlir/test/Dialect/MIR/roundtrip.mlir
@@ -1,32 +1,33 @@
// RUN: mlir-opt %s | mlir-opt | FileCheck %s
-// Exercises the MIR dialect LLT type system, attributes, generic-opcode stubs,
-// and the ABI-boundary physical-register copies. This is a parse/print
-// round-trip (idempotence) check.
+// Exercises the MIR dialect LLT type system, attributes, generated generic
+// (G_*) opcodes, and the ABI-boundary physical-register copies. This is a
+// parse/print round-trip (idempotence) check.
// CHECK-LABEL: mir.func @scalar_flow
mir.func @scalar_flow {
- // CHECK: %[[C:.*]] = mir.g_constant 42 : !mir.scalar<32>
- %c = mir.g_constant 42 : !mir.scalar<32>
- // CHECK: %{{.*}} = mir.g_add %[[C]], %[[C]] : !mir.scalar<32>
- %s = mir.g_add %c, %c : !mir.scalar<32>
-
// CHECK: %[[P:.*]] = mir.copy_from_phys #mir.physreg<"x0"> -> !mir.pointer<0, 64>
%p = mir.copy_from_phys #mir.physreg<"x0"> -> !mir.pointer<0, 64>
- // CHECK: %[[L:.*]] = mir.g_load %[[P]] {mmo = #mir.mmo<size = 4, align = 4>} : !mir.pointer<0, 64> -> !mir.scalar<32>
- %l = mir.g_load %p {mmo = #mir.mmo<size = 4, align = 4>} : !mir.pointer<0, 64> -> !mir.scalar<32>
- // CHECK: mir.g_store %[[L]], %[[P]] {mmo = #mir.mmo<size = 8, align = 8, volatile true>} : !mir.scalar<32>, !mir.pointer<0, 64>
- mir.g_store %l, %p {mmo = #mir.mmo<size = 8, align = 8, volatile true>} : !mir.scalar<32>, !mir.pointer<0, 64>
- // CHECK: %[[CP:.*]] = mir.copy %[[L]] : !mir.scalar<32>
- %cp = mir.copy %l : !mir.scalar<32>
+ // Generated generic opcodes use the uniform functional-type assembly form.
+ // CHECK: %[[L:.*]] = mir.g_load %[[P]] {mmo = #mir.mmo<size = 4, align = 4>} : (!mir.pointer<0, 64>) -> !mir.scalar<32>
+ %l = mir.g_load %p {mmo = #mir.mmo<size = 4, align = 4>} : (!mir.pointer<0, 64>) -> !mir.scalar<32>
+ // CHECK: %[[A:.*]] = mir.g_add %[[L]], %[[L]] : (!mir.scalar<32>, !mir.scalar<32>) -> !mir.scalar<32>
+ %a = mir.g_add %l, %l : (!mir.scalar<32>, !mir.scalar<32>) -> !mir.scalar<32>
+ // CHECK: mir.g_store %[[A]], %[[P]] : (!mir.scalar<32>, !mir.pointer<0, 64>) -> ()
+ mir.g_store %a, %p : (!mir.scalar<32>, !mir.pointer<0, 64>) -> ()
+
+ // CHECK: %[[CP:.*]] = mir.copy %[[A]] : !mir.scalar<32>
+ %cp = mir.copy %a : !mir.scalar<32>
// CHECK: mir.copy_to_phys %[[CP]] : !mir.scalar<32> to #mir.physreg<"x0">
mir.copy_to_phys %cp : !mir.scalar<32> to #mir.physreg<"x0">
}
-// CHECK-LABEL: mir.func @vector_type
-mir.func @vector_type {
- // CHECK: mir.copy %{{.*}} : !mir.vector<4 x !mir.scalar<32>>
+// CHECK-LABEL: mir.func @vector_and_phi
+mir.func @vector_and_phi {
+ // CHECK: %[[V:.*]] = mir.copy_from_phys #mir.physreg<"q0"> -> !mir.vector<4 x !mir.scalar<32>>
%v = mir.copy_from_phys #mir.physreg<"q0"> -> !mir.vector<4 x !mir.scalar<32>>
- %w = mir.copy %v : !mir.vector<4 x !mir.scalar<32>>
+ // Variadic-operand generic op (PHI).
+ // CHECK: %{{.*}} = mir.g_phi %[[V]], %[[V]] : (!mir.vector<4 x !mir.scalar<32>>, !mir.vector<4 x !mir.scalar<32>>) -> !mir.vector<4 x !mir.scalar<32>>
+ %phi = mir.g_phi %v, %v : (!mir.vector<4 x !mir.scalar<32>>, !mir.vector<4 x !mir.scalar<32>>) -> !mir.vector<4 x !mir.scalar<32>>
}
diff --git a/mlir/test/mlir-tblgen/mir-generic-ops.td b/mlir/test/mlir-tblgen/mir-generic-ops.td
new file mode 100644
index 0000000000000..0111099e08ac5
--- /dev/null
+++ b/mlir/test/mlir-tblgen/mir-generic-ops.td
@@ -0,0 +1,46 @@
+// Verify the -gen-mir-generic-ops backend consumes LLVM's generic (G_*) opcode
+// definitions and emits well-formed MLIR ODS.
+//
+// RUN: mlir-tblgen -gen-mir-generic-ops -I %S/../../../llvm/include %s | FileCheck %s
+//
+// It also checks that the emitted ODS is consumable by ODS itself: feeding it
+// back into -gen-op-decls must produce C++ op class declarations.
+//
+// RUN: mlir-tblgen -gen-mir-generic-ops -I %S/../../../llvm/include %s \
+// RUN: | mlir-tblgen -gen-op-decls -I %S/../../include \
+// RUN: | FileCheck --check-prefix=ODS %s
+
+include "llvm/Target/Target.td"
+
+// A pure, commutative binary op with two LLT operands and one LLT result.
+// CHECK: def MIR_G_ADD : MIR_GenericOp<"g_add", [Pure, Commutative]> {
+// CHECK-NEXT: let arguments = (ins MIR_AnyLLT:$src1, MIR_AnyLLT:$src2);
+// CHECK-NEXT: let results = (outs MIR_AnyLLT:$dst);
+
+// A load is not pure (mayLoad) and takes a pointer-typed operand.
+// CHECK: def MIR_G_LOAD : MIR_GenericOp<"g_load", []> {
+// CHECK-NEXT: let arguments = (ins MIR_AnyLLT:$addr);
+// CHECK-NEXT: let results = (outs MIR_AnyLLT:$dst);
+
+// PHI carries a variadic operand list.
+// CHECK: def MIR_G_PHI : MIR_GenericOp<"g_phi", [Pure]> {
+// CHECK-NEXT: let arguments = (ins Variadic<MIR_AnyLLT>:$varargs);
+
+// A store has no results.
+// CHECK: def MIR_G_STORE : MIR_GenericOp<"g_store", []> {
+// CHECK: let results = (outs);
+
+// UNMERGE has variadic results.
+// CHECK: def MIR_G_UNMERGE_VALUES : MIR_GenericOp<"g_unmerge_values", [Pure]> {
+// CHECK: let results = (outs MIR_AnyLLT:$dst0, Variadic<MIR_AnyLLT>:$outs);
+
+// A C++ keyword operand name is sanitized.
+// CHECK: def MIR_G_WRITE_REGISTER : MIR_GenericOp<"g_write_register", []> {
+// CHECK-NEXT: let arguments = (ins MIR_AnyLLT:$value, AnyAttr:$register_);
+
+// All 279 generic opcodes are emitted with none skipped.
+// CHECK: Emitted 279 ops, skipped 0.
+
+// The emitted ODS produces C++ op classes.
+// ODS: class G_ADD
+// ODS: class G_LOAD
diff --git a/mlir/tools/mlir-tblgen/CMakeLists.txt b/mlir/tools/mlir-tblgen/CMakeLists.txt
index 936c84ef58b2b..cf8221157e294 100644
--- a/mlir/tools/mlir-tblgen/CMakeLists.txt
+++ b/mlir/tools/mlir-tblgen/CMakeLists.txt
@@ -19,6 +19,7 @@ add_tablegen(mlir-tblgen MLIR
FormatGen.cpp
LLVMIRConversionGen.cpp
LLVMIRIntrinsicGen.cpp
+ MIRGenericOpGen.cpp
mlir-tblgen.cpp
OmpOpGen.cpp
OpClass.cpp
diff --git a/mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp b/mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp
new file mode 100644
index 0000000000000..cf12118a14f47
--- /dev/null
+++ b/mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp
@@ -0,0 +1,185 @@
+//===- MIRGenericOpGen.cpp - Generate MIR generic-opcode ODS --------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// A TableGen backend that reads LLVM's generic (GlobalISel) opcode definitions
+// from `GenericInstruction` records (llvm/include/llvm/Target/GenericOpcodes.td)
+// and emits MLIR ODS operation definitions for the `mir` dialect.
+//
+// Each `G_*` record becomes an op `mir.g_*` derived from the `MIR_GenericOp`
+// base class. Generic-type operands/results (type0/ptype0/...) map onto the
+// LLT-typed value constraint `MIR_AnyLLT`; `variable_ops` maps to a variadic;
+// immediate placeholders (i32imm, untyped_imm_0, unknown, ...) map to
+// attributes. `hasSideEffects`/`mayLoad`/`mayStore` decide the `Pure` trait and
+// `isCommutable` the `Commutative` trait.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/TableGen/GenInfo.h"
+
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+
+using llvm::DagInit;
+using llvm::DefInit;
+using llvm::Init;
+using llvm::Record;
+using llvm::RecordKeeper;
+using namespace mlir;
+
+/// Return the value of a boolean record field, treating an unset (`?`) or
+/// missing field as `false`.
+static bool getBitOrFalse(const Record &record, llvm::StringRef field) {
+ const llvm::RecordVal *rv = record.getValue(field);
+ if (!rv)
+ return false;
+ if (const auto *bit = llvm::dyn_cast_or_null<llvm::BitInit>(rv->getValue()))
+ return bit->getValue();
+ return false;
+}
+
+/// Return an operand/attribute name safe to use as a C++ identifier in
+/// generated ODS accessors, appending `_` to C++ keywords.
+static std::string sanitizeName(llvm::StringRef name) {
+ static const char *kKeywords[] = {
+ "register", "int", "float", "double", "char", "bool",
+ "void", "class", "struct", "const", "static", "new",
+ "delete", "operator", "template", "default", "return"};
+ for (const char *kw : kKeywords)
+ if (name == kw)
+ return (name + "_").str();
+ return name.str();
+}
+
+/// Classify a dag operand by the name of its `TypedOperand`/marker def and
+/// append the corresponding ODS entry to either the operand or attribute list.
+/// Returns false and does nothing for unrecognized kinds (the caller treats
+/// this as "skip the whole op").
+static bool appendArg(llvm::StringRef defName, llvm::StringRef rawName,
+ llvm::SmallVectorImpl<std::string> &operands,
+ llvm::SmallVectorImpl<std::string> &attributes) {
+ std::string argName = sanitizeName(rawName);
+ // Generic type variables and pointer type variables become LLT-typed values.
+ if (defName.starts_with("type") || defName.starts_with("ptype")) {
+ operands.push_back(("MIR_AnyLLT:$" + argName));
+ return true;
+ }
+ // A variadic tail of same-typed values.
+ if (defName == "variable_ops") {
+ operands.push_back("Variadic<MIR_AnyLLT>:$varargs");
+ return true;
+ }
+ // Immediate / opaque placeholders become attributes.
+ if (defName == "unknown" || defName.ends_with("imm") ||
+ defName.starts_with("untyped_imm") || defName.starts_with("i") ) {
+ attributes.push_back(("AnyAttr:$" + argName));
+ return true;
+ }
+ return false;
+}
+
+/// Emit the ODS definition for a single `GenericInstruction` record. Returns
+/// true if the op was emitted, false if it was skipped.
+static bool emitGenericOp(const Record &record, llvm::raw_ostream &os) {
+ llvm::StringRef recordName = record.getName();
+ std::string opName = recordName.lower(); // G_ADD -> g_add
+
+ const DagInit *outs = record.getValueAsDag("OutOperandList");
+ const DagInit *ins = record.getValueAsDag("InOperandList");
+
+ llvm::SmallVector<std::string> operands, attributes, results;
+
+ auto handleDag = [&](const DagInit *dag, bool isResult) -> bool {
+ for (unsigned i = 0, e = dag->getNumArgs(); i < e; ++i) {
+ const auto *def = llvm::dyn_cast<DefInit>(dag->getArg(i));
+ if (!def)
+ return false;
+ llvm::StringRef defName = def->getDef()->getName();
+ llvm::StringRef argName = dag->getArgNameStr(i);
+ if (isResult) {
+ // Generic type variables become LLT-typed results; a trailing
+ // `variable_ops` becomes a single variadic result.
+ if (defName.starts_with("type") || defName.starts_with("ptype")) {
+ results.push_back("MIR_AnyLLT:$" + sanitizeName(argName));
+ continue;
+ }
+ if (defName == "variable_ops") {
+ results.push_back("Variadic<MIR_AnyLLT>:$outs");
+ continue;
+ }
+ return false;
+ }
+ if (!appendArg(defName, argName, operands, attributes))
+ return false;
+ }
+ return true;
+ };
+
+ if (!handleDag(outs, /*isResult=*/true) || !handleDag(ins, /*isResult=*/false))
+ return false;
+
+ // Traits.
+ llvm::SmallVector<llvm::StringRef> traits;
+ bool pure = !getBitOrFalse(record, "hasSideEffects") &&
+ !getBitOrFalse(record, "mayLoad") &&
+ !getBitOrFalse(record, "mayStore");
+ if (pure)
+ traits.push_back("Pure");
+ if (getBitOrFalse(record, "isCommutable"))
+ traits.push_back("Commutative");
+
+ // Emit.
+ os << "def MIR_" << recordName << " : MIR_GenericOp<\"" << opName << "\", [";
+ llvm::interleaveComma(traits, os);
+ os << "]> {\n";
+
+ os << " let arguments = (ins";
+ llvm::SmallVector<std::string> args(operands);
+ args.append(attributes.begin(), attributes.end());
+ if (!args.empty()) {
+ os << " ";
+ llvm::interleaveComma(args, os);
+ }
+ os << ");\n";
+
+ os << " let results = (outs";
+ if (!results.empty()) {
+ os << " ";
+ llvm::interleaveComma(results, os);
+ }
+ os << ");\n";
+
+ os << "}\n\n";
+ return true;
+}
+
+static bool emitGenericOps(const RecordKeeper &records, llvm::raw_ostream &os) {
+ llvm::emitSourceFileHeader("MIR dialect generic (G_*) operations", os,
+ records);
+ // Emit includes so the generated file is self-contained. Include guards in
+ // these headers make re-inclusion (when MIROps.td also includes them) safe.
+ os << "include \"mlir/Dialect/MIR/IR/MIRTypes.td\"\n";
+ os << "include \"mlir/Interfaces/SideEffectInterfaces.td\"\n\n";
+ unsigned emitted = 0, skipped = 0;
+ for (const Record *r : records.getAllDerivedDefinitions("GenericInstruction")) {
+ if (emitGenericOp(*r, os))
+ ++emitted;
+ else {
+ ++skipped;
+ os << "// skipped: " << r->getName() << "\n";
+ }
+ }
+ os << "// Emitted " << emitted << " ops, skipped " << skipped << ".\n";
+ return false;
+}
+
+static mlir::GenRegistration
+ genMIRGenericOps("gen-mir-generic-ops",
+ "Generate MIR dialect generic (G_*) operation ODS",
+ emitGenericOps);
>From 803d83b4aaffc5a9f823b6ce0f34b65ef0b418f9 Mon Sep 17 00:00:00 2001
From: makslevental <maksim.levental at gmail.com>
Date: Mon, 24 Aug 2026 10:55:51 -0700
Subject: [PATCH 3/7] [MLIR] Add aarch64_mir dialect and -gen-mir-target-ops
backend
Adds the second, closely-coupled dialect: aarch64_mir, modeling AArch64
selected (post-instruction-select, pre-RA) MachineIR.
- MIRTargetOpGen (-gen-mir-target-ops) reads a target's Instruction records
(filtered by Namespace, skipping pseudos/codegen-only) and collapses the many
per-encoding/per-operand-kind variants into one op per assembler mnemonic:
7484 AArch64 instructions -> 1551 ops. Operands/results are modeled as
variadic mir LLT values with an optional `variant` discriminator; each op
records the concrete opcodes it subsumes (the lowering table for export).
Mnemonics and identifiers are sanitized (e.g. "b.$cond" -> b_cond; the
"and" mnemonic keeps its name but gets class/def name and_).
- The aarch64_mir dialect depends on mir and reuses MIR_AnyLLT; its ops
intermix with generic mir.g_* ops in a single mir.func, as in a
partially-selected function.
Verified by mir-aarch64-ops.td (generator output) and
Dialect/AArch64MIR/roundtrip.mlir (mixed generic + selected round-trip).
---
.../mlir/Dialect/AArch64MIR/CMakeLists.txt | 1 +
.../Dialect/AArch64MIR/IR/AArch64MIRBase.td | 46 +
.../Dialect/AArch64MIR/IR/AArch64MIRDialect.h | 16 +
.../Dialect/AArch64MIR/IR/AArch64MIRGenOps.td | 10870 ++++++++++++++++
.../Dialect/AArch64MIR/IR/AArch64MIROps.h | 21 +
.../Dialect/AArch64MIR/IR/AArch64MIROps.td | 20 +
.../mlir/Dialect/AArch64MIR/IR/CMakeLists.txt | 2 +
mlir/include/mlir/Dialect/CMakeLists.txt | 1 +
mlir/lib/Dialect/AArch64MIR/CMakeLists.txt | 1 +
.../AArch64MIR/IR/AArch64MIRDialect.cpp | 27 +
mlir/lib/Dialect/AArch64MIR/IR/CMakeLists.txt | 14 +
mlir/lib/Dialect/CMakeLists.txt | 1 +
mlir/lib/RegisterAllDialects.cpp | 2 +
mlir/test/Dialect/AArch64MIR/roundtrip.mlir | 24 +
mlir/test/mlir-tblgen/mir-aarch64-ops.td | 27 +
mlir/tools/mlir-tblgen/CMakeLists.txt | 1 +
mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp | 206 +
17 files changed, 11280 insertions(+)
create mode 100644 mlir/include/mlir/Dialect/AArch64MIR/CMakeLists.txt
create mode 100644 mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRBase.td
create mode 100644 mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRDialect.h
create mode 100644 mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRGenOps.td
create mode 100644 mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIROps.h
create mode 100644 mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIROps.td
create mode 100644 mlir/include/mlir/Dialect/AArch64MIR/IR/CMakeLists.txt
create mode 100644 mlir/lib/Dialect/AArch64MIR/CMakeLists.txt
create mode 100644 mlir/lib/Dialect/AArch64MIR/IR/AArch64MIRDialect.cpp
create mode 100644 mlir/lib/Dialect/AArch64MIR/IR/CMakeLists.txt
create mode 100644 mlir/test/Dialect/AArch64MIR/roundtrip.mlir
create mode 100644 mlir/test/mlir-tblgen/mir-aarch64-ops.td
create mode 100644 mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
diff --git a/mlir/include/mlir/Dialect/AArch64MIR/CMakeLists.txt b/mlir/include/mlir/Dialect/AArch64MIR/CMakeLists.txt
new file mode 100644
index 0000000000000..f33061b2d87cf
--- /dev/null
+++ b/mlir/include/mlir/Dialect/AArch64MIR/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory(IR)
diff --git a/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRBase.td b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRBase.td
new file mode 100644
index 0000000000000..bd9e836f129ff
--- /dev/null
+++ b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRBase.td
@@ -0,0 +1,46 @@
+//===- AArch64MIRBase.td - AArch64 MIR dialect base --------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// The `aarch64_mir` dialect models AArch64 selected (post-instruction-select,
+// pre-register-allocation) MachineIR. It is closely coupled to the `mir`
+// dialect: its ops reuse the mir LLT type system (MIR_AnyLLT) and live in the
+// same mir.func container, intermixing with generic (mir.g_*) ops in a
+// partially-selected function.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIRBASE_TD
+#define MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIRBASE_TD
+
+include "mlir/IR/OpBase.td"
+include "mlir/Dialect/MIR/IR/MIRTypes.td"
+
+def AArch64MIR_Dialect : Dialect {
+ let name = "aarch64_mir";
+ let cppNamespace = "::mlir::aarch64_mir";
+ let summary = "AArch64 selected, pre-register-allocation MachineIR";
+ let description = [{
+ Operations for AArch64 selected MachineIR, generated from AArch64's
+ instruction TableGen by the `-gen-mir-target-ops` backend. The many
+ per-encoding / per-operand-kind record variants of a mnemonic are collapsed
+ into a single op; the concrete target opcode is recovered at export time
+ from the operand types plus an optional `variant` discriminator.
+ }];
+
+ let dependentDialects = ["::mlir::mir::MIRDialect"];
+}
+
+// Base class for generated AArch64 target ops. Uses the same uniform assembly
+// format as the generic MIR ops.
+class AArch64MIR_TargetOp<string mnemonic, list<Trait> traits = []>
+ : Op<AArch64MIR_Dialect, mnemonic, traits> {
+ let assemblyFormat =
+ "operands attr-dict `:` functional-type(operands, results)";
+}
+
+#endif // MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIRBASE_TD
diff --git a/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRDialect.h b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRDialect.h
new file mode 100644
index 0000000000000..fcfad357e6937
--- /dev/null
+++ b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRDialect.h
@@ -0,0 +1,16 @@
+//===- AArch64MIRDialect.h - AArch64 MIR dialect --------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIRDIALECT_H
+#define MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIRDIALECT_H
+
+#include "mlir/IR/Dialect.h"
+
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIROpsDialect.h.inc"
+
+#endif // MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIRDIALECT_H
diff --git a/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRGenOps.td b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRGenOps.td
new file mode 100644
index 0000000000000..58f4b7a19660c
--- /dev/null
+++ b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIRGenOps.td
@@ -0,0 +1,10870 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* AArch64 MIR target operations *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* From: a64.td *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+include "mlir/Dialect/MIR/IR/MIRTypes.td"
+include "mlir/Interfaces/SideEffectInterfaces.td"
+
+def AArch64MIR_abs : AArch64MIR_TargetOp<"abs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ABSWr ABSXr ABS_ZPmZ_B ABS_ZPmZ_D ABS_ZPmZ_H ABS_ZPmZ_S ABS_ZPzZ_B ABS_ZPzZ_D ABS_ZPzZ_H ABS_ZPzZ_S ABSv1i64 ABSv2i32 ABSv2i64 ABSv4i16 ABSv4i32 ABSv8i8 ABSv8i16 ABSv16i8
+}
+
+def AArch64MIR_adclb : AArch64MIR_TargetOp<"adclb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADCLB_ZZZ_D ADCLB_ZZZ_S
+}
+
+def AArch64MIR_adclt : AArch64MIR_TargetOp<"adclt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADCLT_ZZZ_D ADCLT_ZZZ_S
+}
+
+def AArch64MIR_adcs : AArch64MIR_TargetOp<"adcs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADCSWr ADCSXr
+}
+
+def AArch64MIR_adc : AArch64MIR_TargetOp<"adc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADCWr ADCXr
+}
+
+def AArch64MIR_addg : AArch64MIR_TargetOp<"addg", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDG
+}
+
+def AArch64MIR_addha : AArch64MIR_TargetOp<"addha", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDHA_MPPZ_D ADDHA_MPPZ_S
+}
+
+def AArch64MIR_addhnb : AArch64MIR_TargetOp<"addhnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDHNB_ZZZ_B ADDHNB_ZZZ_H ADDHNB_ZZZ_S
+}
+
+def AArch64MIR_addhnt : AArch64MIR_TargetOp<"addhnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDHNT_ZZZ_B ADDHNT_ZZZ_H ADDHNT_ZZZ_S
+}
+
+def AArch64MIR_addhn : AArch64MIR_TargetOp<"addhn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDHNv2i64_v2i32 ADDHNv4i32_v4i16 ADDHNv8i16_v8i8
+}
+
+def AArch64MIR_addhn2 : AArch64MIR_TargetOp<"addhn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDHNv2i64_v4i32 ADDHNv4i32_v8i16 ADDHNv8i16_v16i8
+}
+
+def AArch64MIR_addpl : AArch64MIR_TargetOp<"addpl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDPL_XXI
+}
+
+def AArch64MIR_addpt : AArch64MIR_TargetOp<"addpt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDPT_shift ADD_ZPmZ_CPA ADD_ZZZ_CPA
+}
+
+def AArch64MIR_addp : AArch64MIR_TargetOp<"addp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDP_ZPmZ_B ADDP_ZPmZ_D ADDP_ZPmZ_H ADDP_ZPmZ_S ADDPv2i32 ADDPv2i64 ADDPv2i64p ADDPv4i16 ADDPv4i32 ADDPv8i8 ADDPv8i16 ADDPv16i8
+}
+
+def AArch64MIR_addqp : AArch64MIR_TargetOp<"addqp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDQP_ZZZ_B ADDQP_ZZZ_D ADDQP_ZZZ_H ADDQP_ZZZ_S
+}
+
+def AArch64MIR_addqv : AArch64MIR_TargetOp<"addqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDQV_VPZ_B ADDQV_VPZ_D ADDQV_VPZ_H ADDQV_VPZ_S
+}
+
+def AArch64MIR_addspl : AArch64MIR_TargetOp<"addspl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDSPL_XXI
+}
+
+def AArch64MIR_addsubp : AArch64MIR_TargetOp<"addsubp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDSUBP_ZZZ_B ADDSUBP_ZZZ_D ADDSUBP_ZZZ_H ADDSUBP_ZZZ_S
+}
+
+def AArch64MIR_addsvl : AArch64MIR_TargetOp<"addsvl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDSVL_XXI
+}
+
+def AArch64MIR_adds : AArch64MIR_TargetOp<"adds", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDSWri ADDSWrs ADDSWrx ADDSXri ADDSXrs ADDSXrx ADDSXrx64
+}
+
+def AArch64MIR_addva : AArch64MIR_TargetOp<"addva", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDVA_MPPZ_D ADDVA_MPPZ_S
+}
+
+def AArch64MIR_addvl : AArch64MIR_TargetOp<"addvl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDVL_XXI
+}
+
+def AArch64MIR_addv : AArch64MIR_TargetOp<"addv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDVv4i16v ADDVv4i32v ADDVv8i8v ADDVv8i16v ADDVv16i8v
+}
+
+def AArch64MIR_add : AArch64MIR_TargetOp<"add", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADDWri ADDWrs ADDWrx ADDXri ADDXrs ADDXrx ADDXrx64 ADD_VG2_2ZZ_B ADD_VG2_2ZZ_D ADD_VG2_2ZZ_H ADD_VG2_2ZZ_S ADD_VG2_M2Z2Z_D ADD_VG2_M2Z2Z_S ADD_VG2_M2ZZ_D ADD_VG2_M2ZZ_S ADD_VG2_M2Z_D ADD_VG2_M2Z_S ADD_VG4_4ZZ_B ADD_VG4_4ZZ_D ADD_VG4_4ZZ_H ADD_VG4_4ZZ_S ADD_VG4_M4Z4Z_D ADD_VG4_M4Z4Z_S ADD_VG4_M4ZZ_D ADD_VG4_M4ZZ_S ADD_VG4_M4Z_D ADD_VG4_M4Z_S ADD_ZI_B ADD_ZI_D ADD_ZI_H ADD_ZI_S ADD_ZPmZ_B ADD_ZPmZ_D ADD_ZPmZ_H ADD_ZPmZ_S ADD_ZZZ_B ADD_ZZZ_D ADD_ZZZ_H ADD_ZZZ_S ADDv1i64 ADDv2i32 ADDv2i64 ADDv4i16 ADDv4i32 ADDv8i8 ADDv8i16 ADDv16i8
+}
+
+def AArch64MIR_adr : AArch64MIR_TargetOp<"adr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADR ADR_LSL_ZZZ_D_0 ADR_LSL_ZZZ_D_1 ADR_LSL_ZZZ_D_2 ADR_LSL_ZZZ_D_3 ADR_LSL_ZZZ_S_0 ADR_LSL_ZZZ_S_1 ADR_LSL_ZZZ_S_2 ADR_LSL_ZZZ_S_3 ADR_SXTW_ZZZ_D_0 ADR_SXTW_ZZZ_D_1 ADR_SXTW_ZZZ_D_2 ADR_SXTW_ZZZ_D_3 ADR_UXTW_ZZZ_D_0 ADR_UXTW_ZZZ_D_1 ADR_UXTW_ZZZ_D_2 ADR_UXTW_ZZZ_D_3
+}
+
+def AArch64MIR_adrp : AArch64MIR_TargetOp<"adrp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ADRP
+}
+
+def AArch64MIR_aesdimc : AArch64MIR_TargetOp<"aesdimc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AESDIMC_2ZZI_B AESDIMC_4ZZI_B
+}
+
+def AArch64MIR_aesd : AArch64MIR_TargetOp<"aesd", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AESD_2ZZI_B AESD_4ZZI_B AESD_ZZZ_B AESDrr
+}
+
+def AArch64MIR_aesemc : AArch64MIR_TargetOp<"aesemc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AESEMC_2ZZI_B AESEMC_4ZZI_B
+}
+
+def AArch64MIR_aese : AArch64MIR_TargetOp<"aese", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AESE_2ZZI_B AESE_4ZZI_B AESE_ZZZ_B AESErr
+}
+
+def AArch64MIR_aesimc : AArch64MIR_TargetOp<"aesimc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AESIMC_ZZ_B AESIMCrr
+}
+
+def AArch64MIR_aesmc : AArch64MIR_TargetOp<"aesmc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AESMC_ZZ_B AESMCrr
+}
+
+def AArch64MIR_andqv : AArch64MIR_TargetOp<"andqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ANDQV_VPZ_B ANDQV_VPZ_D ANDQV_VPZ_H ANDQV_VPZ_S
+}
+
+def AArch64MIR_ands : AArch64MIR_TargetOp<"ands", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ANDSWri ANDSWrs ANDSXri ANDSXrs ANDS_PPzPP
+}
+
+def AArch64MIR_andv : AArch64MIR_TargetOp<"andv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ANDV_VPZ_B ANDV_VPZ_D ANDV_VPZ_H ANDV_VPZ_S
+}
+
+def AArch64MIR_and_ : AArch64MIR_TargetOp<"and", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ANDWri ANDWrs ANDXri ANDXrs AND_PPzPP AND_ZI AND_ZPmZ_B AND_ZPmZ_D AND_ZPmZ_H AND_ZPmZ_S AND_ZZZ ANDv8i8 ANDv16i8
+}
+
+def AArch64MIR_asrd : AArch64MIR_TargetOp<"asrd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ASRD_ZPmI_B ASRD_ZPmI_D ASRD_ZPmI_H ASRD_ZPmI_S
+}
+
+def AArch64MIR_asrr : AArch64MIR_TargetOp<"asrr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ASRR_ZPmZ_B ASRR_ZPmZ_D ASRR_ZPmZ_H ASRR_ZPmZ_S
+}
+
+def AArch64MIR_asr : AArch64MIR_TargetOp<"asr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ASRVWr ASRVXr ASR_WIDE_ZPmZ_B ASR_WIDE_ZPmZ_H ASR_WIDE_ZPmZ_S ASR_WIDE_ZZZ_B ASR_WIDE_ZZZ_H ASR_WIDE_ZZZ_S ASR_ZPmI_B ASR_ZPmI_D ASR_ZPmI_H ASR_ZPmI_S ASR_ZPmZ_B ASR_ZPmZ_D ASR_ZPmZ_H ASR_ZPmZ_S ASR_ZZI_B ASR_ZZI_D ASR_ZZI_H ASR_ZZI_S
+}
+
+def AArch64MIR_autda : AArch64MIR_TargetOp<"autda", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTDA
+}
+
+def AArch64MIR_autdb : AArch64MIR_TargetOp<"autdb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTDB
+}
+
+def AArch64MIR_autdza : AArch64MIR_TargetOp<"autdza", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTDZA
+}
+
+def AArch64MIR_autdzb : AArch64MIR_TargetOp<"autdzb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTDZB
+}
+
+def AArch64MIR_autia : AArch64MIR_TargetOp<"autia", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIA
+}
+
+def AArch64MIR_hint : AArch64MIR_TargetOp<"hint", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIA1716 AUTIASP AUTIAZ AUTIB1716 AUTIBSP AUTIBZ CHKFEAT HINT NOP PACIA1716 PACIASP PACIAZ PACIB1716 PACIBSP PACIBZ PACM XPACLRI
+}
+
+def AArch64MIR_autia171615 : AArch64MIR_TargetOp<"autia171615", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIA171615
+}
+
+def AArch64MIR_autiasppc : AArch64MIR_TargetOp<"autiasppc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIASPPCi
+}
+
+def AArch64MIR_autiasppcr : AArch64MIR_TargetOp<"autiasppcr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIASPPCr
+}
+
+def AArch64MIR_autib : AArch64MIR_TargetOp<"autib", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIB
+}
+
+def AArch64MIR_autib171615 : AArch64MIR_TargetOp<"autib171615", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIB171615
+}
+
+def AArch64MIR_autibsppc : AArch64MIR_TargetOp<"autibsppc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIBSPPCi
+}
+
+def AArch64MIR_autibsppcr : AArch64MIR_TargetOp<"autibsppcr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIBSPPCr
+}
+
+def AArch64MIR_autiza : AArch64MIR_TargetOp<"autiza", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIZA
+}
+
+def AArch64MIR_autizb : AArch64MIR_TargetOp<"autizb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AUTIZB
+}
+
+def AArch64MIR_axflag : AArch64MIR_TargetOp<"axflag", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: AXFLAG
+}
+
+def AArch64MIR_b : AArch64MIR_TargetOp<"b", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: B
+}
+
+def AArch64MIR_bcax : AArch64MIR_TargetOp<"bcax", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BCAX BCAX_ZZZZ
+}
+
+def AArch64MIR_bc_cond : AArch64MIR_TargetOp<"bc_cond", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BCcc
+}
+
+def AArch64MIR_bdep : AArch64MIR_TargetOp<"bdep", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BDEP_ZZZ_B BDEP_ZZZ_D BDEP_ZZZ_H BDEP_ZZZ_S
+}
+
+def AArch64MIR_bext : AArch64MIR_TargetOp<"bext", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BEXT_ZZZ_B BEXT_ZZZ_D BEXT_ZZZ_H BEXT_ZZZ_S
+}
+
+def AArch64MIR_bf1cvtl : AArch64MIR_TargetOp<"bf1cvtl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF1CVTL BF1CVTL_2ZZ_BtoH
+}
+
+def AArch64MIR_bf1cvtl2 : AArch64MIR_TargetOp<"bf1cvtl2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF1CVTL2
+}
+
+def AArch64MIR_bf1cvtlt : AArch64MIR_TargetOp<"bf1cvtlt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF1CVTLT_ZZ_BtoH
+}
+
+def AArch64MIR_bf1cvt : AArch64MIR_TargetOp<"bf1cvt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF1CVT_2ZZ_BtoH BF1CVT_ZZ_BtoH
+}
+
+def AArch64MIR_bf2cvtl : AArch64MIR_TargetOp<"bf2cvtl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF2CVTL BF2CVTL_2ZZ_BtoH
+}
+
+def AArch64MIR_bf2cvtl2 : AArch64MIR_TargetOp<"bf2cvtl2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF2CVTL2
+}
+
+def AArch64MIR_bf2cvtlt : AArch64MIR_TargetOp<"bf2cvtlt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF2CVTLT_ZZ_BtoH
+}
+
+def AArch64MIR_bf2cvt : AArch64MIR_TargetOp<"bf2cvt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF2CVT_2ZZ_BtoH BF2CVT_ZZ_BtoH
+}
+
+def AArch64MIR_bfdot : AArch64MIR_TargetOp<"bfdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BF16DOTlanev4bf16 BF16DOTlanev8bf16 BFDOT_VG2_M2Z2Z_HtoS BFDOT_VG2_M2ZZI_HtoS BFDOT_VG2_M2ZZ_HtoS BFDOT_VG4_M4Z4Z_HtoS BFDOT_VG4_M4ZZI_HtoS BFDOT_VG4_M4ZZ_HtoS BFDOT_ZZI BFDOT_ZZZ BFDOTv4bf16 BFDOTv8bf16
+}
+
+def AArch64MIR_bfadd : AArch64MIR_TargetOp<"bfadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFADD_VG2_M2Z_H BFADD_VG4_M4Z_H BFADD_ZPmZ BFADD_ZZZ
+}
+
+def AArch64MIR_bfclamp : AArch64MIR_TargetOp<"bfclamp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFCLAMP_VG2_2ZZZ_H BFCLAMP_VG4_4ZZZ_H BFCLAMP_ZZZ
+}
+
+def AArch64MIR_bfcvt : AArch64MIR_TargetOp<"bfcvt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFCVT BFCVT_Z2Z_HtoB BFCVT_Z2Z_StoH BFCVT_ZPmZ BFCVT_ZPzZ_StoH
+}
+
+def AArch64MIR_bfcvtn : AArch64MIR_TargetOp<"bfcvtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFCVTN BFCVTN_Z2Z_HtoB BFCVTN_Z2Z_StoH
+}
+
+def AArch64MIR_bfcvtn2 : AArch64MIR_TargetOp<"bfcvtn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFCVTN2
+}
+
+def AArch64MIR_bfcvtnt : AArch64MIR_TargetOp<"bfcvtnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFCVTNT_ZPmZ BFCVTNT_ZPzZ_StoH
+}
+
+def AArch64MIR_bfmaxnm : AArch64MIR_TargetOp<"bfmaxnm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMAXNM_VG2_2Z2Z_H BFMAXNM_VG2_2ZZ_H BFMAXNM_VG4_4Z2Z_H BFMAXNM_VG4_4ZZ_H BFMAXNM_ZPmZ
+}
+
+def AArch64MIR_bfmax : AArch64MIR_TargetOp<"bfmax", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMAX_VG2_2Z2Z_H BFMAX_VG2_2ZZ_H BFMAX_VG4_4Z2Z_H BFMAX_VG4_4ZZ_H BFMAX_ZPmZ
+}
+
+def AArch64MIR_bfminnm : AArch64MIR_TargetOp<"bfminnm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMINNM_VG2_2Z2Z_H BFMINNM_VG2_2ZZ_H BFMINNM_VG4_4Z2Z_H BFMINNM_VG4_4ZZ_H BFMINNM_ZPmZ
+}
+
+def AArch64MIR_bfmin : AArch64MIR_TargetOp<"bfmin", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMIN_VG2_2Z2Z_H BFMIN_VG2_2ZZ_H BFMIN_VG4_4Z2Z_H BFMIN_VG4_4ZZ_H BFMIN_ZPmZ
+}
+
+def AArch64MIR_bfmlalb : AArch64MIR_TargetOp<"bfmlalb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMLALB BFMLALBIdx BFMLALB_ZZZ BFMLALB_ZZZI
+}
+
+def AArch64MIR_bfmlalt : AArch64MIR_TargetOp<"bfmlalt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMLALT BFMLALTIdx BFMLALT_ZZZ BFMLALT_ZZZI
+}
+
+def AArch64MIR_bfmlal : AArch64MIR_TargetOp<"bfmlal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMLAL_MZZI_HtoS BFMLAL_MZZ_HtoS BFMLAL_VG2_M2Z2Z_HtoS BFMLAL_VG2_M2ZZI_HtoS BFMLAL_VG2_M2ZZ_HtoS BFMLAL_VG4_M4Z4Z_HtoS BFMLAL_VG4_M4ZZI_HtoS BFMLAL_VG4_M4ZZ_HtoS
+}
+
+def AArch64MIR_bfmla : AArch64MIR_TargetOp<"bfmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMLA_VG2_M2Z2Z BFMLA_VG2_M2ZZ BFMLA_VG2_M2ZZI BFMLA_VG4_M4Z4Z BFMLA_VG4_M4ZZ BFMLA_VG4_M4ZZI BFMLA_ZPmZZ BFMLA_ZZZI
+}
+
+def AArch64MIR_bfmlslb : AArch64MIR_TargetOp<"bfmlslb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMLSLB_ZZZI_S BFMLSLB_ZZZ_S
+}
+
+def AArch64MIR_bfmlslt : AArch64MIR_TargetOp<"bfmlslt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMLSLT_ZZZI_S BFMLSLT_ZZZ_S
+}
+
+def AArch64MIR_bfmlsl : AArch64MIR_TargetOp<"bfmlsl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMLSL_MZZI_HtoS BFMLSL_MZZ_HtoS BFMLSL_VG2_M2Z2Z_HtoS BFMLSL_VG2_M2ZZI_HtoS BFMLSL_VG2_M2ZZ_HtoS BFMLSL_VG4_M4Z4Z_HtoS BFMLSL_VG4_M4ZZI_HtoS BFMLSL_VG4_M4ZZ_HtoS
+}
+
+def AArch64MIR_bfmls : AArch64MIR_TargetOp<"bfmls", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMLS_VG2_M2Z2Z BFMLS_VG2_M2ZZ BFMLS_VG2_M2ZZI BFMLS_VG4_M4Z4Z BFMLS_VG4_M4ZZ BFMLS_VG4_M4ZZI BFMLS_ZPmZZ BFMLS_ZZZI
+}
+
+def AArch64MIR_bfmmla : AArch64MIR_TargetOp<"bfmmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMMLA BFMMLA_ZZZ_H BFMMLA_ZZZ_HtoS
+}
+
+def AArch64MIR_bfmop4a : AArch64MIR_TargetOp<"bfmop4a", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMOP4A_M2Z2Z_H BFMOP4A_M2Z2Z_S BFMOP4A_M2ZZ_H BFMOP4A_M2ZZ_S BFMOP4A_MZ2Z_H BFMOP4A_MZ2Z_S BFMOP4A_MZZ_H BFMOP4A_MZZ_S
+}
+
+def AArch64MIR_bfmop4s : AArch64MIR_TargetOp<"bfmop4s", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMOP4S_M2Z2Z_H BFMOP4S_M2Z2Z_S BFMOP4S_M2ZZ_H BFMOP4S_M2ZZ_S BFMOP4S_MZ2Z_H BFMOP4S_MZ2Z_S BFMOP4S_MZZ_H BFMOP4S_MZZ_S
+}
+
+def AArch64MIR_bfmopa : AArch64MIR_TargetOp<"bfmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMOPA_MPPZZ BFMOPA_MPPZZ_H
+}
+
+def AArch64MIR_bfmops : AArch64MIR_TargetOp<"bfmops", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMOPS_MPPZZ BFMOPS_MPPZZ_H
+}
+
+def AArch64MIR_bfmul : AArch64MIR_TargetOp<"bfmul", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMUL_2Z2Z BFMUL_2ZZ BFMUL_4Z4Z BFMUL_4ZZ BFMUL_ZPmZ BFMUL_ZZZ BFMUL_ZZZI
+}
+
+def AArch64MIR_bfm : AArch64MIR_TargetOp<"bfm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFMWri BFMXri
+}
+
+def AArch64MIR_bfscale : AArch64MIR_TargetOp<"bfscale", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFSCALE_2Z2Z BFSCALE_2ZZ BFSCALE_4Z4Z BFSCALE_4ZZ BFSCALE_ZPmZ
+}
+
+def AArch64MIR_bfsub : AArch64MIR_TargetOp<"bfsub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFSUB_VG2_M2Z_H BFSUB_VG4_M4Z_H BFSUB_ZPmZ BFSUB_ZZZ
+}
+
+def AArch64MIR_bftmopa : AArch64MIR_TargetOp<"bftmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFTMOPA_M2ZZZI_HtoH BFTMOPA_M2ZZZI_HtoS
+}
+
+def AArch64MIR_bfvdot : AArch64MIR_TargetOp<"bfvdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BFVDOT_VG2_M2ZZI_HtoS
+}
+
+def AArch64MIR_bgrp : AArch64MIR_TargetOp<"bgrp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BGRP_ZZZ_B BGRP_ZZZ_D BGRP_ZZZ_H BGRP_ZZZ_S
+}
+
+def AArch64MIR_bics : AArch64MIR_TargetOp<"bics", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BICSWrs BICSXrs BICS_PPzPP
+}
+
+def AArch64MIR_bic : AArch64MIR_TargetOp<"bic", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BICWrs BICXrs BIC_PPzPP BIC_ZPmZ_B BIC_ZPmZ_D BIC_ZPmZ_H BIC_ZPmZ_S BIC_ZZZ BICv2i32 BICv4i16 BICv4i32 BICv8i8 BICv8i16 BICv16i8
+}
+
+def AArch64MIR_bif : AArch64MIR_TargetOp<"bif", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BIFv8i8 BIFv16i8
+}
+
+def AArch64MIR_bit : AArch64MIR_TargetOp<"bit", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BITv8i8 BITv16i8
+}
+
+def AArch64MIR_bl : AArch64MIR_TargetOp<"bl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BL
+}
+
+def AArch64MIR_blr : AArch64MIR_TargetOp<"blr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BLR
+}
+
+def AArch64MIR_blraa : AArch64MIR_TargetOp<"blraa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BLRAA
+}
+
+def AArch64MIR_blraaz : AArch64MIR_TargetOp<"blraaz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BLRAAZ
+}
+
+def AArch64MIR_blrab : AArch64MIR_TargetOp<"blrab", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BLRAB
+}
+
+def AArch64MIR_blrabz : AArch64MIR_TargetOp<"blrabz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BLRABZ
+}
+
+def AArch64MIR_bmopa : AArch64MIR_TargetOp<"bmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BMOPA_MPPZZ_S
+}
+
+def AArch64MIR_bmops : AArch64MIR_TargetOp<"bmops", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BMOPS_MPPZZ_S
+}
+
+def AArch64MIR_br : AArch64MIR_TargetOp<"br", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BR
+}
+
+def AArch64MIR_braa : AArch64MIR_TargetOp<"braa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRAA
+}
+
+def AArch64MIR_braaz : AArch64MIR_TargetOp<"braaz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRAAZ
+}
+
+def AArch64MIR_brab : AArch64MIR_TargetOp<"brab", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRAB
+}
+
+def AArch64MIR_brabz : AArch64MIR_TargetOp<"brabz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRABZ
+}
+
+def AArch64MIR_brk : AArch64MIR_TargetOp<"brk", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRK
+}
+
+def AArch64MIR_brkas : AArch64MIR_TargetOp<"brkas", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKAS_PPzP
+}
+
+def AArch64MIR_brka : AArch64MIR_TargetOp<"brka", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKA_PPmP BRKA_PPzP
+}
+
+def AArch64MIR_brkbs : AArch64MIR_TargetOp<"brkbs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKBS_PPzP
+}
+
+def AArch64MIR_brkb : AArch64MIR_TargetOp<"brkb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKB_PPmP BRKB_PPzP
+}
+
+def AArch64MIR_brkns : AArch64MIR_TargetOp<"brkns", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKNS_PPzP
+}
+
+def AArch64MIR_brkn : AArch64MIR_TargetOp<"brkn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKN_PPzP
+}
+
+def AArch64MIR_brkpas : AArch64MIR_TargetOp<"brkpas", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKPAS_PPzPP
+}
+
+def AArch64MIR_brkpa : AArch64MIR_TargetOp<"brkpa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKPA_PPzPP
+}
+
+def AArch64MIR_brkpbs : AArch64MIR_TargetOp<"brkpbs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKPBS_PPzPP
+}
+
+def AArch64MIR_brkpb : AArch64MIR_TargetOp<"brkpb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BRKPB_PPzPP
+}
+
+def AArch64MIR_bsl1n : AArch64MIR_TargetOp<"bsl1n", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BSL1N_ZZZZ
+}
+
+def AArch64MIR_bsl2n : AArch64MIR_TargetOp<"bsl2n", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BSL2N_ZZZZ
+}
+
+def AArch64MIR_bsl : AArch64MIR_TargetOp<"bsl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: BSL_ZZZZ BSLv8i8 BSLv16i8
+}
+
+def AArch64MIR_b_cond : AArch64MIR_TargetOp<"b_cond", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: Bcc
+}
+
+def AArch64MIR_cadd : AArch64MIR_TargetOp<"cadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CADD_ZZI_B CADD_ZZI_D CADD_ZZI_H CADD_ZZI_S
+}
+
+def AArch64MIR_casab : AArch64MIR_TargetOp<"casab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASAB
+}
+
+def AArch64MIR_casah : AArch64MIR_TargetOp<"casah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASAH
+}
+
+def AArch64MIR_casalb : AArch64MIR_TargetOp<"casalb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASALB
+}
+
+def AArch64MIR_casalh : AArch64MIR_TargetOp<"casalh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASALH
+}
+
+def AArch64MIR_casalt : AArch64MIR_TargetOp<"casalt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASALTX
+}
+
+def AArch64MIR_casal : AArch64MIR_TargetOp<"casal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASALW CASALX
+}
+
+def AArch64MIR_casat : AArch64MIR_TargetOp<"casat", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASATX
+}
+
+def AArch64MIR_casa : AArch64MIR_TargetOp<"casa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASAW CASAX
+}
+
+def AArch64MIR_casb : AArch64MIR_TargetOp<"casb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASB
+}
+
+def AArch64MIR_cash : AArch64MIR_TargetOp<"cash", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASH
+}
+
+def AArch64MIR_caslb : AArch64MIR_TargetOp<"caslb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASLB
+}
+
+def AArch64MIR_caslh : AArch64MIR_TargetOp<"caslh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASLH
+}
+
+def AArch64MIR_caslt : AArch64MIR_TargetOp<"caslt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASLTX
+}
+
+def AArch64MIR_casl : AArch64MIR_TargetOp<"casl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASLW CASLX
+}
+
+def AArch64MIR_caspalt : AArch64MIR_TargetOp<"caspalt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASPALTX
+}
+
+def AArch64MIR_caspal : AArch64MIR_TargetOp<"caspal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASPALW CASPALX
+}
+
+def AArch64MIR_caspat : AArch64MIR_TargetOp<"caspat", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASPATX
+}
+
+def AArch64MIR_caspa : AArch64MIR_TargetOp<"caspa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASPAW CASPAX
+}
+
+def AArch64MIR_casplt : AArch64MIR_TargetOp<"casplt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASPLTX
+}
+
+def AArch64MIR_caspl : AArch64MIR_TargetOp<"caspl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASPLW CASPLX
+}
+
+def AArch64MIR_caspt : AArch64MIR_TargetOp<"caspt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASPTX
+}
+
+def AArch64MIR_casp : AArch64MIR_TargetOp<"casp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASPW CASPX
+}
+
+def AArch64MIR_cast : AArch64MIR_TargetOp<"cast", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASTX
+}
+
+def AArch64MIR_cas : AArch64MIR_TargetOp<"cas", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CASW CASX
+}
+
+def AArch64MIR_cbbeq : AArch64MIR_TargetOp<"cbbeq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBBEQWrr
+}
+
+def AArch64MIR_cbbge : AArch64MIR_TargetOp<"cbbge", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBBGEWrr
+}
+
+def AArch64MIR_cbbgt : AArch64MIR_TargetOp<"cbbgt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBBGTWrr
+}
+
+def AArch64MIR_cbbhi : AArch64MIR_TargetOp<"cbbhi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBBHIWrr
+}
+
+def AArch64MIR_cbbhs : AArch64MIR_TargetOp<"cbbhs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBBHSWrr
+}
+
+def AArch64MIR_cbbne : AArch64MIR_TargetOp<"cbbne", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBBNEWrr
+}
+
+def AArch64MIR_cbeq : AArch64MIR_TargetOp<"cbeq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBEQWri CBEQWrr CBEQXri CBEQXrr
+}
+
+def AArch64MIR_cbge : AArch64MIR_TargetOp<"cbge", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBGEWrr CBGEXrr
+}
+
+def AArch64MIR_cbgt : AArch64MIR_TargetOp<"cbgt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBGTWri CBGTWrr CBGTXri CBGTXrr
+}
+
+def AArch64MIR_cbheq : AArch64MIR_TargetOp<"cbheq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBHEQWrr
+}
+
+def AArch64MIR_cbhge : AArch64MIR_TargetOp<"cbhge", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBHGEWrr
+}
+
+def AArch64MIR_cbhgt : AArch64MIR_TargetOp<"cbhgt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBHGTWrr
+}
+
+def AArch64MIR_cbhhi : AArch64MIR_TargetOp<"cbhhi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBHHIWrr
+}
+
+def AArch64MIR_cbhhs : AArch64MIR_TargetOp<"cbhhs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBHHSWrr
+}
+
+def AArch64MIR_cbhi : AArch64MIR_TargetOp<"cbhi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBHIWri CBHIWrr CBHIXri CBHIXrr
+}
+
+def AArch64MIR_cbhne : AArch64MIR_TargetOp<"cbhne", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBHNEWrr
+}
+
+def AArch64MIR_cbhs : AArch64MIR_TargetOp<"cbhs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBHSWrr CBHSXrr
+}
+
+def AArch64MIR_cblo : AArch64MIR_TargetOp<"cblo", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBLOWri CBLOXri
+}
+
+def AArch64MIR_cblt : AArch64MIR_TargetOp<"cblt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBLTWri CBLTXri
+}
+
+def AArch64MIR_cbne : AArch64MIR_TargetOp<"cbne", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBNEWri CBNEWrr CBNEXri CBNEXrr
+}
+
+def AArch64MIR_cbnz : AArch64MIR_TargetOp<"cbnz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBNZW CBNZX
+}
+
+def AArch64MIR_cbz : AArch64MIR_TargetOp<"cbz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CBZW CBZX
+}
+
+def AArch64MIR_ccmn : AArch64MIR_TargetOp<"ccmn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CCMNWi CCMNWr CCMNXi CCMNXr
+}
+
+def AArch64MIR_ccmp : AArch64MIR_TargetOp<"ccmp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CCMPWi CCMPWr CCMPXi CCMPXr
+}
+
+def AArch64MIR_cdot : AArch64MIR_TargetOp<"cdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CDOT_ZZZI_D CDOT_ZZZI_S CDOT_ZZZ_D CDOT_ZZZ_S
+}
+
+def AArch64MIR_cfinv : AArch64MIR_TargetOp<"cfinv", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CFINV
+}
+
+def AArch64MIR_clasta : AArch64MIR_TargetOp<"clasta", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CLASTA_RPZ_B CLASTA_RPZ_D CLASTA_RPZ_H CLASTA_RPZ_S CLASTA_VPZ_B CLASTA_VPZ_D CLASTA_VPZ_H CLASTA_VPZ_S CLASTA_ZPZ_B CLASTA_ZPZ_D CLASTA_ZPZ_H CLASTA_ZPZ_S
+}
+
+def AArch64MIR_clastb : AArch64MIR_TargetOp<"clastb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CLASTB_RPZ_B CLASTB_RPZ_D CLASTB_RPZ_H CLASTB_RPZ_S CLASTB_VPZ_B CLASTB_VPZ_D CLASTB_VPZ_H CLASTB_VPZ_S CLASTB_ZPZ_B CLASTB_ZPZ_D CLASTB_ZPZ_H CLASTB_ZPZ_S
+}
+
+def AArch64MIR_clrex : AArch64MIR_TargetOp<"clrex", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CLREX
+}
+
+def AArch64MIR_cls : AArch64MIR_TargetOp<"cls", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CLSWr CLSXr CLS_ZPmZ_B CLS_ZPmZ_D CLS_ZPmZ_H CLS_ZPmZ_S CLS_ZPzZ_B CLS_ZPzZ_D CLS_ZPzZ_H CLS_ZPzZ_S CLSv2i32 CLSv4i16 CLSv4i32 CLSv8i8 CLSv8i16 CLSv16i8
+}
+
+def AArch64MIR_clz : AArch64MIR_TargetOp<"clz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CLZWr CLZXr CLZ_ZPmZ_B CLZ_ZPmZ_D CLZ_ZPmZ_H CLZ_ZPmZ_S CLZ_ZPzZ_B CLZ_ZPzZ_D CLZ_ZPzZ_H CLZ_ZPzZ_S CLZv2i32 CLZv4i16 CLZv4i32 CLZv8i8 CLZv8i16 CLZv16i8
+}
+
+def AArch64MIR_cmeq : AArch64MIR_TargetOp<"cmeq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMEQv1i64 CMEQv1i64rz CMEQv2i32 CMEQv2i32rz CMEQv2i64 CMEQv2i64rz CMEQv4i16 CMEQv4i16rz CMEQv4i32 CMEQv4i32rz CMEQv8i8 CMEQv8i8rz CMEQv8i16 CMEQv8i16rz CMEQv16i8 CMEQv16i8rz
+}
+
+def AArch64MIR_cmge : AArch64MIR_TargetOp<"cmge", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMGEv1i64 CMGEv1i64rz CMGEv2i32 CMGEv2i32rz CMGEv2i64 CMGEv2i64rz CMGEv4i16 CMGEv4i16rz CMGEv4i32 CMGEv4i32rz CMGEv8i8 CMGEv8i8rz CMGEv8i16 CMGEv8i16rz CMGEv16i8 CMGEv16i8rz
+}
+
+def AArch64MIR_cmgt : AArch64MIR_TargetOp<"cmgt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMGTv1i64 CMGTv1i64rz CMGTv2i32 CMGTv2i32rz CMGTv2i64 CMGTv2i64rz CMGTv4i16 CMGTv4i16rz CMGTv4i32 CMGTv4i32rz CMGTv8i8 CMGTv8i8rz CMGTv8i16 CMGTv8i16rz CMGTv16i8 CMGTv16i8rz
+}
+
+def AArch64MIR_cmhi : AArch64MIR_TargetOp<"cmhi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMHIv1i64 CMHIv2i32 CMHIv2i64 CMHIv4i16 CMHIv4i32 CMHIv8i8 CMHIv8i16 CMHIv16i8
+}
+
+def AArch64MIR_cmhs : AArch64MIR_TargetOp<"cmhs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMHSv1i64 CMHSv2i32 CMHSv2i64 CMHSv4i16 CMHSv4i32 CMHSv8i8 CMHSv8i16 CMHSv16i8
+}
+
+def AArch64MIR_cmla : AArch64MIR_TargetOp<"cmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMLA_ZZZI_H CMLA_ZZZI_S CMLA_ZZZ_B CMLA_ZZZ_D CMLA_ZZZ_H CMLA_ZZZ_S
+}
+
+def AArch64MIR_cmle : AArch64MIR_TargetOp<"cmle", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMLEv1i64rz CMLEv2i32rz CMLEv2i64rz CMLEv4i16rz CMLEv4i32rz CMLEv8i8rz CMLEv8i16rz CMLEv16i8rz
+}
+
+def AArch64MIR_cmlt : AArch64MIR_TargetOp<"cmlt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMLTv1i64rz CMLTv2i32rz CMLTv2i64rz CMLTv4i16rz CMLTv4i32rz CMLTv8i8rz CMLTv8i16rz CMLTv16i8rz
+}
+
+def AArch64MIR_cmpeq : AArch64MIR_TargetOp<"cmpeq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPEQ_PPzZI_B CMPEQ_PPzZI_D CMPEQ_PPzZI_H CMPEQ_PPzZI_S CMPEQ_PPzZZ_B CMPEQ_PPzZZ_D CMPEQ_PPzZZ_H CMPEQ_PPzZZ_S CMPEQ_WIDE_PPzZZ_B CMPEQ_WIDE_PPzZZ_H CMPEQ_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmpge : AArch64MIR_TargetOp<"cmpge", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPGE_PPzZI_B CMPGE_PPzZI_D CMPGE_PPzZI_H CMPGE_PPzZI_S CMPGE_PPzZZ_B CMPGE_PPzZZ_D CMPGE_PPzZZ_H CMPGE_PPzZZ_S CMPGE_WIDE_PPzZZ_B CMPGE_WIDE_PPzZZ_H CMPGE_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmpgt : AArch64MIR_TargetOp<"cmpgt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPGT_PPzZI_B CMPGT_PPzZI_D CMPGT_PPzZI_H CMPGT_PPzZI_S CMPGT_PPzZZ_B CMPGT_PPzZZ_D CMPGT_PPzZZ_H CMPGT_PPzZZ_S CMPGT_WIDE_PPzZZ_B CMPGT_WIDE_PPzZZ_H CMPGT_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmphi : AArch64MIR_TargetOp<"cmphi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPHI_PPzZI_B CMPHI_PPzZI_D CMPHI_PPzZI_H CMPHI_PPzZI_S CMPHI_PPzZZ_B CMPHI_PPzZZ_D CMPHI_PPzZZ_H CMPHI_PPzZZ_S CMPHI_WIDE_PPzZZ_B CMPHI_WIDE_PPzZZ_H CMPHI_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmphs : AArch64MIR_TargetOp<"cmphs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPHS_PPzZI_B CMPHS_PPzZI_D CMPHS_PPzZI_H CMPHS_PPzZI_S CMPHS_PPzZZ_B CMPHS_PPzZZ_D CMPHS_PPzZZ_H CMPHS_PPzZZ_S CMPHS_WIDE_PPzZZ_B CMPHS_WIDE_PPzZZ_H CMPHS_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmple : AArch64MIR_TargetOp<"cmple", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPLE_PPzZI_B CMPLE_PPzZI_D CMPLE_PPzZI_H CMPLE_PPzZI_S CMPLE_WIDE_PPzZZ_B CMPLE_WIDE_PPzZZ_H CMPLE_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmplo : AArch64MIR_TargetOp<"cmplo", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPLO_PPzZI_B CMPLO_PPzZI_D CMPLO_PPzZI_H CMPLO_PPzZI_S CMPLO_WIDE_PPzZZ_B CMPLO_WIDE_PPzZZ_H CMPLO_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmpls : AArch64MIR_TargetOp<"cmpls", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPLS_PPzZI_B CMPLS_PPzZI_D CMPLS_PPzZI_H CMPLS_PPzZI_S CMPLS_WIDE_PPzZZ_B CMPLS_WIDE_PPzZZ_H CMPLS_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmplt : AArch64MIR_TargetOp<"cmplt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPLT_PPzZI_B CMPLT_PPzZI_D CMPLT_PPzZI_H CMPLT_PPzZI_S CMPLT_WIDE_PPzZZ_B CMPLT_WIDE_PPzZZ_H CMPLT_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmpne : AArch64MIR_TargetOp<"cmpne", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMPNE_PPzZI_B CMPNE_PPzZI_D CMPNE_PPzZI_H CMPNE_PPzZI_S CMPNE_PPzZZ_B CMPNE_PPzZZ_D CMPNE_PPzZZ_H CMPNE_PPzZZ_S CMPNE_WIDE_PPzZZ_B CMPNE_WIDE_PPzZZ_H CMPNE_WIDE_PPzZZ_S
+}
+
+def AArch64MIR_cmtst : AArch64MIR_TargetOp<"cmtst", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CMTSTv1i64 CMTSTv2i32 CMTSTv2i64 CMTSTv4i16 CMTSTv4i32 CMTSTv8i8 CMTSTv8i16 CMTSTv16i8
+}
+
+def AArch64MIR_cnot : AArch64MIR_TargetOp<"cnot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CNOT_ZPmZ_B CNOT_ZPmZ_D CNOT_ZPmZ_H CNOT_ZPmZ_S CNOT_ZPzZ_B CNOT_ZPzZ_D CNOT_ZPzZ_H CNOT_ZPzZ_S
+}
+
+def AArch64MIR_cntb : AArch64MIR_TargetOp<"cntb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CNTB_XPiI
+}
+
+def AArch64MIR_cntd : AArch64MIR_TargetOp<"cntd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CNTD_XPiI
+}
+
+def AArch64MIR_cnth : AArch64MIR_TargetOp<"cnth", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CNTH_XPiI
+}
+
+def AArch64MIR_cntp : AArch64MIR_TargetOp<"cntp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CNTP_XCI_B CNTP_XCI_D CNTP_XCI_H CNTP_XCI_S CNTP_XPP_B CNTP_XPP_D CNTP_XPP_H CNTP_XPP_S
+}
+
+def AArch64MIR_cntw : AArch64MIR_TargetOp<"cntw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CNTW_XPiI
+}
+
+def AArch64MIR_cnt : AArch64MIR_TargetOp<"cnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CNTWr CNTXr CNT_ZPmZ_B CNT_ZPmZ_D CNT_ZPmZ_H CNT_ZPmZ_S CNT_ZPzZ_B CNT_ZPzZ_D CNT_ZPzZ_H CNT_ZPzZ_S CNTv8i8 CNTv16i8
+}
+
+def AArch64MIR_compact : AArch64MIR_TargetOp<"compact", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: COMPACT_ZPZ_B COMPACT_ZPZ_D COMPACT_ZPZ_H COMPACT_ZPZ_S
+}
+
+def AArch64MIR_cpye : AArch64MIR_TargetOp<"cpye", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYE
+}
+
+def AArch64MIR_cpyen : AArch64MIR_TargetOp<"cpyen", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYEN
+}
+
+def AArch64MIR_cpyern : AArch64MIR_TargetOp<"cpyern", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYERN
+}
+
+def AArch64MIR_cpyert : AArch64MIR_TargetOp<"cpyert", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYERT
+}
+
+def AArch64MIR_cpyertn : AArch64MIR_TargetOp<"cpyertn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYERTN
+}
+
+def AArch64MIR_cpyertrn : AArch64MIR_TargetOp<"cpyertrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYERTRN
+}
+
+def AArch64MIR_cpyertwn : AArch64MIR_TargetOp<"cpyertwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYERTWN
+}
+
+def AArch64MIR_cpyet : AArch64MIR_TargetOp<"cpyet", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYET
+}
+
+def AArch64MIR_cpyetn : AArch64MIR_TargetOp<"cpyetn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYETN
+}
+
+def AArch64MIR_cpyetrn : AArch64MIR_TargetOp<"cpyetrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYETRN
+}
+
+def AArch64MIR_cpyetwn : AArch64MIR_TargetOp<"cpyetwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYETWN
+}
+
+def AArch64MIR_cpyewn : AArch64MIR_TargetOp<"cpyewn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYEWN
+}
+
+def AArch64MIR_cpyewt : AArch64MIR_TargetOp<"cpyewt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYEWT
+}
+
+def AArch64MIR_cpyewtn : AArch64MIR_TargetOp<"cpyewtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYEWTN
+}
+
+def AArch64MIR_cpyewtrn : AArch64MIR_TargetOp<"cpyewtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYEWTRN
+}
+
+def AArch64MIR_cpyewtwn : AArch64MIR_TargetOp<"cpyewtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYEWTWN
+}
+
+def AArch64MIR_cpyfe : AArch64MIR_TargetOp<"cpyfe", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFE
+}
+
+def AArch64MIR_cpyfen : AArch64MIR_TargetOp<"cpyfen", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFEN
+}
+
+def AArch64MIR_cpyfern : AArch64MIR_TargetOp<"cpyfern", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFERN
+}
+
+def AArch64MIR_cpyfert : AArch64MIR_TargetOp<"cpyfert", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFERT
+}
+
+def AArch64MIR_cpyfertn : AArch64MIR_TargetOp<"cpyfertn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFERTN
+}
+
+def AArch64MIR_cpyfertrn : AArch64MIR_TargetOp<"cpyfertrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFERTRN
+}
+
+def AArch64MIR_cpyfertwn : AArch64MIR_TargetOp<"cpyfertwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFERTWN
+}
+
+def AArch64MIR_cpyfet : AArch64MIR_TargetOp<"cpyfet", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFET
+}
+
+def AArch64MIR_cpyfetn : AArch64MIR_TargetOp<"cpyfetn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFETN
+}
+
+def AArch64MIR_cpyfetrn : AArch64MIR_TargetOp<"cpyfetrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFETRN
+}
+
+def AArch64MIR_cpyfetwn : AArch64MIR_TargetOp<"cpyfetwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFETWN
+}
+
+def AArch64MIR_cpyfewn : AArch64MIR_TargetOp<"cpyfewn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFEWN
+}
+
+def AArch64MIR_cpyfewt : AArch64MIR_TargetOp<"cpyfewt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFEWT
+}
+
+def AArch64MIR_cpyfewtn : AArch64MIR_TargetOp<"cpyfewtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFEWTN
+}
+
+def AArch64MIR_cpyfewtrn : AArch64MIR_TargetOp<"cpyfewtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFEWTRN
+}
+
+def AArch64MIR_cpyfewtwn : AArch64MIR_TargetOp<"cpyfewtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFEWTWN
+}
+
+def AArch64MIR_cpyfm : AArch64MIR_TargetOp<"cpyfm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFM
+}
+
+def AArch64MIR_cpyfmn : AArch64MIR_TargetOp<"cpyfmn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMN
+}
+
+def AArch64MIR_cpyfmrn : AArch64MIR_TargetOp<"cpyfmrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMRN
+}
+
+def AArch64MIR_cpyfmrt : AArch64MIR_TargetOp<"cpyfmrt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMRT
+}
+
+def AArch64MIR_cpyfmrtn : AArch64MIR_TargetOp<"cpyfmrtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMRTN
+}
+
+def AArch64MIR_cpyfmrtrn : AArch64MIR_TargetOp<"cpyfmrtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMRTRN
+}
+
+def AArch64MIR_cpyfmrtwn : AArch64MIR_TargetOp<"cpyfmrtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMRTWN
+}
+
+def AArch64MIR_cpyfmt : AArch64MIR_TargetOp<"cpyfmt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMT
+}
+
+def AArch64MIR_cpyfmtn : AArch64MIR_TargetOp<"cpyfmtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMTN
+}
+
+def AArch64MIR_cpyfmtrn : AArch64MIR_TargetOp<"cpyfmtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMTRN
+}
+
+def AArch64MIR_cpyfmtwn : AArch64MIR_TargetOp<"cpyfmtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMTWN
+}
+
+def AArch64MIR_cpyfmwn : AArch64MIR_TargetOp<"cpyfmwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMWN
+}
+
+def AArch64MIR_cpyfmwt : AArch64MIR_TargetOp<"cpyfmwt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMWT
+}
+
+def AArch64MIR_cpyfmwtn : AArch64MIR_TargetOp<"cpyfmwtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMWTN
+}
+
+def AArch64MIR_cpyfmwtrn : AArch64MIR_TargetOp<"cpyfmwtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMWTRN
+}
+
+def AArch64MIR_cpyfmwtwn : AArch64MIR_TargetOp<"cpyfmwtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFMWTWN
+}
+
+def AArch64MIR_cpyfp : AArch64MIR_TargetOp<"cpyfp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFP
+}
+
+def AArch64MIR_cpyfpn : AArch64MIR_TargetOp<"cpyfpn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPN
+}
+
+def AArch64MIR_cpyfprn : AArch64MIR_TargetOp<"cpyfprn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPRN
+}
+
+def AArch64MIR_cpyfprt : AArch64MIR_TargetOp<"cpyfprt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPRT
+}
+
+def AArch64MIR_cpyfprtn : AArch64MIR_TargetOp<"cpyfprtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPRTN
+}
+
+def AArch64MIR_cpyfprtrn : AArch64MIR_TargetOp<"cpyfprtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPRTRN
+}
+
+def AArch64MIR_cpyfprtwn : AArch64MIR_TargetOp<"cpyfprtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPRTWN
+}
+
+def AArch64MIR_cpyfpt : AArch64MIR_TargetOp<"cpyfpt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPT
+}
+
+def AArch64MIR_cpyfptn : AArch64MIR_TargetOp<"cpyfptn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPTN
+}
+
+def AArch64MIR_cpyfptrn : AArch64MIR_TargetOp<"cpyfptrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPTRN
+}
+
+def AArch64MIR_cpyfptwn : AArch64MIR_TargetOp<"cpyfptwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPTWN
+}
+
+def AArch64MIR_cpyfpwn : AArch64MIR_TargetOp<"cpyfpwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPWN
+}
+
+def AArch64MIR_cpyfpwt : AArch64MIR_TargetOp<"cpyfpwt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPWT
+}
+
+def AArch64MIR_cpyfpwtn : AArch64MIR_TargetOp<"cpyfpwtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPWTN
+}
+
+def AArch64MIR_cpyfpwtrn : AArch64MIR_TargetOp<"cpyfpwtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPWTRN
+}
+
+def AArch64MIR_cpyfpwtwn : AArch64MIR_TargetOp<"cpyfpwtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYFPWTWN
+}
+
+def AArch64MIR_cpym : AArch64MIR_TargetOp<"cpym", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYM
+}
+
+def AArch64MIR_cpymn : AArch64MIR_TargetOp<"cpymn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMN
+}
+
+def AArch64MIR_cpymrn : AArch64MIR_TargetOp<"cpymrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMRN
+}
+
+def AArch64MIR_cpymrt : AArch64MIR_TargetOp<"cpymrt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMRT
+}
+
+def AArch64MIR_cpymrtn : AArch64MIR_TargetOp<"cpymrtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMRTN
+}
+
+def AArch64MIR_cpymrtrn : AArch64MIR_TargetOp<"cpymrtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMRTRN
+}
+
+def AArch64MIR_cpymrtwn : AArch64MIR_TargetOp<"cpymrtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMRTWN
+}
+
+def AArch64MIR_cpymt : AArch64MIR_TargetOp<"cpymt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMT
+}
+
+def AArch64MIR_cpymtn : AArch64MIR_TargetOp<"cpymtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMTN
+}
+
+def AArch64MIR_cpymtrn : AArch64MIR_TargetOp<"cpymtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMTRN
+}
+
+def AArch64MIR_cpymtwn : AArch64MIR_TargetOp<"cpymtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMTWN
+}
+
+def AArch64MIR_cpymwn : AArch64MIR_TargetOp<"cpymwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMWN
+}
+
+def AArch64MIR_cpymwt : AArch64MIR_TargetOp<"cpymwt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMWT
+}
+
+def AArch64MIR_cpymwtn : AArch64MIR_TargetOp<"cpymwtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMWTN
+}
+
+def AArch64MIR_cpymwtrn : AArch64MIR_TargetOp<"cpymwtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMWTRN
+}
+
+def AArch64MIR_cpymwtwn : AArch64MIR_TargetOp<"cpymwtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYMWTWN
+}
+
+def AArch64MIR_cpyp : AArch64MIR_TargetOp<"cpyp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYP
+}
+
+def AArch64MIR_cpypn : AArch64MIR_TargetOp<"cpypn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPN
+}
+
+def AArch64MIR_cpyprn : AArch64MIR_TargetOp<"cpyprn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPRN
+}
+
+def AArch64MIR_cpyprt : AArch64MIR_TargetOp<"cpyprt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPRT
+}
+
+def AArch64MIR_cpyprtn : AArch64MIR_TargetOp<"cpyprtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPRTN
+}
+
+def AArch64MIR_cpyprtrn : AArch64MIR_TargetOp<"cpyprtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPRTRN
+}
+
+def AArch64MIR_cpyprtwn : AArch64MIR_TargetOp<"cpyprtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPRTWN
+}
+
+def AArch64MIR_cpypt : AArch64MIR_TargetOp<"cpypt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPT
+}
+
+def AArch64MIR_cpyptn : AArch64MIR_TargetOp<"cpyptn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPTN
+}
+
+def AArch64MIR_cpyptrn : AArch64MIR_TargetOp<"cpyptrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPTRN
+}
+
+def AArch64MIR_cpyptwn : AArch64MIR_TargetOp<"cpyptwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPTWN
+}
+
+def AArch64MIR_cpypwn : AArch64MIR_TargetOp<"cpypwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPWN
+}
+
+def AArch64MIR_cpypwt : AArch64MIR_TargetOp<"cpypwt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPWT
+}
+
+def AArch64MIR_cpypwtn : AArch64MIR_TargetOp<"cpypwtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPWTN
+}
+
+def AArch64MIR_cpypwtrn : AArch64MIR_TargetOp<"cpypwtrn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPWTRN
+}
+
+def AArch64MIR_cpypwtwn : AArch64MIR_TargetOp<"cpypwtwn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPYPWTWN
+}
+
+def AArch64MIR_cpy : AArch64MIR_TargetOp<"cpy", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CPY_ZPmI_B CPY_ZPmI_D CPY_ZPmI_H CPY_ZPmI_S CPY_ZPmR_B CPY_ZPmR_D CPY_ZPmR_H CPY_ZPmR_S CPY_ZPmV_B CPY_ZPmV_D CPY_ZPmV_H CPY_ZPmV_S CPY_ZPzI_B CPY_ZPzI_D CPY_ZPzI_H CPY_ZPzI_S
+}
+
+def AArch64MIR_crc32b : AArch64MIR_TargetOp<"crc32b", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CRC32Brr
+}
+
+def AArch64MIR_crc32cb : AArch64MIR_TargetOp<"crc32cb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CRC32CBrr
+}
+
+def AArch64MIR_crc32ch : AArch64MIR_TargetOp<"crc32ch", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CRC32CHrr
+}
+
+def AArch64MIR_crc32cw : AArch64MIR_TargetOp<"crc32cw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CRC32CWrr
+}
+
+def AArch64MIR_crc32cx : AArch64MIR_TargetOp<"crc32cx", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CRC32CXrr
+}
+
+def AArch64MIR_crc32h : AArch64MIR_TargetOp<"crc32h", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CRC32Hrr
+}
+
+def AArch64MIR_crc32w : AArch64MIR_TargetOp<"crc32w", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CRC32Wrr
+}
+
+def AArch64MIR_crc32x : AArch64MIR_TargetOp<"crc32x", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CRC32Xrr
+}
+
+def AArch64MIR_csel : AArch64MIR_TargetOp<"csel", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CSELWr CSELXr
+}
+
+def AArch64MIR_csinc : AArch64MIR_TargetOp<"csinc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CSINCWr CSINCXr
+}
+
+def AArch64MIR_csinv : AArch64MIR_TargetOp<"csinv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CSINVWr CSINVXr
+}
+
+def AArch64MIR_csneg : AArch64MIR_TargetOp<"csneg", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CSNEGWr CSNEGXr
+}
+
+def AArch64MIR_ctermeq : AArch64MIR_TargetOp<"ctermeq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CTERMEQ_WW CTERMEQ_XX
+}
+
+def AArch64MIR_ctermne : AArch64MIR_TargetOp<"ctermne", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CTERMNE_WW CTERMNE_XX
+}
+
+def AArch64MIR_ctz : AArch64MIR_TargetOp<"ctz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: CTZWr CTZXr
+}
+
+def AArch64MIR_dcps1 : AArch64MIR_TargetOp<"dcps1", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DCPS1
+}
+
+def AArch64MIR_dcps2 : AArch64MIR_TargetOp<"dcps2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DCPS2
+}
+
+def AArch64MIR_dcps3 : AArch64MIR_TargetOp<"dcps3", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DCPS3
+}
+
+def AArch64MIR_decb : AArch64MIR_TargetOp<"decb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DECB_XPiI
+}
+
+def AArch64MIR_decd : AArch64MIR_TargetOp<"decd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DECD_XPiI DECD_ZPiI
+}
+
+def AArch64MIR_dech : AArch64MIR_TargetOp<"dech", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DECH_XPiI DECH_ZPiI
+}
+
+def AArch64MIR_decp : AArch64MIR_TargetOp<"decp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DECP_XP_B DECP_XP_D DECP_XP_H DECP_XP_S DECP_ZP_D DECP_ZP_H DECP_ZP_S
+}
+
+def AArch64MIR_decw : AArch64MIR_TargetOp<"decw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DECW_XPiI DECW_ZPiI
+}
+
+def AArch64MIR_dmb : AArch64MIR_TargetOp<"dmb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DMB
+}
+
+def AArch64MIR_drps : AArch64MIR_TargetOp<"drps", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DRPS
+}
+
+def AArch64MIR_dsb : AArch64MIR_TargetOp<"dsb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DSB DSBnXS
+}
+
+def AArch64MIR_dupm : AArch64MIR_TargetOp<"dupm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DUPM_ZI
+}
+
+def AArch64MIR_dupq : AArch64MIR_TargetOp<"dupq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DUPQ_ZZI_B DUPQ_ZZI_D DUPQ_ZZI_H DUPQ_ZZI_S
+}
+
+def AArch64MIR_dup : AArch64MIR_TargetOp<"dup", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DUP_ZI_B DUP_ZI_D DUP_ZI_H DUP_ZI_S DUP_ZR_B DUP_ZR_D DUP_ZR_H DUP_ZR_S DUP_ZZI_B DUP_ZZI_D DUP_ZZI_H DUP_ZZI_Q DUP_ZZI_S DUPv2i32gpr DUPv2i32lane DUPv2i64gpr DUPv2i64lane DUPv4i16gpr DUPv4i16lane DUPv4i32gpr DUPv4i32lane DUPv8i8gpr DUPv8i8lane DUPv8i16gpr DUPv8i16lane DUPv16i8gpr DUPv16i8lane
+}
+
+def AArch64MIR_mov : AArch64MIR_TargetOp<"mov", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: DUPi8 DUPi16 DUPi32 DUPi64
+}
+
+def AArch64MIR_eon : AArch64MIR_TargetOp<"eon", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EONWrs EONXrs
+}
+
+def AArch64MIR_eor3 : AArch64MIR_TargetOp<"eor3", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EOR3 EOR3_ZZZZ
+}
+
+def AArch64MIR_eorbt : AArch64MIR_TargetOp<"eorbt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EORBT_ZZZ_B EORBT_ZZZ_D EORBT_ZZZ_H EORBT_ZZZ_S
+}
+
+def AArch64MIR_eorqv : AArch64MIR_TargetOp<"eorqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EORQV_VPZ_B EORQV_VPZ_D EORQV_VPZ_H EORQV_VPZ_S
+}
+
+def AArch64MIR_eors : AArch64MIR_TargetOp<"eors", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EORS_PPzPP
+}
+
+def AArch64MIR_eortb : AArch64MIR_TargetOp<"eortb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EORTB_ZZZ_B EORTB_ZZZ_D EORTB_ZZZ_H EORTB_ZZZ_S
+}
+
+def AArch64MIR_eorv : AArch64MIR_TargetOp<"eorv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EORV_VPZ_B EORV_VPZ_D EORV_VPZ_H EORV_VPZ_S
+}
+
+def AArch64MIR_eor : AArch64MIR_TargetOp<"eor", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EORWri EORWrs EORXri EORXrs EOR_PPzPP EOR_ZI EOR_ZPmZ_B EOR_ZPmZ_D EOR_ZPmZ_H EOR_ZPmZ_S EOR_ZZZ EORv8i8 EORv16i8
+}
+
+def AArch64MIR_eret : AArch64MIR_TargetOp<"eret", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ERET
+}
+
+def AArch64MIR_eretaa : AArch64MIR_TargetOp<"eretaa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ERETAA
+}
+
+def AArch64MIR_eretab : AArch64MIR_TargetOp<"eretab", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ERETAB
+}
+
+def AArch64MIR_expand : AArch64MIR_TargetOp<"expand", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EXPAND_ZPZ_B EXPAND_ZPZ_D EXPAND_ZPZ_H EXPAND_ZPZ_S
+}
+
+def AArch64MIR_extq : AArch64MIR_TargetOp<"extq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EXTQ_ZZI
+}
+
+def AArch64MIR_mova : AArch64MIR_TargetOp<"mova", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EXTRACT_ZPMXI_H_B EXTRACT_ZPMXI_H_D EXTRACT_ZPMXI_H_H EXTRACT_ZPMXI_H_Q EXTRACT_ZPMXI_H_S EXTRACT_ZPMXI_V_B EXTRACT_ZPMXI_V_D EXTRACT_ZPMXI_V_H EXTRACT_ZPMXI_V_Q EXTRACT_ZPMXI_V_S INSERT_MXIPZ_H_B INSERT_MXIPZ_H_D INSERT_MXIPZ_H_H INSERT_MXIPZ_H_Q INSERT_MXIPZ_H_S INSERT_MXIPZ_V_B INSERT_MXIPZ_V_D INSERT_MXIPZ_V_H INSERT_MXIPZ_V_Q INSERT_MXIPZ_V_S MOVA_2ZMXI_H_B MOVA_2ZMXI_H_D MOVA_2ZMXI_H_H MOVA_2ZMXI_H_S MOVA_2ZMXI_V_B MOVA_2ZMXI_V_D MOVA_2ZMXI_V_H MOVA_2ZMXI_V_S MOVA_4ZMXI_H_B MOVA_4ZMXI_H_D MOVA_4ZMXI_H_H MOVA_4ZMXI_H_S MOVA_4ZMXI_V_B MOVA_4ZMXI_V_D MOVA_4ZMXI_V_H MOVA_4ZMXI_V_S MOVA_MXI2Z_H_B MOVA_MXI2Z_H_D MOVA_MXI2Z_H_H MOVA_MXI2Z_H_S MOVA_MXI2Z_V_B MOVA_MXI2Z_V_D MOVA_MXI2Z_V_H MOVA_MXI2Z_V_S MOVA_MXI4Z_H_B MOVA_MXI4Z_H_D MOVA_MXI4Z_H_H MOVA_MXI4Z_H_S MOVA_MXI4Z_V_B MOVA_MXI4Z_V_D MOVA_MXI4Z_V_H MOVA_MXI4Z_V_S MOVA_VG2_2ZMXI MOVA_VG2_MXI2Z MOVA_VG4_4ZMXI MOVA_VG4_MXI4Z
+}
+
+def AArch64MIR_extr : AArch64MIR_TargetOp<"extr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EXTRWrri EXTRXrri
+}
+
+def AArch64MIR_ext : AArch64MIR_TargetOp<"ext", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: EXT_ZZI EXT_ZZI_B EXTv8i8 EXTv16i8
+}
+
+def AArch64MIR_f1cvtl : AArch64MIR_TargetOp<"f1cvtl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: F1CVTL F1CVTL_2ZZ_BtoH
+}
+
+def AArch64MIR_f1cvtl2 : AArch64MIR_TargetOp<"f1cvtl2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: F1CVTL2
+}
+
+def AArch64MIR_f1cvtlt : AArch64MIR_TargetOp<"f1cvtlt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: F1CVTLT_ZZ_BtoH
+}
+
+def AArch64MIR_f1cvt : AArch64MIR_TargetOp<"f1cvt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: F1CVT_2ZZ_BtoH F1CVT_ZZ_BtoH
+}
+
+def AArch64MIR_f2cvtl : AArch64MIR_TargetOp<"f2cvtl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: F2CVTL F2CVTL_2ZZ_BtoH
+}
+
+def AArch64MIR_f2cvtl2 : AArch64MIR_TargetOp<"f2cvtl2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: F2CVTL2
+}
+
+def AArch64MIR_f2cvtlt : AArch64MIR_TargetOp<"f2cvtlt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: F2CVTLT_ZZ_BtoH
+}
+
+def AArch64MIR_f2cvt : AArch64MIR_TargetOp<"f2cvt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: F2CVT_2ZZ_BtoH F2CVT_ZZ_BtoH
+}
+
+def AArch64MIR_fabd : AArch64MIR_TargetOp<"fabd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FABD16 FABD32 FABD64 FABD_ZPmZ_D FABD_ZPmZ_H FABD_ZPmZ_S FABDv2f32 FABDv2f64 FABDv4f16 FABDv4f32 FABDv8f16
+}
+
+def AArch64MIR_fabs : AArch64MIR_TargetOp<"fabs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FABSDr FABSHr FABSSr FABS_ZPmZ_D FABS_ZPmZ_H FABS_ZPmZ_S FABS_ZPzZ_D FABS_ZPzZ_H FABS_ZPzZ_S FABSv2f32 FABSv2f64 FABSv4f16 FABSv4f32 FABSv8f16
+}
+
+def AArch64MIR_facge : AArch64MIR_TargetOp<"facge", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FACGE16 FACGE32 FACGE64 FACGE_PPzZZ_D FACGE_PPzZZ_H FACGE_PPzZZ_S FACGEv2f32 FACGEv2f64 FACGEv4f16 FACGEv4f32 FACGEv8f16
+}
+
+def AArch64MIR_facgt : AArch64MIR_TargetOp<"facgt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FACGT16 FACGT32 FACGT64 FACGT_PPzZZ_D FACGT_PPzZZ_H FACGT_PPzZZ_S FACGTv2f32 FACGTv2f64 FACGTv4f16 FACGTv4f32 FACGTv8f16
+}
+
+def AArch64MIR_fadda : AArch64MIR_TargetOp<"fadda", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FADDA_VPZ_D FADDA_VPZ_H FADDA_VPZ_S
+}
+
+def AArch64MIR_fadd : AArch64MIR_TargetOp<"fadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FADDDrr FADDHrr FADDSrr FADD_VG2_M2Z_D FADD_VG2_M2Z_H FADD_VG2_M2Z_S FADD_VG4_M4Z_D FADD_VG4_M4Z_H FADD_VG4_M4Z_S FADD_ZPmI_D FADD_ZPmI_H FADD_ZPmI_S FADD_ZPmZ_D FADD_ZPmZ_H FADD_ZPmZ_S FADD_ZZZ_D FADD_ZZZ_H FADD_ZZZ_S FADDv2f32 FADDv2f64 FADDv4f16 FADDv4f32 FADDv8f16
+}
+
+def AArch64MIR_faddp : AArch64MIR_TargetOp<"faddp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FADDP_ZPmZZ_D FADDP_ZPmZZ_H FADDP_ZPmZZ_S FADDPv2f32 FADDPv2f64 FADDPv2i16p FADDPv2i32p FADDPv2i64p FADDPv4f16 FADDPv4f32 FADDPv8f16
+}
+
+def AArch64MIR_faddqv : AArch64MIR_TargetOp<"faddqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FADDQV_D FADDQV_H FADDQV_S
+}
+
+def AArch64MIR_faddv : AArch64MIR_TargetOp<"faddv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FADDV_VPZ_D FADDV_VPZ_H FADDV_VPZ_S
+}
+
+def AArch64MIR_famax : AArch64MIR_TargetOp<"famax", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FAMAX_2Z2Z_D FAMAX_2Z2Z_H FAMAX_2Z2Z_S FAMAX_4Z4Z_D FAMAX_4Z4Z_H FAMAX_4Z4Z_S FAMAX_ZPmZ_D FAMAX_ZPmZ_H FAMAX_ZPmZ_S FAMAXv2f32 FAMAXv2f64 FAMAXv4f16 FAMAXv4f32 FAMAXv8f16
+}
+
+def AArch64MIR_famin : AArch64MIR_TargetOp<"famin", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FAMIN_2Z2Z_D FAMIN_2Z2Z_H FAMIN_2Z2Z_S FAMIN_4Z4Z_D FAMIN_4Z4Z_H FAMIN_4Z4Z_S FAMIN_ZPmZ_D FAMIN_ZPmZ_H FAMIN_ZPmZ_S FAMINv2f32 FAMINv2f64 FAMINv4f16 FAMINv4f32 FAMINv8f16
+}
+
+def AArch64MIR_fcadd : AArch64MIR_TargetOp<"fcadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCADD_ZPmZ_D FCADD_ZPmZ_H FCADD_ZPmZ_S FCADDv2f32 FCADDv2f64 FCADDv4f16 FCADDv4f32 FCADDv8f16
+}
+
+def AArch64MIR_fccmp : AArch64MIR_TargetOp<"fccmp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCCMPDrr FCCMPHrr FCCMPSrr
+}
+
+def AArch64MIR_fccmpe : AArch64MIR_TargetOp<"fccmpe", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCCMPEDrr FCCMPEHrr FCCMPESrr
+}
+
+def AArch64MIR_fclamp : AArch64MIR_TargetOp<"fclamp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCLAMP_VG2_2Z2Z_D FCLAMP_VG2_2Z2Z_H FCLAMP_VG2_2Z2Z_S FCLAMP_VG4_4Z4Z_D FCLAMP_VG4_4Z4Z_H FCLAMP_VG4_4Z4Z_S FCLAMP_ZZZ_D FCLAMP_ZZZ_H FCLAMP_ZZZ_S
+}
+
+def AArch64MIR_fcmeq : AArch64MIR_TargetOp<"fcmeq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMEQ16 FCMEQ32 FCMEQ64 FCMEQ_PPzZ0_D FCMEQ_PPzZ0_H FCMEQ_PPzZ0_S FCMEQ_PPzZZ_D FCMEQ_PPzZZ_H FCMEQ_PPzZZ_S FCMEQv1i16rz FCMEQv1i32rz FCMEQv1i64rz FCMEQv2f32 FCMEQv2f64 FCMEQv2i32rz FCMEQv2i64rz FCMEQv4f16 FCMEQv4f32 FCMEQv4i16rz FCMEQv4i32rz FCMEQv8f16 FCMEQv8i16rz
+}
+
+def AArch64MIR_fcmge : AArch64MIR_TargetOp<"fcmge", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMGE16 FCMGE32 FCMGE64 FCMGE_PPzZ0_D FCMGE_PPzZ0_H FCMGE_PPzZ0_S FCMGE_PPzZZ_D FCMGE_PPzZZ_H FCMGE_PPzZZ_S FCMGEv1i16rz FCMGEv1i32rz FCMGEv1i64rz FCMGEv2f32 FCMGEv2f64 FCMGEv2i32rz FCMGEv2i64rz FCMGEv4f16 FCMGEv4f32 FCMGEv4i16rz FCMGEv4i32rz FCMGEv8f16 FCMGEv8i16rz
+}
+
+def AArch64MIR_fcmgt : AArch64MIR_TargetOp<"fcmgt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMGT16 FCMGT32 FCMGT64 FCMGT_PPzZ0_D FCMGT_PPzZ0_H FCMGT_PPzZ0_S FCMGT_PPzZZ_D FCMGT_PPzZZ_H FCMGT_PPzZZ_S FCMGTv1i16rz FCMGTv1i32rz FCMGTv1i64rz FCMGTv2f32 FCMGTv2f64 FCMGTv2i32rz FCMGTv2i64rz FCMGTv4f16 FCMGTv4f32 FCMGTv4i16rz FCMGTv4i32rz FCMGTv8f16 FCMGTv8i16rz
+}
+
+def AArch64MIR_fcmla : AArch64MIR_TargetOp<"fcmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMLA_ZPmZZ_D FCMLA_ZPmZZ_H FCMLA_ZPmZZ_S FCMLA_ZZZI_H FCMLA_ZZZI_S FCMLAv2f32 FCMLAv2f64 FCMLAv4f16 FCMLAv4f16_indexed FCMLAv4f32 FCMLAv4f32_indexed FCMLAv8f16 FCMLAv8f16_indexed
+}
+
+def AArch64MIR_fcmle : AArch64MIR_TargetOp<"fcmle", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMLE_PPzZ0_D FCMLE_PPzZ0_H FCMLE_PPzZ0_S FCMLEv1i16rz FCMLEv1i32rz FCMLEv1i64rz FCMLEv2i32rz FCMLEv2i64rz FCMLEv4i16rz FCMLEv4i32rz FCMLEv8i16rz
+}
+
+def AArch64MIR_fcmlt : AArch64MIR_TargetOp<"fcmlt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMLT_PPzZ0_D FCMLT_PPzZ0_H FCMLT_PPzZ0_S FCMLTv1i16rz FCMLTv1i32rz FCMLTv1i64rz FCMLTv2i32rz FCMLTv2i64rz FCMLTv4i16rz FCMLTv4i32rz FCMLTv8i16rz
+}
+
+def AArch64MIR_fcmne : AArch64MIR_TargetOp<"fcmne", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMNE_PPzZ0_D FCMNE_PPzZ0_H FCMNE_PPzZ0_S FCMNE_PPzZZ_D FCMNE_PPzZZ_H FCMNE_PPzZZ_S
+}
+
+def AArch64MIR_fcmp : AArch64MIR_TargetOp<"fcmp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMPDri FCMPDrr FCMPHri FCMPHrr FCMPSri FCMPSrr
+}
+
+def AArch64MIR_fcmpe : AArch64MIR_TargetOp<"fcmpe", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMPEDri FCMPEDrr FCMPEHri FCMPEHrr FCMPESri FCMPESrr
+}
+
+def AArch64MIR_fcmuo : AArch64MIR_TargetOp<"fcmuo", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCMUO_PPzZZ_D FCMUO_PPzZZ_H FCMUO_PPzZZ_S
+}
+
+def AArch64MIR_fcpy : AArch64MIR_TargetOp<"fcpy", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCPY_ZPmI_D FCPY_ZPmI_H FCPY_ZPmI_S
+}
+
+def AArch64MIR_fcsel : AArch64MIR_TargetOp<"fcsel", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCSELDrrr FCSELHrrr FCSELSrrr
+}
+
+def AArch64MIR_fcvtas : AArch64MIR_TargetOp<"fcvtas", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTASDHr FCVTASDSr FCVTASSDr FCVTASSHr FCVTASUWDr FCVTASUWHr FCVTASUWSr FCVTASUXDr FCVTASUXHr FCVTASUXSr FCVTASv1f16 FCVTASv1i32 FCVTASv1i64 FCVTASv2f32 FCVTASv2f64 FCVTASv4f16 FCVTASv4f32 FCVTASv8f16
+}
+
+def AArch64MIR_fcvtau : AArch64MIR_TargetOp<"fcvtau", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTAUDHr FCVTAUDSr FCVTAUSDr FCVTAUSHr FCVTAUUWDr FCVTAUUWHr FCVTAUUWSr FCVTAUUXDr FCVTAUUXHr FCVTAUUXSr FCVTAUv1f16 FCVTAUv1i32 FCVTAUv1i64 FCVTAUv2f32 FCVTAUv2f64 FCVTAUv4f16 FCVTAUv4f32 FCVTAUv8f16
+}
+
+def AArch64MIR_fcvt : AArch64MIR_TargetOp<"fcvt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTDHr FCVTDSr FCVTHDr FCVTHSr FCVTSDr FCVTSHr FCVT_2ZZ_H_S FCVT_Z2Z_HtoB FCVT_Z2Z_StoH FCVT_Z4Z_StoB FCVT_ZPmZ_DtoH FCVT_ZPmZ_DtoS FCVT_ZPmZ_HtoD FCVT_ZPmZ_HtoS FCVT_ZPmZ_StoD FCVT_ZPmZ_StoH FCVT_ZPzZ_DtoH FCVT_ZPzZ_DtoS FCVT_ZPzZ_HtoD FCVT_ZPzZ_HtoS FCVT_ZPzZ_StoD FCVT_ZPzZ_StoH
+}
+
+def AArch64MIR_fcvtlt : AArch64MIR_TargetOp<"fcvtlt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTLT_ZPmZ_HtoS FCVTLT_ZPmZ_StoD FCVTLT_ZPzZ_HtoS FCVTLT_ZPzZ_StoD
+}
+
+def AArch64MIR_fcvtl : AArch64MIR_TargetOp<"fcvtl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTL_2ZZ_H_S FCVTLv2i32 FCVTLv4i16
+}
+
+def AArch64MIR_fcvtl2 : AArch64MIR_TargetOp<"fcvtl2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTLv4i32 FCVTLv8i16
+}
+
+def AArch64MIR_fcvtms : AArch64MIR_TargetOp<"fcvtms", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTMSDHr FCVTMSDSr FCVTMSSDr FCVTMSSHr FCVTMSUWDr FCVTMSUWHr FCVTMSUWSr FCVTMSUXDr FCVTMSUXHr FCVTMSUXSr FCVTMSv1f16 FCVTMSv1i32 FCVTMSv1i64 FCVTMSv2f32 FCVTMSv2f64 FCVTMSv4f16 FCVTMSv4f32 FCVTMSv8f16
+}
+
+def AArch64MIR_fcvtmu : AArch64MIR_TargetOp<"fcvtmu", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTMUDHr FCVTMUDSr FCVTMUSDr FCVTMUSHr FCVTMUUWDr FCVTMUUWHr FCVTMUUWSr FCVTMUUXDr FCVTMUUXHr FCVTMUUXSr FCVTMUv1f16 FCVTMUv1i32 FCVTMUv1i64 FCVTMUv2f32 FCVTMUv2f64 FCVTMUv4f16 FCVTMUv4f32 FCVTMUv8f16
+}
+
+def AArch64MIR_fcvtnb : AArch64MIR_TargetOp<"fcvtnb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTNB_Z2Z_StoB
+}
+
+def AArch64MIR_fcvtns : AArch64MIR_TargetOp<"fcvtns", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTNSDHr FCVTNSDSr FCVTNSSDr FCVTNSSHr FCVTNSUWDr FCVTNSUWHr FCVTNSUWSr FCVTNSUXDr FCVTNSUXHr FCVTNSUXSr FCVTNSv1f16 FCVTNSv1i32 FCVTNSv1i64 FCVTNSv2f32 FCVTNSv2f64 FCVTNSv4f16 FCVTNSv4f32 FCVTNSv8f16
+}
+
+def AArch64MIR_fcvtnt : AArch64MIR_TargetOp<"fcvtnt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTNT_Z2Z_StoB FCVTNT_ZPmZ_DtoS FCVTNT_ZPmZ_StoH FCVTNT_ZPzZ_DtoS FCVTNT_ZPzZ_StoH
+}
+
+def AArch64MIR_fcvtnu : AArch64MIR_TargetOp<"fcvtnu", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTNUDHr FCVTNUDSr FCVTNUSDr FCVTNUSHr FCVTNUUWDr FCVTNUUWHr FCVTNUUWSr FCVTNUUXDr FCVTNUUXHr FCVTNUUXSr FCVTNUv1f16 FCVTNUv1i32 FCVTNUv1i64 FCVTNUv2f32 FCVTNUv2f64 FCVTNUv4f16 FCVTNUv4f32 FCVTNUv8f16
+}
+
+def AArch64MIR_fcvtn : AArch64MIR_TargetOp<"fcvtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTN_F16v8f8 FCVTN_F16v16f8 FCVTN_F32v8f8 FCVTN_Z2Z_HtoB FCVTN_Z2Z_StoH FCVTN_Z4Z_StoB FCVTNv2i32 FCVTNv4i16
+}
+
+def AArch64MIR_fcvtn2 : AArch64MIR_TargetOp<"fcvtn2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTN_F322v16f8 FCVTNv4i32 FCVTNv8i16
+}
+
+def AArch64MIR_fcvtps : AArch64MIR_TargetOp<"fcvtps", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTPSDHr FCVTPSDSr FCVTPSSDr FCVTPSSHr FCVTPSUWDr FCVTPSUWHr FCVTPSUWSr FCVTPSUXDr FCVTPSUXHr FCVTPSUXSr FCVTPSv1f16 FCVTPSv1i32 FCVTPSv1i64 FCVTPSv2f32 FCVTPSv2f64 FCVTPSv4f16 FCVTPSv4f32 FCVTPSv8f16
+}
+
+def AArch64MIR_fcvtpu : AArch64MIR_TargetOp<"fcvtpu", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTPUDHr FCVTPUDSr FCVTPUSDr FCVTPUSHr FCVTPUUWDr FCVTPUUWHr FCVTPUUWSr FCVTPUUXDr FCVTPUUXHr FCVTPUUXSr FCVTPUv1f16 FCVTPUv1i32 FCVTPUv1i64 FCVTPUv2f32 FCVTPUv2f64 FCVTPUv4f16 FCVTPUv4f32 FCVTPUv8f16
+}
+
+def AArch64MIR_fcvtxnt : AArch64MIR_TargetOp<"fcvtxnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTXNT_ZPmZ_DtoS FCVTXNT_ZPzZ_StoD
+}
+
+def AArch64MIR_fcvtxn : AArch64MIR_TargetOp<"fcvtxn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTXNv1i64 FCVTXNv2f32
+}
+
+def AArch64MIR_fcvtxn2 : AArch64MIR_TargetOp<"fcvtxn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTXNv4f32
+}
+
+def AArch64MIR_fcvtx : AArch64MIR_TargetOp<"fcvtx", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTX_ZPmZ_DtoS FCVTX_ZPzZ_DtoS
+}
+
+def AArch64MIR_fcvtzs : AArch64MIR_TargetOp<"fcvtzs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTZSDHr FCVTZSDSr FCVTZSSDr FCVTZSSHr FCVTZSSWDri FCVTZSSWHri FCVTZSSWSri FCVTZSSXDri FCVTZSSXHri FCVTZSSXSri FCVTZSUWDr FCVTZSUWHr FCVTZSUWSr FCVTZSUXDr FCVTZSUXHr FCVTZSUXSr FCVTZS_2Z2Z_StoS FCVTZS_4Z4Z_StoS FCVTZS_ZPmZ_DtoD FCVTZS_ZPmZ_DtoS FCVTZS_ZPmZ_HtoD FCVTZS_ZPmZ_HtoH FCVTZS_ZPmZ_HtoS FCVTZS_ZPmZ_StoD FCVTZS_ZPmZ_StoS FCVTZS_ZPzZ_DtoD FCVTZS_ZPzZ_DtoS FCVTZS_ZPzZ_HtoD FCVTZS_ZPzZ_HtoH FCVTZS_ZPzZ_HtoS FCVTZS_ZPzZ_StoD FCVTZS_ZPzZ_StoS FCVTZSd FCVTZSh FCVTZSs FCVTZSv1f16 FCVTZSv1i32 FCVTZSv1i64 FCVTZSv2f32 FCVTZSv2f64 FCVTZSv2i32_shift FCVTZSv2i64_shift FCVTZSv4f16 FCVTZSv4f32 FCVTZSv4i16_shift FCVTZSv4i32_shift FCVTZSv8f16 FCVTZSv8i16_shift
+}
+
+def AArch64MIR_fcvtzsn : AArch64MIR_TargetOp<"fcvtzsn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTZSN_Z2Z_DtoS FCVTZSN_Z2Z_HtoB FCVTZSN_Z2Z_StoH
+}
+
+def AArch64MIR_fcvtzu : AArch64MIR_TargetOp<"fcvtzu", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTZUDHr FCVTZUDSr FCVTZUSDr FCVTZUSHr FCVTZUSWDri FCVTZUSWHri FCVTZUSWSri FCVTZUSXDri FCVTZUSXHri FCVTZUSXSri FCVTZUUWDr FCVTZUUWHr FCVTZUUWSr FCVTZUUXDr FCVTZUUXHr FCVTZUUXSr FCVTZU_2Z2Z_StoS FCVTZU_4Z4Z_StoS FCVTZU_ZPmZ_DtoD FCVTZU_ZPmZ_DtoS FCVTZU_ZPmZ_HtoD FCVTZU_ZPmZ_HtoH FCVTZU_ZPmZ_HtoS FCVTZU_ZPmZ_StoD FCVTZU_ZPmZ_StoS FCVTZU_ZPzZ_DtoD FCVTZU_ZPzZ_DtoS FCVTZU_ZPzZ_HtoD FCVTZU_ZPzZ_HtoH FCVTZU_ZPzZ_HtoS FCVTZU_ZPzZ_StoD FCVTZU_ZPzZ_StoS FCVTZUd FCVTZUh FCVTZUs FCVTZUv1f16 FCVTZUv1i32 FCVTZUv1i64 FCVTZUv2f32 FCVTZUv2f64 FCVTZUv2i32_shift FCVTZUv2i64_shift FCVTZUv4f16 FCVTZUv4f32 FCVTZUv4i16_shift FCVTZUv4i32_shift FCVTZUv8f16 FCVTZUv8i16_shift
+}
+
+def AArch64MIR_fcvtzun : AArch64MIR_TargetOp<"fcvtzun", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FCVTZUN_Z2Z_DtoS FCVTZUN_Z2Z_HtoB FCVTZUN_Z2Z_StoH
+}
+
+def AArch64MIR_fdiv : AArch64MIR_TargetOp<"fdiv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FDIVDrr FDIVHrr FDIVSrr FDIV_ZPmZ_D FDIV_ZPmZ_H FDIV_ZPmZ_S FDIVv2f32 FDIVv2f64 FDIVv4f16 FDIVv4f32 FDIVv8f16
+}
+
+def AArch64MIR_fdivr : AArch64MIR_TargetOp<"fdivr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FDIVR_ZPmZ_D FDIVR_ZPmZ_H FDIVR_ZPmZ_S
+}
+
+def AArch64MIR_fdot : AArch64MIR_TargetOp<"fdot", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FDOT_VG2_M2Z2Z_BtoH FDOT_VG2_M2Z2Z_BtoS FDOT_VG2_M2Z2Z_HtoS FDOT_VG2_M2ZZI_BtoH FDOT_VG2_M2ZZI_BtoS FDOT_VG2_M2ZZI_HtoS FDOT_VG2_M2ZZ_BtoH FDOT_VG2_M2ZZ_BtoS FDOT_VG2_M2ZZ_HtoS FDOT_VG4_M4Z4Z_BtoH FDOT_VG4_M4Z4Z_BtoS FDOT_VG4_M4Z4Z_HtoS FDOT_VG4_M4ZZI_BtoH FDOT_VG4_M4ZZI_BtoS FDOT_VG4_M4ZZI_HtoS FDOT_VG4_M4ZZ_BtoH FDOT_VG4_M4ZZ_BtoS FDOT_VG4_M4ZZ_HtoS FDOT_ZZZI_BtoH FDOT_ZZZI_BtoS FDOT_ZZZI_S FDOT_ZZZ_BtoH FDOT_ZZZ_BtoS FDOT_ZZZ_S FDOTlanev2f32 FDOTlanev4f16 FDOTlanev4f16_v2f32 FDOTlanev4f32 FDOTlanev8f16 FDOTlanev8f16_v4f32 FDOTv2f32 FDOTv4f16 FDOTv4f16_v2f32 FDOTv4f32 FDOTv8f16 FDOTv8f16_v4f32
+}
+
+def AArch64MIR_fdup : AArch64MIR_TargetOp<"fdup", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FDUP_ZI_D FDUP_ZI_H FDUP_ZI_S
+}
+
+def AArch64MIR_fexpa : AArch64MIR_TargetOp<"fexpa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FEXPA_ZZ_D FEXPA_ZZ_H FEXPA_ZZ_S
+}
+
+def AArch64MIR_firstp : AArch64MIR_TargetOp<"firstp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FIRSTP_XPP_B FIRSTP_XPP_D FIRSTP_XPP_H FIRSTP_XPP_S
+}
+
+def AArch64MIR_fjcvtzs : AArch64MIR_TargetOp<"fjcvtzs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FJCVTZS
+}
+
+def AArch64MIR_flogb : AArch64MIR_TargetOp<"flogb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FLOGB_ZPmZ_D FLOGB_ZPmZ_H FLOGB_ZPmZ_S FLOGB_ZPzZ_D FLOGB_ZPzZ_H FLOGB_ZPzZ_S
+}
+
+def AArch64MIR_fmadd : AArch64MIR_TargetOp<"fmadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMADDDrrr FMADDHrrr FMADDSrrr
+}
+
+def AArch64MIR_fmad : AArch64MIR_TargetOp<"fmad", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAD_ZPmZZ_D FMAD_ZPmZZ_H FMAD_ZPmZZ_S
+}
+
+def AArch64MIR_fmax : AArch64MIR_TargetOp<"fmax", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAXDrr FMAXHrr FMAXSrr FMAX_VG2_2Z2Z_D FMAX_VG2_2Z2Z_H FMAX_VG2_2Z2Z_S FMAX_VG2_2ZZ_D FMAX_VG2_2ZZ_H FMAX_VG2_2ZZ_S FMAX_VG4_4Z4Z_D FMAX_VG4_4Z4Z_H FMAX_VG4_4Z4Z_S FMAX_VG4_4ZZ_D FMAX_VG4_4ZZ_H FMAX_VG4_4ZZ_S FMAX_ZPmI_D FMAX_ZPmI_H FMAX_ZPmI_S FMAX_ZPmZ_D FMAX_ZPmZ_H FMAX_ZPmZ_S FMAXv2f32 FMAXv2f64 FMAXv4f16 FMAXv4f32 FMAXv8f16
+}
+
+def AArch64MIR_fmaxnm : AArch64MIR_TargetOp<"fmaxnm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAXNMDrr FMAXNMHrr FMAXNMSrr FMAXNM_VG2_2Z2Z_D FMAXNM_VG2_2Z2Z_H FMAXNM_VG2_2Z2Z_S FMAXNM_VG2_2ZZ_D FMAXNM_VG2_2ZZ_H FMAXNM_VG2_2ZZ_S FMAXNM_VG4_4Z4Z_D FMAXNM_VG4_4Z4Z_H FMAXNM_VG4_4Z4Z_S FMAXNM_VG4_4ZZ_D FMAXNM_VG4_4ZZ_H FMAXNM_VG4_4ZZ_S FMAXNM_ZPmI_D FMAXNM_ZPmI_H FMAXNM_ZPmI_S FMAXNM_ZPmZ_D FMAXNM_ZPmZ_H FMAXNM_ZPmZ_S FMAXNMv2f32 FMAXNMv2f64 FMAXNMv4f16 FMAXNMv4f32 FMAXNMv8f16
+}
+
+def AArch64MIR_fmaxnmp : AArch64MIR_TargetOp<"fmaxnmp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAXNMP_ZPmZZ_D FMAXNMP_ZPmZZ_H FMAXNMP_ZPmZZ_S FMAXNMPv2f32 FMAXNMPv2f64 FMAXNMPv2i16p FMAXNMPv2i32p FMAXNMPv2i64p FMAXNMPv4f16 FMAXNMPv4f32 FMAXNMPv8f16
+}
+
+def AArch64MIR_fmaxnmqv : AArch64MIR_TargetOp<"fmaxnmqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAXNMQV_D FMAXNMQV_H FMAXNMQV_S
+}
+
+def AArch64MIR_fmaxnmv : AArch64MIR_TargetOp<"fmaxnmv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAXNMV_VPZ_D FMAXNMV_VPZ_H FMAXNMV_VPZ_S FMAXNMVv4i16v FMAXNMVv4i32v FMAXNMVv8i16v
+}
+
+def AArch64MIR_fmaxp : AArch64MIR_TargetOp<"fmaxp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAXP_ZPmZZ_D FMAXP_ZPmZZ_H FMAXP_ZPmZZ_S FMAXPv2f32 FMAXPv2f64 FMAXPv2i16p FMAXPv2i32p FMAXPv2i64p FMAXPv4f16 FMAXPv4f32 FMAXPv8f16
+}
+
+def AArch64MIR_fmaxqv : AArch64MIR_TargetOp<"fmaxqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAXQV_D FMAXQV_H FMAXQV_S
+}
+
+def AArch64MIR_fmaxv : AArch64MIR_TargetOp<"fmaxv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMAXV_VPZ_D FMAXV_VPZ_H FMAXV_VPZ_S FMAXVv4i16v FMAXVv4i32v FMAXVv8i16v
+}
+
+def AArch64MIR_fmin : AArch64MIR_TargetOp<"fmin", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMINDrr FMINHrr FMINSrr FMIN_VG2_2Z2Z_D FMIN_VG2_2Z2Z_H FMIN_VG2_2Z2Z_S FMIN_VG2_2ZZ_D FMIN_VG2_2ZZ_H FMIN_VG2_2ZZ_S FMIN_VG4_4Z4Z_D FMIN_VG4_4Z4Z_H FMIN_VG4_4Z4Z_S FMIN_VG4_4ZZ_D FMIN_VG4_4ZZ_H FMIN_VG4_4ZZ_S FMIN_ZPmI_D FMIN_ZPmI_H FMIN_ZPmI_S FMIN_ZPmZ_D FMIN_ZPmZ_H FMIN_ZPmZ_S FMINv2f32 FMINv2f64 FMINv4f16 FMINv4f32 FMINv8f16
+}
+
+def AArch64MIR_fminnm : AArch64MIR_TargetOp<"fminnm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMINNMDrr FMINNMHrr FMINNMSrr FMINNM_VG2_2Z2Z_D FMINNM_VG2_2Z2Z_H FMINNM_VG2_2Z2Z_S FMINNM_VG2_2ZZ_D FMINNM_VG2_2ZZ_H FMINNM_VG2_2ZZ_S FMINNM_VG4_4Z4Z_D FMINNM_VG4_4Z4Z_H FMINNM_VG4_4Z4Z_S FMINNM_VG4_4ZZ_D FMINNM_VG4_4ZZ_H FMINNM_VG4_4ZZ_S FMINNM_ZPmI_D FMINNM_ZPmI_H FMINNM_ZPmI_S FMINNM_ZPmZ_D FMINNM_ZPmZ_H FMINNM_ZPmZ_S FMINNMv2f32 FMINNMv2f64 FMINNMv4f16 FMINNMv4f32 FMINNMv8f16
+}
+
+def AArch64MIR_fminnmp : AArch64MIR_TargetOp<"fminnmp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMINNMP_ZPmZZ_D FMINNMP_ZPmZZ_H FMINNMP_ZPmZZ_S FMINNMPv2f32 FMINNMPv2f64 FMINNMPv2i16p FMINNMPv2i32p FMINNMPv2i64p FMINNMPv4f16 FMINNMPv4f32 FMINNMPv8f16
+}
+
+def AArch64MIR_fminnmqv : AArch64MIR_TargetOp<"fminnmqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMINNMQV_D FMINNMQV_H FMINNMQV_S
+}
+
+def AArch64MIR_fminnmv : AArch64MIR_TargetOp<"fminnmv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMINNMV_VPZ_D FMINNMV_VPZ_H FMINNMV_VPZ_S FMINNMVv4i16v FMINNMVv4i32v FMINNMVv8i16v
+}
+
+def AArch64MIR_fminp : AArch64MIR_TargetOp<"fminp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMINP_ZPmZZ_D FMINP_ZPmZZ_H FMINP_ZPmZZ_S FMINPv2f32 FMINPv2f64 FMINPv2i16p FMINPv2i32p FMINPv2i64p FMINPv4f16 FMINPv4f32 FMINPv8f16
+}
+
+def AArch64MIR_fminqv : AArch64MIR_TargetOp<"fminqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMINQV_D FMINQV_H FMINQV_S
+}
+
+def AArch64MIR_fminv : AArch64MIR_TargetOp<"fminv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMINV_VPZ_D FMINV_VPZ_H FMINV_VPZ_S FMINVv4i16v FMINVv4i32v FMINVv8i16v
+}
+
+def AArch64MIR_fmlal2 : AArch64MIR_TargetOp<"fmlal2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLAL2lanev4f16 FMLAL2lanev8f16 FMLAL2v4f16 FMLAL2v8f16
+}
+
+def AArch64MIR_fmlalb : AArch64MIR_TargetOp<"fmlalb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLALB_ZZZ FMLALB_ZZZI FMLALB_ZZZI_SHH FMLALB_ZZZ_SHH FMLALBlanev8f16 FMLALBv16i8_v8f16
+}
+
+def AArch64MIR_fmlallbb : AArch64MIR_TargetOp<"fmlallbb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLALLBB_ZZZ FMLALLBB_ZZZI FMLALLBBlanev4f32 FMLALLBBv4f32
+}
+
+def AArch64MIR_fmlallbt : AArch64MIR_TargetOp<"fmlallbt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLALLBT_ZZZ FMLALLBT_ZZZI FMLALLBTlanev4f32 FMLALLBTv4f32
+}
+
+def AArch64MIR_fmlalltb : AArch64MIR_TargetOp<"fmlalltb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLALLTB_ZZZ FMLALLTB_ZZZI FMLALLTBlanev4f32 FMLALLTBv4f32
+}
+
+def AArch64MIR_fmlalltt : AArch64MIR_TargetOp<"fmlalltt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLALLTT_ZZZ FMLALLTT_ZZZI FMLALLTTlanev4f32 FMLALLTTv4f32
+}
+
+def AArch64MIR_fmlall : AArch64MIR_TargetOp<"fmlall", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLALL_MZZI_BtoS FMLALL_MZZ_BtoS FMLALL_VG2_M2Z2Z_BtoS FMLALL_VG2_M2ZZI_BtoS FMLALL_VG2_M2ZZ_BtoS FMLALL_VG4_M4Z4Z_BtoS FMLALL_VG4_M4ZZI_BtoS FMLALL_VG4_M4ZZ_BtoS
+}
+
+def AArch64MIR_fmlalt : AArch64MIR_TargetOp<"fmlalt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLALT_ZZZ FMLALT_ZZZI FMLALT_ZZZI_SHH FMLALT_ZZZ_SHH FMLALTlanev8f16 FMLALTv16i8_v8f16
+}
+
+def AArch64MIR_fmlal : AArch64MIR_TargetOp<"fmlal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLAL_MZZI_BtoH FMLAL_MZZI_HtoS FMLAL_MZZ_HtoS FMLAL_VG2_M2Z2Z_BtoH FMLAL_VG2_M2Z2Z_HtoS FMLAL_VG2_M2ZZI_BtoH FMLAL_VG2_M2ZZI_HtoS FMLAL_VG2_M2ZZ_BtoH FMLAL_VG2_M2ZZ_HtoS FMLAL_VG2_MZZ_BtoH FMLAL_VG4_M4Z4Z_BtoH FMLAL_VG4_M4Z4Z_HtoS FMLAL_VG4_M4ZZI_BtoH FMLAL_VG4_M4ZZI_HtoS FMLAL_VG4_M4ZZ_BtoH FMLAL_VG4_M4ZZ_HtoS FMLALlanev4f16 FMLALlanev8f16 FMLALv4f16 FMLALv8f16
+}
+
+def AArch64MIR_fmla : AArch64MIR_TargetOp<"fmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLA_VG2_M2Z2Z_D FMLA_VG2_M2Z2Z_H FMLA_VG2_M2Z2Z_S FMLA_VG2_M2ZZI_D FMLA_VG2_M2ZZI_H FMLA_VG2_M2ZZI_S FMLA_VG2_M2ZZ_D FMLA_VG2_M2ZZ_H FMLA_VG2_M2ZZ_S FMLA_VG4_M4Z4Z_D FMLA_VG4_M4Z4Z_H FMLA_VG4_M4Z4Z_S FMLA_VG4_M4ZZI_D FMLA_VG4_M4ZZI_H FMLA_VG4_M4ZZI_S FMLA_VG4_M4ZZ_D FMLA_VG4_M4ZZ_H FMLA_VG4_M4ZZ_S FMLA_ZPmZZ_D FMLA_ZPmZZ_H FMLA_ZPmZZ_S FMLA_ZZZI_D FMLA_ZZZI_H FMLA_ZZZI_S FMLAv1i16_indexed FMLAv1i32_indexed FMLAv1i64_indexed FMLAv2f32 FMLAv2f64 FMLAv2i32_indexed FMLAv2i64_indexed FMLAv4f16 FMLAv4f32 FMLAv4i16_indexed FMLAv4i32_indexed FMLAv8f16 FMLAv8i16_indexed
+}
+
+def AArch64MIR_fmmla : AArch64MIR_TargetOp<"fmmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLLA_ZZZ_HtoS FMMLA_ZZZ_BtoH FMMLA_ZZZ_BtoS FMMLA_ZZZ_D FMMLA_ZZZ_H FMMLA_ZZZ_S FMMLAv4f32 FMMLAv8f16 FMMLAv8f16_v4f32 FMMLAv8f16_v8f16
+}
+
+def AArch64MIR_fmlsl2 : AArch64MIR_TargetOp<"fmlsl2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLSL2lanev4f16 FMLSL2lanev8f16 FMLSL2v4f16 FMLSL2v8f16
+}
+
+def AArch64MIR_fmlslb : AArch64MIR_TargetOp<"fmlslb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLSLB_ZZZI_SHH FMLSLB_ZZZ_SHH
+}
+
+def AArch64MIR_fmlslt : AArch64MIR_TargetOp<"fmlslt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLSLT_ZZZI_SHH FMLSLT_ZZZ_SHH
+}
+
+def AArch64MIR_fmlsl : AArch64MIR_TargetOp<"fmlsl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLSL_MZZI_HtoS FMLSL_MZZ_HtoS FMLSL_VG2_M2Z2Z_HtoS FMLSL_VG2_M2ZZI_HtoS FMLSL_VG2_M2ZZ_HtoS FMLSL_VG4_M4Z4Z_HtoS FMLSL_VG4_M4ZZI_HtoS FMLSL_VG4_M4ZZ_HtoS FMLSLlanev4f16 FMLSLlanev8f16 FMLSLv4f16 FMLSLv8f16
+}
+
+def AArch64MIR_fmls : AArch64MIR_TargetOp<"fmls", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMLS_VG2_M2Z2Z_D FMLS_VG2_M2Z2Z_H FMLS_VG2_M2Z2Z_S FMLS_VG2_M2ZZI_D FMLS_VG2_M2ZZI_H FMLS_VG2_M2ZZI_S FMLS_VG2_M2ZZ_D FMLS_VG2_M2ZZ_H FMLS_VG2_M2ZZ_S FMLS_VG4_M4Z4Z_D FMLS_VG4_M4Z4Z_H FMLS_VG4_M4Z4Z_S FMLS_VG4_M4ZZI_D FMLS_VG4_M4ZZI_H FMLS_VG4_M4ZZI_S FMLS_VG4_M4ZZ_D FMLS_VG4_M4ZZ_H FMLS_VG4_M4ZZ_S FMLS_ZPmZZ_D FMLS_ZPmZZ_H FMLS_ZPmZZ_S FMLS_ZZZI_D FMLS_ZZZI_H FMLS_ZZZI_S FMLSv1i16_indexed FMLSv1i32_indexed FMLSv1i64_indexed FMLSv2f32 FMLSv2f64 FMLSv2i32_indexed FMLSv2i64_indexed FMLSv4f16 FMLSv4f32 FMLSv4i16_indexed FMLSv4i32_indexed FMLSv8f16 FMLSv8i16_indexed
+}
+
+def AArch64MIR_fmop4a : AArch64MIR_TargetOp<"fmop4a", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMOP4A_M2Z2Z_BtoH FMOP4A_M2Z2Z_BtoS FMOP4A_M2Z2Z_D FMOP4A_M2Z2Z_H FMOP4A_M2Z2Z_HtoS FMOP4A_M2Z2Z_S FMOP4A_M2ZZ_BtoH FMOP4A_M2ZZ_BtoS FMOP4A_M2ZZ_D FMOP4A_M2ZZ_H FMOP4A_M2ZZ_HtoS FMOP4A_M2ZZ_S FMOP4A_MZ2Z_BtoH FMOP4A_MZ2Z_BtoS FMOP4A_MZ2Z_D FMOP4A_MZ2Z_H FMOP4A_MZ2Z_HtoS FMOP4A_MZ2Z_S FMOP4A_MZZ_BtoH FMOP4A_MZZ_BtoS FMOP4A_MZZ_D FMOP4A_MZZ_H FMOP4A_MZZ_HtoS FMOP4A_MZZ_S
+}
+
+def AArch64MIR_fmop4s : AArch64MIR_TargetOp<"fmop4s", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMOP4S_M2Z2Z_D FMOP4S_M2Z2Z_H FMOP4S_M2Z2Z_HtoS FMOP4S_M2Z2Z_S FMOP4S_M2ZZ_D FMOP4S_M2ZZ_H FMOP4S_M2ZZ_HtoS FMOP4S_M2ZZ_S FMOP4S_MZ2Z_D FMOP4S_MZ2Z_H FMOP4S_MZ2Z_HtoS FMOP4S_MZ2Z_S FMOP4S_MZZ_D FMOP4S_MZZ_H FMOP4S_MZZ_HtoS FMOP4S_MZZ_S
+}
+
+def AArch64MIR_fmopa : AArch64MIR_TargetOp<"fmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMOPAL_MPPZZ FMOPA_MPPZZ_BtoH FMOPA_MPPZZ_BtoS FMOPA_MPPZZ_D FMOPA_MPPZZ_H FMOPA_MPPZZ_S
+}
+
+def AArch64MIR_fmops : AArch64MIR_TargetOp<"fmops", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMOPSL_MPPZZ FMOPS_MPPZZ_D FMOPS_MPPZZ_H FMOPS_MPPZZ_S
+}
+
+def AArch64MIR_fmov : AArch64MIR_TargetOp<"fmov", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMOVDXHighr FMOVDXr FMOVDi FMOVDr FMOVHWr FMOVHXr FMOVHi FMOVHr FMOVSWr FMOVSi FMOVSr FMOVWHr FMOVWSr FMOVXDHighr FMOVXDr FMOVXHr FMOVv2f32_ns FMOVv2f64_ns FMOVv4f16_ns FMOVv4f32_ns FMOVv8f16_ns
+}
+
+def AArch64MIR_fmsb : AArch64MIR_TargetOp<"fmsb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMSB_ZPmZZ_D FMSB_ZPmZZ_H FMSB_ZPmZZ_S
+}
+
+def AArch64MIR_fmsub : AArch64MIR_TargetOp<"fmsub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMSUBDrrr FMSUBHrrr FMSUBSrrr
+}
+
+def AArch64MIR_fmul : AArch64MIR_TargetOp<"fmul", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMULDrr FMULHrr FMULSrr FMUL_2Z2Z_D FMUL_2Z2Z_H FMUL_2Z2Z_S FMUL_2ZZ_D FMUL_2ZZ_H FMUL_2ZZ_S FMUL_4Z4Z_D FMUL_4Z4Z_H FMUL_4Z4Z_S FMUL_4ZZ_D FMUL_4ZZ_H FMUL_4ZZ_S FMUL_ZPmI_D FMUL_ZPmI_H FMUL_ZPmI_S FMUL_ZPmZ_D FMUL_ZPmZ_H FMUL_ZPmZ_S FMUL_ZZZI_D FMUL_ZZZI_H FMUL_ZZZI_S FMUL_ZZZ_D FMUL_ZZZ_H FMUL_ZZZ_S FMULv1i16_indexed FMULv1i32_indexed FMULv1i64_indexed FMULv2f32 FMULv2f64 FMULv2i32_indexed FMULv2i64_indexed FMULv4f16 FMULv4f32 FMULv4i16_indexed FMULv4i32_indexed FMULv8f16 FMULv8i16_indexed
+}
+
+def AArch64MIR_fmulx : AArch64MIR_TargetOp<"fmulx", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FMULX16 FMULX32 FMULX64 FMULX_ZPmZ_D FMULX_ZPmZ_H FMULX_ZPmZ_S FMULXv1i16_indexed FMULXv1i32_indexed FMULXv1i64_indexed FMULXv2f32 FMULXv2f64 FMULXv2i32_indexed FMULXv2i64_indexed FMULXv4f16 FMULXv4f32 FMULXv4i16_indexed FMULXv4i32_indexed FMULXv8f16 FMULXv8i16_indexed
+}
+
+def AArch64MIR_fneg : AArch64MIR_TargetOp<"fneg", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FNEGDr FNEGHr FNEGSr FNEG_ZPmZ_D FNEG_ZPmZ_H FNEG_ZPmZ_S FNEG_ZPzZ_D FNEG_ZPzZ_H FNEG_ZPzZ_S FNEGv2f32 FNEGv2f64 FNEGv4f16 FNEGv4f32 FNEGv8f16
+}
+
+def AArch64MIR_fnmadd : AArch64MIR_TargetOp<"fnmadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FNMADDDrrr FNMADDHrrr FNMADDSrrr
+}
+
+def AArch64MIR_fnmad : AArch64MIR_TargetOp<"fnmad", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FNMAD_ZPmZZ_D FNMAD_ZPmZZ_H FNMAD_ZPmZZ_S
+}
+
+def AArch64MIR_fnmla : AArch64MIR_TargetOp<"fnmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FNMLA_ZPmZZ_D FNMLA_ZPmZZ_H FNMLA_ZPmZZ_S
+}
+
+def AArch64MIR_fnmls : AArch64MIR_TargetOp<"fnmls", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FNMLS_ZPmZZ_D FNMLS_ZPmZZ_H FNMLS_ZPmZZ_S
+}
+
+def AArch64MIR_fnmsb : AArch64MIR_TargetOp<"fnmsb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FNMSB_ZPmZZ_D FNMSB_ZPmZZ_H FNMSB_ZPmZZ_S
+}
+
+def AArch64MIR_fnmsub : AArch64MIR_TargetOp<"fnmsub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FNMSUBDrrr FNMSUBHrrr FNMSUBSrrr
+}
+
+def AArch64MIR_fnmul : AArch64MIR_TargetOp<"fnmul", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FNMULDrr FNMULHrr FNMULSrr
+}
+
+def AArch64MIR_frecpe : AArch64MIR_TargetOp<"frecpe", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRECPE_ZZ_D FRECPE_ZZ_H FRECPE_ZZ_S FRECPEv1f16 FRECPEv1i32 FRECPEv1i64 FRECPEv2f32 FRECPEv2f64 FRECPEv4f16 FRECPEv4f32 FRECPEv8f16
+}
+
+def AArch64MIR_frecps : AArch64MIR_TargetOp<"frecps", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRECPS16 FRECPS32 FRECPS64 FRECPS_ZZZ_D FRECPS_ZZZ_H FRECPS_ZZZ_S FRECPSv2f32 FRECPSv2f64 FRECPSv4f16 FRECPSv4f32 FRECPSv8f16
+}
+
+def AArch64MIR_frecpx : AArch64MIR_TargetOp<"frecpx", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRECPX_ZPmZ_D FRECPX_ZPmZ_H FRECPX_ZPmZ_S FRECPX_ZPzZ_D FRECPX_ZPzZ_H FRECPX_ZPzZ_S FRECPXv1f16 FRECPXv1i32 FRECPXv1i64
+}
+
+def AArch64MIR_frint32x : AArch64MIR_TargetOp<"frint32x", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINT32XDr FRINT32XSr FRINT32X_ZPmZ_D FRINT32X_ZPmZ_S FRINT32X_ZPzZ_D FRINT32X_ZPzZ_S FRINT32Xv2f32 FRINT32Xv2f64 FRINT32Xv4f32
+}
+
+def AArch64MIR_frint32z : AArch64MIR_TargetOp<"frint32z", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINT32ZDr FRINT32ZSr FRINT32Z_ZPmZ_D FRINT32Z_ZPmZ_S FRINT32Z_ZPzZ_D FRINT32Z_ZPzZ_S FRINT32Zv2f32 FRINT32Zv2f64 FRINT32Zv4f32
+}
+
+def AArch64MIR_frint64x : AArch64MIR_TargetOp<"frint64x", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINT64XDr FRINT64XSr FRINT64X_ZPmZ_D FRINT64X_ZPmZ_S FRINT64X_ZPzZ_D FRINT64X_ZPzZ_S FRINT64Xv2f32 FRINT64Xv2f64 FRINT64Xv4f32
+}
+
+def AArch64MIR_frint64z : AArch64MIR_TargetOp<"frint64z", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINT64ZDr FRINT64ZSr FRINT64Z_ZPmZ_D FRINT64Z_ZPmZ_S FRINT64Z_ZPzZ_D FRINT64Z_ZPzZ_S FRINT64Zv2f32 FRINT64Zv2f64 FRINT64Zv4f32
+}
+
+def AArch64MIR_frinta : AArch64MIR_TargetOp<"frinta", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINTADr FRINTAHr FRINTASr FRINTA_2Z2Z_S FRINTA_4Z4Z_S FRINTA_ZPmZ_D FRINTA_ZPmZ_H FRINTA_ZPmZ_S FRINTA_ZPzZ_D FRINTA_ZPzZ_H FRINTA_ZPzZ_S FRINTAv2f32 FRINTAv2f64 FRINTAv4f16 FRINTAv4f32 FRINTAv8f16
+}
+
+def AArch64MIR_frinti : AArch64MIR_TargetOp<"frinti", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINTIDr FRINTIHr FRINTISr FRINTI_ZPmZ_D FRINTI_ZPmZ_H FRINTI_ZPmZ_S FRINTI_ZPzZ_D FRINTI_ZPzZ_H FRINTI_ZPzZ_S FRINTIv2f32 FRINTIv2f64 FRINTIv4f16 FRINTIv4f32 FRINTIv8f16
+}
+
+def AArch64MIR_frintm : AArch64MIR_TargetOp<"frintm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINTMDr FRINTMHr FRINTMSr FRINTM_2Z2Z_S FRINTM_4Z4Z_S FRINTM_ZPmZ_D FRINTM_ZPmZ_H FRINTM_ZPmZ_S FRINTM_ZPzZ_D FRINTM_ZPzZ_H FRINTM_ZPzZ_S FRINTMv2f32 FRINTMv2f64 FRINTMv4f16 FRINTMv4f32 FRINTMv8f16
+}
+
+def AArch64MIR_frintn : AArch64MIR_TargetOp<"frintn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINTNDr FRINTNHr FRINTNSr FRINTN_2Z2Z_S FRINTN_4Z4Z_S FRINTN_ZPmZ_D FRINTN_ZPmZ_H FRINTN_ZPmZ_S FRINTN_ZPzZ_D FRINTN_ZPzZ_H FRINTN_ZPzZ_S FRINTNv2f32 FRINTNv2f64 FRINTNv4f16 FRINTNv4f32 FRINTNv8f16
+}
+
+def AArch64MIR_frintp : AArch64MIR_TargetOp<"frintp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINTPDr FRINTPHr FRINTPSr FRINTP_2Z2Z_S FRINTP_4Z4Z_S FRINTP_ZPmZ_D FRINTP_ZPmZ_H FRINTP_ZPmZ_S FRINTP_ZPzZ_D FRINTP_ZPzZ_H FRINTP_ZPzZ_S FRINTPv2f32 FRINTPv2f64 FRINTPv4f16 FRINTPv4f32 FRINTPv8f16
+}
+
+def AArch64MIR_frintx : AArch64MIR_TargetOp<"frintx", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINTXDr FRINTXHr FRINTXSr FRINTX_ZPmZ_D FRINTX_ZPmZ_H FRINTX_ZPmZ_S FRINTX_ZPzZ_D FRINTX_ZPzZ_H FRINTX_ZPzZ_S FRINTXv2f32 FRINTXv2f64 FRINTXv4f16 FRINTXv4f32 FRINTXv8f16
+}
+
+def AArch64MIR_frintz : AArch64MIR_TargetOp<"frintz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRINTZDr FRINTZHr FRINTZSr FRINTZ_ZPmZ_D FRINTZ_ZPmZ_H FRINTZ_ZPmZ_S FRINTZ_ZPzZ_D FRINTZ_ZPzZ_H FRINTZ_ZPzZ_S FRINTZv2f32 FRINTZv2f64 FRINTZv4f16 FRINTZv4f32 FRINTZv8f16
+}
+
+def AArch64MIR_frsqrte : AArch64MIR_TargetOp<"frsqrte", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRSQRTE_ZZ_D FRSQRTE_ZZ_H FRSQRTE_ZZ_S FRSQRTEv1f16 FRSQRTEv1i32 FRSQRTEv1i64 FRSQRTEv2f32 FRSQRTEv2f64 FRSQRTEv4f16 FRSQRTEv4f32 FRSQRTEv8f16
+}
+
+def AArch64MIR_frsqrts : AArch64MIR_TargetOp<"frsqrts", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FRSQRTS16 FRSQRTS32 FRSQRTS64 FRSQRTS_ZZZ_D FRSQRTS_ZZZ_H FRSQRTS_ZZZ_S FRSQRTSv2f32 FRSQRTSv2f64 FRSQRTSv4f16 FRSQRTSv4f32 FRSQRTSv8f16
+}
+
+def AArch64MIR_fscale : AArch64MIR_TargetOp<"fscale", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FSCALE_2Z2Z_D FSCALE_2Z2Z_H FSCALE_2Z2Z_S FSCALE_2ZZ_D FSCALE_2ZZ_H FSCALE_2ZZ_S FSCALE_4Z4Z_D FSCALE_4Z4Z_H FSCALE_4Z4Z_S FSCALE_4ZZ_D FSCALE_4ZZ_H FSCALE_4ZZ_S FSCALE_ZPmZ_D FSCALE_ZPmZ_H FSCALE_ZPmZ_S FSCALEv2f32 FSCALEv2f64 FSCALEv4f16 FSCALEv4f32 FSCALEv8f16
+}
+
+def AArch64MIR_fsqrt : AArch64MIR_TargetOp<"fsqrt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FSQRTDr FSQRTHr FSQRTSr FSQRT_ZPZz_D FSQRT_ZPZz_H FSQRT_ZPZz_S FSQRT_ZPmZ_D FSQRT_ZPmZ_H FSQRT_ZPmZ_S FSQRTv2f32 FSQRTv2f64 FSQRTv4f16 FSQRTv4f32 FSQRTv8f16
+}
+
+def AArch64MIR_fsub : AArch64MIR_TargetOp<"fsub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FSUBDrr FSUBHrr FSUBSrr FSUB_VG2_M2Z_D FSUB_VG2_M2Z_H FSUB_VG2_M2Z_S FSUB_VG4_M4Z_D FSUB_VG4_M4Z_H FSUB_VG4_M4Z_S FSUB_ZPmI_D FSUB_ZPmI_H FSUB_ZPmI_S FSUB_ZPmZ_D FSUB_ZPmZ_H FSUB_ZPmZ_S FSUB_ZZZ_D FSUB_ZZZ_H FSUB_ZZZ_S FSUBv2f32 FSUBv2f64 FSUBv4f16 FSUBv4f32 FSUBv8f16
+}
+
+def AArch64MIR_fsubr : AArch64MIR_TargetOp<"fsubr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FSUBR_ZPmI_D FSUBR_ZPmI_H FSUBR_ZPmI_S FSUBR_ZPmZ_D FSUBR_ZPmZ_H FSUBR_ZPmZ_S
+}
+
+def AArch64MIR_ftmad : AArch64MIR_TargetOp<"ftmad", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FTMAD_ZZI_D FTMAD_ZZI_H FTMAD_ZZI_S
+}
+
+def AArch64MIR_ftmopa : AArch64MIR_TargetOp<"ftmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FTMOPA_M2ZZZI_BtoH FTMOPA_M2ZZZI_BtoS FTMOPA_M2ZZZI_HtoH FTMOPA_M2ZZZI_HtoS FTMOPA_M2ZZZI_StoS
+}
+
+def AArch64MIR_ftsmul : AArch64MIR_TargetOp<"ftsmul", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FTSMUL_ZZZ_D FTSMUL_ZZZ_H FTSMUL_ZZZ_S
+}
+
+def AArch64MIR_ftssel : AArch64MIR_TargetOp<"ftssel", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FTSSEL_ZZZ_D FTSSEL_ZZZ_H FTSSEL_ZZZ_S
+}
+
+def AArch64MIR_fvdotb : AArch64MIR_TargetOp<"fvdotb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FVDOTB_VG4_M2ZZI_BtoS
+}
+
+def AArch64MIR_fvdott : AArch64MIR_TargetOp<"fvdott", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FVDOTT_VG4_M2ZZI_BtoS
+}
+
+def AArch64MIR_fvdot : AArch64MIR_TargetOp<"fvdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: FVDOT_VG2_M2ZZI_BtoH FVDOT_VG2_M2ZZI_HtoS
+}
+
+def AArch64MIR_gcspopcx : AArch64MIR_TargetOp<"gcspopcx", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSPOPCX
+}
+
+def AArch64MIR_gcspopm : AArch64MIR_TargetOp<"gcspopm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSPOPM
+}
+
+def AArch64MIR_gcspopx : AArch64MIR_TargetOp<"gcspopx", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSPOPX
+}
+
+def AArch64MIR_gcspushm : AArch64MIR_TargetOp<"gcspushm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSPUSHM
+}
+
+def AArch64MIR_gcspushx : AArch64MIR_TargetOp<"gcspushx", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSPUSHX
+}
+
+def AArch64MIR_gcsss1 : AArch64MIR_TargetOp<"gcsss1", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSSS1
+}
+
+def AArch64MIR_gcsss2 : AArch64MIR_TargetOp<"gcsss2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSSS2
+}
+
+def AArch64MIR_gcsstr : AArch64MIR_TargetOp<"gcsstr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSSTR
+}
+
+def AArch64MIR_gcssttr : AArch64MIR_TargetOp<"gcssttr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GCSSTTR
+}
+
+def AArch64MIR_ld1b : AArch64MIR_TargetOp<"ld1b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLD1B_D GLD1B_D_IMM GLD1B_D_SXTW GLD1B_D_UXTW GLD1B_S_IMM GLD1B_S_SXTW GLD1B_S_UXTW LD1B LD1B_2Z LD1B_2Z_IMM LD1B_2Z_STRIDED LD1B_2Z_STRIDED_IMM LD1B_4Z LD1B_4Z_IMM LD1B_4Z_STRIDED LD1B_4Z_STRIDED_IMM LD1B_D LD1B_D_IMM LD1B_H LD1B_H_IMM LD1B_IMM LD1B_S LD1B_S_IMM LD1_MXIPXX_H_B LD1_MXIPXX_V_B
+}
+
+def AArch64MIR_ld1d : AArch64MIR_TargetOp<"ld1d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLD1D GLD1D_IMM GLD1D_SCALED GLD1D_SXTW GLD1D_SXTW_SCALED GLD1D_UXTW GLD1D_UXTW_SCALED LD1D LD1D_2Z LD1D_2Z_IMM LD1D_2Z_STRIDED LD1D_2Z_STRIDED_IMM LD1D_4Z LD1D_4Z_IMM LD1D_4Z_STRIDED LD1D_4Z_STRIDED_IMM LD1D_IMM LD1D_Q LD1D_Q_IMM LD1_MXIPXX_H_D LD1_MXIPXX_V_D
+}
+
+def AArch64MIR_ld1h : AArch64MIR_TargetOp<"ld1h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLD1H_D GLD1H_D_IMM GLD1H_D_SCALED GLD1H_D_SXTW GLD1H_D_SXTW_SCALED GLD1H_D_UXTW GLD1H_D_UXTW_SCALED GLD1H_S_IMM GLD1H_S_SXTW GLD1H_S_SXTW_SCALED GLD1H_S_UXTW GLD1H_S_UXTW_SCALED LD1H LD1H_2Z LD1H_2Z_IMM LD1H_2Z_STRIDED LD1H_2Z_STRIDED_IMM LD1H_4Z LD1H_4Z_IMM LD1H_4Z_STRIDED LD1H_4Z_STRIDED_IMM LD1H_D LD1H_D_IMM LD1H_IMM LD1H_S LD1H_S_IMM LD1_MXIPXX_H_H LD1_MXIPXX_V_H
+}
+
+def AArch64MIR_ld1q : AArch64MIR_TargetOp<"ld1q", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLD1Q LD1_MXIPXX_H_Q LD1_MXIPXX_V_Q
+}
+
+def AArch64MIR_ld1sb : AArch64MIR_TargetOp<"ld1sb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLD1SB_D GLD1SB_D_IMM GLD1SB_D_SXTW GLD1SB_D_UXTW GLD1SB_S_IMM GLD1SB_S_SXTW GLD1SB_S_UXTW LD1SB_D LD1SB_D_IMM LD1SB_H LD1SB_H_IMM LD1SB_S LD1SB_S_IMM
+}
+
+def AArch64MIR_ld1sh : AArch64MIR_TargetOp<"ld1sh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLD1SH_D GLD1SH_D_IMM GLD1SH_D_SCALED GLD1SH_D_SXTW GLD1SH_D_SXTW_SCALED GLD1SH_D_UXTW GLD1SH_D_UXTW_SCALED GLD1SH_S_IMM GLD1SH_S_SXTW GLD1SH_S_SXTW_SCALED GLD1SH_S_UXTW GLD1SH_S_UXTW_SCALED LD1SH_D LD1SH_D_IMM LD1SH_S LD1SH_S_IMM
+}
+
+def AArch64MIR_ld1sw : AArch64MIR_TargetOp<"ld1sw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLD1SW_D GLD1SW_D_IMM GLD1SW_D_SCALED GLD1SW_D_SXTW GLD1SW_D_SXTW_SCALED GLD1SW_D_UXTW GLD1SW_D_UXTW_SCALED LD1SW_D LD1SW_D_IMM
+}
+
+def AArch64MIR_ld1w : AArch64MIR_TargetOp<"ld1w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLD1W_D GLD1W_D_IMM GLD1W_D_SCALED GLD1W_D_SXTW GLD1W_D_SXTW_SCALED GLD1W_D_UXTW GLD1W_D_UXTW_SCALED GLD1W_IMM GLD1W_SXTW GLD1W_SXTW_SCALED GLD1W_UXTW GLD1W_UXTW_SCALED LD1W LD1W_2Z LD1W_2Z_IMM LD1W_2Z_STRIDED LD1W_2Z_STRIDED_IMM LD1W_4Z LD1W_4Z_IMM LD1W_4Z_STRIDED LD1W_4Z_STRIDED_IMM LD1W_D LD1W_D_IMM LD1W_IMM LD1W_Q LD1W_Q_IMM LD1_MXIPXX_H_S LD1_MXIPXX_V_S
+}
+
+def AArch64MIR_ldff1b : AArch64MIR_TargetOp<"ldff1b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLDFF1B_D GLDFF1B_D_IMM GLDFF1B_D_SXTW GLDFF1B_D_UXTW GLDFF1B_S_IMM GLDFF1B_S_SXTW GLDFF1B_S_UXTW LDFF1B LDFF1B_D LDFF1B_H LDFF1B_S
+}
+
+def AArch64MIR_ldff1d : AArch64MIR_TargetOp<"ldff1d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLDFF1D GLDFF1D_IMM GLDFF1D_SCALED GLDFF1D_SXTW GLDFF1D_SXTW_SCALED GLDFF1D_UXTW GLDFF1D_UXTW_SCALED LDFF1D
+}
+
+def AArch64MIR_ldff1h : AArch64MIR_TargetOp<"ldff1h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLDFF1H_D GLDFF1H_D_IMM GLDFF1H_D_SCALED GLDFF1H_D_SXTW GLDFF1H_D_SXTW_SCALED GLDFF1H_D_UXTW GLDFF1H_D_UXTW_SCALED GLDFF1H_S_IMM GLDFF1H_S_SXTW GLDFF1H_S_SXTW_SCALED GLDFF1H_S_UXTW GLDFF1H_S_UXTW_SCALED LDFF1H LDFF1H_D LDFF1H_S
+}
+
+def AArch64MIR_ldff1sb : AArch64MIR_TargetOp<"ldff1sb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLDFF1SB_D GLDFF1SB_D_IMM GLDFF1SB_D_SXTW GLDFF1SB_D_UXTW GLDFF1SB_S_IMM GLDFF1SB_S_SXTW GLDFF1SB_S_UXTW LDFF1SB_D LDFF1SB_H LDFF1SB_S
+}
+
+def AArch64MIR_ldff1sh : AArch64MIR_TargetOp<"ldff1sh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLDFF1SH_D GLDFF1SH_D_IMM GLDFF1SH_D_SCALED GLDFF1SH_D_SXTW GLDFF1SH_D_SXTW_SCALED GLDFF1SH_D_UXTW GLDFF1SH_D_UXTW_SCALED GLDFF1SH_S_IMM GLDFF1SH_S_SXTW GLDFF1SH_S_SXTW_SCALED GLDFF1SH_S_UXTW GLDFF1SH_S_UXTW_SCALED LDFF1SH_D LDFF1SH_S
+}
+
+def AArch64MIR_ldff1sw : AArch64MIR_TargetOp<"ldff1sw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLDFF1SW_D GLDFF1SW_D_IMM GLDFF1SW_D_SCALED GLDFF1SW_D_SXTW GLDFF1SW_D_SXTW_SCALED GLDFF1SW_D_UXTW GLDFF1SW_D_UXTW_SCALED LDFF1SW_D
+}
+
+def AArch64MIR_ldff1w : AArch64MIR_TargetOp<"ldff1w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GLDFF1W_D GLDFF1W_D_IMM GLDFF1W_D_SCALED GLDFF1W_D_SXTW GLDFF1W_D_SXTW_SCALED GLDFF1W_D_UXTW GLDFF1W_D_UXTW_SCALED GLDFF1W_IMM GLDFF1W_SXTW GLDFF1W_SXTW_SCALED GLDFF1W_UXTW GLDFF1W_UXTW_SCALED LDFF1W LDFF1W_D
+}
+
+def AArch64MIR_gmi : AArch64MIR_TargetOp<"gmi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: GMI
+}
+
+def AArch64MIR_hinte : AArch64MIR_TargetOp<"hinte", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: HINTE
+}
+
+def AArch64MIR_histcnt : AArch64MIR_TargetOp<"histcnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: HISTCNT_ZPzZZ_D HISTCNT_ZPzZZ_S
+}
+
+def AArch64MIR_histseg : AArch64MIR_TargetOp<"histseg", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: HISTSEG_ZZZ
+}
+
+def AArch64MIR_hlt : AArch64MIR_TargetOp<"hlt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: HLT
+}
+
+def AArch64MIR_hvc : AArch64MIR_TargetOp<"hvc", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: HVC
+}
+
+def AArch64MIR_incb : AArch64MIR_TargetOp<"incb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: INCB_XPiI
+}
+
+def AArch64MIR_incd : AArch64MIR_TargetOp<"incd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: INCD_XPiI INCD_ZPiI
+}
+
+def AArch64MIR_inch : AArch64MIR_TargetOp<"inch", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: INCH_XPiI INCH_ZPiI
+}
+
+def AArch64MIR_incp : AArch64MIR_TargetOp<"incp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: INCP_XP_B INCP_XP_D INCP_XP_H INCP_XP_S INCP_ZP_D INCP_ZP_H INCP_ZP_S
+}
+
+def AArch64MIR_incw : AArch64MIR_TargetOp<"incw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: INCW_XPiI INCW_ZPiI
+}
+
+def AArch64MIR_index : AArch64MIR_TargetOp<"index", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: INDEX_II_B INDEX_II_D INDEX_II_H INDEX_II_S INDEX_IR_B INDEX_IR_D INDEX_IR_H INDEX_IR_S INDEX_RI_B INDEX_RI_D INDEX_RI_H INDEX_RI_S INDEX_RR_B INDEX_RR_D INDEX_RR_H INDEX_RR_S
+}
+
+def AArch64MIR_insr : AArch64MIR_TargetOp<"insr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: INSR_ZR_B INSR_ZR_D INSR_ZR_H INSR_ZR_S INSR_ZV_B INSR_ZV_D INSR_ZV_H INSR_ZV_S
+}
+
+def AArch64MIR_ins : AArch64MIR_TargetOp<"ins", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: INSvi8gpr INSvi8lane INSvi16gpr INSvi16lane INSvi32gpr INSvi32lane INSvi64gpr INSvi64lane
+}
+
+def AArch64MIR_irg : AArch64MIR_TargetOp<"irg", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: IRG
+}
+
+def AArch64MIR_isb : AArch64MIR_TargetOp<"isb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ISB
+}
+
+def AArch64MIR_lasta : AArch64MIR_TargetOp<"lasta", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LASTA_RPZ_B LASTA_RPZ_D LASTA_RPZ_H LASTA_RPZ_S LASTA_VPZ_B LASTA_VPZ_D LASTA_VPZ_H LASTA_VPZ_S
+}
+
+def AArch64MIR_lastb : AArch64MIR_TargetOp<"lastb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LASTB_RPZ_B LASTB_RPZ_D LASTB_RPZ_H LASTB_RPZ_S LASTB_VPZ_B LASTB_VPZ_D LASTB_VPZ_H LASTB_VPZ_S
+}
+
+def AArch64MIR_lastp : AArch64MIR_TargetOp<"lastp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LASTP_XPP_B LASTP_XPP_D LASTP_XPP_H LASTP_XPP_S
+}
+
+def AArch64MIR_ld1 : AArch64MIR_TargetOp<"ld1", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1Fourv1d LD1Fourv1d_POST LD1Fourv2d LD1Fourv2d_POST LD1Fourv2s LD1Fourv2s_POST LD1Fourv4h LD1Fourv4h_POST LD1Fourv4s LD1Fourv4s_POST LD1Fourv8b LD1Fourv8b_POST LD1Fourv8h LD1Fourv8h_POST LD1Fourv16b LD1Fourv16b_POST LD1Onev1d LD1Onev1d_POST LD1Onev2d LD1Onev2d_POST LD1Onev2s LD1Onev2s_POST LD1Onev4h LD1Onev4h_POST LD1Onev4s LD1Onev4s_POST LD1Onev8b LD1Onev8b_POST LD1Onev8h LD1Onev8h_POST LD1Onev16b LD1Onev16b_POST LD1Threev1d LD1Threev1d_POST LD1Threev2d LD1Threev2d_POST LD1Threev2s LD1Threev2s_POST LD1Threev4h LD1Threev4h_POST LD1Threev4s LD1Threev4s_POST LD1Threev8b LD1Threev8b_POST LD1Threev8h LD1Threev8h_POST LD1Threev16b LD1Threev16b_POST LD1Twov1d LD1Twov1d_POST LD1Twov2d LD1Twov2d_POST LD1Twov2s LD1Twov2s_POST LD1Twov4h LD1Twov4h_POST LD1Twov4s LD1Twov4s_POST LD1Twov8b LD1Twov8b_POST LD1Twov8h LD1Twov8h_POST LD1Twov16b LD1Twov16b_POST LD1i8 LD1i8_POST LD1i16 LD1i16_POST LD1i32 LD1i32_POST LD1i64 LD1i64_POST
+}
+
+def AArch64MIR_ld1rb : AArch64MIR_TargetOp<"ld1rb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RB_D_IMM LD1RB_H_IMM LD1RB_IMM LD1RB_S_IMM
+}
+
+def AArch64MIR_ld1rd : AArch64MIR_TargetOp<"ld1rd", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RD_IMM
+}
+
+def AArch64MIR_ld1rh : AArch64MIR_TargetOp<"ld1rh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RH_D_IMM LD1RH_IMM LD1RH_S_IMM
+}
+
+def AArch64MIR_ld1rob : AArch64MIR_TargetOp<"ld1rob", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RO_B LD1RO_B_IMM
+}
+
+def AArch64MIR_ld1rod : AArch64MIR_TargetOp<"ld1rod", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RO_D LD1RO_D_IMM
+}
+
+def AArch64MIR_ld1roh : AArch64MIR_TargetOp<"ld1roh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RO_H LD1RO_H_IMM
+}
+
+def AArch64MIR_ld1row : AArch64MIR_TargetOp<"ld1row", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RO_W LD1RO_W_IMM
+}
+
+def AArch64MIR_ld1rqb : AArch64MIR_TargetOp<"ld1rqb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RQ_B LD1RQ_B_IMM
+}
+
+def AArch64MIR_ld1rqd : AArch64MIR_TargetOp<"ld1rqd", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RQ_D LD1RQ_D_IMM
+}
+
+def AArch64MIR_ld1rqh : AArch64MIR_TargetOp<"ld1rqh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RQ_H LD1RQ_H_IMM
+}
+
+def AArch64MIR_ld1rqw : AArch64MIR_TargetOp<"ld1rqw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RQ_W LD1RQ_W_IMM
+}
+
+def AArch64MIR_ld1rsb : AArch64MIR_TargetOp<"ld1rsb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RSB_D_IMM LD1RSB_H_IMM LD1RSB_S_IMM
+}
+
+def AArch64MIR_ld1rsh : AArch64MIR_TargetOp<"ld1rsh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RSH_D_IMM LD1RSH_S_IMM
+}
+
+def AArch64MIR_ld1rsw : AArch64MIR_TargetOp<"ld1rsw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RSW_IMM
+}
+
+def AArch64MIR_ld1rw : AArch64MIR_TargetOp<"ld1rw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1RW_D_IMM LD1RW_IMM
+}
+
+def AArch64MIR_ld1r : AArch64MIR_TargetOp<"ld1r", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD1Rv1d LD1Rv1d_POST LD1Rv2d LD1Rv2d_POST LD1Rv2s LD1Rv2s_POST LD1Rv4h LD1Rv4h_POST LD1Rv4s LD1Rv4s_POST LD1Rv8b LD1Rv8b_POST LD1Rv8h LD1Rv8h_POST LD1Rv16b LD1Rv16b_POST
+}
+
+def AArch64MIR_ld2b : AArch64MIR_TargetOp<"ld2b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD2B LD2B_IMM
+}
+
+def AArch64MIR_ld2d : AArch64MIR_TargetOp<"ld2d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD2D LD2D_IMM
+}
+
+def AArch64MIR_ld2h : AArch64MIR_TargetOp<"ld2h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD2H LD2H_IMM
+}
+
+def AArch64MIR_ld2q : AArch64MIR_TargetOp<"ld2q", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD2Q LD2Q_IMM
+}
+
+def AArch64MIR_ld2r : AArch64MIR_TargetOp<"ld2r", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD2Rv1d LD2Rv1d_POST LD2Rv2d LD2Rv2d_POST LD2Rv2s LD2Rv2s_POST LD2Rv4h LD2Rv4h_POST LD2Rv4s LD2Rv4s_POST LD2Rv8b LD2Rv8b_POST LD2Rv8h LD2Rv8h_POST LD2Rv16b LD2Rv16b_POST
+}
+
+def AArch64MIR_ld2 : AArch64MIR_TargetOp<"ld2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD2Twov2d LD2Twov2d_POST LD2Twov2s LD2Twov2s_POST LD2Twov4h LD2Twov4h_POST LD2Twov4s LD2Twov4s_POST LD2Twov8b LD2Twov8b_POST LD2Twov8h LD2Twov8h_POST LD2Twov16b LD2Twov16b_POST LD2i8 LD2i8_POST LD2i16 LD2i16_POST LD2i32 LD2i32_POST LD2i64 LD2i64_POST
+}
+
+def AArch64MIR_ld2w : AArch64MIR_TargetOp<"ld2w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD2W LD2W_IMM
+}
+
+def AArch64MIR_ld3b : AArch64MIR_TargetOp<"ld3b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD3B LD3B_IMM
+}
+
+def AArch64MIR_ld3d : AArch64MIR_TargetOp<"ld3d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD3D LD3D_IMM
+}
+
+def AArch64MIR_ld3h : AArch64MIR_TargetOp<"ld3h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD3H LD3H_IMM
+}
+
+def AArch64MIR_ld3q : AArch64MIR_TargetOp<"ld3q", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD3Q LD3Q_IMM
+}
+
+def AArch64MIR_ld3r : AArch64MIR_TargetOp<"ld3r", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD3Rv1d LD3Rv1d_POST LD3Rv2d LD3Rv2d_POST LD3Rv2s LD3Rv2s_POST LD3Rv4h LD3Rv4h_POST LD3Rv4s LD3Rv4s_POST LD3Rv8b LD3Rv8b_POST LD3Rv8h LD3Rv8h_POST LD3Rv16b LD3Rv16b_POST
+}
+
+def AArch64MIR_ld3 : AArch64MIR_TargetOp<"ld3", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD3Threev2d LD3Threev2d_POST LD3Threev2s LD3Threev2s_POST LD3Threev4h LD3Threev4h_POST LD3Threev4s LD3Threev4s_POST LD3Threev8b LD3Threev8b_POST LD3Threev8h LD3Threev8h_POST LD3Threev16b LD3Threev16b_POST LD3i8 LD3i8_POST LD3i16 LD3i16_POST LD3i32 LD3i32_POST LD3i64 LD3i64_POST
+}
+
+def AArch64MIR_ld3w : AArch64MIR_TargetOp<"ld3w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD3W LD3W_IMM
+}
+
+def AArch64MIR_ld4b : AArch64MIR_TargetOp<"ld4b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD4B LD4B_IMM
+}
+
+def AArch64MIR_ld4d : AArch64MIR_TargetOp<"ld4d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD4D LD4D_IMM
+}
+
+def AArch64MIR_ld4 : AArch64MIR_TargetOp<"ld4", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD4Fourv2d LD4Fourv2d_POST LD4Fourv2s LD4Fourv2s_POST LD4Fourv4h LD4Fourv4h_POST LD4Fourv4s LD4Fourv4s_POST LD4Fourv8b LD4Fourv8b_POST LD4Fourv8h LD4Fourv8h_POST LD4Fourv16b LD4Fourv16b_POST LD4i8 LD4i8_POST LD4i16 LD4i16_POST LD4i32 LD4i32_POST LD4i64 LD4i64_POST
+}
+
+def AArch64MIR_ld4h : AArch64MIR_TargetOp<"ld4h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD4H LD4H_IMM
+}
+
+def AArch64MIR_ld4q : AArch64MIR_TargetOp<"ld4q", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD4Q LD4Q_IMM
+}
+
+def AArch64MIR_ld4r : AArch64MIR_TargetOp<"ld4r", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD4Rv1d LD4Rv1d_POST LD4Rv2d LD4Rv2d_POST LD4Rv2s LD4Rv2s_POST LD4Rv4h LD4Rv4h_POST LD4Rv4s LD4Rv4s_POST LD4Rv8b LD4Rv8b_POST LD4Rv8h LD4Rv8h_POST LD4Rv16b LD4Rv16b_POST
+}
+
+def AArch64MIR_ld4w : AArch64MIR_TargetOp<"ld4w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD4W LD4W_IMM
+}
+
+def AArch64MIR_ld64b : AArch64MIR_TargetOp<"ld64b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LD64B
+}
+
+def AArch64MIR_ldaddab : AArch64MIR_TargetOp<"ldaddab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDAB
+}
+
+def AArch64MIR_ldaddah : AArch64MIR_TargetOp<"ldaddah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDAH
+}
+
+def AArch64MIR_ldaddalb : AArch64MIR_TargetOp<"ldaddalb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDALB
+}
+
+def AArch64MIR_ldaddalh : AArch64MIR_TargetOp<"ldaddalh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDALH
+}
+
+def AArch64MIR_ldaddal : AArch64MIR_TargetOp<"ldaddal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDALW LDADDALX
+}
+
+def AArch64MIR_ldadda : AArch64MIR_TargetOp<"ldadda", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDAW LDADDAX
+}
+
+def AArch64MIR_ldaddb : AArch64MIR_TargetOp<"ldaddb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDB
+}
+
+def AArch64MIR_ldaddh : AArch64MIR_TargetOp<"ldaddh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDH
+}
+
+def AArch64MIR_ldaddlb : AArch64MIR_TargetOp<"ldaddlb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDLB
+}
+
+def AArch64MIR_ldaddlh : AArch64MIR_TargetOp<"ldaddlh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDLH
+}
+
+def AArch64MIR_ldaddl : AArch64MIR_TargetOp<"ldaddl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDLW LDADDLX
+}
+
+def AArch64MIR_ldadd : AArch64MIR_TargetOp<"ldadd", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDADDW LDADDX
+}
+
+def AArch64MIR_ldap1 : AArch64MIR_TargetOp<"ldap1", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAP1
+}
+
+def AArch64MIR_ldapp : AArch64MIR_TargetOp<"ldapp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPPi
+}
+
+def AArch64MIR_ldaprb : AArch64MIR_TargetOp<"ldaprb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPRB
+}
+
+def AArch64MIR_ldaprh : AArch64MIR_TargetOp<"ldaprh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPRH
+}
+
+def AArch64MIR_ldapr : AArch64MIR_TargetOp<"ldapr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPRW LDAPRWpost LDAPRX LDAPRXpost
+}
+
+def AArch64MIR_ldapurb : AArch64MIR_TargetOp<"ldapurb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPURBi
+}
+
+def AArch64MIR_ldapurh : AArch64MIR_TargetOp<"ldapurh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPURHi
+}
+
+def AArch64MIR_ldapursb : AArch64MIR_TargetOp<"ldapursb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPURSBWi LDAPURSBXi
+}
+
+def AArch64MIR_ldapursh : AArch64MIR_TargetOp<"ldapursh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPURSHWi LDAPURSHXi
+}
+
+def AArch64MIR_ldapursw : AArch64MIR_TargetOp<"ldapursw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPURSWi
+}
+
+def AArch64MIR_ldapur : AArch64MIR_TargetOp<"ldapur", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPURXi LDAPURbi LDAPURdi LDAPURhi LDAPURi LDAPURqi LDAPURsi
+}
+
+def AArch64MIR_ldap : AArch64MIR_TargetOp<"ldap", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAPi
+}
+
+def AArch64MIR_ldarb : AArch64MIR_TargetOp<"ldarb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDARB
+}
+
+def AArch64MIR_ldarh : AArch64MIR_TargetOp<"ldarh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDARH
+}
+
+def AArch64MIR_ldar : AArch64MIR_TargetOp<"ldar", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDARW LDARX
+}
+
+def AArch64MIR_ldatxr : AArch64MIR_TargetOp<"ldatxr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDATXRW LDATXRX
+}
+
+def AArch64MIR_ldaxp : AArch64MIR_TargetOp<"ldaxp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAXPW LDAXPX
+}
+
+def AArch64MIR_ldaxrb : AArch64MIR_TargetOp<"ldaxrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAXRB
+}
+
+def AArch64MIR_ldaxrh : AArch64MIR_TargetOp<"ldaxrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAXRH
+}
+
+def AArch64MIR_ldaxr : AArch64MIR_TargetOp<"ldaxr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDAXRW LDAXRX
+}
+
+def AArch64MIR_ldbfadd : AArch64MIR_TargetOp<"ldbfadd", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFADD
+}
+
+def AArch64MIR_ldbfadda : AArch64MIR_TargetOp<"ldbfadda", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFADDA
+}
+
+def AArch64MIR_ldbfaddal : AArch64MIR_TargetOp<"ldbfaddal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFADDAL
+}
+
+def AArch64MIR_ldbfaddl : AArch64MIR_TargetOp<"ldbfaddl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFADDL
+}
+
+def AArch64MIR_ldbfmax : AArch64MIR_TargetOp<"ldbfmax", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMAX
+}
+
+def AArch64MIR_ldbfmaxa : AArch64MIR_TargetOp<"ldbfmaxa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMAXA
+}
+
+def AArch64MIR_ldbfmaxal : AArch64MIR_TargetOp<"ldbfmaxal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMAXAL
+}
+
+def AArch64MIR_ldbfmaxl : AArch64MIR_TargetOp<"ldbfmaxl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMAXL
+}
+
+def AArch64MIR_ldbfmaxnm : AArch64MIR_TargetOp<"ldbfmaxnm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMAXNM
+}
+
+def AArch64MIR_ldbfmaxnma : AArch64MIR_TargetOp<"ldbfmaxnma", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMAXNMA
+}
+
+def AArch64MIR_ldbfmaxnmal : AArch64MIR_TargetOp<"ldbfmaxnmal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMAXNMAL
+}
+
+def AArch64MIR_ldbfmaxnml : AArch64MIR_TargetOp<"ldbfmaxnml", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMAXNML
+}
+
+def AArch64MIR_ldbfmin : AArch64MIR_TargetOp<"ldbfmin", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMIN
+}
+
+def AArch64MIR_ldbfmina : AArch64MIR_TargetOp<"ldbfmina", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMINA
+}
+
+def AArch64MIR_ldbfminal : AArch64MIR_TargetOp<"ldbfminal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMINAL
+}
+
+def AArch64MIR_ldbfminl : AArch64MIR_TargetOp<"ldbfminl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMINL
+}
+
+def AArch64MIR_ldbfminnm : AArch64MIR_TargetOp<"ldbfminnm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMINNM
+}
+
+def AArch64MIR_ldbfminnma : AArch64MIR_TargetOp<"ldbfminnma", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMINNMA
+}
+
+def AArch64MIR_ldbfminnmal : AArch64MIR_TargetOp<"ldbfminnmal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMINNMAL
+}
+
+def AArch64MIR_ldbfminnml : AArch64MIR_TargetOp<"ldbfminnml", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDBFMINNML
+}
+
+def AArch64MIR_ldclrab : AArch64MIR_TargetOp<"ldclrab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRAB
+}
+
+def AArch64MIR_ldclrah : AArch64MIR_TargetOp<"ldclrah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRAH
+}
+
+def AArch64MIR_ldclralb : AArch64MIR_TargetOp<"ldclralb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRALB
+}
+
+def AArch64MIR_ldclralh : AArch64MIR_TargetOp<"ldclralh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRALH
+}
+
+def AArch64MIR_ldclral : AArch64MIR_TargetOp<"ldclral", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRALW LDCLRALX
+}
+
+def AArch64MIR_ldclra : AArch64MIR_TargetOp<"ldclra", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRAW LDCLRAX
+}
+
+def AArch64MIR_ldclrb : AArch64MIR_TargetOp<"ldclrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRB
+}
+
+def AArch64MIR_ldclrh : AArch64MIR_TargetOp<"ldclrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRH
+}
+
+def AArch64MIR_ldclrlb : AArch64MIR_TargetOp<"ldclrlb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRLB
+}
+
+def AArch64MIR_ldclrlh : AArch64MIR_TargetOp<"ldclrlh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRLH
+}
+
+def AArch64MIR_ldclrl : AArch64MIR_TargetOp<"ldclrl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRLW LDCLRLX
+}
+
+def AArch64MIR_ldclrp : AArch64MIR_TargetOp<"ldclrp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRP
+}
+
+def AArch64MIR_ldclrpa : AArch64MIR_TargetOp<"ldclrpa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRPA
+}
+
+def AArch64MIR_ldclrpal : AArch64MIR_TargetOp<"ldclrpal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRPAL
+}
+
+def AArch64MIR_ldclrpl : AArch64MIR_TargetOp<"ldclrpl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRPL
+}
+
+def AArch64MIR_ldclr : AArch64MIR_TargetOp<"ldclr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDCLRW LDCLRX
+}
+
+def AArch64MIR_ldeorab : AArch64MIR_TargetOp<"ldeorab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORAB
+}
+
+def AArch64MIR_ldeorah : AArch64MIR_TargetOp<"ldeorah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORAH
+}
+
+def AArch64MIR_ldeoralb : AArch64MIR_TargetOp<"ldeoralb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORALB
+}
+
+def AArch64MIR_ldeoralh : AArch64MIR_TargetOp<"ldeoralh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORALH
+}
+
+def AArch64MIR_ldeoral : AArch64MIR_TargetOp<"ldeoral", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORALW LDEORALX
+}
+
+def AArch64MIR_ldeora : AArch64MIR_TargetOp<"ldeora", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORAW LDEORAX
+}
+
+def AArch64MIR_ldeorb : AArch64MIR_TargetOp<"ldeorb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORB
+}
+
+def AArch64MIR_ldeorh : AArch64MIR_TargetOp<"ldeorh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORH
+}
+
+def AArch64MIR_ldeorlb : AArch64MIR_TargetOp<"ldeorlb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORLB
+}
+
+def AArch64MIR_ldeorlh : AArch64MIR_TargetOp<"ldeorlh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORLH
+}
+
+def AArch64MIR_ldeorl : AArch64MIR_TargetOp<"ldeorl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORLW LDEORLX
+}
+
+def AArch64MIR_ldeor : AArch64MIR_TargetOp<"ldeor", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDEORW LDEORX
+}
+
+def AArch64MIR_ldfadda : AArch64MIR_TargetOp<"ldfadda", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFADDAD LDFADDAH LDFADDAS
+}
+
+def AArch64MIR_ldfaddal : AArch64MIR_TargetOp<"ldfaddal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFADDALD LDFADDALH LDFADDALS
+}
+
+def AArch64MIR_ldfadd : AArch64MIR_TargetOp<"ldfadd", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFADDD LDFADDH LDFADDS
+}
+
+def AArch64MIR_ldfaddl : AArch64MIR_TargetOp<"ldfaddl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFADDLD LDFADDLH LDFADDLS
+}
+
+def AArch64MIR_ldfmaxa : AArch64MIR_TargetOp<"ldfmaxa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMAXAD LDFMAXAH LDFMAXAS
+}
+
+def AArch64MIR_ldfmaxal : AArch64MIR_TargetOp<"ldfmaxal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMAXALD LDFMAXALH LDFMAXALS
+}
+
+def AArch64MIR_ldfmax : AArch64MIR_TargetOp<"ldfmax", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMAXD LDFMAXH LDFMAXS
+}
+
+def AArch64MIR_ldfmaxl : AArch64MIR_TargetOp<"ldfmaxl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMAXLD LDFMAXLH LDFMAXLS
+}
+
+def AArch64MIR_ldfmaxnma : AArch64MIR_TargetOp<"ldfmaxnma", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMAXNMAD LDFMAXNMAH LDFMAXNMAS
+}
+
+def AArch64MIR_ldfmaxnmal : AArch64MIR_TargetOp<"ldfmaxnmal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMAXNMALD LDFMAXNMALH LDFMAXNMALS
+}
+
+def AArch64MIR_ldfmaxnm : AArch64MIR_TargetOp<"ldfmaxnm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMAXNMD LDFMAXNMH LDFMAXNMS
+}
+
+def AArch64MIR_ldfmaxnml : AArch64MIR_TargetOp<"ldfmaxnml", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMAXNMLD LDFMAXNMLH LDFMAXNMLS
+}
+
+def AArch64MIR_ldfmina : AArch64MIR_TargetOp<"ldfmina", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMINAD LDFMINAH LDFMINAS
+}
+
+def AArch64MIR_ldfminal : AArch64MIR_TargetOp<"ldfminal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMINALD LDFMINALH LDFMINALS
+}
+
+def AArch64MIR_ldfmin : AArch64MIR_TargetOp<"ldfmin", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMIND LDFMINH LDFMINS
+}
+
+def AArch64MIR_ldfminl : AArch64MIR_TargetOp<"ldfminl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMINLD LDFMINLH LDFMINLS
+}
+
+def AArch64MIR_ldfminnma : AArch64MIR_TargetOp<"ldfminnma", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMINNMAD LDFMINNMAH LDFMINNMAS
+}
+
+def AArch64MIR_ldfminnmal : AArch64MIR_TargetOp<"ldfminnmal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMINNMALD LDFMINNMALH LDFMINNMALS
+}
+
+def AArch64MIR_ldfminnm : AArch64MIR_TargetOp<"ldfminnm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMINNMD LDFMINNMH LDFMINNMS
+}
+
+def AArch64MIR_ldfminnml : AArch64MIR_TargetOp<"ldfminnml", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDFMINNMLD LDFMINNMLH LDFMINNMLS
+}
+
+def AArch64MIR_ldg : AArch64MIR_TargetOp<"ldg", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDG
+}
+
+def AArch64MIR_ldgm : AArch64MIR_TargetOp<"ldgm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDGM
+}
+
+def AArch64MIR_ldiapp : AArch64MIR_TargetOp<"ldiapp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDIAPPW LDIAPPWpost LDIAPPX LDIAPPXpost
+}
+
+def AArch64MIR_ldlarb : AArch64MIR_TargetOp<"ldlarb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDLARB
+}
+
+def AArch64MIR_ldlarh : AArch64MIR_TargetOp<"ldlarh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDLARH
+}
+
+def AArch64MIR_ldlar : AArch64MIR_TargetOp<"ldlar", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDLARW LDLARX
+}
+
+def AArch64MIR_ldnf1b : AArch64MIR_TargetOp<"ldnf1b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNF1B_D_IMM LDNF1B_H_IMM LDNF1B_IMM LDNF1B_S_IMM
+}
+
+def AArch64MIR_ldnf1d : AArch64MIR_TargetOp<"ldnf1d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNF1D_IMM
+}
+
+def AArch64MIR_ldnf1h : AArch64MIR_TargetOp<"ldnf1h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNF1H_D_IMM LDNF1H_IMM LDNF1H_S_IMM
+}
+
+def AArch64MIR_ldnf1sb : AArch64MIR_TargetOp<"ldnf1sb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNF1SB_D_IMM LDNF1SB_H_IMM LDNF1SB_S_IMM
+}
+
+def AArch64MIR_ldnf1sh : AArch64MIR_TargetOp<"ldnf1sh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNF1SH_D_IMM LDNF1SH_S_IMM
+}
+
+def AArch64MIR_ldnf1sw : AArch64MIR_TargetOp<"ldnf1sw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNF1SW_D_IMM
+}
+
+def AArch64MIR_ldnf1w : AArch64MIR_TargetOp<"ldnf1w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNF1W_D_IMM LDNF1W_IMM
+}
+
+def AArch64MIR_ldnp : AArch64MIR_TargetOp<"ldnp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNPDi LDNPQi LDNPSi LDNPWi LDNPXi
+}
+
+def AArch64MIR_ldnt1b : AArch64MIR_TargetOp<"ldnt1b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNT1B_2Z LDNT1B_2Z_IMM LDNT1B_2Z_STRIDED LDNT1B_2Z_STRIDED_IMM LDNT1B_4Z LDNT1B_4Z_IMM LDNT1B_4Z_STRIDED LDNT1B_4Z_STRIDED_IMM LDNT1B_ZRI LDNT1B_ZRR LDNT1B_ZZR_D LDNT1B_ZZR_S
+}
+
+def AArch64MIR_ldnt1d : AArch64MIR_TargetOp<"ldnt1d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNT1D_2Z LDNT1D_2Z_IMM LDNT1D_2Z_STRIDED LDNT1D_2Z_STRIDED_IMM LDNT1D_4Z LDNT1D_4Z_IMM LDNT1D_4Z_STRIDED LDNT1D_4Z_STRIDED_IMM LDNT1D_ZRI LDNT1D_ZRR LDNT1D_ZZR_D
+}
+
+def AArch64MIR_ldnt1h : AArch64MIR_TargetOp<"ldnt1h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNT1H_2Z LDNT1H_2Z_IMM LDNT1H_2Z_STRIDED LDNT1H_2Z_STRIDED_IMM LDNT1H_4Z LDNT1H_4Z_IMM LDNT1H_4Z_STRIDED LDNT1H_4Z_STRIDED_IMM LDNT1H_ZRI LDNT1H_ZRR LDNT1H_ZZR_D LDNT1H_ZZR_S
+}
+
+def AArch64MIR_ldnt1sb : AArch64MIR_TargetOp<"ldnt1sb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNT1SB_ZZR_D LDNT1SB_ZZR_S
+}
+
+def AArch64MIR_ldnt1sh : AArch64MIR_TargetOp<"ldnt1sh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNT1SH_ZZR_D LDNT1SH_ZZR_S
+}
+
+def AArch64MIR_ldnt1sw : AArch64MIR_TargetOp<"ldnt1sw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNT1SW_ZZR_D
+}
+
+def AArch64MIR_ldnt1w : AArch64MIR_TargetOp<"ldnt1w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDNT1W_2Z LDNT1W_2Z_IMM LDNT1W_2Z_STRIDED LDNT1W_2Z_STRIDED_IMM LDNT1W_4Z LDNT1W_4Z_IMM LDNT1W_4Z_STRIDED LDNT1W_4Z_STRIDED_IMM LDNT1W_ZRI LDNT1W_ZRR LDNT1W_ZZR_D LDNT1W_ZZR_S
+}
+
+def AArch64MIR_ldp : AArch64MIR_TargetOp<"ldp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDPDi LDPDpost LDPDpre LDPQi LDPQpost LDPQpre LDPSi LDPSpost LDPSpre LDPWi LDPWpost LDPWpre LDPXi LDPXpost LDPXpre
+}
+
+def AArch64MIR_ldpsw : AArch64MIR_TargetOp<"ldpsw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDPSWi LDPSWpost LDPSWpre
+}
+
+def AArch64MIR_ldraa : AArch64MIR_TargetOp<"ldraa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDRAAindexed LDRAAwriteback
+}
+
+def AArch64MIR_ldrab : AArch64MIR_TargetOp<"ldrab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDRABindexed LDRABwriteback
+}
+
+def AArch64MIR_ldrb : AArch64MIR_TargetOp<"ldrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDRBBpost LDRBBpre LDRBBroW LDRBBroX LDRBBui
+}
+
+def AArch64MIR_ldr : AArch64MIR_TargetOp<"ldr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDRBpost LDRBpre LDRBroW LDRBroX LDRBui LDRDl LDRDpost LDRDpre LDRDroW LDRDroX LDRDui LDRHpost LDRHpre LDRHroW LDRHroX LDRHui LDRQl LDRQpost LDRQpre LDRQroW LDRQroX LDRQui LDRSl LDRSpost LDRSpre LDRSroW LDRSroX LDRSui LDRWl LDRWpost LDRWpre LDRWroW LDRWroX LDRWui LDRXl LDRXpost LDRXpre LDRXroW LDRXroX LDRXui LDR_PXI LDR_TX LDR_ZA LDR_ZXI
+}
+
+def AArch64MIR_ldrh : AArch64MIR_TargetOp<"ldrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDRHHpost LDRHHpre LDRHHroW LDRHHroX LDRHHui
+}
+
+def AArch64MIR_ldrsb : AArch64MIR_TargetOp<"ldrsb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDRSBWpost LDRSBWpre LDRSBWroW LDRSBWroX LDRSBWui LDRSBXpost LDRSBXpre LDRSBXroW LDRSBXroX LDRSBXui
+}
+
+def AArch64MIR_ldrsh : AArch64MIR_TargetOp<"ldrsh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDRSHWpost LDRSHWpre LDRSHWroW LDRSHWroX LDRSHWui LDRSHXpost LDRSHXpre LDRSHXroW LDRSHXroX LDRSHXui
+}
+
+def AArch64MIR_ldrsw : AArch64MIR_TargetOp<"ldrsw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDRSWl LDRSWpost LDRSWpre LDRSWroW LDRSWroX LDRSWui
+}
+
+def AArch64MIR_ldsetab : AArch64MIR_TargetOp<"ldsetab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETAB
+}
+
+def AArch64MIR_ldsetah : AArch64MIR_TargetOp<"ldsetah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETAH
+}
+
+def AArch64MIR_ldsetalb : AArch64MIR_TargetOp<"ldsetalb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETALB
+}
+
+def AArch64MIR_ldsetalh : AArch64MIR_TargetOp<"ldsetalh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETALH
+}
+
+def AArch64MIR_ldsetal : AArch64MIR_TargetOp<"ldsetal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETALW LDSETALX
+}
+
+def AArch64MIR_ldseta : AArch64MIR_TargetOp<"ldseta", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETAW LDSETAX
+}
+
+def AArch64MIR_ldsetb : AArch64MIR_TargetOp<"ldsetb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETB
+}
+
+def AArch64MIR_ldseth : AArch64MIR_TargetOp<"ldseth", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETH
+}
+
+def AArch64MIR_ldsetlb : AArch64MIR_TargetOp<"ldsetlb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETLB
+}
+
+def AArch64MIR_ldsetlh : AArch64MIR_TargetOp<"ldsetlh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETLH
+}
+
+def AArch64MIR_ldsetl : AArch64MIR_TargetOp<"ldsetl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETLW LDSETLX
+}
+
+def AArch64MIR_ldsetp : AArch64MIR_TargetOp<"ldsetp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETP
+}
+
+def AArch64MIR_ldsetpa : AArch64MIR_TargetOp<"ldsetpa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETPA
+}
+
+def AArch64MIR_ldsetpal : AArch64MIR_TargetOp<"ldsetpal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETPAL
+}
+
+def AArch64MIR_ldsetpl : AArch64MIR_TargetOp<"ldsetpl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETPL
+}
+
+def AArch64MIR_ldset : AArch64MIR_TargetOp<"ldset", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSETW LDSETX
+}
+
+def AArch64MIR_ldsmaxab : AArch64MIR_TargetOp<"ldsmaxab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXAB
+}
+
+def AArch64MIR_ldsmaxah : AArch64MIR_TargetOp<"ldsmaxah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXAH
+}
+
+def AArch64MIR_ldsmaxalb : AArch64MIR_TargetOp<"ldsmaxalb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXALB
+}
+
+def AArch64MIR_ldsmaxalh : AArch64MIR_TargetOp<"ldsmaxalh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXALH
+}
+
+def AArch64MIR_ldsmaxal : AArch64MIR_TargetOp<"ldsmaxal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXALW LDSMAXALX
+}
+
+def AArch64MIR_ldsmaxa : AArch64MIR_TargetOp<"ldsmaxa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXAW LDSMAXAX
+}
+
+def AArch64MIR_ldsmaxb : AArch64MIR_TargetOp<"ldsmaxb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXB
+}
+
+def AArch64MIR_ldsmaxh : AArch64MIR_TargetOp<"ldsmaxh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXH
+}
+
+def AArch64MIR_ldsmaxlb : AArch64MIR_TargetOp<"ldsmaxlb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXLB
+}
+
+def AArch64MIR_ldsmaxlh : AArch64MIR_TargetOp<"ldsmaxlh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXLH
+}
+
+def AArch64MIR_ldsmaxl : AArch64MIR_TargetOp<"ldsmaxl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXLW LDSMAXLX
+}
+
+def AArch64MIR_ldsmax : AArch64MIR_TargetOp<"ldsmax", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMAXW LDSMAXX
+}
+
+def AArch64MIR_ldsminab : AArch64MIR_TargetOp<"ldsminab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINAB
+}
+
+def AArch64MIR_ldsminah : AArch64MIR_TargetOp<"ldsminah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINAH
+}
+
+def AArch64MIR_ldsminalb : AArch64MIR_TargetOp<"ldsminalb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINALB
+}
+
+def AArch64MIR_ldsminalh : AArch64MIR_TargetOp<"ldsminalh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINALH
+}
+
+def AArch64MIR_ldsminal : AArch64MIR_TargetOp<"ldsminal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINALW LDSMINALX
+}
+
+def AArch64MIR_ldsmina : AArch64MIR_TargetOp<"ldsmina", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINAW LDSMINAX
+}
+
+def AArch64MIR_ldsminb : AArch64MIR_TargetOp<"ldsminb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINB
+}
+
+def AArch64MIR_ldsminh : AArch64MIR_TargetOp<"ldsminh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINH
+}
+
+def AArch64MIR_ldsminlb : AArch64MIR_TargetOp<"ldsminlb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINLB
+}
+
+def AArch64MIR_ldsminlh : AArch64MIR_TargetOp<"ldsminlh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINLH
+}
+
+def AArch64MIR_ldsminl : AArch64MIR_TargetOp<"ldsminl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINLW LDSMINLX
+}
+
+def AArch64MIR_ldsmin : AArch64MIR_TargetOp<"ldsmin", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDSMINW LDSMINX
+}
+
+def AArch64MIR_ldtaddal : AArch64MIR_TargetOp<"ldtaddal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTADDALW LDTADDALX
+}
+
+def AArch64MIR_ldtadda : AArch64MIR_TargetOp<"ldtadda", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTADDAW LDTADDAX
+}
+
+def AArch64MIR_ldtaddl : AArch64MIR_TargetOp<"ldtaddl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTADDLW LDTADDLX
+}
+
+def AArch64MIR_ldtadd : AArch64MIR_TargetOp<"ldtadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTADDW LDTADDX
+}
+
+def AArch64MIR_ldtclral : AArch64MIR_TargetOp<"ldtclral", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTCLRALW LDTCLRALX
+}
+
+def AArch64MIR_ldtclra : AArch64MIR_TargetOp<"ldtclra", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTCLRAW LDTCLRAX
+}
+
+def AArch64MIR_ldtclrl : AArch64MIR_TargetOp<"ldtclrl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTCLRLW LDTCLRLX
+}
+
+def AArch64MIR_ldtclr : AArch64MIR_TargetOp<"ldtclr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTCLRW LDTCLRX
+}
+
+def AArch64MIR_ldtnp : AArch64MIR_TargetOp<"ldtnp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTNPQi LDTNPXi
+}
+
+def AArch64MIR_ldtp : AArch64MIR_TargetOp<"ldtp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTPQi LDTPQpost LDTPQpre LDTPi LDTPpost LDTPpre
+}
+
+def AArch64MIR_ldtrb : AArch64MIR_TargetOp<"ldtrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTRBi
+}
+
+def AArch64MIR_ldtrh : AArch64MIR_TargetOp<"ldtrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTRHi
+}
+
+def AArch64MIR_ldtrsb : AArch64MIR_TargetOp<"ldtrsb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTRSBWi LDTRSBXi
+}
+
+def AArch64MIR_ldtrsh : AArch64MIR_TargetOp<"ldtrsh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTRSHWi LDTRSHXi
+}
+
+def AArch64MIR_ldtrsw : AArch64MIR_TargetOp<"ldtrsw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTRSWi
+}
+
+def AArch64MIR_ldtr : AArch64MIR_TargetOp<"ldtr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTRWi LDTRXi
+}
+
+def AArch64MIR_ldtsetal : AArch64MIR_TargetOp<"ldtsetal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTSETALW LDTSETALX
+}
+
+def AArch64MIR_ldtseta : AArch64MIR_TargetOp<"ldtseta", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTSETAW LDTSETAX
+}
+
+def AArch64MIR_ldtsetl : AArch64MIR_TargetOp<"ldtsetl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTSETLW LDTSETLX
+}
+
+def AArch64MIR_ldtset : AArch64MIR_TargetOp<"ldtset", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTSETW LDTSETX
+}
+
+def AArch64MIR_ldtxr : AArch64MIR_TargetOp<"ldtxr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDTXRWr LDTXRXr
+}
+
+def AArch64MIR_ldumaxab : AArch64MIR_TargetOp<"ldumaxab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXAB
+}
+
+def AArch64MIR_ldumaxah : AArch64MIR_TargetOp<"ldumaxah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXAH
+}
+
+def AArch64MIR_ldumaxalb : AArch64MIR_TargetOp<"ldumaxalb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXALB
+}
+
+def AArch64MIR_ldumaxalh : AArch64MIR_TargetOp<"ldumaxalh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXALH
+}
+
+def AArch64MIR_ldumaxal : AArch64MIR_TargetOp<"ldumaxal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXALW LDUMAXALX
+}
+
+def AArch64MIR_ldumaxa : AArch64MIR_TargetOp<"ldumaxa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXAW LDUMAXAX
+}
+
+def AArch64MIR_ldumaxb : AArch64MIR_TargetOp<"ldumaxb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXB
+}
+
+def AArch64MIR_ldumaxh : AArch64MIR_TargetOp<"ldumaxh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXH
+}
+
+def AArch64MIR_ldumaxlb : AArch64MIR_TargetOp<"ldumaxlb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXLB
+}
+
+def AArch64MIR_ldumaxlh : AArch64MIR_TargetOp<"ldumaxlh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXLH
+}
+
+def AArch64MIR_ldumaxl : AArch64MIR_TargetOp<"ldumaxl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXLW LDUMAXLX
+}
+
+def AArch64MIR_ldumax : AArch64MIR_TargetOp<"ldumax", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMAXW LDUMAXX
+}
+
+def AArch64MIR_lduminab : AArch64MIR_TargetOp<"lduminab", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINAB
+}
+
+def AArch64MIR_lduminah : AArch64MIR_TargetOp<"lduminah", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINAH
+}
+
+def AArch64MIR_lduminalb : AArch64MIR_TargetOp<"lduminalb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINALB
+}
+
+def AArch64MIR_lduminalh : AArch64MIR_TargetOp<"lduminalh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINALH
+}
+
+def AArch64MIR_lduminal : AArch64MIR_TargetOp<"lduminal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINALW LDUMINALX
+}
+
+def AArch64MIR_ldumina : AArch64MIR_TargetOp<"ldumina", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINAW LDUMINAX
+}
+
+def AArch64MIR_lduminb : AArch64MIR_TargetOp<"lduminb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINB
+}
+
+def AArch64MIR_lduminh : AArch64MIR_TargetOp<"lduminh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINH
+}
+
+def AArch64MIR_lduminlb : AArch64MIR_TargetOp<"lduminlb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINLB
+}
+
+def AArch64MIR_lduminlh : AArch64MIR_TargetOp<"lduminlh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINLH
+}
+
+def AArch64MIR_lduminl : AArch64MIR_TargetOp<"lduminl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINLW LDUMINLX
+}
+
+def AArch64MIR_ldumin : AArch64MIR_TargetOp<"ldumin", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDUMINW LDUMINX
+}
+
+def AArch64MIR_ldurb : AArch64MIR_TargetOp<"ldurb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDURBBi
+}
+
+def AArch64MIR_ldur : AArch64MIR_TargetOp<"ldur", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDURBi LDURDi LDURHi LDURQi LDURSi LDURWi LDURXi
+}
+
+def AArch64MIR_ldurh : AArch64MIR_TargetOp<"ldurh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDURHHi
+}
+
+def AArch64MIR_ldursb : AArch64MIR_TargetOp<"ldursb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDURSBWi LDURSBXi
+}
+
+def AArch64MIR_ldursh : AArch64MIR_TargetOp<"ldursh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDURSHWi LDURSHXi
+}
+
+def AArch64MIR_ldursw : AArch64MIR_TargetOp<"ldursw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDURSWi
+}
+
+def AArch64MIR_ldxp : AArch64MIR_TargetOp<"ldxp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDXPW LDXPX
+}
+
+def AArch64MIR_ldxrb : AArch64MIR_TargetOp<"ldxrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDXRB
+}
+
+def AArch64MIR_ldxrh : AArch64MIR_TargetOp<"ldxrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDXRH
+}
+
+def AArch64MIR_ldxr : AArch64MIR_TargetOp<"ldxr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LDXRW LDXRX
+}
+
+def AArch64MIR_lslr : AArch64MIR_TargetOp<"lslr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LSLR_ZPmZ_B LSLR_ZPmZ_D LSLR_ZPmZ_H LSLR_ZPmZ_S
+}
+
+def AArch64MIR_lsl : AArch64MIR_TargetOp<"lsl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LSLVWr LSLVXr LSL_WIDE_ZPmZ_B LSL_WIDE_ZPmZ_H LSL_WIDE_ZPmZ_S LSL_WIDE_ZZZ_B LSL_WIDE_ZZZ_H LSL_WIDE_ZZZ_S LSL_ZPmI_B LSL_ZPmI_D LSL_ZPmI_H LSL_ZPmI_S LSL_ZPmZ_B LSL_ZPmZ_D LSL_ZPmZ_H LSL_ZPmZ_S LSL_ZZI_B LSL_ZZI_D LSL_ZZI_H LSL_ZZI_S
+}
+
+def AArch64MIR_lsrr : AArch64MIR_TargetOp<"lsrr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LSRR_ZPmZ_B LSRR_ZPmZ_D LSRR_ZPmZ_H LSRR_ZPmZ_S
+}
+
+def AArch64MIR_lsr : AArch64MIR_TargetOp<"lsr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LSRVWr LSRVXr LSR_WIDE_ZPmZ_B LSR_WIDE_ZPmZ_H LSR_WIDE_ZPmZ_S LSR_WIDE_ZZZ_B LSR_WIDE_ZZZ_H LSR_WIDE_ZZZ_S LSR_ZPmI_B LSR_ZPmI_D LSR_ZPmI_H LSR_ZPmI_S LSR_ZPmZ_B LSR_ZPmZ_D LSR_ZPmZ_H LSR_ZPmZ_S LSR_ZZI_B LSR_ZZI_D LSR_ZZI_H LSR_ZZI_S
+}
+
+def AArch64MIR_luti2 : AArch64MIR_TargetOp<"luti2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LUT2_B LUT2_H LUTI2_2ZTZI_B LUTI2_2ZTZI_H LUTI2_2ZTZI_S LUTI2_4ZTZI_B LUTI2_4ZTZI_H LUTI2_4ZTZI_S LUTI2_S_2ZTZI_B LUTI2_S_2ZTZI_H LUTI2_S_4ZTZI_B LUTI2_S_4ZTZI_H LUTI2_ZTZI_B LUTI2_ZTZI_H LUTI2_ZTZI_S LUTI2_ZZZI_B LUTI2_ZZZI_H
+}
+
+def AArch64MIR_luti4 : AArch64MIR_TargetOp<"luti4", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LUT4_B LUT4_H LUTI4_2ZTZI_B LUTI4_2ZTZI_H LUTI4_2ZTZI_S LUTI4_4ZTZI_H LUTI4_4ZTZI_S LUTI4_4ZZT2Z LUTI4_S_2ZTZI_B LUTI4_S_2ZTZI_H LUTI4_S_4ZTZI_H LUTI4_S_4ZZT2Z LUTI4_Z2ZZI LUTI4_ZTZI_B LUTI4_ZTZI_H LUTI4_ZTZI_S LUTI4_ZZZI_B LUTI4_ZZZI_H
+}
+
+def AArch64MIR_luti6 : AArch64MIR_TargetOp<"luti6", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: LUTI6_4Z2Z2ZI LUTI6_4ZT3Z LUTI6_S_4Z2Z2ZI LUTI6_S_4ZT3Z LUTI6_Z2ZZ LUTI6_Z2ZZI_H LUTI6_ZTZ
+}
+
+def AArch64MIR_maddpt : AArch64MIR_TargetOp<"maddpt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MADDPT
+}
+
+def AArch64MIR_madd : AArch64MIR_TargetOp<"madd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MADDWrrr MADDXrrr
+}
+
+def AArch64MIR_madpt : AArch64MIR_TargetOp<"madpt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MAD_CPA
+}
+
+def AArch64MIR_mad : AArch64MIR_TargetOp<"mad", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MAD_ZPmZZ_B MAD_ZPmZZ_D MAD_ZPmZZ_H MAD_ZPmZZ_S
+}
+
+def AArch64MIR_match : AArch64MIR_TargetOp<"match", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MATCH_PPzZZ_B MATCH_PPzZZ_H
+}
+
+def AArch64MIR_mlapt : AArch64MIR_TargetOp<"mlapt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MLA_CPA
+}
+
+def AArch64MIR_mla : AArch64MIR_TargetOp<"mla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MLA_ZPmZZ_B MLA_ZPmZZ_D MLA_ZPmZZ_H MLA_ZPmZZ_S MLA_ZZZI_D MLA_ZZZI_H MLA_ZZZI_S MLAv2i32 MLAv2i32_indexed MLAv4i16 MLAv4i16_indexed MLAv4i32 MLAv4i32_indexed MLAv8i8 MLAv8i16 MLAv8i16_indexed MLAv16i8
+}
+
+def AArch64MIR_mls : AArch64MIR_TargetOp<"mls", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MLS_ZPmZZ_B MLS_ZPmZZ_D MLS_ZPmZZ_H MLS_ZPmZZ_S MLS_ZZZI_D MLS_ZZZI_H MLS_ZZZI_S MLSv2i32 MLSv2i32_indexed MLSv4i16 MLSv4i16_indexed MLSv4i32 MLSv4i32_indexed MLSv8i8 MLSv8i16 MLSv8i16_indexed MLSv16i8
+}
+
+def AArch64MIR_setge : AArch64MIR_TargetOp<"setge", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOPSSETGE
+}
+
+def AArch64MIR_setgen : AArch64MIR_TargetOp<"setgen", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOPSSETGEN
+}
+
+def AArch64MIR_setget : AArch64MIR_TargetOp<"setget", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOPSSETGET
+}
+
+def AArch64MIR_setgetn : AArch64MIR_TargetOp<"setgetn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOPSSETGETN
+}
+
+def AArch64MIR_movaz : AArch64MIR_TargetOp<"movaz", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOVAZ_2ZMI_H_B MOVAZ_2ZMI_H_D MOVAZ_2ZMI_H_H MOVAZ_2ZMI_H_S MOVAZ_2ZMI_V_B MOVAZ_2ZMI_V_D MOVAZ_2ZMI_V_H MOVAZ_2ZMI_V_S MOVAZ_4ZMI_H_B MOVAZ_4ZMI_H_D MOVAZ_4ZMI_H_H MOVAZ_4ZMI_H_S MOVAZ_4ZMI_V_B MOVAZ_4ZMI_V_D MOVAZ_4ZMI_V_H MOVAZ_4ZMI_V_S MOVAZ_VG2_2ZMXI MOVAZ_VG4_4ZMXI MOVAZ_ZMI_H_B MOVAZ_ZMI_H_D MOVAZ_ZMI_H_H MOVAZ_ZMI_H_Q MOVAZ_ZMI_H_S MOVAZ_ZMI_V_B MOVAZ_ZMI_V_D MOVAZ_ZMI_V_H MOVAZ_ZMI_V_Q MOVAZ_ZMI_V_S
+}
+
+def AArch64MIR_movi : AArch64MIR_TargetOp<"movi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOVID MOVIv2d_ns MOVIv2i32 MOVIv2s_msl MOVIv4i16 MOVIv4i32 MOVIv4s_msl MOVIv8b_ns MOVIv8i16 MOVIv16b_ns
+}
+
+def AArch64MIR_movk : AArch64MIR_TargetOp<"movk", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOVKWi MOVKXi
+}
+
+def AArch64MIR_movn : AArch64MIR_TargetOp<"movn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOVNWi MOVNXi
+}
+
+def AArch64MIR_movprfx : AArch64MIR_TargetOp<"movprfx", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOVPRFX_ZPmZ_B MOVPRFX_ZPmZ_D MOVPRFX_ZPmZ_H MOVPRFX_ZPmZ_S MOVPRFX_ZPzZ_B MOVPRFX_ZPzZ_D MOVPRFX_ZPzZ_H MOVPRFX_ZPzZ_S MOVPRFX_ZZ
+}
+
+def AArch64MIR_movt : AArch64MIR_TargetOp<"movt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOVT_TIX MOVT_TIZ MOVT_XTI
+}
+
+def AArch64MIR_movz : AArch64MIR_TargetOp<"movz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MOVZWi MOVZXi
+}
+
+def AArch64MIR_mrrs : AArch64MIR_TargetOp<"mrrs", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MRRS
+}
+
+def AArch64MIR_mrs : AArch64MIR_TargetOp<"mrs", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MRS
+}
+
+def AArch64MIR_msb : AArch64MIR_TargetOp<"msb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MSB_ZPmZZ_B MSB_ZPmZZ_D MSB_ZPmZZ_H MSB_ZPmZZ_S
+}
+
+def AArch64MIR_msr : AArch64MIR_TargetOp<"msr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MSR MSRpstateImm1 MSRpstateImm4 MSRpstatesvcrImm1
+}
+
+def AArch64MIR_msrr : AArch64MIR_TargetOp<"msrr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MSRR
+}
+
+def AArch64MIR_msubpt : AArch64MIR_TargetOp<"msubpt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MSUBPT
+}
+
+def AArch64MIR_msub : AArch64MIR_TargetOp<"msub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MSUBWrrr MSUBXrrr
+}
+
+def AArch64MIR_mul : AArch64MIR_TargetOp<"mul", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MUL_ZI_B MUL_ZI_D MUL_ZI_H MUL_ZI_S MUL_ZPmZ_B MUL_ZPmZ_D MUL_ZPmZ_H MUL_ZPmZ_S MUL_ZZZI_D MUL_ZZZI_H MUL_ZZZI_S MUL_ZZZ_B MUL_ZZZ_D MUL_ZZZ_H MUL_ZZZ_S MULv2i32 MULv2i32_indexed MULv4i16 MULv4i16_indexed MULv4i32 MULv4i32_indexed MULv8i8 MULv8i16 MULv8i16_indexed MULv16i8
+}
+
+def AArch64MIR_mvni : AArch64MIR_TargetOp<"mvni", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: MVNIv2i32 MVNIv2s_msl MVNIv4i16 MVNIv4i32 MVNIv4s_msl MVNIv8i16
+}
+
+def AArch64MIR_nands : AArch64MIR_TargetOp<"nands", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: NANDS_PPzPP
+}
+
+def AArch64MIR_nand : AArch64MIR_TargetOp<"nand", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: NAND_PPzPP
+}
+
+def AArch64MIR_nbsl : AArch64MIR_TargetOp<"nbsl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: NBSL_ZZZZ
+}
+
+def AArch64MIR_neg : AArch64MIR_TargetOp<"neg", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: NEG_ZPmZ_B NEG_ZPmZ_D NEG_ZPmZ_H NEG_ZPmZ_S NEG_ZPzZ_B NEG_ZPzZ_D NEG_ZPzZ_H NEG_ZPzZ_S NEGv1i64 NEGv2i32 NEGv2i64 NEGv4i16 NEGv4i32 NEGv8i8 NEGv8i16 NEGv16i8
+}
+
+def AArch64MIR_nmatch : AArch64MIR_TargetOp<"nmatch", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: NMATCH_PPzZZ_B NMATCH_PPzZZ_H
+}
+
+def AArch64MIR_nors : AArch64MIR_TargetOp<"nors", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: NORS_PPzPP
+}
+
+def AArch64MIR_nor : AArch64MIR_TargetOp<"nor", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: NOR_PPzPP
+}
+
+def AArch64MIR_not_ : AArch64MIR_TargetOp<"not", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: NOT_ZPmZ_B NOT_ZPmZ_D NOT_ZPmZ_H NOT_ZPmZ_S NOT_ZPzZ_B NOT_ZPzZ_D NOT_ZPzZ_H NOT_ZPzZ_S NOTv8i8 NOTv16i8
+}
+
+def AArch64MIR_orns : AArch64MIR_TargetOp<"orns", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ORNS_PPzPP
+}
+
+def AArch64MIR_orn : AArch64MIR_TargetOp<"orn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ORNWrs ORNXrs ORN_PPzPP ORNv8i8 ORNv16i8
+}
+
+def AArch64MIR_orqv : AArch64MIR_TargetOp<"orqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ORQV_VPZ_B ORQV_VPZ_D ORQV_VPZ_H ORQV_VPZ_S
+}
+
+def AArch64MIR_orrs : AArch64MIR_TargetOp<"orrs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ORRS_PPzPP
+}
+
+def AArch64MIR_orr : AArch64MIR_TargetOp<"orr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ORRWri ORRWrs ORRXri ORRXrs ORR_PPzPP ORR_ZI ORR_ZPmZ_B ORR_ZPmZ_D ORR_ZPmZ_H ORR_ZPmZ_S ORR_ZZZ ORRv2i32 ORRv4i16 ORRv4i32 ORRv8i8 ORRv8i16 ORRv16i8
+}
+
+def AArch64MIR_orv : AArch64MIR_TargetOp<"orv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ORV_VPZ_B ORV_VPZ_D ORV_VPZ_H ORV_VPZ_S
+}
+
+def AArch64MIR_pacda : AArch64MIR_TargetOp<"pacda", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACDA
+}
+
+def AArch64MIR_pacdb : AArch64MIR_TargetOp<"pacdb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACDB
+}
+
+def AArch64MIR_pacdza : AArch64MIR_TargetOp<"pacdza", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACDZA
+}
+
+def AArch64MIR_pacdzb : AArch64MIR_TargetOp<"pacdzb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACDZB
+}
+
+def AArch64MIR_pacga : AArch64MIR_TargetOp<"pacga", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACGA
+}
+
+def AArch64MIR_pacia : AArch64MIR_TargetOp<"pacia", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACIA
+}
+
+def AArch64MIR_pacia171615 : AArch64MIR_TargetOp<"pacia171615", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACIA171615
+}
+
+def AArch64MIR_paciasppc : AArch64MIR_TargetOp<"paciasppc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACIASPPC
+}
+
+def AArch64MIR_pacib : AArch64MIR_TargetOp<"pacib", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACIB
+}
+
+def AArch64MIR_pacib171615 : AArch64MIR_TargetOp<"pacib171615", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACIB171615
+}
+
+def AArch64MIR_pacibsppc : AArch64MIR_TargetOp<"pacibsppc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACIBSPPC
+}
+
+def AArch64MIR_paciza : AArch64MIR_TargetOp<"paciza", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACIZA
+}
+
+def AArch64MIR_pacizb : AArch64MIR_TargetOp<"pacizb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACIZB
+}
+
+def AArch64MIR_pacnbiasppc : AArch64MIR_TargetOp<"pacnbiasppc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACNBIASPPC
+}
+
+def AArch64MIR_pacnbibsppc : AArch64MIR_TargetOp<"pacnbibsppc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PACNBIBSPPC
+}
+
+def AArch64MIR_pext : AArch64MIR_TargetOp<"pext", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PEXT_2PCI_B PEXT_2PCI_D PEXT_2PCI_H PEXT_2PCI_S PEXT_PCI_B PEXT_PCI_D PEXT_PCI_H PEXT_PCI_S
+}
+
+def AArch64MIR_pfalse : AArch64MIR_TargetOp<"pfalse", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PFALSE
+}
+
+def AArch64MIR_pfirst : AArch64MIR_TargetOp<"pfirst", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PFIRST_B
+}
+
+def AArch64MIR_pmlal : AArch64MIR_TargetOp<"pmlal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PMLAL_2ZZZ_Q
+}
+
+def AArch64MIR_pmov : AArch64MIR_TargetOp<"pmov", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PMOV_PZI_B PMOV_PZI_D PMOV_PZI_H PMOV_PZI_S PMOV_ZIP_B PMOV_ZIP_D PMOV_ZIP_H PMOV_ZIP_S
+}
+
+def AArch64MIR_pmullb : AArch64MIR_TargetOp<"pmullb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PMULLB_ZZZ_D PMULLB_ZZZ_H PMULLB_ZZZ_Q
+}
+
+def AArch64MIR_pmullt : AArch64MIR_TargetOp<"pmullt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PMULLT_ZZZ_D PMULLT_ZZZ_H PMULLT_ZZZ_Q
+}
+
+def AArch64MIR_pmull : AArch64MIR_TargetOp<"pmull", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PMULL_2ZZZ_Q PMULLv1i64 PMULLv8i8
+}
+
+def AArch64MIR_pmull2 : AArch64MIR_TargetOp<"pmull2", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PMULLv2i64 PMULLv16i8
+}
+
+def AArch64MIR_pmul : AArch64MIR_TargetOp<"pmul", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PMUL_ZZZ_B PMULv8i8 PMULv16i8
+}
+
+def AArch64MIR_pnext : AArch64MIR_TargetOp<"pnext", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PNEXT_B PNEXT_D PNEXT_H PNEXT_S
+}
+
+def AArch64MIR_prfb : AArch64MIR_TargetOp<"prfb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PRFB_D_PZI PRFB_D_SCALED PRFB_D_SXTW_SCALED PRFB_D_UXTW_SCALED PRFB_PRI PRFB_PRR PRFB_S_PZI PRFB_S_SXTW_SCALED PRFB_S_UXTW_SCALED
+}
+
+def AArch64MIR_prfd : AArch64MIR_TargetOp<"prfd", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PRFD_D_PZI PRFD_D_SCALED PRFD_D_SXTW_SCALED PRFD_D_UXTW_SCALED PRFD_PRI PRFD_PRR PRFD_S_PZI PRFD_S_SXTW_SCALED PRFD_S_UXTW_SCALED
+}
+
+def AArch64MIR_prfh : AArch64MIR_TargetOp<"prfh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PRFH_D_PZI PRFH_D_SCALED PRFH_D_SXTW_SCALED PRFH_D_UXTW_SCALED PRFH_PRI PRFH_PRR PRFH_S_PZI PRFH_S_SXTW_SCALED PRFH_S_UXTW_SCALED
+}
+
+def AArch64MIR_prfm : AArch64MIR_TargetOp<"prfm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PRFMl PRFMroW PRFMroX PRFMui
+}
+
+def AArch64MIR_prfum : AArch64MIR_TargetOp<"prfum", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PRFUMi
+}
+
+def AArch64MIR_prfw : AArch64MIR_TargetOp<"prfw", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PRFW_D_PZI PRFW_D_SCALED PRFW_D_SXTW_SCALED PRFW_D_UXTW_SCALED PRFW_PRI PRFW_PRR PRFW_S_PZI PRFW_S_SXTW_SCALED PRFW_S_UXTW_SCALED
+}
+
+def AArch64MIR_psel : AArch64MIR_TargetOp<"psel", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PSEL_PPPRI_B PSEL_PPPRI_D PSEL_PPPRI_H PSEL_PPPRI_S
+}
+
+def AArch64MIR_ptest : AArch64MIR_TargetOp<"ptest", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PTEST_PP
+}
+
+def AArch64MIR_ptrues : AArch64MIR_TargetOp<"ptrues", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PTRUES_B PTRUES_D PTRUES_H PTRUES_S
+}
+
+def AArch64MIR_ptrue : AArch64MIR_TargetOp<"ptrue", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PTRUE_B PTRUE_C_B PTRUE_C_D PTRUE_C_H PTRUE_C_S PTRUE_D PTRUE_H PTRUE_S
+}
+
+def AArch64MIR_punpkhi : AArch64MIR_TargetOp<"punpkhi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PUNPKHI_PP
+}
+
+def AArch64MIR_punpklo : AArch64MIR_TargetOp<"punpklo", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: PUNPKLO_PP
+}
+
+def AArch64MIR_raddhnb : AArch64MIR_TargetOp<"raddhnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RADDHNB_ZZZ_B RADDHNB_ZZZ_H RADDHNB_ZZZ_S
+}
+
+def AArch64MIR_raddhnt : AArch64MIR_TargetOp<"raddhnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RADDHNT_ZZZ_B RADDHNT_ZZZ_H RADDHNT_ZZZ_S
+}
+
+def AArch64MIR_raddhn : AArch64MIR_TargetOp<"raddhn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RADDHNv2i64_v2i32 RADDHNv4i32_v4i16 RADDHNv8i16_v8i8
+}
+
+def AArch64MIR_raddhn2 : AArch64MIR_TargetOp<"raddhn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RADDHNv2i64_v4i32 RADDHNv4i32_v8i16 RADDHNv8i16_v16i8
+}
+
+def AArch64MIR_rax1 : AArch64MIR_TargetOp<"rax1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RAX1 RAX1_ZZZ_D
+}
+
+def AArch64MIR_rbit : AArch64MIR_TargetOp<"rbit", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RBITWr RBITXr RBIT_ZPmZ_B RBIT_ZPmZ_D RBIT_ZPmZ_H RBIT_ZPmZ_S RBIT_ZPzZ_B RBIT_ZPzZ_D RBIT_ZPzZ_H RBIT_ZPzZ_S RBITv8i8 RBITv16i8
+}
+
+def AArch64MIR_rcwcas : AArch64MIR_TargetOp<"rcwcas", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCAS
+}
+
+def AArch64MIR_rcwcasa : AArch64MIR_TargetOp<"rcwcasa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCASA
+}
+
+def AArch64MIR_rcwcasal : AArch64MIR_TargetOp<"rcwcasal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCASAL
+}
+
+def AArch64MIR_rcwcasl : AArch64MIR_TargetOp<"rcwcasl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCASL
+}
+
+def AArch64MIR_rcwcasp : AArch64MIR_TargetOp<"rcwcasp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCASP
+}
+
+def AArch64MIR_rcwcaspa : AArch64MIR_TargetOp<"rcwcaspa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCASPA
+}
+
+def AArch64MIR_rcwcaspal : AArch64MIR_TargetOp<"rcwcaspal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCASPAL
+}
+
+def AArch64MIR_rcwcaspl : AArch64MIR_TargetOp<"rcwcaspl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCASPL
+}
+
+def AArch64MIR_rcwclr : AArch64MIR_TargetOp<"rcwclr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLR
+}
+
+def AArch64MIR_rcwclra : AArch64MIR_TargetOp<"rcwclra", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRA
+}
+
+def AArch64MIR_rcwclral : AArch64MIR_TargetOp<"rcwclral", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRAL
+}
+
+def AArch64MIR_rcwclrl : AArch64MIR_TargetOp<"rcwclrl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRL
+}
+
+def AArch64MIR_rcwclrp : AArch64MIR_TargetOp<"rcwclrp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRP
+}
+
+def AArch64MIR_rcwclrpa : AArch64MIR_TargetOp<"rcwclrpa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRPA
+}
+
+def AArch64MIR_rcwclrpal : AArch64MIR_TargetOp<"rcwclrpal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRPAL
+}
+
+def AArch64MIR_rcwclrpl : AArch64MIR_TargetOp<"rcwclrpl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRPL
+}
+
+def AArch64MIR_rcwsclr : AArch64MIR_TargetOp<"rcwsclr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRS
+}
+
+def AArch64MIR_rcwsclra : AArch64MIR_TargetOp<"rcwsclra", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRSA
+}
+
+def AArch64MIR_rcwsclral : AArch64MIR_TargetOp<"rcwsclral", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRSAL
+}
+
+def AArch64MIR_rcwsclrl : AArch64MIR_TargetOp<"rcwsclrl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRSL
+}
+
+def AArch64MIR_rcwsclrp : AArch64MIR_TargetOp<"rcwsclrp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRSP
+}
+
+def AArch64MIR_rcwsclrpa : AArch64MIR_TargetOp<"rcwsclrpa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRSPA
+}
+
+def AArch64MIR_rcwsclrpal : AArch64MIR_TargetOp<"rcwsclrpal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRSPAL
+}
+
+def AArch64MIR_rcwsclrpl : AArch64MIR_TargetOp<"rcwsclrpl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWCLRSPL
+}
+
+def AArch64MIR_rcwscas : AArch64MIR_TargetOp<"rcwscas", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSCAS
+}
+
+def AArch64MIR_rcwscasa : AArch64MIR_TargetOp<"rcwscasa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSCASA
+}
+
+def AArch64MIR_rcwscasal : AArch64MIR_TargetOp<"rcwscasal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSCASAL
+}
+
+def AArch64MIR_rcwscasl : AArch64MIR_TargetOp<"rcwscasl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSCASL
+}
+
+def AArch64MIR_rcwscasp : AArch64MIR_TargetOp<"rcwscasp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSCASP
+}
+
+def AArch64MIR_rcwscaspa : AArch64MIR_TargetOp<"rcwscaspa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSCASPA
+}
+
+def AArch64MIR_rcwscaspal : AArch64MIR_TargetOp<"rcwscaspal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSCASPAL
+}
+
+def AArch64MIR_rcwscaspl : AArch64MIR_TargetOp<"rcwscaspl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSCASPL
+}
+
+def AArch64MIR_rcwset : AArch64MIR_TargetOp<"rcwset", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSET
+}
+
+def AArch64MIR_rcwseta : AArch64MIR_TargetOp<"rcwseta", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETA
+}
+
+def AArch64MIR_rcwsetal : AArch64MIR_TargetOp<"rcwsetal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETAL
+}
+
+def AArch64MIR_rcwsetl : AArch64MIR_TargetOp<"rcwsetl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETL
+}
+
+def AArch64MIR_rcwsetp : AArch64MIR_TargetOp<"rcwsetp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETP
+}
+
+def AArch64MIR_rcwsetpa : AArch64MIR_TargetOp<"rcwsetpa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETPA
+}
+
+def AArch64MIR_rcwsetpal : AArch64MIR_TargetOp<"rcwsetpal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETPAL
+}
+
+def AArch64MIR_rcwsetpl : AArch64MIR_TargetOp<"rcwsetpl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETPL
+}
+
+def AArch64MIR_rcwsset : AArch64MIR_TargetOp<"rcwsset", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETS
+}
+
+def AArch64MIR_rcwsseta : AArch64MIR_TargetOp<"rcwsseta", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETSA
+}
+
+def AArch64MIR_rcwssetal : AArch64MIR_TargetOp<"rcwssetal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETSAL
+}
+
+def AArch64MIR_rcwssetl : AArch64MIR_TargetOp<"rcwssetl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETSL
+}
+
+def AArch64MIR_rcwssetp : AArch64MIR_TargetOp<"rcwssetp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETSP
+}
+
+def AArch64MIR_rcwssetpa : AArch64MIR_TargetOp<"rcwssetpa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETSPA
+}
+
+def AArch64MIR_rcwssetpal : AArch64MIR_TargetOp<"rcwssetpal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETSPAL
+}
+
+def AArch64MIR_rcwssetpl : AArch64MIR_TargetOp<"rcwssetpl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSETSPL
+}
+
+def AArch64MIR_rcwswp : AArch64MIR_TargetOp<"rcwswp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWP
+}
+
+def AArch64MIR_rcwswpa : AArch64MIR_TargetOp<"rcwswpa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPA
+}
+
+def AArch64MIR_rcwswpal : AArch64MIR_TargetOp<"rcwswpal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPAL
+}
+
+def AArch64MIR_rcwswpl : AArch64MIR_TargetOp<"rcwswpl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPL
+}
+
+def AArch64MIR_rcwswpp : AArch64MIR_TargetOp<"rcwswpp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPP
+}
+
+def AArch64MIR_rcwswppa : AArch64MIR_TargetOp<"rcwswppa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPPA
+}
+
+def AArch64MIR_rcwswppal : AArch64MIR_TargetOp<"rcwswppal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPPAL
+}
+
+def AArch64MIR_rcwswppl : AArch64MIR_TargetOp<"rcwswppl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPPL
+}
+
+def AArch64MIR_rcwsswp : AArch64MIR_TargetOp<"rcwsswp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPS
+}
+
+def AArch64MIR_rcwsswpa : AArch64MIR_TargetOp<"rcwsswpa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPSA
+}
+
+def AArch64MIR_rcwsswpal : AArch64MIR_TargetOp<"rcwsswpal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPSAL
+}
+
+def AArch64MIR_rcwsswpl : AArch64MIR_TargetOp<"rcwsswpl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPSL
+}
+
+def AArch64MIR_rcwsswpp : AArch64MIR_TargetOp<"rcwsswpp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPSP
+}
+
+def AArch64MIR_rcwsswppa : AArch64MIR_TargetOp<"rcwsswppa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPSPA
+}
+
+def AArch64MIR_rcwsswppal : AArch64MIR_TargetOp<"rcwsswppal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPSPAL
+}
+
+def AArch64MIR_rcwsswppl : AArch64MIR_TargetOp<"rcwsswppl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RCWSWPSPL
+}
+
+def AArch64MIR_rdffrs : AArch64MIR_TargetOp<"rdffrs", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RDFFRS_PPz
+}
+
+def AArch64MIR_rdffr : AArch64MIR_TargetOp<"rdffr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RDFFR_P RDFFR_PPz
+}
+
+def AArch64MIR_rdsvl : AArch64MIR_TargetOp<"rdsvl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RDSVLI_XI
+}
+
+def AArch64MIR_rdvl : AArch64MIR_TargetOp<"rdvl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RDVLI_XI
+}
+
+def AArch64MIR_ret : AArch64MIR_TargetOp<"ret", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RET
+}
+
+def AArch64MIR_retaa : AArch64MIR_TargetOp<"retaa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RETAA
+}
+
+def AArch64MIR_retaasppc : AArch64MIR_TargetOp<"retaasppc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RETAASPPCi
+}
+
+def AArch64MIR_retaasppcr : AArch64MIR_TargetOp<"retaasppcr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RETAASPPCr
+}
+
+def AArch64MIR_retab : AArch64MIR_TargetOp<"retab", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RETAB
+}
+
+def AArch64MIR_retabsppc : AArch64MIR_TargetOp<"retabsppc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RETABSPPCi
+}
+
+def AArch64MIR_retabsppcr : AArch64MIR_TargetOp<"retabsppcr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RETABSPPCr
+}
+
+def AArch64MIR_rev16 : AArch64MIR_TargetOp<"rev16", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: REV16Wr REV16Xr REV16v8i8 REV16v16i8
+}
+
+def AArch64MIR_rev32 : AArch64MIR_TargetOp<"rev32", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: REV32Xr REV32v4i16 REV32v8i8 REV32v8i16 REV32v16i8
+}
+
+def AArch64MIR_rev64 : AArch64MIR_TargetOp<"rev64", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: REV64v2i32 REV64v4i16 REV64v4i32 REV64v8i8 REV64v8i16 REV64v16i8
+}
+
+def AArch64MIR_revb : AArch64MIR_TargetOp<"revb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: REVB_ZPmZ_D REVB_ZPmZ_H REVB_ZPmZ_S REVB_ZPzZ_D REVB_ZPzZ_H REVB_ZPzZ_S
+}
+
+def AArch64MIR_revd : AArch64MIR_TargetOp<"revd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: REVD_ZPmZ REVD_ZPzZ
+}
+
+def AArch64MIR_revh : AArch64MIR_TargetOp<"revh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: REVH_ZPmZ_D REVH_ZPmZ_S REVH_ZPzZ_D REVH_ZPzZ_S
+}
+
+def AArch64MIR_revw : AArch64MIR_TargetOp<"revw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: REVW_ZPmZ_D REVW_ZPzZ_D
+}
+
+def AArch64MIR_rev : AArch64MIR_TargetOp<"rev", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: REVWr REVXr REV_PP_B REV_PP_D REV_PP_H REV_PP_S REV_ZZ_B REV_ZZ_D REV_ZZ_H REV_ZZ_S
+}
+
+def AArch64MIR_rmif : AArch64MIR_TargetOp<"rmif", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RMIF
+}
+
+def AArch64MIR_ror : AArch64MIR_TargetOp<"ror", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RORVWr RORVXr
+}
+
+def AArch64MIR_rprfm : AArch64MIR_TargetOp<"rprfm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RPRFM
+}
+
+def AArch64MIR_rshrnb : AArch64MIR_TargetOp<"rshrnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RSHRNB_ZZI_B RSHRNB_ZZI_H RSHRNB_ZZI_S
+}
+
+def AArch64MIR_rshrnt : AArch64MIR_TargetOp<"rshrnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RSHRNT_ZZI_B RSHRNT_ZZI_H RSHRNT_ZZI_S
+}
+
+def AArch64MIR_rshrn : AArch64MIR_TargetOp<"rshrn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RSHRNv2i32_shift RSHRNv4i16_shift RSHRNv8i8_shift
+}
+
+def AArch64MIR_rshrn2 : AArch64MIR_TargetOp<"rshrn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RSHRNv4i32_shift RSHRNv8i16_shift RSHRNv16i8_shift
+}
+
+def AArch64MIR_rsubhnb : AArch64MIR_TargetOp<"rsubhnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RSUBHNB_ZZZ_B RSUBHNB_ZZZ_H RSUBHNB_ZZZ_S
+}
+
+def AArch64MIR_rsubhnt : AArch64MIR_TargetOp<"rsubhnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RSUBHNT_ZZZ_B RSUBHNT_ZZZ_H RSUBHNT_ZZZ_S
+}
+
+def AArch64MIR_rsubhn : AArch64MIR_TargetOp<"rsubhn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RSUBHNv2i64_v2i32 RSUBHNv4i32_v4i16 RSUBHNv8i16_v8i8
+}
+
+def AArch64MIR_rsubhn2 : AArch64MIR_TargetOp<"rsubhn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: RSUBHNv2i64_v4i32 RSUBHNv4i32_v8i16 RSUBHNv8i16_v16i8
+}
+
+def AArch64MIR_sabalb : AArch64MIR_TargetOp<"sabalb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABALB_ZZZ_D SABALB_ZZZ_H SABALB_ZZZ_S
+}
+
+def AArch64MIR_sabalt : AArch64MIR_TargetOp<"sabalt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABALT_ZZZ_D SABALT_ZZZ_H SABALT_ZZZ_S
+}
+
+def AArch64MIR_sabal : AArch64MIR_TargetOp<"sabal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABAL_ZZZ_BtoH SABAL_ZZZ_HtoS SABAL_ZZZ_StoD SABALv2i32_v2i64 SABALv4i16_v4i32 SABALv8i8_v8i16
+}
+
+def AArch64MIR_sabal2 : AArch64MIR_TargetOp<"sabal2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABALv4i32_v2i64 SABALv8i16_v4i32 SABALv16i8_v8i16
+}
+
+def AArch64MIR_saba : AArch64MIR_TargetOp<"saba", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABA_ZZZ_B SABA_ZZZ_D SABA_ZZZ_H SABA_ZZZ_S SABAv2i32 SABAv4i16 SABAv4i32 SABAv8i8 SABAv8i16 SABAv16i8
+}
+
+def AArch64MIR_sabdlb : AArch64MIR_TargetOp<"sabdlb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABDLB_ZZZ_D SABDLB_ZZZ_H SABDLB_ZZZ_S
+}
+
+def AArch64MIR_sabdlt : AArch64MIR_TargetOp<"sabdlt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABDLT_ZZZ_D SABDLT_ZZZ_H SABDLT_ZZZ_S
+}
+
+def AArch64MIR_sabdl : AArch64MIR_TargetOp<"sabdl", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABDLv2i32_v2i64 SABDLv4i16_v4i32 SABDLv8i8_v8i16
+}
+
+def AArch64MIR_sabdl2 : AArch64MIR_TargetOp<"sabdl2", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABDLv4i32_v2i64 SABDLv8i16_v4i32 SABDLv16i8_v8i16
+}
+
+def AArch64MIR_sabd : AArch64MIR_TargetOp<"sabd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SABD_ZPmZ_B SABD_ZPmZ_D SABD_ZPmZ_H SABD_ZPmZ_S SABDv2i32 SABDv4i16 SABDv4i32 SABDv8i8 SABDv8i16 SABDv16i8
+}
+
+def AArch64MIR_sadalp : AArch64MIR_TargetOp<"sadalp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADALP_ZPmZ_D SADALP_ZPmZ_H SADALP_ZPmZ_S SADALPv2i32_v1i64 SADALPv4i16_v2i32 SADALPv4i32_v2i64 SADALPv8i8_v4i16 SADALPv8i16_v4i32 SADALPv16i8_v8i16
+}
+
+def AArch64MIR_saddlbt : AArch64MIR_TargetOp<"saddlbt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDLBT_ZZZ_D SADDLBT_ZZZ_H SADDLBT_ZZZ_S
+}
+
+def AArch64MIR_saddlb : AArch64MIR_TargetOp<"saddlb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDLB_ZZZ_D SADDLB_ZZZ_H SADDLB_ZZZ_S
+}
+
+def AArch64MIR_saddlp : AArch64MIR_TargetOp<"saddlp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDLPv2i32_v1i64 SADDLPv4i16_v2i32 SADDLPv4i32_v2i64 SADDLPv8i8_v4i16 SADDLPv8i16_v4i32 SADDLPv16i8_v8i16
+}
+
+def AArch64MIR_saddlt : AArch64MIR_TargetOp<"saddlt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDLT_ZZZ_D SADDLT_ZZZ_H SADDLT_ZZZ_S
+}
+
+def AArch64MIR_saddlv : AArch64MIR_TargetOp<"saddlv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDLVv4i16v SADDLVv4i32v SADDLVv8i8v SADDLVv8i16v SADDLVv16i8v
+}
+
+def AArch64MIR_saddl : AArch64MIR_TargetOp<"saddl", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDLv2i32_v2i64 SADDLv4i16_v4i32 SADDLv8i8_v8i16
+}
+
+def AArch64MIR_saddl2 : AArch64MIR_TargetOp<"saddl2", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDLv4i32_v2i64 SADDLv8i16_v4i32 SADDLv16i8_v8i16
+}
+
+def AArch64MIR_saddv : AArch64MIR_TargetOp<"saddv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDV_VPZ_B SADDV_VPZ_H SADDV_VPZ_S
+}
+
+def AArch64MIR_saddwb : AArch64MIR_TargetOp<"saddwb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDWB_ZZZ_D SADDWB_ZZZ_H SADDWB_ZZZ_S
+}
+
+def AArch64MIR_saddwt : AArch64MIR_TargetOp<"saddwt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDWT_ZZZ_D SADDWT_ZZZ_H SADDWT_ZZZ_S
+}
+
+def AArch64MIR_saddw : AArch64MIR_TargetOp<"saddw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDWv2i32_v2i64 SADDWv4i16_v4i32 SADDWv8i8_v8i16
+}
+
+def AArch64MIR_saddw2 : AArch64MIR_TargetOp<"saddw2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SADDWv4i32_v2i64 SADDWv8i16_v4i32 SADDWv16i8_v8i16
+}
+
+def AArch64MIR_sb : AArch64MIR_TargetOp<"sb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SB
+}
+
+def AArch64MIR_sbclb : AArch64MIR_TargetOp<"sbclb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SBCLB_ZZZ_D SBCLB_ZZZ_S
+}
+
+def AArch64MIR_sbclt : AArch64MIR_TargetOp<"sbclt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SBCLT_ZZZ_D SBCLT_ZZZ_S
+}
+
+def AArch64MIR_sbcs : AArch64MIR_TargetOp<"sbcs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SBCSWr SBCSXr
+}
+
+def AArch64MIR_sbc : AArch64MIR_TargetOp<"sbc", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SBCWr SBCXr
+}
+
+def AArch64MIR_sbfm : AArch64MIR_TargetOp<"sbfm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SBFMWri SBFMXri
+}
+
+def AArch64MIR_sclamp : AArch64MIR_TargetOp<"sclamp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SCLAMP_VG2_2Z2Z_B SCLAMP_VG2_2Z2Z_D SCLAMP_VG2_2Z2Z_H SCLAMP_VG2_2Z2Z_S SCLAMP_VG4_4Z4Z_B SCLAMP_VG4_4Z4Z_D SCLAMP_VG4_4Z4Z_H SCLAMP_VG4_4Z4Z_S SCLAMP_ZZZ_B SCLAMP_ZZZ_D SCLAMP_ZZZ_H SCLAMP_ZZZ_S
+}
+
+def AArch64MIR_scvtf : AArch64MIR_TargetOp<"scvtf", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SCVTFDSr SCVTFHDr SCVTFHSr SCVTFSDr SCVTFSWDri SCVTFSWHri SCVTFSWSri SCVTFSXDri SCVTFSXHri SCVTFSXSri SCVTFUWDri SCVTFUWHri SCVTFUWSri SCVTFUXDri SCVTFUXHri SCVTFUXSri SCVTF_2Z2Z_StoS SCVTF_4Z4Z_StoS SCVTF_ZPmZ_DtoD SCVTF_ZPmZ_DtoH SCVTF_ZPmZ_DtoS SCVTF_ZPmZ_HtoH SCVTF_ZPmZ_StoD SCVTF_ZPmZ_StoH SCVTF_ZPmZ_StoS SCVTF_ZPzZ_DtoD SCVTF_ZPzZ_DtoH SCVTF_ZPzZ_DtoS SCVTF_ZPzZ_HtoH SCVTF_ZPzZ_StoD SCVTF_ZPzZ_StoH SCVTF_ZPzZ_StoS SCVTF_ZZ_BtoH SCVTF_ZZ_HtoS SCVTF_ZZ_StoD SCVTFd SCVTFh SCVTFs SCVTFv1i16 SCVTFv1i32 SCVTFv1i64 SCVTFv2f32 SCVTFv2f64 SCVTFv2i32_shift SCVTFv2i64_shift SCVTFv4f16 SCVTFv4f32 SCVTFv4i16_shift SCVTFv4i32_shift SCVTFv8f16 SCVTFv8i16_shift
+}
+
+def AArch64MIR_scvtflt : AArch64MIR_TargetOp<"scvtflt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SCVTFLT_ZZ_BtoH SCVTFLT_ZZ_HtoS SCVTFLT_ZZ_StoD
+}
+
+def AArch64MIR_sdivr : AArch64MIR_TargetOp<"sdivr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SDIVR_ZPmZ_D SDIVR_ZPmZ_S
+}
+
+def AArch64MIR_sdiv : AArch64MIR_TargetOp<"sdiv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SDIVWr SDIVXr SDIV_ZPmZ_D SDIV_ZPmZ_S
+}
+
+def AArch64MIR_sdot : AArch64MIR_TargetOp<"sdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SDOT_VG2_M2Z2Z_BtoS SDOT_VG2_M2Z2Z_HtoD SDOT_VG2_M2Z2Z_HtoS SDOT_VG2_M2ZZI_BToS SDOT_VG2_M2ZZI_HToS SDOT_VG2_M2ZZI_HtoD SDOT_VG2_M2ZZ_BtoS SDOT_VG2_M2ZZ_HtoD SDOT_VG2_M2ZZ_HtoS SDOT_VG4_M4Z4Z_BtoS SDOT_VG4_M4Z4Z_HtoD SDOT_VG4_M4Z4Z_HtoS SDOT_VG4_M4ZZI_BToS SDOT_VG4_M4ZZI_HToS SDOT_VG4_M4ZZI_HtoD SDOT_VG4_M4ZZ_BtoS SDOT_VG4_M4ZZ_HtoD SDOT_VG4_M4ZZ_HtoS SDOT_ZZZI_BtoH SDOT_ZZZI_BtoS SDOT_ZZZI_HtoD SDOT_ZZZI_HtoS SDOT_ZZZ_BtoH SDOT_ZZZ_BtoS SDOT_ZZZ_HtoD SDOT_ZZZ_HtoS SDOTlanev8i8 SDOTlanev16i8 SDOTv8i8 SDOTv16i8
+}
+
+def AArch64MIR_sel : AArch64MIR_TargetOp<"sel", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SEL_PPPP SEL_VG2_2ZC2Z2Z_B SEL_VG2_2ZC2Z2Z_D SEL_VG2_2ZC2Z2Z_H SEL_VG2_2ZC2Z2Z_S SEL_VG4_4ZC4Z4Z_B SEL_VG4_4ZC4Z4Z_D SEL_VG4_4ZC4Z4Z_H SEL_VG4_4ZC4Z4Z_S SEL_ZPZZ_B SEL_ZPZZ_D SEL_ZPZZ_H SEL_ZPZZ_S
+}
+
+def AArch64MIR_sete : AArch64MIR_TargetOp<"sete", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETE
+}
+
+def AArch64MIR_seten : AArch64MIR_TargetOp<"seten", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETEN
+}
+
+def AArch64MIR_setet : AArch64MIR_TargetOp<"setet", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETET
+}
+
+def AArch64MIR_setetn : AArch64MIR_TargetOp<"setetn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETETN
+}
+
+def AArch64MIR_setf8 : AArch64MIR_TargetOp<"setf8", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETF8
+}
+
+def AArch64MIR_setf16 : AArch64MIR_TargetOp<"setf16", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETF16
+}
+
+def AArch64MIR_setffr : AArch64MIR_TargetOp<"setffr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETFFR
+}
+
+def AArch64MIR_setgm : AArch64MIR_TargetOp<"setgm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGM
+}
+
+def AArch64MIR_setgmn : AArch64MIR_TargetOp<"setgmn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGMN
+}
+
+def AArch64MIR_setgmt : AArch64MIR_TargetOp<"setgmt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGMT
+}
+
+def AArch64MIR_setgmtn : AArch64MIR_TargetOp<"setgmtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGMTN
+}
+
+def AArch64MIR_setgoe : AArch64MIR_TargetOp<"setgoe", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOE
+}
+
+def AArch64MIR_setgoen : AArch64MIR_TargetOp<"setgoen", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOEN
+}
+
+def AArch64MIR_setgoet : AArch64MIR_TargetOp<"setgoet", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOET
+}
+
+def AArch64MIR_setgoetn : AArch64MIR_TargetOp<"setgoetn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOETN
+}
+
+def AArch64MIR_setgom : AArch64MIR_TargetOp<"setgom", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOM
+}
+
+def AArch64MIR_setgomn : AArch64MIR_TargetOp<"setgomn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOMN
+}
+
+def AArch64MIR_setgomt : AArch64MIR_TargetOp<"setgomt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOMT
+}
+
+def AArch64MIR_setgomtn : AArch64MIR_TargetOp<"setgomtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOMTN
+}
+
+def AArch64MIR_setgop : AArch64MIR_TargetOp<"setgop", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOP
+}
+
+def AArch64MIR_setgopn : AArch64MIR_TargetOp<"setgopn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOPN
+}
+
+def AArch64MIR_setgopt : AArch64MIR_TargetOp<"setgopt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOPT
+}
+
+def AArch64MIR_setgoptn : AArch64MIR_TargetOp<"setgoptn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGOPTN
+}
+
+def AArch64MIR_setgp : AArch64MIR_TargetOp<"setgp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGP
+}
+
+def AArch64MIR_setgpn : AArch64MIR_TargetOp<"setgpn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGPN
+}
+
+def AArch64MIR_setgpt : AArch64MIR_TargetOp<"setgpt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGPT
+}
+
+def AArch64MIR_setgptn : AArch64MIR_TargetOp<"setgptn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETGPTN
+}
+
+def AArch64MIR_setm : AArch64MIR_TargetOp<"setm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETM
+}
+
+def AArch64MIR_setmn : AArch64MIR_TargetOp<"setmn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETMN
+}
+
+def AArch64MIR_setmt : AArch64MIR_TargetOp<"setmt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETMT
+}
+
+def AArch64MIR_setmtn : AArch64MIR_TargetOp<"setmtn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETMTN
+}
+
+def AArch64MIR_setp : AArch64MIR_TargetOp<"setp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETP
+}
+
+def AArch64MIR_setpn : AArch64MIR_TargetOp<"setpn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETPN
+}
+
+def AArch64MIR_setpt : AArch64MIR_TargetOp<"setpt", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETPT
+}
+
+def AArch64MIR_setptn : AArch64MIR_TargetOp<"setptn", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SETPTN
+}
+
+def AArch64MIR_sha1c : AArch64MIR_TargetOp<"sha1c", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA1Crrr
+}
+
+def AArch64MIR_sha1h : AArch64MIR_TargetOp<"sha1h", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA1Hrr
+}
+
+def AArch64MIR_sha1m : AArch64MIR_TargetOp<"sha1m", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA1Mrrr
+}
+
+def AArch64MIR_sha1p : AArch64MIR_TargetOp<"sha1p", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA1Prrr
+}
+
+def AArch64MIR_sha1su0 : AArch64MIR_TargetOp<"sha1su0", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA1SU0rrr
+}
+
+def AArch64MIR_sha1su1 : AArch64MIR_TargetOp<"sha1su1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA1SU1rr
+}
+
+def AArch64MIR_sha256h2 : AArch64MIR_TargetOp<"sha256h2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA256H2rrr
+}
+
+def AArch64MIR_sha256h : AArch64MIR_TargetOp<"sha256h", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA256Hrrr
+}
+
+def AArch64MIR_sha256su0 : AArch64MIR_TargetOp<"sha256su0", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA256SU0rr
+}
+
+def AArch64MIR_sha256su1 : AArch64MIR_TargetOp<"sha256su1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA256SU1rrr
+}
+
+def AArch64MIR_sha512h : AArch64MIR_TargetOp<"sha512h", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA512H
+}
+
+def AArch64MIR_sha512h2 : AArch64MIR_TargetOp<"sha512h2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA512H2
+}
+
+def AArch64MIR_sha512su0 : AArch64MIR_TargetOp<"sha512su0", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA512SU0
+}
+
+def AArch64MIR_sha512su1 : AArch64MIR_TargetOp<"sha512su1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHA512SU1
+}
+
+def AArch64MIR_shadd : AArch64MIR_TargetOp<"shadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHADD_ZPmZ_B SHADD_ZPmZ_D SHADD_ZPmZ_H SHADD_ZPmZ_S SHADDv2i32 SHADDv4i16 SHADDv4i32 SHADDv8i8 SHADDv8i16 SHADDv16i8
+}
+
+def AArch64MIR_shll : AArch64MIR_TargetOp<"shll", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHLLv2i32 SHLLv4i16 SHLLv8i8
+}
+
+def AArch64MIR_shll2 : AArch64MIR_TargetOp<"shll2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHLLv4i32 SHLLv8i16 SHLLv16i8
+}
+
+def AArch64MIR_shl : AArch64MIR_TargetOp<"shl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHLd SHLv2i32_shift SHLv2i64_shift SHLv4i16_shift SHLv4i32_shift SHLv8i8_shift SHLv8i16_shift SHLv16i8_shift
+}
+
+def AArch64MIR_shrnb : AArch64MIR_TargetOp<"shrnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHRNB_ZZI_B SHRNB_ZZI_H SHRNB_ZZI_S
+}
+
+def AArch64MIR_shrnt : AArch64MIR_TargetOp<"shrnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHRNT_ZZI_B SHRNT_ZZI_H SHRNT_ZZI_S
+}
+
+def AArch64MIR_shrn : AArch64MIR_TargetOp<"shrn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHRNv2i32_shift SHRNv4i16_shift SHRNv8i8_shift
+}
+
+def AArch64MIR_shrn2 : AArch64MIR_TargetOp<"shrn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHRNv4i32_shift SHRNv8i16_shift SHRNv16i8_shift
+}
+
+def AArch64MIR_shsubr : AArch64MIR_TargetOp<"shsubr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHSUBR_ZPmZ_B SHSUBR_ZPmZ_D SHSUBR_ZPmZ_H SHSUBR_ZPmZ_S
+}
+
+def AArch64MIR_shsub : AArch64MIR_TargetOp<"shsub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SHSUB_ZPmZ_B SHSUB_ZPmZ_D SHSUB_ZPmZ_H SHSUB_ZPmZ_S SHSUBv2i32 SHSUBv4i16 SHSUBv4i32 SHSUBv8i8 SHSUBv8i16 SHSUBv16i8
+}
+
+def AArch64MIR_sli : AArch64MIR_TargetOp<"sli", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SLI_ZZI_B SLI_ZZI_D SLI_ZZI_H SLI_ZZI_S SLId SLIv2i32_shift SLIv2i64_shift SLIv4i16_shift SLIv4i32_shift SLIv8i8_shift SLIv8i16_shift SLIv16i8_shift
+}
+
+def AArch64MIR_sm3partw1 : AArch64MIR_TargetOp<"sm3partw1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM3PARTW1
+}
+
+def AArch64MIR_sm3partw2 : AArch64MIR_TargetOp<"sm3partw2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM3PARTW2
+}
+
+def AArch64MIR_sm3ss1 : AArch64MIR_TargetOp<"sm3ss1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM3SS1
+}
+
+def AArch64MIR_sm3tt1a : AArch64MIR_TargetOp<"sm3tt1a", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM3TT1A
+}
+
+def AArch64MIR_sm3tt1b : AArch64MIR_TargetOp<"sm3tt1b", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM3TT1B
+}
+
+def AArch64MIR_sm3tt2a : AArch64MIR_TargetOp<"sm3tt2a", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM3TT2A
+}
+
+def AArch64MIR_sm3tt2b : AArch64MIR_TargetOp<"sm3tt2b", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM3TT2B
+}
+
+def AArch64MIR_sm4e : AArch64MIR_TargetOp<"sm4e", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM4E SM4E_ZZZ_S
+}
+
+def AArch64MIR_sm4ekey : AArch64MIR_TargetOp<"sm4ekey", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SM4EKEY_ZZZ_S SM4ENCKEY
+}
+
+def AArch64MIR_smaddl : AArch64MIR_TargetOp<"smaddl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMADDLrrr
+}
+
+def AArch64MIR_smaxp : AArch64MIR_TargetOp<"smaxp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMAXP_ZPmZ_B SMAXP_ZPmZ_D SMAXP_ZPmZ_H SMAXP_ZPmZ_S SMAXPv2i32 SMAXPv4i16 SMAXPv4i32 SMAXPv8i8 SMAXPv8i16 SMAXPv16i8
+}
+
+def AArch64MIR_smaxqv : AArch64MIR_TargetOp<"smaxqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMAXQV_VPZ_B SMAXQV_VPZ_D SMAXQV_VPZ_H SMAXQV_VPZ_S
+}
+
+def AArch64MIR_smaxv : AArch64MIR_TargetOp<"smaxv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMAXV_VPZ_B SMAXV_VPZ_D SMAXV_VPZ_H SMAXV_VPZ_S SMAXVv4i16v SMAXVv4i32v SMAXVv8i8v SMAXVv8i16v SMAXVv16i8v
+}
+
+def AArch64MIR_smax : AArch64MIR_TargetOp<"smax", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMAXWri SMAXWrr SMAXXri SMAXXrr SMAX_VG2_2Z2Z_B SMAX_VG2_2Z2Z_D SMAX_VG2_2Z2Z_H SMAX_VG2_2Z2Z_S SMAX_VG2_2ZZ_B SMAX_VG2_2ZZ_D SMAX_VG2_2ZZ_H SMAX_VG2_2ZZ_S SMAX_VG4_4Z4Z_B SMAX_VG4_4Z4Z_D SMAX_VG4_4Z4Z_H SMAX_VG4_4Z4Z_S SMAX_VG4_4ZZ_B SMAX_VG4_4ZZ_D SMAX_VG4_4ZZ_H SMAX_VG4_4ZZ_S SMAX_ZI_B SMAX_ZI_D SMAX_ZI_H SMAX_ZI_S SMAX_ZPmZ_B SMAX_ZPmZ_D SMAX_ZPmZ_H SMAX_ZPmZ_S SMAXv2i32 SMAXv4i16 SMAXv4i32 SMAXv8i8 SMAXv8i16 SMAXv16i8
+}
+
+def AArch64MIR_smc : AArch64MIR_TargetOp<"smc", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMC
+}
+
+def AArch64MIR_sminp : AArch64MIR_TargetOp<"sminp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMINP_ZPmZ_B SMINP_ZPmZ_D SMINP_ZPmZ_H SMINP_ZPmZ_S SMINPv2i32 SMINPv4i16 SMINPv4i32 SMINPv8i8 SMINPv8i16 SMINPv16i8
+}
+
+def AArch64MIR_sminqv : AArch64MIR_TargetOp<"sminqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMINQV_VPZ_B SMINQV_VPZ_D SMINQV_VPZ_H SMINQV_VPZ_S
+}
+
+def AArch64MIR_sminv : AArch64MIR_TargetOp<"sminv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMINV_VPZ_B SMINV_VPZ_D SMINV_VPZ_H SMINV_VPZ_S SMINVv4i16v SMINVv4i32v SMINVv8i8v SMINVv8i16v SMINVv16i8v
+}
+
+def AArch64MIR_smin : AArch64MIR_TargetOp<"smin", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMINWri SMINWrr SMINXri SMINXrr SMIN_VG2_2Z2Z_B SMIN_VG2_2Z2Z_D SMIN_VG2_2Z2Z_H SMIN_VG2_2Z2Z_S SMIN_VG2_2ZZ_B SMIN_VG2_2ZZ_D SMIN_VG2_2ZZ_H SMIN_VG2_2ZZ_S SMIN_VG4_4Z4Z_B SMIN_VG4_4Z4Z_D SMIN_VG4_4Z4Z_H SMIN_VG4_4Z4Z_S SMIN_VG4_4ZZ_B SMIN_VG4_4ZZ_D SMIN_VG4_4ZZ_H SMIN_VG4_4ZZ_S SMIN_ZI_B SMIN_ZI_D SMIN_ZI_H SMIN_ZI_S SMIN_ZPmZ_B SMIN_ZPmZ_D SMIN_ZPmZ_H SMIN_ZPmZ_S SMINv2i32 SMINv4i16 SMINv4i32 SMINv8i8 SMINv8i16 SMINv16i8
+}
+
+def AArch64MIR_smlalb : AArch64MIR_TargetOp<"smlalb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLALB_ZZZI_D SMLALB_ZZZI_S SMLALB_ZZZ_D SMLALB_ZZZ_H SMLALB_ZZZ_S
+}
+
+def AArch64MIR_smlall : AArch64MIR_TargetOp<"smlall", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLALL_MZZI_BtoS SMLALL_MZZI_HtoD SMLALL_MZZ_BtoS SMLALL_MZZ_HtoD SMLALL_VG2_M2Z2Z_BtoS SMLALL_VG2_M2Z2Z_HtoD SMLALL_VG2_M2ZZI_BtoS SMLALL_VG2_M2ZZI_HtoD SMLALL_VG2_M2ZZ_BtoS SMLALL_VG2_M2ZZ_HtoD SMLALL_VG4_M4Z4Z_BtoS SMLALL_VG4_M4Z4Z_HtoD SMLALL_VG4_M4ZZI_BtoS SMLALL_VG4_M4ZZI_HtoD SMLALL_VG4_M4ZZ_BtoS SMLALL_VG4_M4ZZ_HtoD
+}
+
+def AArch64MIR_smlalt : AArch64MIR_TargetOp<"smlalt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLALT_ZZZI_D SMLALT_ZZZI_S SMLALT_ZZZ_D SMLALT_ZZZ_H SMLALT_ZZZ_S
+}
+
+def AArch64MIR_smlal : AArch64MIR_TargetOp<"smlal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLAL_MZZI_HtoS SMLAL_MZZ_HtoS SMLAL_VG2_M2Z2Z_HtoS SMLAL_VG2_M2ZZI_S SMLAL_VG2_M2ZZ_HtoS SMLAL_VG4_M4Z4Z_HtoS SMLAL_VG4_M4ZZI_HtoS SMLAL_VG4_M4ZZ_HtoS SMLALv2i32_indexed SMLALv2i32_v2i64 SMLALv4i16_indexed SMLALv4i16_v4i32 SMLALv8i8_v8i16
+}
+
+def AArch64MIR_smlal2 : AArch64MIR_TargetOp<"smlal2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLALv4i32_indexed SMLALv4i32_v2i64 SMLALv8i16_indexed SMLALv8i16_v4i32 SMLALv16i8_v8i16
+}
+
+def AArch64MIR_smlslb : AArch64MIR_TargetOp<"smlslb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLSLB_ZZZI_D SMLSLB_ZZZI_S SMLSLB_ZZZ_D SMLSLB_ZZZ_H SMLSLB_ZZZ_S
+}
+
+def AArch64MIR_smlsll : AArch64MIR_TargetOp<"smlsll", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLSLL_MZZI_BtoS SMLSLL_MZZI_HtoD SMLSLL_MZZ_BtoS SMLSLL_MZZ_HtoD SMLSLL_VG2_M2Z2Z_BtoS SMLSLL_VG2_M2Z2Z_HtoD SMLSLL_VG2_M2ZZI_BtoS SMLSLL_VG2_M2ZZI_HtoD SMLSLL_VG2_M2ZZ_BtoS SMLSLL_VG2_M2ZZ_HtoD SMLSLL_VG4_M4Z4Z_BtoS SMLSLL_VG4_M4Z4Z_HtoD SMLSLL_VG4_M4ZZI_BtoS SMLSLL_VG4_M4ZZI_HtoD SMLSLL_VG4_M4ZZ_BtoS SMLSLL_VG4_M4ZZ_HtoD
+}
+
+def AArch64MIR_smlslt : AArch64MIR_TargetOp<"smlslt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLSLT_ZZZI_D SMLSLT_ZZZI_S SMLSLT_ZZZ_D SMLSLT_ZZZ_H SMLSLT_ZZZ_S
+}
+
+def AArch64MIR_smlsl : AArch64MIR_TargetOp<"smlsl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLSL_MZZI_HtoS SMLSL_MZZ_HtoS SMLSL_VG2_M2Z2Z_HtoS SMLSL_VG2_M2ZZI_S SMLSL_VG2_M2ZZ_HtoS SMLSL_VG4_M4Z4Z_HtoS SMLSL_VG4_M4ZZI_HtoS SMLSL_VG4_M4ZZ_HtoS SMLSLv2i32_indexed SMLSLv2i32_v2i64 SMLSLv4i16_indexed SMLSLv4i16_v4i32 SMLSLv8i8_v8i16
+}
+
+def AArch64MIR_smlsl2 : AArch64MIR_TargetOp<"smlsl2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMLSLv4i32_indexed SMLSLv4i32_v2i64 SMLSLv8i16_indexed SMLSLv8i16_v4i32 SMLSLv16i8_v8i16
+}
+
+def AArch64MIR_smmla : AArch64MIR_TargetOp<"smmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMMLA SMMLA_ZZZ
+}
+
+def AArch64MIR_smop4a : AArch64MIR_TargetOp<"smop4a", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMOP4A_M2Z2Z_BToS SMOP4A_M2Z2Z_HToS SMOP4A_M2Z2Z_HtoD SMOP4A_M2ZZ_BToS SMOP4A_M2ZZ_HToS SMOP4A_M2ZZ_HtoD SMOP4A_MZ2Z_BToS SMOP4A_MZ2Z_HToS SMOP4A_MZ2Z_HtoD SMOP4A_MZZ_BToS SMOP4A_MZZ_HToS SMOP4A_MZZ_HtoD
+}
+
+def AArch64MIR_smop4s : AArch64MIR_TargetOp<"smop4s", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMOP4S_M2Z2Z_BToS SMOP4S_M2Z2Z_HToS SMOP4S_M2Z2Z_HtoD SMOP4S_M2ZZ_BToS SMOP4S_M2ZZ_HToS SMOP4S_M2ZZ_HtoD SMOP4S_MZ2Z_BToS SMOP4S_MZ2Z_HToS SMOP4S_MZ2Z_HtoD SMOP4S_MZZ_BToS SMOP4S_MZZ_HToS SMOP4S_MZZ_HtoD
+}
+
+def AArch64MIR_smopa : AArch64MIR_TargetOp<"smopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMOPA_MPPZZ_D SMOPA_MPPZZ_HtoS SMOPA_MPPZZ_S
+}
+
+def AArch64MIR_smops : AArch64MIR_TargetOp<"smops", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMOPS_MPPZZ_D SMOPS_MPPZZ_HtoS SMOPS_MPPZZ_S
+}
+
+def AArch64MIR_smov : AArch64MIR_TargetOp<"smov", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMOVvi8to32 SMOVvi8to32_idx0 SMOVvi8to64 SMOVvi8to64_idx0 SMOVvi16to32 SMOVvi16to32_idx0 SMOVvi16to64 SMOVvi16to64_idx0 SMOVvi32to64 SMOVvi32to64_idx0
+}
+
+def AArch64MIR_smsubl : AArch64MIR_TargetOp<"smsubl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMSUBLrrr
+}
+
+def AArch64MIR_smulh : AArch64MIR_TargetOp<"smulh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMULH_ZPmZ_B SMULH_ZPmZ_D SMULH_ZPmZ_H SMULH_ZPmZ_S SMULH_ZZZ_B SMULH_ZZZ_D SMULH_ZZZ_H SMULH_ZZZ_S SMULHrr
+}
+
+def AArch64MIR_smullb : AArch64MIR_TargetOp<"smullb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMULLB_ZZZI_D SMULLB_ZZZI_S SMULLB_ZZZ_D SMULLB_ZZZ_H SMULLB_ZZZ_S
+}
+
+def AArch64MIR_smullt : AArch64MIR_TargetOp<"smullt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMULLT_ZZZI_D SMULLT_ZZZI_S SMULLT_ZZZ_D SMULLT_ZZZ_H SMULLT_ZZZ_S
+}
+
+def AArch64MIR_smull : AArch64MIR_TargetOp<"smull", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMULLv2i32_indexed SMULLv2i32_v2i64 SMULLv4i16_indexed SMULLv4i16_v4i32 SMULLv8i8_v8i16
+}
+
+def AArch64MIR_smull2 : AArch64MIR_TargetOp<"smull2", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SMULLv4i32_indexed SMULLv4i32_v2i64 SMULLv8i16_indexed SMULLv8i16_v4i32 SMULLv16i8_v8i16
+}
+
+def AArch64MIR_splice : AArch64MIR_TargetOp<"splice", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SPLICE_ZPZZ_B SPLICE_ZPZZ_D SPLICE_ZPZZ_H SPLICE_ZPZZ_S SPLICE_ZPZ_B SPLICE_ZPZ_D SPLICE_ZPZ_H SPLICE_ZPZ_S
+}
+
+def AArch64MIR_sqabs : AArch64MIR_TargetOp<"sqabs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQABS_ZPmZ_B SQABS_ZPmZ_D SQABS_ZPmZ_H SQABS_ZPmZ_S SQABS_ZPzZ_B SQABS_ZPzZ_D SQABS_ZPzZ_H SQABS_ZPzZ_S SQABSv1i8 SQABSv1i16 SQABSv1i32 SQABSv1i64 SQABSv2i32 SQABSv2i64 SQABSv4i16 SQABSv4i32 SQABSv8i8 SQABSv8i16 SQABSv16i8
+}
+
+def AArch64MIR_sqadd : AArch64MIR_TargetOp<"sqadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQADD_ZI_B SQADD_ZI_D SQADD_ZI_H SQADD_ZI_S SQADD_ZPmZ_B SQADD_ZPmZ_D SQADD_ZPmZ_H SQADD_ZPmZ_S SQADD_ZZZ_B SQADD_ZZZ_D SQADD_ZZZ_H SQADD_ZZZ_S SQADDv1i8 SQADDv1i16 SQADDv1i32 SQADDv1i64 SQADDv2i32 SQADDv2i64 SQADDv4i16 SQADDv4i32 SQADDv8i8 SQADDv8i16 SQADDv16i8
+}
+
+def AArch64MIR_sqcadd : AArch64MIR_TargetOp<"sqcadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQCADD_ZZI_B SQCADD_ZZI_D SQCADD_ZZI_H SQCADD_ZZI_S
+}
+
+def AArch64MIR_sqcvtn : AArch64MIR_TargetOp<"sqcvtn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQCVTN_Z2Z_StoH SQCVTN_Z4Z_DtoH SQCVTN_Z4Z_StoB
+}
+
+def AArch64MIR_sqcvtun : AArch64MIR_TargetOp<"sqcvtun", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQCVTUN_Z2Z_StoH SQCVTUN_Z4Z_DtoH SQCVTUN_Z4Z_StoB
+}
+
+def AArch64MIR_sqcvtu : AArch64MIR_TargetOp<"sqcvtu", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQCVTU_Z2Z_StoH SQCVTU_Z4Z_DtoH SQCVTU_Z4Z_StoB
+}
+
+def AArch64MIR_sqcvt : AArch64MIR_TargetOp<"sqcvt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQCVT_Z2Z_StoH SQCVT_Z4Z_DtoH SQCVT_Z4Z_StoB
+}
+
+def AArch64MIR_sqdecb : AArch64MIR_TargetOp<"sqdecb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDECB_XPiI SQDECB_XPiWdI
+}
+
+def AArch64MIR_sqdecd : AArch64MIR_TargetOp<"sqdecd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDECD_XPiI SQDECD_XPiWdI SQDECD_ZPiI
+}
+
+def AArch64MIR_sqdech : AArch64MIR_TargetOp<"sqdech", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDECH_XPiI SQDECH_XPiWdI SQDECH_ZPiI
+}
+
+def AArch64MIR_sqdecp : AArch64MIR_TargetOp<"sqdecp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDECP_XPWd_B SQDECP_XPWd_D SQDECP_XPWd_H SQDECP_XPWd_S SQDECP_XP_B SQDECP_XP_D SQDECP_XP_H SQDECP_XP_S SQDECP_ZP_D SQDECP_ZP_H SQDECP_ZP_S
+}
+
+def AArch64MIR_sqdecw : AArch64MIR_TargetOp<"sqdecw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDECW_XPiI SQDECW_XPiWdI SQDECW_ZPiI
+}
+
+def AArch64MIR_sqdmlalbt : AArch64MIR_TargetOp<"sqdmlalbt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLALBT_ZZZ_D SQDMLALBT_ZZZ_H SQDMLALBT_ZZZ_S
+}
+
+def AArch64MIR_sqdmlalb : AArch64MIR_TargetOp<"sqdmlalb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLALB_ZZZI_D SQDMLALB_ZZZI_S SQDMLALB_ZZZ_D SQDMLALB_ZZZ_H SQDMLALB_ZZZ_S
+}
+
+def AArch64MIR_sqdmlalt : AArch64MIR_TargetOp<"sqdmlalt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLALT_ZZZI_D SQDMLALT_ZZZI_S SQDMLALT_ZZZ_D SQDMLALT_ZZZ_H SQDMLALT_ZZZ_S
+}
+
+def AArch64MIR_sqdmlal : AArch64MIR_TargetOp<"sqdmlal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLALi16 SQDMLALi32 SQDMLALv1i32_indexed SQDMLALv1i64_indexed SQDMLALv2i32_indexed SQDMLALv2i32_v2i64 SQDMLALv4i16_indexed SQDMLALv4i16_v4i32
+}
+
+def AArch64MIR_sqdmlal2 : AArch64MIR_TargetOp<"sqdmlal2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLALv4i32_indexed SQDMLALv4i32_v2i64 SQDMLALv8i16_indexed SQDMLALv8i16_v4i32
+}
+
+def AArch64MIR_sqdmlslbt : AArch64MIR_TargetOp<"sqdmlslbt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLSLBT_ZZZ_D SQDMLSLBT_ZZZ_H SQDMLSLBT_ZZZ_S
+}
+
+def AArch64MIR_sqdmlslb : AArch64MIR_TargetOp<"sqdmlslb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLSLB_ZZZI_D SQDMLSLB_ZZZI_S SQDMLSLB_ZZZ_D SQDMLSLB_ZZZ_H SQDMLSLB_ZZZ_S
+}
+
+def AArch64MIR_sqdmlslt : AArch64MIR_TargetOp<"sqdmlslt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLSLT_ZZZI_D SQDMLSLT_ZZZI_S SQDMLSLT_ZZZ_D SQDMLSLT_ZZZ_H SQDMLSLT_ZZZ_S
+}
+
+def AArch64MIR_sqdmlsl : AArch64MIR_TargetOp<"sqdmlsl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLSLi16 SQDMLSLi32 SQDMLSLv1i32_indexed SQDMLSLv1i64_indexed SQDMLSLv2i32_indexed SQDMLSLv2i32_v2i64 SQDMLSLv4i16_indexed SQDMLSLv4i16_v4i32
+}
+
+def AArch64MIR_sqdmlsl2 : AArch64MIR_TargetOp<"sqdmlsl2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMLSLv4i32_indexed SQDMLSLv4i32_v2i64 SQDMLSLv8i16_indexed SQDMLSLv8i16_v4i32
+}
+
+def AArch64MIR_sqdmulh : AArch64MIR_TargetOp<"sqdmulh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMULH_VG2_2Z2Z_B SQDMULH_VG2_2Z2Z_D SQDMULH_VG2_2Z2Z_H SQDMULH_VG2_2Z2Z_S SQDMULH_VG2_2ZZ_B SQDMULH_VG2_2ZZ_D SQDMULH_VG2_2ZZ_H SQDMULH_VG2_2ZZ_S SQDMULH_VG4_4Z4Z_B SQDMULH_VG4_4Z4Z_D SQDMULH_VG4_4Z4Z_H SQDMULH_VG4_4Z4Z_S SQDMULH_VG4_4ZZ_B SQDMULH_VG4_4ZZ_D SQDMULH_VG4_4ZZ_H SQDMULH_VG4_4ZZ_S SQDMULH_ZZZI_D SQDMULH_ZZZI_H SQDMULH_ZZZI_S SQDMULH_ZZZ_B SQDMULH_ZZZ_D SQDMULH_ZZZ_H SQDMULH_ZZZ_S SQDMULHv1i16 SQDMULHv1i16_indexed SQDMULHv1i32 SQDMULHv1i32_indexed SQDMULHv2i32 SQDMULHv2i32_indexed SQDMULHv4i16 SQDMULHv4i16_indexed SQDMULHv4i32 SQDMULHv4i32_indexed SQDMULHv8i16 SQDMULHv8i16_indexed
+}
+
+def AArch64MIR_sqdmullb : AArch64MIR_TargetOp<"sqdmullb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMULLB_ZZZI_D SQDMULLB_ZZZI_S SQDMULLB_ZZZ_D SQDMULLB_ZZZ_H SQDMULLB_ZZZ_S
+}
+
+def AArch64MIR_sqdmullt : AArch64MIR_TargetOp<"sqdmullt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMULLT_ZZZI_D SQDMULLT_ZZZI_S SQDMULLT_ZZZ_D SQDMULLT_ZZZ_H SQDMULLT_ZZZ_S
+}
+
+def AArch64MIR_sqdmull : AArch64MIR_TargetOp<"sqdmull", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMULLi16 SQDMULLi32 SQDMULLv1i32_indexed SQDMULLv1i64_indexed SQDMULLv2i32_indexed SQDMULLv2i32_v2i64 SQDMULLv4i16_indexed SQDMULLv4i16_v4i32
+}
+
+def AArch64MIR_sqdmull2 : AArch64MIR_TargetOp<"sqdmull2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQDMULLv4i32_indexed SQDMULLv4i32_v2i64 SQDMULLv8i16_indexed SQDMULLv8i16_v4i32
+}
+
+def AArch64MIR_sqincb : AArch64MIR_TargetOp<"sqincb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQINCB_XPiI SQINCB_XPiWdI
+}
+
+def AArch64MIR_sqincd : AArch64MIR_TargetOp<"sqincd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQINCD_XPiI SQINCD_XPiWdI SQINCD_ZPiI
+}
+
+def AArch64MIR_sqinch : AArch64MIR_TargetOp<"sqinch", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQINCH_XPiI SQINCH_XPiWdI SQINCH_ZPiI
+}
+
+def AArch64MIR_sqincp : AArch64MIR_TargetOp<"sqincp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQINCP_XPWd_B SQINCP_XPWd_D SQINCP_XPWd_H SQINCP_XPWd_S SQINCP_XP_B SQINCP_XP_D SQINCP_XP_H SQINCP_XP_S SQINCP_ZP_D SQINCP_ZP_H SQINCP_ZP_S
+}
+
+def AArch64MIR_sqincw : AArch64MIR_TargetOp<"sqincw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQINCW_XPiI SQINCW_XPiWdI SQINCW_ZPiI
+}
+
+def AArch64MIR_sqneg : AArch64MIR_TargetOp<"sqneg", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQNEG_ZPmZ_B SQNEG_ZPmZ_D SQNEG_ZPmZ_H SQNEG_ZPmZ_S SQNEG_ZPzZ_B SQNEG_ZPzZ_D SQNEG_ZPzZ_H SQNEG_ZPzZ_S SQNEGv1i8 SQNEGv1i16 SQNEGv1i32 SQNEGv1i64 SQNEGv2i32 SQNEGv2i64 SQNEGv4i16 SQNEGv4i32 SQNEGv8i8 SQNEGv8i16 SQNEGv16i8
+}
+
+def AArch64MIR_sqrdcmlah : AArch64MIR_TargetOp<"sqrdcmlah", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRDCMLAH_ZZZI_H SQRDCMLAH_ZZZI_S SQRDCMLAH_ZZZ_B SQRDCMLAH_ZZZ_D SQRDCMLAH_ZZZ_H SQRDCMLAH_ZZZ_S
+}
+
+def AArch64MIR_sqrdmlah : AArch64MIR_TargetOp<"sqrdmlah", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRDMLAH_ZZZI_D SQRDMLAH_ZZZI_H SQRDMLAH_ZZZI_S SQRDMLAH_ZZZ_B SQRDMLAH_ZZZ_D SQRDMLAH_ZZZ_H SQRDMLAH_ZZZ_S SQRDMLAHv1i16 SQRDMLAHv1i16_indexed SQRDMLAHv1i32 SQRDMLAHv1i32_indexed SQRDMLAHv2i32 SQRDMLAHv2i32_indexed SQRDMLAHv4i16 SQRDMLAHv4i16_indexed SQRDMLAHv4i32 SQRDMLAHv4i32_indexed SQRDMLAHv8i16 SQRDMLAHv8i16_indexed
+}
+
+def AArch64MIR_sqrdmlsh : AArch64MIR_TargetOp<"sqrdmlsh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRDMLSH_ZZZI_D SQRDMLSH_ZZZI_H SQRDMLSH_ZZZI_S SQRDMLSH_ZZZ_B SQRDMLSH_ZZZ_D SQRDMLSH_ZZZ_H SQRDMLSH_ZZZ_S SQRDMLSHv1i16 SQRDMLSHv1i16_indexed SQRDMLSHv1i32 SQRDMLSHv1i32_indexed SQRDMLSHv2i32 SQRDMLSHv2i32_indexed SQRDMLSHv4i16 SQRDMLSHv4i16_indexed SQRDMLSHv4i32 SQRDMLSHv4i32_indexed SQRDMLSHv8i16 SQRDMLSHv8i16_indexed
+}
+
+def AArch64MIR_sqrdmulh : AArch64MIR_TargetOp<"sqrdmulh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRDMULH_ZZZI_D SQRDMULH_ZZZI_H SQRDMULH_ZZZI_S SQRDMULH_ZZZ_B SQRDMULH_ZZZ_D SQRDMULH_ZZZ_H SQRDMULH_ZZZ_S SQRDMULHv1i16 SQRDMULHv1i16_indexed SQRDMULHv1i32 SQRDMULHv1i32_indexed SQRDMULHv2i32 SQRDMULHv2i32_indexed SQRDMULHv4i16 SQRDMULHv4i16_indexed SQRDMULHv4i32 SQRDMULHv4i32_indexed SQRDMULHv8i16 SQRDMULHv8i16_indexed
+}
+
+def AArch64MIR_sqrshlr : AArch64MIR_TargetOp<"sqrshlr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHLR_ZPmZ_B SQRSHLR_ZPmZ_D SQRSHLR_ZPmZ_H SQRSHLR_ZPmZ_S
+}
+
+def AArch64MIR_sqrshl : AArch64MIR_TargetOp<"sqrshl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHL_ZPmZ_B SQRSHL_ZPmZ_D SQRSHL_ZPmZ_H SQRSHL_ZPmZ_S SQRSHLv1i8 SQRSHLv1i16 SQRSHLv1i32 SQRSHLv1i64 SQRSHLv2i32 SQRSHLv2i64 SQRSHLv4i16 SQRSHLv4i32 SQRSHLv8i8 SQRSHLv8i16 SQRSHLv16i8
+}
+
+def AArch64MIR_sqrshrnb : AArch64MIR_TargetOp<"sqrshrnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRNB_ZZI_B SQRSHRNB_ZZI_H SQRSHRNB_ZZI_S
+}
+
+def AArch64MIR_sqrshrnt : AArch64MIR_TargetOp<"sqrshrnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRNT_ZZI_B SQRSHRNT_ZZI_H SQRSHRNT_ZZI_S
+}
+
+def AArch64MIR_sqrshrn : AArch64MIR_TargetOp<"sqrshrn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRN_VG4_Z4ZI_B SQRSHRN_VG4_Z4ZI_H SQRSHRN_Z2ZI_HtoB SQRSHRN_Z2ZI_StoH SQRSHRNb SQRSHRNh SQRSHRNs SQRSHRNv2i32_shift SQRSHRNv4i16_shift SQRSHRNv8i8_shift
+}
+
+def AArch64MIR_sqrshrn2 : AArch64MIR_TargetOp<"sqrshrn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRNv4i32_shift SQRSHRNv8i16_shift SQRSHRNv16i8_shift
+}
+
+def AArch64MIR_sqrshrunb : AArch64MIR_TargetOp<"sqrshrunb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRUNB_ZZI_B SQRSHRUNB_ZZI_H SQRSHRUNB_ZZI_S
+}
+
+def AArch64MIR_sqrshrunt : AArch64MIR_TargetOp<"sqrshrunt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRUNT_ZZI_B SQRSHRUNT_ZZI_H SQRSHRUNT_ZZI_S
+}
+
+def AArch64MIR_sqrshrun : AArch64MIR_TargetOp<"sqrshrun", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRUN_VG4_Z4ZI_B SQRSHRUN_VG4_Z4ZI_H SQRSHRUN_Z2ZI_HtoB SQRSHRUN_Z2ZI_StoH SQRSHRUNb SQRSHRUNh SQRSHRUNs SQRSHRUNv2i32_shift SQRSHRUNv4i16_shift SQRSHRUNv8i8_shift
+}
+
+def AArch64MIR_sqrshrun2 : AArch64MIR_TargetOp<"sqrshrun2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRUNv4i32_shift SQRSHRUNv8i16_shift SQRSHRUNv16i8_shift
+}
+
+def AArch64MIR_sqrshru : AArch64MIR_TargetOp<"sqrshru", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHRU_VG2_Z2ZI_H SQRSHRU_VG4_Z4ZI_B SQRSHRU_VG4_Z4ZI_H
+}
+
+def AArch64MIR_sqrshr : AArch64MIR_TargetOp<"sqrshr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQRSHR_VG2_Z2ZI_H SQRSHR_VG4_Z4ZI_B SQRSHR_VG4_Z4ZI_H
+}
+
+def AArch64MIR_sqshlr : AArch64MIR_TargetOp<"sqshlr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHLR_ZPmZ_B SQSHLR_ZPmZ_D SQSHLR_ZPmZ_H SQSHLR_ZPmZ_S
+}
+
+def AArch64MIR_sqshlu : AArch64MIR_TargetOp<"sqshlu", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHLU_ZPmI_B SQSHLU_ZPmI_D SQSHLU_ZPmI_H SQSHLU_ZPmI_S SQSHLUb SQSHLUd SQSHLUh SQSHLUs SQSHLUv2i32_shift SQSHLUv2i64_shift SQSHLUv4i16_shift SQSHLUv4i32_shift SQSHLUv8i8_shift SQSHLUv8i16_shift SQSHLUv16i8_shift
+}
+
+def AArch64MIR_sqshl : AArch64MIR_TargetOp<"sqshl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHL_ZPmI_B SQSHL_ZPmI_D SQSHL_ZPmI_H SQSHL_ZPmI_S SQSHL_ZPmZ_B SQSHL_ZPmZ_D SQSHL_ZPmZ_H SQSHL_ZPmZ_S SQSHLb SQSHLd SQSHLh SQSHLs SQSHLv1i8 SQSHLv1i16 SQSHLv1i32 SQSHLv1i64 SQSHLv2i32 SQSHLv2i32_shift SQSHLv2i64 SQSHLv2i64_shift SQSHLv4i16 SQSHLv4i16_shift SQSHLv4i32 SQSHLv4i32_shift SQSHLv8i8 SQSHLv8i8_shift SQSHLv8i16 SQSHLv8i16_shift SQSHLv16i8 SQSHLv16i8_shift
+}
+
+def AArch64MIR_sqshrnb : AArch64MIR_TargetOp<"sqshrnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHRNB_ZZI_B SQSHRNB_ZZI_H SQSHRNB_ZZI_S
+}
+
+def AArch64MIR_sqshrnt : AArch64MIR_TargetOp<"sqshrnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHRNT_ZZI_B SQSHRNT_ZZI_H SQSHRNT_ZZI_S
+}
+
+def AArch64MIR_sqshrn : AArch64MIR_TargetOp<"sqshrn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHRN_Z2ZI_HtoB SQSHRN_Z2ZI_StoH SQSHRNb SQSHRNh SQSHRNs SQSHRNv2i32_shift SQSHRNv4i16_shift SQSHRNv8i8_shift
+}
+
+def AArch64MIR_sqshrn2 : AArch64MIR_TargetOp<"sqshrn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHRNv4i32_shift SQSHRNv8i16_shift SQSHRNv16i8_shift
+}
+
+def AArch64MIR_sqshrunb : AArch64MIR_TargetOp<"sqshrunb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHRUNB_ZZI_B SQSHRUNB_ZZI_H SQSHRUNB_ZZI_S
+}
+
+def AArch64MIR_sqshrunt : AArch64MIR_TargetOp<"sqshrunt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHRUNT_ZZI_B SQSHRUNT_ZZI_H SQSHRUNT_ZZI_S
+}
+
+def AArch64MIR_sqshrun : AArch64MIR_TargetOp<"sqshrun", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHRUN_Z2ZI_HtoB SQSHRUN_Z2ZI_StoH SQSHRUNb SQSHRUNh SQSHRUNs SQSHRUNv2i32_shift SQSHRUNv4i16_shift SQSHRUNv8i8_shift
+}
+
+def AArch64MIR_sqshrun2 : AArch64MIR_TargetOp<"sqshrun2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSHRUNv4i32_shift SQSHRUNv8i16_shift SQSHRUNv16i8_shift
+}
+
+def AArch64MIR_sqsubr : AArch64MIR_TargetOp<"sqsubr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSUBR_ZPmZ_B SQSUBR_ZPmZ_D SQSUBR_ZPmZ_H SQSUBR_ZPmZ_S
+}
+
+def AArch64MIR_sqsub : AArch64MIR_TargetOp<"sqsub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQSUB_ZI_B SQSUB_ZI_D SQSUB_ZI_H SQSUB_ZI_S SQSUB_ZPmZ_B SQSUB_ZPmZ_D SQSUB_ZPmZ_H SQSUB_ZPmZ_S SQSUB_ZZZ_B SQSUB_ZZZ_D SQSUB_ZZZ_H SQSUB_ZZZ_S SQSUBv1i8 SQSUBv1i16 SQSUBv1i32 SQSUBv1i64 SQSUBv2i32 SQSUBv2i64 SQSUBv4i16 SQSUBv4i32 SQSUBv8i8 SQSUBv8i16 SQSUBv16i8
+}
+
+def AArch64MIR_sqxtnb : AArch64MIR_TargetOp<"sqxtnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQXTNB_ZZ_B SQXTNB_ZZ_H SQXTNB_ZZ_S
+}
+
+def AArch64MIR_sqxtnt : AArch64MIR_TargetOp<"sqxtnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQXTNT_ZZ_B SQXTNT_ZZ_H SQXTNT_ZZ_S
+}
+
+def AArch64MIR_sqxtn : AArch64MIR_TargetOp<"sqxtn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQXTNv1i8 SQXTNv1i16 SQXTNv1i32 SQXTNv2i32 SQXTNv4i16 SQXTNv8i8
+}
+
+def AArch64MIR_sqxtn2 : AArch64MIR_TargetOp<"sqxtn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQXTNv4i32 SQXTNv8i16 SQXTNv16i8
+}
+
+def AArch64MIR_sqxtunb : AArch64MIR_TargetOp<"sqxtunb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQXTUNB_ZZ_B SQXTUNB_ZZ_H SQXTUNB_ZZ_S
+}
+
+def AArch64MIR_sqxtunt : AArch64MIR_TargetOp<"sqxtunt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQXTUNT_ZZ_B SQXTUNT_ZZ_H SQXTUNT_ZZ_S
+}
+
+def AArch64MIR_sqxtun : AArch64MIR_TargetOp<"sqxtun", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQXTUNv1i8 SQXTUNv1i16 SQXTUNv1i32 SQXTUNv2i32 SQXTUNv4i16 SQXTUNv8i8
+}
+
+def AArch64MIR_sqxtun2 : AArch64MIR_TargetOp<"sqxtun2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SQXTUNv4i32 SQXTUNv8i16 SQXTUNv16i8
+}
+
+def AArch64MIR_srhadd : AArch64MIR_TargetOp<"srhadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SRHADD_ZPmZ_B SRHADD_ZPmZ_D SRHADD_ZPmZ_H SRHADD_ZPmZ_S SRHADDv2i32 SRHADDv4i16 SRHADDv4i32 SRHADDv8i8 SRHADDv8i16 SRHADDv16i8
+}
+
+def AArch64MIR_sri : AArch64MIR_TargetOp<"sri", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SRI_ZZI_B SRI_ZZI_D SRI_ZZI_H SRI_ZZI_S SRId SRIv2i32_shift SRIv2i64_shift SRIv4i16_shift SRIv4i32_shift SRIv8i8_shift SRIv8i16_shift SRIv16i8_shift
+}
+
+def AArch64MIR_srshlr : AArch64MIR_TargetOp<"srshlr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SRSHLR_ZPmZ_B SRSHLR_ZPmZ_D SRSHLR_ZPmZ_H SRSHLR_ZPmZ_S
+}
+
+def AArch64MIR_srshl : AArch64MIR_TargetOp<"srshl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SRSHL_VG2_2Z2Z_B SRSHL_VG2_2Z2Z_D SRSHL_VG2_2Z2Z_H SRSHL_VG2_2Z2Z_S SRSHL_VG2_2ZZ_B SRSHL_VG2_2ZZ_D SRSHL_VG2_2ZZ_H SRSHL_VG2_2ZZ_S SRSHL_VG4_4Z4Z_B SRSHL_VG4_4Z4Z_D SRSHL_VG4_4Z4Z_H SRSHL_VG4_4Z4Z_S SRSHL_VG4_4ZZ_B SRSHL_VG4_4ZZ_D SRSHL_VG4_4ZZ_H SRSHL_VG4_4ZZ_S SRSHL_ZPmZ_B SRSHL_ZPmZ_D SRSHL_ZPmZ_H SRSHL_ZPmZ_S SRSHLv1i64 SRSHLv2i32 SRSHLv2i64 SRSHLv4i16 SRSHLv4i32 SRSHLv8i8 SRSHLv8i16 SRSHLv16i8
+}
+
+def AArch64MIR_srshr : AArch64MIR_TargetOp<"srshr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SRSHR_ZPmI_B SRSHR_ZPmI_D SRSHR_ZPmI_H SRSHR_ZPmI_S SRSHRd SRSHRv2i32_shift SRSHRv2i64_shift SRSHRv4i16_shift SRSHRv4i32_shift SRSHRv8i8_shift SRSHRv8i16_shift SRSHRv16i8_shift
+}
+
+def AArch64MIR_srsra : AArch64MIR_TargetOp<"srsra", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SRSRA_ZZI_B SRSRA_ZZI_D SRSRA_ZZI_H SRSRA_ZZI_S SRSRAd SRSRAv2i32_shift SRSRAv2i64_shift SRSRAv4i16_shift SRSRAv4i32_shift SRSRAv8i8_shift SRSRAv8i16_shift SRSRAv16i8_shift
+}
+
+def AArch64MIR_sshllb : AArch64MIR_TargetOp<"sshllb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSHLLB_ZZI_D SSHLLB_ZZI_H SSHLLB_ZZI_S
+}
+
+def AArch64MIR_sshllt : AArch64MIR_TargetOp<"sshllt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSHLLT_ZZI_D SSHLLT_ZZI_H SSHLLT_ZZI_S
+}
+
+def AArch64MIR_sshll : AArch64MIR_TargetOp<"sshll", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSHLLv2i32_shift SSHLLv4i16_shift SSHLLv8i8_shift
+}
+
+def AArch64MIR_sshll2 : AArch64MIR_TargetOp<"sshll2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSHLLv4i32_shift SSHLLv8i16_shift SSHLLv16i8_shift
+}
+
+def AArch64MIR_sshl : AArch64MIR_TargetOp<"sshl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSHLv1i64 SSHLv2i32 SSHLv2i64 SSHLv4i16 SSHLv4i32 SSHLv8i8 SSHLv8i16 SSHLv16i8
+}
+
+def AArch64MIR_sshr : AArch64MIR_TargetOp<"sshr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSHRd SSHRv2i32_shift SSHRv2i64_shift SSHRv4i16_shift SSHRv4i32_shift SSHRv8i8_shift SSHRv8i16_shift SSHRv16i8_shift
+}
+
+def AArch64MIR_ssra : AArch64MIR_TargetOp<"ssra", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSRA_ZZI_B SSRA_ZZI_D SSRA_ZZI_H SSRA_ZZI_S SSRAd SSRAv2i32_shift SSRAv2i64_shift SSRAv4i16_shift SSRAv4i32_shift SSRAv8i8_shift SSRAv8i16_shift SSRAv16i8_shift
+}
+
+def AArch64MIR_st1b : AArch64MIR_TargetOp<"st1b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SST1B_D SST1B_D_IMM SST1B_D_SXTW SST1B_D_UXTW SST1B_S_IMM SST1B_S_SXTW SST1B_S_UXTW ST1B ST1B_2Z ST1B_2Z_IMM ST1B_2Z_STRIDED ST1B_2Z_STRIDED_IMM ST1B_4Z ST1B_4Z_IMM ST1B_4Z_STRIDED ST1B_4Z_STRIDED_IMM ST1B_D ST1B_D_IMM ST1B_H ST1B_H_IMM ST1B_IMM ST1B_S ST1B_S_IMM ST1_MXIPXX_H_B ST1_MXIPXX_V_B
+}
+
+def AArch64MIR_st1d : AArch64MIR_TargetOp<"st1d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SST1D SST1D_IMM SST1D_SCALED SST1D_SXTW SST1D_SXTW_SCALED SST1D_UXTW SST1D_UXTW_SCALED ST1D ST1D_2Z ST1D_2Z_IMM ST1D_2Z_STRIDED ST1D_2Z_STRIDED_IMM ST1D_4Z ST1D_4Z_IMM ST1D_4Z_STRIDED ST1D_4Z_STRIDED_IMM ST1D_IMM ST1D_Q ST1D_Q_IMM ST1_MXIPXX_H_D ST1_MXIPXX_V_D
+}
+
+def AArch64MIR_st1h : AArch64MIR_TargetOp<"st1h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SST1H_D SST1H_D_IMM SST1H_D_SCALED SST1H_D_SXTW SST1H_D_SXTW_SCALED SST1H_D_UXTW SST1H_D_UXTW_SCALED SST1H_S_IMM SST1H_S_SXTW SST1H_S_SXTW_SCALED SST1H_S_UXTW SST1H_S_UXTW_SCALED ST1H ST1H_2Z ST1H_2Z_IMM ST1H_2Z_STRIDED ST1H_2Z_STRIDED_IMM ST1H_4Z ST1H_4Z_IMM ST1H_4Z_STRIDED ST1H_4Z_STRIDED_IMM ST1H_D ST1H_D_IMM ST1H_IMM ST1H_S ST1H_S_IMM ST1_MXIPXX_H_H ST1_MXIPXX_V_H
+}
+
+def AArch64MIR_st1q : AArch64MIR_TargetOp<"st1q", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SST1Q ST1_MXIPXX_H_Q ST1_MXIPXX_V_Q
+}
+
+def AArch64MIR_st1w : AArch64MIR_TargetOp<"st1w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SST1W_D SST1W_D_IMM SST1W_D_SCALED SST1W_D_SXTW SST1W_D_SXTW_SCALED SST1W_D_UXTW SST1W_D_UXTW_SCALED SST1W_IMM SST1W_SXTW SST1W_SXTW_SCALED SST1W_UXTW SST1W_UXTW_SCALED ST1W ST1W_2Z ST1W_2Z_IMM ST1W_2Z_STRIDED ST1W_2Z_STRIDED_IMM ST1W_4Z ST1W_4Z_IMM ST1W_4Z_STRIDED ST1W_4Z_STRIDED_IMM ST1W_D ST1W_D_IMM ST1W_IMM ST1W_Q ST1W_Q_IMM ST1_MXIPXX_H_S ST1_MXIPXX_V_S
+}
+
+def AArch64MIR_ssublbt : AArch64MIR_TargetOp<"ssublbt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBLBT_ZZZ_D SSUBLBT_ZZZ_H SSUBLBT_ZZZ_S
+}
+
+def AArch64MIR_ssublb : AArch64MIR_TargetOp<"ssublb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBLB_ZZZ_D SSUBLB_ZZZ_H SSUBLB_ZZZ_S
+}
+
+def AArch64MIR_ssubltb : AArch64MIR_TargetOp<"ssubltb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBLTB_ZZZ_D SSUBLTB_ZZZ_H SSUBLTB_ZZZ_S
+}
+
+def AArch64MIR_ssublt : AArch64MIR_TargetOp<"ssublt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBLT_ZZZ_D SSUBLT_ZZZ_H SSUBLT_ZZZ_S
+}
+
+def AArch64MIR_ssubl : AArch64MIR_TargetOp<"ssubl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBLv2i32_v2i64 SSUBLv4i16_v4i32 SSUBLv8i8_v8i16
+}
+
+def AArch64MIR_ssubl2 : AArch64MIR_TargetOp<"ssubl2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBLv4i32_v2i64 SSUBLv8i16_v4i32 SSUBLv16i8_v8i16
+}
+
+def AArch64MIR_ssubwb : AArch64MIR_TargetOp<"ssubwb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBWB_ZZZ_D SSUBWB_ZZZ_H SSUBWB_ZZZ_S
+}
+
+def AArch64MIR_ssubwt : AArch64MIR_TargetOp<"ssubwt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBWT_ZZZ_D SSUBWT_ZZZ_H SSUBWT_ZZZ_S
+}
+
+def AArch64MIR_ssubw : AArch64MIR_TargetOp<"ssubw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBWv2i32_v2i64 SSUBWv4i16_v4i32 SSUBWv8i8_v8i16
+}
+
+def AArch64MIR_ssubw2 : AArch64MIR_TargetOp<"ssubw2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SSUBWv4i32_v2i64 SSUBWv8i16_v4i32 SSUBWv16i8_v8i16
+}
+
+def AArch64MIR_st1 : AArch64MIR_TargetOp<"st1", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST1Fourv1d ST1Fourv1d_POST ST1Fourv2d ST1Fourv2d_POST ST1Fourv2s ST1Fourv2s_POST ST1Fourv4h ST1Fourv4h_POST ST1Fourv4s ST1Fourv4s_POST ST1Fourv8b ST1Fourv8b_POST ST1Fourv8h ST1Fourv8h_POST ST1Fourv16b ST1Fourv16b_POST ST1Onev1d ST1Onev1d_POST ST1Onev2d ST1Onev2d_POST ST1Onev2s ST1Onev2s_POST ST1Onev4h ST1Onev4h_POST ST1Onev4s ST1Onev4s_POST ST1Onev8b ST1Onev8b_POST ST1Onev8h ST1Onev8h_POST ST1Onev16b ST1Onev16b_POST ST1Threev1d ST1Threev1d_POST ST1Threev2d ST1Threev2d_POST ST1Threev2s ST1Threev2s_POST ST1Threev4h ST1Threev4h_POST ST1Threev4s ST1Threev4s_POST ST1Threev8b ST1Threev8b_POST ST1Threev8h ST1Threev8h_POST ST1Threev16b ST1Threev16b_POST ST1Twov1d ST1Twov1d_POST ST1Twov2d ST1Twov2d_POST ST1Twov2s ST1Twov2s_POST ST1Twov4h ST1Twov4h_POST ST1Twov4s ST1Twov4s_POST ST1Twov8b ST1Twov8b_POST ST1Twov8h ST1Twov8h_POST ST1Twov16b ST1Twov16b_POST ST1i8 ST1i8_POST ST1i16 ST1i16_POST ST1i32 ST1i32_POST ST1i64 ST1i64_POST
+}
+
+def AArch64MIR_st2b : AArch64MIR_TargetOp<"st2b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST2B ST2B_IMM
+}
+
+def AArch64MIR_st2d : AArch64MIR_TargetOp<"st2d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST2D ST2D_IMM
+}
+
+def AArch64MIR_st2g : AArch64MIR_TargetOp<"st2g", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST2GPostIndex ST2GPreIndex ST2Gi
+}
+
+def AArch64MIR_st2h : AArch64MIR_TargetOp<"st2h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST2H ST2H_IMM
+}
+
+def AArch64MIR_st2q : AArch64MIR_TargetOp<"st2q", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST2Q ST2Q_IMM
+}
+
+def AArch64MIR_st2 : AArch64MIR_TargetOp<"st2", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST2Twov2d ST2Twov2d_POST ST2Twov2s ST2Twov2s_POST ST2Twov4h ST2Twov4h_POST ST2Twov4s ST2Twov4s_POST ST2Twov8b ST2Twov8b_POST ST2Twov8h ST2Twov8h_POST ST2Twov16b ST2Twov16b_POST ST2i8 ST2i8_POST ST2i16 ST2i16_POST ST2i32 ST2i32_POST ST2i64 ST2i64_POST
+}
+
+def AArch64MIR_st2w : AArch64MIR_TargetOp<"st2w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST2W ST2W_IMM
+}
+
+def AArch64MIR_st3b : AArch64MIR_TargetOp<"st3b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST3B ST3B_IMM
+}
+
+def AArch64MIR_st3d : AArch64MIR_TargetOp<"st3d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST3D ST3D_IMM
+}
+
+def AArch64MIR_st3h : AArch64MIR_TargetOp<"st3h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST3H ST3H_IMM
+}
+
+def AArch64MIR_st3q : AArch64MIR_TargetOp<"st3q", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST3Q ST3Q_IMM
+}
+
+def AArch64MIR_st3 : AArch64MIR_TargetOp<"st3", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST3Threev2d ST3Threev2d_POST ST3Threev2s ST3Threev2s_POST ST3Threev4h ST3Threev4h_POST ST3Threev4s ST3Threev4s_POST ST3Threev8b ST3Threev8b_POST ST3Threev8h ST3Threev8h_POST ST3Threev16b ST3Threev16b_POST ST3i8 ST3i8_POST ST3i16 ST3i16_POST ST3i32 ST3i32_POST ST3i64 ST3i64_POST
+}
+
+def AArch64MIR_st3w : AArch64MIR_TargetOp<"st3w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST3W ST3W_IMM
+}
+
+def AArch64MIR_st4b : AArch64MIR_TargetOp<"st4b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST4B ST4B_IMM
+}
+
+def AArch64MIR_st4d : AArch64MIR_TargetOp<"st4d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST4D ST4D_IMM
+}
+
+def AArch64MIR_st4 : AArch64MIR_TargetOp<"st4", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST4Fourv2d ST4Fourv2d_POST ST4Fourv2s ST4Fourv2s_POST ST4Fourv4h ST4Fourv4h_POST ST4Fourv4s ST4Fourv4s_POST ST4Fourv8b ST4Fourv8b_POST ST4Fourv8h ST4Fourv8h_POST ST4Fourv16b ST4Fourv16b_POST ST4i8 ST4i8_POST ST4i16 ST4i16_POST ST4i32 ST4i32_POST ST4i64 ST4i64_POST
+}
+
+def AArch64MIR_st4h : AArch64MIR_TargetOp<"st4h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST4H ST4H_IMM
+}
+
+def AArch64MIR_st4q : AArch64MIR_TargetOp<"st4q", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST4Q ST4Q_IMM
+}
+
+def AArch64MIR_st4w : AArch64MIR_TargetOp<"st4w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST4W ST4W_IMM
+}
+
+def AArch64MIR_st64b : AArch64MIR_TargetOp<"st64b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST64B
+}
+
+def AArch64MIR_st64bv : AArch64MIR_TargetOp<"st64bv", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST64BV
+}
+
+def AArch64MIR_st64bv0 : AArch64MIR_TargetOp<"st64bv0", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ST64BV0
+}
+
+def AArch64MIR_stbfadd : AArch64MIR_TargetOp<"stbfadd", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFADD
+}
+
+def AArch64MIR_stbfaddl : AArch64MIR_TargetOp<"stbfaddl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFADDL
+}
+
+def AArch64MIR_stbfmax : AArch64MIR_TargetOp<"stbfmax", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFMAX
+}
+
+def AArch64MIR_stbfmaxl : AArch64MIR_TargetOp<"stbfmaxl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFMAXL
+}
+
+def AArch64MIR_stbfmaxnm : AArch64MIR_TargetOp<"stbfmaxnm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFMAXNM
+}
+
+def AArch64MIR_stbfmaxnml : AArch64MIR_TargetOp<"stbfmaxnml", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFMAXNML
+}
+
+def AArch64MIR_stbfmin : AArch64MIR_TargetOp<"stbfmin", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFMIN
+}
+
+def AArch64MIR_stbfminl : AArch64MIR_TargetOp<"stbfminl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFMINL
+}
+
+def AArch64MIR_stbfminnm : AArch64MIR_TargetOp<"stbfminnm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFMINNM
+}
+
+def AArch64MIR_stbfminnml : AArch64MIR_TargetOp<"stbfminnml", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STBFMINNML
+}
+
+def AArch64MIR_stfadd : AArch64MIR_TargetOp<"stfadd", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFADDD STFADDH STFADDS
+}
+
+def AArch64MIR_stfaddl : AArch64MIR_TargetOp<"stfaddl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFADDLD STFADDLH STFADDLS
+}
+
+def AArch64MIR_stfmax : AArch64MIR_TargetOp<"stfmax", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFMAXD STFMAXH STFMAXS
+}
+
+def AArch64MIR_stfmaxl : AArch64MIR_TargetOp<"stfmaxl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFMAXLD STFMAXLH STFMAXLS
+}
+
+def AArch64MIR_stfmaxnm : AArch64MIR_TargetOp<"stfmaxnm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFMAXNMD STFMAXNMH STFMAXNMS
+}
+
+def AArch64MIR_stfmaxnml : AArch64MIR_TargetOp<"stfmaxnml", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFMAXNMLD STFMAXNMLH STFMAXNMLS
+}
+
+def AArch64MIR_stfmin : AArch64MIR_TargetOp<"stfmin", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFMIND STFMINH STFMINS
+}
+
+def AArch64MIR_stfminl : AArch64MIR_TargetOp<"stfminl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFMINLD STFMINLH STFMINLS
+}
+
+def AArch64MIR_stfminnm : AArch64MIR_TargetOp<"stfminnm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFMINNMD STFMINNMH STFMINNMS
+}
+
+def AArch64MIR_stfminnml : AArch64MIR_TargetOp<"stfminnml", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STFMINNMLD STFMINNMLH STFMINNMLS
+}
+
+def AArch64MIR_stgm : AArch64MIR_TargetOp<"stgm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STGM
+}
+
+def AArch64MIR_stgp : AArch64MIR_TargetOp<"stgp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STGPi STGPpost STGPpre
+}
+
+def AArch64MIR_stg : AArch64MIR_TargetOp<"stg", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STGPostIndex STGPreIndex STGi
+}
+
+def AArch64MIR_stilp : AArch64MIR_TargetOp<"stilp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STILPW STILPWpre STILPX STILPXpre
+}
+
+def AArch64MIR_stl1 : AArch64MIR_TargetOp<"stl1", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STL1
+}
+
+def AArch64MIR_stllrb : AArch64MIR_TargetOp<"stllrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLLRB
+}
+
+def AArch64MIR_stllrh : AArch64MIR_TargetOp<"stllrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLLRH
+}
+
+def AArch64MIR_stllr : AArch64MIR_TargetOp<"stllr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLLRW STLLRX
+}
+
+def AArch64MIR_stlp : AArch64MIR_TargetOp<"stlp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLPi
+}
+
+def AArch64MIR_stlrb : AArch64MIR_TargetOp<"stlrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLRB
+}
+
+def AArch64MIR_stlrh : AArch64MIR_TargetOp<"stlrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLRH
+}
+
+def AArch64MIR_stlr : AArch64MIR_TargetOp<"stlr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLRW STLRWpre STLRX STLRXpre
+}
+
+def AArch64MIR_stltxr : AArch64MIR_TargetOp<"stltxr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLTXRW STLTXRX
+}
+
+def AArch64MIR_stlurb : AArch64MIR_TargetOp<"stlurb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLURBi
+}
+
+def AArch64MIR_stlurh : AArch64MIR_TargetOp<"stlurh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLURHi
+}
+
+def AArch64MIR_stlur : AArch64MIR_TargetOp<"stlur", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLURWi STLURXi STLURbi STLURdi STLURhi STLURqi STLURsi
+}
+
+def AArch64MIR_stlxp : AArch64MIR_TargetOp<"stlxp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLXPW STLXPX
+}
+
+def AArch64MIR_stlxrb : AArch64MIR_TargetOp<"stlxrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLXRB
+}
+
+def AArch64MIR_stlxrh : AArch64MIR_TargetOp<"stlxrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLXRH
+}
+
+def AArch64MIR_stlxr : AArch64MIR_TargetOp<"stlxr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STLXRW STLXRX
+}
+
+def AArch64MIR_stmopa : AArch64MIR_TargetOp<"stmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STMOPA_M2ZZZI_BtoS STMOPA_M2ZZZI_HtoS
+}
+
+def AArch64MIR_stnp : AArch64MIR_TargetOp<"stnp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STNPDi STNPQi STNPSi STNPWi STNPXi
+}
+
+def AArch64MIR_stnt1b : AArch64MIR_TargetOp<"stnt1b", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STNT1B_2Z STNT1B_2Z_IMM STNT1B_2Z_STRIDED STNT1B_2Z_STRIDED_IMM STNT1B_4Z STNT1B_4Z_IMM STNT1B_4Z_STRIDED STNT1B_4Z_STRIDED_IMM STNT1B_ZRI STNT1B_ZRR STNT1B_ZZR_D STNT1B_ZZR_S
+}
+
+def AArch64MIR_stnt1d : AArch64MIR_TargetOp<"stnt1d", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STNT1D_2Z STNT1D_2Z_IMM STNT1D_2Z_STRIDED STNT1D_2Z_STRIDED_IMM STNT1D_4Z STNT1D_4Z_IMM STNT1D_4Z_STRIDED STNT1D_4Z_STRIDED_IMM STNT1D_ZRI STNT1D_ZRR STNT1D_ZZR_D
+}
+
+def AArch64MIR_stnt1h : AArch64MIR_TargetOp<"stnt1h", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STNT1H_2Z STNT1H_2Z_IMM STNT1H_2Z_STRIDED STNT1H_2Z_STRIDED_IMM STNT1H_4Z STNT1H_4Z_IMM STNT1H_4Z_STRIDED STNT1H_4Z_STRIDED_IMM STNT1H_ZRI STNT1H_ZRR STNT1H_ZZR_D STNT1H_ZZR_S
+}
+
+def AArch64MIR_stnt1w : AArch64MIR_TargetOp<"stnt1w", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STNT1W_2Z STNT1W_2Z_IMM STNT1W_2Z_STRIDED STNT1W_2Z_STRIDED_IMM STNT1W_4Z STNT1W_4Z_IMM STNT1W_4Z_STRIDED STNT1W_4Z_STRIDED_IMM STNT1W_ZRI STNT1W_ZRR STNT1W_ZZR_D STNT1W_ZZR_S
+}
+
+def AArch64MIR_stp : AArch64MIR_TargetOp<"stp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STPDi STPDpost STPDpre STPQi STPQpost STPQpre STPSi STPSpost STPSpre STPWi STPWpost STPWpre STPXi STPXpost STPXpre
+}
+
+def AArch64MIR_strb : AArch64MIR_TargetOp<"strb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STRBBpost STRBBpre STRBBroW STRBBroX STRBBui
+}
+
+def AArch64MIR_str : AArch64MIR_TargetOp<"str", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STRBpost STRBpre STRBroW STRBroX STRBui STRDpost STRDpre STRDroW STRDroX STRDui STRHpost STRHpre STRHroW STRHroX STRHui STRQpost STRQpre STRQroW STRQroX STRQui STRSpost STRSpre STRSroW STRSroX STRSui STRWpost STRWpre STRWroW STRWroX STRWui STRXpost STRXpre STRXroW STRXroX STRXui STR_PXI STR_TX STR_ZA STR_ZXI
+}
+
+def AArch64MIR_strh : AArch64MIR_TargetOp<"strh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STRHHpost STRHHpre STRHHroW STRHHroX STRHHui
+}
+
+def AArch64MIR_sttnp : AArch64MIR_TargetOp<"sttnp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STTNPQi STTNPXi
+}
+
+def AArch64MIR_sttp : AArch64MIR_TargetOp<"sttp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STTPQi STTPQpost STTPQpre STTPi STTPpost STTPpre
+}
+
+def AArch64MIR_sttrb : AArch64MIR_TargetOp<"sttrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STTRBi
+}
+
+def AArch64MIR_sttrh : AArch64MIR_TargetOp<"sttrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STTRHi
+}
+
+def AArch64MIR_sttr : AArch64MIR_TargetOp<"sttr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STTRWi STTRXi
+}
+
+def AArch64MIR_sttxr : AArch64MIR_TargetOp<"sttxr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STTXRWr STTXRXr
+}
+
+def AArch64MIR_sturb : AArch64MIR_TargetOp<"sturb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STURBBi
+}
+
+def AArch64MIR_stur : AArch64MIR_TargetOp<"stur", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STURBi STURDi STURHi STURQi STURSi STURWi STURXi
+}
+
+def AArch64MIR_sturh : AArch64MIR_TargetOp<"sturh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STURHHi
+}
+
+def AArch64MIR_stxp : AArch64MIR_TargetOp<"stxp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STXPW STXPX
+}
+
+def AArch64MIR_stxrb : AArch64MIR_TargetOp<"stxrb", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STXRB
+}
+
+def AArch64MIR_stxrh : AArch64MIR_TargetOp<"stxrh", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STXRH
+}
+
+def AArch64MIR_stxr : AArch64MIR_TargetOp<"stxr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STXRW STXRX
+}
+
+def AArch64MIR_stz2g : AArch64MIR_TargetOp<"stz2g", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STZ2GPostIndex STZ2GPreIndex STZ2Gi
+}
+
+def AArch64MIR_stzgm : AArch64MIR_TargetOp<"stzgm", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STZGM
+}
+
+def AArch64MIR_stzg : AArch64MIR_TargetOp<"stzg", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: STZGPostIndex STZGPreIndex STZGi
+}
+
+def AArch64MIR_subg : AArch64MIR_TargetOp<"subg", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBG
+}
+
+def AArch64MIR_subhnb : AArch64MIR_TargetOp<"subhnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBHNB_ZZZ_B SUBHNB_ZZZ_H SUBHNB_ZZZ_S
+}
+
+def AArch64MIR_subhnt : AArch64MIR_TargetOp<"subhnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBHNT_ZZZ_B SUBHNT_ZZZ_H SUBHNT_ZZZ_S
+}
+
+def AArch64MIR_subhn : AArch64MIR_TargetOp<"subhn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBHNv2i64_v2i32 SUBHNv4i32_v4i16 SUBHNv8i16_v8i8
+}
+
+def AArch64MIR_subhn2 : AArch64MIR_TargetOp<"subhn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBHNv2i64_v4i32 SUBHNv4i32_v8i16 SUBHNv8i16_v16i8
+}
+
+def AArch64MIR_subp : AArch64MIR_TargetOp<"subp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBP SUBP_ZPmZZ_B SUBP_ZPmZZ_D SUBP_ZPmZZ_H SUBP_ZPmZZ_S
+}
+
+def AArch64MIR_subps : AArch64MIR_TargetOp<"subps", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBPS
+}
+
+def AArch64MIR_subpt : AArch64MIR_TargetOp<"subpt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBPT_shift SUB_ZPmZ_CPA SUB_ZZZ_CPA
+}
+
+def AArch64MIR_subr : AArch64MIR_TargetOp<"subr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBR_ZI_B SUBR_ZI_D SUBR_ZI_H SUBR_ZI_S SUBR_ZPmZ_B SUBR_ZPmZ_D SUBR_ZPmZ_H SUBR_ZPmZ_S
+}
+
+def AArch64MIR_subs : AArch64MIR_TargetOp<"subs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBSWri SUBSWrs SUBSWrx SUBSXri SUBSXrs SUBSXrx SUBSXrx64
+}
+
+def AArch64MIR_sub : AArch64MIR_TargetOp<"sub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUBWri SUBWrs SUBWrx SUBXri SUBXrs SUBXrx SUBXrx64 SUB_VG2_M2Z2Z_D SUB_VG2_M2Z2Z_S SUB_VG2_M2ZZ_D SUB_VG2_M2ZZ_S SUB_VG2_M2Z_D SUB_VG2_M2Z_S SUB_VG4_M4Z4Z_D SUB_VG4_M4Z4Z_S SUB_VG4_M4ZZ_D SUB_VG4_M4ZZ_S SUB_VG4_M4Z_D SUB_VG4_M4Z_S SUB_ZI_B SUB_ZI_D SUB_ZI_H SUB_ZI_S SUB_ZPmZ_B SUB_ZPmZ_D SUB_ZPmZ_H SUB_ZPmZ_S SUB_ZZZ_B SUB_ZZZ_D SUB_ZZZ_H SUB_ZZZ_S SUBv1i64 SUBv2i32 SUBv2i64 SUBv4i16 SUBv4i32 SUBv8i8 SUBv8i16 SUBv16i8
+}
+
+def AArch64MIR_sudot : AArch64MIR_TargetOp<"sudot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUDOT_VG2_M2ZZI_BToS SUDOT_VG2_M2ZZ_BToS SUDOT_VG4_M4ZZI_BToS SUDOT_VG4_M4ZZ_BToS SUDOT_ZZZI SUDOTlanev8i8 SUDOTlanev16i8
+}
+
+def AArch64MIR_sumlall : AArch64MIR_TargetOp<"sumlall", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUMLALL_MZZI_BtoS SUMLALL_VG2_M2ZZI_BtoS SUMLALL_VG2_M2ZZ_BtoS SUMLALL_VG4_M4ZZI_BtoS SUMLALL_VG4_M4ZZ_BtoS
+}
+
+def AArch64MIR_sumop4a : AArch64MIR_TargetOp<"sumop4a", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUMOP4A_M2Z2Z_BToS SUMOP4A_M2Z2Z_HtoD SUMOP4A_M2ZZ_BToS SUMOP4A_M2ZZ_HtoD SUMOP4A_MZ2Z_BToS SUMOP4A_MZ2Z_HtoD SUMOP4A_MZZ_BToS SUMOP4A_MZZ_HtoD
+}
+
+def AArch64MIR_sumop4s : AArch64MIR_TargetOp<"sumop4s", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUMOP4S_M2Z2Z_BToS SUMOP4S_M2Z2Z_HtoD SUMOP4S_M2ZZ_BToS SUMOP4S_M2ZZ_HtoD SUMOP4S_MZ2Z_BToS SUMOP4S_MZ2Z_HtoD SUMOP4S_MZZ_BToS SUMOP4S_MZZ_HtoD
+}
+
+def AArch64MIR_sumopa : AArch64MIR_TargetOp<"sumopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUMOPA_MPPZZ_D SUMOPA_MPPZZ_S
+}
+
+def AArch64MIR_sumops : AArch64MIR_TargetOp<"sumops", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUMOPS_MPPZZ_D SUMOPS_MPPZZ_S
+}
+
+def AArch64MIR_sunpkhi : AArch64MIR_TargetOp<"sunpkhi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUNPKHI_ZZ_D SUNPKHI_ZZ_H SUNPKHI_ZZ_S
+}
+
+def AArch64MIR_sunpklo : AArch64MIR_TargetOp<"sunpklo", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUNPKLO_ZZ_D SUNPKLO_ZZ_H SUNPKLO_ZZ_S
+}
+
+def AArch64MIR_sunpk : AArch64MIR_TargetOp<"sunpk", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUNPK_VG2_2ZZ_D SUNPK_VG2_2ZZ_H SUNPK_VG2_2ZZ_S SUNPK_VG4_4Z2Z_D SUNPK_VG4_4Z2Z_H SUNPK_VG4_4Z2Z_S
+}
+
+def AArch64MIR_suqadd : AArch64MIR_TargetOp<"suqadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUQADD_ZPmZ_B SUQADD_ZPmZ_D SUQADD_ZPmZ_H SUQADD_ZPmZ_S SUQADDv1i8 SUQADDv1i16 SUQADDv1i32 SUQADDv1i64 SUQADDv2i32 SUQADDv2i64 SUQADDv4i16 SUQADDv4i32 SUQADDv8i8 SUQADDv8i16 SUQADDv16i8
+}
+
+def AArch64MIR_sutmopa : AArch64MIR_TargetOp<"sutmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUTMOPA_M2ZZZI_BtoS
+}
+
+def AArch64MIR_suvdot : AArch64MIR_TargetOp<"suvdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SUVDOT_VG4_M4ZZI_BToS
+}
+
+def AArch64MIR_svc : AArch64MIR_TargetOp<"svc", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SVC
+}
+
+def AArch64MIR_svdot : AArch64MIR_TargetOp<"svdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SVDOT_VG2_M2ZZI_HtoS SVDOT_VG4_M4ZZI_BtoS SVDOT_VG4_M4ZZI_HtoD
+}
+
+def AArch64MIR_swpab : AArch64MIR_TargetOp<"swpab", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPAB
+}
+
+def AArch64MIR_swpah : AArch64MIR_TargetOp<"swpah", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPAH
+}
+
+def AArch64MIR_swpalb : AArch64MIR_TargetOp<"swpalb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPALB
+}
+
+def AArch64MIR_swpalh : AArch64MIR_TargetOp<"swpalh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPALH
+}
+
+def AArch64MIR_swpal : AArch64MIR_TargetOp<"swpal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPALW SWPALX
+}
+
+def AArch64MIR_swpa : AArch64MIR_TargetOp<"swpa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPAW SWPAX
+}
+
+def AArch64MIR_swpb : AArch64MIR_TargetOp<"swpb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPB
+}
+
+def AArch64MIR_swph : AArch64MIR_TargetOp<"swph", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPH
+}
+
+def AArch64MIR_swplb : AArch64MIR_TargetOp<"swplb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPLB
+}
+
+def AArch64MIR_swplh : AArch64MIR_TargetOp<"swplh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPLH
+}
+
+def AArch64MIR_swpl : AArch64MIR_TargetOp<"swpl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPLW SWPLX
+}
+
+def AArch64MIR_swpp : AArch64MIR_TargetOp<"swpp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPP
+}
+
+def AArch64MIR_swppa : AArch64MIR_TargetOp<"swppa", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPPA
+}
+
+def AArch64MIR_swppal : AArch64MIR_TargetOp<"swppal", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPPAL
+}
+
+def AArch64MIR_swppl : AArch64MIR_TargetOp<"swppl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPPL
+}
+
+def AArch64MIR_swptal : AArch64MIR_TargetOp<"swptal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPTALW SWPTALX
+}
+
+def AArch64MIR_swpta : AArch64MIR_TargetOp<"swpta", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPTAW SWPTAX
+}
+
+def AArch64MIR_swptl : AArch64MIR_TargetOp<"swptl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPTLW SWPTLX
+}
+
+def AArch64MIR_swpt : AArch64MIR_TargetOp<"swpt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPTW SWPTX
+}
+
+def AArch64MIR_swp : AArch64MIR_TargetOp<"swp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SWPW SWPX
+}
+
+def AArch64MIR_sxtb : AArch64MIR_TargetOp<"sxtb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SXTB_ZPmZ_D SXTB_ZPmZ_H SXTB_ZPmZ_S SXTB_ZPzZ_D SXTB_ZPzZ_H SXTB_ZPzZ_S
+}
+
+def AArch64MIR_sxth : AArch64MIR_TargetOp<"sxth", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SXTH_ZPmZ_D SXTH_ZPmZ_S SXTH_ZPzZ_D SXTH_ZPzZ_S
+}
+
+def AArch64MIR_sxtw : AArch64MIR_TargetOp<"sxtw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SXTW_ZPmZ_D SXTW_ZPzZ_D
+}
+
+def AArch64MIR_sysl : AArch64MIR_TargetOp<"sysl", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SYSLxt
+}
+
+def AArch64MIR_sysp : AArch64MIR_TargetOp<"sysp", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SYSPxt SYSPxt_XZR
+}
+
+def AArch64MIR_sys : AArch64MIR_TargetOp<"sys", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: SYSxt
+}
+
+def AArch64MIR_tblq : AArch64MIR_TargetOp<"tblq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TBLQ_ZZZ_B TBLQ_ZZZ_D TBLQ_ZZZ_H TBLQ_ZZZ_S
+}
+
+def AArch64MIR_tbl : AArch64MIR_TargetOp<"tbl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TBL_ZZZZ_B TBL_ZZZZ_D TBL_ZZZZ_H TBL_ZZZZ_S TBL_ZZZ_B TBL_ZZZ_D TBL_ZZZ_H TBL_ZZZ_S TBLv8i8Four TBLv8i8One TBLv8i8Three TBLv8i8Two TBLv16i8Four TBLv16i8One TBLv16i8Three TBLv16i8Two
+}
+
+def AArch64MIR_tbnz : AArch64MIR_TargetOp<"tbnz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TBNZW TBNZX
+}
+
+def AArch64MIR_tbxq : AArch64MIR_TargetOp<"tbxq", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TBXQ_ZZZ_B TBXQ_ZZZ_D TBXQ_ZZZ_H TBXQ_ZZZ_S
+}
+
+def AArch64MIR_tbx : AArch64MIR_TargetOp<"tbx", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TBX_ZZZ_B TBX_ZZZ_D TBX_ZZZ_H TBX_ZZZ_S TBXv8i8Four TBXv8i8One TBXv8i8Three TBXv8i8Two TBXv16i8Four TBXv16i8One TBXv16i8Three TBXv16i8Two
+}
+
+def AArch64MIR_tbz : AArch64MIR_TargetOp<"tbz", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TBZW TBZX
+}
+
+def AArch64MIR_tchangeb : AArch64MIR_TargetOp<"tchangeb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TCHANGEBri TCHANGEBrr
+}
+
+def AArch64MIR_tchangef : AArch64MIR_TargetOp<"tchangef", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TCHANGEFri TCHANGEFrr
+}
+
+def AArch64MIR_tenter : AArch64MIR_TargetOp<"tenter", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TENTER
+}
+
+def AArch64MIR_texit : AArch64MIR_TargetOp<"texit", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TEXIT
+}
+
+def AArch64MIR_trn1 : AArch64MIR_TargetOp<"trn1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TRN1_PPP_B TRN1_PPP_D TRN1_PPP_H TRN1_PPP_S TRN1_ZZZ_B TRN1_ZZZ_D TRN1_ZZZ_H TRN1_ZZZ_Q TRN1_ZZZ_S TRN1v2i32 TRN1v2i64 TRN1v4i16 TRN1v4i32 TRN1v8i8 TRN1v8i16 TRN1v16i8
+}
+
+def AArch64MIR_trn2 : AArch64MIR_TargetOp<"trn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: TRN2_PPP_B TRN2_PPP_D TRN2_PPP_H TRN2_PPP_S TRN2_ZZZ_B TRN2_ZZZ_D TRN2_ZZZ_H TRN2_ZZZ_Q TRN2_ZZZ_S TRN2v2i32 TRN2v2i64 TRN2v4i16 TRN2v4i32 TRN2v8i8 TRN2v8i16 TRN2v16i8
+}
+
+def AArch64MIR_uabalb : AArch64MIR_TargetOp<"uabalb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABALB_ZZZ_D UABALB_ZZZ_H UABALB_ZZZ_S
+}
+
+def AArch64MIR_uabalt : AArch64MIR_TargetOp<"uabalt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABALT_ZZZ_D UABALT_ZZZ_H UABALT_ZZZ_S
+}
+
+def AArch64MIR_uabal : AArch64MIR_TargetOp<"uabal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABAL_ZZZ_BtoH UABAL_ZZZ_HtoS UABAL_ZZZ_StoD UABALv2i32_v2i64 UABALv4i16_v4i32 UABALv8i8_v8i16
+}
+
+def AArch64MIR_uabal2 : AArch64MIR_TargetOp<"uabal2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABALv4i32_v2i64 UABALv8i16_v4i32 UABALv16i8_v8i16
+}
+
+def AArch64MIR_uaba : AArch64MIR_TargetOp<"uaba", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABA_ZZZ_B UABA_ZZZ_D UABA_ZZZ_H UABA_ZZZ_S UABAv2i32 UABAv4i16 UABAv4i32 UABAv8i8 UABAv8i16 UABAv16i8
+}
+
+def AArch64MIR_uabdlb : AArch64MIR_TargetOp<"uabdlb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABDLB_ZZZ_D UABDLB_ZZZ_H UABDLB_ZZZ_S
+}
+
+def AArch64MIR_uabdlt : AArch64MIR_TargetOp<"uabdlt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABDLT_ZZZ_D UABDLT_ZZZ_H UABDLT_ZZZ_S
+}
+
+def AArch64MIR_uabdl : AArch64MIR_TargetOp<"uabdl", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABDLv2i32_v2i64 UABDLv4i16_v4i32 UABDLv8i8_v8i16
+}
+
+def AArch64MIR_uabdl2 : AArch64MIR_TargetOp<"uabdl2", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABDLv4i32_v2i64 UABDLv8i16_v4i32 UABDLv16i8_v8i16
+}
+
+def AArch64MIR_uabd : AArch64MIR_TargetOp<"uabd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UABD_ZPmZ_B UABD_ZPmZ_D UABD_ZPmZ_H UABD_ZPmZ_S UABDv2i32 UABDv4i16 UABDv4i32 UABDv8i8 UABDv8i16 UABDv16i8
+}
+
+def AArch64MIR_uadalp : AArch64MIR_TargetOp<"uadalp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADALP_ZPmZ_D UADALP_ZPmZ_H UADALP_ZPmZ_S UADALPv2i32_v1i64 UADALPv4i16_v2i32 UADALPv4i32_v2i64 UADALPv8i8_v4i16 UADALPv8i16_v4i32 UADALPv16i8_v8i16
+}
+
+def AArch64MIR_uaddlb : AArch64MIR_TargetOp<"uaddlb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDLB_ZZZ_D UADDLB_ZZZ_H UADDLB_ZZZ_S
+}
+
+def AArch64MIR_uaddlp : AArch64MIR_TargetOp<"uaddlp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDLPv2i32_v1i64 UADDLPv4i16_v2i32 UADDLPv4i32_v2i64 UADDLPv8i8_v4i16 UADDLPv8i16_v4i32 UADDLPv16i8_v8i16
+}
+
+def AArch64MIR_uaddlt : AArch64MIR_TargetOp<"uaddlt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDLT_ZZZ_D UADDLT_ZZZ_H UADDLT_ZZZ_S
+}
+
+def AArch64MIR_uaddlv : AArch64MIR_TargetOp<"uaddlv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDLVv4i16v UADDLVv4i32v UADDLVv8i8v UADDLVv8i16v UADDLVv16i8v
+}
+
+def AArch64MIR_uaddl : AArch64MIR_TargetOp<"uaddl", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDLv2i32_v2i64 UADDLv4i16_v4i32 UADDLv8i8_v8i16
+}
+
+def AArch64MIR_uaddl2 : AArch64MIR_TargetOp<"uaddl2", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDLv4i32_v2i64 UADDLv8i16_v4i32 UADDLv16i8_v8i16
+}
+
+def AArch64MIR_uaddv : AArch64MIR_TargetOp<"uaddv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDV_VPZ_B UADDV_VPZ_D UADDV_VPZ_H UADDV_VPZ_S
+}
+
+def AArch64MIR_uaddwb : AArch64MIR_TargetOp<"uaddwb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDWB_ZZZ_D UADDWB_ZZZ_H UADDWB_ZZZ_S
+}
+
+def AArch64MIR_uaddwt : AArch64MIR_TargetOp<"uaddwt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDWT_ZZZ_D UADDWT_ZZZ_H UADDWT_ZZZ_S
+}
+
+def AArch64MIR_uaddw : AArch64MIR_TargetOp<"uaddw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDWv2i32_v2i64 UADDWv4i16_v4i32 UADDWv8i8_v8i16
+}
+
+def AArch64MIR_uaddw2 : AArch64MIR_TargetOp<"uaddw2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UADDWv4i32_v2i64 UADDWv8i16_v4i32 UADDWv16i8_v8i16
+}
+
+def AArch64MIR_ubfm : AArch64MIR_TargetOp<"ubfm", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UBFMWri UBFMXri
+}
+
+def AArch64MIR_uclamp : AArch64MIR_TargetOp<"uclamp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UCLAMP_VG2_2Z2Z_B UCLAMP_VG2_2Z2Z_D UCLAMP_VG2_2Z2Z_H UCLAMP_VG2_2Z2Z_S UCLAMP_VG4_4Z4Z_B UCLAMP_VG4_4Z4Z_D UCLAMP_VG4_4Z4Z_H UCLAMP_VG4_4Z4Z_S UCLAMP_ZZZ_B UCLAMP_ZZZ_D UCLAMP_ZZZ_H UCLAMP_ZZZ_S
+}
+
+def AArch64MIR_ucvtf : AArch64MIR_TargetOp<"ucvtf", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UCVTFDSr UCVTFHDr UCVTFHSr UCVTFSDr UCVTFSWDri UCVTFSWHri UCVTFSWSri UCVTFSXDri UCVTFSXHri UCVTFSXSri UCVTFUWDri UCVTFUWHri UCVTFUWSri UCVTFUXDri UCVTFUXHri UCVTFUXSri UCVTF_2Z2Z_StoS UCVTF_4Z4Z_StoS UCVTF_ZPmZ_DtoD UCVTF_ZPmZ_DtoH UCVTF_ZPmZ_DtoS UCVTF_ZPmZ_HtoH UCVTF_ZPmZ_StoD UCVTF_ZPmZ_StoH UCVTF_ZPmZ_StoS UCVTF_ZPzZ_DtoD UCVTF_ZPzZ_DtoH UCVTF_ZPzZ_DtoS UCVTF_ZPzZ_HtoH UCVTF_ZPzZ_StoD UCVTF_ZPzZ_StoH UCVTF_ZPzZ_StoS UCVTF_ZZ_BtoH UCVTF_ZZ_HtoS UCVTF_ZZ_StoD UCVTFd UCVTFh UCVTFs UCVTFv1i16 UCVTFv1i32 UCVTFv1i64 UCVTFv2f32 UCVTFv2f64 UCVTFv2i32_shift UCVTFv2i64_shift UCVTFv4f16 UCVTFv4f32 UCVTFv4i16_shift UCVTFv4i32_shift UCVTFv8f16 UCVTFv8i16_shift
+}
+
+def AArch64MIR_ucvtflt : AArch64MIR_TargetOp<"ucvtflt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UCVTFLT_ZZ_BtoH UCVTFLT_ZZ_HtoS UCVTFLT_ZZ_StoD
+}
+
+def AArch64MIR_udf : AArch64MIR_TargetOp<"udf", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UDF
+}
+
+def AArch64MIR_udivr : AArch64MIR_TargetOp<"udivr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UDIVR_ZPmZ_D UDIVR_ZPmZ_S
+}
+
+def AArch64MIR_udiv : AArch64MIR_TargetOp<"udiv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UDIVWr UDIVXr UDIV_ZPmZ_D UDIV_ZPmZ_S
+}
+
+def AArch64MIR_udot : AArch64MIR_TargetOp<"udot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UDOT_VG2_M2Z2Z_BtoS UDOT_VG2_M2Z2Z_HtoD UDOT_VG2_M2Z2Z_HtoS UDOT_VG2_M2ZZI_BToS UDOT_VG2_M2ZZI_HToS UDOT_VG2_M2ZZI_HtoD UDOT_VG2_M2ZZ_BtoS UDOT_VG2_M2ZZ_HtoD UDOT_VG2_M2ZZ_HtoS UDOT_VG4_M4Z4Z_BtoS UDOT_VG4_M4Z4Z_HtoD UDOT_VG4_M4Z4Z_HtoS UDOT_VG4_M4ZZI_BtoS UDOT_VG4_M4ZZI_HToS UDOT_VG4_M4ZZI_HtoD UDOT_VG4_M4ZZ_BtoS UDOT_VG4_M4ZZ_HtoD UDOT_VG4_M4ZZ_HtoS UDOT_ZZZI_BtoH UDOT_ZZZI_BtoS UDOT_ZZZI_HtoD UDOT_ZZZI_HtoS UDOT_ZZZ_BtoH UDOT_ZZZ_BtoS UDOT_ZZZ_HtoD UDOT_ZZZ_HtoS UDOTlanev8i8 UDOTlanev16i8 UDOTv8i8 UDOTv16i8
+}
+
+def AArch64MIR_uhadd : AArch64MIR_TargetOp<"uhadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UHADD_ZPmZ_B UHADD_ZPmZ_D UHADD_ZPmZ_H UHADD_ZPmZ_S UHADDv2i32 UHADDv4i16 UHADDv4i32 UHADDv8i8 UHADDv8i16 UHADDv16i8
+}
+
+def AArch64MIR_uhsubr : AArch64MIR_TargetOp<"uhsubr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UHSUBR_ZPmZ_B UHSUBR_ZPmZ_D UHSUBR_ZPmZ_H UHSUBR_ZPmZ_S
+}
+
+def AArch64MIR_uhsub : AArch64MIR_TargetOp<"uhsub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UHSUB_ZPmZ_B UHSUB_ZPmZ_D UHSUB_ZPmZ_H UHSUB_ZPmZ_S UHSUBv2i32 UHSUBv4i16 UHSUBv4i32 UHSUBv8i8 UHSUBv8i16 UHSUBv16i8
+}
+
+def AArch64MIR_umaddl : AArch64MIR_TargetOp<"umaddl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMADDLrrr
+}
+
+def AArch64MIR_umaxp : AArch64MIR_TargetOp<"umaxp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMAXP_ZPmZ_B UMAXP_ZPmZ_D UMAXP_ZPmZ_H UMAXP_ZPmZ_S UMAXPv2i32 UMAXPv4i16 UMAXPv4i32 UMAXPv8i8 UMAXPv8i16 UMAXPv16i8
+}
+
+def AArch64MIR_umaxqv : AArch64MIR_TargetOp<"umaxqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMAXQV_VPZ_B UMAXQV_VPZ_D UMAXQV_VPZ_H UMAXQV_VPZ_S
+}
+
+def AArch64MIR_umaxv : AArch64MIR_TargetOp<"umaxv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMAXV_VPZ_B UMAXV_VPZ_D UMAXV_VPZ_H UMAXV_VPZ_S UMAXVv4i16v UMAXVv4i32v UMAXVv8i8v UMAXVv8i16v UMAXVv16i8v
+}
+
+def AArch64MIR_umax : AArch64MIR_TargetOp<"umax", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMAXWri UMAXWrr UMAXXri UMAXXrr UMAX_VG2_2Z2Z_B UMAX_VG2_2Z2Z_D UMAX_VG2_2Z2Z_H UMAX_VG2_2Z2Z_S UMAX_VG2_2ZZ_B UMAX_VG2_2ZZ_D UMAX_VG2_2ZZ_H UMAX_VG2_2ZZ_S UMAX_VG4_4Z4Z_B UMAX_VG4_4Z4Z_D UMAX_VG4_4Z4Z_H UMAX_VG4_4Z4Z_S UMAX_VG4_4ZZ_B UMAX_VG4_4ZZ_D UMAX_VG4_4ZZ_H UMAX_VG4_4ZZ_S UMAX_ZI_B UMAX_ZI_D UMAX_ZI_H UMAX_ZI_S UMAX_ZPmZ_B UMAX_ZPmZ_D UMAX_ZPmZ_H UMAX_ZPmZ_S UMAXv2i32 UMAXv4i16 UMAXv4i32 UMAXv8i8 UMAXv8i16 UMAXv16i8
+}
+
+def AArch64MIR_uminp : AArch64MIR_TargetOp<"uminp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMINP_ZPmZ_B UMINP_ZPmZ_D UMINP_ZPmZ_H UMINP_ZPmZ_S UMINPv2i32 UMINPv4i16 UMINPv4i32 UMINPv8i8 UMINPv8i16 UMINPv16i8
+}
+
+def AArch64MIR_uminqv : AArch64MIR_TargetOp<"uminqv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMINQV_VPZ_B UMINQV_VPZ_D UMINQV_VPZ_H UMINQV_VPZ_S
+}
+
+def AArch64MIR_uminv : AArch64MIR_TargetOp<"uminv", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMINV_VPZ_B UMINV_VPZ_D UMINV_VPZ_H UMINV_VPZ_S UMINVv4i16v UMINVv4i32v UMINVv8i8v UMINVv8i16v UMINVv16i8v
+}
+
+def AArch64MIR_umin : AArch64MIR_TargetOp<"umin", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMINWri UMINWrr UMINXri UMINXrr UMIN_VG2_2Z2Z_B UMIN_VG2_2Z2Z_D UMIN_VG2_2Z2Z_H UMIN_VG2_2Z2Z_S UMIN_VG2_2ZZ_B UMIN_VG2_2ZZ_D UMIN_VG2_2ZZ_H UMIN_VG2_2ZZ_S UMIN_VG4_4Z4Z_B UMIN_VG4_4Z4Z_D UMIN_VG4_4Z4Z_H UMIN_VG4_4Z4Z_S UMIN_VG4_4ZZ_B UMIN_VG4_4ZZ_D UMIN_VG4_4ZZ_H UMIN_VG4_4ZZ_S UMIN_ZI_B UMIN_ZI_D UMIN_ZI_H UMIN_ZI_S UMIN_ZPmZ_B UMIN_ZPmZ_D UMIN_ZPmZ_H UMIN_ZPmZ_S UMINv2i32 UMINv4i16 UMINv4i32 UMINv8i8 UMINv8i16 UMINv16i8
+}
+
+def AArch64MIR_umlalb : AArch64MIR_TargetOp<"umlalb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLALB_ZZZI_D UMLALB_ZZZI_S UMLALB_ZZZ_D UMLALB_ZZZ_H UMLALB_ZZZ_S
+}
+
+def AArch64MIR_umlall : AArch64MIR_TargetOp<"umlall", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLALL_MZZI_BtoS UMLALL_MZZI_HtoD UMLALL_MZZ_BtoS UMLALL_MZZ_HtoD UMLALL_VG2_M2Z2Z_BtoS UMLALL_VG2_M2Z2Z_HtoD UMLALL_VG2_M2ZZI_BtoS UMLALL_VG2_M2ZZI_HtoD UMLALL_VG2_M2ZZ_BtoS UMLALL_VG2_M2ZZ_HtoD UMLALL_VG4_M4Z4Z_BtoS UMLALL_VG4_M4Z4Z_HtoD UMLALL_VG4_M4ZZI_BtoS UMLALL_VG4_M4ZZI_HtoD UMLALL_VG4_M4ZZ_BtoS UMLALL_VG4_M4ZZ_HtoD
+}
+
+def AArch64MIR_umlalt : AArch64MIR_TargetOp<"umlalt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLALT_ZZZI_D UMLALT_ZZZI_S UMLALT_ZZZ_D UMLALT_ZZZ_H UMLALT_ZZZ_S
+}
+
+def AArch64MIR_umlal : AArch64MIR_TargetOp<"umlal", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLAL_MZZI_HtoS UMLAL_MZZ_HtoS UMLAL_VG2_M2Z2Z_HtoS UMLAL_VG2_M2ZZI_S UMLAL_VG2_M2ZZ_HtoS UMLAL_VG4_M4Z4Z_HtoS UMLAL_VG4_M4ZZI_HtoS UMLAL_VG4_M4ZZ_HtoS UMLALv2i32_indexed UMLALv2i32_v2i64 UMLALv4i16_indexed UMLALv4i16_v4i32 UMLALv8i8_v8i16
+}
+
+def AArch64MIR_umlal2 : AArch64MIR_TargetOp<"umlal2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLALv4i32_indexed UMLALv4i32_v2i64 UMLALv8i16_indexed UMLALv8i16_v4i32 UMLALv16i8_v8i16
+}
+
+def AArch64MIR_umlslb : AArch64MIR_TargetOp<"umlslb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLSLB_ZZZI_D UMLSLB_ZZZI_S UMLSLB_ZZZ_D UMLSLB_ZZZ_H UMLSLB_ZZZ_S
+}
+
+def AArch64MIR_umlsll : AArch64MIR_TargetOp<"umlsll", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLSLL_MZZI_BtoS UMLSLL_MZZI_HtoD UMLSLL_MZZ_BtoS UMLSLL_MZZ_HtoD UMLSLL_VG2_M2Z2Z_BtoS UMLSLL_VG2_M2Z2Z_HtoD UMLSLL_VG2_M2ZZI_BtoS UMLSLL_VG2_M2ZZI_HtoD UMLSLL_VG2_M2ZZ_BtoS UMLSLL_VG2_M2ZZ_HtoD UMLSLL_VG4_M4Z4Z_BtoS UMLSLL_VG4_M4Z4Z_HtoD UMLSLL_VG4_M4ZZI_BtoS UMLSLL_VG4_M4ZZI_HtoD UMLSLL_VG4_M4ZZ_BtoS UMLSLL_VG4_M4ZZ_HtoD
+}
+
+def AArch64MIR_umlslt : AArch64MIR_TargetOp<"umlslt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLSLT_ZZZI_D UMLSLT_ZZZI_S UMLSLT_ZZZ_D UMLSLT_ZZZ_H UMLSLT_ZZZ_S
+}
+
+def AArch64MIR_umlsl : AArch64MIR_TargetOp<"umlsl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLSL_MZZI_HtoS UMLSL_MZZ_HtoS UMLSL_VG2_M2Z2Z_HtoS UMLSL_VG2_M2ZZI_S UMLSL_VG2_M2ZZ_HtoS UMLSL_VG4_M4Z4Z_HtoS UMLSL_VG4_M4ZZI_HtoS UMLSL_VG4_M4ZZ_HtoS UMLSLv2i32_indexed UMLSLv2i32_v2i64 UMLSLv4i16_indexed UMLSLv4i16_v4i32 UMLSLv8i8_v8i16
+}
+
+def AArch64MIR_umlsl2 : AArch64MIR_TargetOp<"umlsl2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMLSLv4i32_indexed UMLSLv4i32_v2i64 UMLSLv8i16_indexed UMLSLv8i16_v4i32 UMLSLv16i8_v8i16
+}
+
+def AArch64MIR_ummla : AArch64MIR_TargetOp<"ummla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMMLA UMMLA_ZZZ
+}
+
+def AArch64MIR_umop4a : AArch64MIR_TargetOp<"umop4a", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMOP4A_M2Z2Z_BToS UMOP4A_M2Z2Z_HToS UMOP4A_M2Z2Z_HtoD UMOP4A_M2ZZ_BToS UMOP4A_M2ZZ_HToS UMOP4A_M2ZZ_HtoD UMOP4A_MZ2Z_BToS UMOP4A_MZ2Z_HToS UMOP4A_MZ2Z_HtoD UMOP4A_MZZ_BToS UMOP4A_MZZ_HToS UMOP4A_MZZ_HtoD
+}
+
+def AArch64MIR_umop4s : AArch64MIR_TargetOp<"umop4s", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMOP4S_M2Z2Z_BToS UMOP4S_M2Z2Z_HToS UMOP4S_M2Z2Z_HtoD UMOP4S_M2ZZ_BToS UMOP4S_M2ZZ_HToS UMOP4S_M2ZZ_HtoD UMOP4S_MZ2Z_BToS UMOP4S_MZ2Z_HToS UMOP4S_MZ2Z_HtoD UMOP4S_MZZ_BToS UMOP4S_MZZ_HToS UMOP4S_MZZ_HtoD
+}
+
+def AArch64MIR_umopa : AArch64MIR_TargetOp<"umopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMOPA_MPPZZ_D UMOPA_MPPZZ_HtoS UMOPA_MPPZZ_S
+}
+
+def AArch64MIR_umops : AArch64MIR_TargetOp<"umops", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMOPS_MPPZZ_D UMOPS_MPPZZ_HtoS UMOPS_MPPZZ_S
+}
+
+def AArch64MIR_umov : AArch64MIR_TargetOp<"umov", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMOVvi8 UMOVvi8_idx0 UMOVvi16 UMOVvi16_idx0 UMOVvi32 UMOVvi32_idx0 UMOVvi64 UMOVvi64_idx0
+}
+
+def AArch64MIR_umsubl : AArch64MIR_TargetOp<"umsubl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMSUBLrrr
+}
+
+def AArch64MIR_umulh : AArch64MIR_TargetOp<"umulh", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMULH_ZPmZ_B UMULH_ZPmZ_D UMULH_ZPmZ_H UMULH_ZPmZ_S UMULH_ZZZ_B UMULH_ZZZ_D UMULH_ZZZ_H UMULH_ZZZ_S UMULHrr
+}
+
+def AArch64MIR_umullb : AArch64MIR_TargetOp<"umullb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMULLB_ZZZI_D UMULLB_ZZZI_S UMULLB_ZZZ_D UMULLB_ZZZ_H UMULLB_ZZZ_S
+}
+
+def AArch64MIR_umullt : AArch64MIR_TargetOp<"umullt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMULLT_ZZZI_D UMULLT_ZZZI_S UMULLT_ZZZ_D UMULLT_ZZZ_H UMULLT_ZZZ_S
+}
+
+def AArch64MIR_umull : AArch64MIR_TargetOp<"umull", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMULLv2i32_indexed UMULLv2i32_v2i64 UMULLv4i16_indexed UMULLv4i16_v4i32 UMULLv8i8_v8i16
+}
+
+def AArch64MIR_umull2 : AArch64MIR_TargetOp<"umull2", [Pure, Commutative]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UMULLv4i32_indexed UMULLv4i32_v2i64 UMULLv8i16_indexed UMULLv8i16_v4i32 UMULLv16i8_v8i16
+}
+
+def AArch64MIR_uqadd : AArch64MIR_TargetOp<"uqadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQADD_ZI_B UQADD_ZI_D UQADD_ZI_H UQADD_ZI_S UQADD_ZPmZ_B UQADD_ZPmZ_D UQADD_ZPmZ_H UQADD_ZPmZ_S UQADD_ZZZ_B UQADD_ZZZ_D UQADD_ZZZ_H UQADD_ZZZ_S UQADDv1i8 UQADDv1i16 UQADDv1i32 UQADDv1i64 UQADDv2i32 UQADDv2i64 UQADDv4i16 UQADDv4i32 UQADDv8i8 UQADDv8i16 UQADDv16i8
+}
+
+def AArch64MIR_uqcvtn : AArch64MIR_TargetOp<"uqcvtn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQCVTN_Z2Z_StoH UQCVTN_Z4Z_DtoH UQCVTN_Z4Z_StoB
+}
+
+def AArch64MIR_uqcvt : AArch64MIR_TargetOp<"uqcvt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQCVT_Z2Z_StoH UQCVT_Z4Z_DtoH UQCVT_Z4Z_StoB
+}
+
+def AArch64MIR_uqdecb : AArch64MIR_TargetOp<"uqdecb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQDECB_WPiI UQDECB_XPiI
+}
+
+def AArch64MIR_uqdecd : AArch64MIR_TargetOp<"uqdecd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQDECD_WPiI UQDECD_XPiI UQDECD_ZPiI
+}
+
+def AArch64MIR_uqdech : AArch64MIR_TargetOp<"uqdech", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQDECH_WPiI UQDECH_XPiI UQDECH_ZPiI
+}
+
+def AArch64MIR_uqdecp : AArch64MIR_TargetOp<"uqdecp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQDECP_WP_B UQDECP_WP_D UQDECP_WP_H UQDECP_WP_S UQDECP_XP_B UQDECP_XP_D UQDECP_XP_H UQDECP_XP_S UQDECP_ZP_D UQDECP_ZP_H UQDECP_ZP_S
+}
+
+def AArch64MIR_uqdecw : AArch64MIR_TargetOp<"uqdecw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQDECW_WPiI UQDECW_XPiI UQDECW_ZPiI
+}
+
+def AArch64MIR_uqincb : AArch64MIR_TargetOp<"uqincb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQINCB_WPiI UQINCB_XPiI
+}
+
+def AArch64MIR_uqincd : AArch64MIR_TargetOp<"uqincd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQINCD_WPiI UQINCD_XPiI UQINCD_ZPiI
+}
+
+def AArch64MIR_uqinch : AArch64MIR_TargetOp<"uqinch", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQINCH_WPiI UQINCH_XPiI UQINCH_ZPiI
+}
+
+def AArch64MIR_uqincp : AArch64MIR_TargetOp<"uqincp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQINCP_WP_B UQINCP_WP_D UQINCP_WP_H UQINCP_WP_S UQINCP_XP_B UQINCP_XP_D UQINCP_XP_H UQINCP_XP_S UQINCP_ZP_D UQINCP_ZP_H UQINCP_ZP_S
+}
+
+def AArch64MIR_uqincw : AArch64MIR_TargetOp<"uqincw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQINCW_WPiI UQINCW_XPiI UQINCW_ZPiI
+}
+
+def AArch64MIR_uqrshlr : AArch64MIR_TargetOp<"uqrshlr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQRSHLR_ZPmZ_B UQRSHLR_ZPmZ_D UQRSHLR_ZPmZ_H UQRSHLR_ZPmZ_S
+}
+
+def AArch64MIR_uqrshl : AArch64MIR_TargetOp<"uqrshl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQRSHL_ZPmZ_B UQRSHL_ZPmZ_D UQRSHL_ZPmZ_H UQRSHL_ZPmZ_S UQRSHLv1i8 UQRSHLv1i16 UQRSHLv1i32 UQRSHLv1i64 UQRSHLv2i32 UQRSHLv2i64 UQRSHLv4i16 UQRSHLv4i32 UQRSHLv8i8 UQRSHLv8i16 UQRSHLv16i8
+}
+
+def AArch64MIR_uqrshrnb : AArch64MIR_TargetOp<"uqrshrnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQRSHRNB_ZZI_B UQRSHRNB_ZZI_H UQRSHRNB_ZZI_S
+}
+
+def AArch64MIR_uqrshrnt : AArch64MIR_TargetOp<"uqrshrnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQRSHRNT_ZZI_B UQRSHRNT_ZZI_H UQRSHRNT_ZZI_S
+}
+
+def AArch64MIR_uqrshrn : AArch64MIR_TargetOp<"uqrshrn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQRSHRN_VG4_Z4ZI_B UQRSHRN_VG4_Z4ZI_H UQRSHRN_Z2ZI_HtoB UQRSHRN_Z2ZI_StoH UQRSHRNb UQRSHRNh UQRSHRNs UQRSHRNv2i32_shift UQRSHRNv4i16_shift UQRSHRNv8i8_shift
+}
+
+def AArch64MIR_uqrshrn2 : AArch64MIR_TargetOp<"uqrshrn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQRSHRNv4i32_shift UQRSHRNv8i16_shift UQRSHRNv16i8_shift
+}
+
+def AArch64MIR_uqrshr : AArch64MIR_TargetOp<"uqrshr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQRSHR_VG2_Z2ZI_H UQRSHR_VG4_Z4ZI_B UQRSHR_VG4_Z4ZI_H
+}
+
+def AArch64MIR_uqshlr : AArch64MIR_TargetOp<"uqshlr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQSHLR_ZPmZ_B UQSHLR_ZPmZ_D UQSHLR_ZPmZ_H UQSHLR_ZPmZ_S
+}
+
+def AArch64MIR_uqshl : AArch64MIR_TargetOp<"uqshl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQSHL_ZPmI_B UQSHL_ZPmI_D UQSHL_ZPmI_H UQSHL_ZPmI_S UQSHL_ZPmZ_B UQSHL_ZPmZ_D UQSHL_ZPmZ_H UQSHL_ZPmZ_S UQSHLb UQSHLd UQSHLh UQSHLs UQSHLv1i8 UQSHLv1i16 UQSHLv1i32 UQSHLv1i64 UQSHLv2i32 UQSHLv2i32_shift UQSHLv2i64 UQSHLv2i64_shift UQSHLv4i16 UQSHLv4i16_shift UQSHLv4i32 UQSHLv4i32_shift UQSHLv8i8 UQSHLv8i8_shift UQSHLv8i16 UQSHLv8i16_shift UQSHLv16i8 UQSHLv16i8_shift
+}
+
+def AArch64MIR_uqshrnb : AArch64MIR_TargetOp<"uqshrnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQSHRNB_ZZI_B UQSHRNB_ZZI_H UQSHRNB_ZZI_S
+}
+
+def AArch64MIR_uqshrnt : AArch64MIR_TargetOp<"uqshrnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQSHRNT_ZZI_B UQSHRNT_ZZI_H UQSHRNT_ZZI_S
+}
+
+def AArch64MIR_uqshrn : AArch64MIR_TargetOp<"uqshrn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQSHRN_Z2ZI_HtoB UQSHRN_Z2ZI_StoH UQSHRNb UQSHRNh UQSHRNs UQSHRNv2i32_shift UQSHRNv4i16_shift UQSHRNv8i8_shift
+}
+
+def AArch64MIR_uqshrn2 : AArch64MIR_TargetOp<"uqshrn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQSHRNv4i32_shift UQSHRNv8i16_shift UQSHRNv16i8_shift
+}
+
+def AArch64MIR_uqsubr : AArch64MIR_TargetOp<"uqsubr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQSUBR_ZPmZ_B UQSUBR_ZPmZ_D UQSUBR_ZPmZ_H UQSUBR_ZPmZ_S
+}
+
+def AArch64MIR_uqsub : AArch64MIR_TargetOp<"uqsub", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQSUB_ZI_B UQSUB_ZI_D UQSUB_ZI_H UQSUB_ZI_S UQSUB_ZPmZ_B UQSUB_ZPmZ_D UQSUB_ZPmZ_H UQSUB_ZPmZ_S UQSUB_ZZZ_B UQSUB_ZZZ_D UQSUB_ZZZ_H UQSUB_ZZZ_S UQSUBv1i8 UQSUBv1i16 UQSUBv1i32 UQSUBv1i64 UQSUBv2i32 UQSUBv2i64 UQSUBv4i16 UQSUBv4i32 UQSUBv8i8 UQSUBv8i16 UQSUBv16i8
+}
+
+def AArch64MIR_uqxtnb : AArch64MIR_TargetOp<"uqxtnb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQXTNB_ZZ_B UQXTNB_ZZ_H UQXTNB_ZZ_S
+}
+
+def AArch64MIR_uqxtnt : AArch64MIR_TargetOp<"uqxtnt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQXTNT_ZZ_B UQXTNT_ZZ_H UQXTNT_ZZ_S
+}
+
+def AArch64MIR_uqxtn : AArch64MIR_TargetOp<"uqxtn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQXTNv1i8 UQXTNv1i16 UQXTNv1i32 UQXTNv2i32 UQXTNv4i16 UQXTNv8i8
+}
+
+def AArch64MIR_uqxtn2 : AArch64MIR_TargetOp<"uqxtn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UQXTNv4i32 UQXTNv8i16 UQXTNv16i8
+}
+
+def AArch64MIR_urecpe : AArch64MIR_TargetOp<"urecpe", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: URECPE_ZPmZ_S URECPE_ZPzZ_S URECPEv2i32 URECPEv4i32
+}
+
+def AArch64MIR_urhadd : AArch64MIR_TargetOp<"urhadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: URHADD_ZPmZ_B URHADD_ZPmZ_D URHADD_ZPmZ_H URHADD_ZPmZ_S URHADDv2i32 URHADDv4i16 URHADDv4i32 URHADDv8i8 URHADDv8i16 URHADDv16i8
+}
+
+def AArch64MIR_urshlr : AArch64MIR_TargetOp<"urshlr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: URSHLR_ZPmZ_B URSHLR_ZPmZ_D URSHLR_ZPmZ_H URSHLR_ZPmZ_S
+}
+
+def AArch64MIR_urshl : AArch64MIR_TargetOp<"urshl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: URSHL_VG2_2Z2Z_B URSHL_VG2_2Z2Z_D URSHL_VG2_2Z2Z_H URSHL_VG2_2Z2Z_S URSHL_VG2_2ZZ_B URSHL_VG2_2ZZ_D URSHL_VG2_2ZZ_H URSHL_VG2_2ZZ_S URSHL_VG4_4Z4Z_B URSHL_VG4_4Z4Z_D URSHL_VG4_4Z4Z_H URSHL_VG4_4Z4Z_S URSHL_VG4_4ZZ_B URSHL_VG4_4ZZ_D URSHL_VG4_4ZZ_H URSHL_VG4_4ZZ_S URSHL_ZPmZ_B URSHL_ZPmZ_D URSHL_ZPmZ_H URSHL_ZPmZ_S URSHLv1i64 URSHLv2i32 URSHLv2i64 URSHLv4i16 URSHLv4i32 URSHLv8i8 URSHLv8i16 URSHLv16i8
+}
+
+def AArch64MIR_urshr : AArch64MIR_TargetOp<"urshr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: URSHR_ZPmI_B URSHR_ZPmI_D URSHR_ZPmI_H URSHR_ZPmI_S URSHRd URSHRv2i32_shift URSHRv2i64_shift URSHRv4i16_shift URSHRv4i32_shift URSHRv8i8_shift URSHRv8i16_shift URSHRv16i8_shift
+}
+
+def AArch64MIR_ursqrte : AArch64MIR_TargetOp<"ursqrte", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: URSQRTE_ZPmZ_S URSQRTE_ZPzZ_S URSQRTEv2i32 URSQRTEv4i32
+}
+
+def AArch64MIR_ursra : AArch64MIR_TargetOp<"ursra", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: URSRA_ZZI_B URSRA_ZZI_D URSRA_ZZI_H URSRA_ZZI_S URSRAd URSRAv2i32_shift URSRAv2i64_shift URSRAv4i16_shift URSRAv4i32_shift URSRAv8i8_shift URSRAv8i16_shift URSRAv16i8_shift
+}
+
+def AArch64MIR_usdot : AArch64MIR_TargetOp<"usdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USDOT_VG2_M2Z2Z_BToS USDOT_VG2_M2ZZI_BToS USDOT_VG2_M2ZZ_BToS USDOT_VG4_M4Z4Z_BToS USDOT_VG4_M4ZZI_BToS USDOT_VG4_M4ZZ_BToS USDOT_ZZZ USDOT_ZZZI USDOTlanev8i8 USDOTlanev16i8 USDOTv8i8 USDOTv16i8
+}
+
+def AArch64MIR_ushllb : AArch64MIR_TargetOp<"ushllb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USHLLB_ZZI_D USHLLB_ZZI_H USHLLB_ZZI_S
+}
+
+def AArch64MIR_ushllt : AArch64MIR_TargetOp<"ushllt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USHLLT_ZZI_D USHLLT_ZZI_H USHLLT_ZZI_S
+}
+
+def AArch64MIR_ushll : AArch64MIR_TargetOp<"ushll", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USHLLv2i32_shift USHLLv4i16_shift USHLLv8i8_shift
+}
+
+def AArch64MIR_ushll2 : AArch64MIR_TargetOp<"ushll2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USHLLv4i32_shift USHLLv8i16_shift USHLLv16i8_shift
+}
+
+def AArch64MIR_ushl : AArch64MIR_TargetOp<"ushl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USHLv1i64 USHLv2i32 USHLv2i64 USHLv4i16 USHLv4i32 USHLv8i8 USHLv8i16 USHLv16i8
+}
+
+def AArch64MIR_ushr : AArch64MIR_TargetOp<"ushr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USHRd USHRv2i32_shift USHRv2i64_shift USHRv4i16_shift USHRv4i32_shift USHRv8i8_shift USHRv8i16_shift USHRv16i8_shift
+}
+
+def AArch64MIR_usmlall : AArch64MIR_TargetOp<"usmlall", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USMLALL_MZZI_BtoS USMLALL_MZZ_BtoS USMLALL_VG2_M2Z2Z_BtoS USMLALL_VG2_M2ZZI_BtoS USMLALL_VG2_M2ZZ_BtoS USMLALL_VG4_M4Z4Z_BtoS USMLALL_VG4_M4ZZI_BtoS USMLALL_VG4_M4ZZ_BtoS
+}
+
+def AArch64MIR_usmmla : AArch64MIR_TargetOp<"usmmla", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USMMLA USMMLA_ZZZ
+}
+
+def AArch64MIR_usmop4a : AArch64MIR_TargetOp<"usmop4a", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USMOP4A_M2Z2Z_BToS USMOP4A_M2Z2Z_HtoD USMOP4A_M2ZZ_BToS USMOP4A_M2ZZ_HtoD USMOP4A_MZ2Z_BToS USMOP4A_MZ2Z_HtoD USMOP4A_MZZ_BToS USMOP4A_MZZ_HtoD
+}
+
+def AArch64MIR_usmop4s : AArch64MIR_TargetOp<"usmop4s", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USMOP4S_M2Z2Z_BToS USMOP4S_M2Z2Z_HtoD USMOP4S_M2ZZ_BToS USMOP4S_M2ZZ_HtoD USMOP4S_MZ2Z_BToS USMOP4S_MZ2Z_HtoD USMOP4S_MZZ_BToS USMOP4S_MZZ_HtoD
+}
+
+def AArch64MIR_usmopa : AArch64MIR_TargetOp<"usmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USMOPA_MPPZZ_D USMOPA_MPPZZ_S
+}
+
+def AArch64MIR_usmops : AArch64MIR_TargetOp<"usmops", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USMOPS_MPPZZ_D USMOPS_MPPZZ_S
+}
+
+def AArch64MIR_usqadd : AArch64MIR_TargetOp<"usqadd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USQADD_ZPmZ_B USQADD_ZPmZ_D USQADD_ZPmZ_H USQADD_ZPmZ_S USQADDv1i8 USQADDv1i16 USQADDv1i32 USQADDv1i64 USQADDv2i32 USQADDv2i64 USQADDv4i16 USQADDv4i32 USQADDv8i8 USQADDv8i16 USQADDv16i8
+}
+
+def AArch64MIR_usra : AArch64MIR_TargetOp<"usra", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USRA_ZZI_B USRA_ZZI_D USRA_ZZI_H USRA_ZZI_S USRAd USRAv2i32_shift USRAv2i64_shift USRAv4i16_shift USRAv4i32_shift USRAv8i8_shift USRAv8i16_shift USRAv16i8_shift
+}
+
+def AArch64MIR_ustmopa : AArch64MIR_TargetOp<"ustmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USTMOPA_M2ZZZI_BtoS
+}
+
+def AArch64MIR_usublb : AArch64MIR_TargetOp<"usublb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USUBLB_ZZZ_D USUBLB_ZZZ_H USUBLB_ZZZ_S
+}
+
+def AArch64MIR_usublt : AArch64MIR_TargetOp<"usublt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USUBLT_ZZZ_D USUBLT_ZZZ_H USUBLT_ZZZ_S
+}
+
+def AArch64MIR_usubl : AArch64MIR_TargetOp<"usubl", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USUBLv2i32_v2i64 USUBLv4i16_v4i32 USUBLv8i8_v8i16
+}
+
+def AArch64MIR_usubl2 : AArch64MIR_TargetOp<"usubl2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USUBLv4i32_v2i64 USUBLv8i16_v4i32 USUBLv16i8_v8i16
+}
+
+def AArch64MIR_usubwb : AArch64MIR_TargetOp<"usubwb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USUBWB_ZZZ_D USUBWB_ZZZ_H USUBWB_ZZZ_S
+}
+
+def AArch64MIR_usubwt : AArch64MIR_TargetOp<"usubwt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USUBWT_ZZZ_D USUBWT_ZZZ_H USUBWT_ZZZ_S
+}
+
+def AArch64MIR_usubw : AArch64MIR_TargetOp<"usubw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USUBWv2i32_v2i64 USUBWv4i16_v4i32 USUBWv8i8_v8i16
+}
+
+def AArch64MIR_usubw2 : AArch64MIR_TargetOp<"usubw2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USUBWv4i32_v2i64 USUBWv8i16_v4i32 USUBWv16i8_v8i16
+}
+
+def AArch64MIR_usvdot : AArch64MIR_TargetOp<"usvdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: USVDOT_VG4_M4ZZI_BToS
+}
+
+def AArch64MIR_utmopa : AArch64MIR_TargetOp<"utmopa", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UTMOPA_M2ZZZI_BtoS UTMOPA_M2ZZZI_HtoS
+}
+
+def AArch64MIR_uunpkhi : AArch64MIR_TargetOp<"uunpkhi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UUNPKHI_ZZ_D UUNPKHI_ZZ_H UUNPKHI_ZZ_S
+}
+
+def AArch64MIR_uunpklo : AArch64MIR_TargetOp<"uunpklo", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UUNPKLO_ZZ_D UUNPKLO_ZZ_H UUNPKLO_ZZ_S
+}
+
+def AArch64MIR_uunpk : AArch64MIR_TargetOp<"uunpk", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UUNPK_VG2_2ZZ_D UUNPK_VG2_2ZZ_H UUNPK_VG2_2ZZ_S UUNPK_VG4_4Z2Z_D UUNPK_VG4_4Z2Z_H UUNPK_VG4_4Z2Z_S
+}
+
+def AArch64MIR_uvdot : AArch64MIR_TargetOp<"uvdot", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UVDOT_VG2_M2ZZI_HtoS UVDOT_VG4_M4ZZI_BtoS UVDOT_VG4_M4ZZI_HtoD
+}
+
+def AArch64MIR_uxtb : AArch64MIR_TargetOp<"uxtb", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UXTB_ZPmZ_D UXTB_ZPmZ_H UXTB_ZPmZ_S UXTB_ZPzZ_D UXTB_ZPzZ_H UXTB_ZPzZ_S
+}
+
+def AArch64MIR_uxth : AArch64MIR_TargetOp<"uxth", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UXTH_ZPmZ_D UXTH_ZPmZ_S UXTH_ZPzZ_D UXTH_ZPzZ_S
+}
+
+def AArch64MIR_uxtw : AArch64MIR_TargetOp<"uxtw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UXTW_ZPmZ_D UXTW_ZPzZ_D
+}
+
+def AArch64MIR_uzp1 : AArch64MIR_TargetOp<"uzp1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UZP1_PPP_B UZP1_PPP_D UZP1_PPP_H UZP1_PPP_S UZP1_ZZZ_B UZP1_ZZZ_D UZP1_ZZZ_H UZP1_ZZZ_Q UZP1_ZZZ_S UZP1v2i32 UZP1v2i64 UZP1v4i16 UZP1v4i32 UZP1v8i8 UZP1v8i16 UZP1v16i8
+}
+
+def AArch64MIR_uzp2 : AArch64MIR_TargetOp<"uzp2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UZP2_PPP_B UZP2_PPP_D UZP2_PPP_H UZP2_PPP_S UZP2_ZZZ_B UZP2_ZZZ_D UZP2_ZZZ_H UZP2_ZZZ_Q UZP2_ZZZ_S UZP2v2i32 UZP2v2i64 UZP2v4i16 UZP2v4i32 UZP2v8i8 UZP2v8i16 UZP2v16i8
+}
+
+def AArch64MIR_uzpq1 : AArch64MIR_TargetOp<"uzpq1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UZPQ1_ZZZ_B UZPQ1_ZZZ_D UZPQ1_ZZZ_H UZPQ1_ZZZ_S
+}
+
+def AArch64MIR_uzpq2 : AArch64MIR_TargetOp<"uzpq2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UZPQ2_ZZZ_B UZPQ2_ZZZ_D UZPQ2_ZZZ_H UZPQ2_ZZZ_S
+}
+
+def AArch64MIR_uzp : AArch64MIR_TargetOp<"uzp", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: UZP_VG2_2ZZZ_B UZP_VG2_2ZZZ_D UZP_VG2_2ZZZ_H UZP_VG2_2ZZZ_Q UZP_VG2_2ZZZ_S UZP_VG4_4Z4Z_B UZP_VG4_4Z4Z_D UZP_VG4_4Z4Z_H UZP_VG4_4Z4Z_Q UZP_VG4_4Z4Z_S
+}
+
+def AArch64MIR_wfet : AArch64MIR_TargetOp<"wfet", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WFET
+}
+
+def AArch64MIR_wfit : AArch64MIR_TargetOp<"wfit", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WFIT
+}
+
+def AArch64MIR_whilege : AArch64MIR_TargetOp<"whilege", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILEGE_2PXX_B WHILEGE_2PXX_D WHILEGE_2PXX_H WHILEGE_2PXX_S WHILEGE_CXX_B WHILEGE_CXX_D WHILEGE_CXX_H WHILEGE_CXX_S WHILEGE_PWW_B WHILEGE_PWW_D WHILEGE_PWW_H WHILEGE_PWW_S WHILEGE_PXX_B WHILEGE_PXX_D WHILEGE_PXX_H WHILEGE_PXX_S
+}
+
+def AArch64MIR_whilegt : AArch64MIR_TargetOp<"whilegt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILEGT_2PXX_B WHILEGT_2PXX_D WHILEGT_2PXX_H WHILEGT_2PXX_S WHILEGT_CXX_B WHILEGT_CXX_D WHILEGT_CXX_H WHILEGT_CXX_S WHILEGT_PWW_B WHILEGT_PWW_D WHILEGT_PWW_H WHILEGT_PWW_S WHILEGT_PXX_B WHILEGT_PXX_D WHILEGT_PXX_H WHILEGT_PXX_S
+}
+
+def AArch64MIR_whilehi : AArch64MIR_TargetOp<"whilehi", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILEHI_2PXX_B WHILEHI_2PXX_D WHILEHI_2PXX_H WHILEHI_2PXX_S WHILEHI_CXX_B WHILEHI_CXX_D WHILEHI_CXX_H WHILEHI_CXX_S WHILEHI_PWW_B WHILEHI_PWW_D WHILEHI_PWW_H WHILEHI_PWW_S WHILEHI_PXX_B WHILEHI_PXX_D WHILEHI_PXX_H WHILEHI_PXX_S
+}
+
+def AArch64MIR_whilehs : AArch64MIR_TargetOp<"whilehs", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILEHS_2PXX_B WHILEHS_2PXX_D WHILEHS_2PXX_H WHILEHS_2PXX_S WHILEHS_CXX_B WHILEHS_CXX_D WHILEHS_CXX_H WHILEHS_CXX_S WHILEHS_PWW_B WHILEHS_PWW_D WHILEHS_PWW_H WHILEHS_PWW_S WHILEHS_PXX_B WHILEHS_PXX_D WHILEHS_PXX_H WHILEHS_PXX_S
+}
+
+def AArch64MIR_whilele : AArch64MIR_TargetOp<"whilele", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILELE_2PXX_B WHILELE_2PXX_D WHILELE_2PXX_H WHILELE_2PXX_S WHILELE_CXX_B WHILELE_CXX_D WHILELE_CXX_H WHILELE_CXX_S WHILELE_PWW_B WHILELE_PWW_D WHILELE_PWW_H WHILELE_PWW_S WHILELE_PXX_B WHILELE_PXX_D WHILELE_PXX_H WHILELE_PXX_S
+}
+
+def AArch64MIR_whilelo : AArch64MIR_TargetOp<"whilelo", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILELO_2PXX_B WHILELO_2PXX_D WHILELO_2PXX_H WHILELO_2PXX_S WHILELO_CXX_B WHILELO_CXX_D WHILELO_CXX_H WHILELO_CXX_S WHILELO_PWW_B WHILELO_PWW_D WHILELO_PWW_H WHILELO_PWW_S WHILELO_PXX_B WHILELO_PXX_D WHILELO_PXX_H WHILELO_PXX_S
+}
+
+def AArch64MIR_whilels : AArch64MIR_TargetOp<"whilels", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILELS_2PXX_B WHILELS_2PXX_D WHILELS_2PXX_H WHILELS_2PXX_S WHILELS_CXX_B WHILELS_CXX_D WHILELS_CXX_H WHILELS_CXX_S WHILELS_PWW_B WHILELS_PWW_D WHILELS_PWW_H WHILELS_PWW_S WHILELS_PXX_B WHILELS_PXX_D WHILELS_PXX_H WHILELS_PXX_S
+}
+
+def AArch64MIR_whilelt : AArch64MIR_TargetOp<"whilelt", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILELT_2PXX_B WHILELT_2PXX_D WHILELT_2PXX_H WHILELT_2PXX_S WHILELT_CXX_B WHILELT_CXX_D WHILELT_CXX_H WHILELT_CXX_S WHILELT_PWW_B WHILELT_PWW_D WHILELT_PWW_H WHILELT_PWW_S WHILELT_PXX_B WHILELT_PXX_D WHILELT_PXX_H WHILELT_PXX_S
+}
+
+def AArch64MIR_whilerw : AArch64MIR_TargetOp<"whilerw", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILERW_PXX_B WHILERW_PXX_D WHILERW_PXX_H WHILERW_PXX_S
+}
+
+def AArch64MIR_whilewr : AArch64MIR_TargetOp<"whilewr", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WHILEWR_PXX_B WHILEWR_PXX_D WHILEWR_PXX_H WHILEWR_PXX_S
+}
+
+def AArch64MIR_wrffr : AArch64MIR_TargetOp<"wrffr", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: WRFFR
+}
+
+def AArch64MIR_xaflag : AArch64MIR_TargetOp<"xaflag", []> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: XAFLAG
+}
+
+def AArch64MIR_xar : AArch64MIR_TargetOp<"xar", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: XAR XAR_ZZZI_B XAR_ZZZI_D XAR_ZZZI_H XAR_ZZZI_S
+}
+
+def AArch64MIR_xpacd : AArch64MIR_TargetOp<"xpacd", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: XPACD
+}
+
+def AArch64MIR_xpaci : AArch64MIR_TargetOp<"xpaci", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: XPACI
+}
+
+def AArch64MIR_xtn : AArch64MIR_TargetOp<"xtn", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: XTNv2i32 XTNv4i16 XTNv8i8
+}
+
+def AArch64MIR_xtn2 : AArch64MIR_TargetOp<"xtn2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: XTNv4i32 XTNv8i16 XTNv16i8
+}
+
+def AArch64MIR_zero : AArch64MIR_TargetOp<"zero", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ZERO_M ZERO_MXI_2Z ZERO_MXI_4Z ZERO_MXI_VG2_2Z ZERO_MXI_VG2_4Z ZERO_MXI_VG2_Z ZERO_MXI_VG4_2Z ZERO_MXI_VG4_4Z ZERO_MXI_VG4_Z ZERO_T
+}
+
+def AArch64MIR_zip1 : AArch64MIR_TargetOp<"zip1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ZIP1_PPP_B ZIP1_PPP_D ZIP1_PPP_H ZIP1_PPP_S ZIP1_ZZZ_B ZIP1_ZZZ_D ZIP1_ZZZ_H ZIP1_ZZZ_Q ZIP1_ZZZ_S ZIP1v2i32 ZIP1v2i64 ZIP1v4i16 ZIP1v4i32 ZIP1v8i8 ZIP1v8i16 ZIP1v16i8
+}
+
+def AArch64MIR_zip2 : AArch64MIR_TargetOp<"zip2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ZIP2_PPP_B ZIP2_PPP_D ZIP2_PPP_H ZIP2_PPP_S ZIP2_ZZZ_B ZIP2_ZZZ_D ZIP2_ZZZ_H ZIP2_ZZZ_Q ZIP2_ZZZ_S ZIP2v2i32 ZIP2v2i64 ZIP2v4i16 ZIP2v4i32 ZIP2v8i8 ZIP2v8i16 ZIP2v16i8
+}
+
+def AArch64MIR_zipq1 : AArch64MIR_TargetOp<"zipq1", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ZIPQ1_ZZZ_B ZIPQ1_ZZZ_D ZIPQ1_ZZZ_H ZIPQ1_ZZZ_S
+}
+
+def AArch64MIR_zipq2 : AArch64MIR_TargetOp<"zipq2", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ZIPQ2_ZZZ_B ZIPQ2_ZZZ_D ZIPQ2_ZZZ_H ZIPQ2_ZZZ_S
+}
+
+def AArch64MIR_zip : AArch64MIR_TargetOp<"zip", [Pure]> {
+ let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+ OptionalAttr<StrAttr>:$variant);
+ let results = (outs Variadic<MIR_AnyLLT>:$rets);
+ // opcodes: ZIP_VG2_2ZZZ_B ZIP_VG2_2ZZZ_D ZIP_VG2_2ZZZ_H ZIP_VG2_2ZZZ_Q ZIP_VG2_2ZZZ_S ZIP_VG4_4Z4Z_B ZIP_VG4_4Z4Z_D ZIP_VG4_4Z4Z_H ZIP_VG4_4Z4Z_Q ZIP_VG4_4Z4Z_S
+}
+
+// Considered 7484 instructions, emitted 1551 ops across 1551 mnemonics.
diff --git a/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIROps.h b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIROps.h
new file mode 100644
index 0000000000000..1a2ede669ffa5
--- /dev/null
+++ b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIROps.h
@@ -0,0 +1,21 @@
+//===- AArch64MIROps.h - AArch64 MIR operations ---------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIROPS_H
+#define MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIROPS_H
+
+#include "mlir/Bytecode/BytecodeOpInterface.h"
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIRDialect.h"
+#include "mlir/Dialect/MIR/IR/MIRTypes.h"
+#include "mlir/IR/OpImplementation.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIROps.h.inc"
+
+#endif // MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIROPS_H
diff --git a/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIROps.td b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIROps.td
new file mode 100644
index 0000000000000..09e283d61e1bd
--- /dev/null
+++ b/mlir/include/mlir/Dialect/AArch64MIR/IR/AArch64MIROps.td
@@ -0,0 +1,20 @@
+//===- AArch64MIROps.td - AArch64 MIR operations ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIROPS_TD
+#define MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIROPS_TD
+
+include "mlir/Dialect/AArch64MIR/IR/AArch64MIRBase.td"
+include "mlir/Interfaces/SideEffectInterfaces.td"
+
+// The full set of AArch64 selected ops is generated from AArch64's instruction
+// TableGen by the `-gen-mir-target-ops` backend and checked in as
+// AArch64MIRGenOps.td.
+include "mlir/Dialect/AArch64MIR/IR/AArch64MIRGenOps.td"
+
+#endif // MLIR_DIALECT_AARCH64MIR_IR_AARCH64MIROPS_TD
diff --git a/mlir/include/mlir/Dialect/AArch64MIR/IR/CMakeLists.txt b/mlir/include/mlir/Dialect/AArch64MIR/IR/CMakeLists.txt
new file mode 100644
index 0000000000000..d7ee5c2ac70e1
--- /dev/null
+++ b/mlir/include/mlir/Dialect/AArch64MIR/IR/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_mlir_dialect(AArch64MIROps aarch64_mir)
+add_mlir_doc(AArch64MIROps AArch64MIROps Dialects/ -gen-dialect-doc)
diff --git a/mlir/include/mlir/Dialect/CMakeLists.txt b/mlir/include/mlir/Dialect/CMakeLists.txt
index dd1926c4cd3a5..f6087979145a6 100644
--- a/mlir/include/mlir/Dialect/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/CMakeLists.txt
@@ -1,4 +1,5 @@
add_subdirectory(Affine)
+add_subdirectory(AArch64MIR)
add_subdirectory(AMDGPU)
add_subdirectory(Arith)
add_subdirectory(ArmNeon)
diff --git a/mlir/lib/Dialect/AArch64MIR/CMakeLists.txt b/mlir/lib/Dialect/AArch64MIR/CMakeLists.txt
new file mode 100644
index 0000000000000..f33061b2d87cf
--- /dev/null
+++ b/mlir/lib/Dialect/AArch64MIR/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory(IR)
diff --git a/mlir/lib/Dialect/AArch64MIR/IR/AArch64MIRDialect.cpp b/mlir/lib/Dialect/AArch64MIR/IR/AArch64MIRDialect.cpp
new file mode 100644
index 0000000000000..21f2035dde666
--- /dev/null
+++ b/mlir/lib/Dialect/AArch64MIR/IR/AArch64MIRDialect.cpp
@@ -0,0 +1,27 @@
+//===- AArch64MIRDialect.cpp - AArch64 MIR dialect impl -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIROps.h"
+#include "mlir/Dialect/MIR/IR/MIRDialect.h"
+#include "mlir/IR/Builders.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIROpsDialect.cpp.inc"
+
+using namespace mlir;
+using namespace mlir::aarch64_mir;
+
+void AArch64MIRDialect::initialize() {
+ addOperations<
+#define GET_OP_LIST
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIROps.cpp.inc"
+ >();
+}
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIROps.cpp.inc"
diff --git a/mlir/lib/Dialect/AArch64MIR/IR/CMakeLists.txt b/mlir/lib/Dialect/AArch64MIR/IR/CMakeLists.txt
new file mode 100644
index 0000000000000..ac9ac8ed93cda
--- /dev/null
+++ b/mlir/lib/Dialect/AArch64MIR/IR/CMakeLists.txt
@@ -0,0 +1,14 @@
+add_mlir_dialect_library(MLIRAArch64MIRDialect
+ AArch64MIRDialect.cpp
+
+ ADDITIONAL_HEADER_DIRS
+ ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/AArch64MIR
+
+ DEPENDS
+ MLIRAArch64MIROpsIncGen
+
+ LINK_LIBS PUBLIC
+ MLIRIR
+ MLIRMIRDialect
+ MLIRSideEffectInterfaces
+ )
diff --git a/mlir/lib/Dialect/CMakeLists.txt b/mlir/lib/Dialect/CMakeLists.txt
index 1a10351744f4d..dfa8d93cb5491 100644
--- a/mlir/lib/Dialect/CMakeLists.txt
+++ b/mlir/lib/Dialect/CMakeLists.txt
@@ -1,4 +1,5 @@
add_subdirectory(Affine)
+add_subdirectory(AArch64MIR)
add_subdirectory(AMDGPU)
add_subdirectory(Arith)
add_subdirectory(ArmNeon)
diff --git a/mlir/lib/RegisterAllDialects.cpp b/mlir/lib/RegisterAllDialects.cpp
index b9cd1cc177e5b..5518479cc2293 100644
--- a/mlir/lib/RegisterAllDialects.cpp
+++ b/mlir/lib/RegisterAllDialects.cpp
@@ -13,6 +13,7 @@
#include "mlir/InitAllDialects.h"
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIRDialect.h"
#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h"
#include "mlir/Dialect/AMDGPU/Transforms/MemoryAccessOpInterfacesImpl.h"
#include "mlir/Dialect/Affine/IR/AffineOps.h"
@@ -116,6 +117,7 @@
void mlir::registerAllDialects(DialectRegistry ®istry) {
// clang-format off
registry.insert<acc::OpenACCDialect,
+ aarch64_mir::AArch64MIRDialect,
affine::AffineDialect,
amdgpu::AMDGPUDialect,
arith::ArithDialect,
diff --git a/mlir/test/Dialect/AArch64MIR/roundtrip.mlir b/mlir/test/Dialect/AArch64MIR/roundtrip.mlir
new file mode 100644
index 0000000000000..466858304a6c8
--- /dev/null
+++ b/mlir/test/Dialect/AArch64MIR/roundtrip.mlir
@@ -0,0 +1,24 @@
+// RUN: mlir-opt %s | mlir-opt | FileCheck %s
+
+// The aarch64_mir dialect (selected AArch64 ops) is closely coupled to the mir
+// dialect: its ops reuse the mir LLT type system and intermix with generic
+// (mir.g_*) ops inside a single mir.func container. This is a parse/print
+// round-trip check of a partially-selected function.
+
+// CHECK-LABEL: mir.func @selected
+mir.func @selected {
+ // CHECK: %[[P:.*]] = mir.copy_from_phys #mir.physreg<"x0"> -> !mir.pointer<0, 64>
+ %p = mir.copy_from_phys #mir.physreg<"x0"> -> !mir.pointer<0, 64>
+ // Generic (not-yet-selected) load.
+ // CHECK: %[[L:.*]] = mir.g_load %[[P]] : (!mir.pointer<0, 64>) -> !mir.scalar<64>
+ %l = mir.g_load %p : (!mir.pointer<0, 64>) -> !mir.scalar<64>
+
+ // Selected AArch64 ops, collapsed to one op per mnemonic.
+ // CHECK: %[[A:.*]] = aarch64_mir.add %[[L]], %[[L]] : (!mir.scalar<64>, !mir.scalar<64>) -> !mir.scalar<64>
+ %a = aarch64_mir.add %l, %l : (!mir.scalar<64>, !mir.scalar<64>) -> !mir.scalar<64>
+ // CHECK: %[[N:.*]] = aarch64_mir.and %[[A]], %[[L]] {variant = "ANDXrr"} : (!mir.scalar<64>, !mir.scalar<64>) -> !mir.scalar<64>
+ %n = aarch64_mir.and %a, %l {variant = "ANDXrr"} : (!mir.scalar<64>, !mir.scalar<64>) -> !mir.scalar<64>
+
+ // CHECK: mir.copy_to_phys %[[N]] : !mir.scalar<64> to #mir.physreg<"x0">
+ mir.copy_to_phys %n : !mir.scalar<64> to #mir.physreg<"x0">
+}
diff --git a/mlir/test/mlir-tblgen/mir-aarch64-ops.td b/mlir/test/mlir-tblgen/mir-aarch64-ops.td
new file mode 100644
index 0000000000000..9080ce7b54d1b
--- /dev/null
+++ b/mlir/test/mlir-tblgen/mir-aarch64-ops.td
@@ -0,0 +1,27 @@
+// Verify the -gen-mir-target-ops backend collapses AArch64's selected
+// instructions into one op per mnemonic and emits well-formed MLIR ODS.
+//
+// This parses the whole AArch64 target, so it is only run when the AArch64
+// target's TableGen is available under the source tree.
+//
+// RUN: mlir-tblgen -gen-mir-target-ops --mir-target=AArch64 \
+// RUN: -I %S/../../../llvm/include -I %S/../../../llvm/lib/Target/AArch64 %s \
+// RUN: | FileCheck %s
+
+include "AArch64.td"
+
+// A pure ALU op collapsed from its many encoding variants.
+// CHECK: def AArch64MIR_add : AArch64MIR_TargetOp<"add", [Pure]> {
+// CHECK-NEXT: let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,
+// CHECK: OptionalAttr<StrAttr>:$variant);
+// CHECK-NEXT: let results = (outs Variadic<MIR_AnyLLT>:$rets);
+// CHECK: // opcodes:
+
+// A C++ keyword mnemonic keeps the mnemonic but sanitizes the class/def name.
+// CHECK: def AArch64MIR_and_ : AArch64MIR_TargetOp<"and", [Pure]> {
+
+// The conditional-branch mnemonic (AsmString "b.$cond") is sanitized.
+// CHECK: def AArch64MIR_b_cond : AArch64MIR_TargetOp<"b_cond",
+
+// The collapse produces on the order of ~1.5k ops from ~7.5k instructions.
+// CHECK: emitted 1551 ops across 1551 mnemonics.
diff --git a/mlir/tools/mlir-tblgen/CMakeLists.txt b/mlir/tools/mlir-tblgen/CMakeLists.txt
index cf8221157e294..c34fabb238405 100644
--- a/mlir/tools/mlir-tblgen/CMakeLists.txt
+++ b/mlir/tools/mlir-tblgen/CMakeLists.txt
@@ -20,6 +20,7 @@ add_tablegen(mlir-tblgen MLIR
LLVMIRConversionGen.cpp
LLVMIRIntrinsicGen.cpp
MIRGenericOpGen.cpp
+ MIRTargetOpGen.cpp
mlir-tblgen.cpp
OmpOpGen.cpp
OpClass.cpp
diff --git a/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp b/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
new file mode 100644
index 0000000000000..1f916a435c5d1
--- /dev/null
+++ b/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
@@ -0,0 +1,206 @@
+//===- MIRTargetOpGen.cpp - Generate target MIR op ODS --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// A TableGen backend that reads a target's selected-instruction definitions
+// (`Instruction` records in a given target Namespace) and emits MLIR ODS for a
+// target MIR dialect (e.g. `aarch64_mir`), collapsing the many per-encoding /
+// per-operand-kind record variants down to one op per assembler mnemonic.
+//
+// The collapse follows the design established for these dialects: within a
+// mnemonic, operand-kind/width variation is absorbed by modeling operands and
+// results as LLT-typed values (mir dialect's MIR_AnyLLT); the concrete target
+// opcode is recovered at export time from the operand types plus an optional
+// `variant` discriminator. This backend also emits a lowering table mapping
+// each generated op back to the set of concrete opcodes it subsumes.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/TableGen/GenInfo.h"
+
+#include "llvm/ADT/DenseSet.h"
+#include "llvm/ADT/MapVector.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSet.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+
+using llvm::Record;
+using llvm::RecordKeeper;
+using namespace mlir;
+
+static llvm::cl::OptionCategory targetOpCat("MIR target-op generator options");
+
+static llvm::cl::opt<std::string>
+ targetNamespace("mir-target",
+ llvm::cl::desc("Target Namespace to filter instructions by "
+ "(e.g. AArch64)"),
+ llvm::cl::init("AArch64"), llvm::cl::cat(targetOpCat));
+
+static llvm::cl::opt<std::string>
+ dialectClass("mir-target-opbase",
+ llvm::cl::desc("ODS base class for the generated ops"),
+ llvm::cl::init("AArch64MIR_TargetOp"),
+ llvm::cl::cat(targetOpCat));
+
+/// Value of a boolean record field, treating unset/missing as false.
+static bool getBitOrFalse(const Record &record, llvm::StringRef field) {
+ const llvm::RecordVal *rv = record.getValue(field);
+ if (!rv)
+ return false;
+ if (const auto *bit = llvm::dyn_cast_or_null<llvm::BitInit>(rv->getValue()))
+ return bit->getValue();
+ return false;
+}
+
+/// Extract the assembler mnemonic (first whitespace/brace/comma-delimited
+/// token) from an AsmString. Returns empty if none.
+static llvm::StringRef getMnemonic(llvm::StringRef asmString) {
+ asmString = asmString.ltrim();
+ size_t end = asmString.find_first_of(" \t{,");
+ return end == llvm::StringRef::npos ? asmString : asmString.take_front(end);
+}
+
+/// Turn a mnemonic into a valid MLIR op name: lowercase, runs of non-alnum
+/// characters collapsed to a single '_', leading/trailing '_' trimmed.
+static std::string sanitizeMnemonic(llvm::StringRef mnemonic) {
+ std::string out;
+ bool lastUnderscore = false;
+ for (char c : mnemonic) {
+ if (llvm::isAlnum(c)) {
+ out += static_cast<char>(llvm::toLower(c));
+ lastUnderscore = false;
+ } else if (!lastUnderscore) {
+ out += '_';
+ lastUnderscore = true;
+ }
+ }
+ llvm::StringRef trimmed = llvm::StringRef(out).trim('_');
+ return trimmed.empty() ? std::string("op") : trimmed.str();
+}
+
+/// Turn a name into a valid ODS/C++ identifier fragment. The result also
+/// becomes the op's C++ class name (ODS strips the dialect prefix), so guard
+/// against C++ keywords and alternative tokens (e.g. the `and` mnemonic).
+static std::string sanitizeIdent(llvm::StringRef name) {
+ std::string out;
+ for (char c : name)
+ out += llvm::isAlnum(c) ? c : '_';
+ if (out.empty() || !llvm::isAlpha(out[0]))
+ out = "op_" + out;
+ static const char *kReserved[] = {
+ "and", "and_eq", "bitand", "bitor", "compl", "not", "not_eq",
+ "or", "or_eq", "xor", "xor_eq", "int", "float", "double",
+ "char", "bool", "void", "class", "struct", "const", "static",
+ "new", "delete", "operator", "template", "default", "return",
+ "register"};
+ for (const char *kw : kReserved)
+ if (out == kw)
+ return out + "_";
+ return out;
+}
+
+namespace {
+/// Accumulated information for one mnemonic cluster.
+struct Cluster {
+ bool anyResults = false; // some variant defines results
+ bool anyOperands = false; // some variant takes inputs
+ bool allPure = true; // every variant is side-effect free
+ bool anyCommutable = false;
+ llvm::SmallVector<std::string> opcodes; // concrete record names subsumed
+};
+} // namespace
+
+/// Count the args in a dag operand list.
+static unsigned numDagArgs(const Record &record, llvm::StringRef field) {
+ if (const auto *dag = llvm::dyn_cast_or_null<llvm::DagInit>(
+ record.getValue(field) ? record.getValue(field)->getValue()
+ : nullptr))
+ return dag->getNumArgs();
+ return 0;
+}
+
+static bool emitTargetOps(const RecordKeeper &records, llvm::raw_ostream &os) {
+ llvm::emitSourceFileHeader(
+ (llvm::Twine(targetNamespace) + " MIR target operations").str(), os,
+ records);
+ os << "include \"mlir/Dialect/MIR/IR/MIRTypes.td\"\n";
+ os << "include \"mlir/Interfaces/SideEffectInterfaces.td\"\n\n";
+
+ // Cluster instructions by mnemonic, preserving first-seen order.
+ llvm::StringMap<unsigned> clusterIndex;
+ llvm::SmallVector<std::pair<std::string, Cluster>> clusters;
+ unsigned considered = 0;
+ for (const Record *r : records.getAllDerivedDefinitions("Instruction")) {
+ if (r->getValueAsString("Namespace") != targetNamespace)
+ continue;
+ if (getBitOrFalse(*r, "isPseudo") || getBitOrFalse(*r, "isCodeGenOnly"))
+ continue;
+ llvm::StringRef mnemonic = getMnemonic(r->getValueAsString("AsmString"));
+ if (mnemonic.empty())
+ continue;
+ ++considered;
+ auto it = clusterIndex.find(mnemonic);
+ if (it == clusterIndex.end()) {
+ it = clusterIndex.insert({mnemonic, clusters.size()}).first;
+ clusters.push_back({mnemonic.str(), Cluster{}});
+ }
+ Cluster &c = clusters[it->second].second;
+ c.anyResults |= numDagArgs(*r, "OutOperandList") > 0;
+ c.anyOperands |= numDagArgs(*r, "InOperandList") > 0;
+ bool pure = !getBitOrFalse(*r, "hasSideEffects") &&
+ !getBitOrFalse(*r, "mayLoad") && !getBitOrFalse(*r, "mayStore");
+ c.allPure &= pure;
+ c.anyCommutable |= getBitOrFalse(*r, "isCommutable");
+ c.opcodes.push_back(r->getName().str());
+ }
+
+ // Emit one op per cluster, uniquifying identifiers.
+ llvm::StringSet<> usedNames;
+ unsigned emitted = 0;
+ for (const auto &kv : clusters) {
+ llvm::StringRef mnemonic = kv.first;
+ const Cluster &c = kv.second;
+
+ std::string opName = sanitizeMnemonic(mnemonic);
+ std::string ident = sanitizeIdent(opName);
+ std::string base = ident;
+ unsigned suffix = 0;
+ while (!usedNames.insert(ident).second)
+ ident = base + "_" + llvm::utostr(suffix++);
+
+ llvm::SmallVector<llvm::StringRef> traits;
+ if (c.allPure)
+ traits.push_back("Pure");
+ if (c.anyCommutable)
+ traits.push_back("Commutative");
+
+ os << "def " << targetNamespace << "MIR_" << ident << " : "
+ << dialectClass << "<\"" << opName << "\", [";
+ llvm::interleaveComma(traits, os);
+ os << "]> {\n";
+ os << " let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,\n"
+ " OptionalAttr<StrAttr>:$variant);\n";
+ os << " let results = (outs Variadic<MIR_AnyLLT>:$rets);\n";
+ // Lowering table: the concrete opcodes this op subsumes.
+ os << " // opcodes:";
+ for (llvm::StringRef opc : c.opcodes)
+ os << " " << opc;
+ os << "\n}\n\n";
+ ++emitted;
+ }
+
+ os << "// Considered " << considered << " instructions, emitted " << emitted
+ << " ops across " << clusters.size() << " mnemonics.\n";
+ return false;
+}
+
+static mlir::GenRegistration
+ genMIRTargetOps("gen-mir-target-ops",
+ "Generate target MIR dialect operation ODS", emitTargetOps);
>From e8647de67b9520c2f88474a0711c4adb3140bb78 Mon Sep 17 00:00:00 2001
From: makslevental <maksim.levental at gmail.com>
Date: Mon, 24 Aug 2026 11:19:51 -0700
Subject: [PATCH 4/7] [MLIR] Add import-mir translation: .mir -> mir dialect
(generic subset)
Adds MLIRTargetMIRImport, registering the `import-mir` mlir-translate
translation. It drives LLVM's MIRParser with a constructed AArch64
TargetMachine + MachineModuleInfo, then walks each MachineFunction into the
mir dialect:
- Generic G_* opcodes -> mir.g_<name> (built generically via OperationState,
operand/result types from each vreg's LLT).
- LLT -> mir types (scalar/pointer/vector).
- COPY at the ABI boundary -> mir.copy_from_phys / mir.copy_to_phys (physreg as
attribute); virtual COPY -> mir.copy. Virtual registers map to SSA values.
Selected target opcodes and dialect->.mir export follow in the next step.
Adds .mir to the MLIR lit suffixes and a round-trip lit test
(Target/MIR/import-generic.mir).
---
mlir/include/mlir/InitAllTranslations.h | 2 +
mlir/lib/Target/CMakeLists.txt | 1 +
mlir/lib/Target/MIR/CMakeLists.txt | 21 ++
mlir/lib/Target/MIR/MIRImport.cpp | 245 ++++++++++++++++++++++++
mlir/test/Target/MIR/import-generic.mir | 28 +++
mlir/test/lit.cfg.py | 1 +
6 files changed, 298 insertions(+)
create mode 100644 mlir/lib/Target/MIR/CMakeLists.txt
create mode 100644 mlir/lib/Target/MIR/MIRImport.cpp
create mode 100644 mlir/test/Target/MIR/import-generic.mir
diff --git a/mlir/include/mlir/InitAllTranslations.h b/mlir/include/mlir/InitAllTranslations.h
index 622024db5a8a2..a5c3a77a4c2a0 100644
--- a/mlir/include/mlir/InitAllTranslations.h
+++ b/mlir/include/mlir/InitAllTranslations.h
@@ -19,6 +19,7 @@
namespace mlir {
void registerFromLLVMIRTranslation();
+void registerFromMIRTranslation();
void registerFromSPIRVTranslation();
void registerFromWasmTranslation();
void registerToCppTranslation();
@@ -35,6 +36,7 @@ void registerExportSMTLIBTranslation();
inline void registerAllTranslations() {
static bool initOnce = []() {
registerFromLLVMIRTranslation();
+ registerFromMIRTranslation();
registerFromSPIRVTranslation();
registerIRDLToCppTranslation();
registerFromWasmTranslation();
diff --git a/mlir/lib/Target/CMakeLists.txt b/mlir/lib/Target/CMakeLists.txt
index f0c3ac4d511c1..214664e75a5aa 100644
--- a/mlir/lib/Target/CMakeLists.txt
+++ b/mlir/lib/Target/CMakeLists.txt
@@ -1,5 +1,6 @@
add_subdirectory(Cpp)
add_subdirectory(IRDLToCpp)
+add_subdirectory(MIR)
add_subdirectory(SPIRV)
add_subdirectory(LLVMIR)
add_subdirectory(LLVM)
diff --git a/mlir/lib/Target/MIR/CMakeLists.txt b/mlir/lib/Target/MIR/CMakeLists.txt
new file mode 100644
index 0000000000000..7e85bfc9fcc6e
--- /dev/null
+++ b/mlir/lib/Target/MIR/CMakeLists.txt
@@ -0,0 +1,21 @@
+add_mlir_translation_library(MLIRTargetMIRImport
+ MIRImport.cpp
+
+ ADDITIONAL_HEADER_DIRS
+ ${MLIR_MAIN_INCLUDE_DIR}/mlir/Target/MIR
+
+ LINK_COMPONENTS
+ AArch64CodeGen
+ AArch64Info
+ AArch64Desc
+ CodeGen
+ Core
+ MIRParser
+ Target
+ TargetParser
+
+ LINK_LIBS PUBLIC
+ MLIRIR
+ MLIRMIRDialect
+ MLIRTranslateLib
+ )
diff --git a/mlir/lib/Target/MIR/MIRImport.cpp b/mlir/lib/Target/MIR/MIRImport.cpp
new file mode 100644
index 0000000000000..d35f122fe6736
--- /dev/null
+++ b/mlir/lib/Target/MIR/MIRImport.cpp
@@ -0,0 +1,245 @@
+//===- MIRImport.cpp - Translate LLVM .mir into the MIR dialects ----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Registers the `import-mir` translation: parse a pre-register-allocation
+// LLVM MachineIR (.mir) file and build the equivalent `mir` (+ `aarch64_mir`)
+// dialect module. This first cut targets the generic (post-legalize /
+// post-regbankselect) subset: generic G_* opcodes, COPY, and the ABI-boundary
+// physical-register copies. Selected target opcodes are handled in a later
+// step.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/MIR/IR/MIROps.h"
+#include "mlir/IR/Builders.h"
+#include "mlir/IR/BuiltinOps.h"
+#include "mlir/IR/OwningOpRef.h"
+#include "mlir/Tools/mlir-translate/Translation.h"
+
+#include "llvm/CodeGen/MIRParser/MIRParser.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/CodeGenTypes/LowLevelType.h"
+#include "llvm/IR/Module.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace mlir;
+
+namespace {
+
+/// Convert an LLT to the corresponding `mir` dialect type.
+static Type lltToType(llvm::LLT llt, MLIRContext *ctx) {
+ if (llt.isPointer())
+ return mir::PointerType::get(ctx, llt.getAddressSpace(),
+ llt.getSizeInBits());
+ if (llt.isVector()) {
+ auto elt = cast<mir::ScalarType>(lltToType(llt.getElementType(), ctx));
+ return mir::VectorType::get(ctx, llt.getElementCount().getFixedValue(),
+ elt);
+ }
+ // Treat everything else as a scalar of the given bit width.
+ return mir::ScalarType::get(ctx, llt.getSizeInBits());
+}
+
+/// Importer state for a single translation.
+class Importer {
+public:
+ Importer(MLIRContext *ctx, const llvm::MachineFunction &mf)
+ : ctx(ctx), mf(mf), mri(mf.getRegInfo()),
+ tii(mf.getSubtarget().getInstrInfo()),
+ tri(mf.getSubtarget().getRegisterInfo()) {}
+
+ /// Build the body of a mir.func for `mf` into `block`. Returns failure on an
+ /// unsupported construct.
+ LogicalResult run(Block *block) {
+ OpBuilder b(block, block->end());
+ Location loc = UnknownLoc::get(ctx);
+ for (const llvm::MachineBasicBlock &mbb : mf)
+ for (const llvm::MachineInstr &mi : mbb)
+ if (failed(convert(b, loc, mi)))
+ return failure();
+ return success();
+ }
+
+private:
+ Value lookup(llvm::Register reg) { return vregMap.lookup(reg); }
+ void map(llvm::Register reg, Value v) { vregMap[reg] = v; }
+
+ StringRef physRegName(llvm::Register reg) { return tri->getName(reg); }
+
+ LogicalResult convert(OpBuilder &b, Location loc,
+ const llvm::MachineInstr &mi) {
+ unsigned opcode = mi.getOpcode();
+
+ // COPY: virtual<->physical boundary copies and virtual->virtual copies.
+ if (opcode == llvm::TargetOpcode::COPY) {
+ const llvm::MachineOperand &dst = mi.getOperand(0);
+ const llvm::MachineOperand &src = mi.getOperand(1);
+ // vreg = COPY $phys -> mir.copy_from_phys
+ if (dst.getReg().isVirtual() && src.getReg().isPhysical()) {
+ Type ty = lltToType(mri.getType(dst.getReg()), ctx);
+ auto reg = mir::PhysRegAttr::get(ctx, physRegName(src.getReg()));
+ auto op = b.create<mir::CopyFromPhysOp>(loc, ty, reg);
+ map(dst.getReg(), op.getResult());
+ return success();
+ }
+ // $phys = COPY vreg -> mir.copy_to_phys
+ if (dst.getReg().isPhysical() && src.getReg().isVirtual()) {
+ Value v = lookup(src.getReg());
+ if (!v)
+ return failure();
+ auto reg = mir::PhysRegAttr::get(ctx, physRegName(dst.getReg()));
+ b.create<mir::CopyToPhysOp>(loc, v, reg);
+ return success();
+ }
+ // vreg = COPY vreg -> mir.copy
+ if (dst.getReg().isVirtual() && src.getReg().isVirtual()) {
+ Value v = lookup(src.getReg());
+ if (!v)
+ return failure();
+ auto op = b.create<mir::CopyOp>(loc, v.getType(), v);
+ map(dst.getReg(), op.getResult());
+ return success();
+ }
+ return failure();
+ }
+
+ // Generic (pre-isel) opcodes -> mir.g_<lowercase name>.
+ if (llvm::isPreISelGenericOpcode(opcode)) {
+ std::string name = ("mir." + tii->getName(opcode)).str();
+ for (char &c : name)
+ c = llvm::toLower(c);
+
+ SmallVector<Value> operands;
+ SmallVector<Type> resultTypes;
+ SmallVector<llvm::Register> defRegs;
+ for (const llvm::MachineOperand &mo : mi.operands()) {
+ if (!mo.isReg())
+ continue; // immediates handled below
+ if (mo.isImplicit())
+ continue;
+ if (mo.isDef()) {
+ resultTypes.push_back(lltToType(mri.getType(mo.getReg()), ctx));
+ defRegs.push_back(mo.getReg());
+ } else {
+ Value v = lookup(mo.getReg());
+ if (!v)
+ return failure();
+ operands.push_back(v);
+ }
+ }
+
+ OperationState state(loc, name);
+ state.addOperands(operands);
+ state.addTypes(resultTypes);
+ Operation *op = b.create(state);
+ for (auto [reg, res] : llvm::zip(defRegs, op->getResults()))
+ map(reg, res);
+ return success();
+ }
+
+ // Selected target opcodes are handled in a later step.
+ return failure();
+ }
+
+ MLIRContext *ctx;
+ const llvm::MachineFunction &mf;
+ const llvm::MachineRegisterInfo &mri;
+ const llvm::TargetInstrInfo *tii;
+ const llvm::TargetRegisterInfo *tri;
+ DenseMap<llvm::Register, Value> vregMap;
+};
+
+} // namespace
+
+/// Parse a .mir buffer and build a `mir`-dialect module.
+static OwningOpRef<Operation *> translateMIRToModule(llvm::SourceMgr &sourceMgr,
+ MLIRContext *ctx) {
+ // Only AArch64 is needed for these dialects.
+ LLVMInitializeAArch64TargetInfo();
+ LLVMInitializeAArch64Target();
+ LLVMInitializeAArch64TargetMC();
+
+ llvm::LLVMContext llvmCtx;
+ auto buffer = llvm::MemoryBuffer::getMemBufferCopy(
+ sourceMgr.getMemoryBuffer(sourceMgr.getMainFileID())->getBuffer());
+ std::unique_ptr<llvm::MIRParser> mirParser =
+ llvm::createMIRParser(std::move(buffer), llvmCtx);
+ if (!mirParser)
+ return {};
+
+ std::unique_ptr<llvm::Module> module = mirParser->parseIRModule();
+ if (!module) {
+ emitError(UnknownLoc::get(ctx)) << "failed to parse .mir IR module";
+ return {};
+ }
+
+ // Construct an AArch64 TargetMachine (defaulting the triple if absent).
+ llvm::Triple triple = module->getTargetTriple();
+ if (triple.getArch() == llvm::Triple::UnknownArch)
+ triple = llvm::Triple("aarch64-unknown-unknown");
+ std::string err;
+ const llvm::Target *target = llvm::TargetRegistry::lookupTarget(triple, err);
+ if (!target) {
+ emitError(UnknownLoc::get(ctx)) << "no target for triple " << triple.str()
+ << ": " << err;
+ return {};
+ }
+ llvm::TargetOptions options;
+ std::unique_ptr<llvm::TargetMachine> tm(target->createTargetMachine(
+ triple, "generic", "", options, /*RM=*/std::nullopt));
+ module->setDataLayout(tm->createDataLayout());
+
+ llvm::MachineModuleInfo mmi(tm.get());
+ if (mirParser->parseMachineFunctions(*module, mmi)) {
+ emitError(UnknownLoc::get(ctx)) << "failed to parse machine functions";
+ return {};
+ }
+
+ OpBuilder b(ctx);
+ ctx->getOrLoadDialect<mir::MIRDialect>();
+ Location loc = UnknownLoc::get(ctx);
+ OwningOpRef<ModuleOp> mlirModule = ModuleOp::create(loc);
+ b.setInsertionPointToEnd(mlirModule->getBody());
+
+ for (llvm::Function &f : *module) {
+ llvm::MachineFunction *mf = mmi.getMachineFunction(f);
+ if (!mf)
+ continue;
+ auto func = b.create<mir::FuncOp>(loc, f.getName());
+ Block *body = &func.getBody().emplaceBlock();
+ if (failed(Importer(ctx, *mf).run(body))) {
+ emitError(loc) << "unsupported construct while importing @"
+ << f.getName();
+ return {};
+ }
+ }
+
+ return mlirModule.release().getOperation();
+}
+
+namespace mlir {
+void registerFromMIRTranslation() {
+ TranslateToMLIRRegistration registration(
+ "import-mir", "Translate pre-RA LLVM MachineIR (.mir) to the MIR dialects",
+ [](llvm::SourceMgr &sourceMgr,
+ MLIRContext *ctx) -> OwningOpRef<Operation *> {
+ return translateMIRToModule(sourceMgr, ctx);
+ },
+ [](DialectRegistry ®istry) {
+ registry.insert<mir::MIRDialect>();
+ });
+}
+} // namespace mlir
diff --git a/mlir/test/Target/MIR/import-generic.mir b/mlir/test/Target/MIR/import-generic.mir
new file mode 100644
index 0000000000000..3dba91aec56af
--- /dev/null
+++ b/mlir/test/Target/MIR/import-generic.mir
@@ -0,0 +1,28 @@
+# RUN: mlir-translate --import-mir %s | FileCheck %s
+
+# Import pre-RA (post-regbankselect) generic MachineIR into the mir dialect:
+# physical-register COPYs at the ABI boundary become copy_from_phys /
+# copy_to_phys, generic G_* opcodes map to mir.g_*, and LLT scalars become
+# !mir.scalar.
+
+--- |
+ define void @add(i64 %a, i64 %b) { ret void }
+...
+---
+name: add
+body: |
+ bb.0:
+ liveins: $x0, $x1
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s64) = G_ADD %0, %1
+ %3:_(s64) = G_MUL %2, %0
+ $x0 = COPY %3
+...
+
+# CHECK-LABEL: mir.func @add
+# CHECK: %[[A:.*]] = mir.copy_from_phys #mir.physreg<"X0"> -> !mir.scalar<64>
+# CHECK: %[[B:.*]] = mir.copy_from_phys #mir.physreg<"X1"> -> !mir.scalar<64>
+# CHECK: %[[S:.*]] = mir.g_add %[[A]], %[[B]] : (!mir.scalar<64>, !mir.scalar<64>) -> !mir.scalar<64>
+# CHECK: %[[M:.*]] = mir.g_mul %[[S]], %[[A]] : (!mir.scalar<64>, !mir.scalar<64>) -> !mir.scalar<64>
+# CHECK: mir.copy_to_phys %[[M]] : !mir.scalar<64> to #mir.physreg<"X0">
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index 6801dbac1ced9..59563e985a914 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -26,6 +26,7 @@
config.suffixes = [
".td",
".mlir",
+ ".mir",
".toy",
".ll",
".tc",
>From 009e1d53e46faed0984c487e6f61d771033870bf Mon Sep 17 00:00:00 2001
From: makslevental <maksim.levental at gmail.com>
Date: Mon, 24 Aug 2026 11:24:31 -0700
Subject: [PATCH 5/7] [MLIR] Add export-mir translation and .mir round-trip
Adds MIRExport (export-mir): rebuilds an LLVM MachineFunction from a
mir-dialect module and prints it with MIRPrinter. For each mir.func it creates
a stub IR function + MachineFunction, then lowers:
- mir.g_* -> the matching generic opcode (reverse name->opcode map from TII),
allocating generic vregs with the LLT recovered from each value's mir type.
- mir.copy_from_phys / copy_to_phys -> COPY to/from the named physreg (with
block liveins); mir.copy -> vreg COPY.
Together with import-mir this gives a lossless .mir -> mir dialect -> .mir
round trip for the generic (post-regbankselect) subset, verified by
Target/MIR/roundtrip.mir.
---
mlir/include/mlir/InitAllTranslations.h | 2 +
mlir/lib/Target/MIR/CMakeLists.txt | 1 +
mlir/lib/Target/MIR/MIRExport.cpp | 210 ++++++++++++++++++++++++
mlir/test/Target/MIR/roundtrip.mir | 28 ++++
4 files changed, 241 insertions(+)
create mode 100644 mlir/lib/Target/MIR/MIRExport.cpp
create mode 100644 mlir/test/Target/MIR/roundtrip.mir
diff --git a/mlir/include/mlir/InitAllTranslations.h b/mlir/include/mlir/InitAllTranslations.h
index a5c3a77a4c2a0..b28e84118f0d5 100644
--- a/mlir/include/mlir/InitAllTranslations.h
+++ b/mlir/include/mlir/InitAllTranslations.h
@@ -20,6 +20,7 @@ namespace mlir {
void registerFromLLVMIRTranslation();
void registerFromMIRTranslation();
+void registerToMIRTranslation();
void registerFromSPIRVTranslation();
void registerFromWasmTranslation();
void registerToCppTranslation();
@@ -37,6 +38,7 @@ inline void registerAllTranslations() {
static bool initOnce = []() {
registerFromLLVMIRTranslation();
registerFromMIRTranslation();
+ registerToMIRTranslation();
registerFromSPIRVTranslation();
registerIRDLToCppTranslation();
registerFromWasmTranslation();
diff --git a/mlir/lib/Target/MIR/CMakeLists.txt b/mlir/lib/Target/MIR/CMakeLists.txt
index 7e85bfc9fcc6e..4f653d5e6f33c 100644
--- a/mlir/lib/Target/MIR/CMakeLists.txt
+++ b/mlir/lib/Target/MIR/CMakeLists.txt
@@ -1,5 +1,6 @@
add_mlir_translation_library(MLIRTargetMIRImport
MIRImport.cpp
+ MIRExport.cpp
ADDITIONAL_HEADER_DIRS
${MLIR_MAIN_INCLUDE_DIR}/mlir/Target/MIR
diff --git a/mlir/lib/Target/MIR/MIRExport.cpp b/mlir/lib/Target/MIR/MIRExport.cpp
new file mode 100644
index 0000000000000..226ca8849ccd7
--- /dev/null
+++ b/mlir/lib/Target/MIR/MIRExport.cpp
@@ -0,0 +1,210 @@
+//===- MIRExport.cpp - Translate the MIR dialects back to .mir ------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Registers the `export-mir` translation: rebuild an LLVM MachineFunction from
+// a `mir`-dialect module and print it as .mir. Covers the generic subset
+// (generic G_* opcodes, COPY, and ABI-boundary physical-register copies),
+// enabling a .mir -> dialect -> .mir round trip.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/MIR/IR/MIROps.h"
+#include "mlir/IR/BuiltinOps.h"
+#include "mlir/Tools/mlir-translate/Translation.h"
+
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MIRPrinter.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/CodeGenTypes/LowLevelType.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Module.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace mlir;
+
+namespace {
+
+/// Convert a `mir` dialect type to an LLT.
+static llvm::LLT typeToLLT(Type t) {
+ if (auto s = dyn_cast<mir::ScalarType>(t))
+ return llvm::LLT::scalar(s.getWidth());
+ if (auto p = dyn_cast<mir::PointerType>(t))
+ return llvm::LLT::pointer(p.getAddressSpace(), p.getSizeInBits());
+ if (auto v = dyn_cast<mir::VectorType>(t))
+ return llvm::LLT::fixed_vector(v.getNumElements(),
+ llvm::LLT::scalar(v.getElementType().getWidth()));
+ return llvm::LLT();
+}
+
+/// Build a MachineFunction body from a mir.func and print nothing; the caller
+/// prints via MIRPrinter.
+class Exporter {
+public:
+ Exporter(llvm::MachineFunction &mf)
+ : mf(mf), mri(mf.getRegInfo()),
+ tii(mf.getSubtarget().getInstrInfo()),
+ tri(mf.getSubtarget().getRegisterInfo()) {
+ // Reverse map: opcode name -> opcode number.
+ for (unsigned op = 0, e = tii->getNumOpcodes(); op != e; ++op)
+ nameToOpcode[tii->getName(op)] = op;
+ }
+
+ LogicalResult run(mir::FuncOp func) {
+ mbb = mf.CreateMachineBasicBlock();
+ mf.push_back(mbb);
+ for (Operation &op : func.getBody().front())
+ if (failed(convert(&op)))
+ return failure();
+ return success();
+ }
+
+private:
+ llvm::Register physRegByName(StringRef name) {
+ for (unsigned r = 1, e = tri->getNumRegs(); r != e; ++r)
+ if (name.equals_insensitive(tri->getName(r)))
+ return r;
+ return llvm::Register();
+ }
+
+ LogicalResult convert(Operation *op) {
+ llvm::DebugLoc dl;
+ if (auto fromPhys = dyn_cast<mir::CopyFromPhysOp>(op)) {
+ llvm::Register phys = physRegByName(fromPhys.getReg().getName());
+ if (!phys)
+ return failure();
+ llvm::Register dst =
+ mri.createGenericVirtualRegister(typeToLLT(fromPhys.getType()));
+ mbb->addLiveIn(phys);
+ llvm::BuildMI(*mbb, mbb->end(), dl, tii->get(llvm::TargetOpcode::COPY),
+ dst)
+ .addReg(phys);
+ valMap[fromPhys.getResult()] = dst;
+ return success();
+ }
+ if (auto toPhys = dyn_cast<mir::CopyToPhysOp>(op)) {
+ llvm::Register phys = physRegByName(toPhys.getReg().getName());
+ llvm::Register src = valMap.lookup(toPhys.getSrc());
+ if (!phys || !src)
+ return failure();
+ llvm::BuildMI(*mbb, mbb->end(), dl, tii->get(llvm::TargetOpcode::COPY),
+ phys)
+ .addReg(src);
+ return success();
+ }
+ if (auto copy = dyn_cast<mir::CopyOp>(op)) {
+ llvm::Register src = valMap.lookup(copy.getSrc());
+ if (!src)
+ return failure();
+ llvm::Register dst =
+ mri.createGenericVirtualRegister(typeToLLT(copy.getType()));
+ llvm::BuildMI(*mbb, mbb->end(), dl, tii->get(llvm::TargetOpcode::COPY),
+ dst)
+ .addReg(src);
+ valMap[copy.getResult()] = dst;
+ return success();
+ }
+
+ // Generic mir.g_* op -> corresponding generic opcode.
+ StringRef opName = op->getName().stripDialect();
+ if (opName.starts_with("g_")) {
+ std::string upper = opName.upper(); // g_add -> G_ADD
+ auto it = nameToOpcode.find(upper);
+ if (it == nameToOpcode.end())
+ return failure();
+ auto mib = llvm::BuildMI(*mbb, mbb->end(), dl, tii->get(it->second));
+ for (Value res : op->getResults()) {
+ llvm::Register dst =
+ mri.createGenericVirtualRegister(typeToLLT(res.getType()));
+ mib.addDef(dst);
+ valMap[res] = dst;
+ }
+ for (Value operand : op->getOperands()) {
+ llvm::Register src = valMap.lookup(operand);
+ if (!src)
+ return failure();
+ mib.addUse(src);
+ }
+ return success();
+ }
+
+ return failure();
+ }
+
+ llvm::MachineFunction &mf;
+ llvm::MachineRegisterInfo &mri;
+ const llvm::TargetInstrInfo *tii;
+ const llvm::TargetRegisterInfo *tri;
+ llvm::MachineBasicBlock *mbb = nullptr;
+ llvm::StringMap<unsigned> nameToOpcode;
+ DenseMap<Value, llvm::Register> valMap;
+};
+
+static LogicalResult translateModuleToMIR(Operation *op,
+ llvm::raw_ostream &output) {
+ auto module = dyn_cast<ModuleOp>(op);
+ if (!module)
+ return op->emitError("expected a module");
+
+ LLVMInitializeAArch64TargetInfo();
+ LLVMInitializeAArch64Target();
+ LLVMInitializeAArch64TargetMC();
+
+ llvm::LLVMContext llvmCtx;
+ auto llvmModule = std::make_unique<llvm::Module>("mir", llvmCtx);
+ llvm::Triple triple("aarch64-unknown-unknown");
+ llvmModule->setTargetTriple(triple);
+
+ std::string err;
+ const llvm::Target *target = llvm::TargetRegistry::lookupTarget(triple, err);
+ if (!target)
+ return module.emitError("no AArch64 target: ") << err;
+ llvm::TargetOptions options;
+ std::unique_ptr<llvm::TargetMachine> tm(target->createTargetMachine(
+ triple, "generic", "", options, /*RM=*/std::nullopt));
+ llvmModule->setDataLayout(tm->createDataLayout());
+
+ llvm::MachineModuleInfo mmi(tm.get());
+
+ // Create an empty IR function + a MachineFunction for each mir.func.
+ for (auto func : module.getOps<mir::FuncOp>()) {
+ auto *fnTy = llvm::FunctionType::get(llvm::Type::getVoidTy(llvmCtx), false);
+ auto *f = llvm::Function::Create(fnTy, llvm::GlobalValue::ExternalLinkage,
+ func.getSymName(), llvmModule.get());
+ llvm::BasicBlock *bb = llvm::BasicBlock::Create(llvmCtx, "entry", f);
+ llvm::IRBuilder<>(bb).CreateRetVoid();
+
+ llvm::MachineFunction &mf = mmi.getOrCreateMachineFunction(*f);
+ if (failed(Exporter(mf).run(func)))
+ return func.emitError("unsupported construct while exporting");
+ }
+
+ // Print the IR module then each machine function.
+ llvm::printMIR(output, *llvmModule);
+ for (llvm::Function &f : *llvmModule)
+ if (llvm::MachineFunction *mf = mmi.getMachineFunction(f))
+ llvm::printMIR(output, mmi, *mf);
+
+ return success();
+}
+
+} // namespace
+
+namespace mlir {
+void registerToMIRTranslation() {
+ TranslateFromMLIRRegistration registration(
+ "export-mir", "Translate the MIR dialects to LLVM MachineIR (.mir)",
+ translateModuleToMIR,
+ [](DialectRegistry ®istry) { registry.insert<mir::MIRDialect>(); });
+}
+} // namespace mlir
diff --git a/mlir/test/Target/MIR/roundtrip.mir b/mlir/test/Target/MIR/roundtrip.mir
new file mode 100644
index 0000000000000..a1dec8b128a14
--- /dev/null
+++ b/mlir/test/Target/MIR/roundtrip.mir
@@ -0,0 +1,28 @@
+# RUN: mlir-translate --import-mir %s | mlir-translate --export-mir | FileCheck %s
+
+# Full round trip: .mir -> mir dialect -> .mir. The regenerated machine
+# function must reproduce the generic opcodes, LLT types, and ABI-boundary
+# physical-register copies of the input.
+
+--- |
+ define void @add(i64 %a, i64 %b) { ret void }
+...
+---
+name: add
+body: |
+ bb.0:
+ liveins: $x0, $x1
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s64) = G_ADD %0, %1
+ %3:_(s64) = G_MUL %2, %0
+ $x0 = COPY %3
+...
+
+# CHECK-LABEL: name:{{.*}}add
+# CHECK: liveins: $x0, $x1
+# CHECK: %0:_(s64) = COPY $x0
+# CHECK: %1:_(s64) = COPY $x1
+# CHECK: %2:_(s64) = G_ADD %0, %1
+# CHECK: %3:_(s64) = G_MUL %2, %0
+# CHECK: $x0 = COPY %3
>From 7d4844056df54285a8e87ad3d071ddcb4dceb8d1 Mon Sep 17 00:00:00 2001
From: makslevental <maksim.levental at gmail.com>
Date: Mon, 24 Aug 2026 11:29:33 -0700
Subject: [PATCH 6/7] MLIR: Extend import-mir to selected AArch64 target
opcodes
Completes the translation layer import side for selected (post-isel) MIR:
- Adds a --mir-emit-lowering mode to -gen-mir-target-ops that emits a C++
opcode-record-name -> collapsed-mnemonic table; the checked-in
AArch64MIRLowering.inc (7484 entries) is generated from it.
- MIRImport uses that table to map a concrete target opcode (e.g. ADDXrs) to
its aarch64_mir op (aarch64_mir.add), attaching a variant attribute naming
the concrete opcode so export can recover it.
- Register-class virtual registers (which carry no LLT post-select) are typed
from their register-class size.
Verified by Target/MIR/import-selected.mir. All seven MIR lit tests pass.
---
mlir/lib/Target/MIR/AArch64MIRLowering.inc | 7485 ++++++++++++++++++++
mlir/lib/Target/MIR/CMakeLists.txt | 1 +
mlir/lib/Target/MIR/MIRImport.cpp | 69 +-
mlir/test/Target/MIR/import-selected.mir | 28 +
mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp | 28 +-
5 files changed, 7602 insertions(+), 9 deletions(-)
create mode 100644 mlir/lib/Target/MIR/AArch64MIRLowering.inc
create mode 100644 mlir/test/Target/MIR/import-selected.mir
diff --git a/mlir/lib/Target/MIR/AArch64MIRLowering.inc b/mlir/lib/Target/MIR/AArch64MIRLowering.inc
new file mode 100644
index 0000000000000..644bd1f8689b3
--- /dev/null
+++ b/mlir/lib/Target/MIR/AArch64MIRLowering.inc
@@ -0,0 +1,7485 @@
+{"ABSWr", "abs"},
+{"ABSXr", "abs"},
+{"ABS_ZPmZ_B", "abs"},
+{"ABS_ZPmZ_D", "abs"},
+{"ABS_ZPmZ_H", "abs"},
+{"ABS_ZPmZ_S", "abs"},
+{"ABS_ZPzZ_B", "abs"},
+{"ABS_ZPzZ_D", "abs"},
+{"ABS_ZPzZ_H", "abs"},
+{"ABS_ZPzZ_S", "abs"},
+{"ABSv1i64", "abs"},
+{"ABSv2i32", "abs"},
+{"ABSv2i64", "abs"},
+{"ABSv4i16", "abs"},
+{"ABSv4i32", "abs"},
+{"ABSv8i8", "abs"},
+{"ABSv8i16", "abs"},
+{"ABSv16i8", "abs"},
+{"ADCLB_ZZZ_D", "adclb"},
+{"ADCLB_ZZZ_S", "adclb"},
+{"ADCLT_ZZZ_D", "adclt"},
+{"ADCLT_ZZZ_S", "adclt"},
+{"ADCSWr", "adcs"},
+{"ADCSXr", "adcs"},
+{"ADCWr", "adc"},
+{"ADCXr", "adc"},
+{"ADDG", "addg"},
+{"ADDHA_MPPZ_D", "addha"},
+{"ADDHA_MPPZ_S", "addha"},
+{"ADDHNB_ZZZ_B", "addhnb"},
+{"ADDHNB_ZZZ_H", "addhnb"},
+{"ADDHNB_ZZZ_S", "addhnb"},
+{"ADDHNT_ZZZ_B", "addhnt"},
+{"ADDHNT_ZZZ_H", "addhnt"},
+{"ADDHNT_ZZZ_S", "addhnt"},
+{"ADDHNv2i64_v2i32", "addhn"},
+{"ADDHNv4i32_v4i16", "addhn"},
+{"ADDHNv8i16_v8i8", "addhn"},
+{"ADDHNv2i64_v4i32", "addhn2"},
+{"ADDHNv4i32_v8i16", "addhn2"},
+{"ADDHNv8i16_v16i8", "addhn2"},
+{"ADDPL_XXI", "addpl"},
+{"ADDPT_shift", "addpt"},
+{"ADD_ZPmZ_CPA", "addpt"},
+{"ADD_ZZZ_CPA", "addpt"},
+{"ADDP_ZPmZ_B", "addp"},
+{"ADDP_ZPmZ_D", "addp"},
+{"ADDP_ZPmZ_H", "addp"},
+{"ADDP_ZPmZ_S", "addp"},
+{"ADDPv2i32", "addp"},
+{"ADDPv2i64", "addp"},
+{"ADDPv2i64p", "addp"},
+{"ADDPv4i16", "addp"},
+{"ADDPv4i32", "addp"},
+{"ADDPv8i8", "addp"},
+{"ADDPv8i16", "addp"},
+{"ADDPv16i8", "addp"},
+{"ADDQP_ZZZ_B", "addqp"},
+{"ADDQP_ZZZ_D", "addqp"},
+{"ADDQP_ZZZ_H", "addqp"},
+{"ADDQP_ZZZ_S", "addqp"},
+{"ADDQV_VPZ_B", "addqv"},
+{"ADDQV_VPZ_D", "addqv"},
+{"ADDQV_VPZ_H", "addqv"},
+{"ADDQV_VPZ_S", "addqv"},
+{"ADDSPL_XXI", "addspl"},
+{"ADDSUBP_ZZZ_B", "addsubp"},
+{"ADDSUBP_ZZZ_D", "addsubp"},
+{"ADDSUBP_ZZZ_H", "addsubp"},
+{"ADDSUBP_ZZZ_S", "addsubp"},
+{"ADDSVL_XXI", "addsvl"},
+{"ADDSWri", "adds"},
+{"ADDSWrs", "adds"},
+{"ADDSWrx", "adds"},
+{"ADDSXri", "adds"},
+{"ADDSXrs", "adds"},
+{"ADDSXrx", "adds"},
+{"ADDSXrx64", "adds"},
+{"ADDVA_MPPZ_D", "addva"},
+{"ADDVA_MPPZ_S", "addva"},
+{"ADDVL_XXI", "addvl"},
+{"ADDVv4i16v", "addv"},
+{"ADDVv4i32v", "addv"},
+{"ADDVv8i8v", "addv"},
+{"ADDVv8i16v", "addv"},
+{"ADDVv16i8v", "addv"},
+{"ADDWri", "add"},
+{"ADDWrs", "add"},
+{"ADDWrx", "add"},
+{"ADDXri", "add"},
+{"ADDXrs", "add"},
+{"ADDXrx", "add"},
+{"ADDXrx64", "add"},
+{"ADD_VG2_2ZZ_B", "add"},
+{"ADD_VG2_2ZZ_D", "add"},
+{"ADD_VG2_2ZZ_H", "add"},
+{"ADD_VG2_2ZZ_S", "add"},
+{"ADD_VG2_M2Z2Z_D", "add"},
+{"ADD_VG2_M2Z2Z_S", "add"},
+{"ADD_VG2_M2ZZ_D", "add"},
+{"ADD_VG2_M2ZZ_S", "add"},
+{"ADD_VG2_M2Z_D", "add"},
+{"ADD_VG2_M2Z_S", "add"},
+{"ADD_VG4_4ZZ_B", "add"},
+{"ADD_VG4_4ZZ_D", "add"},
+{"ADD_VG4_4ZZ_H", "add"},
+{"ADD_VG4_4ZZ_S", "add"},
+{"ADD_VG4_M4Z4Z_D", "add"},
+{"ADD_VG4_M4Z4Z_S", "add"},
+{"ADD_VG4_M4ZZ_D", "add"},
+{"ADD_VG4_M4ZZ_S", "add"},
+{"ADD_VG4_M4Z_D", "add"},
+{"ADD_VG4_M4Z_S", "add"},
+{"ADD_ZI_B", "add"},
+{"ADD_ZI_D", "add"},
+{"ADD_ZI_H", "add"},
+{"ADD_ZI_S", "add"},
+{"ADD_ZPmZ_B", "add"},
+{"ADD_ZPmZ_D", "add"},
+{"ADD_ZPmZ_H", "add"},
+{"ADD_ZPmZ_S", "add"},
+{"ADD_ZZZ_B", "add"},
+{"ADD_ZZZ_D", "add"},
+{"ADD_ZZZ_H", "add"},
+{"ADD_ZZZ_S", "add"},
+{"ADDv1i64", "add"},
+{"ADDv2i32", "add"},
+{"ADDv2i64", "add"},
+{"ADDv4i16", "add"},
+{"ADDv4i32", "add"},
+{"ADDv8i8", "add"},
+{"ADDv8i16", "add"},
+{"ADDv16i8", "add"},
+{"ADR", "adr"},
+{"ADR_LSL_ZZZ_D_0", "adr"},
+{"ADR_LSL_ZZZ_D_1", "adr"},
+{"ADR_LSL_ZZZ_D_2", "adr"},
+{"ADR_LSL_ZZZ_D_3", "adr"},
+{"ADR_LSL_ZZZ_S_0", "adr"},
+{"ADR_LSL_ZZZ_S_1", "adr"},
+{"ADR_LSL_ZZZ_S_2", "adr"},
+{"ADR_LSL_ZZZ_S_3", "adr"},
+{"ADR_SXTW_ZZZ_D_0", "adr"},
+{"ADR_SXTW_ZZZ_D_1", "adr"},
+{"ADR_SXTW_ZZZ_D_2", "adr"},
+{"ADR_SXTW_ZZZ_D_3", "adr"},
+{"ADR_UXTW_ZZZ_D_0", "adr"},
+{"ADR_UXTW_ZZZ_D_1", "adr"},
+{"ADR_UXTW_ZZZ_D_2", "adr"},
+{"ADR_UXTW_ZZZ_D_3", "adr"},
+{"ADRP", "adrp"},
+{"AESDIMC_2ZZI_B", "aesdimc"},
+{"AESDIMC_4ZZI_B", "aesdimc"},
+{"AESD_2ZZI_B", "aesd"},
+{"AESD_4ZZI_B", "aesd"},
+{"AESD_ZZZ_B", "aesd"},
+{"AESDrr", "aesd"},
+{"AESEMC_2ZZI_B", "aesemc"},
+{"AESEMC_4ZZI_B", "aesemc"},
+{"AESE_2ZZI_B", "aese"},
+{"AESE_4ZZI_B", "aese"},
+{"AESE_ZZZ_B", "aese"},
+{"AESErr", "aese"},
+{"AESIMC_ZZ_B", "aesimc"},
+{"AESIMCrr", "aesimc"},
+{"AESMC_ZZ_B", "aesmc"},
+{"AESMCrr", "aesmc"},
+{"ANDQV_VPZ_B", "andqv"},
+{"ANDQV_VPZ_D", "andqv"},
+{"ANDQV_VPZ_H", "andqv"},
+{"ANDQV_VPZ_S", "andqv"},
+{"ANDSWri", "ands"},
+{"ANDSWrs", "ands"},
+{"ANDSXri", "ands"},
+{"ANDSXrs", "ands"},
+{"ANDS_PPzPP", "ands"},
+{"ANDV_VPZ_B", "andv"},
+{"ANDV_VPZ_D", "andv"},
+{"ANDV_VPZ_H", "andv"},
+{"ANDV_VPZ_S", "andv"},
+{"ANDWri", "and"},
+{"ANDWrs", "and"},
+{"ANDXri", "and"},
+{"ANDXrs", "and"},
+{"AND_PPzPP", "and"},
+{"AND_ZI", "and"},
+{"AND_ZPmZ_B", "and"},
+{"AND_ZPmZ_D", "and"},
+{"AND_ZPmZ_H", "and"},
+{"AND_ZPmZ_S", "and"},
+{"AND_ZZZ", "and"},
+{"ANDv8i8", "and"},
+{"ANDv16i8", "and"},
+{"ASRD_ZPmI_B", "asrd"},
+{"ASRD_ZPmI_D", "asrd"},
+{"ASRD_ZPmI_H", "asrd"},
+{"ASRD_ZPmI_S", "asrd"},
+{"ASRR_ZPmZ_B", "asrr"},
+{"ASRR_ZPmZ_D", "asrr"},
+{"ASRR_ZPmZ_H", "asrr"},
+{"ASRR_ZPmZ_S", "asrr"},
+{"ASRVWr", "asr"},
+{"ASRVXr", "asr"},
+{"ASR_WIDE_ZPmZ_B", "asr"},
+{"ASR_WIDE_ZPmZ_H", "asr"},
+{"ASR_WIDE_ZPmZ_S", "asr"},
+{"ASR_WIDE_ZZZ_B", "asr"},
+{"ASR_WIDE_ZZZ_H", "asr"},
+{"ASR_WIDE_ZZZ_S", "asr"},
+{"ASR_ZPmI_B", "asr"},
+{"ASR_ZPmI_D", "asr"},
+{"ASR_ZPmI_H", "asr"},
+{"ASR_ZPmI_S", "asr"},
+{"ASR_ZPmZ_B", "asr"},
+{"ASR_ZPmZ_D", "asr"},
+{"ASR_ZPmZ_H", "asr"},
+{"ASR_ZPmZ_S", "asr"},
+{"ASR_ZZI_B", "asr"},
+{"ASR_ZZI_D", "asr"},
+{"ASR_ZZI_H", "asr"},
+{"ASR_ZZI_S", "asr"},
+{"AUTDA", "autda"},
+{"AUTDB", "autdb"},
+{"AUTDZA", "autdza"},
+{"AUTDZB", "autdzb"},
+{"AUTIA", "autia"},
+{"AUTIA1716", "hint"},
+{"AUTIASP", "hint"},
+{"AUTIAZ", "hint"},
+{"AUTIB1716", "hint"},
+{"AUTIBSP", "hint"},
+{"AUTIBZ", "hint"},
+{"CHKFEAT", "hint"},
+{"HINT", "hint"},
+{"NOP", "hint"},
+{"PACIA1716", "hint"},
+{"PACIASP", "hint"},
+{"PACIAZ", "hint"},
+{"PACIB1716", "hint"},
+{"PACIBSP", "hint"},
+{"PACIBZ", "hint"},
+{"PACM", "hint"},
+{"XPACLRI", "hint"},
+{"AUTIA171615", "autia171615"},
+{"AUTIASPPCi", "autiasppc"},
+{"AUTIASPPCr", "autiasppcr"},
+{"AUTIB", "autib"},
+{"AUTIB171615", "autib171615"},
+{"AUTIBSPPCi", "autibsppc"},
+{"AUTIBSPPCr", "autibsppcr"},
+{"AUTIZA", "autiza"},
+{"AUTIZB", "autizb"},
+{"AXFLAG", "axflag"},
+{"B", "b"},
+{"BCAX", "bcax"},
+{"BCAX_ZZZZ", "bcax"},
+{"BCcc", "bc_cond"},
+{"BDEP_ZZZ_B", "bdep"},
+{"BDEP_ZZZ_D", "bdep"},
+{"BDEP_ZZZ_H", "bdep"},
+{"BDEP_ZZZ_S", "bdep"},
+{"BEXT_ZZZ_B", "bext"},
+{"BEXT_ZZZ_D", "bext"},
+{"BEXT_ZZZ_H", "bext"},
+{"BEXT_ZZZ_S", "bext"},
+{"BF1CVTL", "bf1cvtl"},
+{"BF1CVTL_2ZZ_BtoH", "bf1cvtl"},
+{"BF1CVTL2", "bf1cvtl2"},
+{"BF1CVTLT_ZZ_BtoH", "bf1cvtlt"},
+{"BF1CVT_2ZZ_BtoH", "bf1cvt"},
+{"BF1CVT_ZZ_BtoH", "bf1cvt"},
+{"BF2CVTL", "bf2cvtl"},
+{"BF2CVTL_2ZZ_BtoH", "bf2cvtl"},
+{"BF2CVTL2", "bf2cvtl2"},
+{"BF2CVTLT_ZZ_BtoH", "bf2cvtlt"},
+{"BF2CVT_2ZZ_BtoH", "bf2cvt"},
+{"BF2CVT_ZZ_BtoH", "bf2cvt"},
+{"BF16DOTlanev4bf16", "bfdot"},
+{"BF16DOTlanev8bf16", "bfdot"},
+{"BFDOT_VG2_M2Z2Z_HtoS", "bfdot"},
+{"BFDOT_VG2_M2ZZI_HtoS", "bfdot"},
+{"BFDOT_VG2_M2ZZ_HtoS", "bfdot"},
+{"BFDOT_VG4_M4Z4Z_HtoS", "bfdot"},
+{"BFDOT_VG4_M4ZZI_HtoS", "bfdot"},
+{"BFDOT_VG4_M4ZZ_HtoS", "bfdot"},
+{"BFDOT_ZZI", "bfdot"},
+{"BFDOT_ZZZ", "bfdot"},
+{"BFDOTv4bf16", "bfdot"},
+{"BFDOTv8bf16", "bfdot"},
+{"BFADD_VG2_M2Z_H", "bfadd"},
+{"BFADD_VG4_M4Z_H", "bfadd"},
+{"BFADD_ZPmZ", "bfadd"},
+{"BFADD_ZZZ", "bfadd"},
+{"BFCLAMP_VG2_2ZZZ_H", "bfclamp"},
+{"BFCLAMP_VG4_4ZZZ_H", "bfclamp"},
+{"BFCLAMP_ZZZ", "bfclamp"},
+{"BFCVT", "bfcvt"},
+{"BFCVT_Z2Z_HtoB", "bfcvt"},
+{"BFCVT_Z2Z_StoH", "bfcvt"},
+{"BFCVT_ZPmZ", "bfcvt"},
+{"BFCVT_ZPzZ_StoH", "bfcvt"},
+{"BFCVTN", "bfcvtn"},
+{"BFCVTN_Z2Z_HtoB", "bfcvtn"},
+{"BFCVTN_Z2Z_StoH", "bfcvtn"},
+{"BFCVTN2", "bfcvtn2"},
+{"BFCVTNT_ZPmZ", "bfcvtnt"},
+{"BFCVTNT_ZPzZ_StoH", "bfcvtnt"},
+{"BFMAXNM_VG2_2Z2Z_H", "bfmaxnm"},
+{"BFMAXNM_VG2_2ZZ_H", "bfmaxnm"},
+{"BFMAXNM_VG4_4Z2Z_H", "bfmaxnm"},
+{"BFMAXNM_VG4_4ZZ_H", "bfmaxnm"},
+{"BFMAXNM_ZPmZ", "bfmaxnm"},
+{"BFMAX_VG2_2Z2Z_H", "bfmax"},
+{"BFMAX_VG2_2ZZ_H", "bfmax"},
+{"BFMAX_VG4_4Z2Z_H", "bfmax"},
+{"BFMAX_VG4_4ZZ_H", "bfmax"},
+{"BFMAX_ZPmZ", "bfmax"},
+{"BFMINNM_VG2_2Z2Z_H", "bfminnm"},
+{"BFMINNM_VG2_2ZZ_H", "bfminnm"},
+{"BFMINNM_VG4_4Z2Z_H", "bfminnm"},
+{"BFMINNM_VG4_4ZZ_H", "bfminnm"},
+{"BFMINNM_ZPmZ", "bfminnm"},
+{"BFMIN_VG2_2Z2Z_H", "bfmin"},
+{"BFMIN_VG2_2ZZ_H", "bfmin"},
+{"BFMIN_VG4_4Z2Z_H", "bfmin"},
+{"BFMIN_VG4_4ZZ_H", "bfmin"},
+{"BFMIN_ZPmZ", "bfmin"},
+{"BFMLALB", "bfmlalb"},
+{"BFMLALBIdx", "bfmlalb"},
+{"BFMLALB_ZZZ", "bfmlalb"},
+{"BFMLALB_ZZZI", "bfmlalb"},
+{"BFMLALT", "bfmlalt"},
+{"BFMLALTIdx", "bfmlalt"},
+{"BFMLALT_ZZZ", "bfmlalt"},
+{"BFMLALT_ZZZI", "bfmlalt"},
+{"BFMLAL_MZZI_HtoS", "bfmlal"},
+{"BFMLAL_MZZ_HtoS", "bfmlal"},
+{"BFMLAL_VG2_M2Z2Z_HtoS", "bfmlal"},
+{"BFMLAL_VG2_M2ZZI_HtoS", "bfmlal"},
+{"BFMLAL_VG2_M2ZZ_HtoS", "bfmlal"},
+{"BFMLAL_VG4_M4Z4Z_HtoS", "bfmlal"},
+{"BFMLAL_VG4_M4ZZI_HtoS", "bfmlal"},
+{"BFMLAL_VG4_M4ZZ_HtoS", "bfmlal"},
+{"BFMLA_VG2_M2Z2Z", "bfmla"},
+{"BFMLA_VG2_M2ZZ", "bfmla"},
+{"BFMLA_VG2_M2ZZI", "bfmla"},
+{"BFMLA_VG4_M4Z4Z", "bfmla"},
+{"BFMLA_VG4_M4ZZ", "bfmla"},
+{"BFMLA_VG4_M4ZZI", "bfmla"},
+{"BFMLA_ZPmZZ", "bfmla"},
+{"BFMLA_ZZZI", "bfmla"},
+{"BFMLSLB_ZZZI_S", "bfmlslb"},
+{"BFMLSLB_ZZZ_S", "bfmlslb"},
+{"BFMLSLT_ZZZI_S", "bfmlslt"},
+{"BFMLSLT_ZZZ_S", "bfmlslt"},
+{"BFMLSL_MZZI_HtoS", "bfmlsl"},
+{"BFMLSL_MZZ_HtoS", "bfmlsl"},
+{"BFMLSL_VG2_M2Z2Z_HtoS", "bfmlsl"},
+{"BFMLSL_VG2_M2ZZI_HtoS", "bfmlsl"},
+{"BFMLSL_VG2_M2ZZ_HtoS", "bfmlsl"},
+{"BFMLSL_VG4_M4Z4Z_HtoS", "bfmlsl"},
+{"BFMLSL_VG4_M4ZZI_HtoS", "bfmlsl"},
+{"BFMLSL_VG4_M4ZZ_HtoS", "bfmlsl"},
+{"BFMLS_VG2_M2Z2Z", "bfmls"},
+{"BFMLS_VG2_M2ZZ", "bfmls"},
+{"BFMLS_VG2_M2ZZI", "bfmls"},
+{"BFMLS_VG4_M4Z4Z", "bfmls"},
+{"BFMLS_VG4_M4ZZ", "bfmls"},
+{"BFMLS_VG4_M4ZZI", "bfmls"},
+{"BFMLS_ZPmZZ", "bfmls"},
+{"BFMLS_ZZZI", "bfmls"},
+{"BFMMLA", "bfmmla"},
+{"BFMMLA_ZZZ_H", "bfmmla"},
+{"BFMMLA_ZZZ_HtoS", "bfmmla"},
+{"BFMOP4A_M2Z2Z_H", "bfmop4a"},
+{"BFMOP4A_M2Z2Z_S", "bfmop4a"},
+{"BFMOP4A_M2ZZ_H", "bfmop4a"},
+{"BFMOP4A_M2ZZ_S", "bfmop4a"},
+{"BFMOP4A_MZ2Z_H", "bfmop4a"},
+{"BFMOP4A_MZ2Z_S", "bfmop4a"},
+{"BFMOP4A_MZZ_H", "bfmop4a"},
+{"BFMOP4A_MZZ_S", "bfmop4a"},
+{"BFMOP4S_M2Z2Z_H", "bfmop4s"},
+{"BFMOP4S_M2Z2Z_S", "bfmop4s"},
+{"BFMOP4S_M2ZZ_H", "bfmop4s"},
+{"BFMOP4S_M2ZZ_S", "bfmop4s"},
+{"BFMOP4S_MZ2Z_H", "bfmop4s"},
+{"BFMOP4S_MZ2Z_S", "bfmop4s"},
+{"BFMOP4S_MZZ_H", "bfmop4s"},
+{"BFMOP4S_MZZ_S", "bfmop4s"},
+{"BFMOPA_MPPZZ", "bfmopa"},
+{"BFMOPA_MPPZZ_H", "bfmopa"},
+{"BFMOPS_MPPZZ", "bfmops"},
+{"BFMOPS_MPPZZ_H", "bfmops"},
+{"BFMUL_2Z2Z", "bfmul"},
+{"BFMUL_2ZZ", "bfmul"},
+{"BFMUL_4Z4Z", "bfmul"},
+{"BFMUL_4ZZ", "bfmul"},
+{"BFMUL_ZPmZ", "bfmul"},
+{"BFMUL_ZZZ", "bfmul"},
+{"BFMUL_ZZZI", "bfmul"},
+{"BFMWri", "bfm"},
+{"BFMXri", "bfm"},
+{"BFSCALE_2Z2Z", "bfscale"},
+{"BFSCALE_2ZZ", "bfscale"},
+{"BFSCALE_4Z4Z", "bfscale"},
+{"BFSCALE_4ZZ", "bfscale"},
+{"BFSCALE_ZPmZ", "bfscale"},
+{"BFSUB_VG2_M2Z_H", "bfsub"},
+{"BFSUB_VG4_M4Z_H", "bfsub"},
+{"BFSUB_ZPmZ", "bfsub"},
+{"BFSUB_ZZZ", "bfsub"},
+{"BFTMOPA_M2ZZZI_HtoH", "bftmopa"},
+{"BFTMOPA_M2ZZZI_HtoS", "bftmopa"},
+{"BFVDOT_VG2_M2ZZI_HtoS", "bfvdot"},
+{"BGRP_ZZZ_B", "bgrp"},
+{"BGRP_ZZZ_D", "bgrp"},
+{"BGRP_ZZZ_H", "bgrp"},
+{"BGRP_ZZZ_S", "bgrp"},
+{"BICSWrs", "bics"},
+{"BICSXrs", "bics"},
+{"BICS_PPzPP", "bics"},
+{"BICWrs", "bic"},
+{"BICXrs", "bic"},
+{"BIC_PPzPP", "bic"},
+{"BIC_ZPmZ_B", "bic"},
+{"BIC_ZPmZ_D", "bic"},
+{"BIC_ZPmZ_H", "bic"},
+{"BIC_ZPmZ_S", "bic"},
+{"BIC_ZZZ", "bic"},
+{"BICv2i32", "bic"},
+{"BICv4i16", "bic"},
+{"BICv4i32", "bic"},
+{"BICv8i8", "bic"},
+{"BICv8i16", "bic"},
+{"BICv16i8", "bic"},
+{"BIFv8i8", "bif"},
+{"BIFv16i8", "bif"},
+{"BITv8i8", "bit"},
+{"BITv16i8", "bit"},
+{"BL", "bl"},
+{"BLR", "blr"},
+{"BLRAA", "blraa"},
+{"BLRAAZ", "blraaz"},
+{"BLRAB", "blrab"},
+{"BLRABZ", "blrabz"},
+{"BMOPA_MPPZZ_S", "bmopa"},
+{"BMOPS_MPPZZ_S", "bmops"},
+{"BR", "br"},
+{"BRAA", "braa"},
+{"BRAAZ", "braaz"},
+{"BRAB", "brab"},
+{"BRABZ", "brabz"},
+{"BRK", "brk"},
+{"BRKAS_PPzP", "brkas"},
+{"BRKA_PPmP", "brka"},
+{"BRKA_PPzP", "brka"},
+{"BRKBS_PPzP", "brkbs"},
+{"BRKB_PPmP", "brkb"},
+{"BRKB_PPzP", "brkb"},
+{"BRKNS_PPzP", "brkns"},
+{"BRKN_PPzP", "brkn"},
+{"BRKPAS_PPzPP", "brkpas"},
+{"BRKPA_PPzPP", "brkpa"},
+{"BRKPBS_PPzPP", "brkpbs"},
+{"BRKPB_PPzPP", "brkpb"},
+{"BSL1N_ZZZZ", "bsl1n"},
+{"BSL2N_ZZZZ", "bsl2n"},
+{"BSL_ZZZZ", "bsl"},
+{"BSLv8i8", "bsl"},
+{"BSLv16i8", "bsl"},
+{"Bcc", "b_cond"},
+{"CADD_ZZI_B", "cadd"},
+{"CADD_ZZI_D", "cadd"},
+{"CADD_ZZI_H", "cadd"},
+{"CADD_ZZI_S", "cadd"},
+{"CASAB", "casab"},
+{"CASAH", "casah"},
+{"CASALB", "casalb"},
+{"CASALH", "casalh"},
+{"CASALTX", "casalt"},
+{"CASALW", "casal"},
+{"CASALX", "casal"},
+{"CASATX", "casat"},
+{"CASAW", "casa"},
+{"CASAX", "casa"},
+{"CASB", "casb"},
+{"CASH", "cash"},
+{"CASLB", "caslb"},
+{"CASLH", "caslh"},
+{"CASLTX", "caslt"},
+{"CASLW", "casl"},
+{"CASLX", "casl"},
+{"CASPALTX", "caspalt"},
+{"CASPALW", "caspal"},
+{"CASPALX", "caspal"},
+{"CASPATX", "caspat"},
+{"CASPAW", "caspa"},
+{"CASPAX", "caspa"},
+{"CASPLTX", "casplt"},
+{"CASPLW", "caspl"},
+{"CASPLX", "caspl"},
+{"CASPTX", "caspt"},
+{"CASPW", "casp"},
+{"CASPX", "casp"},
+{"CASTX", "cast"},
+{"CASW", "cas"},
+{"CASX", "cas"},
+{"CBBEQWrr", "cbbeq"},
+{"CBBGEWrr", "cbbge"},
+{"CBBGTWrr", "cbbgt"},
+{"CBBHIWrr", "cbbhi"},
+{"CBBHSWrr", "cbbhs"},
+{"CBBNEWrr", "cbbne"},
+{"CBEQWri", "cbeq"},
+{"CBEQWrr", "cbeq"},
+{"CBEQXri", "cbeq"},
+{"CBEQXrr", "cbeq"},
+{"CBGEWrr", "cbge"},
+{"CBGEXrr", "cbge"},
+{"CBGTWri", "cbgt"},
+{"CBGTWrr", "cbgt"},
+{"CBGTXri", "cbgt"},
+{"CBGTXrr", "cbgt"},
+{"CBHEQWrr", "cbheq"},
+{"CBHGEWrr", "cbhge"},
+{"CBHGTWrr", "cbhgt"},
+{"CBHHIWrr", "cbhhi"},
+{"CBHHSWrr", "cbhhs"},
+{"CBHIWri", "cbhi"},
+{"CBHIWrr", "cbhi"},
+{"CBHIXri", "cbhi"},
+{"CBHIXrr", "cbhi"},
+{"CBHNEWrr", "cbhne"},
+{"CBHSWrr", "cbhs"},
+{"CBHSXrr", "cbhs"},
+{"CBLOWri", "cblo"},
+{"CBLOXri", "cblo"},
+{"CBLTWri", "cblt"},
+{"CBLTXri", "cblt"},
+{"CBNEWri", "cbne"},
+{"CBNEWrr", "cbne"},
+{"CBNEXri", "cbne"},
+{"CBNEXrr", "cbne"},
+{"CBNZW", "cbnz"},
+{"CBNZX", "cbnz"},
+{"CBZW", "cbz"},
+{"CBZX", "cbz"},
+{"CCMNWi", "ccmn"},
+{"CCMNWr", "ccmn"},
+{"CCMNXi", "ccmn"},
+{"CCMNXr", "ccmn"},
+{"CCMPWi", "ccmp"},
+{"CCMPWr", "ccmp"},
+{"CCMPXi", "ccmp"},
+{"CCMPXr", "ccmp"},
+{"CDOT_ZZZI_D", "cdot"},
+{"CDOT_ZZZI_S", "cdot"},
+{"CDOT_ZZZ_D", "cdot"},
+{"CDOT_ZZZ_S", "cdot"},
+{"CFINV", "cfinv"},
+{"CLASTA_RPZ_B", "clasta"},
+{"CLASTA_RPZ_D", "clasta"},
+{"CLASTA_RPZ_H", "clasta"},
+{"CLASTA_RPZ_S", "clasta"},
+{"CLASTA_VPZ_B", "clasta"},
+{"CLASTA_VPZ_D", "clasta"},
+{"CLASTA_VPZ_H", "clasta"},
+{"CLASTA_VPZ_S", "clasta"},
+{"CLASTA_ZPZ_B", "clasta"},
+{"CLASTA_ZPZ_D", "clasta"},
+{"CLASTA_ZPZ_H", "clasta"},
+{"CLASTA_ZPZ_S", "clasta"},
+{"CLASTB_RPZ_B", "clastb"},
+{"CLASTB_RPZ_D", "clastb"},
+{"CLASTB_RPZ_H", "clastb"},
+{"CLASTB_RPZ_S", "clastb"},
+{"CLASTB_VPZ_B", "clastb"},
+{"CLASTB_VPZ_D", "clastb"},
+{"CLASTB_VPZ_H", "clastb"},
+{"CLASTB_VPZ_S", "clastb"},
+{"CLASTB_ZPZ_B", "clastb"},
+{"CLASTB_ZPZ_D", "clastb"},
+{"CLASTB_ZPZ_H", "clastb"},
+{"CLASTB_ZPZ_S", "clastb"},
+{"CLREX", "clrex"},
+{"CLSWr", "cls"},
+{"CLSXr", "cls"},
+{"CLS_ZPmZ_B", "cls"},
+{"CLS_ZPmZ_D", "cls"},
+{"CLS_ZPmZ_H", "cls"},
+{"CLS_ZPmZ_S", "cls"},
+{"CLS_ZPzZ_B", "cls"},
+{"CLS_ZPzZ_D", "cls"},
+{"CLS_ZPzZ_H", "cls"},
+{"CLS_ZPzZ_S", "cls"},
+{"CLSv2i32", "cls"},
+{"CLSv4i16", "cls"},
+{"CLSv4i32", "cls"},
+{"CLSv8i8", "cls"},
+{"CLSv8i16", "cls"},
+{"CLSv16i8", "cls"},
+{"CLZWr", "clz"},
+{"CLZXr", "clz"},
+{"CLZ_ZPmZ_B", "clz"},
+{"CLZ_ZPmZ_D", "clz"},
+{"CLZ_ZPmZ_H", "clz"},
+{"CLZ_ZPmZ_S", "clz"},
+{"CLZ_ZPzZ_B", "clz"},
+{"CLZ_ZPzZ_D", "clz"},
+{"CLZ_ZPzZ_H", "clz"},
+{"CLZ_ZPzZ_S", "clz"},
+{"CLZv2i32", "clz"},
+{"CLZv4i16", "clz"},
+{"CLZv4i32", "clz"},
+{"CLZv8i8", "clz"},
+{"CLZv8i16", "clz"},
+{"CLZv16i8", "clz"},
+{"CMEQv1i64", "cmeq"},
+{"CMEQv1i64rz", "cmeq"},
+{"CMEQv2i32", "cmeq"},
+{"CMEQv2i32rz", "cmeq"},
+{"CMEQv2i64", "cmeq"},
+{"CMEQv2i64rz", "cmeq"},
+{"CMEQv4i16", "cmeq"},
+{"CMEQv4i16rz", "cmeq"},
+{"CMEQv4i32", "cmeq"},
+{"CMEQv4i32rz", "cmeq"},
+{"CMEQv8i8", "cmeq"},
+{"CMEQv8i8rz", "cmeq"},
+{"CMEQv8i16", "cmeq"},
+{"CMEQv8i16rz", "cmeq"},
+{"CMEQv16i8", "cmeq"},
+{"CMEQv16i8rz", "cmeq"},
+{"CMGEv1i64", "cmge"},
+{"CMGEv1i64rz", "cmge"},
+{"CMGEv2i32", "cmge"},
+{"CMGEv2i32rz", "cmge"},
+{"CMGEv2i64", "cmge"},
+{"CMGEv2i64rz", "cmge"},
+{"CMGEv4i16", "cmge"},
+{"CMGEv4i16rz", "cmge"},
+{"CMGEv4i32", "cmge"},
+{"CMGEv4i32rz", "cmge"},
+{"CMGEv8i8", "cmge"},
+{"CMGEv8i8rz", "cmge"},
+{"CMGEv8i16", "cmge"},
+{"CMGEv8i16rz", "cmge"},
+{"CMGEv16i8", "cmge"},
+{"CMGEv16i8rz", "cmge"},
+{"CMGTv1i64", "cmgt"},
+{"CMGTv1i64rz", "cmgt"},
+{"CMGTv2i32", "cmgt"},
+{"CMGTv2i32rz", "cmgt"},
+{"CMGTv2i64", "cmgt"},
+{"CMGTv2i64rz", "cmgt"},
+{"CMGTv4i16", "cmgt"},
+{"CMGTv4i16rz", "cmgt"},
+{"CMGTv4i32", "cmgt"},
+{"CMGTv4i32rz", "cmgt"},
+{"CMGTv8i8", "cmgt"},
+{"CMGTv8i8rz", "cmgt"},
+{"CMGTv8i16", "cmgt"},
+{"CMGTv8i16rz", "cmgt"},
+{"CMGTv16i8", "cmgt"},
+{"CMGTv16i8rz", "cmgt"},
+{"CMHIv1i64", "cmhi"},
+{"CMHIv2i32", "cmhi"},
+{"CMHIv2i64", "cmhi"},
+{"CMHIv4i16", "cmhi"},
+{"CMHIv4i32", "cmhi"},
+{"CMHIv8i8", "cmhi"},
+{"CMHIv8i16", "cmhi"},
+{"CMHIv16i8", "cmhi"},
+{"CMHSv1i64", "cmhs"},
+{"CMHSv2i32", "cmhs"},
+{"CMHSv2i64", "cmhs"},
+{"CMHSv4i16", "cmhs"},
+{"CMHSv4i32", "cmhs"},
+{"CMHSv8i8", "cmhs"},
+{"CMHSv8i16", "cmhs"},
+{"CMHSv16i8", "cmhs"},
+{"CMLA_ZZZI_H", "cmla"},
+{"CMLA_ZZZI_S", "cmla"},
+{"CMLA_ZZZ_B", "cmla"},
+{"CMLA_ZZZ_D", "cmla"},
+{"CMLA_ZZZ_H", "cmla"},
+{"CMLA_ZZZ_S", "cmla"},
+{"CMLEv1i64rz", "cmle"},
+{"CMLEv2i32rz", "cmle"},
+{"CMLEv2i64rz", "cmle"},
+{"CMLEv4i16rz", "cmle"},
+{"CMLEv4i32rz", "cmle"},
+{"CMLEv8i8rz", "cmle"},
+{"CMLEv8i16rz", "cmle"},
+{"CMLEv16i8rz", "cmle"},
+{"CMLTv1i64rz", "cmlt"},
+{"CMLTv2i32rz", "cmlt"},
+{"CMLTv2i64rz", "cmlt"},
+{"CMLTv4i16rz", "cmlt"},
+{"CMLTv4i32rz", "cmlt"},
+{"CMLTv8i8rz", "cmlt"},
+{"CMLTv8i16rz", "cmlt"},
+{"CMLTv16i8rz", "cmlt"},
+{"CMPEQ_PPzZI_B", "cmpeq"},
+{"CMPEQ_PPzZI_D", "cmpeq"},
+{"CMPEQ_PPzZI_H", "cmpeq"},
+{"CMPEQ_PPzZI_S", "cmpeq"},
+{"CMPEQ_PPzZZ_B", "cmpeq"},
+{"CMPEQ_PPzZZ_D", "cmpeq"},
+{"CMPEQ_PPzZZ_H", "cmpeq"},
+{"CMPEQ_PPzZZ_S", "cmpeq"},
+{"CMPEQ_WIDE_PPzZZ_B", "cmpeq"},
+{"CMPEQ_WIDE_PPzZZ_H", "cmpeq"},
+{"CMPEQ_WIDE_PPzZZ_S", "cmpeq"},
+{"CMPGE_PPzZI_B", "cmpge"},
+{"CMPGE_PPzZI_D", "cmpge"},
+{"CMPGE_PPzZI_H", "cmpge"},
+{"CMPGE_PPzZI_S", "cmpge"},
+{"CMPGE_PPzZZ_B", "cmpge"},
+{"CMPGE_PPzZZ_D", "cmpge"},
+{"CMPGE_PPzZZ_H", "cmpge"},
+{"CMPGE_PPzZZ_S", "cmpge"},
+{"CMPGE_WIDE_PPzZZ_B", "cmpge"},
+{"CMPGE_WIDE_PPzZZ_H", "cmpge"},
+{"CMPGE_WIDE_PPzZZ_S", "cmpge"},
+{"CMPGT_PPzZI_B", "cmpgt"},
+{"CMPGT_PPzZI_D", "cmpgt"},
+{"CMPGT_PPzZI_H", "cmpgt"},
+{"CMPGT_PPzZI_S", "cmpgt"},
+{"CMPGT_PPzZZ_B", "cmpgt"},
+{"CMPGT_PPzZZ_D", "cmpgt"},
+{"CMPGT_PPzZZ_H", "cmpgt"},
+{"CMPGT_PPzZZ_S", "cmpgt"},
+{"CMPGT_WIDE_PPzZZ_B", "cmpgt"},
+{"CMPGT_WIDE_PPzZZ_H", "cmpgt"},
+{"CMPGT_WIDE_PPzZZ_S", "cmpgt"},
+{"CMPHI_PPzZI_B", "cmphi"},
+{"CMPHI_PPzZI_D", "cmphi"},
+{"CMPHI_PPzZI_H", "cmphi"},
+{"CMPHI_PPzZI_S", "cmphi"},
+{"CMPHI_PPzZZ_B", "cmphi"},
+{"CMPHI_PPzZZ_D", "cmphi"},
+{"CMPHI_PPzZZ_H", "cmphi"},
+{"CMPHI_PPzZZ_S", "cmphi"},
+{"CMPHI_WIDE_PPzZZ_B", "cmphi"},
+{"CMPHI_WIDE_PPzZZ_H", "cmphi"},
+{"CMPHI_WIDE_PPzZZ_S", "cmphi"},
+{"CMPHS_PPzZI_B", "cmphs"},
+{"CMPHS_PPzZI_D", "cmphs"},
+{"CMPHS_PPzZI_H", "cmphs"},
+{"CMPHS_PPzZI_S", "cmphs"},
+{"CMPHS_PPzZZ_B", "cmphs"},
+{"CMPHS_PPzZZ_D", "cmphs"},
+{"CMPHS_PPzZZ_H", "cmphs"},
+{"CMPHS_PPzZZ_S", "cmphs"},
+{"CMPHS_WIDE_PPzZZ_B", "cmphs"},
+{"CMPHS_WIDE_PPzZZ_H", "cmphs"},
+{"CMPHS_WIDE_PPzZZ_S", "cmphs"},
+{"CMPLE_PPzZI_B", "cmple"},
+{"CMPLE_PPzZI_D", "cmple"},
+{"CMPLE_PPzZI_H", "cmple"},
+{"CMPLE_PPzZI_S", "cmple"},
+{"CMPLE_WIDE_PPzZZ_B", "cmple"},
+{"CMPLE_WIDE_PPzZZ_H", "cmple"},
+{"CMPLE_WIDE_PPzZZ_S", "cmple"},
+{"CMPLO_PPzZI_B", "cmplo"},
+{"CMPLO_PPzZI_D", "cmplo"},
+{"CMPLO_PPzZI_H", "cmplo"},
+{"CMPLO_PPzZI_S", "cmplo"},
+{"CMPLO_WIDE_PPzZZ_B", "cmplo"},
+{"CMPLO_WIDE_PPzZZ_H", "cmplo"},
+{"CMPLO_WIDE_PPzZZ_S", "cmplo"},
+{"CMPLS_PPzZI_B", "cmpls"},
+{"CMPLS_PPzZI_D", "cmpls"},
+{"CMPLS_PPzZI_H", "cmpls"},
+{"CMPLS_PPzZI_S", "cmpls"},
+{"CMPLS_WIDE_PPzZZ_B", "cmpls"},
+{"CMPLS_WIDE_PPzZZ_H", "cmpls"},
+{"CMPLS_WIDE_PPzZZ_S", "cmpls"},
+{"CMPLT_PPzZI_B", "cmplt"},
+{"CMPLT_PPzZI_D", "cmplt"},
+{"CMPLT_PPzZI_H", "cmplt"},
+{"CMPLT_PPzZI_S", "cmplt"},
+{"CMPLT_WIDE_PPzZZ_B", "cmplt"},
+{"CMPLT_WIDE_PPzZZ_H", "cmplt"},
+{"CMPLT_WIDE_PPzZZ_S", "cmplt"},
+{"CMPNE_PPzZI_B", "cmpne"},
+{"CMPNE_PPzZI_D", "cmpne"},
+{"CMPNE_PPzZI_H", "cmpne"},
+{"CMPNE_PPzZI_S", "cmpne"},
+{"CMPNE_PPzZZ_B", "cmpne"},
+{"CMPNE_PPzZZ_D", "cmpne"},
+{"CMPNE_PPzZZ_H", "cmpne"},
+{"CMPNE_PPzZZ_S", "cmpne"},
+{"CMPNE_WIDE_PPzZZ_B", "cmpne"},
+{"CMPNE_WIDE_PPzZZ_H", "cmpne"},
+{"CMPNE_WIDE_PPzZZ_S", "cmpne"},
+{"CMTSTv1i64", "cmtst"},
+{"CMTSTv2i32", "cmtst"},
+{"CMTSTv2i64", "cmtst"},
+{"CMTSTv4i16", "cmtst"},
+{"CMTSTv4i32", "cmtst"},
+{"CMTSTv8i8", "cmtst"},
+{"CMTSTv8i16", "cmtst"},
+{"CMTSTv16i8", "cmtst"},
+{"CNOT_ZPmZ_B", "cnot"},
+{"CNOT_ZPmZ_D", "cnot"},
+{"CNOT_ZPmZ_H", "cnot"},
+{"CNOT_ZPmZ_S", "cnot"},
+{"CNOT_ZPzZ_B", "cnot"},
+{"CNOT_ZPzZ_D", "cnot"},
+{"CNOT_ZPzZ_H", "cnot"},
+{"CNOT_ZPzZ_S", "cnot"},
+{"CNTB_XPiI", "cntb"},
+{"CNTD_XPiI", "cntd"},
+{"CNTH_XPiI", "cnth"},
+{"CNTP_XCI_B", "cntp"},
+{"CNTP_XCI_D", "cntp"},
+{"CNTP_XCI_H", "cntp"},
+{"CNTP_XCI_S", "cntp"},
+{"CNTP_XPP_B", "cntp"},
+{"CNTP_XPP_D", "cntp"},
+{"CNTP_XPP_H", "cntp"},
+{"CNTP_XPP_S", "cntp"},
+{"CNTW_XPiI", "cntw"},
+{"CNTWr", "cnt"},
+{"CNTXr", "cnt"},
+{"CNT_ZPmZ_B", "cnt"},
+{"CNT_ZPmZ_D", "cnt"},
+{"CNT_ZPmZ_H", "cnt"},
+{"CNT_ZPmZ_S", "cnt"},
+{"CNT_ZPzZ_B", "cnt"},
+{"CNT_ZPzZ_D", "cnt"},
+{"CNT_ZPzZ_H", "cnt"},
+{"CNT_ZPzZ_S", "cnt"},
+{"CNTv8i8", "cnt"},
+{"CNTv16i8", "cnt"},
+{"COMPACT_ZPZ_B", "compact"},
+{"COMPACT_ZPZ_D", "compact"},
+{"COMPACT_ZPZ_H", "compact"},
+{"COMPACT_ZPZ_S", "compact"},
+{"CPYE", "cpye"},
+{"CPYEN", "cpyen"},
+{"CPYERN", "cpyern"},
+{"CPYERT", "cpyert"},
+{"CPYERTN", "cpyertn"},
+{"CPYERTRN", "cpyertrn"},
+{"CPYERTWN", "cpyertwn"},
+{"CPYET", "cpyet"},
+{"CPYETN", "cpyetn"},
+{"CPYETRN", "cpyetrn"},
+{"CPYETWN", "cpyetwn"},
+{"CPYEWN", "cpyewn"},
+{"CPYEWT", "cpyewt"},
+{"CPYEWTN", "cpyewtn"},
+{"CPYEWTRN", "cpyewtrn"},
+{"CPYEWTWN", "cpyewtwn"},
+{"CPYFE", "cpyfe"},
+{"CPYFEN", "cpyfen"},
+{"CPYFERN", "cpyfern"},
+{"CPYFERT", "cpyfert"},
+{"CPYFERTN", "cpyfertn"},
+{"CPYFERTRN", "cpyfertrn"},
+{"CPYFERTWN", "cpyfertwn"},
+{"CPYFET", "cpyfet"},
+{"CPYFETN", "cpyfetn"},
+{"CPYFETRN", "cpyfetrn"},
+{"CPYFETWN", "cpyfetwn"},
+{"CPYFEWN", "cpyfewn"},
+{"CPYFEWT", "cpyfewt"},
+{"CPYFEWTN", "cpyfewtn"},
+{"CPYFEWTRN", "cpyfewtrn"},
+{"CPYFEWTWN", "cpyfewtwn"},
+{"CPYFM", "cpyfm"},
+{"CPYFMN", "cpyfmn"},
+{"CPYFMRN", "cpyfmrn"},
+{"CPYFMRT", "cpyfmrt"},
+{"CPYFMRTN", "cpyfmrtn"},
+{"CPYFMRTRN", "cpyfmrtrn"},
+{"CPYFMRTWN", "cpyfmrtwn"},
+{"CPYFMT", "cpyfmt"},
+{"CPYFMTN", "cpyfmtn"},
+{"CPYFMTRN", "cpyfmtrn"},
+{"CPYFMTWN", "cpyfmtwn"},
+{"CPYFMWN", "cpyfmwn"},
+{"CPYFMWT", "cpyfmwt"},
+{"CPYFMWTN", "cpyfmwtn"},
+{"CPYFMWTRN", "cpyfmwtrn"},
+{"CPYFMWTWN", "cpyfmwtwn"},
+{"CPYFP", "cpyfp"},
+{"CPYFPN", "cpyfpn"},
+{"CPYFPRN", "cpyfprn"},
+{"CPYFPRT", "cpyfprt"},
+{"CPYFPRTN", "cpyfprtn"},
+{"CPYFPRTRN", "cpyfprtrn"},
+{"CPYFPRTWN", "cpyfprtwn"},
+{"CPYFPT", "cpyfpt"},
+{"CPYFPTN", "cpyfptn"},
+{"CPYFPTRN", "cpyfptrn"},
+{"CPYFPTWN", "cpyfptwn"},
+{"CPYFPWN", "cpyfpwn"},
+{"CPYFPWT", "cpyfpwt"},
+{"CPYFPWTN", "cpyfpwtn"},
+{"CPYFPWTRN", "cpyfpwtrn"},
+{"CPYFPWTWN", "cpyfpwtwn"},
+{"CPYM", "cpym"},
+{"CPYMN", "cpymn"},
+{"CPYMRN", "cpymrn"},
+{"CPYMRT", "cpymrt"},
+{"CPYMRTN", "cpymrtn"},
+{"CPYMRTRN", "cpymrtrn"},
+{"CPYMRTWN", "cpymrtwn"},
+{"CPYMT", "cpymt"},
+{"CPYMTN", "cpymtn"},
+{"CPYMTRN", "cpymtrn"},
+{"CPYMTWN", "cpymtwn"},
+{"CPYMWN", "cpymwn"},
+{"CPYMWT", "cpymwt"},
+{"CPYMWTN", "cpymwtn"},
+{"CPYMWTRN", "cpymwtrn"},
+{"CPYMWTWN", "cpymwtwn"},
+{"CPYP", "cpyp"},
+{"CPYPN", "cpypn"},
+{"CPYPRN", "cpyprn"},
+{"CPYPRT", "cpyprt"},
+{"CPYPRTN", "cpyprtn"},
+{"CPYPRTRN", "cpyprtrn"},
+{"CPYPRTWN", "cpyprtwn"},
+{"CPYPT", "cpypt"},
+{"CPYPTN", "cpyptn"},
+{"CPYPTRN", "cpyptrn"},
+{"CPYPTWN", "cpyptwn"},
+{"CPYPWN", "cpypwn"},
+{"CPYPWT", "cpypwt"},
+{"CPYPWTN", "cpypwtn"},
+{"CPYPWTRN", "cpypwtrn"},
+{"CPYPWTWN", "cpypwtwn"},
+{"CPY_ZPmI_B", "cpy"},
+{"CPY_ZPmI_D", "cpy"},
+{"CPY_ZPmI_H", "cpy"},
+{"CPY_ZPmI_S", "cpy"},
+{"CPY_ZPmR_B", "cpy"},
+{"CPY_ZPmR_D", "cpy"},
+{"CPY_ZPmR_H", "cpy"},
+{"CPY_ZPmR_S", "cpy"},
+{"CPY_ZPmV_B", "cpy"},
+{"CPY_ZPmV_D", "cpy"},
+{"CPY_ZPmV_H", "cpy"},
+{"CPY_ZPmV_S", "cpy"},
+{"CPY_ZPzI_B", "cpy"},
+{"CPY_ZPzI_D", "cpy"},
+{"CPY_ZPzI_H", "cpy"},
+{"CPY_ZPzI_S", "cpy"},
+{"CRC32Brr", "crc32b"},
+{"CRC32CBrr", "crc32cb"},
+{"CRC32CHrr", "crc32ch"},
+{"CRC32CWrr", "crc32cw"},
+{"CRC32CXrr", "crc32cx"},
+{"CRC32Hrr", "crc32h"},
+{"CRC32Wrr", "crc32w"},
+{"CRC32Xrr", "crc32x"},
+{"CSELWr", "csel"},
+{"CSELXr", "csel"},
+{"CSINCWr", "csinc"},
+{"CSINCXr", "csinc"},
+{"CSINVWr", "csinv"},
+{"CSINVXr", "csinv"},
+{"CSNEGWr", "csneg"},
+{"CSNEGXr", "csneg"},
+{"CTERMEQ_WW", "ctermeq"},
+{"CTERMEQ_XX", "ctermeq"},
+{"CTERMNE_WW", "ctermne"},
+{"CTERMNE_XX", "ctermne"},
+{"CTZWr", "ctz"},
+{"CTZXr", "ctz"},
+{"DCPS1", "dcps1"},
+{"DCPS2", "dcps2"},
+{"DCPS3", "dcps3"},
+{"DECB_XPiI", "decb"},
+{"DECD_XPiI", "decd"},
+{"DECD_ZPiI", "decd"},
+{"DECH_XPiI", "dech"},
+{"DECH_ZPiI", "dech"},
+{"DECP_XP_B", "decp"},
+{"DECP_XP_D", "decp"},
+{"DECP_XP_H", "decp"},
+{"DECP_XP_S", "decp"},
+{"DECP_ZP_D", "decp"},
+{"DECP_ZP_H", "decp"},
+{"DECP_ZP_S", "decp"},
+{"DECW_XPiI", "decw"},
+{"DECW_ZPiI", "decw"},
+{"DMB", "dmb"},
+{"DRPS", "drps"},
+{"DSB", "dsb"},
+{"DSBnXS", "dsb"},
+{"DUPM_ZI", "dupm"},
+{"DUPQ_ZZI_B", "dupq"},
+{"DUPQ_ZZI_D", "dupq"},
+{"DUPQ_ZZI_H", "dupq"},
+{"DUPQ_ZZI_S", "dupq"},
+{"DUP_ZI_B", "dup"},
+{"DUP_ZI_D", "dup"},
+{"DUP_ZI_H", "dup"},
+{"DUP_ZI_S", "dup"},
+{"DUP_ZR_B", "dup"},
+{"DUP_ZR_D", "dup"},
+{"DUP_ZR_H", "dup"},
+{"DUP_ZR_S", "dup"},
+{"DUP_ZZI_B", "dup"},
+{"DUP_ZZI_D", "dup"},
+{"DUP_ZZI_H", "dup"},
+{"DUP_ZZI_Q", "dup"},
+{"DUP_ZZI_S", "dup"},
+{"DUPv2i32gpr", "dup"},
+{"DUPv2i32lane", "dup"},
+{"DUPv2i64gpr", "dup"},
+{"DUPv2i64lane", "dup"},
+{"DUPv4i16gpr", "dup"},
+{"DUPv4i16lane", "dup"},
+{"DUPv4i32gpr", "dup"},
+{"DUPv4i32lane", "dup"},
+{"DUPv8i8gpr", "dup"},
+{"DUPv8i8lane", "dup"},
+{"DUPv8i16gpr", "dup"},
+{"DUPv8i16lane", "dup"},
+{"DUPv16i8gpr", "dup"},
+{"DUPv16i8lane", "dup"},
+{"DUPi8", "mov"},
+{"DUPi16", "mov"},
+{"DUPi32", "mov"},
+{"DUPi64", "mov"},
+{"EONWrs", "eon"},
+{"EONXrs", "eon"},
+{"EOR3", "eor3"},
+{"EOR3_ZZZZ", "eor3"},
+{"EORBT_ZZZ_B", "eorbt"},
+{"EORBT_ZZZ_D", "eorbt"},
+{"EORBT_ZZZ_H", "eorbt"},
+{"EORBT_ZZZ_S", "eorbt"},
+{"EORQV_VPZ_B", "eorqv"},
+{"EORQV_VPZ_D", "eorqv"},
+{"EORQV_VPZ_H", "eorqv"},
+{"EORQV_VPZ_S", "eorqv"},
+{"EORS_PPzPP", "eors"},
+{"EORTB_ZZZ_B", "eortb"},
+{"EORTB_ZZZ_D", "eortb"},
+{"EORTB_ZZZ_H", "eortb"},
+{"EORTB_ZZZ_S", "eortb"},
+{"EORV_VPZ_B", "eorv"},
+{"EORV_VPZ_D", "eorv"},
+{"EORV_VPZ_H", "eorv"},
+{"EORV_VPZ_S", "eorv"},
+{"EORWri", "eor"},
+{"EORWrs", "eor"},
+{"EORXri", "eor"},
+{"EORXrs", "eor"},
+{"EOR_PPzPP", "eor"},
+{"EOR_ZI", "eor"},
+{"EOR_ZPmZ_B", "eor"},
+{"EOR_ZPmZ_D", "eor"},
+{"EOR_ZPmZ_H", "eor"},
+{"EOR_ZPmZ_S", "eor"},
+{"EOR_ZZZ", "eor"},
+{"EORv8i8", "eor"},
+{"EORv16i8", "eor"},
+{"ERET", "eret"},
+{"ERETAA", "eretaa"},
+{"ERETAB", "eretab"},
+{"EXPAND_ZPZ_B", "expand"},
+{"EXPAND_ZPZ_D", "expand"},
+{"EXPAND_ZPZ_H", "expand"},
+{"EXPAND_ZPZ_S", "expand"},
+{"EXTQ_ZZI", "extq"},
+{"EXTRACT_ZPMXI_H_B", "mova"},
+{"EXTRACT_ZPMXI_H_D", "mova"},
+{"EXTRACT_ZPMXI_H_H", "mova"},
+{"EXTRACT_ZPMXI_H_Q", "mova"},
+{"EXTRACT_ZPMXI_H_S", "mova"},
+{"EXTRACT_ZPMXI_V_B", "mova"},
+{"EXTRACT_ZPMXI_V_D", "mova"},
+{"EXTRACT_ZPMXI_V_H", "mova"},
+{"EXTRACT_ZPMXI_V_Q", "mova"},
+{"EXTRACT_ZPMXI_V_S", "mova"},
+{"INSERT_MXIPZ_H_B", "mova"},
+{"INSERT_MXIPZ_H_D", "mova"},
+{"INSERT_MXIPZ_H_H", "mova"},
+{"INSERT_MXIPZ_H_Q", "mova"},
+{"INSERT_MXIPZ_H_S", "mova"},
+{"INSERT_MXIPZ_V_B", "mova"},
+{"INSERT_MXIPZ_V_D", "mova"},
+{"INSERT_MXIPZ_V_H", "mova"},
+{"INSERT_MXIPZ_V_Q", "mova"},
+{"INSERT_MXIPZ_V_S", "mova"},
+{"MOVA_2ZMXI_H_B", "mova"},
+{"MOVA_2ZMXI_H_D", "mova"},
+{"MOVA_2ZMXI_H_H", "mova"},
+{"MOVA_2ZMXI_H_S", "mova"},
+{"MOVA_2ZMXI_V_B", "mova"},
+{"MOVA_2ZMXI_V_D", "mova"},
+{"MOVA_2ZMXI_V_H", "mova"},
+{"MOVA_2ZMXI_V_S", "mova"},
+{"MOVA_4ZMXI_H_B", "mova"},
+{"MOVA_4ZMXI_H_D", "mova"},
+{"MOVA_4ZMXI_H_H", "mova"},
+{"MOVA_4ZMXI_H_S", "mova"},
+{"MOVA_4ZMXI_V_B", "mova"},
+{"MOVA_4ZMXI_V_D", "mova"},
+{"MOVA_4ZMXI_V_H", "mova"},
+{"MOVA_4ZMXI_V_S", "mova"},
+{"MOVA_MXI2Z_H_B", "mova"},
+{"MOVA_MXI2Z_H_D", "mova"},
+{"MOVA_MXI2Z_H_H", "mova"},
+{"MOVA_MXI2Z_H_S", "mova"},
+{"MOVA_MXI2Z_V_B", "mova"},
+{"MOVA_MXI2Z_V_D", "mova"},
+{"MOVA_MXI2Z_V_H", "mova"},
+{"MOVA_MXI2Z_V_S", "mova"},
+{"MOVA_MXI4Z_H_B", "mova"},
+{"MOVA_MXI4Z_H_D", "mova"},
+{"MOVA_MXI4Z_H_H", "mova"},
+{"MOVA_MXI4Z_H_S", "mova"},
+{"MOVA_MXI4Z_V_B", "mova"},
+{"MOVA_MXI4Z_V_D", "mova"},
+{"MOVA_MXI4Z_V_H", "mova"},
+{"MOVA_MXI4Z_V_S", "mova"},
+{"MOVA_VG2_2ZMXI", "mova"},
+{"MOVA_VG2_MXI2Z", "mova"},
+{"MOVA_VG4_4ZMXI", "mova"},
+{"MOVA_VG4_MXI4Z", "mova"},
+{"EXTRWrri", "extr"},
+{"EXTRXrri", "extr"},
+{"EXT_ZZI", "ext"},
+{"EXT_ZZI_B", "ext"},
+{"EXTv8i8", "ext"},
+{"EXTv16i8", "ext"},
+{"F1CVTL", "f1cvtl"},
+{"F1CVTL_2ZZ_BtoH", "f1cvtl"},
+{"F1CVTL2", "f1cvtl2"},
+{"F1CVTLT_ZZ_BtoH", "f1cvtlt"},
+{"F1CVT_2ZZ_BtoH", "f1cvt"},
+{"F1CVT_ZZ_BtoH", "f1cvt"},
+{"F2CVTL", "f2cvtl"},
+{"F2CVTL_2ZZ_BtoH", "f2cvtl"},
+{"F2CVTL2", "f2cvtl2"},
+{"F2CVTLT_ZZ_BtoH", "f2cvtlt"},
+{"F2CVT_2ZZ_BtoH", "f2cvt"},
+{"F2CVT_ZZ_BtoH", "f2cvt"},
+{"FABD16", "fabd"},
+{"FABD32", "fabd"},
+{"FABD64", "fabd"},
+{"FABD_ZPmZ_D", "fabd"},
+{"FABD_ZPmZ_H", "fabd"},
+{"FABD_ZPmZ_S", "fabd"},
+{"FABDv2f32", "fabd"},
+{"FABDv2f64", "fabd"},
+{"FABDv4f16", "fabd"},
+{"FABDv4f32", "fabd"},
+{"FABDv8f16", "fabd"},
+{"FABSDr", "fabs"},
+{"FABSHr", "fabs"},
+{"FABSSr", "fabs"},
+{"FABS_ZPmZ_D", "fabs"},
+{"FABS_ZPmZ_H", "fabs"},
+{"FABS_ZPmZ_S", "fabs"},
+{"FABS_ZPzZ_D", "fabs"},
+{"FABS_ZPzZ_H", "fabs"},
+{"FABS_ZPzZ_S", "fabs"},
+{"FABSv2f32", "fabs"},
+{"FABSv2f64", "fabs"},
+{"FABSv4f16", "fabs"},
+{"FABSv4f32", "fabs"},
+{"FABSv8f16", "fabs"},
+{"FACGE16", "facge"},
+{"FACGE32", "facge"},
+{"FACGE64", "facge"},
+{"FACGE_PPzZZ_D", "facge"},
+{"FACGE_PPzZZ_H", "facge"},
+{"FACGE_PPzZZ_S", "facge"},
+{"FACGEv2f32", "facge"},
+{"FACGEv2f64", "facge"},
+{"FACGEv4f16", "facge"},
+{"FACGEv4f32", "facge"},
+{"FACGEv8f16", "facge"},
+{"FACGT16", "facgt"},
+{"FACGT32", "facgt"},
+{"FACGT64", "facgt"},
+{"FACGT_PPzZZ_D", "facgt"},
+{"FACGT_PPzZZ_H", "facgt"},
+{"FACGT_PPzZZ_S", "facgt"},
+{"FACGTv2f32", "facgt"},
+{"FACGTv2f64", "facgt"},
+{"FACGTv4f16", "facgt"},
+{"FACGTv4f32", "facgt"},
+{"FACGTv8f16", "facgt"},
+{"FADDA_VPZ_D", "fadda"},
+{"FADDA_VPZ_H", "fadda"},
+{"FADDA_VPZ_S", "fadda"},
+{"FADDDrr", "fadd"},
+{"FADDHrr", "fadd"},
+{"FADDSrr", "fadd"},
+{"FADD_VG2_M2Z_D", "fadd"},
+{"FADD_VG2_M2Z_H", "fadd"},
+{"FADD_VG2_M2Z_S", "fadd"},
+{"FADD_VG4_M4Z_D", "fadd"},
+{"FADD_VG4_M4Z_H", "fadd"},
+{"FADD_VG4_M4Z_S", "fadd"},
+{"FADD_ZPmI_D", "fadd"},
+{"FADD_ZPmI_H", "fadd"},
+{"FADD_ZPmI_S", "fadd"},
+{"FADD_ZPmZ_D", "fadd"},
+{"FADD_ZPmZ_H", "fadd"},
+{"FADD_ZPmZ_S", "fadd"},
+{"FADD_ZZZ_D", "fadd"},
+{"FADD_ZZZ_H", "fadd"},
+{"FADD_ZZZ_S", "fadd"},
+{"FADDv2f32", "fadd"},
+{"FADDv2f64", "fadd"},
+{"FADDv4f16", "fadd"},
+{"FADDv4f32", "fadd"},
+{"FADDv8f16", "fadd"},
+{"FADDP_ZPmZZ_D", "faddp"},
+{"FADDP_ZPmZZ_H", "faddp"},
+{"FADDP_ZPmZZ_S", "faddp"},
+{"FADDPv2f32", "faddp"},
+{"FADDPv2f64", "faddp"},
+{"FADDPv2i16p", "faddp"},
+{"FADDPv2i32p", "faddp"},
+{"FADDPv2i64p", "faddp"},
+{"FADDPv4f16", "faddp"},
+{"FADDPv4f32", "faddp"},
+{"FADDPv8f16", "faddp"},
+{"FADDQV_D", "faddqv"},
+{"FADDQV_H", "faddqv"},
+{"FADDQV_S", "faddqv"},
+{"FADDV_VPZ_D", "faddv"},
+{"FADDV_VPZ_H", "faddv"},
+{"FADDV_VPZ_S", "faddv"},
+{"FAMAX_2Z2Z_D", "famax"},
+{"FAMAX_2Z2Z_H", "famax"},
+{"FAMAX_2Z2Z_S", "famax"},
+{"FAMAX_4Z4Z_D", "famax"},
+{"FAMAX_4Z4Z_H", "famax"},
+{"FAMAX_4Z4Z_S", "famax"},
+{"FAMAX_ZPmZ_D", "famax"},
+{"FAMAX_ZPmZ_H", "famax"},
+{"FAMAX_ZPmZ_S", "famax"},
+{"FAMAXv2f32", "famax"},
+{"FAMAXv2f64", "famax"},
+{"FAMAXv4f16", "famax"},
+{"FAMAXv4f32", "famax"},
+{"FAMAXv8f16", "famax"},
+{"FAMIN_2Z2Z_D", "famin"},
+{"FAMIN_2Z2Z_H", "famin"},
+{"FAMIN_2Z2Z_S", "famin"},
+{"FAMIN_4Z4Z_D", "famin"},
+{"FAMIN_4Z4Z_H", "famin"},
+{"FAMIN_4Z4Z_S", "famin"},
+{"FAMIN_ZPmZ_D", "famin"},
+{"FAMIN_ZPmZ_H", "famin"},
+{"FAMIN_ZPmZ_S", "famin"},
+{"FAMINv2f32", "famin"},
+{"FAMINv2f64", "famin"},
+{"FAMINv4f16", "famin"},
+{"FAMINv4f32", "famin"},
+{"FAMINv8f16", "famin"},
+{"FCADD_ZPmZ_D", "fcadd"},
+{"FCADD_ZPmZ_H", "fcadd"},
+{"FCADD_ZPmZ_S", "fcadd"},
+{"FCADDv2f32", "fcadd"},
+{"FCADDv2f64", "fcadd"},
+{"FCADDv4f16", "fcadd"},
+{"FCADDv4f32", "fcadd"},
+{"FCADDv8f16", "fcadd"},
+{"FCCMPDrr", "fccmp"},
+{"FCCMPHrr", "fccmp"},
+{"FCCMPSrr", "fccmp"},
+{"FCCMPEDrr", "fccmpe"},
+{"FCCMPEHrr", "fccmpe"},
+{"FCCMPESrr", "fccmpe"},
+{"FCLAMP_VG2_2Z2Z_D", "fclamp"},
+{"FCLAMP_VG2_2Z2Z_H", "fclamp"},
+{"FCLAMP_VG2_2Z2Z_S", "fclamp"},
+{"FCLAMP_VG4_4Z4Z_D", "fclamp"},
+{"FCLAMP_VG4_4Z4Z_H", "fclamp"},
+{"FCLAMP_VG4_4Z4Z_S", "fclamp"},
+{"FCLAMP_ZZZ_D", "fclamp"},
+{"FCLAMP_ZZZ_H", "fclamp"},
+{"FCLAMP_ZZZ_S", "fclamp"},
+{"FCMEQ16", "fcmeq"},
+{"FCMEQ32", "fcmeq"},
+{"FCMEQ64", "fcmeq"},
+{"FCMEQ_PPzZ0_D", "fcmeq"},
+{"FCMEQ_PPzZ0_H", "fcmeq"},
+{"FCMEQ_PPzZ0_S", "fcmeq"},
+{"FCMEQ_PPzZZ_D", "fcmeq"},
+{"FCMEQ_PPzZZ_H", "fcmeq"},
+{"FCMEQ_PPzZZ_S", "fcmeq"},
+{"FCMEQv1i16rz", "fcmeq"},
+{"FCMEQv1i32rz", "fcmeq"},
+{"FCMEQv1i64rz", "fcmeq"},
+{"FCMEQv2f32", "fcmeq"},
+{"FCMEQv2f64", "fcmeq"},
+{"FCMEQv2i32rz", "fcmeq"},
+{"FCMEQv2i64rz", "fcmeq"},
+{"FCMEQv4f16", "fcmeq"},
+{"FCMEQv4f32", "fcmeq"},
+{"FCMEQv4i16rz", "fcmeq"},
+{"FCMEQv4i32rz", "fcmeq"},
+{"FCMEQv8f16", "fcmeq"},
+{"FCMEQv8i16rz", "fcmeq"},
+{"FCMGE16", "fcmge"},
+{"FCMGE32", "fcmge"},
+{"FCMGE64", "fcmge"},
+{"FCMGE_PPzZ0_D", "fcmge"},
+{"FCMGE_PPzZ0_H", "fcmge"},
+{"FCMGE_PPzZ0_S", "fcmge"},
+{"FCMGE_PPzZZ_D", "fcmge"},
+{"FCMGE_PPzZZ_H", "fcmge"},
+{"FCMGE_PPzZZ_S", "fcmge"},
+{"FCMGEv1i16rz", "fcmge"},
+{"FCMGEv1i32rz", "fcmge"},
+{"FCMGEv1i64rz", "fcmge"},
+{"FCMGEv2f32", "fcmge"},
+{"FCMGEv2f64", "fcmge"},
+{"FCMGEv2i32rz", "fcmge"},
+{"FCMGEv2i64rz", "fcmge"},
+{"FCMGEv4f16", "fcmge"},
+{"FCMGEv4f32", "fcmge"},
+{"FCMGEv4i16rz", "fcmge"},
+{"FCMGEv4i32rz", "fcmge"},
+{"FCMGEv8f16", "fcmge"},
+{"FCMGEv8i16rz", "fcmge"},
+{"FCMGT16", "fcmgt"},
+{"FCMGT32", "fcmgt"},
+{"FCMGT64", "fcmgt"},
+{"FCMGT_PPzZ0_D", "fcmgt"},
+{"FCMGT_PPzZ0_H", "fcmgt"},
+{"FCMGT_PPzZ0_S", "fcmgt"},
+{"FCMGT_PPzZZ_D", "fcmgt"},
+{"FCMGT_PPzZZ_H", "fcmgt"},
+{"FCMGT_PPzZZ_S", "fcmgt"},
+{"FCMGTv1i16rz", "fcmgt"},
+{"FCMGTv1i32rz", "fcmgt"},
+{"FCMGTv1i64rz", "fcmgt"},
+{"FCMGTv2f32", "fcmgt"},
+{"FCMGTv2f64", "fcmgt"},
+{"FCMGTv2i32rz", "fcmgt"},
+{"FCMGTv2i64rz", "fcmgt"},
+{"FCMGTv4f16", "fcmgt"},
+{"FCMGTv4f32", "fcmgt"},
+{"FCMGTv4i16rz", "fcmgt"},
+{"FCMGTv4i32rz", "fcmgt"},
+{"FCMGTv8f16", "fcmgt"},
+{"FCMGTv8i16rz", "fcmgt"},
+{"FCMLA_ZPmZZ_D", "fcmla"},
+{"FCMLA_ZPmZZ_H", "fcmla"},
+{"FCMLA_ZPmZZ_S", "fcmla"},
+{"FCMLA_ZZZI_H", "fcmla"},
+{"FCMLA_ZZZI_S", "fcmla"},
+{"FCMLAv2f32", "fcmla"},
+{"FCMLAv2f64", "fcmla"},
+{"FCMLAv4f16", "fcmla"},
+{"FCMLAv4f16_indexed", "fcmla"},
+{"FCMLAv4f32", "fcmla"},
+{"FCMLAv4f32_indexed", "fcmla"},
+{"FCMLAv8f16", "fcmla"},
+{"FCMLAv8f16_indexed", "fcmla"},
+{"FCMLE_PPzZ0_D", "fcmle"},
+{"FCMLE_PPzZ0_H", "fcmle"},
+{"FCMLE_PPzZ0_S", "fcmle"},
+{"FCMLEv1i16rz", "fcmle"},
+{"FCMLEv1i32rz", "fcmle"},
+{"FCMLEv1i64rz", "fcmle"},
+{"FCMLEv2i32rz", "fcmle"},
+{"FCMLEv2i64rz", "fcmle"},
+{"FCMLEv4i16rz", "fcmle"},
+{"FCMLEv4i32rz", "fcmle"},
+{"FCMLEv8i16rz", "fcmle"},
+{"FCMLT_PPzZ0_D", "fcmlt"},
+{"FCMLT_PPzZ0_H", "fcmlt"},
+{"FCMLT_PPzZ0_S", "fcmlt"},
+{"FCMLTv1i16rz", "fcmlt"},
+{"FCMLTv1i32rz", "fcmlt"},
+{"FCMLTv1i64rz", "fcmlt"},
+{"FCMLTv2i32rz", "fcmlt"},
+{"FCMLTv2i64rz", "fcmlt"},
+{"FCMLTv4i16rz", "fcmlt"},
+{"FCMLTv4i32rz", "fcmlt"},
+{"FCMLTv8i16rz", "fcmlt"},
+{"FCMNE_PPzZ0_D", "fcmne"},
+{"FCMNE_PPzZ0_H", "fcmne"},
+{"FCMNE_PPzZ0_S", "fcmne"},
+{"FCMNE_PPzZZ_D", "fcmne"},
+{"FCMNE_PPzZZ_H", "fcmne"},
+{"FCMNE_PPzZZ_S", "fcmne"},
+{"FCMPDri", "fcmp"},
+{"FCMPDrr", "fcmp"},
+{"FCMPHri", "fcmp"},
+{"FCMPHrr", "fcmp"},
+{"FCMPSri", "fcmp"},
+{"FCMPSrr", "fcmp"},
+{"FCMPEDri", "fcmpe"},
+{"FCMPEDrr", "fcmpe"},
+{"FCMPEHri", "fcmpe"},
+{"FCMPEHrr", "fcmpe"},
+{"FCMPESri", "fcmpe"},
+{"FCMPESrr", "fcmpe"},
+{"FCMUO_PPzZZ_D", "fcmuo"},
+{"FCMUO_PPzZZ_H", "fcmuo"},
+{"FCMUO_PPzZZ_S", "fcmuo"},
+{"FCPY_ZPmI_D", "fcpy"},
+{"FCPY_ZPmI_H", "fcpy"},
+{"FCPY_ZPmI_S", "fcpy"},
+{"FCSELDrrr", "fcsel"},
+{"FCSELHrrr", "fcsel"},
+{"FCSELSrrr", "fcsel"},
+{"FCVTASDHr", "fcvtas"},
+{"FCVTASDSr", "fcvtas"},
+{"FCVTASSDr", "fcvtas"},
+{"FCVTASSHr", "fcvtas"},
+{"FCVTASUWDr", "fcvtas"},
+{"FCVTASUWHr", "fcvtas"},
+{"FCVTASUWSr", "fcvtas"},
+{"FCVTASUXDr", "fcvtas"},
+{"FCVTASUXHr", "fcvtas"},
+{"FCVTASUXSr", "fcvtas"},
+{"FCVTASv1f16", "fcvtas"},
+{"FCVTASv1i32", "fcvtas"},
+{"FCVTASv1i64", "fcvtas"},
+{"FCVTASv2f32", "fcvtas"},
+{"FCVTASv2f64", "fcvtas"},
+{"FCVTASv4f16", "fcvtas"},
+{"FCVTASv4f32", "fcvtas"},
+{"FCVTASv8f16", "fcvtas"},
+{"FCVTAUDHr", "fcvtau"},
+{"FCVTAUDSr", "fcvtau"},
+{"FCVTAUSDr", "fcvtau"},
+{"FCVTAUSHr", "fcvtau"},
+{"FCVTAUUWDr", "fcvtau"},
+{"FCVTAUUWHr", "fcvtau"},
+{"FCVTAUUWSr", "fcvtau"},
+{"FCVTAUUXDr", "fcvtau"},
+{"FCVTAUUXHr", "fcvtau"},
+{"FCVTAUUXSr", "fcvtau"},
+{"FCVTAUv1f16", "fcvtau"},
+{"FCVTAUv1i32", "fcvtau"},
+{"FCVTAUv1i64", "fcvtau"},
+{"FCVTAUv2f32", "fcvtau"},
+{"FCVTAUv2f64", "fcvtau"},
+{"FCVTAUv4f16", "fcvtau"},
+{"FCVTAUv4f32", "fcvtau"},
+{"FCVTAUv8f16", "fcvtau"},
+{"FCVTDHr", "fcvt"},
+{"FCVTDSr", "fcvt"},
+{"FCVTHDr", "fcvt"},
+{"FCVTHSr", "fcvt"},
+{"FCVTSDr", "fcvt"},
+{"FCVTSHr", "fcvt"},
+{"FCVT_2ZZ_H_S", "fcvt"},
+{"FCVT_Z2Z_HtoB", "fcvt"},
+{"FCVT_Z2Z_StoH", "fcvt"},
+{"FCVT_Z4Z_StoB", "fcvt"},
+{"FCVT_ZPmZ_DtoH", "fcvt"},
+{"FCVT_ZPmZ_DtoS", "fcvt"},
+{"FCVT_ZPmZ_HtoD", "fcvt"},
+{"FCVT_ZPmZ_HtoS", "fcvt"},
+{"FCVT_ZPmZ_StoD", "fcvt"},
+{"FCVT_ZPmZ_StoH", "fcvt"},
+{"FCVT_ZPzZ_DtoH", "fcvt"},
+{"FCVT_ZPzZ_DtoS", "fcvt"},
+{"FCVT_ZPzZ_HtoD", "fcvt"},
+{"FCVT_ZPzZ_HtoS", "fcvt"},
+{"FCVT_ZPzZ_StoD", "fcvt"},
+{"FCVT_ZPzZ_StoH", "fcvt"},
+{"FCVTLT_ZPmZ_HtoS", "fcvtlt"},
+{"FCVTLT_ZPmZ_StoD", "fcvtlt"},
+{"FCVTLT_ZPzZ_HtoS", "fcvtlt"},
+{"FCVTLT_ZPzZ_StoD", "fcvtlt"},
+{"FCVTL_2ZZ_H_S", "fcvtl"},
+{"FCVTLv2i32", "fcvtl"},
+{"FCVTLv4i16", "fcvtl"},
+{"FCVTLv4i32", "fcvtl2"},
+{"FCVTLv8i16", "fcvtl2"},
+{"FCVTMSDHr", "fcvtms"},
+{"FCVTMSDSr", "fcvtms"},
+{"FCVTMSSDr", "fcvtms"},
+{"FCVTMSSHr", "fcvtms"},
+{"FCVTMSUWDr", "fcvtms"},
+{"FCVTMSUWHr", "fcvtms"},
+{"FCVTMSUWSr", "fcvtms"},
+{"FCVTMSUXDr", "fcvtms"},
+{"FCVTMSUXHr", "fcvtms"},
+{"FCVTMSUXSr", "fcvtms"},
+{"FCVTMSv1f16", "fcvtms"},
+{"FCVTMSv1i32", "fcvtms"},
+{"FCVTMSv1i64", "fcvtms"},
+{"FCVTMSv2f32", "fcvtms"},
+{"FCVTMSv2f64", "fcvtms"},
+{"FCVTMSv4f16", "fcvtms"},
+{"FCVTMSv4f32", "fcvtms"},
+{"FCVTMSv8f16", "fcvtms"},
+{"FCVTMUDHr", "fcvtmu"},
+{"FCVTMUDSr", "fcvtmu"},
+{"FCVTMUSDr", "fcvtmu"},
+{"FCVTMUSHr", "fcvtmu"},
+{"FCVTMUUWDr", "fcvtmu"},
+{"FCVTMUUWHr", "fcvtmu"},
+{"FCVTMUUWSr", "fcvtmu"},
+{"FCVTMUUXDr", "fcvtmu"},
+{"FCVTMUUXHr", "fcvtmu"},
+{"FCVTMUUXSr", "fcvtmu"},
+{"FCVTMUv1f16", "fcvtmu"},
+{"FCVTMUv1i32", "fcvtmu"},
+{"FCVTMUv1i64", "fcvtmu"},
+{"FCVTMUv2f32", "fcvtmu"},
+{"FCVTMUv2f64", "fcvtmu"},
+{"FCVTMUv4f16", "fcvtmu"},
+{"FCVTMUv4f32", "fcvtmu"},
+{"FCVTMUv8f16", "fcvtmu"},
+{"FCVTNB_Z2Z_StoB", "fcvtnb"},
+{"FCVTNSDHr", "fcvtns"},
+{"FCVTNSDSr", "fcvtns"},
+{"FCVTNSSDr", "fcvtns"},
+{"FCVTNSSHr", "fcvtns"},
+{"FCVTNSUWDr", "fcvtns"},
+{"FCVTNSUWHr", "fcvtns"},
+{"FCVTNSUWSr", "fcvtns"},
+{"FCVTNSUXDr", "fcvtns"},
+{"FCVTNSUXHr", "fcvtns"},
+{"FCVTNSUXSr", "fcvtns"},
+{"FCVTNSv1f16", "fcvtns"},
+{"FCVTNSv1i32", "fcvtns"},
+{"FCVTNSv1i64", "fcvtns"},
+{"FCVTNSv2f32", "fcvtns"},
+{"FCVTNSv2f64", "fcvtns"},
+{"FCVTNSv4f16", "fcvtns"},
+{"FCVTNSv4f32", "fcvtns"},
+{"FCVTNSv8f16", "fcvtns"},
+{"FCVTNT_Z2Z_StoB", "fcvtnt"},
+{"FCVTNT_ZPmZ_DtoS", "fcvtnt"},
+{"FCVTNT_ZPmZ_StoH", "fcvtnt"},
+{"FCVTNT_ZPzZ_DtoS", "fcvtnt"},
+{"FCVTNT_ZPzZ_StoH", "fcvtnt"},
+{"FCVTNUDHr", "fcvtnu"},
+{"FCVTNUDSr", "fcvtnu"},
+{"FCVTNUSDr", "fcvtnu"},
+{"FCVTNUSHr", "fcvtnu"},
+{"FCVTNUUWDr", "fcvtnu"},
+{"FCVTNUUWHr", "fcvtnu"},
+{"FCVTNUUWSr", "fcvtnu"},
+{"FCVTNUUXDr", "fcvtnu"},
+{"FCVTNUUXHr", "fcvtnu"},
+{"FCVTNUUXSr", "fcvtnu"},
+{"FCVTNUv1f16", "fcvtnu"},
+{"FCVTNUv1i32", "fcvtnu"},
+{"FCVTNUv1i64", "fcvtnu"},
+{"FCVTNUv2f32", "fcvtnu"},
+{"FCVTNUv2f64", "fcvtnu"},
+{"FCVTNUv4f16", "fcvtnu"},
+{"FCVTNUv4f32", "fcvtnu"},
+{"FCVTNUv8f16", "fcvtnu"},
+{"FCVTN_F16v8f8", "fcvtn"},
+{"FCVTN_F16v16f8", "fcvtn"},
+{"FCVTN_F32v8f8", "fcvtn"},
+{"FCVTN_Z2Z_HtoB", "fcvtn"},
+{"FCVTN_Z2Z_StoH", "fcvtn"},
+{"FCVTN_Z4Z_StoB", "fcvtn"},
+{"FCVTNv2i32", "fcvtn"},
+{"FCVTNv4i16", "fcvtn"},
+{"FCVTN_F322v16f8", "fcvtn2"},
+{"FCVTNv4i32", "fcvtn2"},
+{"FCVTNv8i16", "fcvtn2"},
+{"FCVTPSDHr", "fcvtps"},
+{"FCVTPSDSr", "fcvtps"},
+{"FCVTPSSDr", "fcvtps"},
+{"FCVTPSSHr", "fcvtps"},
+{"FCVTPSUWDr", "fcvtps"},
+{"FCVTPSUWHr", "fcvtps"},
+{"FCVTPSUWSr", "fcvtps"},
+{"FCVTPSUXDr", "fcvtps"},
+{"FCVTPSUXHr", "fcvtps"},
+{"FCVTPSUXSr", "fcvtps"},
+{"FCVTPSv1f16", "fcvtps"},
+{"FCVTPSv1i32", "fcvtps"},
+{"FCVTPSv1i64", "fcvtps"},
+{"FCVTPSv2f32", "fcvtps"},
+{"FCVTPSv2f64", "fcvtps"},
+{"FCVTPSv4f16", "fcvtps"},
+{"FCVTPSv4f32", "fcvtps"},
+{"FCVTPSv8f16", "fcvtps"},
+{"FCVTPUDHr", "fcvtpu"},
+{"FCVTPUDSr", "fcvtpu"},
+{"FCVTPUSDr", "fcvtpu"},
+{"FCVTPUSHr", "fcvtpu"},
+{"FCVTPUUWDr", "fcvtpu"},
+{"FCVTPUUWHr", "fcvtpu"},
+{"FCVTPUUWSr", "fcvtpu"},
+{"FCVTPUUXDr", "fcvtpu"},
+{"FCVTPUUXHr", "fcvtpu"},
+{"FCVTPUUXSr", "fcvtpu"},
+{"FCVTPUv1f16", "fcvtpu"},
+{"FCVTPUv1i32", "fcvtpu"},
+{"FCVTPUv1i64", "fcvtpu"},
+{"FCVTPUv2f32", "fcvtpu"},
+{"FCVTPUv2f64", "fcvtpu"},
+{"FCVTPUv4f16", "fcvtpu"},
+{"FCVTPUv4f32", "fcvtpu"},
+{"FCVTPUv8f16", "fcvtpu"},
+{"FCVTXNT_ZPmZ_DtoS", "fcvtxnt"},
+{"FCVTXNT_ZPzZ_StoD", "fcvtxnt"},
+{"FCVTXNv1i64", "fcvtxn"},
+{"FCVTXNv2f32", "fcvtxn"},
+{"FCVTXNv4f32", "fcvtxn2"},
+{"FCVTX_ZPmZ_DtoS", "fcvtx"},
+{"FCVTX_ZPzZ_DtoS", "fcvtx"},
+{"FCVTZSDHr", "fcvtzs"},
+{"FCVTZSDSr", "fcvtzs"},
+{"FCVTZSSDr", "fcvtzs"},
+{"FCVTZSSHr", "fcvtzs"},
+{"FCVTZSSWDri", "fcvtzs"},
+{"FCVTZSSWHri", "fcvtzs"},
+{"FCVTZSSWSri", "fcvtzs"},
+{"FCVTZSSXDri", "fcvtzs"},
+{"FCVTZSSXHri", "fcvtzs"},
+{"FCVTZSSXSri", "fcvtzs"},
+{"FCVTZSUWDr", "fcvtzs"},
+{"FCVTZSUWHr", "fcvtzs"},
+{"FCVTZSUWSr", "fcvtzs"},
+{"FCVTZSUXDr", "fcvtzs"},
+{"FCVTZSUXHr", "fcvtzs"},
+{"FCVTZSUXSr", "fcvtzs"},
+{"FCVTZS_2Z2Z_StoS", "fcvtzs"},
+{"FCVTZS_4Z4Z_StoS", "fcvtzs"},
+{"FCVTZS_ZPmZ_DtoD", "fcvtzs"},
+{"FCVTZS_ZPmZ_DtoS", "fcvtzs"},
+{"FCVTZS_ZPmZ_HtoD", "fcvtzs"},
+{"FCVTZS_ZPmZ_HtoH", "fcvtzs"},
+{"FCVTZS_ZPmZ_HtoS", "fcvtzs"},
+{"FCVTZS_ZPmZ_StoD", "fcvtzs"},
+{"FCVTZS_ZPmZ_StoS", "fcvtzs"},
+{"FCVTZS_ZPzZ_DtoD", "fcvtzs"},
+{"FCVTZS_ZPzZ_DtoS", "fcvtzs"},
+{"FCVTZS_ZPzZ_HtoD", "fcvtzs"},
+{"FCVTZS_ZPzZ_HtoH", "fcvtzs"},
+{"FCVTZS_ZPzZ_HtoS", "fcvtzs"},
+{"FCVTZS_ZPzZ_StoD", "fcvtzs"},
+{"FCVTZS_ZPzZ_StoS", "fcvtzs"},
+{"FCVTZSd", "fcvtzs"},
+{"FCVTZSh", "fcvtzs"},
+{"FCVTZSs", "fcvtzs"},
+{"FCVTZSv1f16", "fcvtzs"},
+{"FCVTZSv1i32", "fcvtzs"},
+{"FCVTZSv1i64", "fcvtzs"},
+{"FCVTZSv2f32", "fcvtzs"},
+{"FCVTZSv2f64", "fcvtzs"},
+{"FCVTZSv2i32_shift", "fcvtzs"},
+{"FCVTZSv2i64_shift", "fcvtzs"},
+{"FCVTZSv4f16", "fcvtzs"},
+{"FCVTZSv4f32", "fcvtzs"},
+{"FCVTZSv4i16_shift", "fcvtzs"},
+{"FCVTZSv4i32_shift", "fcvtzs"},
+{"FCVTZSv8f16", "fcvtzs"},
+{"FCVTZSv8i16_shift", "fcvtzs"},
+{"FCVTZSN_Z2Z_DtoS", "fcvtzsn"},
+{"FCVTZSN_Z2Z_HtoB", "fcvtzsn"},
+{"FCVTZSN_Z2Z_StoH", "fcvtzsn"},
+{"FCVTZUDHr", "fcvtzu"},
+{"FCVTZUDSr", "fcvtzu"},
+{"FCVTZUSDr", "fcvtzu"},
+{"FCVTZUSHr", "fcvtzu"},
+{"FCVTZUSWDri", "fcvtzu"},
+{"FCVTZUSWHri", "fcvtzu"},
+{"FCVTZUSWSri", "fcvtzu"},
+{"FCVTZUSXDri", "fcvtzu"},
+{"FCVTZUSXHri", "fcvtzu"},
+{"FCVTZUSXSri", "fcvtzu"},
+{"FCVTZUUWDr", "fcvtzu"},
+{"FCVTZUUWHr", "fcvtzu"},
+{"FCVTZUUWSr", "fcvtzu"},
+{"FCVTZUUXDr", "fcvtzu"},
+{"FCVTZUUXHr", "fcvtzu"},
+{"FCVTZUUXSr", "fcvtzu"},
+{"FCVTZU_2Z2Z_StoS", "fcvtzu"},
+{"FCVTZU_4Z4Z_StoS", "fcvtzu"},
+{"FCVTZU_ZPmZ_DtoD", "fcvtzu"},
+{"FCVTZU_ZPmZ_DtoS", "fcvtzu"},
+{"FCVTZU_ZPmZ_HtoD", "fcvtzu"},
+{"FCVTZU_ZPmZ_HtoH", "fcvtzu"},
+{"FCVTZU_ZPmZ_HtoS", "fcvtzu"},
+{"FCVTZU_ZPmZ_StoD", "fcvtzu"},
+{"FCVTZU_ZPmZ_StoS", "fcvtzu"},
+{"FCVTZU_ZPzZ_DtoD", "fcvtzu"},
+{"FCVTZU_ZPzZ_DtoS", "fcvtzu"},
+{"FCVTZU_ZPzZ_HtoD", "fcvtzu"},
+{"FCVTZU_ZPzZ_HtoH", "fcvtzu"},
+{"FCVTZU_ZPzZ_HtoS", "fcvtzu"},
+{"FCVTZU_ZPzZ_StoD", "fcvtzu"},
+{"FCVTZU_ZPzZ_StoS", "fcvtzu"},
+{"FCVTZUd", "fcvtzu"},
+{"FCVTZUh", "fcvtzu"},
+{"FCVTZUs", "fcvtzu"},
+{"FCVTZUv1f16", "fcvtzu"},
+{"FCVTZUv1i32", "fcvtzu"},
+{"FCVTZUv1i64", "fcvtzu"},
+{"FCVTZUv2f32", "fcvtzu"},
+{"FCVTZUv2f64", "fcvtzu"},
+{"FCVTZUv2i32_shift", "fcvtzu"},
+{"FCVTZUv2i64_shift", "fcvtzu"},
+{"FCVTZUv4f16", "fcvtzu"},
+{"FCVTZUv4f32", "fcvtzu"},
+{"FCVTZUv4i16_shift", "fcvtzu"},
+{"FCVTZUv4i32_shift", "fcvtzu"},
+{"FCVTZUv8f16", "fcvtzu"},
+{"FCVTZUv8i16_shift", "fcvtzu"},
+{"FCVTZUN_Z2Z_DtoS", "fcvtzun"},
+{"FCVTZUN_Z2Z_HtoB", "fcvtzun"},
+{"FCVTZUN_Z2Z_StoH", "fcvtzun"},
+{"FDIVDrr", "fdiv"},
+{"FDIVHrr", "fdiv"},
+{"FDIVSrr", "fdiv"},
+{"FDIV_ZPmZ_D", "fdiv"},
+{"FDIV_ZPmZ_H", "fdiv"},
+{"FDIV_ZPmZ_S", "fdiv"},
+{"FDIVv2f32", "fdiv"},
+{"FDIVv2f64", "fdiv"},
+{"FDIVv4f16", "fdiv"},
+{"FDIVv4f32", "fdiv"},
+{"FDIVv8f16", "fdiv"},
+{"FDIVR_ZPmZ_D", "fdivr"},
+{"FDIVR_ZPmZ_H", "fdivr"},
+{"FDIVR_ZPmZ_S", "fdivr"},
+{"FDOT_VG2_M2Z2Z_BtoH", "fdot"},
+{"FDOT_VG2_M2Z2Z_BtoS", "fdot"},
+{"FDOT_VG2_M2Z2Z_HtoS", "fdot"},
+{"FDOT_VG2_M2ZZI_BtoH", "fdot"},
+{"FDOT_VG2_M2ZZI_BtoS", "fdot"},
+{"FDOT_VG2_M2ZZI_HtoS", "fdot"},
+{"FDOT_VG2_M2ZZ_BtoH", "fdot"},
+{"FDOT_VG2_M2ZZ_BtoS", "fdot"},
+{"FDOT_VG2_M2ZZ_HtoS", "fdot"},
+{"FDOT_VG4_M4Z4Z_BtoH", "fdot"},
+{"FDOT_VG4_M4Z4Z_BtoS", "fdot"},
+{"FDOT_VG4_M4Z4Z_HtoS", "fdot"},
+{"FDOT_VG4_M4ZZI_BtoH", "fdot"},
+{"FDOT_VG4_M4ZZI_BtoS", "fdot"},
+{"FDOT_VG4_M4ZZI_HtoS", "fdot"},
+{"FDOT_VG4_M4ZZ_BtoH", "fdot"},
+{"FDOT_VG4_M4ZZ_BtoS", "fdot"},
+{"FDOT_VG4_M4ZZ_HtoS", "fdot"},
+{"FDOT_ZZZI_BtoH", "fdot"},
+{"FDOT_ZZZI_BtoS", "fdot"},
+{"FDOT_ZZZI_S", "fdot"},
+{"FDOT_ZZZ_BtoH", "fdot"},
+{"FDOT_ZZZ_BtoS", "fdot"},
+{"FDOT_ZZZ_S", "fdot"},
+{"FDOTlanev2f32", "fdot"},
+{"FDOTlanev4f16", "fdot"},
+{"FDOTlanev4f16_v2f32", "fdot"},
+{"FDOTlanev4f32", "fdot"},
+{"FDOTlanev8f16", "fdot"},
+{"FDOTlanev8f16_v4f32", "fdot"},
+{"FDOTv2f32", "fdot"},
+{"FDOTv4f16", "fdot"},
+{"FDOTv4f16_v2f32", "fdot"},
+{"FDOTv4f32", "fdot"},
+{"FDOTv8f16", "fdot"},
+{"FDOTv8f16_v4f32", "fdot"},
+{"FDUP_ZI_D", "fdup"},
+{"FDUP_ZI_H", "fdup"},
+{"FDUP_ZI_S", "fdup"},
+{"FEXPA_ZZ_D", "fexpa"},
+{"FEXPA_ZZ_H", "fexpa"},
+{"FEXPA_ZZ_S", "fexpa"},
+{"FIRSTP_XPP_B", "firstp"},
+{"FIRSTP_XPP_D", "firstp"},
+{"FIRSTP_XPP_H", "firstp"},
+{"FIRSTP_XPP_S", "firstp"},
+{"FJCVTZS", "fjcvtzs"},
+{"FLOGB_ZPmZ_D", "flogb"},
+{"FLOGB_ZPmZ_H", "flogb"},
+{"FLOGB_ZPmZ_S", "flogb"},
+{"FLOGB_ZPzZ_D", "flogb"},
+{"FLOGB_ZPzZ_H", "flogb"},
+{"FLOGB_ZPzZ_S", "flogb"},
+{"FMADDDrrr", "fmadd"},
+{"FMADDHrrr", "fmadd"},
+{"FMADDSrrr", "fmadd"},
+{"FMAD_ZPmZZ_D", "fmad"},
+{"FMAD_ZPmZZ_H", "fmad"},
+{"FMAD_ZPmZZ_S", "fmad"},
+{"FMAXDrr", "fmax"},
+{"FMAXHrr", "fmax"},
+{"FMAXSrr", "fmax"},
+{"FMAX_VG2_2Z2Z_D", "fmax"},
+{"FMAX_VG2_2Z2Z_H", "fmax"},
+{"FMAX_VG2_2Z2Z_S", "fmax"},
+{"FMAX_VG2_2ZZ_D", "fmax"},
+{"FMAX_VG2_2ZZ_H", "fmax"},
+{"FMAX_VG2_2ZZ_S", "fmax"},
+{"FMAX_VG4_4Z4Z_D", "fmax"},
+{"FMAX_VG4_4Z4Z_H", "fmax"},
+{"FMAX_VG4_4Z4Z_S", "fmax"},
+{"FMAX_VG4_4ZZ_D", "fmax"},
+{"FMAX_VG4_4ZZ_H", "fmax"},
+{"FMAX_VG4_4ZZ_S", "fmax"},
+{"FMAX_ZPmI_D", "fmax"},
+{"FMAX_ZPmI_H", "fmax"},
+{"FMAX_ZPmI_S", "fmax"},
+{"FMAX_ZPmZ_D", "fmax"},
+{"FMAX_ZPmZ_H", "fmax"},
+{"FMAX_ZPmZ_S", "fmax"},
+{"FMAXv2f32", "fmax"},
+{"FMAXv2f64", "fmax"},
+{"FMAXv4f16", "fmax"},
+{"FMAXv4f32", "fmax"},
+{"FMAXv8f16", "fmax"},
+{"FMAXNMDrr", "fmaxnm"},
+{"FMAXNMHrr", "fmaxnm"},
+{"FMAXNMSrr", "fmaxnm"},
+{"FMAXNM_VG2_2Z2Z_D", "fmaxnm"},
+{"FMAXNM_VG2_2Z2Z_H", "fmaxnm"},
+{"FMAXNM_VG2_2Z2Z_S", "fmaxnm"},
+{"FMAXNM_VG2_2ZZ_D", "fmaxnm"},
+{"FMAXNM_VG2_2ZZ_H", "fmaxnm"},
+{"FMAXNM_VG2_2ZZ_S", "fmaxnm"},
+{"FMAXNM_VG4_4Z4Z_D", "fmaxnm"},
+{"FMAXNM_VG4_4Z4Z_H", "fmaxnm"},
+{"FMAXNM_VG4_4Z4Z_S", "fmaxnm"},
+{"FMAXNM_VG4_4ZZ_D", "fmaxnm"},
+{"FMAXNM_VG4_4ZZ_H", "fmaxnm"},
+{"FMAXNM_VG4_4ZZ_S", "fmaxnm"},
+{"FMAXNM_ZPmI_D", "fmaxnm"},
+{"FMAXNM_ZPmI_H", "fmaxnm"},
+{"FMAXNM_ZPmI_S", "fmaxnm"},
+{"FMAXNM_ZPmZ_D", "fmaxnm"},
+{"FMAXNM_ZPmZ_H", "fmaxnm"},
+{"FMAXNM_ZPmZ_S", "fmaxnm"},
+{"FMAXNMv2f32", "fmaxnm"},
+{"FMAXNMv2f64", "fmaxnm"},
+{"FMAXNMv4f16", "fmaxnm"},
+{"FMAXNMv4f32", "fmaxnm"},
+{"FMAXNMv8f16", "fmaxnm"},
+{"FMAXNMP_ZPmZZ_D", "fmaxnmp"},
+{"FMAXNMP_ZPmZZ_H", "fmaxnmp"},
+{"FMAXNMP_ZPmZZ_S", "fmaxnmp"},
+{"FMAXNMPv2f32", "fmaxnmp"},
+{"FMAXNMPv2f64", "fmaxnmp"},
+{"FMAXNMPv2i16p", "fmaxnmp"},
+{"FMAXNMPv2i32p", "fmaxnmp"},
+{"FMAXNMPv2i64p", "fmaxnmp"},
+{"FMAXNMPv4f16", "fmaxnmp"},
+{"FMAXNMPv4f32", "fmaxnmp"},
+{"FMAXNMPv8f16", "fmaxnmp"},
+{"FMAXNMQV_D", "fmaxnmqv"},
+{"FMAXNMQV_H", "fmaxnmqv"},
+{"FMAXNMQV_S", "fmaxnmqv"},
+{"FMAXNMV_VPZ_D", "fmaxnmv"},
+{"FMAXNMV_VPZ_H", "fmaxnmv"},
+{"FMAXNMV_VPZ_S", "fmaxnmv"},
+{"FMAXNMVv4i16v", "fmaxnmv"},
+{"FMAXNMVv4i32v", "fmaxnmv"},
+{"FMAXNMVv8i16v", "fmaxnmv"},
+{"FMAXP_ZPmZZ_D", "fmaxp"},
+{"FMAXP_ZPmZZ_H", "fmaxp"},
+{"FMAXP_ZPmZZ_S", "fmaxp"},
+{"FMAXPv2f32", "fmaxp"},
+{"FMAXPv2f64", "fmaxp"},
+{"FMAXPv2i16p", "fmaxp"},
+{"FMAXPv2i32p", "fmaxp"},
+{"FMAXPv2i64p", "fmaxp"},
+{"FMAXPv4f16", "fmaxp"},
+{"FMAXPv4f32", "fmaxp"},
+{"FMAXPv8f16", "fmaxp"},
+{"FMAXQV_D", "fmaxqv"},
+{"FMAXQV_H", "fmaxqv"},
+{"FMAXQV_S", "fmaxqv"},
+{"FMAXV_VPZ_D", "fmaxv"},
+{"FMAXV_VPZ_H", "fmaxv"},
+{"FMAXV_VPZ_S", "fmaxv"},
+{"FMAXVv4i16v", "fmaxv"},
+{"FMAXVv4i32v", "fmaxv"},
+{"FMAXVv8i16v", "fmaxv"},
+{"FMINDrr", "fmin"},
+{"FMINHrr", "fmin"},
+{"FMINSrr", "fmin"},
+{"FMIN_VG2_2Z2Z_D", "fmin"},
+{"FMIN_VG2_2Z2Z_H", "fmin"},
+{"FMIN_VG2_2Z2Z_S", "fmin"},
+{"FMIN_VG2_2ZZ_D", "fmin"},
+{"FMIN_VG2_2ZZ_H", "fmin"},
+{"FMIN_VG2_2ZZ_S", "fmin"},
+{"FMIN_VG4_4Z4Z_D", "fmin"},
+{"FMIN_VG4_4Z4Z_H", "fmin"},
+{"FMIN_VG4_4Z4Z_S", "fmin"},
+{"FMIN_VG4_4ZZ_D", "fmin"},
+{"FMIN_VG4_4ZZ_H", "fmin"},
+{"FMIN_VG4_4ZZ_S", "fmin"},
+{"FMIN_ZPmI_D", "fmin"},
+{"FMIN_ZPmI_H", "fmin"},
+{"FMIN_ZPmI_S", "fmin"},
+{"FMIN_ZPmZ_D", "fmin"},
+{"FMIN_ZPmZ_H", "fmin"},
+{"FMIN_ZPmZ_S", "fmin"},
+{"FMINv2f32", "fmin"},
+{"FMINv2f64", "fmin"},
+{"FMINv4f16", "fmin"},
+{"FMINv4f32", "fmin"},
+{"FMINv8f16", "fmin"},
+{"FMINNMDrr", "fminnm"},
+{"FMINNMHrr", "fminnm"},
+{"FMINNMSrr", "fminnm"},
+{"FMINNM_VG2_2Z2Z_D", "fminnm"},
+{"FMINNM_VG2_2Z2Z_H", "fminnm"},
+{"FMINNM_VG2_2Z2Z_S", "fminnm"},
+{"FMINNM_VG2_2ZZ_D", "fminnm"},
+{"FMINNM_VG2_2ZZ_H", "fminnm"},
+{"FMINNM_VG2_2ZZ_S", "fminnm"},
+{"FMINNM_VG4_4Z4Z_D", "fminnm"},
+{"FMINNM_VG4_4Z4Z_H", "fminnm"},
+{"FMINNM_VG4_4Z4Z_S", "fminnm"},
+{"FMINNM_VG4_4ZZ_D", "fminnm"},
+{"FMINNM_VG4_4ZZ_H", "fminnm"},
+{"FMINNM_VG4_4ZZ_S", "fminnm"},
+{"FMINNM_ZPmI_D", "fminnm"},
+{"FMINNM_ZPmI_H", "fminnm"},
+{"FMINNM_ZPmI_S", "fminnm"},
+{"FMINNM_ZPmZ_D", "fminnm"},
+{"FMINNM_ZPmZ_H", "fminnm"},
+{"FMINNM_ZPmZ_S", "fminnm"},
+{"FMINNMv2f32", "fminnm"},
+{"FMINNMv2f64", "fminnm"},
+{"FMINNMv4f16", "fminnm"},
+{"FMINNMv4f32", "fminnm"},
+{"FMINNMv8f16", "fminnm"},
+{"FMINNMP_ZPmZZ_D", "fminnmp"},
+{"FMINNMP_ZPmZZ_H", "fminnmp"},
+{"FMINNMP_ZPmZZ_S", "fminnmp"},
+{"FMINNMPv2f32", "fminnmp"},
+{"FMINNMPv2f64", "fminnmp"},
+{"FMINNMPv2i16p", "fminnmp"},
+{"FMINNMPv2i32p", "fminnmp"},
+{"FMINNMPv2i64p", "fminnmp"},
+{"FMINNMPv4f16", "fminnmp"},
+{"FMINNMPv4f32", "fminnmp"},
+{"FMINNMPv8f16", "fminnmp"},
+{"FMINNMQV_D", "fminnmqv"},
+{"FMINNMQV_H", "fminnmqv"},
+{"FMINNMQV_S", "fminnmqv"},
+{"FMINNMV_VPZ_D", "fminnmv"},
+{"FMINNMV_VPZ_H", "fminnmv"},
+{"FMINNMV_VPZ_S", "fminnmv"},
+{"FMINNMVv4i16v", "fminnmv"},
+{"FMINNMVv4i32v", "fminnmv"},
+{"FMINNMVv8i16v", "fminnmv"},
+{"FMINP_ZPmZZ_D", "fminp"},
+{"FMINP_ZPmZZ_H", "fminp"},
+{"FMINP_ZPmZZ_S", "fminp"},
+{"FMINPv2f32", "fminp"},
+{"FMINPv2f64", "fminp"},
+{"FMINPv2i16p", "fminp"},
+{"FMINPv2i32p", "fminp"},
+{"FMINPv2i64p", "fminp"},
+{"FMINPv4f16", "fminp"},
+{"FMINPv4f32", "fminp"},
+{"FMINPv8f16", "fminp"},
+{"FMINQV_D", "fminqv"},
+{"FMINQV_H", "fminqv"},
+{"FMINQV_S", "fminqv"},
+{"FMINV_VPZ_D", "fminv"},
+{"FMINV_VPZ_H", "fminv"},
+{"FMINV_VPZ_S", "fminv"},
+{"FMINVv4i16v", "fminv"},
+{"FMINVv4i32v", "fminv"},
+{"FMINVv8i16v", "fminv"},
+{"FMLAL2lanev4f16", "fmlal2"},
+{"FMLAL2lanev8f16", "fmlal2"},
+{"FMLAL2v4f16", "fmlal2"},
+{"FMLAL2v8f16", "fmlal2"},
+{"FMLALB_ZZZ", "fmlalb"},
+{"FMLALB_ZZZI", "fmlalb"},
+{"FMLALB_ZZZI_SHH", "fmlalb"},
+{"FMLALB_ZZZ_SHH", "fmlalb"},
+{"FMLALBlanev8f16", "fmlalb"},
+{"FMLALBv16i8_v8f16", "fmlalb"},
+{"FMLALLBB_ZZZ", "fmlallbb"},
+{"FMLALLBB_ZZZI", "fmlallbb"},
+{"FMLALLBBlanev4f32", "fmlallbb"},
+{"FMLALLBBv4f32", "fmlallbb"},
+{"FMLALLBT_ZZZ", "fmlallbt"},
+{"FMLALLBT_ZZZI", "fmlallbt"},
+{"FMLALLBTlanev4f32", "fmlallbt"},
+{"FMLALLBTv4f32", "fmlallbt"},
+{"FMLALLTB_ZZZ", "fmlalltb"},
+{"FMLALLTB_ZZZI", "fmlalltb"},
+{"FMLALLTBlanev4f32", "fmlalltb"},
+{"FMLALLTBv4f32", "fmlalltb"},
+{"FMLALLTT_ZZZ", "fmlalltt"},
+{"FMLALLTT_ZZZI", "fmlalltt"},
+{"FMLALLTTlanev4f32", "fmlalltt"},
+{"FMLALLTTv4f32", "fmlalltt"},
+{"FMLALL_MZZI_BtoS", "fmlall"},
+{"FMLALL_MZZ_BtoS", "fmlall"},
+{"FMLALL_VG2_M2Z2Z_BtoS", "fmlall"},
+{"FMLALL_VG2_M2ZZI_BtoS", "fmlall"},
+{"FMLALL_VG2_M2ZZ_BtoS", "fmlall"},
+{"FMLALL_VG4_M4Z4Z_BtoS", "fmlall"},
+{"FMLALL_VG4_M4ZZI_BtoS", "fmlall"},
+{"FMLALL_VG4_M4ZZ_BtoS", "fmlall"},
+{"FMLALT_ZZZ", "fmlalt"},
+{"FMLALT_ZZZI", "fmlalt"},
+{"FMLALT_ZZZI_SHH", "fmlalt"},
+{"FMLALT_ZZZ_SHH", "fmlalt"},
+{"FMLALTlanev8f16", "fmlalt"},
+{"FMLALTv16i8_v8f16", "fmlalt"},
+{"FMLAL_MZZI_BtoH", "fmlal"},
+{"FMLAL_MZZI_HtoS", "fmlal"},
+{"FMLAL_MZZ_HtoS", "fmlal"},
+{"FMLAL_VG2_M2Z2Z_BtoH", "fmlal"},
+{"FMLAL_VG2_M2Z2Z_HtoS", "fmlal"},
+{"FMLAL_VG2_M2ZZI_BtoH", "fmlal"},
+{"FMLAL_VG2_M2ZZI_HtoS", "fmlal"},
+{"FMLAL_VG2_M2ZZ_BtoH", "fmlal"},
+{"FMLAL_VG2_M2ZZ_HtoS", "fmlal"},
+{"FMLAL_VG2_MZZ_BtoH", "fmlal"},
+{"FMLAL_VG4_M4Z4Z_BtoH", "fmlal"},
+{"FMLAL_VG4_M4Z4Z_HtoS", "fmlal"},
+{"FMLAL_VG4_M4ZZI_BtoH", "fmlal"},
+{"FMLAL_VG4_M4ZZI_HtoS", "fmlal"},
+{"FMLAL_VG4_M4ZZ_BtoH", "fmlal"},
+{"FMLAL_VG4_M4ZZ_HtoS", "fmlal"},
+{"FMLALlanev4f16", "fmlal"},
+{"FMLALlanev8f16", "fmlal"},
+{"FMLALv4f16", "fmlal"},
+{"FMLALv8f16", "fmlal"},
+{"FMLA_VG2_M2Z2Z_D", "fmla"},
+{"FMLA_VG2_M2Z2Z_H", "fmla"},
+{"FMLA_VG2_M2Z2Z_S", "fmla"},
+{"FMLA_VG2_M2ZZI_D", "fmla"},
+{"FMLA_VG2_M2ZZI_H", "fmla"},
+{"FMLA_VG2_M2ZZI_S", "fmla"},
+{"FMLA_VG2_M2ZZ_D", "fmla"},
+{"FMLA_VG2_M2ZZ_H", "fmla"},
+{"FMLA_VG2_M2ZZ_S", "fmla"},
+{"FMLA_VG4_M4Z4Z_D", "fmla"},
+{"FMLA_VG4_M4Z4Z_H", "fmla"},
+{"FMLA_VG4_M4Z4Z_S", "fmla"},
+{"FMLA_VG4_M4ZZI_D", "fmla"},
+{"FMLA_VG4_M4ZZI_H", "fmla"},
+{"FMLA_VG4_M4ZZI_S", "fmla"},
+{"FMLA_VG4_M4ZZ_D", "fmla"},
+{"FMLA_VG4_M4ZZ_H", "fmla"},
+{"FMLA_VG4_M4ZZ_S", "fmla"},
+{"FMLA_ZPmZZ_D", "fmla"},
+{"FMLA_ZPmZZ_H", "fmla"},
+{"FMLA_ZPmZZ_S", "fmla"},
+{"FMLA_ZZZI_D", "fmla"},
+{"FMLA_ZZZI_H", "fmla"},
+{"FMLA_ZZZI_S", "fmla"},
+{"FMLAv1i16_indexed", "fmla"},
+{"FMLAv1i32_indexed", "fmla"},
+{"FMLAv1i64_indexed", "fmla"},
+{"FMLAv2f32", "fmla"},
+{"FMLAv2f64", "fmla"},
+{"FMLAv2i32_indexed", "fmla"},
+{"FMLAv2i64_indexed", "fmla"},
+{"FMLAv4f16", "fmla"},
+{"FMLAv4f32", "fmla"},
+{"FMLAv4i16_indexed", "fmla"},
+{"FMLAv4i32_indexed", "fmla"},
+{"FMLAv8f16", "fmla"},
+{"FMLAv8i16_indexed", "fmla"},
+{"FMLLA_ZZZ_HtoS", "fmmla"},
+{"FMMLA_ZZZ_BtoH", "fmmla"},
+{"FMMLA_ZZZ_BtoS", "fmmla"},
+{"FMMLA_ZZZ_D", "fmmla"},
+{"FMMLA_ZZZ_H", "fmmla"},
+{"FMMLA_ZZZ_S", "fmmla"},
+{"FMMLAv4f32", "fmmla"},
+{"FMMLAv8f16", "fmmla"},
+{"FMMLAv8f16_v4f32", "fmmla"},
+{"FMMLAv8f16_v8f16", "fmmla"},
+{"FMLSL2lanev4f16", "fmlsl2"},
+{"FMLSL2lanev8f16", "fmlsl2"},
+{"FMLSL2v4f16", "fmlsl2"},
+{"FMLSL2v8f16", "fmlsl2"},
+{"FMLSLB_ZZZI_SHH", "fmlslb"},
+{"FMLSLB_ZZZ_SHH", "fmlslb"},
+{"FMLSLT_ZZZI_SHH", "fmlslt"},
+{"FMLSLT_ZZZ_SHH", "fmlslt"},
+{"FMLSL_MZZI_HtoS", "fmlsl"},
+{"FMLSL_MZZ_HtoS", "fmlsl"},
+{"FMLSL_VG2_M2Z2Z_HtoS", "fmlsl"},
+{"FMLSL_VG2_M2ZZI_HtoS", "fmlsl"},
+{"FMLSL_VG2_M2ZZ_HtoS", "fmlsl"},
+{"FMLSL_VG4_M4Z4Z_HtoS", "fmlsl"},
+{"FMLSL_VG4_M4ZZI_HtoS", "fmlsl"},
+{"FMLSL_VG4_M4ZZ_HtoS", "fmlsl"},
+{"FMLSLlanev4f16", "fmlsl"},
+{"FMLSLlanev8f16", "fmlsl"},
+{"FMLSLv4f16", "fmlsl"},
+{"FMLSLv8f16", "fmlsl"},
+{"FMLS_VG2_M2Z2Z_D", "fmls"},
+{"FMLS_VG2_M2Z2Z_H", "fmls"},
+{"FMLS_VG2_M2Z2Z_S", "fmls"},
+{"FMLS_VG2_M2ZZI_D", "fmls"},
+{"FMLS_VG2_M2ZZI_H", "fmls"},
+{"FMLS_VG2_M2ZZI_S", "fmls"},
+{"FMLS_VG2_M2ZZ_D", "fmls"},
+{"FMLS_VG2_M2ZZ_H", "fmls"},
+{"FMLS_VG2_M2ZZ_S", "fmls"},
+{"FMLS_VG4_M4Z4Z_D", "fmls"},
+{"FMLS_VG4_M4Z4Z_H", "fmls"},
+{"FMLS_VG4_M4Z4Z_S", "fmls"},
+{"FMLS_VG4_M4ZZI_D", "fmls"},
+{"FMLS_VG4_M4ZZI_H", "fmls"},
+{"FMLS_VG4_M4ZZI_S", "fmls"},
+{"FMLS_VG4_M4ZZ_D", "fmls"},
+{"FMLS_VG4_M4ZZ_H", "fmls"},
+{"FMLS_VG4_M4ZZ_S", "fmls"},
+{"FMLS_ZPmZZ_D", "fmls"},
+{"FMLS_ZPmZZ_H", "fmls"},
+{"FMLS_ZPmZZ_S", "fmls"},
+{"FMLS_ZZZI_D", "fmls"},
+{"FMLS_ZZZI_H", "fmls"},
+{"FMLS_ZZZI_S", "fmls"},
+{"FMLSv1i16_indexed", "fmls"},
+{"FMLSv1i32_indexed", "fmls"},
+{"FMLSv1i64_indexed", "fmls"},
+{"FMLSv2f32", "fmls"},
+{"FMLSv2f64", "fmls"},
+{"FMLSv2i32_indexed", "fmls"},
+{"FMLSv2i64_indexed", "fmls"},
+{"FMLSv4f16", "fmls"},
+{"FMLSv4f32", "fmls"},
+{"FMLSv4i16_indexed", "fmls"},
+{"FMLSv4i32_indexed", "fmls"},
+{"FMLSv8f16", "fmls"},
+{"FMLSv8i16_indexed", "fmls"},
+{"FMOP4A_M2Z2Z_BtoH", "fmop4a"},
+{"FMOP4A_M2Z2Z_BtoS", "fmop4a"},
+{"FMOP4A_M2Z2Z_D", "fmop4a"},
+{"FMOP4A_M2Z2Z_H", "fmop4a"},
+{"FMOP4A_M2Z2Z_HtoS", "fmop4a"},
+{"FMOP4A_M2Z2Z_S", "fmop4a"},
+{"FMOP4A_M2ZZ_BtoH", "fmop4a"},
+{"FMOP4A_M2ZZ_BtoS", "fmop4a"},
+{"FMOP4A_M2ZZ_D", "fmop4a"},
+{"FMOP4A_M2ZZ_H", "fmop4a"},
+{"FMOP4A_M2ZZ_HtoS", "fmop4a"},
+{"FMOP4A_M2ZZ_S", "fmop4a"},
+{"FMOP4A_MZ2Z_BtoH", "fmop4a"},
+{"FMOP4A_MZ2Z_BtoS", "fmop4a"},
+{"FMOP4A_MZ2Z_D", "fmop4a"},
+{"FMOP4A_MZ2Z_H", "fmop4a"},
+{"FMOP4A_MZ2Z_HtoS", "fmop4a"},
+{"FMOP4A_MZ2Z_S", "fmop4a"},
+{"FMOP4A_MZZ_BtoH", "fmop4a"},
+{"FMOP4A_MZZ_BtoS", "fmop4a"},
+{"FMOP4A_MZZ_D", "fmop4a"},
+{"FMOP4A_MZZ_H", "fmop4a"},
+{"FMOP4A_MZZ_HtoS", "fmop4a"},
+{"FMOP4A_MZZ_S", "fmop4a"},
+{"FMOP4S_M2Z2Z_D", "fmop4s"},
+{"FMOP4S_M2Z2Z_H", "fmop4s"},
+{"FMOP4S_M2Z2Z_HtoS", "fmop4s"},
+{"FMOP4S_M2Z2Z_S", "fmop4s"},
+{"FMOP4S_M2ZZ_D", "fmop4s"},
+{"FMOP4S_M2ZZ_H", "fmop4s"},
+{"FMOP4S_M2ZZ_HtoS", "fmop4s"},
+{"FMOP4S_M2ZZ_S", "fmop4s"},
+{"FMOP4S_MZ2Z_D", "fmop4s"},
+{"FMOP4S_MZ2Z_H", "fmop4s"},
+{"FMOP4S_MZ2Z_HtoS", "fmop4s"},
+{"FMOP4S_MZ2Z_S", "fmop4s"},
+{"FMOP4S_MZZ_D", "fmop4s"},
+{"FMOP4S_MZZ_H", "fmop4s"},
+{"FMOP4S_MZZ_HtoS", "fmop4s"},
+{"FMOP4S_MZZ_S", "fmop4s"},
+{"FMOPAL_MPPZZ", "fmopa"},
+{"FMOPA_MPPZZ_BtoH", "fmopa"},
+{"FMOPA_MPPZZ_BtoS", "fmopa"},
+{"FMOPA_MPPZZ_D", "fmopa"},
+{"FMOPA_MPPZZ_H", "fmopa"},
+{"FMOPA_MPPZZ_S", "fmopa"},
+{"FMOPSL_MPPZZ", "fmops"},
+{"FMOPS_MPPZZ_D", "fmops"},
+{"FMOPS_MPPZZ_H", "fmops"},
+{"FMOPS_MPPZZ_S", "fmops"},
+{"FMOVDXHighr", "fmov"},
+{"FMOVDXr", "fmov"},
+{"FMOVDi", "fmov"},
+{"FMOVDr", "fmov"},
+{"FMOVHWr", "fmov"},
+{"FMOVHXr", "fmov"},
+{"FMOVHi", "fmov"},
+{"FMOVHr", "fmov"},
+{"FMOVSWr", "fmov"},
+{"FMOVSi", "fmov"},
+{"FMOVSr", "fmov"},
+{"FMOVWHr", "fmov"},
+{"FMOVWSr", "fmov"},
+{"FMOVXDHighr", "fmov"},
+{"FMOVXDr", "fmov"},
+{"FMOVXHr", "fmov"},
+{"FMOVv2f32_ns", "fmov"},
+{"FMOVv2f64_ns", "fmov"},
+{"FMOVv4f16_ns", "fmov"},
+{"FMOVv4f32_ns", "fmov"},
+{"FMOVv8f16_ns", "fmov"},
+{"FMSB_ZPmZZ_D", "fmsb"},
+{"FMSB_ZPmZZ_H", "fmsb"},
+{"FMSB_ZPmZZ_S", "fmsb"},
+{"FMSUBDrrr", "fmsub"},
+{"FMSUBHrrr", "fmsub"},
+{"FMSUBSrrr", "fmsub"},
+{"FMULDrr", "fmul"},
+{"FMULHrr", "fmul"},
+{"FMULSrr", "fmul"},
+{"FMUL_2Z2Z_D", "fmul"},
+{"FMUL_2Z2Z_H", "fmul"},
+{"FMUL_2Z2Z_S", "fmul"},
+{"FMUL_2ZZ_D", "fmul"},
+{"FMUL_2ZZ_H", "fmul"},
+{"FMUL_2ZZ_S", "fmul"},
+{"FMUL_4Z4Z_D", "fmul"},
+{"FMUL_4Z4Z_H", "fmul"},
+{"FMUL_4Z4Z_S", "fmul"},
+{"FMUL_4ZZ_D", "fmul"},
+{"FMUL_4ZZ_H", "fmul"},
+{"FMUL_4ZZ_S", "fmul"},
+{"FMUL_ZPmI_D", "fmul"},
+{"FMUL_ZPmI_H", "fmul"},
+{"FMUL_ZPmI_S", "fmul"},
+{"FMUL_ZPmZ_D", "fmul"},
+{"FMUL_ZPmZ_H", "fmul"},
+{"FMUL_ZPmZ_S", "fmul"},
+{"FMUL_ZZZI_D", "fmul"},
+{"FMUL_ZZZI_H", "fmul"},
+{"FMUL_ZZZI_S", "fmul"},
+{"FMUL_ZZZ_D", "fmul"},
+{"FMUL_ZZZ_H", "fmul"},
+{"FMUL_ZZZ_S", "fmul"},
+{"FMULv1i16_indexed", "fmul"},
+{"FMULv1i32_indexed", "fmul"},
+{"FMULv1i64_indexed", "fmul"},
+{"FMULv2f32", "fmul"},
+{"FMULv2f64", "fmul"},
+{"FMULv2i32_indexed", "fmul"},
+{"FMULv2i64_indexed", "fmul"},
+{"FMULv4f16", "fmul"},
+{"FMULv4f32", "fmul"},
+{"FMULv4i16_indexed", "fmul"},
+{"FMULv4i32_indexed", "fmul"},
+{"FMULv8f16", "fmul"},
+{"FMULv8i16_indexed", "fmul"},
+{"FMULX16", "fmulx"},
+{"FMULX32", "fmulx"},
+{"FMULX64", "fmulx"},
+{"FMULX_ZPmZ_D", "fmulx"},
+{"FMULX_ZPmZ_H", "fmulx"},
+{"FMULX_ZPmZ_S", "fmulx"},
+{"FMULXv1i16_indexed", "fmulx"},
+{"FMULXv1i32_indexed", "fmulx"},
+{"FMULXv1i64_indexed", "fmulx"},
+{"FMULXv2f32", "fmulx"},
+{"FMULXv2f64", "fmulx"},
+{"FMULXv2i32_indexed", "fmulx"},
+{"FMULXv2i64_indexed", "fmulx"},
+{"FMULXv4f16", "fmulx"},
+{"FMULXv4f32", "fmulx"},
+{"FMULXv4i16_indexed", "fmulx"},
+{"FMULXv4i32_indexed", "fmulx"},
+{"FMULXv8f16", "fmulx"},
+{"FMULXv8i16_indexed", "fmulx"},
+{"FNEGDr", "fneg"},
+{"FNEGHr", "fneg"},
+{"FNEGSr", "fneg"},
+{"FNEG_ZPmZ_D", "fneg"},
+{"FNEG_ZPmZ_H", "fneg"},
+{"FNEG_ZPmZ_S", "fneg"},
+{"FNEG_ZPzZ_D", "fneg"},
+{"FNEG_ZPzZ_H", "fneg"},
+{"FNEG_ZPzZ_S", "fneg"},
+{"FNEGv2f32", "fneg"},
+{"FNEGv2f64", "fneg"},
+{"FNEGv4f16", "fneg"},
+{"FNEGv4f32", "fneg"},
+{"FNEGv8f16", "fneg"},
+{"FNMADDDrrr", "fnmadd"},
+{"FNMADDHrrr", "fnmadd"},
+{"FNMADDSrrr", "fnmadd"},
+{"FNMAD_ZPmZZ_D", "fnmad"},
+{"FNMAD_ZPmZZ_H", "fnmad"},
+{"FNMAD_ZPmZZ_S", "fnmad"},
+{"FNMLA_ZPmZZ_D", "fnmla"},
+{"FNMLA_ZPmZZ_H", "fnmla"},
+{"FNMLA_ZPmZZ_S", "fnmla"},
+{"FNMLS_ZPmZZ_D", "fnmls"},
+{"FNMLS_ZPmZZ_H", "fnmls"},
+{"FNMLS_ZPmZZ_S", "fnmls"},
+{"FNMSB_ZPmZZ_D", "fnmsb"},
+{"FNMSB_ZPmZZ_H", "fnmsb"},
+{"FNMSB_ZPmZZ_S", "fnmsb"},
+{"FNMSUBDrrr", "fnmsub"},
+{"FNMSUBHrrr", "fnmsub"},
+{"FNMSUBSrrr", "fnmsub"},
+{"FNMULDrr", "fnmul"},
+{"FNMULHrr", "fnmul"},
+{"FNMULSrr", "fnmul"},
+{"FRECPE_ZZ_D", "frecpe"},
+{"FRECPE_ZZ_H", "frecpe"},
+{"FRECPE_ZZ_S", "frecpe"},
+{"FRECPEv1f16", "frecpe"},
+{"FRECPEv1i32", "frecpe"},
+{"FRECPEv1i64", "frecpe"},
+{"FRECPEv2f32", "frecpe"},
+{"FRECPEv2f64", "frecpe"},
+{"FRECPEv4f16", "frecpe"},
+{"FRECPEv4f32", "frecpe"},
+{"FRECPEv8f16", "frecpe"},
+{"FRECPS16", "frecps"},
+{"FRECPS32", "frecps"},
+{"FRECPS64", "frecps"},
+{"FRECPS_ZZZ_D", "frecps"},
+{"FRECPS_ZZZ_H", "frecps"},
+{"FRECPS_ZZZ_S", "frecps"},
+{"FRECPSv2f32", "frecps"},
+{"FRECPSv2f64", "frecps"},
+{"FRECPSv4f16", "frecps"},
+{"FRECPSv4f32", "frecps"},
+{"FRECPSv8f16", "frecps"},
+{"FRECPX_ZPmZ_D", "frecpx"},
+{"FRECPX_ZPmZ_H", "frecpx"},
+{"FRECPX_ZPmZ_S", "frecpx"},
+{"FRECPX_ZPzZ_D", "frecpx"},
+{"FRECPX_ZPzZ_H", "frecpx"},
+{"FRECPX_ZPzZ_S", "frecpx"},
+{"FRECPXv1f16", "frecpx"},
+{"FRECPXv1i32", "frecpx"},
+{"FRECPXv1i64", "frecpx"},
+{"FRINT32XDr", "frint32x"},
+{"FRINT32XSr", "frint32x"},
+{"FRINT32X_ZPmZ_D", "frint32x"},
+{"FRINT32X_ZPmZ_S", "frint32x"},
+{"FRINT32X_ZPzZ_D", "frint32x"},
+{"FRINT32X_ZPzZ_S", "frint32x"},
+{"FRINT32Xv2f32", "frint32x"},
+{"FRINT32Xv2f64", "frint32x"},
+{"FRINT32Xv4f32", "frint32x"},
+{"FRINT32ZDr", "frint32z"},
+{"FRINT32ZSr", "frint32z"},
+{"FRINT32Z_ZPmZ_D", "frint32z"},
+{"FRINT32Z_ZPmZ_S", "frint32z"},
+{"FRINT32Z_ZPzZ_D", "frint32z"},
+{"FRINT32Z_ZPzZ_S", "frint32z"},
+{"FRINT32Zv2f32", "frint32z"},
+{"FRINT32Zv2f64", "frint32z"},
+{"FRINT32Zv4f32", "frint32z"},
+{"FRINT64XDr", "frint64x"},
+{"FRINT64XSr", "frint64x"},
+{"FRINT64X_ZPmZ_D", "frint64x"},
+{"FRINT64X_ZPmZ_S", "frint64x"},
+{"FRINT64X_ZPzZ_D", "frint64x"},
+{"FRINT64X_ZPzZ_S", "frint64x"},
+{"FRINT64Xv2f32", "frint64x"},
+{"FRINT64Xv2f64", "frint64x"},
+{"FRINT64Xv4f32", "frint64x"},
+{"FRINT64ZDr", "frint64z"},
+{"FRINT64ZSr", "frint64z"},
+{"FRINT64Z_ZPmZ_D", "frint64z"},
+{"FRINT64Z_ZPmZ_S", "frint64z"},
+{"FRINT64Z_ZPzZ_D", "frint64z"},
+{"FRINT64Z_ZPzZ_S", "frint64z"},
+{"FRINT64Zv2f32", "frint64z"},
+{"FRINT64Zv2f64", "frint64z"},
+{"FRINT64Zv4f32", "frint64z"},
+{"FRINTADr", "frinta"},
+{"FRINTAHr", "frinta"},
+{"FRINTASr", "frinta"},
+{"FRINTA_2Z2Z_S", "frinta"},
+{"FRINTA_4Z4Z_S", "frinta"},
+{"FRINTA_ZPmZ_D", "frinta"},
+{"FRINTA_ZPmZ_H", "frinta"},
+{"FRINTA_ZPmZ_S", "frinta"},
+{"FRINTA_ZPzZ_D", "frinta"},
+{"FRINTA_ZPzZ_H", "frinta"},
+{"FRINTA_ZPzZ_S", "frinta"},
+{"FRINTAv2f32", "frinta"},
+{"FRINTAv2f64", "frinta"},
+{"FRINTAv4f16", "frinta"},
+{"FRINTAv4f32", "frinta"},
+{"FRINTAv8f16", "frinta"},
+{"FRINTIDr", "frinti"},
+{"FRINTIHr", "frinti"},
+{"FRINTISr", "frinti"},
+{"FRINTI_ZPmZ_D", "frinti"},
+{"FRINTI_ZPmZ_H", "frinti"},
+{"FRINTI_ZPmZ_S", "frinti"},
+{"FRINTI_ZPzZ_D", "frinti"},
+{"FRINTI_ZPzZ_H", "frinti"},
+{"FRINTI_ZPzZ_S", "frinti"},
+{"FRINTIv2f32", "frinti"},
+{"FRINTIv2f64", "frinti"},
+{"FRINTIv4f16", "frinti"},
+{"FRINTIv4f32", "frinti"},
+{"FRINTIv8f16", "frinti"},
+{"FRINTMDr", "frintm"},
+{"FRINTMHr", "frintm"},
+{"FRINTMSr", "frintm"},
+{"FRINTM_2Z2Z_S", "frintm"},
+{"FRINTM_4Z4Z_S", "frintm"},
+{"FRINTM_ZPmZ_D", "frintm"},
+{"FRINTM_ZPmZ_H", "frintm"},
+{"FRINTM_ZPmZ_S", "frintm"},
+{"FRINTM_ZPzZ_D", "frintm"},
+{"FRINTM_ZPzZ_H", "frintm"},
+{"FRINTM_ZPzZ_S", "frintm"},
+{"FRINTMv2f32", "frintm"},
+{"FRINTMv2f64", "frintm"},
+{"FRINTMv4f16", "frintm"},
+{"FRINTMv4f32", "frintm"},
+{"FRINTMv8f16", "frintm"},
+{"FRINTNDr", "frintn"},
+{"FRINTNHr", "frintn"},
+{"FRINTNSr", "frintn"},
+{"FRINTN_2Z2Z_S", "frintn"},
+{"FRINTN_4Z4Z_S", "frintn"},
+{"FRINTN_ZPmZ_D", "frintn"},
+{"FRINTN_ZPmZ_H", "frintn"},
+{"FRINTN_ZPmZ_S", "frintn"},
+{"FRINTN_ZPzZ_D", "frintn"},
+{"FRINTN_ZPzZ_H", "frintn"},
+{"FRINTN_ZPzZ_S", "frintn"},
+{"FRINTNv2f32", "frintn"},
+{"FRINTNv2f64", "frintn"},
+{"FRINTNv4f16", "frintn"},
+{"FRINTNv4f32", "frintn"},
+{"FRINTNv8f16", "frintn"},
+{"FRINTPDr", "frintp"},
+{"FRINTPHr", "frintp"},
+{"FRINTPSr", "frintp"},
+{"FRINTP_2Z2Z_S", "frintp"},
+{"FRINTP_4Z4Z_S", "frintp"},
+{"FRINTP_ZPmZ_D", "frintp"},
+{"FRINTP_ZPmZ_H", "frintp"},
+{"FRINTP_ZPmZ_S", "frintp"},
+{"FRINTP_ZPzZ_D", "frintp"},
+{"FRINTP_ZPzZ_H", "frintp"},
+{"FRINTP_ZPzZ_S", "frintp"},
+{"FRINTPv2f32", "frintp"},
+{"FRINTPv2f64", "frintp"},
+{"FRINTPv4f16", "frintp"},
+{"FRINTPv4f32", "frintp"},
+{"FRINTPv8f16", "frintp"},
+{"FRINTXDr", "frintx"},
+{"FRINTXHr", "frintx"},
+{"FRINTXSr", "frintx"},
+{"FRINTX_ZPmZ_D", "frintx"},
+{"FRINTX_ZPmZ_H", "frintx"},
+{"FRINTX_ZPmZ_S", "frintx"},
+{"FRINTX_ZPzZ_D", "frintx"},
+{"FRINTX_ZPzZ_H", "frintx"},
+{"FRINTX_ZPzZ_S", "frintx"},
+{"FRINTXv2f32", "frintx"},
+{"FRINTXv2f64", "frintx"},
+{"FRINTXv4f16", "frintx"},
+{"FRINTXv4f32", "frintx"},
+{"FRINTXv8f16", "frintx"},
+{"FRINTZDr", "frintz"},
+{"FRINTZHr", "frintz"},
+{"FRINTZSr", "frintz"},
+{"FRINTZ_ZPmZ_D", "frintz"},
+{"FRINTZ_ZPmZ_H", "frintz"},
+{"FRINTZ_ZPmZ_S", "frintz"},
+{"FRINTZ_ZPzZ_D", "frintz"},
+{"FRINTZ_ZPzZ_H", "frintz"},
+{"FRINTZ_ZPzZ_S", "frintz"},
+{"FRINTZv2f32", "frintz"},
+{"FRINTZv2f64", "frintz"},
+{"FRINTZv4f16", "frintz"},
+{"FRINTZv4f32", "frintz"},
+{"FRINTZv8f16", "frintz"},
+{"FRSQRTE_ZZ_D", "frsqrte"},
+{"FRSQRTE_ZZ_H", "frsqrte"},
+{"FRSQRTE_ZZ_S", "frsqrte"},
+{"FRSQRTEv1f16", "frsqrte"},
+{"FRSQRTEv1i32", "frsqrte"},
+{"FRSQRTEv1i64", "frsqrte"},
+{"FRSQRTEv2f32", "frsqrte"},
+{"FRSQRTEv2f64", "frsqrte"},
+{"FRSQRTEv4f16", "frsqrte"},
+{"FRSQRTEv4f32", "frsqrte"},
+{"FRSQRTEv8f16", "frsqrte"},
+{"FRSQRTS16", "frsqrts"},
+{"FRSQRTS32", "frsqrts"},
+{"FRSQRTS64", "frsqrts"},
+{"FRSQRTS_ZZZ_D", "frsqrts"},
+{"FRSQRTS_ZZZ_H", "frsqrts"},
+{"FRSQRTS_ZZZ_S", "frsqrts"},
+{"FRSQRTSv2f32", "frsqrts"},
+{"FRSQRTSv2f64", "frsqrts"},
+{"FRSQRTSv4f16", "frsqrts"},
+{"FRSQRTSv4f32", "frsqrts"},
+{"FRSQRTSv8f16", "frsqrts"},
+{"FSCALE_2Z2Z_D", "fscale"},
+{"FSCALE_2Z2Z_H", "fscale"},
+{"FSCALE_2Z2Z_S", "fscale"},
+{"FSCALE_2ZZ_D", "fscale"},
+{"FSCALE_2ZZ_H", "fscale"},
+{"FSCALE_2ZZ_S", "fscale"},
+{"FSCALE_4Z4Z_D", "fscale"},
+{"FSCALE_4Z4Z_H", "fscale"},
+{"FSCALE_4Z4Z_S", "fscale"},
+{"FSCALE_4ZZ_D", "fscale"},
+{"FSCALE_4ZZ_H", "fscale"},
+{"FSCALE_4ZZ_S", "fscale"},
+{"FSCALE_ZPmZ_D", "fscale"},
+{"FSCALE_ZPmZ_H", "fscale"},
+{"FSCALE_ZPmZ_S", "fscale"},
+{"FSCALEv2f32", "fscale"},
+{"FSCALEv2f64", "fscale"},
+{"FSCALEv4f16", "fscale"},
+{"FSCALEv4f32", "fscale"},
+{"FSCALEv8f16", "fscale"},
+{"FSQRTDr", "fsqrt"},
+{"FSQRTHr", "fsqrt"},
+{"FSQRTSr", "fsqrt"},
+{"FSQRT_ZPZz_D", "fsqrt"},
+{"FSQRT_ZPZz_H", "fsqrt"},
+{"FSQRT_ZPZz_S", "fsqrt"},
+{"FSQRT_ZPmZ_D", "fsqrt"},
+{"FSQRT_ZPmZ_H", "fsqrt"},
+{"FSQRT_ZPmZ_S", "fsqrt"},
+{"FSQRTv2f32", "fsqrt"},
+{"FSQRTv2f64", "fsqrt"},
+{"FSQRTv4f16", "fsqrt"},
+{"FSQRTv4f32", "fsqrt"},
+{"FSQRTv8f16", "fsqrt"},
+{"FSUBDrr", "fsub"},
+{"FSUBHrr", "fsub"},
+{"FSUBSrr", "fsub"},
+{"FSUB_VG2_M2Z_D", "fsub"},
+{"FSUB_VG2_M2Z_H", "fsub"},
+{"FSUB_VG2_M2Z_S", "fsub"},
+{"FSUB_VG4_M4Z_D", "fsub"},
+{"FSUB_VG4_M4Z_H", "fsub"},
+{"FSUB_VG4_M4Z_S", "fsub"},
+{"FSUB_ZPmI_D", "fsub"},
+{"FSUB_ZPmI_H", "fsub"},
+{"FSUB_ZPmI_S", "fsub"},
+{"FSUB_ZPmZ_D", "fsub"},
+{"FSUB_ZPmZ_H", "fsub"},
+{"FSUB_ZPmZ_S", "fsub"},
+{"FSUB_ZZZ_D", "fsub"},
+{"FSUB_ZZZ_H", "fsub"},
+{"FSUB_ZZZ_S", "fsub"},
+{"FSUBv2f32", "fsub"},
+{"FSUBv2f64", "fsub"},
+{"FSUBv4f16", "fsub"},
+{"FSUBv4f32", "fsub"},
+{"FSUBv8f16", "fsub"},
+{"FSUBR_ZPmI_D", "fsubr"},
+{"FSUBR_ZPmI_H", "fsubr"},
+{"FSUBR_ZPmI_S", "fsubr"},
+{"FSUBR_ZPmZ_D", "fsubr"},
+{"FSUBR_ZPmZ_H", "fsubr"},
+{"FSUBR_ZPmZ_S", "fsubr"},
+{"FTMAD_ZZI_D", "ftmad"},
+{"FTMAD_ZZI_H", "ftmad"},
+{"FTMAD_ZZI_S", "ftmad"},
+{"FTMOPA_M2ZZZI_BtoH", "ftmopa"},
+{"FTMOPA_M2ZZZI_BtoS", "ftmopa"},
+{"FTMOPA_M2ZZZI_HtoH", "ftmopa"},
+{"FTMOPA_M2ZZZI_HtoS", "ftmopa"},
+{"FTMOPA_M2ZZZI_StoS", "ftmopa"},
+{"FTSMUL_ZZZ_D", "ftsmul"},
+{"FTSMUL_ZZZ_H", "ftsmul"},
+{"FTSMUL_ZZZ_S", "ftsmul"},
+{"FTSSEL_ZZZ_D", "ftssel"},
+{"FTSSEL_ZZZ_H", "ftssel"},
+{"FTSSEL_ZZZ_S", "ftssel"},
+{"FVDOTB_VG4_M2ZZI_BtoS", "fvdotb"},
+{"FVDOTT_VG4_M2ZZI_BtoS", "fvdott"},
+{"FVDOT_VG2_M2ZZI_BtoH", "fvdot"},
+{"FVDOT_VG2_M2ZZI_HtoS", "fvdot"},
+{"GCSPOPCX", "gcspopcx"},
+{"GCSPOPM", "gcspopm"},
+{"GCSPOPX", "gcspopx"},
+{"GCSPUSHM", "gcspushm"},
+{"GCSPUSHX", "gcspushx"},
+{"GCSSS1", "gcsss1"},
+{"GCSSS2", "gcsss2"},
+{"GCSSTR", "gcsstr"},
+{"GCSSTTR", "gcssttr"},
+{"GLD1B_D", "ld1b"},
+{"GLD1B_D_IMM", "ld1b"},
+{"GLD1B_D_SXTW", "ld1b"},
+{"GLD1B_D_UXTW", "ld1b"},
+{"GLD1B_S_IMM", "ld1b"},
+{"GLD1B_S_SXTW", "ld1b"},
+{"GLD1B_S_UXTW", "ld1b"},
+{"LD1B", "ld1b"},
+{"LD1B_2Z", "ld1b"},
+{"LD1B_2Z_IMM", "ld1b"},
+{"LD1B_2Z_STRIDED", "ld1b"},
+{"LD1B_2Z_STRIDED_IMM", "ld1b"},
+{"LD1B_4Z", "ld1b"},
+{"LD1B_4Z_IMM", "ld1b"},
+{"LD1B_4Z_STRIDED", "ld1b"},
+{"LD1B_4Z_STRIDED_IMM", "ld1b"},
+{"LD1B_D", "ld1b"},
+{"LD1B_D_IMM", "ld1b"},
+{"LD1B_H", "ld1b"},
+{"LD1B_H_IMM", "ld1b"},
+{"LD1B_IMM", "ld1b"},
+{"LD1B_S", "ld1b"},
+{"LD1B_S_IMM", "ld1b"},
+{"LD1_MXIPXX_H_B", "ld1b"},
+{"LD1_MXIPXX_V_B", "ld1b"},
+{"GLD1D", "ld1d"},
+{"GLD1D_IMM", "ld1d"},
+{"GLD1D_SCALED", "ld1d"},
+{"GLD1D_SXTW", "ld1d"},
+{"GLD1D_SXTW_SCALED", "ld1d"},
+{"GLD1D_UXTW", "ld1d"},
+{"GLD1D_UXTW_SCALED", "ld1d"},
+{"LD1D", "ld1d"},
+{"LD1D_2Z", "ld1d"},
+{"LD1D_2Z_IMM", "ld1d"},
+{"LD1D_2Z_STRIDED", "ld1d"},
+{"LD1D_2Z_STRIDED_IMM", "ld1d"},
+{"LD1D_4Z", "ld1d"},
+{"LD1D_4Z_IMM", "ld1d"},
+{"LD1D_4Z_STRIDED", "ld1d"},
+{"LD1D_4Z_STRIDED_IMM", "ld1d"},
+{"LD1D_IMM", "ld1d"},
+{"LD1D_Q", "ld1d"},
+{"LD1D_Q_IMM", "ld1d"},
+{"LD1_MXIPXX_H_D", "ld1d"},
+{"LD1_MXIPXX_V_D", "ld1d"},
+{"GLD1H_D", "ld1h"},
+{"GLD1H_D_IMM", "ld1h"},
+{"GLD1H_D_SCALED", "ld1h"},
+{"GLD1H_D_SXTW", "ld1h"},
+{"GLD1H_D_SXTW_SCALED", "ld1h"},
+{"GLD1H_D_UXTW", "ld1h"},
+{"GLD1H_D_UXTW_SCALED", "ld1h"},
+{"GLD1H_S_IMM", "ld1h"},
+{"GLD1H_S_SXTW", "ld1h"},
+{"GLD1H_S_SXTW_SCALED", "ld1h"},
+{"GLD1H_S_UXTW", "ld1h"},
+{"GLD1H_S_UXTW_SCALED", "ld1h"},
+{"LD1H", "ld1h"},
+{"LD1H_2Z", "ld1h"},
+{"LD1H_2Z_IMM", "ld1h"},
+{"LD1H_2Z_STRIDED", "ld1h"},
+{"LD1H_2Z_STRIDED_IMM", "ld1h"},
+{"LD1H_4Z", "ld1h"},
+{"LD1H_4Z_IMM", "ld1h"},
+{"LD1H_4Z_STRIDED", "ld1h"},
+{"LD1H_4Z_STRIDED_IMM", "ld1h"},
+{"LD1H_D", "ld1h"},
+{"LD1H_D_IMM", "ld1h"},
+{"LD1H_IMM", "ld1h"},
+{"LD1H_S", "ld1h"},
+{"LD1H_S_IMM", "ld1h"},
+{"LD1_MXIPXX_H_H", "ld1h"},
+{"LD1_MXIPXX_V_H", "ld1h"},
+{"GLD1Q", "ld1q"},
+{"LD1_MXIPXX_H_Q", "ld1q"},
+{"LD1_MXIPXX_V_Q", "ld1q"},
+{"GLD1SB_D", "ld1sb"},
+{"GLD1SB_D_IMM", "ld1sb"},
+{"GLD1SB_D_SXTW", "ld1sb"},
+{"GLD1SB_D_UXTW", "ld1sb"},
+{"GLD1SB_S_IMM", "ld1sb"},
+{"GLD1SB_S_SXTW", "ld1sb"},
+{"GLD1SB_S_UXTW", "ld1sb"},
+{"LD1SB_D", "ld1sb"},
+{"LD1SB_D_IMM", "ld1sb"},
+{"LD1SB_H", "ld1sb"},
+{"LD1SB_H_IMM", "ld1sb"},
+{"LD1SB_S", "ld1sb"},
+{"LD1SB_S_IMM", "ld1sb"},
+{"GLD1SH_D", "ld1sh"},
+{"GLD1SH_D_IMM", "ld1sh"},
+{"GLD1SH_D_SCALED", "ld1sh"},
+{"GLD1SH_D_SXTW", "ld1sh"},
+{"GLD1SH_D_SXTW_SCALED", "ld1sh"},
+{"GLD1SH_D_UXTW", "ld1sh"},
+{"GLD1SH_D_UXTW_SCALED", "ld1sh"},
+{"GLD1SH_S_IMM", "ld1sh"},
+{"GLD1SH_S_SXTW", "ld1sh"},
+{"GLD1SH_S_SXTW_SCALED", "ld1sh"},
+{"GLD1SH_S_UXTW", "ld1sh"},
+{"GLD1SH_S_UXTW_SCALED", "ld1sh"},
+{"LD1SH_D", "ld1sh"},
+{"LD1SH_D_IMM", "ld1sh"},
+{"LD1SH_S", "ld1sh"},
+{"LD1SH_S_IMM", "ld1sh"},
+{"GLD1SW_D", "ld1sw"},
+{"GLD1SW_D_IMM", "ld1sw"},
+{"GLD1SW_D_SCALED", "ld1sw"},
+{"GLD1SW_D_SXTW", "ld1sw"},
+{"GLD1SW_D_SXTW_SCALED", "ld1sw"},
+{"GLD1SW_D_UXTW", "ld1sw"},
+{"GLD1SW_D_UXTW_SCALED", "ld1sw"},
+{"LD1SW_D", "ld1sw"},
+{"LD1SW_D_IMM", "ld1sw"},
+{"GLD1W_D", "ld1w"},
+{"GLD1W_D_IMM", "ld1w"},
+{"GLD1W_D_SCALED", "ld1w"},
+{"GLD1W_D_SXTW", "ld1w"},
+{"GLD1W_D_SXTW_SCALED", "ld1w"},
+{"GLD1W_D_UXTW", "ld1w"},
+{"GLD1W_D_UXTW_SCALED", "ld1w"},
+{"GLD1W_IMM", "ld1w"},
+{"GLD1W_SXTW", "ld1w"},
+{"GLD1W_SXTW_SCALED", "ld1w"},
+{"GLD1W_UXTW", "ld1w"},
+{"GLD1W_UXTW_SCALED", "ld1w"},
+{"LD1W", "ld1w"},
+{"LD1W_2Z", "ld1w"},
+{"LD1W_2Z_IMM", "ld1w"},
+{"LD1W_2Z_STRIDED", "ld1w"},
+{"LD1W_2Z_STRIDED_IMM", "ld1w"},
+{"LD1W_4Z", "ld1w"},
+{"LD1W_4Z_IMM", "ld1w"},
+{"LD1W_4Z_STRIDED", "ld1w"},
+{"LD1W_4Z_STRIDED_IMM", "ld1w"},
+{"LD1W_D", "ld1w"},
+{"LD1W_D_IMM", "ld1w"},
+{"LD1W_IMM", "ld1w"},
+{"LD1W_Q", "ld1w"},
+{"LD1W_Q_IMM", "ld1w"},
+{"LD1_MXIPXX_H_S", "ld1w"},
+{"LD1_MXIPXX_V_S", "ld1w"},
+{"GLDFF1B_D", "ldff1b"},
+{"GLDFF1B_D_IMM", "ldff1b"},
+{"GLDFF1B_D_SXTW", "ldff1b"},
+{"GLDFF1B_D_UXTW", "ldff1b"},
+{"GLDFF1B_S_IMM", "ldff1b"},
+{"GLDFF1B_S_SXTW", "ldff1b"},
+{"GLDFF1B_S_UXTW", "ldff1b"},
+{"LDFF1B", "ldff1b"},
+{"LDFF1B_D", "ldff1b"},
+{"LDFF1B_H", "ldff1b"},
+{"LDFF1B_S", "ldff1b"},
+{"GLDFF1D", "ldff1d"},
+{"GLDFF1D_IMM", "ldff1d"},
+{"GLDFF1D_SCALED", "ldff1d"},
+{"GLDFF1D_SXTW", "ldff1d"},
+{"GLDFF1D_SXTW_SCALED", "ldff1d"},
+{"GLDFF1D_UXTW", "ldff1d"},
+{"GLDFF1D_UXTW_SCALED", "ldff1d"},
+{"LDFF1D", "ldff1d"},
+{"GLDFF1H_D", "ldff1h"},
+{"GLDFF1H_D_IMM", "ldff1h"},
+{"GLDFF1H_D_SCALED", "ldff1h"},
+{"GLDFF1H_D_SXTW", "ldff1h"},
+{"GLDFF1H_D_SXTW_SCALED", "ldff1h"},
+{"GLDFF1H_D_UXTW", "ldff1h"},
+{"GLDFF1H_D_UXTW_SCALED", "ldff1h"},
+{"GLDFF1H_S_IMM", "ldff1h"},
+{"GLDFF1H_S_SXTW", "ldff1h"},
+{"GLDFF1H_S_SXTW_SCALED", "ldff1h"},
+{"GLDFF1H_S_UXTW", "ldff1h"},
+{"GLDFF1H_S_UXTW_SCALED", "ldff1h"},
+{"LDFF1H", "ldff1h"},
+{"LDFF1H_D", "ldff1h"},
+{"LDFF1H_S", "ldff1h"},
+{"GLDFF1SB_D", "ldff1sb"},
+{"GLDFF1SB_D_IMM", "ldff1sb"},
+{"GLDFF1SB_D_SXTW", "ldff1sb"},
+{"GLDFF1SB_D_UXTW", "ldff1sb"},
+{"GLDFF1SB_S_IMM", "ldff1sb"},
+{"GLDFF1SB_S_SXTW", "ldff1sb"},
+{"GLDFF1SB_S_UXTW", "ldff1sb"},
+{"LDFF1SB_D", "ldff1sb"},
+{"LDFF1SB_H", "ldff1sb"},
+{"LDFF1SB_S", "ldff1sb"},
+{"GLDFF1SH_D", "ldff1sh"},
+{"GLDFF1SH_D_IMM", "ldff1sh"},
+{"GLDFF1SH_D_SCALED", "ldff1sh"},
+{"GLDFF1SH_D_SXTW", "ldff1sh"},
+{"GLDFF1SH_D_SXTW_SCALED", "ldff1sh"},
+{"GLDFF1SH_D_UXTW", "ldff1sh"},
+{"GLDFF1SH_D_UXTW_SCALED", "ldff1sh"},
+{"GLDFF1SH_S_IMM", "ldff1sh"},
+{"GLDFF1SH_S_SXTW", "ldff1sh"},
+{"GLDFF1SH_S_SXTW_SCALED", "ldff1sh"},
+{"GLDFF1SH_S_UXTW", "ldff1sh"},
+{"GLDFF1SH_S_UXTW_SCALED", "ldff1sh"},
+{"LDFF1SH_D", "ldff1sh"},
+{"LDFF1SH_S", "ldff1sh"},
+{"GLDFF1SW_D", "ldff1sw"},
+{"GLDFF1SW_D_IMM", "ldff1sw"},
+{"GLDFF1SW_D_SCALED", "ldff1sw"},
+{"GLDFF1SW_D_SXTW", "ldff1sw"},
+{"GLDFF1SW_D_SXTW_SCALED", "ldff1sw"},
+{"GLDFF1SW_D_UXTW", "ldff1sw"},
+{"GLDFF1SW_D_UXTW_SCALED", "ldff1sw"},
+{"LDFF1SW_D", "ldff1sw"},
+{"GLDFF1W_D", "ldff1w"},
+{"GLDFF1W_D_IMM", "ldff1w"},
+{"GLDFF1W_D_SCALED", "ldff1w"},
+{"GLDFF1W_D_SXTW", "ldff1w"},
+{"GLDFF1W_D_SXTW_SCALED", "ldff1w"},
+{"GLDFF1W_D_UXTW", "ldff1w"},
+{"GLDFF1W_D_UXTW_SCALED", "ldff1w"},
+{"GLDFF1W_IMM", "ldff1w"},
+{"GLDFF1W_SXTW", "ldff1w"},
+{"GLDFF1W_SXTW_SCALED", "ldff1w"},
+{"GLDFF1W_UXTW", "ldff1w"},
+{"GLDFF1W_UXTW_SCALED", "ldff1w"},
+{"LDFF1W", "ldff1w"},
+{"LDFF1W_D", "ldff1w"},
+{"GMI", "gmi"},
+{"HINTE", "hinte"},
+{"HISTCNT_ZPzZZ_D", "histcnt"},
+{"HISTCNT_ZPzZZ_S", "histcnt"},
+{"HISTSEG_ZZZ", "histseg"},
+{"HLT", "hlt"},
+{"HVC", "hvc"},
+{"INCB_XPiI", "incb"},
+{"INCD_XPiI", "incd"},
+{"INCD_ZPiI", "incd"},
+{"INCH_XPiI", "inch"},
+{"INCH_ZPiI", "inch"},
+{"INCP_XP_B", "incp"},
+{"INCP_XP_D", "incp"},
+{"INCP_XP_H", "incp"},
+{"INCP_XP_S", "incp"},
+{"INCP_ZP_D", "incp"},
+{"INCP_ZP_H", "incp"},
+{"INCP_ZP_S", "incp"},
+{"INCW_XPiI", "incw"},
+{"INCW_ZPiI", "incw"},
+{"INDEX_II_B", "index"},
+{"INDEX_II_D", "index"},
+{"INDEX_II_H", "index"},
+{"INDEX_II_S", "index"},
+{"INDEX_IR_B", "index"},
+{"INDEX_IR_D", "index"},
+{"INDEX_IR_H", "index"},
+{"INDEX_IR_S", "index"},
+{"INDEX_RI_B", "index"},
+{"INDEX_RI_D", "index"},
+{"INDEX_RI_H", "index"},
+{"INDEX_RI_S", "index"},
+{"INDEX_RR_B", "index"},
+{"INDEX_RR_D", "index"},
+{"INDEX_RR_H", "index"},
+{"INDEX_RR_S", "index"},
+{"INSR_ZR_B", "insr"},
+{"INSR_ZR_D", "insr"},
+{"INSR_ZR_H", "insr"},
+{"INSR_ZR_S", "insr"},
+{"INSR_ZV_B", "insr"},
+{"INSR_ZV_D", "insr"},
+{"INSR_ZV_H", "insr"},
+{"INSR_ZV_S", "insr"},
+{"INSvi8gpr", "ins"},
+{"INSvi8lane", "ins"},
+{"INSvi16gpr", "ins"},
+{"INSvi16lane", "ins"},
+{"INSvi32gpr", "ins"},
+{"INSvi32lane", "ins"},
+{"INSvi64gpr", "ins"},
+{"INSvi64lane", "ins"},
+{"IRG", "irg"},
+{"ISB", "isb"},
+{"LASTA_RPZ_B", "lasta"},
+{"LASTA_RPZ_D", "lasta"},
+{"LASTA_RPZ_H", "lasta"},
+{"LASTA_RPZ_S", "lasta"},
+{"LASTA_VPZ_B", "lasta"},
+{"LASTA_VPZ_D", "lasta"},
+{"LASTA_VPZ_H", "lasta"},
+{"LASTA_VPZ_S", "lasta"},
+{"LASTB_RPZ_B", "lastb"},
+{"LASTB_RPZ_D", "lastb"},
+{"LASTB_RPZ_H", "lastb"},
+{"LASTB_RPZ_S", "lastb"},
+{"LASTB_VPZ_B", "lastb"},
+{"LASTB_VPZ_D", "lastb"},
+{"LASTB_VPZ_H", "lastb"},
+{"LASTB_VPZ_S", "lastb"},
+{"LASTP_XPP_B", "lastp"},
+{"LASTP_XPP_D", "lastp"},
+{"LASTP_XPP_H", "lastp"},
+{"LASTP_XPP_S", "lastp"},
+{"LD1Fourv1d", "ld1"},
+{"LD1Fourv1d_POST", "ld1"},
+{"LD1Fourv2d", "ld1"},
+{"LD1Fourv2d_POST", "ld1"},
+{"LD1Fourv2s", "ld1"},
+{"LD1Fourv2s_POST", "ld1"},
+{"LD1Fourv4h", "ld1"},
+{"LD1Fourv4h_POST", "ld1"},
+{"LD1Fourv4s", "ld1"},
+{"LD1Fourv4s_POST", "ld1"},
+{"LD1Fourv8b", "ld1"},
+{"LD1Fourv8b_POST", "ld1"},
+{"LD1Fourv8h", "ld1"},
+{"LD1Fourv8h_POST", "ld1"},
+{"LD1Fourv16b", "ld1"},
+{"LD1Fourv16b_POST", "ld1"},
+{"LD1Onev1d", "ld1"},
+{"LD1Onev1d_POST", "ld1"},
+{"LD1Onev2d", "ld1"},
+{"LD1Onev2d_POST", "ld1"},
+{"LD1Onev2s", "ld1"},
+{"LD1Onev2s_POST", "ld1"},
+{"LD1Onev4h", "ld1"},
+{"LD1Onev4h_POST", "ld1"},
+{"LD1Onev4s", "ld1"},
+{"LD1Onev4s_POST", "ld1"},
+{"LD1Onev8b", "ld1"},
+{"LD1Onev8b_POST", "ld1"},
+{"LD1Onev8h", "ld1"},
+{"LD1Onev8h_POST", "ld1"},
+{"LD1Onev16b", "ld1"},
+{"LD1Onev16b_POST", "ld1"},
+{"LD1Threev1d", "ld1"},
+{"LD1Threev1d_POST", "ld1"},
+{"LD1Threev2d", "ld1"},
+{"LD1Threev2d_POST", "ld1"},
+{"LD1Threev2s", "ld1"},
+{"LD1Threev2s_POST", "ld1"},
+{"LD1Threev4h", "ld1"},
+{"LD1Threev4h_POST", "ld1"},
+{"LD1Threev4s", "ld1"},
+{"LD1Threev4s_POST", "ld1"},
+{"LD1Threev8b", "ld1"},
+{"LD1Threev8b_POST", "ld1"},
+{"LD1Threev8h", "ld1"},
+{"LD1Threev8h_POST", "ld1"},
+{"LD1Threev16b", "ld1"},
+{"LD1Threev16b_POST", "ld1"},
+{"LD1Twov1d", "ld1"},
+{"LD1Twov1d_POST", "ld1"},
+{"LD1Twov2d", "ld1"},
+{"LD1Twov2d_POST", "ld1"},
+{"LD1Twov2s", "ld1"},
+{"LD1Twov2s_POST", "ld1"},
+{"LD1Twov4h", "ld1"},
+{"LD1Twov4h_POST", "ld1"},
+{"LD1Twov4s", "ld1"},
+{"LD1Twov4s_POST", "ld1"},
+{"LD1Twov8b", "ld1"},
+{"LD1Twov8b_POST", "ld1"},
+{"LD1Twov8h", "ld1"},
+{"LD1Twov8h_POST", "ld1"},
+{"LD1Twov16b", "ld1"},
+{"LD1Twov16b_POST", "ld1"},
+{"LD1i8", "ld1"},
+{"LD1i8_POST", "ld1"},
+{"LD1i16", "ld1"},
+{"LD1i16_POST", "ld1"},
+{"LD1i32", "ld1"},
+{"LD1i32_POST", "ld1"},
+{"LD1i64", "ld1"},
+{"LD1i64_POST", "ld1"},
+{"LD1RB_D_IMM", "ld1rb"},
+{"LD1RB_H_IMM", "ld1rb"},
+{"LD1RB_IMM", "ld1rb"},
+{"LD1RB_S_IMM", "ld1rb"},
+{"LD1RD_IMM", "ld1rd"},
+{"LD1RH_D_IMM", "ld1rh"},
+{"LD1RH_IMM", "ld1rh"},
+{"LD1RH_S_IMM", "ld1rh"},
+{"LD1RO_B", "ld1rob"},
+{"LD1RO_B_IMM", "ld1rob"},
+{"LD1RO_D", "ld1rod"},
+{"LD1RO_D_IMM", "ld1rod"},
+{"LD1RO_H", "ld1roh"},
+{"LD1RO_H_IMM", "ld1roh"},
+{"LD1RO_W", "ld1row"},
+{"LD1RO_W_IMM", "ld1row"},
+{"LD1RQ_B", "ld1rqb"},
+{"LD1RQ_B_IMM", "ld1rqb"},
+{"LD1RQ_D", "ld1rqd"},
+{"LD1RQ_D_IMM", "ld1rqd"},
+{"LD1RQ_H", "ld1rqh"},
+{"LD1RQ_H_IMM", "ld1rqh"},
+{"LD1RQ_W", "ld1rqw"},
+{"LD1RQ_W_IMM", "ld1rqw"},
+{"LD1RSB_D_IMM", "ld1rsb"},
+{"LD1RSB_H_IMM", "ld1rsb"},
+{"LD1RSB_S_IMM", "ld1rsb"},
+{"LD1RSH_D_IMM", "ld1rsh"},
+{"LD1RSH_S_IMM", "ld1rsh"},
+{"LD1RSW_IMM", "ld1rsw"},
+{"LD1RW_D_IMM", "ld1rw"},
+{"LD1RW_IMM", "ld1rw"},
+{"LD1Rv1d", "ld1r"},
+{"LD1Rv1d_POST", "ld1r"},
+{"LD1Rv2d", "ld1r"},
+{"LD1Rv2d_POST", "ld1r"},
+{"LD1Rv2s", "ld1r"},
+{"LD1Rv2s_POST", "ld1r"},
+{"LD1Rv4h", "ld1r"},
+{"LD1Rv4h_POST", "ld1r"},
+{"LD1Rv4s", "ld1r"},
+{"LD1Rv4s_POST", "ld1r"},
+{"LD1Rv8b", "ld1r"},
+{"LD1Rv8b_POST", "ld1r"},
+{"LD1Rv8h", "ld1r"},
+{"LD1Rv8h_POST", "ld1r"},
+{"LD1Rv16b", "ld1r"},
+{"LD1Rv16b_POST", "ld1r"},
+{"LD2B", "ld2b"},
+{"LD2B_IMM", "ld2b"},
+{"LD2D", "ld2d"},
+{"LD2D_IMM", "ld2d"},
+{"LD2H", "ld2h"},
+{"LD2H_IMM", "ld2h"},
+{"LD2Q", "ld2q"},
+{"LD2Q_IMM", "ld2q"},
+{"LD2Rv1d", "ld2r"},
+{"LD2Rv1d_POST", "ld2r"},
+{"LD2Rv2d", "ld2r"},
+{"LD2Rv2d_POST", "ld2r"},
+{"LD2Rv2s", "ld2r"},
+{"LD2Rv2s_POST", "ld2r"},
+{"LD2Rv4h", "ld2r"},
+{"LD2Rv4h_POST", "ld2r"},
+{"LD2Rv4s", "ld2r"},
+{"LD2Rv4s_POST", "ld2r"},
+{"LD2Rv8b", "ld2r"},
+{"LD2Rv8b_POST", "ld2r"},
+{"LD2Rv8h", "ld2r"},
+{"LD2Rv8h_POST", "ld2r"},
+{"LD2Rv16b", "ld2r"},
+{"LD2Rv16b_POST", "ld2r"},
+{"LD2Twov2d", "ld2"},
+{"LD2Twov2d_POST", "ld2"},
+{"LD2Twov2s", "ld2"},
+{"LD2Twov2s_POST", "ld2"},
+{"LD2Twov4h", "ld2"},
+{"LD2Twov4h_POST", "ld2"},
+{"LD2Twov4s", "ld2"},
+{"LD2Twov4s_POST", "ld2"},
+{"LD2Twov8b", "ld2"},
+{"LD2Twov8b_POST", "ld2"},
+{"LD2Twov8h", "ld2"},
+{"LD2Twov8h_POST", "ld2"},
+{"LD2Twov16b", "ld2"},
+{"LD2Twov16b_POST", "ld2"},
+{"LD2i8", "ld2"},
+{"LD2i8_POST", "ld2"},
+{"LD2i16", "ld2"},
+{"LD2i16_POST", "ld2"},
+{"LD2i32", "ld2"},
+{"LD2i32_POST", "ld2"},
+{"LD2i64", "ld2"},
+{"LD2i64_POST", "ld2"},
+{"LD2W", "ld2w"},
+{"LD2W_IMM", "ld2w"},
+{"LD3B", "ld3b"},
+{"LD3B_IMM", "ld3b"},
+{"LD3D", "ld3d"},
+{"LD3D_IMM", "ld3d"},
+{"LD3H", "ld3h"},
+{"LD3H_IMM", "ld3h"},
+{"LD3Q", "ld3q"},
+{"LD3Q_IMM", "ld3q"},
+{"LD3Rv1d", "ld3r"},
+{"LD3Rv1d_POST", "ld3r"},
+{"LD3Rv2d", "ld3r"},
+{"LD3Rv2d_POST", "ld3r"},
+{"LD3Rv2s", "ld3r"},
+{"LD3Rv2s_POST", "ld3r"},
+{"LD3Rv4h", "ld3r"},
+{"LD3Rv4h_POST", "ld3r"},
+{"LD3Rv4s", "ld3r"},
+{"LD3Rv4s_POST", "ld3r"},
+{"LD3Rv8b", "ld3r"},
+{"LD3Rv8b_POST", "ld3r"},
+{"LD3Rv8h", "ld3r"},
+{"LD3Rv8h_POST", "ld3r"},
+{"LD3Rv16b", "ld3r"},
+{"LD3Rv16b_POST", "ld3r"},
+{"LD3Threev2d", "ld3"},
+{"LD3Threev2d_POST", "ld3"},
+{"LD3Threev2s", "ld3"},
+{"LD3Threev2s_POST", "ld3"},
+{"LD3Threev4h", "ld3"},
+{"LD3Threev4h_POST", "ld3"},
+{"LD3Threev4s", "ld3"},
+{"LD3Threev4s_POST", "ld3"},
+{"LD3Threev8b", "ld3"},
+{"LD3Threev8b_POST", "ld3"},
+{"LD3Threev8h", "ld3"},
+{"LD3Threev8h_POST", "ld3"},
+{"LD3Threev16b", "ld3"},
+{"LD3Threev16b_POST", "ld3"},
+{"LD3i8", "ld3"},
+{"LD3i8_POST", "ld3"},
+{"LD3i16", "ld3"},
+{"LD3i16_POST", "ld3"},
+{"LD3i32", "ld3"},
+{"LD3i32_POST", "ld3"},
+{"LD3i64", "ld3"},
+{"LD3i64_POST", "ld3"},
+{"LD3W", "ld3w"},
+{"LD3W_IMM", "ld3w"},
+{"LD4B", "ld4b"},
+{"LD4B_IMM", "ld4b"},
+{"LD4D", "ld4d"},
+{"LD4D_IMM", "ld4d"},
+{"LD4Fourv2d", "ld4"},
+{"LD4Fourv2d_POST", "ld4"},
+{"LD4Fourv2s", "ld4"},
+{"LD4Fourv2s_POST", "ld4"},
+{"LD4Fourv4h", "ld4"},
+{"LD4Fourv4h_POST", "ld4"},
+{"LD4Fourv4s", "ld4"},
+{"LD4Fourv4s_POST", "ld4"},
+{"LD4Fourv8b", "ld4"},
+{"LD4Fourv8b_POST", "ld4"},
+{"LD4Fourv8h", "ld4"},
+{"LD4Fourv8h_POST", "ld4"},
+{"LD4Fourv16b", "ld4"},
+{"LD4Fourv16b_POST", "ld4"},
+{"LD4i8", "ld4"},
+{"LD4i8_POST", "ld4"},
+{"LD4i16", "ld4"},
+{"LD4i16_POST", "ld4"},
+{"LD4i32", "ld4"},
+{"LD4i32_POST", "ld4"},
+{"LD4i64", "ld4"},
+{"LD4i64_POST", "ld4"},
+{"LD4H", "ld4h"},
+{"LD4H_IMM", "ld4h"},
+{"LD4Q", "ld4q"},
+{"LD4Q_IMM", "ld4q"},
+{"LD4Rv1d", "ld4r"},
+{"LD4Rv1d_POST", "ld4r"},
+{"LD4Rv2d", "ld4r"},
+{"LD4Rv2d_POST", "ld4r"},
+{"LD4Rv2s", "ld4r"},
+{"LD4Rv2s_POST", "ld4r"},
+{"LD4Rv4h", "ld4r"},
+{"LD4Rv4h_POST", "ld4r"},
+{"LD4Rv4s", "ld4r"},
+{"LD4Rv4s_POST", "ld4r"},
+{"LD4Rv8b", "ld4r"},
+{"LD4Rv8b_POST", "ld4r"},
+{"LD4Rv8h", "ld4r"},
+{"LD4Rv8h_POST", "ld4r"},
+{"LD4Rv16b", "ld4r"},
+{"LD4Rv16b_POST", "ld4r"},
+{"LD4W", "ld4w"},
+{"LD4W_IMM", "ld4w"},
+{"LD64B", "ld64b"},
+{"LDADDAB", "ldaddab"},
+{"LDADDAH", "ldaddah"},
+{"LDADDALB", "ldaddalb"},
+{"LDADDALH", "ldaddalh"},
+{"LDADDALW", "ldaddal"},
+{"LDADDALX", "ldaddal"},
+{"LDADDAW", "ldadda"},
+{"LDADDAX", "ldadda"},
+{"LDADDB", "ldaddb"},
+{"LDADDH", "ldaddh"},
+{"LDADDLB", "ldaddlb"},
+{"LDADDLH", "ldaddlh"},
+{"LDADDLW", "ldaddl"},
+{"LDADDLX", "ldaddl"},
+{"LDADDW", "ldadd"},
+{"LDADDX", "ldadd"},
+{"LDAP1", "ldap1"},
+{"LDAPPi", "ldapp"},
+{"LDAPRB", "ldaprb"},
+{"LDAPRH", "ldaprh"},
+{"LDAPRW", "ldapr"},
+{"LDAPRWpost", "ldapr"},
+{"LDAPRX", "ldapr"},
+{"LDAPRXpost", "ldapr"},
+{"LDAPURBi", "ldapurb"},
+{"LDAPURHi", "ldapurh"},
+{"LDAPURSBWi", "ldapursb"},
+{"LDAPURSBXi", "ldapursb"},
+{"LDAPURSHWi", "ldapursh"},
+{"LDAPURSHXi", "ldapursh"},
+{"LDAPURSWi", "ldapursw"},
+{"LDAPURXi", "ldapur"},
+{"LDAPURbi", "ldapur"},
+{"LDAPURdi", "ldapur"},
+{"LDAPURhi", "ldapur"},
+{"LDAPURi", "ldapur"},
+{"LDAPURqi", "ldapur"},
+{"LDAPURsi", "ldapur"},
+{"LDAPi", "ldap"},
+{"LDARB", "ldarb"},
+{"LDARH", "ldarh"},
+{"LDARW", "ldar"},
+{"LDARX", "ldar"},
+{"LDATXRW", "ldatxr"},
+{"LDATXRX", "ldatxr"},
+{"LDAXPW", "ldaxp"},
+{"LDAXPX", "ldaxp"},
+{"LDAXRB", "ldaxrb"},
+{"LDAXRH", "ldaxrh"},
+{"LDAXRW", "ldaxr"},
+{"LDAXRX", "ldaxr"},
+{"LDBFADD", "ldbfadd"},
+{"LDBFADDA", "ldbfadda"},
+{"LDBFADDAL", "ldbfaddal"},
+{"LDBFADDL", "ldbfaddl"},
+{"LDBFMAX", "ldbfmax"},
+{"LDBFMAXA", "ldbfmaxa"},
+{"LDBFMAXAL", "ldbfmaxal"},
+{"LDBFMAXL", "ldbfmaxl"},
+{"LDBFMAXNM", "ldbfmaxnm"},
+{"LDBFMAXNMA", "ldbfmaxnma"},
+{"LDBFMAXNMAL", "ldbfmaxnmal"},
+{"LDBFMAXNML", "ldbfmaxnml"},
+{"LDBFMIN", "ldbfmin"},
+{"LDBFMINA", "ldbfmina"},
+{"LDBFMINAL", "ldbfminal"},
+{"LDBFMINL", "ldbfminl"},
+{"LDBFMINNM", "ldbfminnm"},
+{"LDBFMINNMA", "ldbfminnma"},
+{"LDBFMINNMAL", "ldbfminnmal"},
+{"LDBFMINNML", "ldbfminnml"},
+{"LDCLRAB", "ldclrab"},
+{"LDCLRAH", "ldclrah"},
+{"LDCLRALB", "ldclralb"},
+{"LDCLRALH", "ldclralh"},
+{"LDCLRALW", "ldclral"},
+{"LDCLRALX", "ldclral"},
+{"LDCLRAW", "ldclra"},
+{"LDCLRAX", "ldclra"},
+{"LDCLRB", "ldclrb"},
+{"LDCLRH", "ldclrh"},
+{"LDCLRLB", "ldclrlb"},
+{"LDCLRLH", "ldclrlh"},
+{"LDCLRLW", "ldclrl"},
+{"LDCLRLX", "ldclrl"},
+{"LDCLRP", "ldclrp"},
+{"LDCLRPA", "ldclrpa"},
+{"LDCLRPAL", "ldclrpal"},
+{"LDCLRPL", "ldclrpl"},
+{"LDCLRW", "ldclr"},
+{"LDCLRX", "ldclr"},
+{"LDEORAB", "ldeorab"},
+{"LDEORAH", "ldeorah"},
+{"LDEORALB", "ldeoralb"},
+{"LDEORALH", "ldeoralh"},
+{"LDEORALW", "ldeoral"},
+{"LDEORALX", "ldeoral"},
+{"LDEORAW", "ldeora"},
+{"LDEORAX", "ldeora"},
+{"LDEORB", "ldeorb"},
+{"LDEORH", "ldeorh"},
+{"LDEORLB", "ldeorlb"},
+{"LDEORLH", "ldeorlh"},
+{"LDEORLW", "ldeorl"},
+{"LDEORLX", "ldeorl"},
+{"LDEORW", "ldeor"},
+{"LDEORX", "ldeor"},
+{"LDFADDAD", "ldfadda"},
+{"LDFADDAH", "ldfadda"},
+{"LDFADDAS", "ldfadda"},
+{"LDFADDALD", "ldfaddal"},
+{"LDFADDALH", "ldfaddal"},
+{"LDFADDALS", "ldfaddal"},
+{"LDFADDD", "ldfadd"},
+{"LDFADDH", "ldfadd"},
+{"LDFADDS", "ldfadd"},
+{"LDFADDLD", "ldfaddl"},
+{"LDFADDLH", "ldfaddl"},
+{"LDFADDLS", "ldfaddl"},
+{"LDFMAXAD", "ldfmaxa"},
+{"LDFMAXAH", "ldfmaxa"},
+{"LDFMAXAS", "ldfmaxa"},
+{"LDFMAXALD", "ldfmaxal"},
+{"LDFMAXALH", "ldfmaxal"},
+{"LDFMAXALS", "ldfmaxal"},
+{"LDFMAXD", "ldfmax"},
+{"LDFMAXH", "ldfmax"},
+{"LDFMAXS", "ldfmax"},
+{"LDFMAXLD", "ldfmaxl"},
+{"LDFMAXLH", "ldfmaxl"},
+{"LDFMAXLS", "ldfmaxl"},
+{"LDFMAXNMAD", "ldfmaxnma"},
+{"LDFMAXNMAH", "ldfmaxnma"},
+{"LDFMAXNMAS", "ldfmaxnma"},
+{"LDFMAXNMALD", "ldfmaxnmal"},
+{"LDFMAXNMALH", "ldfmaxnmal"},
+{"LDFMAXNMALS", "ldfmaxnmal"},
+{"LDFMAXNMD", "ldfmaxnm"},
+{"LDFMAXNMH", "ldfmaxnm"},
+{"LDFMAXNMS", "ldfmaxnm"},
+{"LDFMAXNMLD", "ldfmaxnml"},
+{"LDFMAXNMLH", "ldfmaxnml"},
+{"LDFMAXNMLS", "ldfmaxnml"},
+{"LDFMINAD", "ldfmina"},
+{"LDFMINAH", "ldfmina"},
+{"LDFMINAS", "ldfmina"},
+{"LDFMINALD", "ldfminal"},
+{"LDFMINALH", "ldfminal"},
+{"LDFMINALS", "ldfminal"},
+{"LDFMIND", "ldfmin"},
+{"LDFMINH", "ldfmin"},
+{"LDFMINS", "ldfmin"},
+{"LDFMINLD", "ldfminl"},
+{"LDFMINLH", "ldfminl"},
+{"LDFMINLS", "ldfminl"},
+{"LDFMINNMAD", "ldfminnma"},
+{"LDFMINNMAH", "ldfminnma"},
+{"LDFMINNMAS", "ldfminnma"},
+{"LDFMINNMALD", "ldfminnmal"},
+{"LDFMINNMALH", "ldfminnmal"},
+{"LDFMINNMALS", "ldfminnmal"},
+{"LDFMINNMD", "ldfminnm"},
+{"LDFMINNMH", "ldfminnm"},
+{"LDFMINNMS", "ldfminnm"},
+{"LDFMINNMLD", "ldfminnml"},
+{"LDFMINNMLH", "ldfminnml"},
+{"LDFMINNMLS", "ldfminnml"},
+{"LDG", "ldg"},
+{"LDGM", "ldgm"},
+{"LDIAPPW", "ldiapp"},
+{"LDIAPPWpost", "ldiapp"},
+{"LDIAPPX", "ldiapp"},
+{"LDIAPPXpost", "ldiapp"},
+{"LDLARB", "ldlarb"},
+{"LDLARH", "ldlarh"},
+{"LDLARW", "ldlar"},
+{"LDLARX", "ldlar"},
+{"LDNF1B_D_IMM", "ldnf1b"},
+{"LDNF1B_H_IMM", "ldnf1b"},
+{"LDNF1B_IMM", "ldnf1b"},
+{"LDNF1B_S_IMM", "ldnf1b"},
+{"LDNF1D_IMM", "ldnf1d"},
+{"LDNF1H_D_IMM", "ldnf1h"},
+{"LDNF1H_IMM", "ldnf1h"},
+{"LDNF1H_S_IMM", "ldnf1h"},
+{"LDNF1SB_D_IMM", "ldnf1sb"},
+{"LDNF1SB_H_IMM", "ldnf1sb"},
+{"LDNF1SB_S_IMM", "ldnf1sb"},
+{"LDNF1SH_D_IMM", "ldnf1sh"},
+{"LDNF1SH_S_IMM", "ldnf1sh"},
+{"LDNF1SW_D_IMM", "ldnf1sw"},
+{"LDNF1W_D_IMM", "ldnf1w"},
+{"LDNF1W_IMM", "ldnf1w"},
+{"LDNPDi", "ldnp"},
+{"LDNPQi", "ldnp"},
+{"LDNPSi", "ldnp"},
+{"LDNPWi", "ldnp"},
+{"LDNPXi", "ldnp"},
+{"LDNT1B_2Z", "ldnt1b"},
+{"LDNT1B_2Z_IMM", "ldnt1b"},
+{"LDNT1B_2Z_STRIDED", "ldnt1b"},
+{"LDNT1B_2Z_STRIDED_IMM", "ldnt1b"},
+{"LDNT1B_4Z", "ldnt1b"},
+{"LDNT1B_4Z_IMM", "ldnt1b"},
+{"LDNT1B_4Z_STRIDED", "ldnt1b"},
+{"LDNT1B_4Z_STRIDED_IMM", "ldnt1b"},
+{"LDNT1B_ZRI", "ldnt1b"},
+{"LDNT1B_ZRR", "ldnt1b"},
+{"LDNT1B_ZZR_D", "ldnt1b"},
+{"LDNT1B_ZZR_S", "ldnt1b"},
+{"LDNT1D_2Z", "ldnt1d"},
+{"LDNT1D_2Z_IMM", "ldnt1d"},
+{"LDNT1D_2Z_STRIDED", "ldnt1d"},
+{"LDNT1D_2Z_STRIDED_IMM", "ldnt1d"},
+{"LDNT1D_4Z", "ldnt1d"},
+{"LDNT1D_4Z_IMM", "ldnt1d"},
+{"LDNT1D_4Z_STRIDED", "ldnt1d"},
+{"LDNT1D_4Z_STRIDED_IMM", "ldnt1d"},
+{"LDNT1D_ZRI", "ldnt1d"},
+{"LDNT1D_ZRR", "ldnt1d"},
+{"LDNT1D_ZZR_D", "ldnt1d"},
+{"LDNT1H_2Z", "ldnt1h"},
+{"LDNT1H_2Z_IMM", "ldnt1h"},
+{"LDNT1H_2Z_STRIDED", "ldnt1h"},
+{"LDNT1H_2Z_STRIDED_IMM", "ldnt1h"},
+{"LDNT1H_4Z", "ldnt1h"},
+{"LDNT1H_4Z_IMM", "ldnt1h"},
+{"LDNT1H_4Z_STRIDED", "ldnt1h"},
+{"LDNT1H_4Z_STRIDED_IMM", "ldnt1h"},
+{"LDNT1H_ZRI", "ldnt1h"},
+{"LDNT1H_ZRR", "ldnt1h"},
+{"LDNT1H_ZZR_D", "ldnt1h"},
+{"LDNT1H_ZZR_S", "ldnt1h"},
+{"LDNT1SB_ZZR_D", "ldnt1sb"},
+{"LDNT1SB_ZZR_S", "ldnt1sb"},
+{"LDNT1SH_ZZR_D", "ldnt1sh"},
+{"LDNT1SH_ZZR_S", "ldnt1sh"},
+{"LDNT1SW_ZZR_D", "ldnt1sw"},
+{"LDNT1W_2Z", "ldnt1w"},
+{"LDNT1W_2Z_IMM", "ldnt1w"},
+{"LDNT1W_2Z_STRIDED", "ldnt1w"},
+{"LDNT1W_2Z_STRIDED_IMM", "ldnt1w"},
+{"LDNT1W_4Z", "ldnt1w"},
+{"LDNT1W_4Z_IMM", "ldnt1w"},
+{"LDNT1W_4Z_STRIDED", "ldnt1w"},
+{"LDNT1W_4Z_STRIDED_IMM", "ldnt1w"},
+{"LDNT1W_ZRI", "ldnt1w"},
+{"LDNT1W_ZRR", "ldnt1w"},
+{"LDNT1W_ZZR_D", "ldnt1w"},
+{"LDNT1W_ZZR_S", "ldnt1w"},
+{"LDPDi", "ldp"},
+{"LDPDpost", "ldp"},
+{"LDPDpre", "ldp"},
+{"LDPQi", "ldp"},
+{"LDPQpost", "ldp"},
+{"LDPQpre", "ldp"},
+{"LDPSi", "ldp"},
+{"LDPSpost", "ldp"},
+{"LDPSpre", "ldp"},
+{"LDPWi", "ldp"},
+{"LDPWpost", "ldp"},
+{"LDPWpre", "ldp"},
+{"LDPXi", "ldp"},
+{"LDPXpost", "ldp"},
+{"LDPXpre", "ldp"},
+{"LDPSWi", "ldpsw"},
+{"LDPSWpost", "ldpsw"},
+{"LDPSWpre", "ldpsw"},
+{"LDRAAindexed", "ldraa"},
+{"LDRAAwriteback", "ldraa"},
+{"LDRABindexed", "ldrab"},
+{"LDRABwriteback", "ldrab"},
+{"LDRBBpost", "ldrb"},
+{"LDRBBpre", "ldrb"},
+{"LDRBBroW", "ldrb"},
+{"LDRBBroX", "ldrb"},
+{"LDRBBui", "ldrb"},
+{"LDRBpost", "ldr"},
+{"LDRBpre", "ldr"},
+{"LDRBroW", "ldr"},
+{"LDRBroX", "ldr"},
+{"LDRBui", "ldr"},
+{"LDRDl", "ldr"},
+{"LDRDpost", "ldr"},
+{"LDRDpre", "ldr"},
+{"LDRDroW", "ldr"},
+{"LDRDroX", "ldr"},
+{"LDRDui", "ldr"},
+{"LDRHpost", "ldr"},
+{"LDRHpre", "ldr"},
+{"LDRHroW", "ldr"},
+{"LDRHroX", "ldr"},
+{"LDRHui", "ldr"},
+{"LDRQl", "ldr"},
+{"LDRQpost", "ldr"},
+{"LDRQpre", "ldr"},
+{"LDRQroW", "ldr"},
+{"LDRQroX", "ldr"},
+{"LDRQui", "ldr"},
+{"LDRSl", "ldr"},
+{"LDRSpost", "ldr"},
+{"LDRSpre", "ldr"},
+{"LDRSroW", "ldr"},
+{"LDRSroX", "ldr"},
+{"LDRSui", "ldr"},
+{"LDRWl", "ldr"},
+{"LDRWpost", "ldr"},
+{"LDRWpre", "ldr"},
+{"LDRWroW", "ldr"},
+{"LDRWroX", "ldr"},
+{"LDRWui", "ldr"},
+{"LDRXl", "ldr"},
+{"LDRXpost", "ldr"},
+{"LDRXpre", "ldr"},
+{"LDRXroW", "ldr"},
+{"LDRXroX", "ldr"},
+{"LDRXui", "ldr"},
+{"LDR_PXI", "ldr"},
+{"LDR_TX", "ldr"},
+{"LDR_ZA", "ldr"},
+{"LDR_ZXI", "ldr"},
+{"LDRHHpost", "ldrh"},
+{"LDRHHpre", "ldrh"},
+{"LDRHHroW", "ldrh"},
+{"LDRHHroX", "ldrh"},
+{"LDRHHui", "ldrh"},
+{"LDRSBWpost", "ldrsb"},
+{"LDRSBWpre", "ldrsb"},
+{"LDRSBWroW", "ldrsb"},
+{"LDRSBWroX", "ldrsb"},
+{"LDRSBWui", "ldrsb"},
+{"LDRSBXpost", "ldrsb"},
+{"LDRSBXpre", "ldrsb"},
+{"LDRSBXroW", "ldrsb"},
+{"LDRSBXroX", "ldrsb"},
+{"LDRSBXui", "ldrsb"},
+{"LDRSHWpost", "ldrsh"},
+{"LDRSHWpre", "ldrsh"},
+{"LDRSHWroW", "ldrsh"},
+{"LDRSHWroX", "ldrsh"},
+{"LDRSHWui", "ldrsh"},
+{"LDRSHXpost", "ldrsh"},
+{"LDRSHXpre", "ldrsh"},
+{"LDRSHXroW", "ldrsh"},
+{"LDRSHXroX", "ldrsh"},
+{"LDRSHXui", "ldrsh"},
+{"LDRSWl", "ldrsw"},
+{"LDRSWpost", "ldrsw"},
+{"LDRSWpre", "ldrsw"},
+{"LDRSWroW", "ldrsw"},
+{"LDRSWroX", "ldrsw"},
+{"LDRSWui", "ldrsw"},
+{"LDSETAB", "ldsetab"},
+{"LDSETAH", "ldsetah"},
+{"LDSETALB", "ldsetalb"},
+{"LDSETALH", "ldsetalh"},
+{"LDSETALW", "ldsetal"},
+{"LDSETALX", "ldsetal"},
+{"LDSETAW", "ldseta"},
+{"LDSETAX", "ldseta"},
+{"LDSETB", "ldsetb"},
+{"LDSETH", "ldseth"},
+{"LDSETLB", "ldsetlb"},
+{"LDSETLH", "ldsetlh"},
+{"LDSETLW", "ldsetl"},
+{"LDSETLX", "ldsetl"},
+{"LDSETP", "ldsetp"},
+{"LDSETPA", "ldsetpa"},
+{"LDSETPAL", "ldsetpal"},
+{"LDSETPL", "ldsetpl"},
+{"LDSETW", "ldset"},
+{"LDSETX", "ldset"},
+{"LDSMAXAB", "ldsmaxab"},
+{"LDSMAXAH", "ldsmaxah"},
+{"LDSMAXALB", "ldsmaxalb"},
+{"LDSMAXALH", "ldsmaxalh"},
+{"LDSMAXALW", "ldsmaxal"},
+{"LDSMAXALX", "ldsmaxal"},
+{"LDSMAXAW", "ldsmaxa"},
+{"LDSMAXAX", "ldsmaxa"},
+{"LDSMAXB", "ldsmaxb"},
+{"LDSMAXH", "ldsmaxh"},
+{"LDSMAXLB", "ldsmaxlb"},
+{"LDSMAXLH", "ldsmaxlh"},
+{"LDSMAXLW", "ldsmaxl"},
+{"LDSMAXLX", "ldsmaxl"},
+{"LDSMAXW", "ldsmax"},
+{"LDSMAXX", "ldsmax"},
+{"LDSMINAB", "ldsminab"},
+{"LDSMINAH", "ldsminah"},
+{"LDSMINALB", "ldsminalb"},
+{"LDSMINALH", "ldsminalh"},
+{"LDSMINALW", "ldsminal"},
+{"LDSMINALX", "ldsminal"},
+{"LDSMINAW", "ldsmina"},
+{"LDSMINAX", "ldsmina"},
+{"LDSMINB", "ldsminb"},
+{"LDSMINH", "ldsminh"},
+{"LDSMINLB", "ldsminlb"},
+{"LDSMINLH", "ldsminlh"},
+{"LDSMINLW", "ldsminl"},
+{"LDSMINLX", "ldsminl"},
+{"LDSMINW", "ldsmin"},
+{"LDSMINX", "ldsmin"},
+{"LDTADDALW", "ldtaddal"},
+{"LDTADDALX", "ldtaddal"},
+{"LDTADDAW", "ldtadda"},
+{"LDTADDAX", "ldtadda"},
+{"LDTADDLW", "ldtaddl"},
+{"LDTADDLX", "ldtaddl"},
+{"LDTADDW", "ldtadd"},
+{"LDTADDX", "ldtadd"},
+{"LDTCLRALW", "ldtclral"},
+{"LDTCLRALX", "ldtclral"},
+{"LDTCLRAW", "ldtclra"},
+{"LDTCLRAX", "ldtclra"},
+{"LDTCLRLW", "ldtclrl"},
+{"LDTCLRLX", "ldtclrl"},
+{"LDTCLRW", "ldtclr"},
+{"LDTCLRX", "ldtclr"},
+{"LDTNPQi", "ldtnp"},
+{"LDTNPXi", "ldtnp"},
+{"LDTPQi", "ldtp"},
+{"LDTPQpost", "ldtp"},
+{"LDTPQpre", "ldtp"},
+{"LDTPi", "ldtp"},
+{"LDTPpost", "ldtp"},
+{"LDTPpre", "ldtp"},
+{"LDTRBi", "ldtrb"},
+{"LDTRHi", "ldtrh"},
+{"LDTRSBWi", "ldtrsb"},
+{"LDTRSBXi", "ldtrsb"},
+{"LDTRSHWi", "ldtrsh"},
+{"LDTRSHXi", "ldtrsh"},
+{"LDTRSWi", "ldtrsw"},
+{"LDTRWi", "ldtr"},
+{"LDTRXi", "ldtr"},
+{"LDTSETALW", "ldtsetal"},
+{"LDTSETALX", "ldtsetal"},
+{"LDTSETAW", "ldtseta"},
+{"LDTSETAX", "ldtseta"},
+{"LDTSETLW", "ldtsetl"},
+{"LDTSETLX", "ldtsetl"},
+{"LDTSETW", "ldtset"},
+{"LDTSETX", "ldtset"},
+{"LDTXRWr", "ldtxr"},
+{"LDTXRXr", "ldtxr"},
+{"LDUMAXAB", "ldumaxab"},
+{"LDUMAXAH", "ldumaxah"},
+{"LDUMAXALB", "ldumaxalb"},
+{"LDUMAXALH", "ldumaxalh"},
+{"LDUMAXALW", "ldumaxal"},
+{"LDUMAXALX", "ldumaxal"},
+{"LDUMAXAW", "ldumaxa"},
+{"LDUMAXAX", "ldumaxa"},
+{"LDUMAXB", "ldumaxb"},
+{"LDUMAXH", "ldumaxh"},
+{"LDUMAXLB", "ldumaxlb"},
+{"LDUMAXLH", "ldumaxlh"},
+{"LDUMAXLW", "ldumaxl"},
+{"LDUMAXLX", "ldumaxl"},
+{"LDUMAXW", "ldumax"},
+{"LDUMAXX", "ldumax"},
+{"LDUMINAB", "lduminab"},
+{"LDUMINAH", "lduminah"},
+{"LDUMINALB", "lduminalb"},
+{"LDUMINALH", "lduminalh"},
+{"LDUMINALW", "lduminal"},
+{"LDUMINALX", "lduminal"},
+{"LDUMINAW", "ldumina"},
+{"LDUMINAX", "ldumina"},
+{"LDUMINB", "lduminb"},
+{"LDUMINH", "lduminh"},
+{"LDUMINLB", "lduminlb"},
+{"LDUMINLH", "lduminlh"},
+{"LDUMINLW", "lduminl"},
+{"LDUMINLX", "lduminl"},
+{"LDUMINW", "ldumin"},
+{"LDUMINX", "ldumin"},
+{"LDURBBi", "ldurb"},
+{"LDURBi", "ldur"},
+{"LDURDi", "ldur"},
+{"LDURHi", "ldur"},
+{"LDURQi", "ldur"},
+{"LDURSi", "ldur"},
+{"LDURWi", "ldur"},
+{"LDURXi", "ldur"},
+{"LDURHHi", "ldurh"},
+{"LDURSBWi", "ldursb"},
+{"LDURSBXi", "ldursb"},
+{"LDURSHWi", "ldursh"},
+{"LDURSHXi", "ldursh"},
+{"LDURSWi", "ldursw"},
+{"LDXPW", "ldxp"},
+{"LDXPX", "ldxp"},
+{"LDXRB", "ldxrb"},
+{"LDXRH", "ldxrh"},
+{"LDXRW", "ldxr"},
+{"LDXRX", "ldxr"},
+{"LSLR_ZPmZ_B", "lslr"},
+{"LSLR_ZPmZ_D", "lslr"},
+{"LSLR_ZPmZ_H", "lslr"},
+{"LSLR_ZPmZ_S", "lslr"},
+{"LSLVWr", "lsl"},
+{"LSLVXr", "lsl"},
+{"LSL_WIDE_ZPmZ_B", "lsl"},
+{"LSL_WIDE_ZPmZ_H", "lsl"},
+{"LSL_WIDE_ZPmZ_S", "lsl"},
+{"LSL_WIDE_ZZZ_B", "lsl"},
+{"LSL_WIDE_ZZZ_H", "lsl"},
+{"LSL_WIDE_ZZZ_S", "lsl"},
+{"LSL_ZPmI_B", "lsl"},
+{"LSL_ZPmI_D", "lsl"},
+{"LSL_ZPmI_H", "lsl"},
+{"LSL_ZPmI_S", "lsl"},
+{"LSL_ZPmZ_B", "lsl"},
+{"LSL_ZPmZ_D", "lsl"},
+{"LSL_ZPmZ_H", "lsl"},
+{"LSL_ZPmZ_S", "lsl"},
+{"LSL_ZZI_B", "lsl"},
+{"LSL_ZZI_D", "lsl"},
+{"LSL_ZZI_H", "lsl"},
+{"LSL_ZZI_S", "lsl"},
+{"LSRR_ZPmZ_B", "lsrr"},
+{"LSRR_ZPmZ_D", "lsrr"},
+{"LSRR_ZPmZ_H", "lsrr"},
+{"LSRR_ZPmZ_S", "lsrr"},
+{"LSRVWr", "lsr"},
+{"LSRVXr", "lsr"},
+{"LSR_WIDE_ZPmZ_B", "lsr"},
+{"LSR_WIDE_ZPmZ_H", "lsr"},
+{"LSR_WIDE_ZPmZ_S", "lsr"},
+{"LSR_WIDE_ZZZ_B", "lsr"},
+{"LSR_WIDE_ZZZ_H", "lsr"},
+{"LSR_WIDE_ZZZ_S", "lsr"},
+{"LSR_ZPmI_B", "lsr"},
+{"LSR_ZPmI_D", "lsr"},
+{"LSR_ZPmI_H", "lsr"},
+{"LSR_ZPmI_S", "lsr"},
+{"LSR_ZPmZ_B", "lsr"},
+{"LSR_ZPmZ_D", "lsr"},
+{"LSR_ZPmZ_H", "lsr"},
+{"LSR_ZPmZ_S", "lsr"},
+{"LSR_ZZI_B", "lsr"},
+{"LSR_ZZI_D", "lsr"},
+{"LSR_ZZI_H", "lsr"},
+{"LSR_ZZI_S", "lsr"},
+{"LUT2_B", "luti2"},
+{"LUT2_H", "luti2"},
+{"LUTI2_2ZTZI_B", "luti2"},
+{"LUTI2_2ZTZI_H", "luti2"},
+{"LUTI2_2ZTZI_S", "luti2"},
+{"LUTI2_4ZTZI_B", "luti2"},
+{"LUTI2_4ZTZI_H", "luti2"},
+{"LUTI2_4ZTZI_S", "luti2"},
+{"LUTI2_S_2ZTZI_B", "luti2"},
+{"LUTI2_S_2ZTZI_H", "luti2"},
+{"LUTI2_S_4ZTZI_B", "luti2"},
+{"LUTI2_S_4ZTZI_H", "luti2"},
+{"LUTI2_ZTZI_B", "luti2"},
+{"LUTI2_ZTZI_H", "luti2"},
+{"LUTI2_ZTZI_S", "luti2"},
+{"LUTI2_ZZZI_B", "luti2"},
+{"LUTI2_ZZZI_H", "luti2"},
+{"LUT4_B", "luti4"},
+{"LUT4_H", "luti4"},
+{"LUTI4_2ZTZI_B", "luti4"},
+{"LUTI4_2ZTZI_H", "luti4"},
+{"LUTI4_2ZTZI_S", "luti4"},
+{"LUTI4_4ZTZI_H", "luti4"},
+{"LUTI4_4ZTZI_S", "luti4"},
+{"LUTI4_4ZZT2Z", "luti4"},
+{"LUTI4_S_2ZTZI_B", "luti4"},
+{"LUTI4_S_2ZTZI_H", "luti4"},
+{"LUTI4_S_4ZTZI_H", "luti4"},
+{"LUTI4_S_4ZZT2Z", "luti4"},
+{"LUTI4_Z2ZZI", "luti4"},
+{"LUTI4_ZTZI_B", "luti4"},
+{"LUTI4_ZTZI_H", "luti4"},
+{"LUTI4_ZTZI_S", "luti4"},
+{"LUTI4_ZZZI_B", "luti4"},
+{"LUTI4_ZZZI_H", "luti4"},
+{"LUTI6_4Z2Z2ZI", "luti6"},
+{"LUTI6_4ZT3Z", "luti6"},
+{"LUTI6_S_4Z2Z2ZI", "luti6"},
+{"LUTI6_S_4ZT3Z", "luti6"},
+{"LUTI6_Z2ZZ", "luti6"},
+{"LUTI6_Z2ZZI_H", "luti6"},
+{"LUTI6_ZTZ", "luti6"},
+{"MADDPT", "maddpt"},
+{"MADDWrrr", "madd"},
+{"MADDXrrr", "madd"},
+{"MAD_CPA", "madpt"},
+{"MAD_ZPmZZ_B", "mad"},
+{"MAD_ZPmZZ_D", "mad"},
+{"MAD_ZPmZZ_H", "mad"},
+{"MAD_ZPmZZ_S", "mad"},
+{"MATCH_PPzZZ_B", "match"},
+{"MATCH_PPzZZ_H", "match"},
+{"MLA_CPA", "mlapt"},
+{"MLA_ZPmZZ_B", "mla"},
+{"MLA_ZPmZZ_D", "mla"},
+{"MLA_ZPmZZ_H", "mla"},
+{"MLA_ZPmZZ_S", "mla"},
+{"MLA_ZZZI_D", "mla"},
+{"MLA_ZZZI_H", "mla"},
+{"MLA_ZZZI_S", "mla"},
+{"MLAv2i32", "mla"},
+{"MLAv2i32_indexed", "mla"},
+{"MLAv4i16", "mla"},
+{"MLAv4i16_indexed", "mla"},
+{"MLAv4i32", "mla"},
+{"MLAv4i32_indexed", "mla"},
+{"MLAv8i8", "mla"},
+{"MLAv8i16", "mla"},
+{"MLAv8i16_indexed", "mla"},
+{"MLAv16i8", "mla"},
+{"MLS_ZPmZZ_B", "mls"},
+{"MLS_ZPmZZ_D", "mls"},
+{"MLS_ZPmZZ_H", "mls"},
+{"MLS_ZPmZZ_S", "mls"},
+{"MLS_ZZZI_D", "mls"},
+{"MLS_ZZZI_H", "mls"},
+{"MLS_ZZZI_S", "mls"},
+{"MLSv2i32", "mls"},
+{"MLSv2i32_indexed", "mls"},
+{"MLSv4i16", "mls"},
+{"MLSv4i16_indexed", "mls"},
+{"MLSv4i32", "mls"},
+{"MLSv4i32_indexed", "mls"},
+{"MLSv8i8", "mls"},
+{"MLSv8i16", "mls"},
+{"MLSv8i16_indexed", "mls"},
+{"MLSv16i8", "mls"},
+{"MOPSSETGE", "setge"},
+{"MOPSSETGEN", "setgen"},
+{"MOPSSETGET", "setget"},
+{"MOPSSETGETN", "setgetn"},
+{"MOVAZ_2ZMI_H_B", "movaz"},
+{"MOVAZ_2ZMI_H_D", "movaz"},
+{"MOVAZ_2ZMI_H_H", "movaz"},
+{"MOVAZ_2ZMI_H_S", "movaz"},
+{"MOVAZ_2ZMI_V_B", "movaz"},
+{"MOVAZ_2ZMI_V_D", "movaz"},
+{"MOVAZ_2ZMI_V_H", "movaz"},
+{"MOVAZ_2ZMI_V_S", "movaz"},
+{"MOVAZ_4ZMI_H_B", "movaz"},
+{"MOVAZ_4ZMI_H_D", "movaz"},
+{"MOVAZ_4ZMI_H_H", "movaz"},
+{"MOVAZ_4ZMI_H_S", "movaz"},
+{"MOVAZ_4ZMI_V_B", "movaz"},
+{"MOVAZ_4ZMI_V_D", "movaz"},
+{"MOVAZ_4ZMI_V_H", "movaz"},
+{"MOVAZ_4ZMI_V_S", "movaz"},
+{"MOVAZ_VG2_2ZMXI", "movaz"},
+{"MOVAZ_VG4_4ZMXI", "movaz"},
+{"MOVAZ_ZMI_H_B", "movaz"},
+{"MOVAZ_ZMI_H_D", "movaz"},
+{"MOVAZ_ZMI_H_H", "movaz"},
+{"MOVAZ_ZMI_H_Q", "movaz"},
+{"MOVAZ_ZMI_H_S", "movaz"},
+{"MOVAZ_ZMI_V_B", "movaz"},
+{"MOVAZ_ZMI_V_D", "movaz"},
+{"MOVAZ_ZMI_V_H", "movaz"},
+{"MOVAZ_ZMI_V_Q", "movaz"},
+{"MOVAZ_ZMI_V_S", "movaz"},
+{"MOVID", "movi"},
+{"MOVIv2d_ns", "movi"},
+{"MOVIv2i32", "movi"},
+{"MOVIv2s_msl", "movi"},
+{"MOVIv4i16", "movi"},
+{"MOVIv4i32", "movi"},
+{"MOVIv4s_msl", "movi"},
+{"MOVIv8b_ns", "movi"},
+{"MOVIv8i16", "movi"},
+{"MOVIv16b_ns", "movi"},
+{"MOVKWi", "movk"},
+{"MOVKXi", "movk"},
+{"MOVNWi", "movn"},
+{"MOVNXi", "movn"},
+{"MOVPRFX_ZPmZ_B", "movprfx"},
+{"MOVPRFX_ZPmZ_D", "movprfx"},
+{"MOVPRFX_ZPmZ_H", "movprfx"},
+{"MOVPRFX_ZPmZ_S", "movprfx"},
+{"MOVPRFX_ZPzZ_B", "movprfx"},
+{"MOVPRFX_ZPzZ_D", "movprfx"},
+{"MOVPRFX_ZPzZ_H", "movprfx"},
+{"MOVPRFX_ZPzZ_S", "movprfx"},
+{"MOVPRFX_ZZ", "movprfx"},
+{"MOVT_TIX", "movt"},
+{"MOVT_TIZ", "movt"},
+{"MOVT_XTI", "movt"},
+{"MOVZWi", "movz"},
+{"MOVZXi", "movz"},
+{"MRRS", "mrrs"},
+{"MRS", "mrs"},
+{"MSB_ZPmZZ_B", "msb"},
+{"MSB_ZPmZZ_D", "msb"},
+{"MSB_ZPmZZ_H", "msb"},
+{"MSB_ZPmZZ_S", "msb"},
+{"MSR", "msr"},
+{"MSRpstateImm1", "msr"},
+{"MSRpstateImm4", "msr"},
+{"MSRpstatesvcrImm1", "msr"},
+{"MSRR", "msrr"},
+{"MSUBPT", "msubpt"},
+{"MSUBWrrr", "msub"},
+{"MSUBXrrr", "msub"},
+{"MUL_ZI_B", "mul"},
+{"MUL_ZI_D", "mul"},
+{"MUL_ZI_H", "mul"},
+{"MUL_ZI_S", "mul"},
+{"MUL_ZPmZ_B", "mul"},
+{"MUL_ZPmZ_D", "mul"},
+{"MUL_ZPmZ_H", "mul"},
+{"MUL_ZPmZ_S", "mul"},
+{"MUL_ZZZI_D", "mul"},
+{"MUL_ZZZI_H", "mul"},
+{"MUL_ZZZI_S", "mul"},
+{"MUL_ZZZ_B", "mul"},
+{"MUL_ZZZ_D", "mul"},
+{"MUL_ZZZ_H", "mul"},
+{"MUL_ZZZ_S", "mul"},
+{"MULv2i32", "mul"},
+{"MULv2i32_indexed", "mul"},
+{"MULv4i16", "mul"},
+{"MULv4i16_indexed", "mul"},
+{"MULv4i32", "mul"},
+{"MULv4i32_indexed", "mul"},
+{"MULv8i8", "mul"},
+{"MULv8i16", "mul"},
+{"MULv8i16_indexed", "mul"},
+{"MULv16i8", "mul"},
+{"MVNIv2i32", "mvni"},
+{"MVNIv2s_msl", "mvni"},
+{"MVNIv4i16", "mvni"},
+{"MVNIv4i32", "mvni"},
+{"MVNIv4s_msl", "mvni"},
+{"MVNIv8i16", "mvni"},
+{"NANDS_PPzPP", "nands"},
+{"NAND_PPzPP", "nand"},
+{"NBSL_ZZZZ", "nbsl"},
+{"NEG_ZPmZ_B", "neg"},
+{"NEG_ZPmZ_D", "neg"},
+{"NEG_ZPmZ_H", "neg"},
+{"NEG_ZPmZ_S", "neg"},
+{"NEG_ZPzZ_B", "neg"},
+{"NEG_ZPzZ_D", "neg"},
+{"NEG_ZPzZ_H", "neg"},
+{"NEG_ZPzZ_S", "neg"},
+{"NEGv1i64", "neg"},
+{"NEGv2i32", "neg"},
+{"NEGv2i64", "neg"},
+{"NEGv4i16", "neg"},
+{"NEGv4i32", "neg"},
+{"NEGv8i8", "neg"},
+{"NEGv8i16", "neg"},
+{"NEGv16i8", "neg"},
+{"NMATCH_PPzZZ_B", "nmatch"},
+{"NMATCH_PPzZZ_H", "nmatch"},
+{"NORS_PPzPP", "nors"},
+{"NOR_PPzPP", "nor"},
+{"NOT_ZPmZ_B", "not"},
+{"NOT_ZPmZ_D", "not"},
+{"NOT_ZPmZ_H", "not"},
+{"NOT_ZPmZ_S", "not"},
+{"NOT_ZPzZ_B", "not"},
+{"NOT_ZPzZ_D", "not"},
+{"NOT_ZPzZ_H", "not"},
+{"NOT_ZPzZ_S", "not"},
+{"NOTv8i8", "not"},
+{"NOTv16i8", "not"},
+{"ORNS_PPzPP", "orns"},
+{"ORNWrs", "orn"},
+{"ORNXrs", "orn"},
+{"ORN_PPzPP", "orn"},
+{"ORNv8i8", "orn"},
+{"ORNv16i8", "orn"},
+{"ORQV_VPZ_B", "orqv"},
+{"ORQV_VPZ_D", "orqv"},
+{"ORQV_VPZ_H", "orqv"},
+{"ORQV_VPZ_S", "orqv"},
+{"ORRS_PPzPP", "orrs"},
+{"ORRWri", "orr"},
+{"ORRWrs", "orr"},
+{"ORRXri", "orr"},
+{"ORRXrs", "orr"},
+{"ORR_PPzPP", "orr"},
+{"ORR_ZI", "orr"},
+{"ORR_ZPmZ_B", "orr"},
+{"ORR_ZPmZ_D", "orr"},
+{"ORR_ZPmZ_H", "orr"},
+{"ORR_ZPmZ_S", "orr"},
+{"ORR_ZZZ", "orr"},
+{"ORRv2i32", "orr"},
+{"ORRv4i16", "orr"},
+{"ORRv4i32", "orr"},
+{"ORRv8i8", "orr"},
+{"ORRv8i16", "orr"},
+{"ORRv16i8", "orr"},
+{"ORV_VPZ_B", "orv"},
+{"ORV_VPZ_D", "orv"},
+{"ORV_VPZ_H", "orv"},
+{"ORV_VPZ_S", "orv"},
+{"PACDA", "pacda"},
+{"PACDB", "pacdb"},
+{"PACDZA", "pacdza"},
+{"PACDZB", "pacdzb"},
+{"PACGA", "pacga"},
+{"PACIA", "pacia"},
+{"PACIA171615", "pacia171615"},
+{"PACIASPPC", "paciasppc"},
+{"PACIB", "pacib"},
+{"PACIB171615", "pacib171615"},
+{"PACIBSPPC", "pacibsppc"},
+{"PACIZA", "paciza"},
+{"PACIZB", "pacizb"},
+{"PACNBIASPPC", "pacnbiasppc"},
+{"PACNBIBSPPC", "pacnbibsppc"},
+{"PEXT_2PCI_B", "pext"},
+{"PEXT_2PCI_D", "pext"},
+{"PEXT_2PCI_H", "pext"},
+{"PEXT_2PCI_S", "pext"},
+{"PEXT_PCI_B", "pext"},
+{"PEXT_PCI_D", "pext"},
+{"PEXT_PCI_H", "pext"},
+{"PEXT_PCI_S", "pext"},
+{"PFALSE", "pfalse"},
+{"PFIRST_B", "pfirst"},
+{"PMLAL_2ZZZ_Q", "pmlal"},
+{"PMOV_PZI_B", "pmov"},
+{"PMOV_PZI_D", "pmov"},
+{"PMOV_PZI_H", "pmov"},
+{"PMOV_PZI_S", "pmov"},
+{"PMOV_ZIP_B", "pmov"},
+{"PMOV_ZIP_D", "pmov"},
+{"PMOV_ZIP_H", "pmov"},
+{"PMOV_ZIP_S", "pmov"},
+{"PMULLB_ZZZ_D", "pmullb"},
+{"PMULLB_ZZZ_H", "pmullb"},
+{"PMULLB_ZZZ_Q", "pmullb"},
+{"PMULLT_ZZZ_D", "pmullt"},
+{"PMULLT_ZZZ_H", "pmullt"},
+{"PMULLT_ZZZ_Q", "pmullt"},
+{"PMULL_2ZZZ_Q", "pmull"},
+{"PMULLv1i64", "pmull"},
+{"PMULLv8i8", "pmull"},
+{"PMULLv2i64", "pmull2"},
+{"PMULLv16i8", "pmull2"},
+{"PMUL_ZZZ_B", "pmul"},
+{"PMULv8i8", "pmul"},
+{"PMULv16i8", "pmul"},
+{"PNEXT_B", "pnext"},
+{"PNEXT_D", "pnext"},
+{"PNEXT_H", "pnext"},
+{"PNEXT_S", "pnext"},
+{"PRFB_D_PZI", "prfb"},
+{"PRFB_D_SCALED", "prfb"},
+{"PRFB_D_SXTW_SCALED", "prfb"},
+{"PRFB_D_UXTW_SCALED", "prfb"},
+{"PRFB_PRI", "prfb"},
+{"PRFB_PRR", "prfb"},
+{"PRFB_S_PZI", "prfb"},
+{"PRFB_S_SXTW_SCALED", "prfb"},
+{"PRFB_S_UXTW_SCALED", "prfb"},
+{"PRFD_D_PZI", "prfd"},
+{"PRFD_D_SCALED", "prfd"},
+{"PRFD_D_SXTW_SCALED", "prfd"},
+{"PRFD_D_UXTW_SCALED", "prfd"},
+{"PRFD_PRI", "prfd"},
+{"PRFD_PRR", "prfd"},
+{"PRFD_S_PZI", "prfd"},
+{"PRFD_S_SXTW_SCALED", "prfd"},
+{"PRFD_S_UXTW_SCALED", "prfd"},
+{"PRFH_D_PZI", "prfh"},
+{"PRFH_D_SCALED", "prfh"},
+{"PRFH_D_SXTW_SCALED", "prfh"},
+{"PRFH_D_UXTW_SCALED", "prfh"},
+{"PRFH_PRI", "prfh"},
+{"PRFH_PRR", "prfh"},
+{"PRFH_S_PZI", "prfh"},
+{"PRFH_S_SXTW_SCALED", "prfh"},
+{"PRFH_S_UXTW_SCALED", "prfh"},
+{"PRFMl", "prfm"},
+{"PRFMroW", "prfm"},
+{"PRFMroX", "prfm"},
+{"PRFMui", "prfm"},
+{"PRFUMi", "prfum"},
+{"PRFW_D_PZI", "prfw"},
+{"PRFW_D_SCALED", "prfw"},
+{"PRFW_D_SXTW_SCALED", "prfw"},
+{"PRFW_D_UXTW_SCALED", "prfw"},
+{"PRFW_PRI", "prfw"},
+{"PRFW_PRR", "prfw"},
+{"PRFW_S_PZI", "prfw"},
+{"PRFW_S_SXTW_SCALED", "prfw"},
+{"PRFW_S_UXTW_SCALED", "prfw"},
+{"PSEL_PPPRI_B", "psel"},
+{"PSEL_PPPRI_D", "psel"},
+{"PSEL_PPPRI_H", "psel"},
+{"PSEL_PPPRI_S", "psel"},
+{"PTEST_PP", "ptest"},
+{"PTRUES_B", "ptrues"},
+{"PTRUES_D", "ptrues"},
+{"PTRUES_H", "ptrues"},
+{"PTRUES_S", "ptrues"},
+{"PTRUE_B", "ptrue"},
+{"PTRUE_C_B", "ptrue"},
+{"PTRUE_C_D", "ptrue"},
+{"PTRUE_C_H", "ptrue"},
+{"PTRUE_C_S", "ptrue"},
+{"PTRUE_D", "ptrue"},
+{"PTRUE_H", "ptrue"},
+{"PTRUE_S", "ptrue"},
+{"PUNPKHI_PP", "punpkhi"},
+{"PUNPKLO_PP", "punpklo"},
+{"RADDHNB_ZZZ_B", "raddhnb"},
+{"RADDHNB_ZZZ_H", "raddhnb"},
+{"RADDHNB_ZZZ_S", "raddhnb"},
+{"RADDHNT_ZZZ_B", "raddhnt"},
+{"RADDHNT_ZZZ_H", "raddhnt"},
+{"RADDHNT_ZZZ_S", "raddhnt"},
+{"RADDHNv2i64_v2i32", "raddhn"},
+{"RADDHNv4i32_v4i16", "raddhn"},
+{"RADDHNv8i16_v8i8", "raddhn"},
+{"RADDHNv2i64_v4i32", "raddhn2"},
+{"RADDHNv4i32_v8i16", "raddhn2"},
+{"RADDHNv8i16_v16i8", "raddhn2"},
+{"RAX1", "rax1"},
+{"RAX1_ZZZ_D", "rax1"},
+{"RBITWr", "rbit"},
+{"RBITXr", "rbit"},
+{"RBIT_ZPmZ_B", "rbit"},
+{"RBIT_ZPmZ_D", "rbit"},
+{"RBIT_ZPmZ_H", "rbit"},
+{"RBIT_ZPmZ_S", "rbit"},
+{"RBIT_ZPzZ_B", "rbit"},
+{"RBIT_ZPzZ_D", "rbit"},
+{"RBIT_ZPzZ_H", "rbit"},
+{"RBIT_ZPzZ_S", "rbit"},
+{"RBITv8i8", "rbit"},
+{"RBITv16i8", "rbit"},
+{"RCWCAS", "rcwcas"},
+{"RCWCASA", "rcwcasa"},
+{"RCWCASAL", "rcwcasal"},
+{"RCWCASL", "rcwcasl"},
+{"RCWCASP", "rcwcasp"},
+{"RCWCASPA", "rcwcaspa"},
+{"RCWCASPAL", "rcwcaspal"},
+{"RCWCASPL", "rcwcaspl"},
+{"RCWCLR", "rcwclr"},
+{"RCWCLRA", "rcwclra"},
+{"RCWCLRAL", "rcwclral"},
+{"RCWCLRL", "rcwclrl"},
+{"RCWCLRP", "rcwclrp"},
+{"RCWCLRPA", "rcwclrpa"},
+{"RCWCLRPAL", "rcwclrpal"},
+{"RCWCLRPL", "rcwclrpl"},
+{"RCWCLRS", "rcwsclr"},
+{"RCWCLRSA", "rcwsclra"},
+{"RCWCLRSAL", "rcwsclral"},
+{"RCWCLRSL", "rcwsclrl"},
+{"RCWCLRSP", "rcwsclrp"},
+{"RCWCLRSPA", "rcwsclrpa"},
+{"RCWCLRSPAL", "rcwsclrpal"},
+{"RCWCLRSPL", "rcwsclrpl"},
+{"RCWSCAS", "rcwscas"},
+{"RCWSCASA", "rcwscasa"},
+{"RCWSCASAL", "rcwscasal"},
+{"RCWSCASL", "rcwscasl"},
+{"RCWSCASP", "rcwscasp"},
+{"RCWSCASPA", "rcwscaspa"},
+{"RCWSCASPAL", "rcwscaspal"},
+{"RCWSCASPL", "rcwscaspl"},
+{"RCWSET", "rcwset"},
+{"RCWSETA", "rcwseta"},
+{"RCWSETAL", "rcwsetal"},
+{"RCWSETL", "rcwsetl"},
+{"RCWSETP", "rcwsetp"},
+{"RCWSETPA", "rcwsetpa"},
+{"RCWSETPAL", "rcwsetpal"},
+{"RCWSETPL", "rcwsetpl"},
+{"RCWSETS", "rcwsset"},
+{"RCWSETSA", "rcwsseta"},
+{"RCWSETSAL", "rcwssetal"},
+{"RCWSETSL", "rcwssetl"},
+{"RCWSETSP", "rcwssetp"},
+{"RCWSETSPA", "rcwssetpa"},
+{"RCWSETSPAL", "rcwssetpal"},
+{"RCWSETSPL", "rcwssetpl"},
+{"RCWSWP", "rcwswp"},
+{"RCWSWPA", "rcwswpa"},
+{"RCWSWPAL", "rcwswpal"},
+{"RCWSWPL", "rcwswpl"},
+{"RCWSWPP", "rcwswpp"},
+{"RCWSWPPA", "rcwswppa"},
+{"RCWSWPPAL", "rcwswppal"},
+{"RCWSWPPL", "rcwswppl"},
+{"RCWSWPS", "rcwsswp"},
+{"RCWSWPSA", "rcwsswpa"},
+{"RCWSWPSAL", "rcwsswpal"},
+{"RCWSWPSL", "rcwsswpl"},
+{"RCWSWPSP", "rcwsswpp"},
+{"RCWSWPSPA", "rcwsswppa"},
+{"RCWSWPSPAL", "rcwsswppal"},
+{"RCWSWPSPL", "rcwsswppl"},
+{"RDFFRS_PPz", "rdffrs"},
+{"RDFFR_P", "rdffr"},
+{"RDFFR_PPz", "rdffr"},
+{"RDSVLI_XI", "rdsvl"},
+{"RDVLI_XI", "rdvl"},
+{"RET", "ret"},
+{"RETAA", "retaa"},
+{"RETAASPPCi", "retaasppc"},
+{"RETAASPPCr", "retaasppcr"},
+{"RETAB", "retab"},
+{"RETABSPPCi", "retabsppc"},
+{"RETABSPPCr", "retabsppcr"},
+{"REV16Wr", "rev16"},
+{"REV16Xr", "rev16"},
+{"REV16v8i8", "rev16"},
+{"REV16v16i8", "rev16"},
+{"REV32Xr", "rev32"},
+{"REV32v4i16", "rev32"},
+{"REV32v8i8", "rev32"},
+{"REV32v8i16", "rev32"},
+{"REV32v16i8", "rev32"},
+{"REV64v2i32", "rev64"},
+{"REV64v4i16", "rev64"},
+{"REV64v4i32", "rev64"},
+{"REV64v8i8", "rev64"},
+{"REV64v8i16", "rev64"},
+{"REV64v16i8", "rev64"},
+{"REVB_ZPmZ_D", "revb"},
+{"REVB_ZPmZ_H", "revb"},
+{"REVB_ZPmZ_S", "revb"},
+{"REVB_ZPzZ_D", "revb"},
+{"REVB_ZPzZ_H", "revb"},
+{"REVB_ZPzZ_S", "revb"},
+{"REVD_ZPmZ", "revd"},
+{"REVD_ZPzZ", "revd"},
+{"REVH_ZPmZ_D", "revh"},
+{"REVH_ZPmZ_S", "revh"},
+{"REVH_ZPzZ_D", "revh"},
+{"REVH_ZPzZ_S", "revh"},
+{"REVW_ZPmZ_D", "revw"},
+{"REVW_ZPzZ_D", "revw"},
+{"REVWr", "rev"},
+{"REVXr", "rev"},
+{"REV_PP_B", "rev"},
+{"REV_PP_D", "rev"},
+{"REV_PP_H", "rev"},
+{"REV_PP_S", "rev"},
+{"REV_ZZ_B", "rev"},
+{"REV_ZZ_D", "rev"},
+{"REV_ZZ_H", "rev"},
+{"REV_ZZ_S", "rev"},
+{"RMIF", "rmif"},
+{"RORVWr", "ror"},
+{"RORVXr", "ror"},
+{"RPRFM", "rprfm"},
+{"RSHRNB_ZZI_B", "rshrnb"},
+{"RSHRNB_ZZI_H", "rshrnb"},
+{"RSHRNB_ZZI_S", "rshrnb"},
+{"RSHRNT_ZZI_B", "rshrnt"},
+{"RSHRNT_ZZI_H", "rshrnt"},
+{"RSHRNT_ZZI_S", "rshrnt"},
+{"RSHRNv2i32_shift", "rshrn"},
+{"RSHRNv4i16_shift", "rshrn"},
+{"RSHRNv8i8_shift", "rshrn"},
+{"RSHRNv4i32_shift", "rshrn2"},
+{"RSHRNv8i16_shift", "rshrn2"},
+{"RSHRNv16i8_shift", "rshrn2"},
+{"RSUBHNB_ZZZ_B", "rsubhnb"},
+{"RSUBHNB_ZZZ_H", "rsubhnb"},
+{"RSUBHNB_ZZZ_S", "rsubhnb"},
+{"RSUBHNT_ZZZ_B", "rsubhnt"},
+{"RSUBHNT_ZZZ_H", "rsubhnt"},
+{"RSUBHNT_ZZZ_S", "rsubhnt"},
+{"RSUBHNv2i64_v2i32", "rsubhn"},
+{"RSUBHNv4i32_v4i16", "rsubhn"},
+{"RSUBHNv8i16_v8i8", "rsubhn"},
+{"RSUBHNv2i64_v4i32", "rsubhn2"},
+{"RSUBHNv4i32_v8i16", "rsubhn2"},
+{"RSUBHNv8i16_v16i8", "rsubhn2"},
+{"SABALB_ZZZ_D", "sabalb"},
+{"SABALB_ZZZ_H", "sabalb"},
+{"SABALB_ZZZ_S", "sabalb"},
+{"SABALT_ZZZ_D", "sabalt"},
+{"SABALT_ZZZ_H", "sabalt"},
+{"SABALT_ZZZ_S", "sabalt"},
+{"SABAL_ZZZ_BtoH", "sabal"},
+{"SABAL_ZZZ_HtoS", "sabal"},
+{"SABAL_ZZZ_StoD", "sabal"},
+{"SABALv2i32_v2i64", "sabal"},
+{"SABALv4i16_v4i32", "sabal"},
+{"SABALv8i8_v8i16", "sabal"},
+{"SABALv4i32_v2i64", "sabal2"},
+{"SABALv8i16_v4i32", "sabal2"},
+{"SABALv16i8_v8i16", "sabal2"},
+{"SABA_ZZZ_B", "saba"},
+{"SABA_ZZZ_D", "saba"},
+{"SABA_ZZZ_H", "saba"},
+{"SABA_ZZZ_S", "saba"},
+{"SABAv2i32", "saba"},
+{"SABAv4i16", "saba"},
+{"SABAv4i32", "saba"},
+{"SABAv8i8", "saba"},
+{"SABAv8i16", "saba"},
+{"SABAv16i8", "saba"},
+{"SABDLB_ZZZ_D", "sabdlb"},
+{"SABDLB_ZZZ_H", "sabdlb"},
+{"SABDLB_ZZZ_S", "sabdlb"},
+{"SABDLT_ZZZ_D", "sabdlt"},
+{"SABDLT_ZZZ_H", "sabdlt"},
+{"SABDLT_ZZZ_S", "sabdlt"},
+{"SABDLv2i32_v2i64", "sabdl"},
+{"SABDLv4i16_v4i32", "sabdl"},
+{"SABDLv8i8_v8i16", "sabdl"},
+{"SABDLv4i32_v2i64", "sabdl2"},
+{"SABDLv8i16_v4i32", "sabdl2"},
+{"SABDLv16i8_v8i16", "sabdl2"},
+{"SABD_ZPmZ_B", "sabd"},
+{"SABD_ZPmZ_D", "sabd"},
+{"SABD_ZPmZ_H", "sabd"},
+{"SABD_ZPmZ_S", "sabd"},
+{"SABDv2i32", "sabd"},
+{"SABDv4i16", "sabd"},
+{"SABDv4i32", "sabd"},
+{"SABDv8i8", "sabd"},
+{"SABDv8i16", "sabd"},
+{"SABDv16i8", "sabd"},
+{"SADALP_ZPmZ_D", "sadalp"},
+{"SADALP_ZPmZ_H", "sadalp"},
+{"SADALP_ZPmZ_S", "sadalp"},
+{"SADALPv2i32_v1i64", "sadalp"},
+{"SADALPv4i16_v2i32", "sadalp"},
+{"SADALPv4i32_v2i64", "sadalp"},
+{"SADALPv8i8_v4i16", "sadalp"},
+{"SADALPv8i16_v4i32", "sadalp"},
+{"SADALPv16i8_v8i16", "sadalp"},
+{"SADDLBT_ZZZ_D", "saddlbt"},
+{"SADDLBT_ZZZ_H", "saddlbt"},
+{"SADDLBT_ZZZ_S", "saddlbt"},
+{"SADDLB_ZZZ_D", "saddlb"},
+{"SADDLB_ZZZ_H", "saddlb"},
+{"SADDLB_ZZZ_S", "saddlb"},
+{"SADDLPv2i32_v1i64", "saddlp"},
+{"SADDLPv4i16_v2i32", "saddlp"},
+{"SADDLPv4i32_v2i64", "saddlp"},
+{"SADDLPv8i8_v4i16", "saddlp"},
+{"SADDLPv8i16_v4i32", "saddlp"},
+{"SADDLPv16i8_v8i16", "saddlp"},
+{"SADDLT_ZZZ_D", "saddlt"},
+{"SADDLT_ZZZ_H", "saddlt"},
+{"SADDLT_ZZZ_S", "saddlt"},
+{"SADDLVv4i16v", "saddlv"},
+{"SADDLVv4i32v", "saddlv"},
+{"SADDLVv8i8v", "saddlv"},
+{"SADDLVv8i16v", "saddlv"},
+{"SADDLVv16i8v", "saddlv"},
+{"SADDLv2i32_v2i64", "saddl"},
+{"SADDLv4i16_v4i32", "saddl"},
+{"SADDLv8i8_v8i16", "saddl"},
+{"SADDLv4i32_v2i64", "saddl2"},
+{"SADDLv8i16_v4i32", "saddl2"},
+{"SADDLv16i8_v8i16", "saddl2"},
+{"SADDV_VPZ_B", "saddv"},
+{"SADDV_VPZ_H", "saddv"},
+{"SADDV_VPZ_S", "saddv"},
+{"SADDWB_ZZZ_D", "saddwb"},
+{"SADDWB_ZZZ_H", "saddwb"},
+{"SADDWB_ZZZ_S", "saddwb"},
+{"SADDWT_ZZZ_D", "saddwt"},
+{"SADDWT_ZZZ_H", "saddwt"},
+{"SADDWT_ZZZ_S", "saddwt"},
+{"SADDWv2i32_v2i64", "saddw"},
+{"SADDWv4i16_v4i32", "saddw"},
+{"SADDWv8i8_v8i16", "saddw"},
+{"SADDWv4i32_v2i64", "saddw2"},
+{"SADDWv8i16_v4i32", "saddw2"},
+{"SADDWv16i8_v8i16", "saddw2"},
+{"SB", "sb"},
+{"SBCLB_ZZZ_D", "sbclb"},
+{"SBCLB_ZZZ_S", "sbclb"},
+{"SBCLT_ZZZ_D", "sbclt"},
+{"SBCLT_ZZZ_S", "sbclt"},
+{"SBCSWr", "sbcs"},
+{"SBCSXr", "sbcs"},
+{"SBCWr", "sbc"},
+{"SBCXr", "sbc"},
+{"SBFMWri", "sbfm"},
+{"SBFMXri", "sbfm"},
+{"SCLAMP_VG2_2Z2Z_B", "sclamp"},
+{"SCLAMP_VG2_2Z2Z_D", "sclamp"},
+{"SCLAMP_VG2_2Z2Z_H", "sclamp"},
+{"SCLAMP_VG2_2Z2Z_S", "sclamp"},
+{"SCLAMP_VG4_4Z4Z_B", "sclamp"},
+{"SCLAMP_VG4_4Z4Z_D", "sclamp"},
+{"SCLAMP_VG4_4Z4Z_H", "sclamp"},
+{"SCLAMP_VG4_4Z4Z_S", "sclamp"},
+{"SCLAMP_ZZZ_B", "sclamp"},
+{"SCLAMP_ZZZ_D", "sclamp"},
+{"SCLAMP_ZZZ_H", "sclamp"},
+{"SCLAMP_ZZZ_S", "sclamp"},
+{"SCVTFDSr", "scvtf"},
+{"SCVTFHDr", "scvtf"},
+{"SCVTFHSr", "scvtf"},
+{"SCVTFSDr", "scvtf"},
+{"SCVTFSWDri", "scvtf"},
+{"SCVTFSWHri", "scvtf"},
+{"SCVTFSWSri", "scvtf"},
+{"SCVTFSXDri", "scvtf"},
+{"SCVTFSXHri", "scvtf"},
+{"SCVTFSXSri", "scvtf"},
+{"SCVTFUWDri", "scvtf"},
+{"SCVTFUWHri", "scvtf"},
+{"SCVTFUWSri", "scvtf"},
+{"SCVTFUXDri", "scvtf"},
+{"SCVTFUXHri", "scvtf"},
+{"SCVTFUXSri", "scvtf"},
+{"SCVTF_2Z2Z_StoS", "scvtf"},
+{"SCVTF_4Z4Z_StoS", "scvtf"},
+{"SCVTF_ZPmZ_DtoD", "scvtf"},
+{"SCVTF_ZPmZ_DtoH", "scvtf"},
+{"SCVTF_ZPmZ_DtoS", "scvtf"},
+{"SCVTF_ZPmZ_HtoH", "scvtf"},
+{"SCVTF_ZPmZ_StoD", "scvtf"},
+{"SCVTF_ZPmZ_StoH", "scvtf"},
+{"SCVTF_ZPmZ_StoS", "scvtf"},
+{"SCVTF_ZPzZ_DtoD", "scvtf"},
+{"SCVTF_ZPzZ_DtoH", "scvtf"},
+{"SCVTF_ZPzZ_DtoS", "scvtf"},
+{"SCVTF_ZPzZ_HtoH", "scvtf"},
+{"SCVTF_ZPzZ_StoD", "scvtf"},
+{"SCVTF_ZPzZ_StoH", "scvtf"},
+{"SCVTF_ZPzZ_StoS", "scvtf"},
+{"SCVTF_ZZ_BtoH", "scvtf"},
+{"SCVTF_ZZ_HtoS", "scvtf"},
+{"SCVTF_ZZ_StoD", "scvtf"},
+{"SCVTFd", "scvtf"},
+{"SCVTFh", "scvtf"},
+{"SCVTFs", "scvtf"},
+{"SCVTFv1i16", "scvtf"},
+{"SCVTFv1i32", "scvtf"},
+{"SCVTFv1i64", "scvtf"},
+{"SCVTFv2f32", "scvtf"},
+{"SCVTFv2f64", "scvtf"},
+{"SCVTFv2i32_shift", "scvtf"},
+{"SCVTFv2i64_shift", "scvtf"},
+{"SCVTFv4f16", "scvtf"},
+{"SCVTFv4f32", "scvtf"},
+{"SCVTFv4i16_shift", "scvtf"},
+{"SCVTFv4i32_shift", "scvtf"},
+{"SCVTFv8f16", "scvtf"},
+{"SCVTFv8i16_shift", "scvtf"},
+{"SCVTFLT_ZZ_BtoH", "scvtflt"},
+{"SCVTFLT_ZZ_HtoS", "scvtflt"},
+{"SCVTFLT_ZZ_StoD", "scvtflt"},
+{"SDIVR_ZPmZ_D", "sdivr"},
+{"SDIVR_ZPmZ_S", "sdivr"},
+{"SDIVWr", "sdiv"},
+{"SDIVXr", "sdiv"},
+{"SDIV_ZPmZ_D", "sdiv"},
+{"SDIV_ZPmZ_S", "sdiv"},
+{"SDOT_VG2_M2Z2Z_BtoS", "sdot"},
+{"SDOT_VG2_M2Z2Z_HtoD", "sdot"},
+{"SDOT_VG2_M2Z2Z_HtoS", "sdot"},
+{"SDOT_VG2_M2ZZI_BToS", "sdot"},
+{"SDOT_VG2_M2ZZI_HToS", "sdot"},
+{"SDOT_VG2_M2ZZI_HtoD", "sdot"},
+{"SDOT_VG2_M2ZZ_BtoS", "sdot"},
+{"SDOT_VG2_M2ZZ_HtoD", "sdot"},
+{"SDOT_VG2_M2ZZ_HtoS", "sdot"},
+{"SDOT_VG4_M4Z4Z_BtoS", "sdot"},
+{"SDOT_VG4_M4Z4Z_HtoD", "sdot"},
+{"SDOT_VG4_M4Z4Z_HtoS", "sdot"},
+{"SDOT_VG4_M4ZZI_BToS", "sdot"},
+{"SDOT_VG4_M4ZZI_HToS", "sdot"},
+{"SDOT_VG4_M4ZZI_HtoD", "sdot"},
+{"SDOT_VG4_M4ZZ_BtoS", "sdot"},
+{"SDOT_VG4_M4ZZ_HtoD", "sdot"},
+{"SDOT_VG4_M4ZZ_HtoS", "sdot"},
+{"SDOT_ZZZI_BtoH", "sdot"},
+{"SDOT_ZZZI_BtoS", "sdot"},
+{"SDOT_ZZZI_HtoD", "sdot"},
+{"SDOT_ZZZI_HtoS", "sdot"},
+{"SDOT_ZZZ_BtoH", "sdot"},
+{"SDOT_ZZZ_BtoS", "sdot"},
+{"SDOT_ZZZ_HtoD", "sdot"},
+{"SDOT_ZZZ_HtoS", "sdot"},
+{"SDOTlanev8i8", "sdot"},
+{"SDOTlanev16i8", "sdot"},
+{"SDOTv8i8", "sdot"},
+{"SDOTv16i8", "sdot"},
+{"SEL_PPPP", "sel"},
+{"SEL_VG2_2ZC2Z2Z_B", "sel"},
+{"SEL_VG2_2ZC2Z2Z_D", "sel"},
+{"SEL_VG2_2ZC2Z2Z_H", "sel"},
+{"SEL_VG2_2ZC2Z2Z_S", "sel"},
+{"SEL_VG4_4ZC4Z4Z_B", "sel"},
+{"SEL_VG4_4ZC4Z4Z_D", "sel"},
+{"SEL_VG4_4ZC4Z4Z_H", "sel"},
+{"SEL_VG4_4ZC4Z4Z_S", "sel"},
+{"SEL_ZPZZ_B", "sel"},
+{"SEL_ZPZZ_D", "sel"},
+{"SEL_ZPZZ_H", "sel"},
+{"SEL_ZPZZ_S", "sel"},
+{"SETE", "sete"},
+{"SETEN", "seten"},
+{"SETET", "setet"},
+{"SETETN", "setetn"},
+{"SETF8", "setf8"},
+{"SETF16", "setf16"},
+{"SETFFR", "setffr"},
+{"SETGM", "setgm"},
+{"SETGMN", "setgmn"},
+{"SETGMT", "setgmt"},
+{"SETGMTN", "setgmtn"},
+{"SETGOE", "setgoe"},
+{"SETGOEN", "setgoen"},
+{"SETGOET", "setgoet"},
+{"SETGOETN", "setgoetn"},
+{"SETGOM", "setgom"},
+{"SETGOMN", "setgomn"},
+{"SETGOMT", "setgomt"},
+{"SETGOMTN", "setgomtn"},
+{"SETGOP", "setgop"},
+{"SETGOPN", "setgopn"},
+{"SETGOPT", "setgopt"},
+{"SETGOPTN", "setgoptn"},
+{"SETGP", "setgp"},
+{"SETGPN", "setgpn"},
+{"SETGPT", "setgpt"},
+{"SETGPTN", "setgptn"},
+{"SETM", "setm"},
+{"SETMN", "setmn"},
+{"SETMT", "setmt"},
+{"SETMTN", "setmtn"},
+{"SETP", "setp"},
+{"SETPN", "setpn"},
+{"SETPT", "setpt"},
+{"SETPTN", "setptn"},
+{"SHA1Crrr", "sha1c"},
+{"SHA1Hrr", "sha1h"},
+{"SHA1Mrrr", "sha1m"},
+{"SHA1Prrr", "sha1p"},
+{"SHA1SU0rrr", "sha1su0"},
+{"SHA1SU1rr", "sha1su1"},
+{"SHA256H2rrr", "sha256h2"},
+{"SHA256Hrrr", "sha256h"},
+{"SHA256SU0rr", "sha256su0"},
+{"SHA256SU1rrr", "sha256su1"},
+{"SHA512H", "sha512h"},
+{"SHA512H2", "sha512h2"},
+{"SHA512SU0", "sha512su0"},
+{"SHA512SU1", "sha512su1"},
+{"SHADD_ZPmZ_B", "shadd"},
+{"SHADD_ZPmZ_D", "shadd"},
+{"SHADD_ZPmZ_H", "shadd"},
+{"SHADD_ZPmZ_S", "shadd"},
+{"SHADDv2i32", "shadd"},
+{"SHADDv4i16", "shadd"},
+{"SHADDv4i32", "shadd"},
+{"SHADDv8i8", "shadd"},
+{"SHADDv8i16", "shadd"},
+{"SHADDv16i8", "shadd"},
+{"SHLLv2i32", "shll"},
+{"SHLLv4i16", "shll"},
+{"SHLLv8i8", "shll"},
+{"SHLLv4i32", "shll2"},
+{"SHLLv8i16", "shll2"},
+{"SHLLv16i8", "shll2"},
+{"SHLd", "shl"},
+{"SHLv2i32_shift", "shl"},
+{"SHLv2i64_shift", "shl"},
+{"SHLv4i16_shift", "shl"},
+{"SHLv4i32_shift", "shl"},
+{"SHLv8i8_shift", "shl"},
+{"SHLv8i16_shift", "shl"},
+{"SHLv16i8_shift", "shl"},
+{"SHRNB_ZZI_B", "shrnb"},
+{"SHRNB_ZZI_H", "shrnb"},
+{"SHRNB_ZZI_S", "shrnb"},
+{"SHRNT_ZZI_B", "shrnt"},
+{"SHRNT_ZZI_H", "shrnt"},
+{"SHRNT_ZZI_S", "shrnt"},
+{"SHRNv2i32_shift", "shrn"},
+{"SHRNv4i16_shift", "shrn"},
+{"SHRNv8i8_shift", "shrn"},
+{"SHRNv4i32_shift", "shrn2"},
+{"SHRNv8i16_shift", "shrn2"},
+{"SHRNv16i8_shift", "shrn2"},
+{"SHSUBR_ZPmZ_B", "shsubr"},
+{"SHSUBR_ZPmZ_D", "shsubr"},
+{"SHSUBR_ZPmZ_H", "shsubr"},
+{"SHSUBR_ZPmZ_S", "shsubr"},
+{"SHSUB_ZPmZ_B", "shsub"},
+{"SHSUB_ZPmZ_D", "shsub"},
+{"SHSUB_ZPmZ_H", "shsub"},
+{"SHSUB_ZPmZ_S", "shsub"},
+{"SHSUBv2i32", "shsub"},
+{"SHSUBv4i16", "shsub"},
+{"SHSUBv4i32", "shsub"},
+{"SHSUBv8i8", "shsub"},
+{"SHSUBv8i16", "shsub"},
+{"SHSUBv16i8", "shsub"},
+{"SLI_ZZI_B", "sli"},
+{"SLI_ZZI_D", "sli"},
+{"SLI_ZZI_H", "sli"},
+{"SLI_ZZI_S", "sli"},
+{"SLId", "sli"},
+{"SLIv2i32_shift", "sli"},
+{"SLIv2i64_shift", "sli"},
+{"SLIv4i16_shift", "sli"},
+{"SLIv4i32_shift", "sli"},
+{"SLIv8i8_shift", "sli"},
+{"SLIv8i16_shift", "sli"},
+{"SLIv16i8_shift", "sli"},
+{"SM3PARTW1", "sm3partw1"},
+{"SM3PARTW2", "sm3partw2"},
+{"SM3SS1", "sm3ss1"},
+{"SM3TT1A", "sm3tt1a"},
+{"SM3TT1B", "sm3tt1b"},
+{"SM3TT2A", "sm3tt2a"},
+{"SM3TT2B", "sm3tt2b"},
+{"SM4E", "sm4e"},
+{"SM4E_ZZZ_S", "sm4e"},
+{"SM4EKEY_ZZZ_S", "sm4ekey"},
+{"SM4ENCKEY", "sm4ekey"},
+{"SMADDLrrr", "smaddl"},
+{"SMAXP_ZPmZ_B", "smaxp"},
+{"SMAXP_ZPmZ_D", "smaxp"},
+{"SMAXP_ZPmZ_H", "smaxp"},
+{"SMAXP_ZPmZ_S", "smaxp"},
+{"SMAXPv2i32", "smaxp"},
+{"SMAXPv4i16", "smaxp"},
+{"SMAXPv4i32", "smaxp"},
+{"SMAXPv8i8", "smaxp"},
+{"SMAXPv8i16", "smaxp"},
+{"SMAXPv16i8", "smaxp"},
+{"SMAXQV_VPZ_B", "smaxqv"},
+{"SMAXQV_VPZ_D", "smaxqv"},
+{"SMAXQV_VPZ_H", "smaxqv"},
+{"SMAXQV_VPZ_S", "smaxqv"},
+{"SMAXV_VPZ_B", "smaxv"},
+{"SMAXV_VPZ_D", "smaxv"},
+{"SMAXV_VPZ_H", "smaxv"},
+{"SMAXV_VPZ_S", "smaxv"},
+{"SMAXVv4i16v", "smaxv"},
+{"SMAXVv4i32v", "smaxv"},
+{"SMAXVv8i8v", "smaxv"},
+{"SMAXVv8i16v", "smaxv"},
+{"SMAXVv16i8v", "smaxv"},
+{"SMAXWri", "smax"},
+{"SMAXWrr", "smax"},
+{"SMAXXri", "smax"},
+{"SMAXXrr", "smax"},
+{"SMAX_VG2_2Z2Z_B", "smax"},
+{"SMAX_VG2_2Z2Z_D", "smax"},
+{"SMAX_VG2_2Z2Z_H", "smax"},
+{"SMAX_VG2_2Z2Z_S", "smax"},
+{"SMAX_VG2_2ZZ_B", "smax"},
+{"SMAX_VG2_2ZZ_D", "smax"},
+{"SMAX_VG2_2ZZ_H", "smax"},
+{"SMAX_VG2_2ZZ_S", "smax"},
+{"SMAX_VG4_4Z4Z_B", "smax"},
+{"SMAX_VG4_4Z4Z_D", "smax"},
+{"SMAX_VG4_4Z4Z_H", "smax"},
+{"SMAX_VG4_4Z4Z_S", "smax"},
+{"SMAX_VG4_4ZZ_B", "smax"},
+{"SMAX_VG4_4ZZ_D", "smax"},
+{"SMAX_VG4_4ZZ_H", "smax"},
+{"SMAX_VG4_4ZZ_S", "smax"},
+{"SMAX_ZI_B", "smax"},
+{"SMAX_ZI_D", "smax"},
+{"SMAX_ZI_H", "smax"},
+{"SMAX_ZI_S", "smax"},
+{"SMAX_ZPmZ_B", "smax"},
+{"SMAX_ZPmZ_D", "smax"},
+{"SMAX_ZPmZ_H", "smax"},
+{"SMAX_ZPmZ_S", "smax"},
+{"SMAXv2i32", "smax"},
+{"SMAXv4i16", "smax"},
+{"SMAXv4i32", "smax"},
+{"SMAXv8i8", "smax"},
+{"SMAXv8i16", "smax"},
+{"SMAXv16i8", "smax"},
+{"SMC", "smc"},
+{"SMINP_ZPmZ_B", "sminp"},
+{"SMINP_ZPmZ_D", "sminp"},
+{"SMINP_ZPmZ_H", "sminp"},
+{"SMINP_ZPmZ_S", "sminp"},
+{"SMINPv2i32", "sminp"},
+{"SMINPv4i16", "sminp"},
+{"SMINPv4i32", "sminp"},
+{"SMINPv8i8", "sminp"},
+{"SMINPv8i16", "sminp"},
+{"SMINPv16i8", "sminp"},
+{"SMINQV_VPZ_B", "sminqv"},
+{"SMINQV_VPZ_D", "sminqv"},
+{"SMINQV_VPZ_H", "sminqv"},
+{"SMINQV_VPZ_S", "sminqv"},
+{"SMINV_VPZ_B", "sminv"},
+{"SMINV_VPZ_D", "sminv"},
+{"SMINV_VPZ_H", "sminv"},
+{"SMINV_VPZ_S", "sminv"},
+{"SMINVv4i16v", "sminv"},
+{"SMINVv4i32v", "sminv"},
+{"SMINVv8i8v", "sminv"},
+{"SMINVv8i16v", "sminv"},
+{"SMINVv16i8v", "sminv"},
+{"SMINWri", "smin"},
+{"SMINWrr", "smin"},
+{"SMINXri", "smin"},
+{"SMINXrr", "smin"},
+{"SMIN_VG2_2Z2Z_B", "smin"},
+{"SMIN_VG2_2Z2Z_D", "smin"},
+{"SMIN_VG2_2Z2Z_H", "smin"},
+{"SMIN_VG2_2Z2Z_S", "smin"},
+{"SMIN_VG2_2ZZ_B", "smin"},
+{"SMIN_VG2_2ZZ_D", "smin"},
+{"SMIN_VG2_2ZZ_H", "smin"},
+{"SMIN_VG2_2ZZ_S", "smin"},
+{"SMIN_VG4_4Z4Z_B", "smin"},
+{"SMIN_VG4_4Z4Z_D", "smin"},
+{"SMIN_VG4_4Z4Z_H", "smin"},
+{"SMIN_VG4_4Z4Z_S", "smin"},
+{"SMIN_VG4_4ZZ_B", "smin"},
+{"SMIN_VG4_4ZZ_D", "smin"},
+{"SMIN_VG4_4ZZ_H", "smin"},
+{"SMIN_VG4_4ZZ_S", "smin"},
+{"SMIN_ZI_B", "smin"},
+{"SMIN_ZI_D", "smin"},
+{"SMIN_ZI_H", "smin"},
+{"SMIN_ZI_S", "smin"},
+{"SMIN_ZPmZ_B", "smin"},
+{"SMIN_ZPmZ_D", "smin"},
+{"SMIN_ZPmZ_H", "smin"},
+{"SMIN_ZPmZ_S", "smin"},
+{"SMINv2i32", "smin"},
+{"SMINv4i16", "smin"},
+{"SMINv4i32", "smin"},
+{"SMINv8i8", "smin"},
+{"SMINv8i16", "smin"},
+{"SMINv16i8", "smin"},
+{"SMLALB_ZZZI_D", "smlalb"},
+{"SMLALB_ZZZI_S", "smlalb"},
+{"SMLALB_ZZZ_D", "smlalb"},
+{"SMLALB_ZZZ_H", "smlalb"},
+{"SMLALB_ZZZ_S", "smlalb"},
+{"SMLALL_MZZI_BtoS", "smlall"},
+{"SMLALL_MZZI_HtoD", "smlall"},
+{"SMLALL_MZZ_BtoS", "smlall"},
+{"SMLALL_MZZ_HtoD", "smlall"},
+{"SMLALL_VG2_M2Z2Z_BtoS", "smlall"},
+{"SMLALL_VG2_M2Z2Z_HtoD", "smlall"},
+{"SMLALL_VG2_M2ZZI_BtoS", "smlall"},
+{"SMLALL_VG2_M2ZZI_HtoD", "smlall"},
+{"SMLALL_VG2_M2ZZ_BtoS", "smlall"},
+{"SMLALL_VG2_M2ZZ_HtoD", "smlall"},
+{"SMLALL_VG4_M4Z4Z_BtoS", "smlall"},
+{"SMLALL_VG4_M4Z4Z_HtoD", "smlall"},
+{"SMLALL_VG4_M4ZZI_BtoS", "smlall"},
+{"SMLALL_VG4_M4ZZI_HtoD", "smlall"},
+{"SMLALL_VG4_M4ZZ_BtoS", "smlall"},
+{"SMLALL_VG4_M4ZZ_HtoD", "smlall"},
+{"SMLALT_ZZZI_D", "smlalt"},
+{"SMLALT_ZZZI_S", "smlalt"},
+{"SMLALT_ZZZ_D", "smlalt"},
+{"SMLALT_ZZZ_H", "smlalt"},
+{"SMLALT_ZZZ_S", "smlalt"},
+{"SMLAL_MZZI_HtoS", "smlal"},
+{"SMLAL_MZZ_HtoS", "smlal"},
+{"SMLAL_VG2_M2Z2Z_HtoS", "smlal"},
+{"SMLAL_VG2_M2ZZI_S", "smlal"},
+{"SMLAL_VG2_M2ZZ_HtoS", "smlal"},
+{"SMLAL_VG4_M4Z4Z_HtoS", "smlal"},
+{"SMLAL_VG4_M4ZZI_HtoS", "smlal"},
+{"SMLAL_VG4_M4ZZ_HtoS", "smlal"},
+{"SMLALv2i32_indexed", "smlal"},
+{"SMLALv2i32_v2i64", "smlal"},
+{"SMLALv4i16_indexed", "smlal"},
+{"SMLALv4i16_v4i32", "smlal"},
+{"SMLALv8i8_v8i16", "smlal"},
+{"SMLALv4i32_indexed", "smlal2"},
+{"SMLALv4i32_v2i64", "smlal2"},
+{"SMLALv8i16_indexed", "smlal2"},
+{"SMLALv8i16_v4i32", "smlal2"},
+{"SMLALv16i8_v8i16", "smlal2"},
+{"SMLSLB_ZZZI_D", "smlslb"},
+{"SMLSLB_ZZZI_S", "smlslb"},
+{"SMLSLB_ZZZ_D", "smlslb"},
+{"SMLSLB_ZZZ_H", "smlslb"},
+{"SMLSLB_ZZZ_S", "smlslb"},
+{"SMLSLL_MZZI_BtoS", "smlsll"},
+{"SMLSLL_MZZI_HtoD", "smlsll"},
+{"SMLSLL_MZZ_BtoS", "smlsll"},
+{"SMLSLL_MZZ_HtoD", "smlsll"},
+{"SMLSLL_VG2_M2Z2Z_BtoS", "smlsll"},
+{"SMLSLL_VG2_M2Z2Z_HtoD", "smlsll"},
+{"SMLSLL_VG2_M2ZZI_BtoS", "smlsll"},
+{"SMLSLL_VG2_M2ZZI_HtoD", "smlsll"},
+{"SMLSLL_VG2_M2ZZ_BtoS", "smlsll"},
+{"SMLSLL_VG2_M2ZZ_HtoD", "smlsll"},
+{"SMLSLL_VG4_M4Z4Z_BtoS", "smlsll"},
+{"SMLSLL_VG4_M4Z4Z_HtoD", "smlsll"},
+{"SMLSLL_VG4_M4ZZI_BtoS", "smlsll"},
+{"SMLSLL_VG4_M4ZZI_HtoD", "smlsll"},
+{"SMLSLL_VG4_M4ZZ_BtoS", "smlsll"},
+{"SMLSLL_VG4_M4ZZ_HtoD", "smlsll"},
+{"SMLSLT_ZZZI_D", "smlslt"},
+{"SMLSLT_ZZZI_S", "smlslt"},
+{"SMLSLT_ZZZ_D", "smlslt"},
+{"SMLSLT_ZZZ_H", "smlslt"},
+{"SMLSLT_ZZZ_S", "smlslt"},
+{"SMLSL_MZZI_HtoS", "smlsl"},
+{"SMLSL_MZZ_HtoS", "smlsl"},
+{"SMLSL_VG2_M2Z2Z_HtoS", "smlsl"},
+{"SMLSL_VG2_M2ZZI_S", "smlsl"},
+{"SMLSL_VG2_M2ZZ_HtoS", "smlsl"},
+{"SMLSL_VG4_M4Z4Z_HtoS", "smlsl"},
+{"SMLSL_VG4_M4ZZI_HtoS", "smlsl"},
+{"SMLSL_VG4_M4ZZ_HtoS", "smlsl"},
+{"SMLSLv2i32_indexed", "smlsl"},
+{"SMLSLv2i32_v2i64", "smlsl"},
+{"SMLSLv4i16_indexed", "smlsl"},
+{"SMLSLv4i16_v4i32", "smlsl"},
+{"SMLSLv8i8_v8i16", "smlsl"},
+{"SMLSLv4i32_indexed", "smlsl2"},
+{"SMLSLv4i32_v2i64", "smlsl2"},
+{"SMLSLv8i16_indexed", "smlsl2"},
+{"SMLSLv8i16_v4i32", "smlsl2"},
+{"SMLSLv16i8_v8i16", "smlsl2"},
+{"SMMLA", "smmla"},
+{"SMMLA_ZZZ", "smmla"},
+{"SMOP4A_M2Z2Z_BToS", "smop4a"},
+{"SMOP4A_M2Z2Z_HToS", "smop4a"},
+{"SMOP4A_M2Z2Z_HtoD", "smop4a"},
+{"SMOP4A_M2ZZ_BToS", "smop4a"},
+{"SMOP4A_M2ZZ_HToS", "smop4a"},
+{"SMOP4A_M2ZZ_HtoD", "smop4a"},
+{"SMOP4A_MZ2Z_BToS", "smop4a"},
+{"SMOP4A_MZ2Z_HToS", "smop4a"},
+{"SMOP4A_MZ2Z_HtoD", "smop4a"},
+{"SMOP4A_MZZ_BToS", "smop4a"},
+{"SMOP4A_MZZ_HToS", "smop4a"},
+{"SMOP4A_MZZ_HtoD", "smop4a"},
+{"SMOP4S_M2Z2Z_BToS", "smop4s"},
+{"SMOP4S_M2Z2Z_HToS", "smop4s"},
+{"SMOP4S_M2Z2Z_HtoD", "smop4s"},
+{"SMOP4S_M2ZZ_BToS", "smop4s"},
+{"SMOP4S_M2ZZ_HToS", "smop4s"},
+{"SMOP4S_M2ZZ_HtoD", "smop4s"},
+{"SMOP4S_MZ2Z_BToS", "smop4s"},
+{"SMOP4S_MZ2Z_HToS", "smop4s"},
+{"SMOP4S_MZ2Z_HtoD", "smop4s"},
+{"SMOP4S_MZZ_BToS", "smop4s"},
+{"SMOP4S_MZZ_HToS", "smop4s"},
+{"SMOP4S_MZZ_HtoD", "smop4s"},
+{"SMOPA_MPPZZ_D", "smopa"},
+{"SMOPA_MPPZZ_HtoS", "smopa"},
+{"SMOPA_MPPZZ_S", "smopa"},
+{"SMOPS_MPPZZ_D", "smops"},
+{"SMOPS_MPPZZ_HtoS", "smops"},
+{"SMOPS_MPPZZ_S", "smops"},
+{"SMOVvi8to32", "smov"},
+{"SMOVvi8to32_idx0", "smov"},
+{"SMOVvi8to64", "smov"},
+{"SMOVvi8to64_idx0", "smov"},
+{"SMOVvi16to32", "smov"},
+{"SMOVvi16to32_idx0", "smov"},
+{"SMOVvi16to64", "smov"},
+{"SMOVvi16to64_idx0", "smov"},
+{"SMOVvi32to64", "smov"},
+{"SMOVvi32to64_idx0", "smov"},
+{"SMSUBLrrr", "smsubl"},
+{"SMULH_ZPmZ_B", "smulh"},
+{"SMULH_ZPmZ_D", "smulh"},
+{"SMULH_ZPmZ_H", "smulh"},
+{"SMULH_ZPmZ_S", "smulh"},
+{"SMULH_ZZZ_B", "smulh"},
+{"SMULH_ZZZ_D", "smulh"},
+{"SMULH_ZZZ_H", "smulh"},
+{"SMULH_ZZZ_S", "smulh"},
+{"SMULHrr", "smulh"},
+{"SMULLB_ZZZI_D", "smullb"},
+{"SMULLB_ZZZI_S", "smullb"},
+{"SMULLB_ZZZ_D", "smullb"},
+{"SMULLB_ZZZ_H", "smullb"},
+{"SMULLB_ZZZ_S", "smullb"},
+{"SMULLT_ZZZI_D", "smullt"},
+{"SMULLT_ZZZI_S", "smullt"},
+{"SMULLT_ZZZ_D", "smullt"},
+{"SMULLT_ZZZ_H", "smullt"},
+{"SMULLT_ZZZ_S", "smullt"},
+{"SMULLv2i32_indexed", "smull"},
+{"SMULLv2i32_v2i64", "smull"},
+{"SMULLv4i16_indexed", "smull"},
+{"SMULLv4i16_v4i32", "smull"},
+{"SMULLv8i8_v8i16", "smull"},
+{"SMULLv4i32_indexed", "smull2"},
+{"SMULLv4i32_v2i64", "smull2"},
+{"SMULLv8i16_indexed", "smull2"},
+{"SMULLv8i16_v4i32", "smull2"},
+{"SMULLv16i8_v8i16", "smull2"},
+{"SPLICE_ZPZZ_B", "splice"},
+{"SPLICE_ZPZZ_D", "splice"},
+{"SPLICE_ZPZZ_H", "splice"},
+{"SPLICE_ZPZZ_S", "splice"},
+{"SPLICE_ZPZ_B", "splice"},
+{"SPLICE_ZPZ_D", "splice"},
+{"SPLICE_ZPZ_H", "splice"},
+{"SPLICE_ZPZ_S", "splice"},
+{"SQABS_ZPmZ_B", "sqabs"},
+{"SQABS_ZPmZ_D", "sqabs"},
+{"SQABS_ZPmZ_H", "sqabs"},
+{"SQABS_ZPmZ_S", "sqabs"},
+{"SQABS_ZPzZ_B", "sqabs"},
+{"SQABS_ZPzZ_D", "sqabs"},
+{"SQABS_ZPzZ_H", "sqabs"},
+{"SQABS_ZPzZ_S", "sqabs"},
+{"SQABSv1i8", "sqabs"},
+{"SQABSv1i16", "sqabs"},
+{"SQABSv1i32", "sqabs"},
+{"SQABSv1i64", "sqabs"},
+{"SQABSv2i32", "sqabs"},
+{"SQABSv2i64", "sqabs"},
+{"SQABSv4i16", "sqabs"},
+{"SQABSv4i32", "sqabs"},
+{"SQABSv8i8", "sqabs"},
+{"SQABSv8i16", "sqabs"},
+{"SQABSv16i8", "sqabs"},
+{"SQADD_ZI_B", "sqadd"},
+{"SQADD_ZI_D", "sqadd"},
+{"SQADD_ZI_H", "sqadd"},
+{"SQADD_ZI_S", "sqadd"},
+{"SQADD_ZPmZ_B", "sqadd"},
+{"SQADD_ZPmZ_D", "sqadd"},
+{"SQADD_ZPmZ_H", "sqadd"},
+{"SQADD_ZPmZ_S", "sqadd"},
+{"SQADD_ZZZ_B", "sqadd"},
+{"SQADD_ZZZ_D", "sqadd"},
+{"SQADD_ZZZ_H", "sqadd"},
+{"SQADD_ZZZ_S", "sqadd"},
+{"SQADDv1i8", "sqadd"},
+{"SQADDv1i16", "sqadd"},
+{"SQADDv1i32", "sqadd"},
+{"SQADDv1i64", "sqadd"},
+{"SQADDv2i32", "sqadd"},
+{"SQADDv2i64", "sqadd"},
+{"SQADDv4i16", "sqadd"},
+{"SQADDv4i32", "sqadd"},
+{"SQADDv8i8", "sqadd"},
+{"SQADDv8i16", "sqadd"},
+{"SQADDv16i8", "sqadd"},
+{"SQCADD_ZZI_B", "sqcadd"},
+{"SQCADD_ZZI_D", "sqcadd"},
+{"SQCADD_ZZI_H", "sqcadd"},
+{"SQCADD_ZZI_S", "sqcadd"},
+{"SQCVTN_Z2Z_StoH", "sqcvtn"},
+{"SQCVTN_Z4Z_DtoH", "sqcvtn"},
+{"SQCVTN_Z4Z_StoB", "sqcvtn"},
+{"SQCVTUN_Z2Z_StoH", "sqcvtun"},
+{"SQCVTUN_Z4Z_DtoH", "sqcvtun"},
+{"SQCVTUN_Z4Z_StoB", "sqcvtun"},
+{"SQCVTU_Z2Z_StoH", "sqcvtu"},
+{"SQCVTU_Z4Z_DtoH", "sqcvtu"},
+{"SQCVTU_Z4Z_StoB", "sqcvtu"},
+{"SQCVT_Z2Z_StoH", "sqcvt"},
+{"SQCVT_Z4Z_DtoH", "sqcvt"},
+{"SQCVT_Z4Z_StoB", "sqcvt"},
+{"SQDECB_XPiI", "sqdecb"},
+{"SQDECB_XPiWdI", "sqdecb"},
+{"SQDECD_XPiI", "sqdecd"},
+{"SQDECD_XPiWdI", "sqdecd"},
+{"SQDECD_ZPiI", "sqdecd"},
+{"SQDECH_XPiI", "sqdech"},
+{"SQDECH_XPiWdI", "sqdech"},
+{"SQDECH_ZPiI", "sqdech"},
+{"SQDECP_XPWd_B", "sqdecp"},
+{"SQDECP_XPWd_D", "sqdecp"},
+{"SQDECP_XPWd_H", "sqdecp"},
+{"SQDECP_XPWd_S", "sqdecp"},
+{"SQDECP_XP_B", "sqdecp"},
+{"SQDECP_XP_D", "sqdecp"},
+{"SQDECP_XP_H", "sqdecp"},
+{"SQDECP_XP_S", "sqdecp"},
+{"SQDECP_ZP_D", "sqdecp"},
+{"SQDECP_ZP_H", "sqdecp"},
+{"SQDECP_ZP_S", "sqdecp"},
+{"SQDECW_XPiI", "sqdecw"},
+{"SQDECW_XPiWdI", "sqdecw"},
+{"SQDECW_ZPiI", "sqdecw"},
+{"SQDMLALBT_ZZZ_D", "sqdmlalbt"},
+{"SQDMLALBT_ZZZ_H", "sqdmlalbt"},
+{"SQDMLALBT_ZZZ_S", "sqdmlalbt"},
+{"SQDMLALB_ZZZI_D", "sqdmlalb"},
+{"SQDMLALB_ZZZI_S", "sqdmlalb"},
+{"SQDMLALB_ZZZ_D", "sqdmlalb"},
+{"SQDMLALB_ZZZ_H", "sqdmlalb"},
+{"SQDMLALB_ZZZ_S", "sqdmlalb"},
+{"SQDMLALT_ZZZI_D", "sqdmlalt"},
+{"SQDMLALT_ZZZI_S", "sqdmlalt"},
+{"SQDMLALT_ZZZ_D", "sqdmlalt"},
+{"SQDMLALT_ZZZ_H", "sqdmlalt"},
+{"SQDMLALT_ZZZ_S", "sqdmlalt"},
+{"SQDMLALi16", "sqdmlal"},
+{"SQDMLALi32", "sqdmlal"},
+{"SQDMLALv1i32_indexed", "sqdmlal"},
+{"SQDMLALv1i64_indexed", "sqdmlal"},
+{"SQDMLALv2i32_indexed", "sqdmlal"},
+{"SQDMLALv2i32_v2i64", "sqdmlal"},
+{"SQDMLALv4i16_indexed", "sqdmlal"},
+{"SQDMLALv4i16_v4i32", "sqdmlal"},
+{"SQDMLALv4i32_indexed", "sqdmlal2"},
+{"SQDMLALv4i32_v2i64", "sqdmlal2"},
+{"SQDMLALv8i16_indexed", "sqdmlal2"},
+{"SQDMLALv8i16_v4i32", "sqdmlal2"},
+{"SQDMLSLBT_ZZZ_D", "sqdmlslbt"},
+{"SQDMLSLBT_ZZZ_H", "sqdmlslbt"},
+{"SQDMLSLBT_ZZZ_S", "sqdmlslbt"},
+{"SQDMLSLB_ZZZI_D", "sqdmlslb"},
+{"SQDMLSLB_ZZZI_S", "sqdmlslb"},
+{"SQDMLSLB_ZZZ_D", "sqdmlslb"},
+{"SQDMLSLB_ZZZ_H", "sqdmlslb"},
+{"SQDMLSLB_ZZZ_S", "sqdmlslb"},
+{"SQDMLSLT_ZZZI_D", "sqdmlslt"},
+{"SQDMLSLT_ZZZI_S", "sqdmlslt"},
+{"SQDMLSLT_ZZZ_D", "sqdmlslt"},
+{"SQDMLSLT_ZZZ_H", "sqdmlslt"},
+{"SQDMLSLT_ZZZ_S", "sqdmlslt"},
+{"SQDMLSLi16", "sqdmlsl"},
+{"SQDMLSLi32", "sqdmlsl"},
+{"SQDMLSLv1i32_indexed", "sqdmlsl"},
+{"SQDMLSLv1i64_indexed", "sqdmlsl"},
+{"SQDMLSLv2i32_indexed", "sqdmlsl"},
+{"SQDMLSLv2i32_v2i64", "sqdmlsl"},
+{"SQDMLSLv4i16_indexed", "sqdmlsl"},
+{"SQDMLSLv4i16_v4i32", "sqdmlsl"},
+{"SQDMLSLv4i32_indexed", "sqdmlsl2"},
+{"SQDMLSLv4i32_v2i64", "sqdmlsl2"},
+{"SQDMLSLv8i16_indexed", "sqdmlsl2"},
+{"SQDMLSLv8i16_v4i32", "sqdmlsl2"},
+{"SQDMULH_VG2_2Z2Z_B", "sqdmulh"},
+{"SQDMULH_VG2_2Z2Z_D", "sqdmulh"},
+{"SQDMULH_VG2_2Z2Z_H", "sqdmulh"},
+{"SQDMULH_VG2_2Z2Z_S", "sqdmulh"},
+{"SQDMULH_VG2_2ZZ_B", "sqdmulh"},
+{"SQDMULH_VG2_2ZZ_D", "sqdmulh"},
+{"SQDMULH_VG2_2ZZ_H", "sqdmulh"},
+{"SQDMULH_VG2_2ZZ_S", "sqdmulh"},
+{"SQDMULH_VG4_4Z4Z_B", "sqdmulh"},
+{"SQDMULH_VG4_4Z4Z_D", "sqdmulh"},
+{"SQDMULH_VG4_4Z4Z_H", "sqdmulh"},
+{"SQDMULH_VG4_4Z4Z_S", "sqdmulh"},
+{"SQDMULH_VG4_4ZZ_B", "sqdmulh"},
+{"SQDMULH_VG4_4ZZ_D", "sqdmulh"},
+{"SQDMULH_VG4_4ZZ_H", "sqdmulh"},
+{"SQDMULH_VG4_4ZZ_S", "sqdmulh"},
+{"SQDMULH_ZZZI_D", "sqdmulh"},
+{"SQDMULH_ZZZI_H", "sqdmulh"},
+{"SQDMULH_ZZZI_S", "sqdmulh"},
+{"SQDMULH_ZZZ_B", "sqdmulh"},
+{"SQDMULH_ZZZ_D", "sqdmulh"},
+{"SQDMULH_ZZZ_H", "sqdmulh"},
+{"SQDMULH_ZZZ_S", "sqdmulh"},
+{"SQDMULHv1i16", "sqdmulh"},
+{"SQDMULHv1i16_indexed", "sqdmulh"},
+{"SQDMULHv1i32", "sqdmulh"},
+{"SQDMULHv1i32_indexed", "sqdmulh"},
+{"SQDMULHv2i32", "sqdmulh"},
+{"SQDMULHv2i32_indexed", "sqdmulh"},
+{"SQDMULHv4i16", "sqdmulh"},
+{"SQDMULHv4i16_indexed", "sqdmulh"},
+{"SQDMULHv4i32", "sqdmulh"},
+{"SQDMULHv4i32_indexed", "sqdmulh"},
+{"SQDMULHv8i16", "sqdmulh"},
+{"SQDMULHv8i16_indexed", "sqdmulh"},
+{"SQDMULLB_ZZZI_D", "sqdmullb"},
+{"SQDMULLB_ZZZI_S", "sqdmullb"},
+{"SQDMULLB_ZZZ_D", "sqdmullb"},
+{"SQDMULLB_ZZZ_H", "sqdmullb"},
+{"SQDMULLB_ZZZ_S", "sqdmullb"},
+{"SQDMULLT_ZZZI_D", "sqdmullt"},
+{"SQDMULLT_ZZZI_S", "sqdmullt"},
+{"SQDMULLT_ZZZ_D", "sqdmullt"},
+{"SQDMULLT_ZZZ_H", "sqdmullt"},
+{"SQDMULLT_ZZZ_S", "sqdmullt"},
+{"SQDMULLi16", "sqdmull"},
+{"SQDMULLi32", "sqdmull"},
+{"SQDMULLv1i32_indexed", "sqdmull"},
+{"SQDMULLv1i64_indexed", "sqdmull"},
+{"SQDMULLv2i32_indexed", "sqdmull"},
+{"SQDMULLv2i32_v2i64", "sqdmull"},
+{"SQDMULLv4i16_indexed", "sqdmull"},
+{"SQDMULLv4i16_v4i32", "sqdmull"},
+{"SQDMULLv4i32_indexed", "sqdmull2"},
+{"SQDMULLv4i32_v2i64", "sqdmull2"},
+{"SQDMULLv8i16_indexed", "sqdmull2"},
+{"SQDMULLv8i16_v4i32", "sqdmull2"},
+{"SQINCB_XPiI", "sqincb"},
+{"SQINCB_XPiWdI", "sqincb"},
+{"SQINCD_XPiI", "sqincd"},
+{"SQINCD_XPiWdI", "sqincd"},
+{"SQINCD_ZPiI", "sqincd"},
+{"SQINCH_XPiI", "sqinch"},
+{"SQINCH_XPiWdI", "sqinch"},
+{"SQINCH_ZPiI", "sqinch"},
+{"SQINCP_XPWd_B", "sqincp"},
+{"SQINCP_XPWd_D", "sqincp"},
+{"SQINCP_XPWd_H", "sqincp"},
+{"SQINCP_XPWd_S", "sqincp"},
+{"SQINCP_XP_B", "sqincp"},
+{"SQINCP_XP_D", "sqincp"},
+{"SQINCP_XP_H", "sqincp"},
+{"SQINCP_XP_S", "sqincp"},
+{"SQINCP_ZP_D", "sqincp"},
+{"SQINCP_ZP_H", "sqincp"},
+{"SQINCP_ZP_S", "sqincp"},
+{"SQINCW_XPiI", "sqincw"},
+{"SQINCW_XPiWdI", "sqincw"},
+{"SQINCW_ZPiI", "sqincw"},
+{"SQNEG_ZPmZ_B", "sqneg"},
+{"SQNEG_ZPmZ_D", "sqneg"},
+{"SQNEG_ZPmZ_H", "sqneg"},
+{"SQNEG_ZPmZ_S", "sqneg"},
+{"SQNEG_ZPzZ_B", "sqneg"},
+{"SQNEG_ZPzZ_D", "sqneg"},
+{"SQNEG_ZPzZ_H", "sqneg"},
+{"SQNEG_ZPzZ_S", "sqneg"},
+{"SQNEGv1i8", "sqneg"},
+{"SQNEGv1i16", "sqneg"},
+{"SQNEGv1i32", "sqneg"},
+{"SQNEGv1i64", "sqneg"},
+{"SQNEGv2i32", "sqneg"},
+{"SQNEGv2i64", "sqneg"},
+{"SQNEGv4i16", "sqneg"},
+{"SQNEGv4i32", "sqneg"},
+{"SQNEGv8i8", "sqneg"},
+{"SQNEGv8i16", "sqneg"},
+{"SQNEGv16i8", "sqneg"},
+{"SQRDCMLAH_ZZZI_H", "sqrdcmlah"},
+{"SQRDCMLAH_ZZZI_S", "sqrdcmlah"},
+{"SQRDCMLAH_ZZZ_B", "sqrdcmlah"},
+{"SQRDCMLAH_ZZZ_D", "sqrdcmlah"},
+{"SQRDCMLAH_ZZZ_H", "sqrdcmlah"},
+{"SQRDCMLAH_ZZZ_S", "sqrdcmlah"},
+{"SQRDMLAH_ZZZI_D", "sqrdmlah"},
+{"SQRDMLAH_ZZZI_H", "sqrdmlah"},
+{"SQRDMLAH_ZZZI_S", "sqrdmlah"},
+{"SQRDMLAH_ZZZ_B", "sqrdmlah"},
+{"SQRDMLAH_ZZZ_D", "sqrdmlah"},
+{"SQRDMLAH_ZZZ_H", "sqrdmlah"},
+{"SQRDMLAH_ZZZ_S", "sqrdmlah"},
+{"SQRDMLAHv1i16", "sqrdmlah"},
+{"SQRDMLAHv1i16_indexed", "sqrdmlah"},
+{"SQRDMLAHv1i32", "sqrdmlah"},
+{"SQRDMLAHv1i32_indexed", "sqrdmlah"},
+{"SQRDMLAHv2i32", "sqrdmlah"},
+{"SQRDMLAHv2i32_indexed", "sqrdmlah"},
+{"SQRDMLAHv4i16", "sqrdmlah"},
+{"SQRDMLAHv4i16_indexed", "sqrdmlah"},
+{"SQRDMLAHv4i32", "sqrdmlah"},
+{"SQRDMLAHv4i32_indexed", "sqrdmlah"},
+{"SQRDMLAHv8i16", "sqrdmlah"},
+{"SQRDMLAHv8i16_indexed", "sqrdmlah"},
+{"SQRDMLSH_ZZZI_D", "sqrdmlsh"},
+{"SQRDMLSH_ZZZI_H", "sqrdmlsh"},
+{"SQRDMLSH_ZZZI_S", "sqrdmlsh"},
+{"SQRDMLSH_ZZZ_B", "sqrdmlsh"},
+{"SQRDMLSH_ZZZ_D", "sqrdmlsh"},
+{"SQRDMLSH_ZZZ_H", "sqrdmlsh"},
+{"SQRDMLSH_ZZZ_S", "sqrdmlsh"},
+{"SQRDMLSHv1i16", "sqrdmlsh"},
+{"SQRDMLSHv1i16_indexed", "sqrdmlsh"},
+{"SQRDMLSHv1i32", "sqrdmlsh"},
+{"SQRDMLSHv1i32_indexed", "sqrdmlsh"},
+{"SQRDMLSHv2i32", "sqrdmlsh"},
+{"SQRDMLSHv2i32_indexed", "sqrdmlsh"},
+{"SQRDMLSHv4i16", "sqrdmlsh"},
+{"SQRDMLSHv4i16_indexed", "sqrdmlsh"},
+{"SQRDMLSHv4i32", "sqrdmlsh"},
+{"SQRDMLSHv4i32_indexed", "sqrdmlsh"},
+{"SQRDMLSHv8i16", "sqrdmlsh"},
+{"SQRDMLSHv8i16_indexed", "sqrdmlsh"},
+{"SQRDMULH_ZZZI_D", "sqrdmulh"},
+{"SQRDMULH_ZZZI_H", "sqrdmulh"},
+{"SQRDMULH_ZZZI_S", "sqrdmulh"},
+{"SQRDMULH_ZZZ_B", "sqrdmulh"},
+{"SQRDMULH_ZZZ_D", "sqrdmulh"},
+{"SQRDMULH_ZZZ_H", "sqrdmulh"},
+{"SQRDMULH_ZZZ_S", "sqrdmulh"},
+{"SQRDMULHv1i16", "sqrdmulh"},
+{"SQRDMULHv1i16_indexed", "sqrdmulh"},
+{"SQRDMULHv1i32", "sqrdmulh"},
+{"SQRDMULHv1i32_indexed", "sqrdmulh"},
+{"SQRDMULHv2i32", "sqrdmulh"},
+{"SQRDMULHv2i32_indexed", "sqrdmulh"},
+{"SQRDMULHv4i16", "sqrdmulh"},
+{"SQRDMULHv4i16_indexed", "sqrdmulh"},
+{"SQRDMULHv4i32", "sqrdmulh"},
+{"SQRDMULHv4i32_indexed", "sqrdmulh"},
+{"SQRDMULHv8i16", "sqrdmulh"},
+{"SQRDMULHv8i16_indexed", "sqrdmulh"},
+{"SQRSHLR_ZPmZ_B", "sqrshlr"},
+{"SQRSHLR_ZPmZ_D", "sqrshlr"},
+{"SQRSHLR_ZPmZ_H", "sqrshlr"},
+{"SQRSHLR_ZPmZ_S", "sqrshlr"},
+{"SQRSHL_ZPmZ_B", "sqrshl"},
+{"SQRSHL_ZPmZ_D", "sqrshl"},
+{"SQRSHL_ZPmZ_H", "sqrshl"},
+{"SQRSHL_ZPmZ_S", "sqrshl"},
+{"SQRSHLv1i8", "sqrshl"},
+{"SQRSHLv1i16", "sqrshl"},
+{"SQRSHLv1i32", "sqrshl"},
+{"SQRSHLv1i64", "sqrshl"},
+{"SQRSHLv2i32", "sqrshl"},
+{"SQRSHLv2i64", "sqrshl"},
+{"SQRSHLv4i16", "sqrshl"},
+{"SQRSHLv4i32", "sqrshl"},
+{"SQRSHLv8i8", "sqrshl"},
+{"SQRSHLv8i16", "sqrshl"},
+{"SQRSHLv16i8", "sqrshl"},
+{"SQRSHRNB_ZZI_B", "sqrshrnb"},
+{"SQRSHRNB_ZZI_H", "sqrshrnb"},
+{"SQRSHRNB_ZZI_S", "sqrshrnb"},
+{"SQRSHRNT_ZZI_B", "sqrshrnt"},
+{"SQRSHRNT_ZZI_H", "sqrshrnt"},
+{"SQRSHRNT_ZZI_S", "sqrshrnt"},
+{"SQRSHRN_VG4_Z4ZI_B", "sqrshrn"},
+{"SQRSHRN_VG4_Z4ZI_H", "sqrshrn"},
+{"SQRSHRN_Z2ZI_HtoB", "sqrshrn"},
+{"SQRSHRN_Z2ZI_StoH", "sqrshrn"},
+{"SQRSHRNb", "sqrshrn"},
+{"SQRSHRNh", "sqrshrn"},
+{"SQRSHRNs", "sqrshrn"},
+{"SQRSHRNv2i32_shift", "sqrshrn"},
+{"SQRSHRNv4i16_shift", "sqrshrn"},
+{"SQRSHRNv8i8_shift", "sqrshrn"},
+{"SQRSHRNv4i32_shift", "sqrshrn2"},
+{"SQRSHRNv8i16_shift", "sqrshrn2"},
+{"SQRSHRNv16i8_shift", "sqrshrn2"},
+{"SQRSHRUNB_ZZI_B", "sqrshrunb"},
+{"SQRSHRUNB_ZZI_H", "sqrshrunb"},
+{"SQRSHRUNB_ZZI_S", "sqrshrunb"},
+{"SQRSHRUNT_ZZI_B", "sqrshrunt"},
+{"SQRSHRUNT_ZZI_H", "sqrshrunt"},
+{"SQRSHRUNT_ZZI_S", "sqrshrunt"},
+{"SQRSHRUN_VG4_Z4ZI_B", "sqrshrun"},
+{"SQRSHRUN_VG4_Z4ZI_H", "sqrshrun"},
+{"SQRSHRUN_Z2ZI_HtoB", "sqrshrun"},
+{"SQRSHRUN_Z2ZI_StoH", "sqrshrun"},
+{"SQRSHRUNb", "sqrshrun"},
+{"SQRSHRUNh", "sqrshrun"},
+{"SQRSHRUNs", "sqrshrun"},
+{"SQRSHRUNv2i32_shift", "sqrshrun"},
+{"SQRSHRUNv4i16_shift", "sqrshrun"},
+{"SQRSHRUNv8i8_shift", "sqrshrun"},
+{"SQRSHRUNv4i32_shift", "sqrshrun2"},
+{"SQRSHRUNv8i16_shift", "sqrshrun2"},
+{"SQRSHRUNv16i8_shift", "sqrshrun2"},
+{"SQRSHRU_VG2_Z2ZI_H", "sqrshru"},
+{"SQRSHRU_VG4_Z4ZI_B", "sqrshru"},
+{"SQRSHRU_VG4_Z4ZI_H", "sqrshru"},
+{"SQRSHR_VG2_Z2ZI_H", "sqrshr"},
+{"SQRSHR_VG4_Z4ZI_B", "sqrshr"},
+{"SQRSHR_VG4_Z4ZI_H", "sqrshr"},
+{"SQSHLR_ZPmZ_B", "sqshlr"},
+{"SQSHLR_ZPmZ_D", "sqshlr"},
+{"SQSHLR_ZPmZ_H", "sqshlr"},
+{"SQSHLR_ZPmZ_S", "sqshlr"},
+{"SQSHLU_ZPmI_B", "sqshlu"},
+{"SQSHLU_ZPmI_D", "sqshlu"},
+{"SQSHLU_ZPmI_H", "sqshlu"},
+{"SQSHLU_ZPmI_S", "sqshlu"},
+{"SQSHLUb", "sqshlu"},
+{"SQSHLUd", "sqshlu"},
+{"SQSHLUh", "sqshlu"},
+{"SQSHLUs", "sqshlu"},
+{"SQSHLUv2i32_shift", "sqshlu"},
+{"SQSHLUv2i64_shift", "sqshlu"},
+{"SQSHLUv4i16_shift", "sqshlu"},
+{"SQSHLUv4i32_shift", "sqshlu"},
+{"SQSHLUv8i8_shift", "sqshlu"},
+{"SQSHLUv8i16_shift", "sqshlu"},
+{"SQSHLUv16i8_shift", "sqshlu"},
+{"SQSHL_ZPmI_B", "sqshl"},
+{"SQSHL_ZPmI_D", "sqshl"},
+{"SQSHL_ZPmI_H", "sqshl"},
+{"SQSHL_ZPmI_S", "sqshl"},
+{"SQSHL_ZPmZ_B", "sqshl"},
+{"SQSHL_ZPmZ_D", "sqshl"},
+{"SQSHL_ZPmZ_H", "sqshl"},
+{"SQSHL_ZPmZ_S", "sqshl"},
+{"SQSHLb", "sqshl"},
+{"SQSHLd", "sqshl"},
+{"SQSHLh", "sqshl"},
+{"SQSHLs", "sqshl"},
+{"SQSHLv1i8", "sqshl"},
+{"SQSHLv1i16", "sqshl"},
+{"SQSHLv1i32", "sqshl"},
+{"SQSHLv1i64", "sqshl"},
+{"SQSHLv2i32", "sqshl"},
+{"SQSHLv2i32_shift", "sqshl"},
+{"SQSHLv2i64", "sqshl"},
+{"SQSHLv2i64_shift", "sqshl"},
+{"SQSHLv4i16", "sqshl"},
+{"SQSHLv4i16_shift", "sqshl"},
+{"SQSHLv4i32", "sqshl"},
+{"SQSHLv4i32_shift", "sqshl"},
+{"SQSHLv8i8", "sqshl"},
+{"SQSHLv8i8_shift", "sqshl"},
+{"SQSHLv8i16", "sqshl"},
+{"SQSHLv8i16_shift", "sqshl"},
+{"SQSHLv16i8", "sqshl"},
+{"SQSHLv16i8_shift", "sqshl"},
+{"SQSHRNB_ZZI_B", "sqshrnb"},
+{"SQSHRNB_ZZI_H", "sqshrnb"},
+{"SQSHRNB_ZZI_S", "sqshrnb"},
+{"SQSHRNT_ZZI_B", "sqshrnt"},
+{"SQSHRNT_ZZI_H", "sqshrnt"},
+{"SQSHRNT_ZZI_S", "sqshrnt"},
+{"SQSHRN_Z2ZI_HtoB", "sqshrn"},
+{"SQSHRN_Z2ZI_StoH", "sqshrn"},
+{"SQSHRNb", "sqshrn"},
+{"SQSHRNh", "sqshrn"},
+{"SQSHRNs", "sqshrn"},
+{"SQSHRNv2i32_shift", "sqshrn"},
+{"SQSHRNv4i16_shift", "sqshrn"},
+{"SQSHRNv8i8_shift", "sqshrn"},
+{"SQSHRNv4i32_shift", "sqshrn2"},
+{"SQSHRNv8i16_shift", "sqshrn2"},
+{"SQSHRNv16i8_shift", "sqshrn2"},
+{"SQSHRUNB_ZZI_B", "sqshrunb"},
+{"SQSHRUNB_ZZI_H", "sqshrunb"},
+{"SQSHRUNB_ZZI_S", "sqshrunb"},
+{"SQSHRUNT_ZZI_B", "sqshrunt"},
+{"SQSHRUNT_ZZI_H", "sqshrunt"},
+{"SQSHRUNT_ZZI_S", "sqshrunt"},
+{"SQSHRUN_Z2ZI_HtoB", "sqshrun"},
+{"SQSHRUN_Z2ZI_StoH", "sqshrun"},
+{"SQSHRUNb", "sqshrun"},
+{"SQSHRUNh", "sqshrun"},
+{"SQSHRUNs", "sqshrun"},
+{"SQSHRUNv2i32_shift", "sqshrun"},
+{"SQSHRUNv4i16_shift", "sqshrun"},
+{"SQSHRUNv8i8_shift", "sqshrun"},
+{"SQSHRUNv4i32_shift", "sqshrun2"},
+{"SQSHRUNv8i16_shift", "sqshrun2"},
+{"SQSHRUNv16i8_shift", "sqshrun2"},
+{"SQSUBR_ZPmZ_B", "sqsubr"},
+{"SQSUBR_ZPmZ_D", "sqsubr"},
+{"SQSUBR_ZPmZ_H", "sqsubr"},
+{"SQSUBR_ZPmZ_S", "sqsubr"},
+{"SQSUB_ZI_B", "sqsub"},
+{"SQSUB_ZI_D", "sqsub"},
+{"SQSUB_ZI_H", "sqsub"},
+{"SQSUB_ZI_S", "sqsub"},
+{"SQSUB_ZPmZ_B", "sqsub"},
+{"SQSUB_ZPmZ_D", "sqsub"},
+{"SQSUB_ZPmZ_H", "sqsub"},
+{"SQSUB_ZPmZ_S", "sqsub"},
+{"SQSUB_ZZZ_B", "sqsub"},
+{"SQSUB_ZZZ_D", "sqsub"},
+{"SQSUB_ZZZ_H", "sqsub"},
+{"SQSUB_ZZZ_S", "sqsub"},
+{"SQSUBv1i8", "sqsub"},
+{"SQSUBv1i16", "sqsub"},
+{"SQSUBv1i32", "sqsub"},
+{"SQSUBv1i64", "sqsub"},
+{"SQSUBv2i32", "sqsub"},
+{"SQSUBv2i64", "sqsub"},
+{"SQSUBv4i16", "sqsub"},
+{"SQSUBv4i32", "sqsub"},
+{"SQSUBv8i8", "sqsub"},
+{"SQSUBv8i16", "sqsub"},
+{"SQSUBv16i8", "sqsub"},
+{"SQXTNB_ZZ_B", "sqxtnb"},
+{"SQXTNB_ZZ_H", "sqxtnb"},
+{"SQXTNB_ZZ_S", "sqxtnb"},
+{"SQXTNT_ZZ_B", "sqxtnt"},
+{"SQXTNT_ZZ_H", "sqxtnt"},
+{"SQXTNT_ZZ_S", "sqxtnt"},
+{"SQXTNv1i8", "sqxtn"},
+{"SQXTNv1i16", "sqxtn"},
+{"SQXTNv1i32", "sqxtn"},
+{"SQXTNv2i32", "sqxtn"},
+{"SQXTNv4i16", "sqxtn"},
+{"SQXTNv8i8", "sqxtn"},
+{"SQXTNv4i32", "sqxtn2"},
+{"SQXTNv8i16", "sqxtn2"},
+{"SQXTNv16i8", "sqxtn2"},
+{"SQXTUNB_ZZ_B", "sqxtunb"},
+{"SQXTUNB_ZZ_H", "sqxtunb"},
+{"SQXTUNB_ZZ_S", "sqxtunb"},
+{"SQXTUNT_ZZ_B", "sqxtunt"},
+{"SQXTUNT_ZZ_H", "sqxtunt"},
+{"SQXTUNT_ZZ_S", "sqxtunt"},
+{"SQXTUNv1i8", "sqxtun"},
+{"SQXTUNv1i16", "sqxtun"},
+{"SQXTUNv1i32", "sqxtun"},
+{"SQXTUNv2i32", "sqxtun"},
+{"SQXTUNv4i16", "sqxtun"},
+{"SQXTUNv8i8", "sqxtun"},
+{"SQXTUNv4i32", "sqxtun2"},
+{"SQXTUNv8i16", "sqxtun2"},
+{"SQXTUNv16i8", "sqxtun2"},
+{"SRHADD_ZPmZ_B", "srhadd"},
+{"SRHADD_ZPmZ_D", "srhadd"},
+{"SRHADD_ZPmZ_H", "srhadd"},
+{"SRHADD_ZPmZ_S", "srhadd"},
+{"SRHADDv2i32", "srhadd"},
+{"SRHADDv4i16", "srhadd"},
+{"SRHADDv4i32", "srhadd"},
+{"SRHADDv8i8", "srhadd"},
+{"SRHADDv8i16", "srhadd"},
+{"SRHADDv16i8", "srhadd"},
+{"SRI_ZZI_B", "sri"},
+{"SRI_ZZI_D", "sri"},
+{"SRI_ZZI_H", "sri"},
+{"SRI_ZZI_S", "sri"},
+{"SRId", "sri"},
+{"SRIv2i32_shift", "sri"},
+{"SRIv2i64_shift", "sri"},
+{"SRIv4i16_shift", "sri"},
+{"SRIv4i32_shift", "sri"},
+{"SRIv8i8_shift", "sri"},
+{"SRIv8i16_shift", "sri"},
+{"SRIv16i8_shift", "sri"},
+{"SRSHLR_ZPmZ_B", "srshlr"},
+{"SRSHLR_ZPmZ_D", "srshlr"},
+{"SRSHLR_ZPmZ_H", "srshlr"},
+{"SRSHLR_ZPmZ_S", "srshlr"},
+{"SRSHL_VG2_2Z2Z_B", "srshl"},
+{"SRSHL_VG2_2Z2Z_D", "srshl"},
+{"SRSHL_VG2_2Z2Z_H", "srshl"},
+{"SRSHL_VG2_2Z2Z_S", "srshl"},
+{"SRSHL_VG2_2ZZ_B", "srshl"},
+{"SRSHL_VG2_2ZZ_D", "srshl"},
+{"SRSHL_VG2_2ZZ_H", "srshl"},
+{"SRSHL_VG2_2ZZ_S", "srshl"},
+{"SRSHL_VG4_4Z4Z_B", "srshl"},
+{"SRSHL_VG4_4Z4Z_D", "srshl"},
+{"SRSHL_VG4_4Z4Z_H", "srshl"},
+{"SRSHL_VG4_4Z4Z_S", "srshl"},
+{"SRSHL_VG4_4ZZ_B", "srshl"},
+{"SRSHL_VG4_4ZZ_D", "srshl"},
+{"SRSHL_VG4_4ZZ_H", "srshl"},
+{"SRSHL_VG4_4ZZ_S", "srshl"},
+{"SRSHL_ZPmZ_B", "srshl"},
+{"SRSHL_ZPmZ_D", "srshl"},
+{"SRSHL_ZPmZ_H", "srshl"},
+{"SRSHL_ZPmZ_S", "srshl"},
+{"SRSHLv1i64", "srshl"},
+{"SRSHLv2i32", "srshl"},
+{"SRSHLv2i64", "srshl"},
+{"SRSHLv4i16", "srshl"},
+{"SRSHLv4i32", "srshl"},
+{"SRSHLv8i8", "srshl"},
+{"SRSHLv8i16", "srshl"},
+{"SRSHLv16i8", "srshl"},
+{"SRSHR_ZPmI_B", "srshr"},
+{"SRSHR_ZPmI_D", "srshr"},
+{"SRSHR_ZPmI_H", "srshr"},
+{"SRSHR_ZPmI_S", "srshr"},
+{"SRSHRd", "srshr"},
+{"SRSHRv2i32_shift", "srshr"},
+{"SRSHRv2i64_shift", "srshr"},
+{"SRSHRv4i16_shift", "srshr"},
+{"SRSHRv4i32_shift", "srshr"},
+{"SRSHRv8i8_shift", "srshr"},
+{"SRSHRv8i16_shift", "srshr"},
+{"SRSHRv16i8_shift", "srshr"},
+{"SRSRA_ZZI_B", "srsra"},
+{"SRSRA_ZZI_D", "srsra"},
+{"SRSRA_ZZI_H", "srsra"},
+{"SRSRA_ZZI_S", "srsra"},
+{"SRSRAd", "srsra"},
+{"SRSRAv2i32_shift", "srsra"},
+{"SRSRAv2i64_shift", "srsra"},
+{"SRSRAv4i16_shift", "srsra"},
+{"SRSRAv4i32_shift", "srsra"},
+{"SRSRAv8i8_shift", "srsra"},
+{"SRSRAv8i16_shift", "srsra"},
+{"SRSRAv16i8_shift", "srsra"},
+{"SSHLLB_ZZI_D", "sshllb"},
+{"SSHLLB_ZZI_H", "sshllb"},
+{"SSHLLB_ZZI_S", "sshllb"},
+{"SSHLLT_ZZI_D", "sshllt"},
+{"SSHLLT_ZZI_H", "sshllt"},
+{"SSHLLT_ZZI_S", "sshllt"},
+{"SSHLLv2i32_shift", "sshll"},
+{"SSHLLv4i16_shift", "sshll"},
+{"SSHLLv8i8_shift", "sshll"},
+{"SSHLLv4i32_shift", "sshll2"},
+{"SSHLLv8i16_shift", "sshll2"},
+{"SSHLLv16i8_shift", "sshll2"},
+{"SSHLv1i64", "sshl"},
+{"SSHLv2i32", "sshl"},
+{"SSHLv2i64", "sshl"},
+{"SSHLv4i16", "sshl"},
+{"SSHLv4i32", "sshl"},
+{"SSHLv8i8", "sshl"},
+{"SSHLv8i16", "sshl"},
+{"SSHLv16i8", "sshl"},
+{"SSHRd", "sshr"},
+{"SSHRv2i32_shift", "sshr"},
+{"SSHRv2i64_shift", "sshr"},
+{"SSHRv4i16_shift", "sshr"},
+{"SSHRv4i32_shift", "sshr"},
+{"SSHRv8i8_shift", "sshr"},
+{"SSHRv8i16_shift", "sshr"},
+{"SSHRv16i8_shift", "sshr"},
+{"SSRA_ZZI_B", "ssra"},
+{"SSRA_ZZI_D", "ssra"},
+{"SSRA_ZZI_H", "ssra"},
+{"SSRA_ZZI_S", "ssra"},
+{"SSRAd", "ssra"},
+{"SSRAv2i32_shift", "ssra"},
+{"SSRAv2i64_shift", "ssra"},
+{"SSRAv4i16_shift", "ssra"},
+{"SSRAv4i32_shift", "ssra"},
+{"SSRAv8i8_shift", "ssra"},
+{"SSRAv8i16_shift", "ssra"},
+{"SSRAv16i8_shift", "ssra"},
+{"SST1B_D", "st1b"},
+{"SST1B_D_IMM", "st1b"},
+{"SST1B_D_SXTW", "st1b"},
+{"SST1B_D_UXTW", "st1b"},
+{"SST1B_S_IMM", "st1b"},
+{"SST1B_S_SXTW", "st1b"},
+{"SST1B_S_UXTW", "st1b"},
+{"ST1B", "st1b"},
+{"ST1B_2Z", "st1b"},
+{"ST1B_2Z_IMM", "st1b"},
+{"ST1B_2Z_STRIDED", "st1b"},
+{"ST1B_2Z_STRIDED_IMM", "st1b"},
+{"ST1B_4Z", "st1b"},
+{"ST1B_4Z_IMM", "st1b"},
+{"ST1B_4Z_STRIDED", "st1b"},
+{"ST1B_4Z_STRIDED_IMM", "st1b"},
+{"ST1B_D", "st1b"},
+{"ST1B_D_IMM", "st1b"},
+{"ST1B_H", "st1b"},
+{"ST1B_H_IMM", "st1b"},
+{"ST1B_IMM", "st1b"},
+{"ST1B_S", "st1b"},
+{"ST1B_S_IMM", "st1b"},
+{"ST1_MXIPXX_H_B", "st1b"},
+{"ST1_MXIPXX_V_B", "st1b"},
+{"SST1D", "st1d"},
+{"SST1D_IMM", "st1d"},
+{"SST1D_SCALED", "st1d"},
+{"SST1D_SXTW", "st1d"},
+{"SST1D_SXTW_SCALED", "st1d"},
+{"SST1D_UXTW", "st1d"},
+{"SST1D_UXTW_SCALED", "st1d"},
+{"ST1D", "st1d"},
+{"ST1D_2Z", "st1d"},
+{"ST1D_2Z_IMM", "st1d"},
+{"ST1D_2Z_STRIDED", "st1d"},
+{"ST1D_2Z_STRIDED_IMM", "st1d"},
+{"ST1D_4Z", "st1d"},
+{"ST1D_4Z_IMM", "st1d"},
+{"ST1D_4Z_STRIDED", "st1d"},
+{"ST1D_4Z_STRIDED_IMM", "st1d"},
+{"ST1D_IMM", "st1d"},
+{"ST1D_Q", "st1d"},
+{"ST1D_Q_IMM", "st1d"},
+{"ST1_MXIPXX_H_D", "st1d"},
+{"ST1_MXIPXX_V_D", "st1d"},
+{"SST1H_D", "st1h"},
+{"SST1H_D_IMM", "st1h"},
+{"SST1H_D_SCALED", "st1h"},
+{"SST1H_D_SXTW", "st1h"},
+{"SST1H_D_SXTW_SCALED", "st1h"},
+{"SST1H_D_UXTW", "st1h"},
+{"SST1H_D_UXTW_SCALED", "st1h"},
+{"SST1H_S_IMM", "st1h"},
+{"SST1H_S_SXTW", "st1h"},
+{"SST1H_S_SXTW_SCALED", "st1h"},
+{"SST1H_S_UXTW", "st1h"},
+{"SST1H_S_UXTW_SCALED", "st1h"},
+{"ST1H", "st1h"},
+{"ST1H_2Z", "st1h"},
+{"ST1H_2Z_IMM", "st1h"},
+{"ST1H_2Z_STRIDED", "st1h"},
+{"ST1H_2Z_STRIDED_IMM", "st1h"},
+{"ST1H_4Z", "st1h"},
+{"ST1H_4Z_IMM", "st1h"},
+{"ST1H_4Z_STRIDED", "st1h"},
+{"ST1H_4Z_STRIDED_IMM", "st1h"},
+{"ST1H_D", "st1h"},
+{"ST1H_D_IMM", "st1h"},
+{"ST1H_IMM", "st1h"},
+{"ST1H_S", "st1h"},
+{"ST1H_S_IMM", "st1h"},
+{"ST1_MXIPXX_H_H", "st1h"},
+{"ST1_MXIPXX_V_H", "st1h"},
+{"SST1Q", "st1q"},
+{"ST1_MXIPXX_H_Q", "st1q"},
+{"ST1_MXIPXX_V_Q", "st1q"},
+{"SST1W_D", "st1w"},
+{"SST1W_D_IMM", "st1w"},
+{"SST1W_D_SCALED", "st1w"},
+{"SST1W_D_SXTW", "st1w"},
+{"SST1W_D_SXTW_SCALED", "st1w"},
+{"SST1W_D_UXTW", "st1w"},
+{"SST1W_D_UXTW_SCALED", "st1w"},
+{"SST1W_IMM", "st1w"},
+{"SST1W_SXTW", "st1w"},
+{"SST1W_SXTW_SCALED", "st1w"},
+{"SST1W_UXTW", "st1w"},
+{"SST1W_UXTW_SCALED", "st1w"},
+{"ST1W", "st1w"},
+{"ST1W_2Z", "st1w"},
+{"ST1W_2Z_IMM", "st1w"},
+{"ST1W_2Z_STRIDED", "st1w"},
+{"ST1W_2Z_STRIDED_IMM", "st1w"},
+{"ST1W_4Z", "st1w"},
+{"ST1W_4Z_IMM", "st1w"},
+{"ST1W_4Z_STRIDED", "st1w"},
+{"ST1W_4Z_STRIDED_IMM", "st1w"},
+{"ST1W_D", "st1w"},
+{"ST1W_D_IMM", "st1w"},
+{"ST1W_IMM", "st1w"},
+{"ST1W_Q", "st1w"},
+{"ST1W_Q_IMM", "st1w"},
+{"ST1_MXIPXX_H_S", "st1w"},
+{"ST1_MXIPXX_V_S", "st1w"},
+{"SSUBLBT_ZZZ_D", "ssublbt"},
+{"SSUBLBT_ZZZ_H", "ssublbt"},
+{"SSUBLBT_ZZZ_S", "ssublbt"},
+{"SSUBLB_ZZZ_D", "ssublb"},
+{"SSUBLB_ZZZ_H", "ssublb"},
+{"SSUBLB_ZZZ_S", "ssublb"},
+{"SSUBLTB_ZZZ_D", "ssubltb"},
+{"SSUBLTB_ZZZ_H", "ssubltb"},
+{"SSUBLTB_ZZZ_S", "ssubltb"},
+{"SSUBLT_ZZZ_D", "ssublt"},
+{"SSUBLT_ZZZ_H", "ssublt"},
+{"SSUBLT_ZZZ_S", "ssublt"},
+{"SSUBLv2i32_v2i64", "ssubl"},
+{"SSUBLv4i16_v4i32", "ssubl"},
+{"SSUBLv8i8_v8i16", "ssubl"},
+{"SSUBLv4i32_v2i64", "ssubl2"},
+{"SSUBLv8i16_v4i32", "ssubl2"},
+{"SSUBLv16i8_v8i16", "ssubl2"},
+{"SSUBWB_ZZZ_D", "ssubwb"},
+{"SSUBWB_ZZZ_H", "ssubwb"},
+{"SSUBWB_ZZZ_S", "ssubwb"},
+{"SSUBWT_ZZZ_D", "ssubwt"},
+{"SSUBWT_ZZZ_H", "ssubwt"},
+{"SSUBWT_ZZZ_S", "ssubwt"},
+{"SSUBWv2i32_v2i64", "ssubw"},
+{"SSUBWv4i16_v4i32", "ssubw"},
+{"SSUBWv8i8_v8i16", "ssubw"},
+{"SSUBWv4i32_v2i64", "ssubw2"},
+{"SSUBWv8i16_v4i32", "ssubw2"},
+{"SSUBWv16i8_v8i16", "ssubw2"},
+{"ST1Fourv1d", "st1"},
+{"ST1Fourv1d_POST", "st1"},
+{"ST1Fourv2d", "st1"},
+{"ST1Fourv2d_POST", "st1"},
+{"ST1Fourv2s", "st1"},
+{"ST1Fourv2s_POST", "st1"},
+{"ST1Fourv4h", "st1"},
+{"ST1Fourv4h_POST", "st1"},
+{"ST1Fourv4s", "st1"},
+{"ST1Fourv4s_POST", "st1"},
+{"ST1Fourv8b", "st1"},
+{"ST1Fourv8b_POST", "st1"},
+{"ST1Fourv8h", "st1"},
+{"ST1Fourv8h_POST", "st1"},
+{"ST1Fourv16b", "st1"},
+{"ST1Fourv16b_POST", "st1"},
+{"ST1Onev1d", "st1"},
+{"ST1Onev1d_POST", "st1"},
+{"ST1Onev2d", "st1"},
+{"ST1Onev2d_POST", "st1"},
+{"ST1Onev2s", "st1"},
+{"ST1Onev2s_POST", "st1"},
+{"ST1Onev4h", "st1"},
+{"ST1Onev4h_POST", "st1"},
+{"ST1Onev4s", "st1"},
+{"ST1Onev4s_POST", "st1"},
+{"ST1Onev8b", "st1"},
+{"ST1Onev8b_POST", "st1"},
+{"ST1Onev8h", "st1"},
+{"ST1Onev8h_POST", "st1"},
+{"ST1Onev16b", "st1"},
+{"ST1Onev16b_POST", "st1"},
+{"ST1Threev1d", "st1"},
+{"ST1Threev1d_POST", "st1"},
+{"ST1Threev2d", "st1"},
+{"ST1Threev2d_POST", "st1"},
+{"ST1Threev2s", "st1"},
+{"ST1Threev2s_POST", "st1"},
+{"ST1Threev4h", "st1"},
+{"ST1Threev4h_POST", "st1"},
+{"ST1Threev4s", "st1"},
+{"ST1Threev4s_POST", "st1"},
+{"ST1Threev8b", "st1"},
+{"ST1Threev8b_POST", "st1"},
+{"ST1Threev8h", "st1"},
+{"ST1Threev8h_POST", "st1"},
+{"ST1Threev16b", "st1"},
+{"ST1Threev16b_POST", "st1"},
+{"ST1Twov1d", "st1"},
+{"ST1Twov1d_POST", "st1"},
+{"ST1Twov2d", "st1"},
+{"ST1Twov2d_POST", "st1"},
+{"ST1Twov2s", "st1"},
+{"ST1Twov2s_POST", "st1"},
+{"ST1Twov4h", "st1"},
+{"ST1Twov4h_POST", "st1"},
+{"ST1Twov4s", "st1"},
+{"ST1Twov4s_POST", "st1"},
+{"ST1Twov8b", "st1"},
+{"ST1Twov8b_POST", "st1"},
+{"ST1Twov8h", "st1"},
+{"ST1Twov8h_POST", "st1"},
+{"ST1Twov16b", "st1"},
+{"ST1Twov16b_POST", "st1"},
+{"ST1i8", "st1"},
+{"ST1i8_POST", "st1"},
+{"ST1i16", "st1"},
+{"ST1i16_POST", "st1"},
+{"ST1i32", "st1"},
+{"ST1i32_POST", "st1"},
+{"ST1i64", "st1"},
+{"ST1i64_POST", "st1"},
+{"ST2B", "st2b"},
+{"ST2B_IMM", "st2b"},
+{"ST2D", "st2d"},
+{"ST2D_IMM", "st2d"},
+{"ST2GPostIndex", "st2g"},
+{"ST2GPreIndex", "st2g"},
+{"ST2Gi", "st2g"},
+{"ST2H", "st2h"},
+{"ST2H_IMM", "st2h"},
+{"ST2Q", "st2q"},
+{"ST2Q_IMM", "st2q"},
+{"ST2Twov2d", "st2"},
+{"ST2Twov2d_POST", "st2"},
+{"ST2Twov2s", "st2"},
+{"ST2Twov2s_POST", "st2"},
+{"ST2Twov4h", "st2"},
+{"ST2Twov4h_POST", "st2"},
+{"ST2Twov4s", "st2"},
+{"ST2Twov4s_POST", "st2"},
+{"ST2Twov8b", "st2"},
+{"ST2Twov8b_POST", "st2"},
+{"ST2Twov8h", "st2"},
+{"ST2Twov8h_POST", "st2"},
+{"ST2Twov16b", "st2"},
+{"ST2Twov16b_POST", "st2"},
+{"ST2i8", "st2"},
+{"ST2i8_POST", "st2"},
+{"ST2i16", "st2"},
+{"ST2i16_POST", "st2"},
+{"ST2i32", "st2"},
+{"ST2i32_POST", "st2"},
+{"ST2i64", "st2"},
+{"ST2i64_POST", "st2"},
+{"ST2W", "st2w"},
+{"ST2W_IMM", "st2w"},
+{"ST3B", "st3b"},
+{"ST3B_IMM", "st3b"},
+{"ST3D", "st3d"},
+{"ST3D_IMM", "st3d"},
+{"ST3H", "st3h"},
+{"ST3H_IMM", "st3h"},
+{"ST3Q", "st3q"},
+{"ST3Q_IMM", "st3q"},
+{"ST3Threev2d", "st3"},
+{"ST3Threev2d_POST", "st3"},
+{"ST3Threev2s", "st3"},
+{"ST3Threev2s_POST", "st3"},
+{"ST3Threev4h", "st3"},
+{"ST3Threev4h_POST", "st3"},
+{"ST3Threev4s", "st3"},
+{"ST3Threev4s_POST", "st3"},
+{"ST3Threev8b", "st3"},
+{"ST3Threev8b_POST", "st3"},
+{"ST3Threev8h", "st3"},
+{"ST3Threev8h_POST", "st3"},
+{"ST3Threev16b", "st3"},
+{"ST3Threev16b_POST", "st3"},
+{"ST3i8", "st3"},
+{"ST3i8_POST", "st3"},
+{"ST3i16", "st3"},
+{"ST3i16_POST", "st3"},
+{"ST3i32", "st3"},
+{"ST3i32_POST", "st3"},
+{"ST3i64", "st3"},
+{"ST3i64_POST", "st3"},
+{"ST3W", "st3w"},
+{"ST3W_IMM", "st3w"},
+{"ST4B", "st4b"},
+{"ST4B_IMM", "st4b"},
+{"ST4D", "st4d"},
+{"ST4D_IMM", "st4d"},
+{"ST4Fourv2d", "st4"},
+{"ST4Fourv2d_POST", "st4"},
+{"ST4Fourv2s", "st4"},
+{"ST4Fourv2s_POST", "st4"},
+{"ST4Fourv4h", "st4"},
+{"ST4Fourv4h_POST", "st4"},
+{"ST4Fourv4s", "st4"},
+{"ST4Fourv4s_POST", "st4"},
+{"ST4Fourv8b", "st4"},
+{"ST4Fourv8b_POST", "st4"},
+{"ST4Fourv8h", "st4"},
+{"ST4Fourv8h_POST", "st4"},
+{"ST4Fourv16b", "st4"},
+{"ST4Fourv16b_POST", "st4"},
+{"ST4i8", "st4"},
+{"ST4i8_POST", "st4"},
+{"ST4i16", "st4"},
+{"ST4i16_POST", "st4"},
+{"ST4i32", "st4"},
+{"ST4i32_POST", "st4"},
+{"ST4i64", "st4"},
+{"ST4i64_POST", "st4"},
+{"ST4H", "st4h"},
+{"ST4H_IMM", "st4h"},
+{"ST4Q", "st4q"},
+{"ST4Q_IMM", "st4q"},
+{"ST4W", "st4w"},
+{"ST4W_IMM", "st4w"},
+{"ST64B", "st64b"},
+{"ST64BV", "st64bv"},
+{"ST64BV0", "st64bv0"},
+{"STBFADD", "stbfadd"},
+{"STBFADDL", "stbfaddl"},
+{"STBFMAX", "stbfmax"},
+{"STBFMAXL", "stbfmaxl"},
+{"STBFMAXNM", "stbfmaxnm"},
+{"STBFMAXNML", "stbfmaxnml"},
+{"STBFMIN", "stbfmin"},
+{"STBFMINL", "stbfminl"},
+{"STBFMINNM", "stbfminnm"},
+{"STBFMINNML", "stbfminnml"},
+{"STFADDD", "stfadd"},
+{"STFADDH", "stfadd"},
+{"STFADDS", "stfadd"},
+{"STFADDLD", "stfaddl"},
+{"STFADDLH", "stfaddl"},
+{"STFADDLS", "stfaddl"},
+{"STFMAXD", "stfmax"},
+{"STFMAXH", "stfmax"},
+{"STFMAXS", "stfmax"},
+{"STFMAXLD", "stfmaxl"},
+{"STFMAXLH", "stfmaxl"},
+{"STFMAXLS", "stfmaxl"},
+{"STFMAXNMD", "stfmaxnm"},
+{"STFMAXNMH", "stfmaxnm"},
+{"STFMAXNMS", "stfmaxnm"},
+{"STFMAXNMLD", "stfmaxnml"},
+{"STFMAXNMLH", "stfmaxnml"},
+{"STFMAXNMLS", "stfmaxnml"},
+{"STFMIND", "stfmin"},
+{"STFMINH", "stfmin"},
+{"STFMINS", "stfmin"},
+{"STFMINLD", "stfminl"},
+{"STFMINLH", "stfminl"},
+{"STFMINLS", "stfminl"},
+{"STFMINNMD", "stfminnm"},
+{"STFMINNMH", "stfminnm"},
+{"STFMINNMS", "stfminnm"},
+{"STFMINNMLD", "stfminnml"},
+{"STFMINNMLH", "stfminnml"},
+{"STFMINNMLS", "stfminnml"},
+{"STGM", "stgm"},
+{"STGPi", "stgp"},
+{"STGPpost", "stgp"},
+{"STGPpre", "stgp"},
+{"STGPostIndex", "stg"},
+{"STGPreIndex", "stg"},
+{"STGi", "stg"},
+{"STILPW", "stilp"},
+{"STILPWpre", "stilp"},
+{"STILPX", "stilp"},
+{"STILPXpre", "stilp"},
+{"STL1", "stl1"},
+{"STLLRB", "stllrb"},
+{"STLLRH", "stllrh"},
+{"STLLRW", "stllr"},
+{"STLLRX", "stllr"},
+{"STLPi", "stlp"},
+{"STLRB", "stlrb"},
+{"STLRH", "stlrh"},
+{"STLRW", "stlr"},
+{"STLRWpre", "stlr"},
+{"STLRX", "stlr"},
+{"STLRXpre", "stlr"},
+{"STLTXRW", "stltxr"},
+{"STLTXRX", "stltxr"},
+{"STLURBi", "stlurb"},
+{"STLURHi", "stlurh"},
+{"STLURWi", "stlur"},
+{"STLURXi", "stlur"},
+{"STLURbi", "stlur"},
+{"STLURdi", "stlur"},
+{"STLURhi", "stlur"},
+{"STLURqi", "stlur"},
+{"STLURsi", "stlur"},
+{"STLXPW", "stlxp"},
+{"STLXPX", "stlxp"},
+{"STLXRB", "stlxrb"},
+{"STLXRH", "stlxrh"},
+{"STLXRW", "stlxr"},
+{"STLXRX", "stlxr"},
+{"STMOPA_M2ZZZI_BtoS", "stmopa"},
+{"STMOPA_M2ZZZI_HtoS", "stmopa"},
+{"STNPDi", "stnp"},
+{"STNPQi", "stnp"},
+{"STNPSi", "stnp"},
+{"STNPWi", "stnp"},
+{"STNPXi", "stnp"},
+{"STNT1B_2Z", "stnt1b"},
+{"STNT1B_2Z_IMM", "stnt1b"},
+{"STNT1B_2Z_STRIDED", "stnt1b"},
+{"STNT1B_2Z_STRIDED_IMM", "stnt1b"},
+{"STNT1B_4Z", "stnt1b"},
+{"STNT1B_4Z_IMM", "stnt1b"},
+{"STNT1B_4Z_STRIDED", "stnt1b"},
+{"STNT1B_4Z_STRIDED_IMM", "stnt1b"},
+{"STNT1B_ZRI", "stnt1b"},
+{"STNT1B_ZRR", "stnt1b"},
+{"STNT1B_ZZR_D", "stnt1b"},
+{"STNT1B_ZZR_S", "stnt1b"},
+{"STNT1D_2Z", "stnt1d"},
+{"STNT1D_2Z_IMM", "stnt1d"},
+{"STNT1D_2Z_STRIDED", "stnt1d"},
+{"STNT1D_2Z_STRIDED_IMM", "stnt1d"},
+{"STNT1D_4Z", "stnt1d"},
+{"STNT1D_4Z_IMM", "stnt1d"},
+{"STNT1D_4Z_STRIDED", "stnt1d"},
+{"STNT1D_4Z_STRIDED_IMM", "stnt1d"},
+{"STNT1D_ZRI", "stnt1d"},
+{"STNT1D_ZRR", "stnt1d"},
+{"STNT1D_ZZR_D", "stnt1d"},
+{"STNT1H_2Z", "stnt1h"},
+{"STNT1H_2Z_IMM", "stnt1h"},
+{"STNT1H_2Z_STRIDED", "stnt1h"},
+{"STNT1H_2Z_STRIDED_IMM", "stnt1h"},
+{"STNT1H_4Z", "stnt1h"},
+{"STNT1H_4Z_IMM", "stnt1h"},
+{"STNT1H_4Z_STRIDED", "stnt1h"},
+{"STNT1H_4Z_STRIDED_IMM", "stnt1h"},
+{"STNT1H_ZRI", "stnt1h"},
+{"STNT1H_ZRR", "stnt1h"},
+{"STNT1H_ZZR_D", "stnt1h"},
+{"STNT1H_ZZR_S", "stnt1h"},
+{"STNT1W_2Z", "stnt1w"},
+{"STNT1W_2Z_IMM", "stnt1w"},
+{"STNT1W_2Z_STRIDED", "stnt1w"},
+{"STNT1W_2Z_STRIDED_IMM", "stnt1w"},
+{"STNT1W_4Z", "stnt1w"},
+{"STNT1W_4Z_IMM", "stnt1w"},
+{"STNT1W_4Z_STRIDED", "stnt1w"},
+{"STNT1W_4Z_STRIDED_IMM", "stnt1w"},
+{"STNT1W_ZRI", "stnt1w"},
+{"STNT1W_ZRR", "stnt1w"},
+{"STNT1W_ZZR_D", "stnt1w"},
+{"STNT1W_ZZR_S", "stnt1w"},
+{"STPDi", "stp"},
+{"STPDpost", "stp"},
+{"STPDpre", "stp"},
+{"STPQi", "stp"},
+{"STPQpost", "stp"},
+{"STPQpre", "stp"},
+{"STPSi", "stp"},
+{"STPSpost", "stp"},
+{"STPSpre", "stp"},
+{"STPWi", "stp"},
+{"STPWpost", "stp"},
+{"STPWpre", "stp"},
+{"STPXi", "stp"},
+{"STPXpost", "stp"},
+{"STPXpre", "stp"},
+{"STRBBpost", "strb"},
+{"STRBBpre", "strb"},
+{"STRBBroW", "strb"},
+{"STRBBroX", "strb"},
+{"STRBBui", "strb"},
+{"STRBpost", "str"},
+{"STRBpre", "str"},
+{"STRBroW", "str"},
+{"STRBroX", "str"},
+{"STRBui", "str"},
+{"STRDpost", "str"},
+{"STRDpre", "str"},
+{"STRDroW", "str"},
+{"STRDroX", "str"},
+{"STRDui", "str"},
+{"STRHpost", "str"},
+{"STRHpre", "str"},
+{"STRHroW", "str"},
+{"STRHroX", "str"},
+{"STRHui", "str"},
+{"STRQpost", "str"},
+{"STRQpre", "str"},
+{"STRQroW", "str"},
+{"STRQroX", "str"},
+{"STRQui", "str"},
+{"STRSpost", "str"},
+{"STRSpre", "str"},
+{"STRSroW", "str"},
+{"STRSroX", "str"},
+{"STRSui", "str"},
+{"STRWpost", "str"},
+{"STRWpre", "str"},
+{"STRWroW", "str"},
+{"STRWroX", "str"},
+{"STRWui", "str"},
+{"STRXpost", "str"},
+{"STRXpre", "str"},
+{"STRXroW", "str"},
+{"STRXroX", "str"},
+{"STRXui", "str"},
+{"STR_PXI", "str"},
+{"STR_TX", "str"},
+{"STR_ZA", "str"},
+{"STR_ZXI", "str"},
+{"STRHHpost", "strh"},
+{"STRHHpre", "strh"},
+{"STRHHroW", "strh"},
+{"STRHHroX", "strh"},
+{"STRHHui", "strh"},
+{"STTNPQi", "sttnp"},
+{"STTNPXi", "sttnp"},
+{"STTPQi", "sttp"},
+{"STTPQpost", "sttp"},
+{"STTPQpre", "sttp"},
+{"STTPi", "sttp"},
+{"STTPpost", "sttp"},
+{"STTPpre", "sttp"},
+{"STTRBi", "sttrb"},
+{"STTRHi", "sttrh"},
+{"STTRWi", "sttr"},
+{"STTRXi", "sttr"},
+{"STTXRWr", "sttxr"},
+{"STTXRXr", "sttxr"},
+{"STURBBi", "sturb"},
+{"STURBi", "stur"},
+{"STURDi", "stur"},
+{"STURHi", "stur"},
+{"STURQi", "stur"},
+{"STURSi", "stur"},
+{"STURWi", "stur"},
+{"STURXi", "stur"},
+{"STURHHi", "sturh"},
+{"STXPW", "stxp"},
+{"STXPX", "stxp"},
+{"STXRB", "stxrb"},
+{"STXRH", "stxrh"},
+{"STXRW", "stxr"},
+{"STXRX", "stxr"},
+{"STZ2GPostIndex", "stz2g"},
+{"STZ2GPreIndex", "stz2g"},
+{"STZ2Gi", "stz2g"},
+{"STZGM", "stzgm"},
+{"STZGPostIndex", "stzg"},
+{"STZGPreIndex", "stzg"},
+{"STZGi", "stzg"},
+{"SUBG", "subg"},
+{"SUBHNB_ZZZ_B", "subhnb"},
+{"SUBHNB_ZZZ_H", "subhnb"},
+{"SUBHNB_ZZZ_S", "subhnb"},
+{"SUBHNT_ZZZ_B", "subhnt"},
+{"SUBHNT_ZZZ_H", "subhnt"},
+{"SUBHNT_ZZZ_S", "subhnt"},
+{"SUBHNv2i64_v2i32", "subhn"},
+{"SUBHNv4i32_v4i16", "subhn"},
+{"SUBHNv8i16_v8i8", "subhn"},
+{"SUBHNv2i64_v4i32", "subhn2"},
+{"SUBHNv4i32_v8i16", "subhn2"},
+{"SUBHNv8i16_v16i8", "subhn2"},
+{"SUBP", "subp"},
+{"SUBP_ZPmZZ_B", "subp"},
+{"SUBP_ZPmZZ_D", "subp"},
+{"SUBP_ZPmZZ_H", "subp"},
+{"SUBP_ZPmZZ_S", "subp"},
+{"SUBPS", "subps"},
+{"SUBPT_shift", "subpt"},
+{"SUB_ZPmZ_CPA", "subpt"},
+{"SUB_ZZZ_CPA", "subpt"},
+{"SUBR_ZI_B", "subr"},
+{"SUBR_ZI_D", "subr"},
+{"SUBR_ZI_H", "subr"},
+{"SUBR_ZI_S", "subr"},
+{"SUBR_ZPmZ_B", "subr"},
+{"SUBR_ZPmZ_D", "subr"},
+{"SUBR_ZPmZ_H", "subr"},
+{"SUBR_ZPmZ_S", "subr"},
+{"SUBSWri", "subs"},
+{"SUBSWrs", "subs"},
+{"SUBSWrx", "subs"},
+{"SUBSXri", "subs"},
+{"SUBSXrs", "subs"},
+{"SUBSXrx", "subs"},
+{"SUBSXrx64", "subs"},
+{"SUBWri", "sub"},
+{"SUBWrs", "sub"},
+{"SUBWrx", "sub"},
+{"SUBXri", "sub"},
+{"SUBXrs", "sub"},
+{"SUBXrx", "sub"},
+{"SUBXrx64", "sub"},
+{"SUB_VG2_M2Z2Z_D", "sub"},
+{"SUB_VG2_M2Z2Z_S", "sub"},
+{"SUB_VG2_M2ZZ_D", "sub"},
+{"SUB_VG2_M2ZZ_S", "sub"},
+{"SUB_VG2_M2Z_D", "sub"},
+{"SUB_VG2_M2Z_S", "sub"},
+{"SUB_VG4_M4Z4Z_D", "sub"},
+{"SUB_VG4_M4Z4Z_S", "sub"},
+{"SUB_VG4_M4ZZ_D", "sub"},
+{"SUB_VG4_M4ZZ_S", "sub"},
+{"SUB_VG4_M4Z_D", "sub"},
+{"SUB_VG4_M4Z_S", "sub"},
+{"SUB_ZI_B", "sub"},
+{"SUB_ZI_D", "sub"},
+{"SUB_ZI_H", "sub"},
+{"SUB_ZI_S", "sub"},
+{"SUB_ZPmZ_B", "sub"},
+{"SUB_ZPmZ_D", "sub"},
+{"SUB_ZPmZ_H", "sub"},
+{"SUB_ZPmZ_S", "sub"},
+{"SUB_ZZZ_B", "sub"},
+{"SUB_ZZZ_D", "sub"},
+{"SUB_ZZZ_H", "sub"},
+{"SUB_ZZZ_S", "sub"},
+{"SUBv1i64", "sub"},
+{"SUBv2i32", "sub"},
+{"SUBv2i64", "sub"},
+{"SUBv4i16", "sub"},
+{"SUBv4i32", "sub"},
+{"SUBv8i8", "sub"},
+{"SUBv8i16", "sub"},
+{"SUBv16i8", "sub"},
+{"SUDOT_VG2_M2ZZI_BToS", "sudot"},
+{"SUDOT_VG2_M2ZZ_BToS", "sudot"},
+{"SUDOT_VG4_M4ZZI_BToS", "sudot"},
+{"SUDOT_VG4_M4ZZ_BToS", "sudot"},
+{"SUDOT_ZZZI", "sudot"},
+{"SUDOTlanev8i8", "sudot"},
+{"SUDOTlanev16i8", "sudot"},
+{"SUMLALL_MZZI_BtoS", "sumlall"},
+{"SUMLALL_VG2_M2ZZI_BtoS", "sumlall"},
+{"SUMLALL_VG2_M2ZZ_BtoS", "sumlall"},
+{"SUMLALL_VG4_M4ZZI_BtoS", "sumlall"},
+{"SUMLALL_VG4_M4ZZ_BtoS", "sumlall"},
+{"SUMOP4A_M2Z2Z_BToS", "sumop4a"},
+{"SUMOP4A_M2Z2Z_HtoD", "sumop4a"},
+{"SUMOP4A_M2ZZ_BToS", "sumop4a"},
+{"SUMOP4A_M2ZZ_HtoD", "sumop4a"},
+{"SUMOP4A_MZ2Z_BToS", "sumop4a"},
+{"SUMOP4A_MZ2Z_HtoD", "sumop4a"},
+{"SUMOP4A_MZZ_BToS", "sumop4a"},
+{"SUMOP4A_MZZ_HtoD", "sumop4a"},
+{"SUMOP4S_M2Z2Z_BToS", "sumop4s"},
+{"SUMOP4S_M2Z2Z_HtoD", "sumop4s"},
+{"SUMOP4S_M2ZZ_BToS", "sumop4s"},
+{"SUMOP4S_M2ZZ_HtoD", "sumop4s"},
+{"SUMOP4S_MZ2Z_BToS", "sumop4s"},
+{"SUMOP4S_MZ2Z_HtoD", "sumop4s"},
+{"SUMOP4S_MZZ_BToS", "sumop4s"},
+{"SUMOP4S_MZZ_HtoD", "sumop4s"},
+{"SUMOPA_MPPZZ_D", "sumopa"},
+{"SUMOPA_MPPZZ_S", "sumopa"},
+{"SUMOPS_MPPZZ_D", "sumops"},
+{"SUMOPS_MPPZZ_S", "sumops"},
+{"SUNPKHI_ZZ_D", "sunpkhi"},
+{"SUNPKHI_ZZ_H", "sunpkhi"},
+{"SUNPKHI_ZZ_S", "sunpkhi"},
+{"SUNPKLO_ZZ_D", "sunpklo"},
+{"SUNPKLO_ZZ_H", "sunpklo"},
+{"SUNPKLO_ZZ_S", "sunpklo"},
+{"SUNPK_VG2_2ZZ_D", "sunpk"},
+{"SUNPK_VG2_2ZZ_H", "sunpk"},
+{"SUNPK_VG2_2ZZ_S", "sunpk"},
+{"SUNPK_VG4_4Z2Z_D", "sunpk"},
+{"SUNPK_VG4_4Z2Z_H", "sunpk"},
+{"SUNPK_VG4_4Z2Z_S", "sunpk"},
+{"SUQADD_ZPmZ_B", "suqadd"},
+{"SUQADD_ZPmZ_D", "suqadd"},
+{"SUQADD_ZPmZ_H", "suqadd"},
+{"SUQADD_ZPmZ_S", "suqadd"},
+{"SUQADDv1i8", "suqadd"},
+{"SUQADDv1i16", "suqadd"},
+{"SUQADDv1i32", "suqadd"},
+{"SUQADDv1i64", "suqadd"},
+{"SUQADDv2i32", "suqadd"},
+{"SUQADDv2i64", "suqadd"},
+{"SUQADDv4i16", "suqadd"},
+{"SUQADDv4i32", "suqadd"},
+{"SUQADDv8i8", "suqadd"},
+{"SUQADDv8i16", "suqadd"},
+{"SUQADDv16i8", "suqadd"},
+{"SUTMOPA_M2ZZZI_BtoS", "sutmopa"},
+{"SUVDOT_VG4_M4ZZI_BToS", "suvdot"},
+{"SVC", "svc"},
+{"SVDOT_VG2_M2ZZI_HtoS", "svdot"},
+{"SVDOT_VG4_M4ZZI_BtoS", "svdot"},
+{"SVDOT_VG4_M4ZZI_HtoD", "svdot"},
+{"SWPAB", "swpab"},
+{"SWPAH", "swpah"},
+{"SWPALB", "swpalb"},
+{"SWPALH", "swpalh"},
+{"SWPALW", "swpal"},
+{"SWPALX", "swpal"},
+{"SWPAW", "swpa"},
+{"SWPAX", "swpa"},
+{"SWPB", "swpb"},
+{"SWPH", "swph"},
+{"SWPLB", "swplb"},
+{"SWPLH", "swplh"},
+{"SWPLW", "swpl"},
+{"SWPLX", "swpl"},
+{"SWPP", "swpp"},
+{"SWPPA", "swppa"},
+{"SWPPAL", "swppal"},
+{"SWPPL", "swppl"},
+{"SWPTALW", "swptal"},
+{"SWPTALX", "swptal"},
+{"SWPTAW", "swpta"},
+{"SWPTAX", "swpta"},
+{"SWPTLW", "swptl"},
+{"SWPTLX", "swptl"},
+{"SWPTW", "swpt"},
+{"SWPTX", "swpt"},
+{"SWPW", "swp"},
+{"SWPX", "swp"},
+{"SXTB_ZPmZ_D", "sxtb"},
+{"SXTB_ZPmZ_H", "sxtb"},
+{"SXTB_ZPmZ_S", "sxtb"},
+{"SXTB_ZPzZ_D", "sxtb"},
+{"SXTB_ZPzZ_H", "sxtb"},
+{"SXTB_ZPzZ_S", "sxtb"},
+{"SXTH_ZPmZ_D", "sxth"},
+{"SXTH_ZPmZ_S", "sxth"},
+{"SXTH_ZPzZ_D", "sxth"},
+{"SXTH_ZPzZ_S", "sxth"},
+{"SXTW_ZPmZ_D", "sxtw"},
+{"SXTW_ZPzZ_D", "sxtw"},
+{"SYSLxt", "sysl"},
+{"SYSPxt", "sysp"},
+{"SYSPxt_XZR", "sysp"},
+{"SYSxt", "sys"},
+{"TBLQ_ZZZ_B", "tblq"},
+{"TBLQ_ZZZ_D", "tblq"},
+{"TBLQ_ZZZ_H", "tblq"},
+{"TBLQ_ZZZ_S", "tblq"},
+{"TBL_ZZZZ_B", "tbl"},
+{"TBL_ZZZZ_D", "tbl"},
+{"TBL_ZZZZ_H", "tbl"},
+{"TBL_ZZZZ_S", "tbl"},
+{"TBL_ZZZ_B", "tbl"},
+{"TBL_ZZZ_D", "tbl"},
+{"TBL_ZZZ_H", "tbl"},
+{"TBL_ZZZ_S", "tbl"},
+{"TBLv8i8Four", "tbl"},
+{"TBLv8i8One", "tbl"},
+{"TBLv8i8Three", "tbl"},
+{"TBLv8i8Two", "tbl"},
+{"TBLv16i8Four", "tbl"},
+{"TBLv16i8One", "tbl"},
+{"TBLv16i8Three", "tbl"},
+{"TBLv16i8Two", "tbl"},
+{"TBNZW", "tbnz"},
+{"TBNZX", "tbnz"},
+{"TBXQ_ZZZ_B", "tbxq"},
+{"TBXQ_ZZZ_D", "tbxq"},
+{"TBXQ_ZZZ_H", "tbxq"},
+{"TBXQ_ZZZ_S", "tbxq"},
+{"TBX_ZZZ_B", "tbx"},
+{"TBX_ZZZ_D", "tbx"},
+{"TBX_ZZZ_H", "tbx"},
+{"TBX_ZZZ_S", "tbx"},
+{"TBXv8i8Four", "tbx"},
+{"TBXv8i8One", "tbx"},
+{"TBXv8i8Three", "tbx"},
+{"TBXv8i8Two", "tbx"},
+{"TBXv16i8Four", "tbx"},
+{"TBXv16i8One", "tbx"},
+{"TBXv16i8Three", "tbx"},
+{"TBXv16i8Two", "tbx"},
+{"TBZW", "tbz"},
+{"TBZX", "tbz"},
+{"TCHANGEBri", "tchangeb"},
+{"TCHANGEBrr", "tchangeb"},
+{"TCHANGEFri", "tchangef"},
+{"TCHANGEFrr", "tchangef"},
+{"TENTER", "tenter"},
+{"TEXIT", "texit"},
+{"TRN1_PPP_B", "trn1"},
+{"TRN1_PPP_D", "trn1"},
+{"TRN1_PPP_H", "trn1"},
+{"TRN1_PPP_S", "trn1"},
+{"TRN1_ZZZ_B", "trn1"},
+{"TRN1_ZZZ_D", "trn1"},
+{"TRN1_ZZZ_H", "trn1"},
+{"TRN1_ZZZ_Q", "trn1"},
+{"TRN1_ZZZ_S", "trn1"},
+{"TRN1v2i32", "trn1"},
+{"TRN1v2i64", "trn1"},
+{"TRN1v4i16", "trn1"},
+{"TRN1v4i32", "trn1"},
+{"TRN1v8i8", "trn1"},
+{"TRN1v8i16", "trn1"},
+{"TRN1v16i8", "trn1"},
+{"TRN2_PPP_B", "trn2"},
+{"TRN2_PPP_D", "trn2"},
+{"TRN2_PPP_H", "trn2"},
+{"TRN2_PPP_S", "trn2"},
+{"TRN2_ZZZ_B", "trn2"},
+{"TRN2_ZZZ_D", "trn2"},
+{"TRN2_ZZZ_H", "trn2"},
+{"TRN2_ZZZ_Q", "trn2"},
+{"TRN2_ZZZ_S", "trn2"},
+{"TRN2v2i32", "trn2"},
+{"TRN2v2i64", "trn2"},
+{"TRN2v4i16", "trn2"},
+{"TRN2v4i32", "trn2"},
+{"TRN2v8i8", "trn2"},
+{"TRN2v8i16", "trn2"},
+{"TRN2v16i8", "trn2"},
+{"UABALB_ZZZ_D", "uabalb"},
+{"UABALB_ZZZ_H", "uabalb"},
+{"UABALB_ZZZ_S", "uabalb"},
+{"UABALT_ZZZ_D", "uabalt"},
+{"UABALT_ZZZ_H", "uabalt"},
+{"UABALT_ZZZ_S", "uabalt"},
+{"UABAL_ZZZ_BtoH", "uabal"},
+{"UABAL_ZZZ_HtoS", "uabal"},
+{"UABAL_ZZZ_StoD", "uabal"},
+{"UABALv2i32_v2i64", "uabal"},
+{"UABALv4i16_v4i32", "uabal"},
+{"UABALv8i8_v8i16", "uabal"},
+{"UABALv4i32_v2i64", "uabal2"},
+{"UABALv8i16_v4i32", "uabal2"},
+{"UABALv16i8_v8i16", "uabal2"},
+{"UABA_ZZZ_B", "uaba"},
+{"UABA_ZZZ_D", "uaba"},
+{"UABA_ZZZ_H", "uaba"},
+{"UABA_ZZZ_S", "uaba"},
+{"UABAv2i32", "uaba"},
+{"UABAv4i16", "uaba"},
+{"UABAv4i32", "uaba"},
+{"UABAv8i8", "uaba"},
+{"UABAv8i16", "uaba"},
+{"UABAv16i8", "uaba"},
+{"UABDLB_ZZZ_D", "uabdlb"},
+{"UABDLB_ZZZ_H", "uabdlb"},
+{"UABDLB_ZZZ_S", "uabdlb"},
+{"UABDLT_ZZZ_D", "uabdlt"},
+{"UABDLT_ZZZ_H", "uabdlt"},
+{"UABDLT_ZZZ_S", "uabdlt"},
+{"UABDLv2i32_v2i64", "uabdl"},
+{"UABDLv4i16_v4i32", "uabdl"},
+{"UABDLv8i8_v8i16", "uabdl"},
+{"UABDLv4i32_v2i64", "uabdl2"},
+{"UABDLv8i16_v4i32", "uabdl2"},
+{"UABDLv16i8_v8i16", "uabdl2"},
+{"UABD_ZPmZ_B", "uabd"},
+{"UABD_ZPmZ_D", "uabd"},
+{"UABD_ZPmZ_H", "uabd"},
+{"UABD_ZPmZ_S", "uabd"},
+{"UABDv2i32", "uabd"},
+{"UABDv4i16", "uabd"},
+{"UABDv4i32", "uabd"},
+{"UABDv8i8", "uabd"},
+{"UABDv8i16", "uabd"},
+{"UABDv16i8", "uabd"},
+{"UADALP_ZPmZ_D", "uadalp"},
+{"UADALP_ZPmZ_H", "uadalp"},
+{"UADALP_ZPmZ_S", "uadalp"},
+{"UADALPv2i32_v1i64", "uadalp"},
+{"UADALPv4i16_v2i32", "uadalp"},
+{"UADALPv4i32_v2i64", "uadalp"},
+{"UADALPv8i8_v4i16", "uadalp"},
+{"UADALPv8i16_v4i32", "uadalp"},
+{"UADALPv16i8_v8i16", "uadalp"},
+{"UADDLB_ZZZ_D", "uaddlb"},
+{"UADDLB_ZZZ_H", "uaddlb"},
+{"UADDLB_ZZZ_S", "uaddlb"},
+{"UADDLPv2i32_v1i64", "uaddlp"},
+{"UADDLPv4i16_v2i32", "uaddlp"},
+{"UADDLPv4i32_v2i64", "uaddlp"},
+{"UADDLPv8i8_v4i16", "uaddlp"},
+{"UADDLPv8i16_v4i32", "uaddlp"},
+{"UADDLPv16i8_v8i16", "uaddlp"},
+{"UADDLT_ZZZ_D", "uaddlt"},
+{"UADDLT_ZZZ_H", "uaddlt"},
+{"UADDLT_ZZZ_S", "uaddlt"},
+{"UADDLVv4i16v", "uaddlv"},
+{"UADDLVv4i32v", "uaddlv"},
+{"UADDLVv8i8v", "uaddlv"},
+{"UADDLVv8i16v", "uaddlv"},
+{"UADDLVv16i8v", "uaddlv"},
+{"UADDLv2i32_v2i64", "uaddl"},
+{"UADDLv4i16_v4i32", "uaddl"},
+{"UADDLv8i8_v8i16", "uaddl"},
+{"UADDLv4i32_v2i64", "uaddl2"},
+{"UADDLv8i16_v4i32", "uaddl2"},
+{"UADDLv16i8_v8i16", "uaddl2"},
+{"UADDV_VPZ_B", "uaddv"},
+{"UADDV_VPZ_D", "uaddv"},
+{"UADDV_VPZ_H", "uaddv"},
+{"UADDV_VPZ_S", "uaddv"},
+{"UADDWB_ZZZ_D", "uaddwb"},
+{"UADDWB_ZZZ_H", "uaddwb"},
+{"UADDWB_ZZZ_S", "uaddwb"},
+{"UADDWT_ZZZ_D", "uaddwt"},
+{"UADDWT_ZZZ_H", "uaddwt"},
+{"UADDWT_ZZZ_S", "uaddwt"},
+{"UADDWv2i32_v2i64", "uaddw"},
+{"UADDWv4i16_v4i32", "uaddw"},
+{"UADDWv8i8_v8i16", "uaddw"},
+{"UADDWv4i32_v2i64", "uaddw2"},
+{"UADDWv8i16_v4i32", "uaddw2"},
+{"UADDWv16i8_v8i16", "uaddw2"},
+{"UBFMWri", "ubfm"},
+{"UBFMXri", "ubfm"},
+{"UCLAMP_VG2_2Z2Z_B", "uclamp"},
+{"UCLAMP_VG2_2Z2Z_D", "uclamp"},
+{"UCLAMP_VG2_2Z2Z_H", "uclamp"},
+{"UCLAMP_VG2_2Z2Z_S", "uclamp"},
+{"UCLAMP_VG4_4Z4Z_B", "uclamp"},
+{"UCLAMP_VG4_4Z4Z_D", "uclamp"},
+{"UCLAMP_VG4_4Z4Z_H", "uclamp"},
+{"UCLAMP_VG4_4Z4Z_S", "uclamp"},
+{"UCLAMP_ZZZ_B", "uclamp"},
+{"UCLAMP_ZZZ_D", "uclamp"},
+{"UCLAMP_ZZZ_H", "uclamp"},
+{"UCLAMP_ZZZ_S", "uclamp"},
+{"UCVTFDSr", "ucvtf"},
+{"UCVTFHDr", "ucvtf"},
+{"UCVTFHSr", "ucvtf"},
+{"UCVTFSDr", "ucvtf"},
+{"UCVTFSWDri", "ucvtf"},
+{"UCVTFSWHri", "ucvtf"},
+{"UCVTFSWSri", "ucvtf"},
+{"UCVTFSXDri", "ucvtf"},
+{"UCVTFSXHri", "ucvtf"},
+{"UCVTFSXSri", "ucvtf"},
+{"UCVTFUWDri", "ucvtf"},
+{"UCVTFUWHri", "ucvtf"},
+{"UCVTFUWSri", "ucvtf"},
+{"UCVTFUXDri", "ucvtf"},
+{"UCVTFUXHri", "ucvtf"},
+{"UCVTFUXSri", "ucvtf"},
+{"UCVTF_2Z2Z_StoS", "ucvtf"},
+{"UCVTF_4Z4Z_StoS", "ucvtf"},
+{"UCVTF_ZPmZ_DtoD", "ucvtf"},
+{"UCVTF_ZPmZ_DtoH", "ucvtf"},
+{"UCVTF_ZPmZ_DtoS", "ucvtf"},
+{"UCVTF_ZPmZ_HtoH", "ucvtf"},
+{"UCVTF_ZPmZ_StoD", "ucvtf"},
+{"UCVTF_ZPmZ_StoH", "ucvtf"},
+{"UCVTF_ZPmZ_StoS", "ucvtf"},
+{"UCVTF_ZPzZ_DtoD", "ucvtf"},
+{"UCVTF_ZPzZ_DtoH", "ucvtf"},
+{"UCVTF_ZPzZ_DtoS", "ucvtf"},
+{"UCVTF_ZPzZ_HtoH", "ucvtf"},
+{"UCVTF_ZPzZ_StoD", "ucvtf"},
+{"UCVTF_ZPzZ_StoH", "ucvtf"},
+{"UCVTF_ZPzZ_StoS", "ucvtf"},
+{"UCVTF_ZZ_BtoH", "ucvtf"},
+{"UCVTF_ZZ_HtoS", "ucvtf"},
+{"UCVTF_ZZ_StoD", "ucvtf"},
+{"UCVTFd", "ucvtf"},
+{"UCVTFh", "ucvtf"},
+{"UCVTFs", "ucvtf"},
+{"UCVTFv1i16", "ucvtf"},
+{"UCVTFv1i32", "ucvtf"},
+{"UCVTFv1i64", "ucvtf"},
+{"UCVTFv2f32", "ucvtf"},
+{"UCVTFv2f64", "ucvtf"},
+{"UCVTFv2i32_shift", "ucvtf"},
+{"UCVTFv2i64_shift", "ucvtf"},
+{"UCVTFv4f16", "ucvtf"},
+{"UCVTFv4f32", "ucvtf"},
+{"UCVTFv4i16_shift", "ucvtf"},
+{"UCVTFv4i32_shift", "ucvtf"},
+{"UCVTFv8f16", "ucvtf"},
+{"UCVTFv8i16_shift", "ucvtf"},
+{"UCVTFLT_ZZ_BtoH", "ucvtflt"},
+{"UCVTFLT_ZZ_HtoS", "ucvtflt"},
+{"UCVTFLT_ZZ_StoD", "ucvtflt"},
+{"UDF", "udf"},
+{"UDIVR_ZPmZ_D", "udivr"},
+{"UDIVR_ZPmZ_S", "udivr"},
+{"UDIVWr", "udiv"},
+{"UDIVXr", "udiv"},
+{"UDIV_ZPmZ_D", "udiv"},
+{"UDIV_ZPmZ_S", "udiv"},
+{"UDOT_VG2_M2Z2Z_BtoS", "udot"},
+{"UDOT_VG2_M2Z2Z_HtoD", "udot"},
+{"UDOT_VG2_M2Z2Z_HtoS", "udot"},
+{"UDOT_VG2_M2ZZI_BToS", "udot"},
+{"UDOT_VG2_M2ZZI_HToS", "udot"},
+{"UDOT_VG2_M2ZZI_HtoD", "udot"},
+{"UDOT_VG2_M2ZZ_BtoS", "udot"},
+{"UDOT_VG2_M2ZZ_HtoD", "udot"},
+{"UDOT_VG2_M2ZZ_HtoS", "udot"},
+{"UDOT_VG4_M4Z4Z_BtoS", "udot"},
+{"UDOT_VG4_M4Z4Z_HtoD", "udot"},
+{"UDOT_VG4_M4Z4Z_HtoS", "udot"},
+{"UDOT_VG4_M4ZZI_BtoS", "udot"},
+{"UDOT_VG4_M4ZZI_HToS", "udot"},
+{"UDOT_VG4_M4ZZI_HtoD", "udot"},
+{"UDOT_VG4_M4ZZ_BtoS", "udot"},
+{"UDOT_VG4_M4ZZ_HtoD", "udot"},
+{"UDOT_VG4_M4ZZ_HtoS", "udot"},
+{"UDOT_ZZZI_BtoH", "udot"},
+{"UDOT_ZZZI_BtoS", "udot"},
+{"UDOT_ZZZI_HtoD", "udot"},
+{"UDOT_ZZZI_HtoS", "udot"},
+{"UDOT_ZZZ_BtoH", "udot"},
+{"UDOT_ZZZ_BtoS", "udot"},
+{"UDOT_ZZZ_HtoD", "udot"},
+{"UDOT_ZZZ_HtoS", "udot"},
+{"UDOTlanev8i8", "udot"},
+{"UDOTlanev16i8", "udot"},
+{"UDOTv8i8", "udot"},
+{"UDOTv16i8", "udot"},
+{"UHADD_ZPmZ_B", "uhadd"},
+{"UHADD_ZPmZ_D", "uhadd"},
+{"UHADD_ZPmZ_H", "uhadd"},
+{"UHADD_ZPmZ_S", "uhadd"},
+{"UHADDv2i32", "uhadd"},
+{"UHADDv4i16", "uhadd"},
+{"UHADDv4i32", "uhadd"},
+{"UHADDv8i8", "uhadd"},
+{"UHADDv8i16", "uhadd"},
+{"UHADDv16i8", "uhadd"},
+{"UHSUBR_ZPmZ_B", "uhsubr"},
+{"UHSUBR_ZPmZ_D", "uhsubr"},
+{"UHSUBR_ZPmZ_H", "uhsubr"},
+{"UHSUBR_ZPmZ_S", "uhsubr"},
+{"UHSUB_ZPmZ_B", "uhsub"},
+{"UHSUB_ZPmZ_D", "uhsub"},
+{"UHSUB_ZPmZ_H", "uhsub"},
+{"UHSUB_ZPmZ_S", "uhsub"},
+{"UHSUBv2i32", "uhsub"},
+{"UHSUBv4i16", "uhsub"},
+{"UHSUBv4i32", "uhsub"},
+{"UHSUBv8i8", "uhsub"},
+{"UHSUBv8i16", "uhsub"},
+{"UHSUBv16i8", "uhsub"},
+{"UMADDLrrr", "umaddl"},
+{"UMAXP_ZPmZ_B", "umaxp"},
+{"UMAXP_ZPmZ_D", "umaxp"},
+{"UMAXP_ZPmZ_H", "umaxp"},
+{"UMAXP_ZPmZ_S", "umaxp"},
+{"UMAXPv2i32", "umaxp"},
+{"UMAXPv4i16", "umaxp"},
+{"UMAXPv4i32", "umaxp"},
+{"UMAXPv8i8", "umaxp"},
+{"UMAXPv8i16", "umaxp"},
+{"UMAXPv16i8", "umaxp"},
+{"UMAXQV_VPZ_B", "umaxqv"},
+{"UMAXQV_VPZ_D", "umaxqv"},
+{"UMAXQV_VPZ_H", "umaxqv"},
+{"UMAXQV_VPZ_S", "umaxqv"},
+{"UMAXV_VPZ_B", "umaxv"},
+{"UMAXV_VPZ_D", "umaxv"},
+{"UMAXV_VPZ_H", "umaxv"},
+{"UMAXV_VPZ_S", "umaxv"},
+{"UMAXVv4i16v", "umaxv"},
+{"UMAXVv4i32v", "umaxv"},
+{"UMAXVv8i8v", "umaxv"},
+{"UMAXVv8i16v", "umaxv"},
+{"UMAXVv16i8v", "umaxv"},
+{"UMAXWri", "umax"},
+{"UMAXWrr", "umax"},
+{"UMAXXri", "umax"},
+{"UMAXXrr", "umax"},
+{"UMAX_VG2_2Z2Z_B", "umax"},
+{"UMAX_VG2_2Z2Z_D", "umax"},
+{"UMAX_VG2_2Z2Z_H", "umax"},
+{"UMAX_VG2_2Z2Z_S", "umax"},
+{"UMAX_VG2_2ZZ_B", "umax"},
+{"UMAX_VG2_2ZZ_D", "umax"},
+{"UMAX_VG2_2ZZ_H", "umax"},
+{"UMAX_VG2_2ZZ_S", "umax"},
+{"UMAX_VG4_4Z4Z_B", "umax"},
+{"UMAX_VG4_4Z4Z_D", "umax"},
+{"UMAX_VG4_4Z4Z_H", "umax"},
+{"UMAX_VG4_4Z4Z_S", "umax"},
+{"UMAX_VG4_4ZZ_B", "umax"},
+{"UMAX_VG4_4ZZ_D", "umax"},
+{"UMAX_VG4_4ZZ_H", "umax"},
+{"UMAX_VG4_4ZZ_S", "umax"},
+{"UMAX_ZI_B", "umax"},
+{"UMAX_ZI_D", "umax"},
+{"UMAX_ZI_H", "umax"},
+{"UMAX_ZI_S", "umax"},
+{"UMAX_ZPmZ_B", "umax"},
+{"UMAX_ZPmZ_D", "umax"},
+{"UMAX_ZPmZ_H", "umax"},
+{"UMAX_ZPmZ_S", "umax"},
+{"UMAXv2i32", "umax"},
+{"UMAXv4i16", "umax"},
+{"UMAXv4i32", "umax"},
+{"UMAXv8i8", "umax"},
+{"UMAXv8i16", "umax"},
+{"UMAXv16i8", "umax"},
+{"UMINP_ZPmZ_B", "uminp"},
+{"UMINP_ZPmZ_D", "uminp"},
+{"UMINP_ZPmZ_H", "uminp"},
+{"UMINP_ZPmZ_S", "uminp"},
+{"UMINPv2i32", "uminp"},
+{"UMINPv4i16", "uminp"},
+{"UMINPv4i32", "uminp"},
+{"UMINPv8i8", "uminp"},
+{"UMINPv8i16", "uminp"},
+{"UMINPv16i8", "uminp"},
+{"UMINQV_VPZ_B", "uminqv"},
+{"UMINQV_VPZ_D", "uminqv"},
+{"UMINQV_VPZ_H", "uminqv"},
+{"UMINQV_VPZ_S", "uminqv"},
+{"UMINV_VPZ_B", "uminv"},
+{"UMINV_VPZ_D", "uminv"},
+{"UMINV_VPZ_H", "uminv"},
+{"UMINV_VPZ_S", "uminv"},
+{"UMINVv4i16v", "uminv"},
+{"UMINVv4i32v", "uminv"},
+{"UMINVv8i8v", "uminv"},
+{"UMINVv8i16v", "uminv"},
+{"UMINVv16i8v", "uminv"},
+{"UMINWri", "umin"},
+{"UMINWrr", "umin"},
+{"UMINXri", "umin"},
+{"UMINXrr", "umin"},
+{"UMIN_VG2_2Z2Z_B", "umin"},
+{"UMIN_VG2_2Z2Z_D", "umin"},
+{"UMIN_VG2_2Z2Z_H", "umin"},
+{"UMIN_VG2_2Z2Z_S", "umin"},
+{"UMIN_VG2_2ZZ_B", "umin"},
+{"UMIN_VG2_2ZZ_D", "umin"},
+{"UMIN_VG2_2ZZ_H", "umin"},
+{"UMIN_VG2_2ZZ_S", "umin"},
+{"UMIN_VG4_4Z4Z_B", "umin"},
+{"UMIN_VG4_4Z4Z_D", "umin"},
+{"UMIN_VG4_4Z4Z_H", "umin"},
+{"UMIN_VG4_4Z4Z_S", "umin"},
+{"UMIN_VG4_4ZZ_B", "umin"},
+{"UMIN_VG4_4ZZ_D", "umin"},
+{"UMIN_VG4_4ZZ_H", "umin"},
+{"UMIN_VG4_4ZZ_S", "umin"},
+{"UMIN_ZI_B", "umin"},
+{"UMIN_ZI_D", "umin"},
+{"UMIN_ZI_H", "umin"},
+{"UMIN_ZI_S", "umin"},
+{"UMIN_ZPmZ_B", "umin"},
+{"UMIN_ZPmZ_D", "umin"},
+{"UMIN_ZPmZ_H", "umin"},
+{"UMIN_ZPmZ_S", "umin"},
+{"UMINv2i32", "umin"},
+{"UMINv4i16", "umin"},
+{"UMINv4i32", "umin"},
+{"UMINv8i8", "umin"},
+{"UMINv8i16", "umin"},
+{"UMINv16i8", "umin"},
+{"UMLALB_ZZZI_D", "umlalb"},
+{"UMLALB_ZZZI_S", "umlalb"},
+{"UMLALB_ZZZ_D", "umlalb"},
+{"UMLALB_ZZZ_H", "umlalb"},
+{"UMLALB_ZZZ_S", "umlalb"},
+{"UMLALL_MZZI_BtoS", "umlall"},
+{"UMLALL_MZZI_HtoD", "umlall"},
+{"UMLALL_MZZ_BtoS", "umlall"},
+{"UMLALL_MZZ_HtoD", "umlall"},
+{"UMLALL_VG2_M2Z2Z_BtoS", "umlall"},
+{"UMLALL_VG2_M2Z2Z_HtoD", "umlall"},
+{"UMLALL_VG2_M2ZZI_BtoS", "umlall"},
+{"UMLALL_VG2_M2ZZI_HtoD", "umlall"},
+{"UMLALL_VG2_M2ZZ_BtoS", "umlall"},
+{"UMLALL_VG2_M2ZZ_HtoD", "umlall"},
+{"UMLALL_VG4_M4Z4Z_BtoS", "umlall"},
+{"UMLALL_VG4_M4Z4Z_HtoD", "umlall"},
+{"UMLALL_VG4_M4ZZI_BtoS", "umlall"},
+{"UMLALL_VG4_M4ZZI_HtoD", "umlall"},
+{"UMLALL_VG4_M4ZZ_BtoS", "umlall"},
+{"UMLALL_VG4_M4ZZ_HtoD", "umlall"},
+{"UMLALT_ZZZI_D", "umlalt"},
+{"UMLALT_ZZZI_S", "umlalt"},
+{"UMLALT_ZZZ_D", "umlalt"},
+{"UMLALT_ZZZ_H", "umlalt"},
+{"UMLALT_ZZZ_S", "umlalt"},
+{"UMLAL_MZZI_HtoS", "umlal"},
+{"UMLAL_MZZ_HtoS", "umlal"},
+{"UMLAL_VG2_M2Z2Z_HtoS", "umlal"},
+{"UMLAL_VG2_M2ZZI_S", "umlal"},
+{"UMLAL_VG2_M2ZZ_HtoS", "umlal"},
+{"UMLAL_VG4_M4Z4Z_HtoS", "umlal"},
+{"UMLAL_VG4_M4ZZI_HtoS", "umlal"},
+{"UMLAL_VG4_M4ZZ_HtoS", "umlal"},
+{"UMLALv2i32_indexed", "umlal"},
+{"UMLALv2i32_v2i64", "umlal"},
+{"UMLALv4i16_indexed", "umlal"},
+{"UMLALv4i16_v4i32", "umlal"},
+{"UMLALv8i8_v8i16", "umlal"},
+{"UMLALv4i32_indexed", "umlal2"},
+{"UMLALv4i32_v2i64", "umlal2"},
+{"UMLALv8i16_indexed", "umlal2"},
+{"UMLALv8i16_v4i32", "umlal2"},
+{"UMLALv16i8_v8i16", "umlal2"},
+{"UMLSLB_ZZZI_D", "umlslb"},
+{"UMLSLB_ZZZI_S", "umlslb"},
+{"UMLSLB_ZZZ_D", "umlslb"},
+{"UMLSLB_ZZZ_H", "umlslb"},
+{"UMLSLB_ZZZ_S", "umlslb"},
+{"UMLSLL_MZZI_BtoS", "umlsll"},
+{"UMLSLL_MZZI_HtoD", "umlsll"},
+{"UMLSLL_MZZ_BtoS", "umlsll"},
+{"UMLSLL_MZZ_HtoD", "umlsll"},
+{"UMLSLL_VG2_M2Z2Z_BtoS", "umlsll"},
+{"UMLSLL_VG2_M2Z2Z_HtoD", "umlsll"},
+{"UMLSLL_VG2_M2ZZI_BtoS", "umlsll"},
+{"UMLSLL_VG2_M2ZZI_HtoD", "umlsll"},
+{"UMLSLL_VG2_M2ZZ_BtoS", "umlsll"},
+{"UMLSLL_VG2_M2ZZ_HtoD", "umlsll"},
+{"UMLSLL_VG4_M4Z4Z_BtoS", "umlsll"},
+{"UMLSLL_VG4_M4Z4Z_HtoD", "umlsll"},
+{"UMLSLL_VG4_M4ZZI_BtoS", "umlsll"},
+{"UMLSLL_VG4_M4ZZI_HtoD", "umlsll"},
+{"UMLSLL_VG4_M4ZZ_BtoS", "umlsll"},
+{"UMLSLL_VG4_M4ZZ_HtoD", "umlsll"},
+{"UMLSLT_ZZZI_D", "umlslt"},
+{"UMLSLT_ZZZI_S", "umlslt"},
+{"UMLSLT_ZZZ_D", "umlslt"},
+{"UMLSLT_ZZZ_H", "umlslt"},
+{"UMLSLT_ZZZ_S", "umlslt"},
+{"UMLSL_MZZI_HtoS", "umlsl"},
+{"UMLSL_MZZ_HtoS", "umlsl"},
+{"UMLSL_VG2_M2Z2Z_HtoS", "umlsl"},
+{"UMLSL_VG2_M2ZZI_S", "umlsl"},
+{"UMLSL_VG2_M2ZZ_HtoS", "umlsl"},
+{"UMLSL_VG4_M4Z4Z_HtoS", "umlsl"},
+{"UMLSL_VG4_M4ZZI_HtoS", "umlsl"},
+{"UMLSL_VG4_M4ZZ_HtoS", "umlsl"},
+{"UMLSLv2i32_indexed", "umlsl"},
+{"UMLSLv2i32_v2i64", "umlsl"},
+{"UMLSLv4i16_indexed", "umlsl"},
+{"UMLSLv4i16_v4i32", "umlsl"},
+{"UMLSLv8i8_v8i16", "umlsl"},
+{"UMLSLv4i32_indexed", "umlsl2"},
+{"UMLSLv4i32_v2i64", "umlsl2"},
+{"UMLSLv8i16_indexed", "umlsl2"},
+{"UMLSLv8i16_v4i32", "umlsl2"},
+{"UMLSLv16i8_v8i16", "umlsl2"},
+{"UMMLA", "ummla"},
+{"UMMLA_ZZZ", "ummla"},
+{"UMOP4A_M2Z2Z_BToS", "umop4a"},
+{"UMOP4A_M2Z2Z_HToS", "umop4a"},
+{"UMOP4A_M2Z2Z_HtoD", "umop4a"},
+{"UMOP4A_M2ZZ_BToS", "umop4a"},
+{"UMOP4A_M2ZZ_HToS", "umop4a"},
+{"UMOP4A_M2ZZ_HtoD", "umop4a"},
+{"UMOP4A_MZ2Z_BToS", "umop4a"},
+{"UMOP4A_MZ2Z_HToS", "umop4a"},
+{"UMOP4A_MZ2Z_HtoD", "umop4a"},
+{"UMOP4A_MZZ_BToS", "umop4a"},
+{"UMOP4A_MZZ_HToS", "umop4a"},
+{"UMOP4A_MZZ_HtoD", "umop4a"},
+{"UMOP4S_M2Z2Z_BToS", "umop4s"},
+{"UMOP4S_M2Z2Z_HToS", "umop4s"},
+{"UMOP4S_M2Z2Z_HtoD", "umop4s"},
+{"UMOP4S_M2ZZ_BToS", "umop4s"},
+{"UMOP4S_M2ZZ_HToS", "umop4s"},
+{"UMOP4S_M2ZZ_HtoD", "umop4s"},
+{"UMOP4S_MZ2Z_BToS", "umop4s"},
+{"UMOP4S_MZ2Z_HToS", "umop4s"},
+{"UMOP4S_MZ2Z_HtoD", "umop4s"},
+{"UMOP4S_MZZ_BToS", "umop4s"},
+{"UMOP4S_MZZ_HToS", "umop4s"},
+{"UMOP4S_MZZ_HtoD", "umop4s"},
+{"UMOPA_MPPZZ_D", "umopa"},
+{"UMOPA_MPPZZ_HtoS", "umopa"},
+{"UMOPA_MPPZZ_S", "umopa"},
+{"UMOPS_MPPZZ_D", "umops"},
+{"UMOPS_MPPZZ_HtoS", "umops"},
+{"UMOPS_MPPZZ_S", "umops"},
+{"UMOVvi8", "umov"},
+{"UMOVvi8_idx0", "umov"},
+{"UMOVvi16", "umov"},
+{"UMOVvi16_idx0", "umov"},
+{"UMOVvi32", "umov"},
+{"UMOVvi32_idx0", "umov"},
+{"UMOVvi64", "umov"},
+{"UMOVvi64_idx0", "umov"},
+{"UMSUBLrrr", "umsubl"},
+{"UMULH_ZPmZ_B", "umulh"},
+{"UMULH_ZPmZ_D", "umulh"},
+{"UMULH_ZPmZ_H", "umulh"},
+{"UMULH_ZPmZ_S", "umulh"},
+{"UMULH_ZZZ_B", "umulh"},
+{"UMULH_ZZZ_D", "umulh"},
+{"UMULH_ZZZ_H", "umulh"},
+{"UMULH_ZZZ_S", "umulh"},
+{"UMULHrr", "umulh"},
+{"UMULLB_ZZZI_D", "umullb"},
+{"UMULLB_ZZZI_S", "umullb"},
+{"UMULLB_ZZZ_D", "umullb"},
+{"UMULLB_ZZZ_H", "umullb"},
+{"UMULLB_ZZZ_S", "umullb"},
+{"UMULLT_ZZZI_D", "umullt"},
+{"UMULLT_ZZZI_S", "umullt"},
+{"UMULLT_ZZZ_D", "umullt"},
+{"UMULLT_ZZZ_H", "umullt"},
+{"UMULLT_ZZZ_S", "umullt"},
+{"UMULLv2i32_indexed", "umull"},
+{"UMULLv2i32_v2i64", "umull"},
+{"UMULLv4i16_indexed", "umull"},
+{"UMULLv4i16_v4i32", "umull"},
+{"UMULLv8i8_v8i16", "umull"},
+{"UMULLv4i32_indexed", "umull2"},
+{"UMULLv4i32_v2i64", "umull2"},
+{"UMULLv8i16_indexed", "umull2"},
+{"UMULLv8i16_v4i32", "umull2"},
+{"UMULLv16i8_v8i16", "umull2"},
+{"UQADD_ZI_B", "uqadd"},
+{"UQADD_ZI_D", "uqadd"},
+{"UQADD_ZI_H", "uqadd"},
+{"UQADD_ZI_S", "uqadd"},
+{"UQADD_ZPmZ_B", "uqadd"},
+{"UQADD_ZPmZ_D", "uqadd"},
+{"UQADD_ZPmZ_H", "uqadd"},
+{"UQADD_ZPmZ_S", "uqadd"},
+{"UQADD_ZZZ_B", "uqadd"},
+{"UQADD_ZZZ_D", "uqadd"},
+{"UQADD_ZZZ_H", "uqadd"},
+{"UQADD_ZZZ_S", "uqadd"},
+{"UQADDv1i8", "uqadd"},
+{"UQADDv1i16", "uqadd"},
+{"UQADDv1i32", "uqadd"},
+{"UQADDv1i64", "uqadd"},
+{"UQADDv2i32", "uqadd"},
+{"UQADDv2i64", "uqadd"},
+{"UQADDv4i16", "uqadd"},
+{"UQADDv4i32", "uqadd"},
+{"UQADDv8i8", "uqadd"},
+{"UQADDv8i16", "uqadd"},
+{"UQADDv16i8", "uqadd"},
+{"UQCVTN_Z2Z_StoH", "uqcvtn"},
+{"UQCVTN_Z4Z_DtoH", "uqcvtn"},
+{"UQCVTN_Z4Z_StoB", "uqcvtn"},
+{"UQCVT_Z2Z_StoH", "uqcvt"},
+{"UQCVT_Z4Z_DtoH", "uqcvt"},
+{"UQCVT_Z4Z_StoB", "uqcvt"},
+{"UQDECB_WPiI", "uqdecb"},
+{"UQDECB_XPiI", "uqdecb"},
+{"UQDECD_WPiI", "uqdecd"},
+{"UQDECD_XPiI", "uqdecd"},
+{"UQDECD_ZPiI", "uqdecd"},
+{"UQDECH_WPiI", "uqdech"},
+{"UQDECH_XPiI", "uqdech"},
+{"UQDECH_ZPiI", "uqdech"},
+{"UQDECP_WP_B", "uqdecp"},
+{"UQDECP_WP_D", "uqdecp"},
+{"UQDECP_WP_H", "uqdecp"},
+{"UQDECP_WP_S", "uqdecp"},
+{"UQDECP_XP_B", "uqdecp"},
+{"UQDECP_XP_D", "uqdecp"},
+{"UQDECP_XP_H", "uqdecp"},
+{"UQDECP_XP_S", "uqdecp"},
+{"UQDECP_ZP_D", "uqdecp"},
+{"UQDECP_ZP_H", "uqdecp"},
+{"UQDECP_ZP_S", "uqdecp"},
+{"UQDECW_WPiI", "uqdecw"},
+{"UQDECW_XPiI", "uqdecw"},
+{"UQDECW_ZPiI", "uqdecw"},
+{"UQINCB_WPiI", "uqincb"},
+{"UQINCB_XPiI", "uqincb"},
+{"UQINCD_WPiI", "uqincd"},
+{"UQINCD_XPiI", "uqincd"},
+{"UQINCD_ZPiI", "uqincd"},
+{"UQINCH_WPiI", "uqinch"},
+{"UQINCH_XPiI", "uqinch"},
+{"UQINCH_ZPiI", "uqinch"},
+{"UQINCP_WP_B", "uqincp"},
+{"UQINCP_WP_D", "uqincp"},
+{"UQINCP_WP_H", "uqincp"},
+{"UQINCP_WP_S", "uqincp"},
+{"UQINCP_XP_B", "uqincp"},
+{"UQINCP_XP_D", "uqincp"},
+{"UQINCP_XP_H", "uqincp"},
+{"UQINCP_XP_S", "uqincp"},
+{"UQINCP_ZP_D", "uqincp"},
+{"UQINCP_ZP_H", "uqincp"},
+{"UQINCP_ZP_S", "uqincp"},
+{"UQINCW_WPiI", "uqincw"},
+{"UQINCW_XPiI", "uqincw"},
+{"UQINCW_ZPiI", "uqincw"},
+{"UQRSHLR_ZPmZ_B", "uqrshlr"},
+{"UQRSHLR_ZPmZ_D", "uqrshlr"},
+{"UQRSHLR_ZPmZ_H", "uqrshlr"},
+{"UQRSHLR_ZPmZ_S", "uqrshlr"},
+{"UQRSHL_ZPmZ_B", "uqrshl"},
+{"UQRSHL_ZPmZ_D", "uqrshl"},
+{"UQRSHL_ZPmZ_H", "uqrshl"},
+{"UQRSHL_ZPmZ_S", "uqrshl"},
+{"UQRSHLv1i8", "uqrshl"},
+{"UQRSHLv1i16", "uqrshl"},
+{"UQRSHLv1i32", "uqrshl"},
+{"UQRSHLv1i64", "uqrshl"},
+{"UQRSHLv2i32", "uqrshl"},
+{"UQRSHLv2i64", "uqrshl"},
+{"UQRSHLv4i16", "uqrshl"},
+{"UQRSHLv4i32", "uqrshl"},
+{"UQRSHLv8i8", "uqrshl"},
+{"UQRSHLv8i16", "uqrshl"},
+{"UQRSHLv16i8", "uqrshl"},
+{"UQRSHRNB_ZZI_B", "uqrshrnb"},
+{"UQRSHRNB_ZZI_H", "uqrshrnb"},
+{"UQRSHRNB_ZZI_S", "uqrshrnb"},
+{"UQRSHRNT_ZZI_B", "uqrshrnt"},
+{"UQRSHRNT_ZZI_H", "uqrshrnt"},
+{"UQRSHRNT_ZZI_S", "uqrshrnt"},
+{"UQRSHRN_VG4_Z4ZI_B", "uqrshrn"},
+{"UQRSHRN_VG4_Z4ZI_H", "uqrshrn"},
+{"UQRSHRN_Z2ZI_HtoB", "uqrshrn"},
+{"UQRSHRN_Z2ZI_StoH", "uqrshrn"},
+{"UQRSHRNb", "uqrshrn"},
+{"UQRSHRNh", "uqrshrn"},
+{"UQRSHRNs", "uqrshrn"},
+{"UQRSHRNv2i32_shift", "uqrshrn"},
+{"UQRSHRNv4i16_shift", "uqrshrn"},
+{"UQRSHRNv8i8_shift", "uqrshrn"},
+{"UQRSHRNv4i32_shift", "uqrshrn2"},
+{"UQRSHRNv8i16_shift", "uqrshrn2"},
+{"UQRSHRNv16i8_shift", "uqrshrn2"},
+{"UQRSHR_VG2_Z2ZI_H", "uqrshr"},
+{"UQRSHR_VG4_Z4ZI_B", "uqrshr"},
+{"UQRSHR_VG4_Z4ZI_H", "uqrshr"},
+{"UQSHLR_ZPmZ_B", "uqshlr"},
+{"UQSHLR_ZPmZ_D", "uqshlr"},
+{"UQSHLR_ZPmZ_H", "uqshlr"},
+{"UQSHLR_ZPmZ_S", "uqshlr"},
+{"UQSHL_ZPmI_B", "uqshl"},
+{"UQSHL_ZPmI_D", "uqshl"},
+{"UQSHL_ZPmI_H", "uqshl"},
+{"UQSHL_ZPmI_S", "uqshl"},
+{"UQSHL_ZPmZ_B", "uqshl"},
+{"UQSHL_ZPmZ_D", "uqshl"},
+{"UQSHL_ZPmZ_H", "uqshl"},
+{"UQSHL_ZPmZ_S", "uqshl"},
+{"UQSHLb", "uqshl"},
+{"UQSHLd", "uqshl"},
+{"UQSHLh", "uqshl"},
+{"UQSHLs", "uqshl"},
+{"UQSHLv1i8", "uqshl"},
+{"UQSHLv1i16", "uqshl"},
+{"UQSHLv1i32", "uqshl"},
+{"UQSHLv1i64", "uqshl"},
+{"UQSHLv2i32", "uqshl"},
+{"UQSHLv2i32_shift", "uqshl"},
+{"UQSHLv2i64", "uqshl"},
+{"UQSHLv2i64_shift", "uqshl"},
+{"UQSHLv4i16", "uqshl"},
+{"UQSHLv4i16_shift", "uqshl"},
+{"UQSHLv4i32", "uqshl"},
+{"UQSHLv4i32_shift", "uqshl"},
+{"UQSHLv8i8", "uqshl"},
+{"UQSHLv8i8_shift", "uqshl"},
+{"UQSHLv8i16", "uqshl"},
+{"UQSHLv8i16_shift", "uqshl"},
+{"UQSHLv16i8", "uqshl"},
+{"UQSHLv16i8_shift", "uqshl"},
+{"UQSHRNB_ZZI_B", "uqshrnb"},
+{"UQSHRNB_ZZI_H", "uqshrnb"},
+{"UQSHRNB_ZZI_S", "uqshrnb"},
+{"UQSHRNT_ZZI_B", "uqshrnt"},
+{"UQSHRNT_ZZI_H", "uqshrnt"},
+{"UQSHRNT_ZZI_S", "uqshrnt"},
+{"UQSHRN_Z2ZI_HtoB", "uqshrn"},
+{"UQSHRN_Z2ZI_StoH", "uqshrn"},
+{"UQSHRNb", "uqshrn"},
+{"UQSHRNh", "uqshrn"},
+{"UQSHRNs", "uqshrn"},
+{"UQSHRNv2i32_shift", "uqshrn"},
+{"UQSHRNv4i16_shift", "uqshrn"},
+{"UQSHRNv8i8_shift", "uqshrn"},
+{"UQSHRNv4i32_shift", "uqshrn2"},
+{"UQSHRNv8i16_shift", "uqshrn2"},
+{"UQSHRNv16i8_shift", "uqshrn2"},
+{"UQSUBR_ZPmZ_B", "uqsubr"},
+{"UQSUBR_ZPmZ_D", "uqsubr"},
+{"UQSUBR_ZPmZ_H", "uqsubr"},
+{"UQSUBR_ZPmZ_S", "uqsubr"},
+{"UQSUB_ZI_B", "uqsub"},
+{"UQSUB_ZI_D", "uqsub"},
+{"UQSUB_ZI_H", "uqsub"},
+{"UQSUB_ZI_S", "uqsub"},
+{"UQSUB_ZPmZ_B", "uqsub"},
+{"UQSUB_ZPmZ_D", "uqsub"},
+{"UQSUB_ZPmZ_H", "uqsub"},
+{"UQSUB_ZPmZ_S", "uqsub"},
+{"UQSUB_ZZZ_B", "uqsub"},
+{"UQSUB_ZZZ_D", "uqsub"},
+{"UQSUB_ZZZ_H", "uqsub"},
+{"UQSUB_ZZZ_S", "uqsub"},
+{"UQSUBv1i8", "uqsub"},
+{"UQSUBv1i16", "uqsub"},
+{"UQSUBv1i32", "uqsub"},
+{"UQSUBv1i64", "uqsub"},
+{"UQSUBv2i32", "uqsub"},
+{"UQSUBv2i64", "uqsub"},
+{"UQSUBv4i16", "uqsub"},
+{"UQSUBv4i32", "uqsub"},
+{"UQSUBv8i8", "uqsub"},
+{"UQSUBv8i16", "uqsub"},
+{"UQSUBv16i8", "uqsub"},
+{"UQXTNB_ZZ_B", "uqxtnb"},
+{"UQXTNB_ZZ_H", "uqxtnb"},
+{"UQXTNB_ZZ_S", "uqxtnb"},
+{"UQXTNT_ZZ_B", "uqxtnt"},
+{"UQXTNT_ZZ_H", "uqxtnt"},
+{"UQXTNT_ZZ_S", "uqxtnt"},
+{"UQXTNv1i8", "uqxtn"},
+{"UQXTNv1i16", "uqxtn"},
+{"UQXTNv1i32", "uqxtn"},
+{"UQXTNv2i32", "uqxtn"},
+{"UQXTNv4i16", "uqxtn"},
+{"UQXTNv8i8", "uqxtn"},
+{"UQXTNv4i32", "uqxtn2"},
+{"UQXTNv8i16", "uqxtn2"},
+{"UQXTNv16i8", "uqxtn2"},
+{"URECPE_ZPmZ_S", "urecpe"},
+{"URECPE_ZPzZ_S", "urecpe"},
+{"URECPEv2i32", "urecpe"},
+{"URECPEv4i32", "urecpe"},
+{"URHADD_ZPmZ_B", "urhadd"},
+{"URHADD_ZPmZ_D", "urhadd"},
+{"URHADD_ZPmZ_H", "urhadd"},
+{"URHADD_ZPmZ_S", "urhadd"},
+{"URHADDv2i32", "urhadd"},
+{"URHADDv4i16", "urhadd"},
+{"URHADDv4i32", "urhadd"},
+{"URHADDv8i8", "urhadd"},
+{"URHADDv8i16", "urhadd"},
+{"URHADDv16i8", "urhadd"},
+{"URSHLR_ZPmZ_B", "urshlr"},
+{"URSHLR_ZPmZ_D", "urshlr"},
+{"URSHLR_ZPmZ_H", "urshlr"},
+{"URSHLR_ZPmZ_S", "urshlr"},
+{"URSHL_VG2_2Z2Z_B", "urshl"},
+{"URSHL_VG2_2Z2Z_D", "urshl"},
+{"URSHL_VG2_2Z2Z_H", "urshl"},
+{"URSHL_VG2_2Z2Z_S", "urshl"},
+{"URSHL_VG2_2ZZ_B", "urshl"},
+{"URSHL_VG2_2ZZ_D", "urshl"},
+{"URSHL_VG2_2ZZ_H", "urshl"},
+{"URSHL_VG2_2ZZ_S", "urshl"},
+{"URSHL_VG4_4Z4Z_B", "urshl"},
+{"URSHL_VG4_4Z4Z_D", "urshl"},
+{"URSHL_VG4_4Z4Z_H", "urshl"},
+{"URSHL_VG4_4Z4Z_S", "urshl"},
+{"URSHL_VG4_4ZZ_B", "urshl"},
+{"URSHL_VG4_4ZZ_D", "urshl"},
+{"URSHL_VG4_4ZZ_H", "urshl"},
+{"URSHL_VG4_4ZZ_S", "urshl"},
+{"URSHL_ZPmZ_B", "urshl"},
+{"URSHL_ZPmZ_D", "urshl"},
+{"URSHL_ZPmZ_H", "urshl"},
+{"URSHL_ZPmZ_S", "urshl"},
+{"URSHLv1i64", "urshl"},
+{"URSHLv2i32", "urshl"},
+{"URSHLv2i64", "urshl"},
+{"URSHLv4i16", "urshl"},
+{"URSHLv4i32", "urshl"},
+{"URSHLv8i8", "urshl"},
+{"URSHLv8i16", "urshl"},
+{"URSHLv16i8", "urshl"},
+{"URSHR_ZPmI_B", "urshr"},
+{"URSHR_ZPmI_D", "urshr"},
+{"URSHR_ZPmI_H", "urshr"},
+{"URSHR_ZPmI_S", "urshr"},
+{"URSHRd", "urshr"},
+{"URSHRv2i32_shift", "urshr"},
+{"URSHRv2i64_shift", "urshr"},
+{"URSHRv4i16_shift", "urshr"},
+{"URSHRv4i32_shift", "urshr"},
+{"URSHRv8i8_shift", "urshr"},
+{"URSHRv8i16_shift", "urshr"},
+{"URSHRv16i8_shift", "urshr"},
+{"URSQRTE_ZPmZ_S", "ursqrte"},
+{"URSQRTE_ZPzZ_S", "ursqrte"},
+{"URSQRTEv2i32", "ursqrte"},
+{"URSQRTEv4i32", "ursqrte"},
+{"URSRA_ZZI_B", "ursra"},
+{"URSRA_ZZI_D", "ursra"},
+{"URSRA_ZZI_H", "ursra"},
+{"URSRA_ZZI_S", "ursra"},
+{"URSRAd", "ursra"},
+{"URSRAv2i32_shift", "ursra"},
+{"URSRAv2i64_shift", "ursra"},
+{"URSRAv4i16_shift", "ursra"},
+{"URSRAv4i32_shift", "ursra"},
+{"URSRAv8i8_shift", "ursra"},
+{"URSRAv8i16_shift", "ursra"},
+{"URSRAv16i8_shift", "ursra"},
+{"USDOT_VG2_M2Z2Z_BToS", "usdot"},
+{"USDOT_VG2_M2ZZI_BToS", "usdot"},
+{"USDOT_VG2_M2ZZ_BToS", "usdot"},
+{"USDOT_VG4_M4Z4Z_BToS", "usdot"},
+{"USDOT_VG4_M4ZZI_BToS", "usdot"},
+{"USDOT_VG4_M4ZZ_BToS", "usdot"},
+{"USDOT_ZZZ", "usdot"},
+{"USDOT_ZZZI", "usdot"},
+{"USDOTlanev8i8", "usdot"},
+{"USDOTlanev16i8", "usdot"},
+{"USDOTv8i8", "usdot"},
+{"USDOTv16i8", "usdot"},
+{"USHLLB_ZZI_D", "ushllb"},
+{"USHLLB_ZZI_H", "ushllb"},
+{"USHLLB_ZZI_S", "ushllb"},
+{"USHLLT_ZZI_D", "ushllt"},
+{"USHLLT_ZZI_H", "ushllt"},
+{"USHLLT_ZZI_S", "ushllt"},
+{"USHLLv2i32_shift", "ushll"},
+{"USHLLv4i16_shift", "ushll"},
+{"USHLLv8i8_shift", "ushll"},
+{"USHLLv4i32_shift", "ushll2"},
+{"USHLLv8i16_shift", "ushll2"},
+{"USHLLv16i8_shift", "ushll2"},
+{"USHLv1i64", "ushl"},
+{"USHLv2i32", "ushl"},
+{"USHLv2i64", "ushl"},
+{"USHLv4i16", "ushl"},
+{"USHLv4i32", "ushl"},
+{"USHLv8i8", "ushl"},
+{"USHLv8i16", "ushl"},
+{"USHLv16i8", "ushl"},
+{"USHRd", "ushr"},
+{"USHRv2i32_shift", "ushr"},
+{"USHRv2i64_shift", "ushr"},
+{"USHRv4i16_shift", "ushr"},
+{"USHRv4i32_shift", "ushr"},
+{"USHRv8i8_shift", "ushr"},
+{"USHRv8i16_shift", "ushr"},
+{"USHRv16i8_shift", "ushr"},
+{"USMLALL_MZZI_BtoS", "usmlall"},
+{"USMLALL_MZZ_BtoS", "usmlall"},
+{"USMLALL_VG2_M2Z2Z_BtoS", "usmlall"},
+{"USMLALL_VG2_M2ZZI_BtoS", "usmlall"},
+{"USMLALL_VG2_M2ZZ_BtoS", "usmlall"},
+{"USMLALL_VG4_M4Z4Z_BtoS", "usmlall"},
+{"USMLALL_VG4_M4ZZI_BtoS", "usmlall"},
+{"USMLALL_VG4_M4ZZ_BtoS", "usmlall"},
+{"USMMLA", "usmmla"},
+{"USMMLA_ZZZ", "usmmla"},
+{"USMOP4A_M2Z2Z_BToS", "usmop4a"},
+{"USMOP4A_M2Z2Z_HtoD", "usmop4a"},
+{"USMOP4A_M2ZZ_BToS", "usmop4a"},
+{"USMOP4A_M2ZZ_HtoD", "usmop4a"},
+{"USMOP4A_MZ2Z_BToS", "usmop4a"},
+{"USMOP4A_MZ2Z_HtoD", "usmop4a"},
+{"USMOP4A_MZZ_BToS", "usmop4a"},
+{"USMOP4A_MZZ_HtoD", "usmop4a"},
+{"USMOP4S_M2Z2Z_BToS", "usmop4s"},
+{"USMOP4S_M2Z2Z_HtoD", "usmop4s"},
+{"USMOP4S_M2ZZ_BToS", "usmop4s"},
+{"USMOP4S_M2ZZ_HtoD", "usmop4s"},
+{"USMOP4S_MZ2Z_BToS", "usmop4s"},
+{"USMOP4S_MZ2Z_HtoD", "usmop4s"},
+{"USMOP4S_MZZ_BToS", "usmop4s"},
+{"USMOP4S_MZZ_HtoD", "usmop4s"},
+{"USMOPA_MPPZZ_D", "usmopa"},
+{"USMOPA_MPPZZ_S", "usmopa"},
+{"USMOPS_MPPZZ_D", "usmops"},
+{"USMOPS_MPPZZ_S", "usmops"},
+{"USQADD_ZPmZ_B", "usqadd"},
+{"USQADD_ZPmZ_D", "usqadd"},
+{"USQADD_ZPmZ_H", "usqadd"},
+{"USQADD_ZPmZ_S", "usqadd"},
+{"USQADDv1i8", "usqadd"},
+{"USQADDv1i16", "usqadd"},
+{"USQADDv1i32", "usqadd"},
+{"USQADDv1i64", "usqadd"},
+{"USQADDv2i32", "usqadd"},
+{"USQADDv2i64", "usqadd"},
+{"USQADDv4i16", "usqadd"},
+{"USQADDv4i32", "usqadd"},
+{"USQADDv8i8", "usqadd"},
+{"USQADDv8i16", "usqadd"},
+{"USQADDv16i8", "usqadd"},
+{"USRA_ZZI_B", "usra"},
+{"USRA_ZZI_D", "usra"},
+{"USRA_ZZI_H", "usra"},
+{"USRA_ZZI_S", "usra"},
+{"USRAd", "usra"},
+{"USRAv2i32_shift", "usra"},
+{"USRAv2i64_shift", "usra"},
+{"USRAv4i16_shift", "usra"},
+{"USRAv4i32_shift", "usra"},
+{"USRAv8i8_shift", "usra"},
+{"USRAv8i16_shift", "usra"},
+{"USRAv16i8_shift", "usra"},
+{"USTMOPA_M2ZZZI_BtoS", "ustmopa"},
+{"USUBLB_ZZZ_D", "usublb"},
+{"USUBLB_ZZZ_H", "usublb"},
+{"USUBLB_ZZZ_S", "usublb"},
+{"USUBLT_ZZZ_D", "usublt"},
+{"USUBLT_ZZZ_H", "usublt"},
+{"USUBLT_ZZZ_S", "usublt"},
+{"USUBLv2i32_v2i64", "usubl"},
+{"USUBLv4i16_v4i32", "usubl"},
+{"USUBLv8i8_v8i16", "usubl"},
+{"USUBLv4i32_v2i64", "usubl2"},
+{"USUBLv8i16_v4i32", "usubl2"},
+{"USUBLv16i8_v8i16", "usubl2"},
+{"USUBWB_ZZZ_D", "usubwb"},
+{"USUBWB_ZZZ_H", "usubwb"},
+{"USUBWB_ZZZ_S", "usubwb"},
+{"USUBWT_ZZZ_D", "usubwt"},
+{"USUBWT_ZZZ_H", "usubwt"},
+{"USUBWT_ZZZ_S", "usubwt"},
+{"USUBWv2i32_v2i64", "usubw"},
+{"USUBWv4i16_v4i32", "usubw"},
+{"USUBWv8i8_v8i16", "usubw"},
+{"USUBWv4i32_v2i64", "usubw2"},
+{"USUBWv8i16_v4i32", "usubw2"},
+{"USUBWv16i8_v8i16", "usubw2"},
+{"USVDOT_VG4_M4ZZI_BToS", "usvdot"},
+{"UTMOPA_M2ZZZI_BtoS", "utmopa"},
+{"UTMOPA_M2ZZZI_HtoS", "utmopa"},
+{"UUNPKHI_ZZ_D", "uunpkhi"},
+{"UUNPKHI_ZZ_H", "uunpkhi"},
+{"UUNPKHI_ZZ_S", "uunpkhi"},
+{"UUNPKLO_ZZ_D", "uunpklo"},
+{"UUNPKLO_ZZ_H", "uunpklo"},
+{"UUNPKLO_ZZ_S", "uunpklo"},
+{"UUNPK_VG2_2ZZ_D", "uunpk"},
+{"UUNPK_VG2_2ZZ_H", "uunpk"},
+{"UUNPK_VG2_2ZZ_S", "uunpk"},
+{"UUNPK_VG4_4Z2Z_D", "uunpk"},
+{"UUNPK_VG4_4Z2Z_H", "uunpk"},
+{"UUNPK_VG4_4Z2Z_S", "uunpk"},
+{"UVDOT_VG2_M2ZZI_HtoS", "uvdot"},
+{"UVDOT_VG4_M4ZZI_BtoS", "uvdot"},
+{"UVDOT_VG4_M4ZZI_HtoD", "uvdot"},
+{"UXTB_ZPmZ_D", "uxtb"},
+{"UXTB_ZPmZ_H", "uxtb"},
+{"UXTB_ZPmZ_S", "uxtb"},
+{"UXTB_ZPzZ_D", "uxtb"},
+{"UXTB_ZPzZ_H", "uxtb"},
+{"UXTB_ZPzZ_S", "uxtb"},
+{"UXTH_ZPmZ_D", "uxth"},
+{"UXTH_ZPmZ_S", "uxth"},
+{"UXTH_ZPzZ_D", "uxth"},
+{"UXTH_ZPzZ_S", "uxth"},
+{"UXTW_ZPmZ_D", "uxtw"},
+{"UXTW_ZPzZ_D", "uxtw"},
+{"UZP1_PPP_B", "uzp1"},
+{"UZP1_PPP_D", "uzp1"},
+{"UZP1_PPP_H", "uzp1"},
+{"UZP1_PPP_S", "uzp1"},
+{"UZP1_ZZZ_B", "uzp1"},
+{"UZP1_ZZZ_D", "uzp1"},
+{"UZP1_ZZZ_H", "uzp1"},
+{"UZP1_ZZZ_Q", "uzp1"},
+{"UZP1_ZZZ_S", "uzp1"},
+{"UZP1v2i32", "uzp1"},
+{"UZP1v2i64", "uzp1"},
+{"UZP1v4i16", "uzp1"},
+{"UZP1v4i32", "uzp1"},
+{"UZP1v8i8", "uzp1"},
+{"UZP1v8i16", "uzp1"},
+{"UZP1v16i8", "uzp1"},
+{"UZP2_PPP_B", "uzp2"},
+{"UZP2_PPP_D", "uzp2"},
+{"UZP2_PPP_H", "uzp2"},
+{"UZP2_PPP_S", "uzp2"},
+{"UZP2_ZZZ_B", "uzp2"},
+{"UZP2_ZZZ_D", "uzp2"},
+{"UZP2_ZZZ_H", "uzp2"},
+{"UZP2_ZZZ_Q", "uzp2"},
+{"UZP2_ZZZ_S", "uzp2"},
+{"UZP2v2i32", "uzp2"},
+{"UZP2v2i64", "uzp2"},
+{"UZP2v4i16", "uzp2"},
+{"UZP2v4i32", "uzp2"},
+{"UZP2v8i8", "uzp2"},
+{"UZP2v8i16", "uzp2"},
+{"UZP2v16i8", "uzp2"},
+{"UZPQ1_ZZZ_B", "uzpq1"},
+{"UZPQ1_ZZZ_D", "uzpq1"},
+{"UZPQ1_ZZZ_H", "uzpq1"},
+{"UZPQ1_ZZZ_S", "uzpq1"},
+{"UZPQ2_ZZZ_B", "uzpq2"},
+{"UZPQ2_ZZZ_D", "uzpq2"},
+{"UZPQ2_ZZZ_H", "uzpq2"},
+{"UZPQ2_ZZZ_S", "uzpq2"},
+{"UZP_VG2_2ZZZ_B", "uzp"},
+{"UZP_VG2_2ZZZ_D", "uzp"},
+{"UZP_VG2_2ZZZ_H", "uzp"},
+{"UZP_VG2_2ZZZ_Q", "uzp"},
+{"UZP_VG2_2ZZZ_S", "uzp"},
+{"UZP_VG4_4Z4Z_B", "uzp"},
+{"UZP_VG4_4Z4Z_D", "uzp"},
+{"UZP_VG4_4Z4Z_H", "uzp"},
+{"UZP_VG4_4Z4Z_Q", "uzp"},
+{"UZP_VG4_4Z4Z_S", "uzp"},
+{"WFET", "wfet"},
+{"WFIT", "wfit"},
+{"WHILEGE_2PXX_B", "whilege"},
+{"WHILEGE_2PXX_D", "whilege"},
+{"WHILEGE_2PXX_H", "whilege"},
+{"WHILEGE_2PXX_S", "whilege"},
+{"WHILEGE_CXX_B", "whilege"},
+{"WHILEGE_CXX_D", "whilege"},
+{"WHILEGE_CXX_H", "whilege"},
+{"WHILEGE_CXX_S", "whilege"},
+{"WHILEGE_PWW_B", "whilege"},
+{"WHILEGE_PWW_D", "whilege"},
+{"WHILEGE_PWW_H", "whilege"},
+{"WHILEGE_PWW_S", "whilege"},
+{"WHILEGE_PXX_B", "whilege"},
+{"WHILEGE_PXX_D", "whilege"},
+{"WHILEGE_PXX_H", "whilege"},
+{"WHILEGE_PXX_S", "whilege"},
+{"WHILEGT_2PXX_B", "whilegt"},
+{"WHILEGT_2PXX_D", "whilegt"},
+{"WHILEGT_2PXX_H", "whilegt"},
+{"WHILEGT_2PXX_S", "whilegt"},
+{"WHILEGT_CXX_B", "whilegt"},
+{"WHILEGT_CXX_D", "whilegt"},
+{"WHILEGT_CXX_H", "whilegt"},
+{"WHILEGT_CXX_S", "whilegt"},
+{"WHILEGT_PWW_B", "whilegt"},
+{"WHILEGT_PWW_D", "whilegt"},
+{"WHILEGT_PWW_H", "whilegt"},
+{"WHILEGT_PWW_S", "whilegt"},
+{"WHILEGT_PXX_B", "whilegt"},
+{"WHILEGT_PXX_D", "whilegt"},
+{"WHILEGT_PXX_H", "whilegt"},
+{"WHILEGT_PXX_S", "whilegt"},
+{"WHILEHI_2PXX_B", "whilehi"},
+{"WHILEHI_2PXX_D", "whilehi"},
+{"WHILEHI_2PXX_H", "whilehi"},
+{"WHILEHI_2PXX_S", "whilehi"},
+{"WHILEHI_CXX_B", "whilehi"},
+{"WHILEHI_CXX_D", "whilehi"},
+{"WHILEHI_CXX_H", "whilehi"},
+{"WHILEHI_CXX_S", "whilehi"},
+{"WHILEHI_PWW_B", "whilehi"},
+{"WHILEHI_PWW_D", "whilehi"},
+{"WHILEHI_PWW_H", "whilehi"},
+{"WHILEHI_PWW_S", "whilehi"},
+{"WHILEHI_PXX_B", "whilehi"},
+{"WHILEHI_PXX_D", "whilehi"},
+{"WHILEHI_PXX_H", "whilehi"},
+{"WHILEHI_PXX_S", "whilehi"},
+{"WHILEHS_2PXX_B", "whilehs"},
+{"WHILEHS_2PXX_D", "whilehs"},
+{"WHILEHS_2PXX_H", "whilehs"},
+{"WHILEHS_2PXX_S", "whilehs"},
+{"WHILEHS_CXX_B", "whilehs"},
+{"WHILEHS_CXX_D", "whilehs"},
+{"WHILEHS_CXX_H", "whilehs"},
+{"WHILEHS_CXX_S", "whilehs"},
+{"WHILEHS_PWW_B", "whilehs"},
+{"WHILEHS_PWW_D", "whilehs"},
+{"WHILEHS_PWW_H", "whilehs"},
+{"WHILEHS_PWW_S", "whilehs"},
+{"WHILEHS_PXX_B", "whilehs"},
+{"WHILEHS_PXX_D", "whilehs"},
+{"WHILEHS_PXX_H", "whilehs"},
+{"WHILEHS_PXX_S", "whilehs"},
+{"WHILELE_2PXX_B", "whilele"},
+{"WHILELE_2PXX_D", "whilele"},
+{"WHILELE_2PXX_H", "whilele"},
+{"WHILELE_2PXX_S", "whilele"},
+{"WHILELE_CXX_B", "whilele"},
+{"WHILELE_CXX_D", "whilele"},
+{"WHILELE_CXX_H", "whilele"},
+{"WHILELE_CXX_S", "whilele"},
+{"WHILELE_PWW_B", "whilele"},
+{"WHILELE_PWW_D", "whilele"},
+{"WHILELE_PWW_H", "whilele"},
+{"WHILELE_PWW_S", "whilele"},
+{"WHILELE_PXX_B", "whilele"},
+{"WHILELE_PXX_D", "whilele"},
+{"WHILELE_PXX_H", "whilele"},
+{"WHILELE_PXX_S", "whilele"},
+{"WHILELO_2PXX_B", "whilelo"},
+{"WHILELO_2PXX_D", "whilelo"},
+{"WHILELO_2PXX_H", "whilelo"},
+{"WHILELO_2PXX_S", "whilelo"},
+{"WHILELO_CXX_B", "whilelo"},
+{"WHILELO_CXX_D", "whilelo"},
+{"WHILELO_CXX_H", "whilelo"},
+{"WHILELO_CXX_S", "whilelo"},
+{"WHILELO_PWW_B", "whilelo"},
+{"WHILELO_PWW_D", "whilelo"},
+{"WHILELO_PWW_H", "whilelo"},
+{"WHILELO_PWW_S", "whilelo"},
+{"WHILELO_PXX_B", "whilelo"},
+{"WHILELO_PXX_D", "whilelo"},
+{"WHILELO_PXX_H", "whilelo"},
+{"WHILELO_PXX_S", "whilelo"},
+{"WHILELS_2PXX_B", "whilels"},
+{"WHILELS_2PXX_D", "whilels"},
+{"WHILELS_2PXX_H", "whilels"},
+{"WHILELS_2PXX_S", "whilels"},
+{"WHILELS_CXX_B", "whilels"},
+{"WHILELS_CXX_D", "whilels"},
+{"WHILELS_CXX_H", "whilels"},
+{"WHILELS_CXX_S", "whilels"},
+{"WHILELS_PWW_B", "whilels"},
+{"WHILELS_PWW_D", "whilels"},
+{"WHILELS_PWW_H", "whilels"},
+{"WHILELS_PWW_S", "whilels"},
+{"WHILELS_PXX_B", "whilels"},
+{"WHILELS_PXX_D", "whilels"},
+{"WHILELS_PXX_H", "whilels"},
+{"WHILELS_PXX_S", "whilels"},
+{"WHILELT_2PXX_B", "whilelt"},
+{"WHILELT_2PXX_D", "whilelt"},
+{"WHILELT_2PXX_H", "whilelt"},
+{"WHILELT_2PXX_S", "whilelt"},
+{"WHILELT_CXX_B", "whilelt"},
+{"WHILELT_CXX_D", "whilelt"},
+{"WHILELT_CXX_H", "whilelt"},
+{"WHILELT_CXX_S", "whilelt"},
+{"WHILELT_PWW_B", "whilelt"},
+{"WHILELT_PWW_D", "whilelt"},
+{"WHILELT_PWW_H", "whilelt"},
+{"WHILELT_PWW_S", "whilelt"},
+{"WHILELT_PXX_B", "whilelt"},
+{"WHILELT_PXX_D", "whilelt"},
+{"WHILELT_PXX_H", "whilelt"},
+{"WHILELT_PXX_S", "whilelt"},
+{"WHILERW_PXX_B", "whilerw"},
+{"WHILERW_PXX_D", "whilerw"},
+{"WHILERW_PXX_H", "whilerw"},
+{"WHILERW_PXX_S", "whilerw"},
+{"WHILEWR_PXX_B", "whilewr"},
+{"WHILEWR_PXX_D", "whilewr"},
+{"WHILEWR_PXX_H", "whilewr"},
+{"WHILEWR_PXX_S", "whilewr"},
+{"WRFFR", "wrffr"},
+{"XAFLAG", "xaflag"},
+{"XAR", "xar"},
+{"XAR_ZZZI_B", "xar"},
+{"XAR_ZZZI_D", "xar"},
+{"XAR_ZZZI_H", "xar"},
+{"XAR_ZZZI_S", "xar"},
+{"XPACD", "xpacd"},
+{"XPACI", "xpaci"},
+{"XTNv2i32", "xtn"},
+{"XTNv4i16", "xtn"},
+{"XTNv8i8", "xtn"},
+{"XTNv4i32", "xtn2"},
+{"XTNv8i16", "xtn2"},
+{"XTNv16i8", "xtn2"},
+{"ZERO_M", "zero"},
+{"ZERO_MXI_2Z", "zero"},
+{"ZERO_MXI_4Z", "zero"},
+{"ZERO_MXI_VG2_2Z", "zero"},
+{"ZERO_MXI_VG2_4Z", "zero"},
+{"ZERO_MXI_VG2_Z", "zero"},
+{"ZERO_MXI_VG4_2Z", "zero"},
+{"ZERO_MXI_VG4_4Z", "zero"},
+{"ZERO_MXI_VG4_Z", "zero"},
+{"ZERO_T", "zero"},
+{"ZIP1_PPP_B", "zip1"},
+{"ZIP1_PPP_D", "zip1"},
+{"ZIP1_PPP_H", "zip1"},
+{"ZIP1_PPP_S", "zip1"},
+{"ZIP1_ZZZ_B", "zip1"},
+{"ZIP1_ZZZ_D", "zip1"},
+{"ZIP1_ZZZ_H", "zip1"},
+{"ZIP1_ZZZ_Q", "zip1"},
+{"ZIP1_ZZZ_S", "zip1"},
+{"ZIP1v2i32", "zip1"},
+{"ZIP1v2i64", "zip1"},
+{"ZIP1v4i16", "zip1"},
+{"ZIP1v4i32", "zip1"},
+{"ZIP1v8i8", "zip1"},
+{"ZIP1v8i16", "zip1"},
+{"ZIP1v16i8", "zip1"},
+{"ZIP2_PPP_B", "zip2"},
+{"ZIP2_PPP_D", "zip2"},
+{"ZIP2_PPP_H", "zip2"},
+{"ZIP2_PPP_S", "zip2"},
+{"ZIP2_ZZZ_B", "zip2"},
+{"ZIP2_ZZZ_D", "zip2"},
+{"ZIP2_ZZZ_H", "zip2"},
+{"ZIP2_ZZZ_Q", "zip2"},
+{"ZIP2_ZZZ_S", "zip2"},
+{"ZIP2v2i32", "zip2"},
+{"ZIP2v2i64", "zip2"},
+{"ZIP2v4i16", "zip2"},
+{"ZIP2v4i32", "zip2"},
+{"ZIP2v8i8", "zip2"},
+{"ZIP2v8i16", "zip2"},
+{"ZIP2v16i8", "zip2"},
+{"ZIPQ1_ZZZ_B", "zipq1"},
+{"ZIPQ1_ZZZ_D", "zipq1"},
+{"ZIPQ1_ZZZ_H", "zipq1"},
+{"ZIPQ1_ZZZ_S", "zipq1"},
+{"ZIPQ2_ZZZ_B", "zipq2"},
+{"ZIPQ2_ZZZ_D", "zipq2"},
+{"ZIPQ2_ZZZ_H", "zipq2"},
+{"ZIPQ2_ZZZ_S", "zipq2"},
+{"ZIP_VG2_2ZZZ_B", "zip"},
+{"ZIP_VG2_2ZZZ_D", "zip"},
+{"ZIP_VG2_2ZZZ_H", "zip"},
+{"ZIP_VG2_2ZZZ_Q", "zip"},
+{"ZIP_VG2_2ZZZ_S", "zip"},
+{"ZIP_VG4_4Z4Z_B", "zip"},
+{"ZIP_VG4_4Z4Z_D", "zip"},
+{"ZIP_VG4_4Z4Z_H", "zip"},
+{"ZIP_VG4_4Z4Z_Q", "zip"},
+{"ZIP_VG4_4Z4Z_S", "zip"},
+// Considered 7484 instructions, emitted 1551 ops across 1551 mnemonics.
diff --git a/mlir/lib/Target/MIR/CMakeLists.txt b/mlir/lib/Target/MIR/CMakeLists.txt
index 4f653d5e6f33c..7ce1a37cf92a6 100644
--- a/mlir/lib/Target/MIR/CMakeLists.txt
+++ b/mlir/lib/Target/MIR/CMakeLists.txt
@@ -17,6 +17,7 @@ add_mlir_translation_library(MLIRTargetMIRImport
LINK_LIBS PUBLIC
MLIRIR
+ MLIRAArch64MIRDialect
MLIRMIRDialect
MLIRTranslateLib
)
diff --git a/mlir/lib/Target/MIR/MIRImport.cpp b/mlir/lib/Target/MIR/MIRImport.cpp
index d35f122fe6736..10b9a562d9fe5 100644
--- a/mlir/lib/Target/MIR/MIRImport.cpp
+++ b/mlir/lib/Target/MIR/MIRImport.cpp
@@ -15,12 +15,14 @@
//
//===----------------------------------------------------------------------===//
+#include "mlir/Dialect/AArch64MIR/IR/AArch64MIRDialect.h"
#include "mlir/Dialect/MIR/IR/MIROps.h"
#include "mlir/IR/Builders.h"
#include "mlir/IR/BuiltinOps.h"
#include "mlir/IR/OwningOpRef.h"
#include "mlir/Tools/mlir-translate/Translation.h"
+#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/MIRParser/MIRParser.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -28,6 +30,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGenTypes/LowLevelType.h"
#include "llvm/IR/Module.h"
@@ -39,6 +42,21 @@ using namespace mlir;
namespace {
+/// AArch64 opcode-record-name -> collapsed op mnemonic, generated by
+/// `mlir-tblgen -gen-mir-target-ops --mir-emit-lowering`.
+static const llvm::StringMap<std::string> &getLoweringMap() {
+ static const llvm::StringMap<std::string> map = [] {
+ llvm::StringMap<std::string> m;
+ static const std::pair<const char *, const char *> entries[] = {
+#include "AArch64MIRLowering.inc"
+ };
+ for (const auto &e : entries)
+ m[e.first] = e.second;
+ return m;
+ }();
+ return map;
+}
+
/// Convert an LLT to the corresponding `mir` dialect type.
static Type lltToType(llvm::LLT llt, MLIRContext *ctx) {
if (llt.isPointer())
@@ -79,6 +97,17 @@ class Importer {
StringRef physRegName(llvm::Register reg) { return tri->getName(reg); }
+ /// The mir type of a virtual register: its LLT if generic, otherwise a
+ /// scalar sized from its register class (post-instruction-select vregs).
+ Type regType(llvm::Register reg) {
+ llvm::LLT llt = mri.getType(reg);
+ if (llt.isValid())
+ return lltToType(llt, ctx);
+ if (const llvm::TargetRegisterClass *rc = mri.getRegClassOrNull(reg))
+ return mir::ScalarType::get(ctx, tri->getRegSizeInBits(*rc));
+ return mir::ScalarType::get(ctx, 0);
+ }
+
LogicalResult convert(OpBuilder &b, Location loc,
const llvm::MachineInstr &mi) {
unsigned opcode = mi.getOpcode();
@@ -89,7 +118,7 @@ class Importer {
const llvm::MachineOperand &src = mi.getOperand(1);
// vreg = COPY $phys -> mir.copy_from_phys
if (dst.getReg().isVirtual() && src.getReg().isPhysical()) {
- Type ty = lltToType(mri.getType(dst.getReg()), ctx);
+ Type ty = regType(dst.getReg());
auto reg = mir::PhysRegAttr::get(ctx, physRegName(src.getReg()));
auto op = b.create<mir::CopyFromPhysOp>(loc, ty, reg);
map(dst.getReg(), op.getResult());
@@ -131,7 +160,7 @@ class Importer {
if (mo.isImplicit())
continue;
if (mo.isDef()) {
- resultTypes.push_back(lltToType(mri.getType(mo.getReg()), ctx));
+ resultTypes.push_back(regType(mo.getReg()));
defRegs.push_back(mo.getReg());
} else {
Value v = lookup(mo.getReg());
@@ -150,7 +179,38 @@ class Importer {
return success();
}
- // Selected target opcodes are handled in a later step.
+ // Selected target opcode -> aarch64_mir.<mnemonic> with a `variant`
+ // discriminator naming the concrete opcode.
+ StringRef recName = tii->getName(opcode);
+ auto it = getLoweringMap().find(recName);
+ if (it != getLoweringMap().end()) {
+ std::string name = "aarch64_mir." + it->second;
+ SmallVector<Value> operands;
+ SmallVector<Type> resultTypes;
+ SmallVector<llvm::Register> defRegs;
+ for (const llvm::MachineOperand &mo : mi.operands()) {
+ if (!mo.isReg() || mo.isImplicit())
+ continue;
+ if (mo.isDef()) {
+ resultTypes.push_back(regType(mo.getReg()));
+ defRegs.push_back(mo.getReg());
+ } else {
+ Value v = lookup(mo.getReg());
+ if (!v)
+ return failure();
+ operands.push_back(v);
+ }
+ }
+ OperationState state(loc, name);
+ state.addOperands(operands);
+ state.addTypes(resultTypes);
+ state.addAttribute("variant", StringAttr::get(ctx, recName));
+ Operation *op = b.create(state);
+ for (auto [reg, res] : llvm::zip(defRegs, op->getResults()))
+ map(reg, res);
+ return success();
+ }
+
return failure();
}
@@ -210,6 +270,7 @@ static OwningOpRef<Operation *> translateMIRToModule(llvm::SourceMgr &sourceMgr,
OpBuilder b(ctx);
ctx->getOrLoadDialect<mir::MIRDialect>();
+ ctx->getOrLoadDialect<aarch64_mir::AArch64MIRDialect>();
Location loc = UnknownLoc::get(ctx);
OwningOpRef<ModuleOp> mlirModule = ModuleOp::create(loc);
b.setInsertionPointToEnd(mlirModule->getBody());
@@ -239,7 +300,7 @@ void registerFromMIRTranslation() {
return translateMIRToModule(sourceMgr, ctx);
},
[](DialectRegistry ®istry) {
- registry.insert<mir::MIRDialect>();
+ registry.insert<mir::MIRDialect, aarch64_mir::AArch64MIRDialect>();
});
}
} // namespace mlir
diff --git a/mlir/test/Target/MIR/import-selected.mir b/mlir/test/Target/MIR/import-selected.mir
new file mode 100644
index 0000000000000..b8f9b8edeb166
--- /dev/null
+++ b/mlir/test/Target/MIR/import-selected.mir
@@ -0,0 +1,28 @@
+# RUN: mlir-translate --import-mir %s | FileCheck %s
+
+# Import selected (post-instruction-select) AArch64 MachineIR. Concrete target
+# opcodes are mapped to their collapsed aarch64_mir op via the generated
+# lowering table, carrying a `variant` attribute that names the concrete
+# opcode. Register-class virtual registers are typed by their class size.
+
+--- |
+ define void @sel(i64 %a, i64 %b) { ret void }
+...
+---
+name: sel
+body: |
+ bb.0:
+ liveins: $x0, $x1
+ %0:gpr64 = COPY $x0
+ %1:gpr64 = COPY $x1
+ %2:gpr64 = ADDXrs %0, %1, 0
+ %3:gpr64 = SUBXrs %2, %0, 0
+ $x0 = COPY %3
+...
+
+# CHECK-LABEL: mir.func @sel
+# CHECK: %[[A:.*]] = mir.copy_from_phys #mir.physreg<"X0"> -> !mir.scalar<64>
+# CHECK: %[[B:.*]] = mir.copy_from_phys #mir.physreg<"X1"> -> !mir.scalar<64>
+# CHECK: %[[S:.*]] = aarch64_mir.add %[[A]], %[[B]] {variant = "ADDXrs"} : (!mir.scalar<64>, !mir.scalar<64>) -> !mir.scalar<64>
+# CHECK: %[[D:.*]] = aarch64_mir.sub %[[S]], %[[A]] {variant = "SUBXrs"} : (!mir.scalar<64>, !mir.scalar<64>) -> !mir.scalar<64>
+# CHECK: mir.copy_to_phys %[[D]] : !mir.scalar<64> to #mir.physreg<"X0">
diff --git a/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp b/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
index 1f916a435c5d1..72459c6eb0632 100644
--- a/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
+++ b/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
@@ -49,6 +49,12 @@ static llvm::cl::opt<std::string>
llvm::cl::init("AArch64MIR_TargetOp"),
llvm::cl::cat(targetOpCat));
+static llvm::cl::opt<bool> emitLowering(
+ "mir-emit-lowering",
+ llvm::cl::desc("Emit a C++ opcode-record-name -> op-mnemonic lowering "
+ "table (as `{\"OPC\", \"mnem\"},` lines) instead of ODS"),
+ llvm::cl::init(false), llvm::cl::cat(targetOpCat));
+
/// Value of a boolean record field, treating unset/missing as false.
static bool getBitOrFalse(const Record &record, llvm::StringRef field) {
const llvm::RecordVal *rv = record.getValue(field);
@@ -127,11 +133,13 @@ static unsigned numDagArgs(const Record &record, llvm::StringRef field) {
}
static bool emitTargetOps(const RecordKeeper &records, llvm::raw_ostream &os) {
- llvm::emitSourceFileHeader(
- (llvm::Twine(targetNamespace) + " MIR target operations").str(), os,
- records);
- os << "include \"mlir/Dialect/MIR/IR/MIRTypes.td\"\n";
- os << "include \"mlir/Interfaces/SideEffectInterfaces.td\"\n\n";
+ if (!emitLowering) {
+ llvm::emitSourceFileHeader(
+ (llvm::Twine(targetNamespace) + " MIR target operations").str(), os,
+ records);
+ os << "include \"mlir/Dialect/MIR/IR/MIRTypes.td\"\n";
+ os << "include \"mlir/Interfaces/SideEffectInterfaces.td\"\n\n";
+ }
// Cluster instructions by mnemonic, preserving first-seen order.
llvm::StringMap<unsigned> clusterIndex;
@@ -169,6 +177,16 @@ static bool emitTargetOps(const RecordKeeper &records, llvm::raw_ostream &os) {
const Cluster &c = kv.second;
std::string opName = sanitizeMnemonic(mnemonic);
+
+ // Lowering-table mode: emit `{"OPCODE", "mnem"},` for each concrete opcode
+ // this op subsumes, and skip ODS emission.
+ if (emitLowering) {
+ for (llvm::StringRef opc : c.opcodes)
+ os << "{\"" << opc << "\", \"" << opName << "\"},\n";
+ ++emitted;
+ continue;
+ }
+
std::string ident = sanitizeIdent(opName);
std::string base = ident;
unsigned suffix = 0;
>From 139601ce56cfaa5b08363d6bf1e5bb3e3667878a Mon Sep 17 00:00:00 2001
From: makslevental <maksim.levental at gmail.com>
Date: Mon, 24 Aug 2026 12:01:35 -0700
Subject: [PATCH 7/7] MLIR: Fix CI: use OpTy::create, clang-format, exempt
generated table
- MIRImport: replace deprecated builder.create<OpTy>() with OpTy::create(...)
(the -Werror -Wdeprecated-declarations build failed on the old form).
- Run clang-format over the hand-written translation and tblgen sources.
- Wrap the generated AArch64MIRLowering.inc in a clang-format off region so the
data table is exempt from formatting.
---
mlir/lib/Target/MIR/AArch64MIRLowering.inc | 1 +
mlir/lib/Target/MIR/MIRExport.cpp | 9 +++---
mlir/lib/Target/MIR/MIRImport.cpp | 15 ++++-----
mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp | 17 +++++-----
mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp | 36 ++++++++++++----------
5 files changed, 43 insertions(+), 35 deletions(-)
diff --git a/mlir/lib/Target/MIR/AArch64MIRLowering.inc b/mlir/lib/Target/MIR/AArch64MIRLowering.inc
index 644bd1f8689b3..9a9e12470461f 100644
--- a/mlir/lib/Target/MIR/AArch64MIRLowering.inc
+++ b/mlir/lib/Target/MIR/AArch64MIRLowering.inc
@@ -1,3 +1,4 @@
+// clang-format off
{"ABSWr", "abs"},
{"ABSXr", "abs"},
{"ABS_ZPmZ_B", "abs"},
diff --git a/mlir/lib/Target/MIR/MIRExport.cpp b/mlir/lib/Target/MIR/MIRExport.cpp
index 226ca8849ccd7..30a5b338368c2 100644
--- a/mlir/lib/Target/MIR/MIRExport.cpp
+++ b/mlir/lib/Target/MIR/MIRExport.cpp
@@ -17,11 +17,11 @@
#include "mlir/IR/BuiltinOps.h"
#include "mlir/Tools/mlir-translate/Translation.h"
+#include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGenTypes/LowLevelType.h"
@@ -42,8 +42,8 @@ static llvm::LLT typeToLLT(Type t) {
if (auto p = dyn_cast<mir::PointerType>(t))
return llvm::LLT::pointer(p.getAddressSpace(), p.getSizeInBits());
if (auto v = dyn_cast<mir::VectorType>(t))
- return llvm::LLT::fixed_vector(v.getNumElements(),
- llvm::LLT::scalar(v.getElementType().getWidth()));
+ return llvm::LLT::fixed_vector(
+ v.getNumElements(), llvm::LLT::scalar(v.getElementType().getWidth()));
return llvm::LLT();
}
@@ -52,8 +52,7 @@ static llvm::LLT typeToLLT(Type t) {
class Exporter {
public:
Exporter(llvm::MachineFunction &mf)
- : mf(mf), mri(mf.getRegInfo()),
- tii(mf.getSubtarget().getInstrInfo()),
+ : mf(mf), mri(mf.getRegInfo()), tii(mf.getSubtarget().getInstrInfo()),
tri(mf.getSubtarget().getRegisterInfo()) {
// Reverse map: opcode name -> opcode number.
for (unsigned op = 0, e = tii->getNumOpcodes(); op != e; ++op)
diff --git a/mlir/lib/Target/MIR/MIRImport.cpp b/mlir/lib/Target/MIR/MIRImport.cpp
index 10b9a562d9fe5..21d7137a523a2 100644
--- a/mlir/lib/Target/MIR/MIRImport.cpp
+++ b/mlir/lib/Target/MIR/MIRImport.cpp
@@ -120,7 +120,7 @@ class Importer {
if (dst.getReg().isVirtual() && src.getReg().isPhysical()) {
Type ty = regType(dst.getReg());
auto reg = mir::PhysRegAttr::get(ctx, physRegName(src.getReg()));
- auto op = b.create<mir::CopyFromPhysOp>(loc, ty, reg);
+ auto op = mir::CopyFromPhysOp::create(b, loc, ty, reg);
map(dst.getReg(), op.getResult());
return success();
}
@@ -130,7 +130,7 @@ class Importer {
if (!v)
return failure();
auto reg = mir::PhysRegAttr::get(ctx, physRegName(dst.getReg()));
- b.create<mir::CopyToPhysOp>(loc, v, reg);
+ mir::CopyToPhysOp::create(b, loc, v, reg);
return success();
}
// vreg = COPY vreg -> mir.copy
@@ -138,7 +138,7 @@ class Importer {
Value v = lookup(src.getReg());
if (!v)
return failure();
- auto op = b.create<mir::CopyOp>(loc, v.getType(), v);
+ auto op = mir::CopyOp::create(b, loc, v.getType(), v);
map(dst.getReg(), op.getResult());
return success();
}
@@ -253,8 +253,8 @@ static OwningOpRef<Operation *> translateMIRToModule(llvm::SourceMgr &sourceMgr,
std::string err;
const llvm::Target *target = llvm::TargetRegistry::lookupTarget(triple, err);
if (!target) {
- emitError(UnknownLoc::get(ctx)) << "no target for triple " << triple.str()
- << ": " << err;
+ emitError(UnknownLoc::get(ctx))
+ << "no target for triple " << triple.str() << ": " << err;
return {};
}
llvm::TargetOptions options;
@@ -279,7 +279,7 @@ static OwningOpRef<Operation *> translateMIRToModule(llvm::SourceMgr &sourceMgr,
llvm::MachineFunction *mf = mmi.getMachineFunction(f);
if (!mf)
continue;
- auto func = b.create<mir::FuncOp>(loc, f.getName());
+ auto func = mir::FuncOp::create(b, loc, f.getName());
Block *body = &func.getBody().emplaceBlock();
if (failed(Importer(ctx, *mf).run(body))) {
emitError(loc) << "unsupported construct while importing @"
@@ -294,7 +294,8 @@ static OwningOpRef<Operation *> translateMIRToModule(llvm::SourceMgr &sourceMgr,
namespace mlir {
void registerFromMIRTranslation() {
TranslateToMLIRRegistration registration(
- "import-mir", "Translate pre-RA LLVM MachineIR (.mir) to the MIR dialects",
+ "import-mir",
+ "Translate pre-RA LLVM MachineIR (.mir) to the MIR dialects",
[](llvm::SourceMgr &sourceMgr,
MLIRContext *ctx) -> OwningOpRef<Operation *> {
return translateMIRToModule(sourceMgr, ctx);
diff --git a/mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp b/mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp
index cf12118a14f47..94d46bef8b203 100644
--- a/mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp
+++ b/mlir/tools/mlir-tblgen/MIRGenericOpGen.cpp
@@ -7,8 +7,9 @@
//===----------------------------------------------------------------------===//
//
// A TableGen backend that reads LLVM's generic (GlobalISel) opcode definitions
-// from `GenericInstruction` records (llvm/include/llvm/Target/GenericOpcodes.td)
-// and emits MLIR ODS operation definitions for the `mir` dialect.
+// from `GenericInstruction` records
+// (llvm/include/llvm/Target/GenericOpcodes.td) and emits MLIR ODS operation
+// definitions for the `mir` dialect.
//
// Each `G_*` record becomes an op `mir.g_*` derived from the `MIR_GenericOp`
// base class. Generic-type operands/results (type0/ptype0/...) map onto the
@@ -48,8 +49,8 @@ static bool getBitOrFalse(const Record &record, llvm::StringRef field) {
/// generated ODS accessors, appending `_` to C++ keywords.
static std::string sanitizeName(llvm::StringRef name) {
static const char *kKeywords[] = {
- "register", "int", "float", "double", "char", "bool",
- "void", "class", "struct", "const", "static", "new",
+ "register", "int", "float", "double", "char", "bool",
+ "void", "class", "struct", "const", "static", "new",
"delete", "operator", "template", "default", "return"};
for (const char *kw : kKeywords)
if (name == kw)
@@ -77,7 +78,7 @@ static bool appendArg(llvm::StringRef defName, llvm::StringRef rawName,
}
// Immediate / opaque placeholders become attributes.
if (defName == "unknown" || defName.ends_with("imm") ||
- defName.starts_with("untyped_imm") || defName.starts_with("i") ) {
+ defName.starts_with("untyped_imm") || defName.starts_with("i")) {
attributes.push_back(("AnyAttr:$" + argName));
return true;
}
@@ -121,7 +122,8 @@ static bool emitGenericOp(const Record &record, llvm::raw_ostream &os) {
return true;
};
- if (!handleDag(outs, /*isResult=*/true) || !handleDag(ins, /*isResult=*/false))
+ if (!handleDag(outs, /*isResult=*/true) ||
+ !handleDag(ins, /*isResult=*/false))
return false;
// Traits.
@@ -167,7 +169,8 @@ static bool emitGenericOps(const RecordKeeper &records, llvm::raw_ostream &os) {
os << "include \"mlir/Dialect/MIR/IR/MIRTypes.td\"\n";
os << "include \"mlir/Interfaces/SideEffectInterfaces.td\"\n\n";
unsigned emitted = 0, skipped = 0;
- for (const Record *r : records.getAllDerivedDefinitions("GenericInstruction")) {
+ for (const Record *r :
+ records.getAllDerivedDefinitions("GenericInstruction")) {
if (emitGenericOp(*r, os))
++emitted;
else {
diff --git a/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp b/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
index 72459c6eb0632..553c82b991afb 100644
--- a/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
+++ b/mlir/tools/mlir-tblgen/MIRTargetOpGen.cpp
@@ -43,11 +43,9 @@ static llvm::cl::opt<std::string>
"(e.g. AArch64)"),
llvm::cl::init("AArch64"), llvm::cl::cat(targetOpCat));
-static llvm::cl::opt<std::string>
- dialectClass("mir-target-opbase",
- llvm::cl::desc("ODS base class for the generated ops"),
- llvm::cl::init("AArch64MIR_TargetOp"),
- llvm::cl::cat(targetOpCat));
+static llvm::cl::opt<std::string> dialectClass(
+ "mir-target-opbase", llvm::cl::desc("ODS base class for the generated ops"),
+ llvm::cl::init("AArch64MIR_TargetOp"), llvm::cl::cat(targetOpCat));
static llvm::cl::opt<bool> emitLowering(
"mir-emit-lowering",
@@ -101,11 +99,11 @@ static std::string sanitizeIdent(llvm::StringRef name) {
if (out.empty() || !llvm::isAlpha(out[0]))
out = "op_" + out;
static const char *kReserved[] = {
- "and", "and_eq", "bitand", "bitor", "compl", "not", "not_eq",
- "or", "or_eq", "xor", "xor_eq", "int", "float", "double",
- "char", "bool", "void", "class", "struct", "const", "static",
- "new", "delete", "operator", "template", "default", "return",
- "register"};
+ "and", "and_eq", "bitand", "bitor", "compl", "not",
+ "not_eq", "or", "or_eq", "xor", "xor_eq", "int",
+ "float", "double", "char", "bool", "void", "class",
+ "struct", "const", "static", "new", "delete", "operator",
+ "template", "default", "return", "register"};
for (const char *kw : kReserved)
if (out == kw)
return out + "_";
@@ -115,9 +113,9 @@ static std::string sanitizeIdent(llvm::StringRef name) {
namespace {
/// Accumulated information for one mnemonic cluster.
struct Cluster {
- bool anyResults = false; // some variant defines results
- bool anyOperands = false; // some variant takes inputs
- bool allPure = true; // every variant is side-effect free
+ bool anyResults = false; // some variant defines results
+ bool anyOperands = false; // some variant takes inputs
+ bool allPure = true; // every variant is side-effect free
bool anyCommutable = false;
llvm::SmallVector<std::string> opcodes; // concrete record names subsumed
};
@@ -127,7 +125,7 @@ struct Cluster {
static unsigned numDagArgs(const Record &record, llvm::StringRef field) {
if (const auto *dag = llvm::dyn_cast_or_null<llvm::DagInit>(
record.getValue(field) ? record.getValue(field)->getValue()
- : nullptr))
+ : nullptr))
return dag->getNumArgs();
return 0;
}
@@ -140,6 +138,9 @@ static bool emitTargetOps(const RecordKeeper &records, llvm::raw_ostream &os) {
os << "include \"mlir/Dialect/MIR/IR/MIRTypes.td\"\n";
os << "include \"mlir/Interfaces/SideEffectInterfaces.td\"\n\n";
}
+ // The lowering table is a generated data table; keep clang-format off it.
+ if (emitLowering)
+ os << "// clang-format off\n";
// Cluster instructions by mnemonic, preserving first-seen order.
llvm::StringMap<unsigned> clusterIndex;
@@ -199,8 +200,8 @@ static bool emitTargetOps(const RecordKeeper &records, llvm::raw_ostream &os) {
if (c.anyCommutable)
traits.push_back("Commutative");
- os << "def " << targetNamespace << "MIR_" << ident << " : "
- << dialectClass << "<\"" << opName << "\", [";
+ os << "def " << targetNamespace << "MIR_" << ident << " : " << dialectClass
+ << "<\"" << opName << "\", [";
llvm::interleaveComma(traits, os);
os << "]> {\n";
os << " let arguments = (ins Variadic<MIR_AnyLLT>:$srcs,\n"
@@ -214,6 +215,9 @@ static bool emitTargetOps(const RecordKeeper &records, llvm::raw_ostream &os) {
++emitted;
}
+ // Note: in lowering mode the whole file stays under `clang-format off`
+ // (opened above); it is #included inside an array initializer, so we do not
+ // re-enable formatting for the trailing summary comment.
os << "// Considered " << considered << " instructions, emitted " << emitted
<< " ops across " << clusters.size() << " mnemonics.\n";
return false;
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