[Mlir-commits] [mlir] 3bc32da - [MLIR] Remove VP intrinsic intregration test. NFC (#218087)

[llvmlistbot at llvm.org]

Author: Luke Lau
Date: 2026-08-22T10:13:44+08:00
New Revision: 3bc32dabccc8175f47671fdd678c6ec28c9906a0

URL: https://github.com/llvm/llvm-project/commit/3bc32dabccc8175f47671fdd678c6ec28c9906a0
DIFF: https://github.com/llvm/llvm-project/commit/3bc32dabccc8175f47671fdd678c6ec28c9906a0.diff

LOG: [MLIR] Remove VP intrinsic intregration test. NFC (#218087)

Fixes the buildbot failure in
https://lab.llvm.org/buildbot/#/builders/177/builds/39732.
vp.add has been removed in #217863 so this just removes the test.

This essentially reverts commit
ee82b864f2086f944f046bd00b03f30697403f8a.

Added: 
    

Modified: 
    mlir/test/lit.site.cfg.py.in

Removed: 
    mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg
    mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir


################################################################################
diff  --git a/mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg b/mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg
deleted file mode 100644
index 3214a1101f084..0000000000000
--- a/mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg
+++ /dev/null
@@ -1,22 +0,0 @@
-import sys
-
-lli_cmd = "lli"
-if config.riscv_emulator_lli_executable:
-    lli_cmd = config.riscv_emulator_lli_executable
-
-config.substitutions.append(
-    (
-        "%mlir_native_utils_lib_dir",
-        config.riscv_emulator_utils_lib_dir or config.mlir_lib_dir,
-    )
-)
-
-if config.riscv_vector_emulator_executable:
-    # Run test in qemu emulator.
-    emulation_cmd = config.riscv_vector_emulator_executable
-    if config.riscv_vector_emulator_options:
-        emulation_cmd = emulation_cmd + " " + config.riscv_vector_emulator_options
-    emulation_cmd = emulation_cmd + " " + lli_cmd + " --march=riscv64 -mattr=+v "
-    config.substitutions.append(("%lli", emulation_cmd))
-else:
-    config.substitutions.append(("%lli", lli_cmd))

diff  --git a/mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir b/mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir
deleted file mode 100644
index 84270ee132231..0000000000000
--- a/mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir
+++ /dev/null
@@ -1,36 +0,0 @@
-// RUN: mlir-opt %s -convert-vector-to-scf -convert-scf-to-cf -convert-cf-to-llvm \
-// RUN: -convert-vector-to-llvm -convert-index-to-llvm -finalize-memref-to-llvm -convert-func-to-llvm -convert-arith-to-llvm \
-// RUN: -reconcile-unrealized-casts | \
-// RUN: mlir-translate -mlir-to-llvmir | \
-// RUN: %lli --entry-function=entry \
-// RUN:      --dlopen=%mlir_native_utils_lib_dir/libmlir_c_runner_utils%shlibext | \
-// RUN: FileCheck %s
-
-// %mlir_native_utils_lib_dir is incorrect on Windows
-// UNSUPPORTED: system-windows
-
-memref.global "private" @gv_i32 : memref<20xi32> =
-    dense<[0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
-           10, 11, 12, 13, 14, 15, 16, 17, 18, 19]>
-
-func.func @entry() -> i32 {
-  %c0 = arith.constant 0 : index
-  %c10 = arith.constant 10 : index
-  %mem_i32 = memref.get_global @gv_i32 : memref<20xi32>
-  // When the vectors are defined as dense constant vector,
-  // the vp intrinsic will be optimized/eliminated on some backend (e.g. X86).
-  // So this test case loads the vector from a memref to test the vp intrinsic
-  // backend support.
-  %vec1 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<8xi32>
-  %vec2 = vector.load %mem_i32[%c10] : memref<20xi32>, vector<8xi32>
-  %mask = arith.constant dense<[1, 0, 1, 0, 1, 0, 1, 0]> : vector<8xi1>
-  %evl = arith.constant 4 : i32
-
-  %res = "llvm.intr.vp.add" (%vec1, %vec2, %mask, %evl) :
-         (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
-  vector.print %res : vector<8xi32>
-  // CHECK: ( 10, {{.*}}, 14, {{.*}}, {{.*}}, {{.*}}, {{.*}}, {{.*}} )
-
-  %ret = arith.constant 0 : i32
-  return %ret : i32
-}

diff  --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 3c25123f630fa..76dab98e2b51e 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -60,7 +60,6 @@ config.mlir_run_arm_neon_tests = @MLIR_RUN_ARM_NEON_TESTS@
 if config.mlir_run_arm_neon_tests:
     config.available_features.add("mlir_arm_neon_tests")
 config.mlir_run_x86_tests = @MLIR_RUN_X86_TESTS@
-config.mlir_run_riscv_vector_tests = "@MLIR_RUN_RISCV_VECTOR_TESTS@"
 config.mlir_run_cuda_tensor_core_tests = @MLIR_RUN_CUDA_TENSOR_CORE_TESTS@
 config.mlir_run_cuda_sm80_tests = @MLIR_RUN_CUDA_SM80_TESTS@
 config.mlir_run_cuda_sm80_lt_tests = @MLIR_RUN_CUDA_SM80_LT_TESTS@
@@ -78,10 +77,6 @@ config.arm_emulator_mlir_runner_executable = "@ARM_EMULATOR_MLIR_RUNNER_EXECUTAB
 config.arm_emulator_lli_executable = "@ARM_EMULATOR_LLI_EXECUTABLE@"
 config.arm_emulator_utils_lib_dir = "@ARM_EMULATOR_UTILS_LIB_DIR@"
 config.arm_sme_abi_routines_shlib = "@ARM_SME_ABI_ROUTINES_SHLIB@"
-config.riscv_vector_emulator_executable = "@RISCV_VECTOR_EMULATOR_EXECUTABLE@"
-config.riscv_vector_emulator_options = "@RISCV_VECTOR_EMULATOR_OPTIONS@"
-config.riscv_emulator_lli_executable = "@RISCV_EMULATOR_LLI_EXECUTABLE@"
-config.riscv_emulator_utils_lib_dir = "@RISCV_EMULATOR_UTILS_LIB_DIR@"
 
 import lit.llvm
 lit.llvm.initialize(lit_config, config)