[Mlir-commits] [llvm] [mlir] [IR] Remove trivial VP intrinsics. NFC (PR #217863)
Luke Lau
llvmlistbot at llvm.org
Fri Aug 21 09:03:10 PDT 2026
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/217863
>From 7df17e9620000e67dcd728a09861535010ecfa13 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Thu, 20 Aug 2026 15:47:51 +0800
Subject: [PATCH 1/2] [IR] Remove trivial VP intrinsics. NFC
Trivial VP intrinsics are now all autoupgraded to their non-VP counterparts, so the intrinsics themselves are dead.
This removes the intrinsics and their corresponding LangRef definitions, as well as the VPIntrinsic subclasses and some methods in ExpandVectorPredication which are now dead. Removing the SDNodes is deferred to a separate patch.
---
llvm/docs/LangRef.md | 4189 +++--------------
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 24 +-
llvm/include/llvm/IR/IntrinsicInst.h | 57 -
llvm/include/llvm/IR/Intrinsics.td | 318 +-
llvm/include/llvm/IR/VPIntrinsics.def | 240 +-
llvm/lib/Analysis/ValueTracking.cpp | 4 +-
llvm/lib/Analysis/VectorUtils.cpp | 10 -
llvm/lib/CodeGen/ExpandVectorPredication.cpp | 172 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 45 -
.../SelectionDAG/SelectionDAGBuilder.h | 1 -
llvm/lib/IR/IntrinsicInst.cpp | 88 +-
llvm/lib/IR/Verifier.cpp | 57 -
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 54 -
.../mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td | 72 -
14 files changed, 835 insertions(+), 4496 deletions(-)
diff --git a/llvm/docs/LangRef.md b/llvm/docs/LangRef.md
index 82eebd26c0054..886b6e98ef54f 100644
--- a/llvm/docs/LangRef.md
+++ b/llvm/docs/LangRef.md
@@ -21872,56 +21872,6 @@ The use of an effective %evl is discouraged for those targets. The function
`TargetTransformInfo::hasActiveVectorLength()` returns true when the target
has native support for %evl.
-(int_vp_select)=
-
-#### '`llvm.vp.select.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.select.v16i32 (<16 x i1> <condition>, <16 x i32> <on_true>, <16 x i32> <on_false>, i32 <evl>)
-declare <vscale x 4 x i64> @llvm.vp.select.nxv4i64 (<vscale x 4 x i1> <condition>, <vscale x 4 x i64> <on_true>, <vscale x 4 x i64> <on_false>, i32 <evl>)
-```
-
-##### Overview:
-
-The '`llvm.vp.select`' intrinsic is used to choose one value based on a
-condition vector, without IR-level branching.
-
-##### Arguments:
-
-The first argument is a vector of `i1` and indicates the condition. The
-second argument is the value that is selected where the condition vector is
-true. The third argument is the value that is selected where the condition
-vector is false. The vectors must be of the same size. The fourth argument is
-the explicit vector length.
-
-1. The optional `fast-math flags` marker indicates that the select has one or
- more {ref}`fast-math flags <fastmath>`. These are optimization hints to
- enable otherwise unsafe floating-point optimizations. Fast-math flags are
- only valid for selects that return {ref}`supported floating-point types <fastmath_return_types>`.
-
-##### Semantics:
-
-The intrinsic selects lanes from the second and third argument depending on a
-condition vector.
-
-All result lanes at positions greater or equal than `%evl` are undefined.
-For all lanes below `%evl` where the condition vector is true the lane is
-taken from the second argument. Otherwise, the lane is taken from the third
-argument.
-
-##### Example:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.select.v4i32(<4 x i1> %cond, <4 x i32> %on_true, <4 x i32> %on_false, i32 %evl)
-
-;;; Expansion.
-;; Any result is legal on lanes at and above %evl.
-%also.r = select <4 x i1> %cond, <4 x i32> %on_true, <4 x i32> %on_false
-```
-
(int_vp_merge)=
#### '`llvm.vp.merge.*`' Intrinsics
@@ -21975,128 +21925,6 @@ is taken from the third argument.
%also.r = select <4 x i1> %mergemask, <4 x i32> %on_true, <4 x i32> %on_false
```
-(int_vp_add)=
-
-#### '`llvm.vp.add.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.add.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.add.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.add.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated integer addition of two vectors of integers.
-
-
-##### Arguments:
-
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.add`' intrinsic performs integer addition ({ref}`add <i_add>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = add <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_sub)=
-
-#### '`llvm.vp.sub.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.sub.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.sub.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.sub.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated integer subtraction of two vectors of integers.
-
-
-##### Arguments:
-
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.sub`' intrinsic performs integer subtraction
-({ref}`sub <i_sub>`) of the first and second vector arguments on each enabled
-lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = sub <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_mul)=
-
-#### '`llvm.vp.mul.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.mul.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.mul.nxv46i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.mul.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated integer multiplication of two vectors of integers.
-
-
-##### Arguments:
-
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-The '`llvm.vp.mul`' intrinsic performs integer multiplication
-({ref}`mul <i_mul>`) of the first and second vector arguments on each enabled
-lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.mul.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = mul <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
(int_vp_sdiv)=
#### '`llvm.vp.sdiv.*`' Intrinsics
@@ -22261,3876 +22089,1315 @@ lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
```
-(int_vp_ashr)=
+(int_vp_reduce_add)=
-#### '`llvm.vp.ashr.*`' Intrinsics
+#### '`llvm.vp.reduce.add.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.ashr.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.ashr.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.add.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.add.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Vector-predicated arithmetic right-shift.
-
+Predicated integer `ADD` reduction of a vector and a scalar starting value,
+returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.ashr`' intrinsic computes the arithmetic right shift
-({ref}`ashr <i_ashr>`) of the first argument by the second argument on each
-enabled lane. The result on disabled lanes is a
-{ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.add`' intrinsic performs the integer `ADD` reduction
+({ref}`llvm.vector.reduce.add <int_vector_reduce_add>`) of the vector argument
+`val` on each enabled lane, adding it to the scalar `start_value`. Disabled
+lanes are treated as containing the neutral value `0` (i.e., having no effect
+on the reduction operation). If the vector length is zero, the result is equal
+to `start_value`.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i32 @llvm.vp.reduce.add.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = ashr <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> zeroinitializer
+%reduction = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %masked.a)
+%also.r = add i32 %reduction, %start
```
-(int_vp_lshr)=
-
+(int_vp_reduce_fadd)=
-#### '`llvm.vp.lshr.*`' Intrinsics
+#### '`llvm.vp.reduce.fadd.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.lshr.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.lshr.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.lshr.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare float @llvm.vp.reduce.fadd.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare double @llvm.vp.reduce.fadd.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Vector-predicated logical right-shift.
-
+Predicated floating-point `ADD` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
+The first argument is the start value of the reduction, which must be a scalar
+floating-point type equal to the result type. The second argument is the vector
+on which the reduction is performed and must be a vector of floating-point
+values whose element type is the result/start type. The third argument is the
+vector mask and is a vector of boolean values with the same number of elements
+as the vector argument. The fourth argument is the explicit vector length of the
operation.
##### Semantics:
-The '`llvm.vp.lshr`' intrinsic computes the logical right shift
-({ref}`lshr <i_lshr>`) of the first argument by the second argument on each
-enabled lane. The result on disabled lanes is a
-{ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.fadd`' intrinsic performs the floating-point `ADD`
+reduction ({ref}`llvm.vector.reduce.fadd <int_vector_reduce_fadd>`) of the
+vector argument `val` on each enabled lane, adding it to the scalar
+`start_value`. Disabled lanes are treated as containing the neutral value
+`-0.0` (i.e., having no effect on the reduction operation). If no lanes are
+enabled, the resulting value will be equal to `start_value`.
+
+To ignore the start value, the neutral value can be used.
+
+See the unpredicated version ({ref}`llvm.vector.reduce.fadd <int_vector_reduce_fadd>`) for more detail on the semantics of the reduction.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call float @llvm.vp.reduce.fadd.v4f32(float %start, <4 x float> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = lshr <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>
+%also.r = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %masked.a)
```
-(int_vp_shl)=
+(int_vp_reduce_mul)=
-#### '`llvm.vp.shl.*`' Intrinsics
+#### '`llvm.vp.reduce.mul.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.shl.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.shl.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.shl.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.mul.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.mul.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Vector-predicated left shift.
+Predicated integer `MUL` reduction of a vector and a scalar starting value,
+returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.shl`' intrinsic computes the left shift ({ref}`shl <i_shl>`) of
-the first argument by the second argument on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.mul`' intrinsic performs the integer `MUL` reduction
+({ref}`llvm.vector.reduce.mul <int_vector_reduce_mul>`) of the vector argument `val`
+on each enabled lane, multiplying it by the scalar `start_value`. Disabled
+lanes are treated as containing the neutral value `1` (i.e., having no effect
+on the reduction operation). If the vector length is zero, the result is the
+start value.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i32 @llvm.vp.reduce.mul.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = shl <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+%reduction = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %masked.a)
+%also.r = mul i32 %reduction, %start
```
-(int_vp_or)=
+(int_vp_reduce_fmul)=
-#### '`llvm.vp.or.*`' Intrinsics
+#### '`llvm.vp.reduce.fmul.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.or.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.or.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.or.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare float @llvm.vp.reduce.fmul.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare double @llvm.vp.reduce.fmul.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Vector-predicated or.
+Predicated floating-point `MUL` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
+The first argument is the start value of the reduction, which must be a scalar
+floating-point type equal to the result type. The second argument is the vector
+on which the reduction is performed and must be a vector of floating-point
+values whose element type is the result/start type. The third argument is the
+vector mask and is a vector of boolean values with the same number of elements
+as the vector argument. The fourth argument is the explicit vector length of the
operation.
##### Semantics:
-The '`llvm.vp.or`' intrinsic performs a bitwise or ({ref}`or <i_or>`) of the
-first two arguments on each enabled lane. The result on disabled lanes is
-a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.fmul`' intrinsic performs the floating-point `MUL`
+reduction ({ref}`llvm.vector.reduce.fmul <int_vector_reduce_fmul>`) of the
+vector argument `val` on each enabled lane, multiplying it by the scalar
+`start_value`. Disabled lanes are treated as containing the neutral value
+`1.0` (i.e., having no effect on the reduction operation). If no lanes are
+enabled, the resulting value will be equal to the starting value.
+
+To ignore the start value, the neutral value can be used.
+
+See the unpredicated version ({ref}`llvm.vector.reduce.fmul <int_vector_reduce_fmul>`) for more detail on the semantics.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call float @llvm.vp.reduce.fmul.v4f32(float %start, <4 x float> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = or <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>
+%also.r = call float @llvm.vector.reduce.fmul.v4f32(float %start, <4 x float> %masked.a)
```
-(int_vp_and)=
+(int_vp_reduce_and)=
-#### '`llvm.vp.and.*`' Intrinsics
+#### '`llvm.vp.reduce.and.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.and.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.and.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.and.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.and.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.and.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Vector-predicated and.
+Predicated integer `AND` reduction of a vector and a scalar starting value,
+returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.and`' intrinsic performs a bitwise and ({ref}`and <i_or>`) of
-the first two arguments on each enabled lane. The result on disabled lanes is
-a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.and`' intrinsic performs the integer `AND` reduction
+({ref}`llvm.vector.reduce.and <int_vector_reduce_and>`) of the vector argument
+`val` on each enabled lane, performing an '`and`' of that with with the
+scalar `start_value`. Disabled lanes are treated as containing the neutral
+value `UINT_MAX`, or `-1` (i.e., having no effect on the reduction
+operation). If the vector length is zero, the result is the start value.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i32 @llvm.vp.reduce.and.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = and <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
+%reduction = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %masked.a)
+%also.r = and i32 %reduction, %start
```
-(int_vp_xor)=
+(int_vp_reduce_or)=
-#### '`llvm.vp.xor.*`' Intrinsics
+#### '`llvm.vp.reduce.or.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.xor.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.xor.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.xor.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.or.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.or.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Vector-predicated, bitwise xor.
+Predicated integer `OR` reduction of a vector and a scalar starting value,
+returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.xor`' intrinsic performs a bitwise xor ({ref}`xor <i_xor>`) of
-the first two arguments on each enabled lane.
-The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.or`' intrinsic performs the integer `OR` reduction
+({ref}`llvm.vector.reduce.or <int_vector_reduce_or>`) of the vector argument
+`val` on each enabled lane, performing an '`or`' of that with the scalar
+`start_value`. Disabled lanes are treated as containing the neutral value
+`0` (i.e., having no effect on the reduction operation). If the vector length
+is zero, the result is the start value.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i32 @llvm.vp.reduce.or.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = xor <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
+%reduction = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %masked.a)
+%also.r = or i32 %reduction, %start
```
-(int_vp_abs)=
+(int_vp_reduce_xor)=
-#### '`llvm.vp.abs.*`' Intrinsics
+#### '`llvm.vp.reduce.xor.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.abs.v16i32 (<16 x i32> <op>, i1 <is_int_min_poison>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.abs.nxv4i32 (<vscale x 4 x i32> <op>, i1 <is_int_min_poison>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.abs.v256i64 (<256 x i64> <op>, i1 <is_int_min_poison>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.xor.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.xor.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated abs of a vector of integers.
+Predicated integer `XOR` reduction of a vector and a scalar starting value,
+returning the result as a scalar.
##### Arguments:
-The first argument and the result have the same vector of integer type. The
-second argument must be a constant and is a flag to indicate whether the result
-value of the '`llvm.vp.abs`' intrinsic is a {ref}`poison value <poisonvalues>`
-if the first argument is statically or dynamically an `INT_MIN` value. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.abs`' intrinsic performs abs ({ref}`abs <int_abs>`) of the first argument on each
-enabled lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.xor`' intrinsic performs the integer `XOR` reduction
+({ref}`llvm.vector.reduce.xor <int_vector_reduce_xor>`) of the vector argument
+`val` on each enabled lane, performing an '`xor`' of that with the scalar
+`start_value`. Disabled lanes are treated as containing the neutral value
+`0` (i.e., having no effect on the reduction operation). If the vector length
+is zero, the result is the start value.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %a, i1 false, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i32 @llvm.vp.reduce.xor.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
+%reduction = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %masked.a)
+%also.r = xor i32 %reduction, %start
```
-(int_vp_smax)=
+(int_vp_reduce_smax)=
-#### '`llvm.vp.smax.*`' Intrinsics
+#### '`llvm.vp.reduce.smax.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.smax.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.smax.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.smax.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.smax.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.smax.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated integer signed maximum of two vectors of integers.
+Predicated signed-integer `MAX` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.smax`' intrinsic performs integer signed maximum ({ref}`smax <int_smax>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.smax`' intrinsic performs the signed-integer `MAX`
+reduction ({ref}`llvm.vector.reduce.smax <int_vector_reduce_smax>`) of the
+vector argument `val` on each enabled lane, and taking the maximum of that and
+the scalar `start_value`. Disabled lanes are treated as containing the
+neutral value `INT_MIN` (i.e., having no effect on the reduction operation).
+If the vector length is zero, the result is the start value.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.smax.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i8 @llvm.vp.reduce.smax.v4i8(i8 %start, <4 x i8> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %b)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i8> %a, <4 x i8> <i8 -128, i8 -128, i8 -128, i8 -128>
+%reduction = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %masked.a)
+%also.r = call i8 @llvm.smax.i8(i8 %reduction, i8 %start)
```
-(int_vp_smin)=
+(int_vp_reduce_smin)=
-#### '`llvm.vp.smin.*`' Intrinsics
+#### '`llvm.vp.reduce.smin.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.smin.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.smin.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.smin.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.smin.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.smin.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated integer signed minimum of two vectors of integers.
+Predicated signed-integer `MIN` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.smin`' intrinsic performs integer signed minimum ({ref}`smin <int_smin>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.smin`' intrinsic performs the signed-integer `MIN`
+reduction ({ref}`llvm.vector.reduce.smin <int_vector_reduce_smin>`) of the
+vector argument `val` on each enabled lane, and taking the minimum of that and
+the scalar `start_value`. Disabled lanes are treated as containing the
+neutral value `INT_MAX` (i.e., having no effect on the reduction operation).
+If the vector length is zero, the result is the start value.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.smin.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i8 @llvm.vp.reduce.smin.v4i8(i8 %start, <4 x i8> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %b)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i8> %a, <4 x i8> <i8 127, i8 127, i8 127, i8 127>
+%reduction = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %masked.a)
+%also.r = call i8 @llvm.smin.i8(i8 %reduction, i8 %start)
```
-(int_vp_umax)=
+(int_vp_reduce_umax)=
-#### '`llvm.vp.umax.*`' Intrinsics
+#### '`llvm.vp.reduce.umax.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.umax.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.umax.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.umax.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.umax.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.umax.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated integer unsigned maximum of two vectors of integers.
+Predicated unsigned-integer `MAX` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.umax`' intrinsic performs integer unsigned maximum ({ref}`umax <int_umax>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.umax`' intrinsic performs the unsigned-integer `MAX`
+reduction ({ref}`llvm.vector.reduce.umax <int_vector_reduce_umax>`) of the
+vector argument `val` on each enabled lane, and taking the maximum of that and
+the scalar `start_value`. Disabled lanes are treated as containing the
+neutral value `0` (i.e., having no effect on the reduction operation). If the
+vector length is zero, the result is the start value.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i32 @llvm.vp.reduce.umax.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %b)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
+%reduction = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %masked.a)
+%also.r = call i32 @llvm.umax.i32(i32 %reduction, i32 %start)
```
-(int_vp_umin)=
+(int_vp_reduce_umin)=
-#### '`llvm.vp.umin.*`' Intrinsics
+#### '`llvm.vp.reduce.umin.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.umin.v16i32 (<16 x i32> <left_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.umin.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.umin.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.reduce.umin.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare i16 @llvm.vp.reduce.umin.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated integer unsigned minimum of two vectors of integers.
+Predicated unsigned-integer `MIN` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the start value of the reduction, which must be a scalar
+integer type equal to the result type. The second argument is the vector on
+which the reduction is performed and must be a vector of integer values whose
+element type is the result/start type. The third argument is the vector mask and
+is a vector of boolean values with the same number of elements as the vector
+argument. The fourth argument is the explicit vector length of the operation.
##### Semantics:
-The '`llvm.vp.umin`' intrinsic performs integer unsigned minimum ({ref}`umin <int_umin>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.vp.reduce.umin`' intrinsic performs the unsigned-integer `MIN`
+reduction ({ref}`llvm.vector.reduce.umin <int_vector_reduce_umin>`) of the
+vector argument `val` on each enabled lane, taking the minimum of that and the
+scalar `start_value`. Disabled lanes are treated as containing the neutral
+value `UINT_MAX`, or `-1` (i.e., having no effect on the reduction
+operation). If the vector length is zero, the result is the start value.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x i32> @llvm.vp.umin.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call i32 @llvm.vp.reduce.umin.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %b)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
+%reduction = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %masked.a)
+%also.r = call i32 @llvm.umin.i32(i32 %reduction, i32 %start)
```
-(int_vp_copysign)=
+(int_vp_reduce_fmax)=
-#### '`llvm.vp.copysign.*`' Intrinsics
+#### '`llvm.vp.reduce.fmax.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x float> @llvm.vp.copysign.v16f32 (<16 x float> <mag_op>, <16 x float> <sign_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.copysign.nxv4f32 (<vscale x 4 x float> <mag_op>, <vscale x 4 x float> <sign_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.copysign.v256f64 (<256 x double> <mag_op>, <256 x double> <sign_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare float @llvm.vp.reduce.fmax.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare double @llvm.vp.reduce.fmax.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated floating-point copysign of two vectors of floating-point values.
+Predicated floating-point `MAX` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
+The first argument is the start value of the reduction, which must be a scalar
+floating-point type equal to the result type. The second argument is the vector
+on which the reduction is performed and must be a vector of floating-point
+values whose element type is the result/start type. The third argument is the
+vector mask and is a vector of boolean values with the same number of elements
+as the vector argument. The fourth argument is the explicit vector length of the
operation.
##### Semantics:
-The '`llvm.vp.copysign`' intrinsic performs floating-point copysign ({ref}`copysign <int_copysign>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
+The '`llvm.vp.reduce.fmax`' intrinsic performs the floating-point `MAX`
+reduction ({ref}`llvm.vector.reduce.fmax <int_vector_reduce_fmax>`) of the
+vector argument `val` on each enabled lane, taking the maximum of that and the
+scalar `start_value`. Disabled lanes are treated as containing the neutral
+value (i.e., having no effect on the reduction operation). If the vector length
+is zero, the result is the start value.
+
+The neutral value is dependent on the {ref}`fast-math flags <fastmath>`. If no
+flags are set, the neutral value is `-QNAN`. If `nnan` and `ninf` are
+both set, then the neutral value is the smallest floating-point value for the
+result type. If only `nnan` is set then the neutral value is `-Infinity`.
+
+This instruction has the same comparison semantics as the
+{ref}`llvm.vector.reduce.fmax <int_vector_reduce_fmax>` intrinsic (and thus the
+'`llvm.maxnum.*`' intrinsic).
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x float> @llvm.vp.copysign.v4f32(<4 x float> %mag, <4 x float> %sign, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call float @llvm.vp.reduce.fmax.v4f32(float %float, <4 x float> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x float> @llvm.copysign.v4f32(<4 x float> %mag, <4 x float> %sign)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
+%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float QNAN, float QNAN, float QNAN, float QNAN>
+%reduction = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %masked.a)
+%also.r = call float @llvm.maxnum.f32(float %reduction, float %start)
```
-(int_vp_minnum)=
+(int_vp_reduce_fmin)=
-#### '`llvm.vp.minnum.*`' Intrinsics
+#### '`llvm.vp.reduce.fmin.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x float> @llvm.vp.minnum.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.minnum.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.minnum.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare float @llvm.vp.reduce.fmin.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare double @llvm.vp.reduce.fmin.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated floating-point IEEE 754-2008 minNum of two vectors of floating-point values.
+Predicated floating-point `MIN` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
+The first argument is the start value of the reduction, which must be a scalar
+floating-point type equal to the result type. The second argument is the vector
+on which the reduction is performed and must be a vector of floating-point
+values whose element type is the result/start type. The third argument is the
+vector mask and is a vector of boolean values with the same number of elements
+as the vector argument. The fourth argument is the explicit vector length of the
operation.
##### Semantics:
-The '`llvm.vp.minnum`' intrinsic performs floating-point minimum ({ref}`minnum <i_minnum>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
+The '`llvm.vp.reduce.fmin`' intrinsic performs the floating-point `MIN`
+reduction ({ref}`llvm.vector.reduce.fmin <int_vector_reduce_fmin>`) of the
+vector argument `val` on each enabled lane, taking the minimum of that and the
+scalar `start_value`. Disabled lanes are treated as containing the neutral
+value (i.e., having no effect on the reduction operation). If the vector length
+is zero, the result is the start value.
+
+The neutral value is dependent on the {ref}`fast-math flags <fastmath>`. If no
+flags are set, the neutral value is `+QNAN`. If `nnan` and `ninf` are
+both set, then the neutral value is the largest floating-point value for the
+result type. If only `nnan` is set then the neutral value is `+Infinity`.
+
+This instruction has the same comparison semantics as the
+{ref}`llvm.vector.reduce.fmin <int_vector_reduce_fmin>` intrinsic (and thus the
+'`llvm.minnum.*`' intrinsic).
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x float> @llvm.vp.minnum.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call float @llvm.vp.reduce.fmin.v4f32(float %start, <4 x float> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
+%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float QNAN, float QNAN, float QNAN, float QNAN>
+%reduction = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %masked.a)
+%also.r = call float @llvm.minnum.f32(float %reduction, float %start)
```
-(int_vp_maxnum)=
+(int_vp_reduce_fmaximum)=
-#### '`llvm.vp.maxnum.*`' Intrinsics
+#### '`llvm.vp.reduce.fmaximum.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x float> @llvm.vp.maxnum.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.maxnum.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.maxnum.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare float @llvm.vp.reduce.fmaximum.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare double @llvm.vp.reduce.fmaximum.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated floating-point IEEE 754-2008 maxNum of two vectors of floating-point values.
+Predicated floating-point `MAX` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
##### Arguments:
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
+The first argument is the start value of the reduction, which must be a scalar
+floating-point type equal to the result type. The second argument is the vector
+on which the reduction is performed and must be a vector of floating-point
+values whose element type is the result/start type. The third argument is the
+vector mask and is a vector of boolean values with the same number of elements
+as the vector argument. The fourth argument is the explicit vector length of the
operation.
##### Semantics:
-The '`llvm.vp.maxnum`' intrinsic performs floating-point maximum ({ref}`maxnum <i_maxnum>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
+The '`llvm.vp.reduce.fmaximum`' intrinsic performs the floating-point `MAX`
+reduction ({ref}`llvm.vector.reduce.fmaximum <int_vector_reduce_fmaximum>`) of
+the vector argument `val` on each enabled lane, taking the maximum of that and
+the scalar `start_value`. Disabled lanes are treated as containing the
+neutral value (i.e., having no effect on the reduction operation). If the vector
+length is zero, the result is the start value.
+
+The neutral value is dependent on the {ref}`fast-math flags <fastmath>`. If no
+flags are set or only the `nnan` is set, the neutral value is `-Infinity`.
+If `ninf` is set, then the neutral value is the smallest floating-point value
+for the result type.
+
+This instruction has the same comparison semantics as the
+{ref}`llvm.vector.reduce.fmaximum <int_vector_reduce_fmaximum>` intrinsic (and
+thus the '`llvm.maximum.*`' intrinsic). That is, the result will always be a
+number unless any of the elements in the vector or the starting value is
+`NaN`. Namely, this intrinsic propagates `NaN`. Also, -0.0 is considered
+less than +0.0.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x float> @llvm.vp.maxnum.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call float @llvm.vp.reduce.fmaximum.v4f32(float %float, <4 x float> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
+%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float -infinity, float -infinity, float -infinity, float -infinity>
+%reduction = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %masked.a)
+%also.r = call float @llvm.maximum.f32(float %reduction, float %start)
```
-(int_vp_minimum)=
+(int_vp_reduce_fminimum)=
-#### '`llvm.vp.minimum.*`' Intrinsics
+#### '`llvm.vp.reduce.fminimum.*`' Intrinsics
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x float> @llvm.vp.minimum.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.minimum.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.minimum.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare float @llvm.vp.reduce.fminimum.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
+declare double @llvm.vp.reduce.fminimum.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated floating-point minimum of two vectors of floating-point values,
-propagating NaNs and treating -0.0 as less than +0.0.
+Predicated floating-point `MIN` reduction of a vector and a scalar starting
+value, returning the result as a scalar.
+
##### Arguments:
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
+The first argument is the start value of the reduction, which must be a scalar
+floating-point type equal to the result type. The second argument is the vector
+on which the reduction is performed and must be a vector of floating-point
+values whose element type is the result/start type. The third argument is the
+vector mask and is a vector of boolean values with the same number of elements
+as the vector argument. The fourth argument is the explicit vector length of the
operation.
##### Semantics:
-The '`llvm.vp.minimum`' intrinsic performs floating-point minimum ({ref}`minimum <i_minimum>`)
-of the first and second vector arguments on each enabled lane, the result being
-NaN if either argument is a NaN. -0.0 is considered to be less than +0.0 for this
-intrinsic. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-The operation is performed in the default floating-point environment.
+The '`llvm.vp.reduce.fminimum`' intrinsic performs the floating-point `MIN`
+reduction ({ref}`llvm.vector.reduce.fminimum <int_vector_reduce_fminimum>`) of
+the vector argument `val` on each enabled lane, taking the minimum of that and
+the scalar `start_value`. Disabled lanes are treated as containing the neutral
+value (i.e., having no effect on the reduction operation). If the vector length
+is zero, the result is the start value.
+
+The neutral value is dependent on the {ref}`fast-math flags <fastmath>`. If no
+flags are set or only the `nnan` is set, the neutral value is `+Infinity`.
+If `ninf` is set, then the neutral value is the largest floating-point value
+for the result type.
+
+This instruction has the same comparison semantics as the
+{ref}`llvm.vector.reduce.fminimum <int_vector_reduce_fminimum>` intrinsic (and
+thus the '`llvm.minimum.*`' intrinsic). That is, the result will always be a
+number unless any of the elements in the vector or the starting value is
+`NaN`. Namely, this intrinsic propagates `NaN`. Also, -0.0 is considered
+less than +0.0.
+
+To ignore the start value, the neutral value can be used.
##### Examples:
```llvm
-%r = call <4 x float> @llvm.vp.minimum.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+%r = call float @llvm.vp.reduce.fminimum.v4f32(float %start, <4 x float> %a, <4 x i1> %mask, i32 %evl)
+; %r is equivalent to %also.r, where lanes greater than or equal to %evl
+; are treated as though %mask were false for those lanes.
-%t = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
+%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float infinity, float infinity, float infinity, float infinity>
+%reduction = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %masked.a)
+%also.r = call float @llvm.minimum.f32(float %reduction, float %start)
```
-(int_vp_maximum)=
+(int_experimental_vp_splice)=
-#### '`llvm.vp.maximum.*`' Intrinsics
+#### '`llvm.experimental.vp.splice`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x float> @llvm.vp.maximum.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.maximum.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.maximum.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %vec1, <2 x double> %vec2, i32 %imm, <2 x i1> %mask, i32 %evl1, i32 %evl2)
+declare <vscale x 4 x i32> @llvm.experimental.vp.splice.nxv4i32(<vscale x 4 x i32> %vec1, <vscale x 4 x i32> %vec2, i32 %imm, <vscale x 4 x i1> %mask, i32 %evl1, i32 %evl2)
```
##### Overview:
-Predicated floating-point maximum of two vectors of floating-point values,
-propagating NaNs and treating -0.0 as less than +0.0.
+The '`llvm.experimental.vp.splice.*`' intrinsic is the vector length
+predicated version of the '`llvm.vector.splice.*`' intrinsic.
##### Arguments:
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The result and the first two arguments `vec1` and `vec2` are vectors with
+the same type. The third argument `imm` is an immediate signed integer that
+indicates the offset index. The fourth argument `mask` is a vector mask and
+has the same number of elements as the result. The last two arguments `evl1`
+and `evl2` are unsigned integers indicating the explicit vector lengths of
+`vec1` and `vec2` respectively. `imm`, `evl1` and `evl2` should
+respect the following constraints: `-evl1 <= imm < evl1`, `0 <= evl1 <= VL`
+and `0 <= evl2 <= VL`, where `VL` is the runtime vector factor. If these
+constraints are not satisfied the intrinsic has undefined behavior.
##### Semantics:
-The '`llvm.vp.maximum`' intrinsic performs floating-point maximum ({ref}`maximum <i_maximum>`)
-of the first and second vector arguments on each enabled lane, the result being
-NaN if either argument is a NaN. -0.0 is considered to be less than +0.0 for this
-intrinsic. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-The operation is performed in the default floating-point environment.
+Effectively, this intrinsic concatenates `vec1[0..evl1-1]` and
+`vec2[0..evl2-1]` and creates the result vector by selecting the elements in a
+window of size `evl2`, starting at index `imm` (for a positive immediate) of
+the concatenated vector. Elements in the result vector beyond `evl2` are
+`undef`. If `imm` is negative the starting index is `evl1 + imm`. The result
+vector of active vector length `evl2` contains `evl1 - imm` (`-imm` for
+negative `imm`) elements from indices `[imm..evl1 - 1]`
+(`[evl1 + imm..evl1 -1]` for negative `imm`) of `vec1` followed by the
+first `evl2 - (evl1 - imm)` (`evl2 + imm` for negative `imm`) elements of
+`vec2`. If `evl1 - imm` (`-imm`) >= `evl2`, only the first `evl2`
+elements are considered and the remaining are `undef`. The lanes in the result
+vector disabled by `mask` are `poison`.
##### Examples:
-```llvm
-%r = call <4 x float> @llvm.vp.maximum.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
+```text
+llvm.experimental.vp.splice(<A,B,C,D>, <E,F,G,H>, 1, 2, 3); ==> <B, E, F, poison> index
+llvm.experimental.vp.splice(<A,B,C,D>, <E,F,G,H>, -2, 3, 2); ==> <B, C, poison, poison> trailing elements
```
-(int_vp_fadd)=
+(int_experimental_vp_reverse)=
+
-#### '`llvm.vp.fadd.*`' Intrinsics
+#### '`llvm.experimental.vp.reverse`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x float> @llvm.vp.fadd.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.fadd.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.fadd.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare <2 x double> @llvm.experimental.vp.reverse.v2f64(<2 x double> %vec, <2 x i1> %mask, i32 %evl)
+declare <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> %vec, <vscale x 4 x i1> %mask, i32 %evl)
```
##### Overview:
-Predicated floating-point addition of two vectors of floating-point values.
-
+The '`llvm.experimental.vp.reverse.*`' intrinsic is the vector length
+predicated version of the '`llvm.vector.reverse.*`' intrinsic.
##### Arguments:
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The result and the first argument `vec` are vectors with the same type.
+The second argument `mask` is a vector mask and has the same number of
+elements as the result. The third argument is the explicit vector length of
+the operation.
##### Semantics:
-The '`llvm.vp.fadd`' intrinsic performs floating-point addition ({ref}`fadd <i_fadd>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.fadd.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fadd <4 x float> %a, %b
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
+This intrinsic reverses the order of the first `evl` elements in a vector.
+The lanes in the result vector disabled by `mask` are `poison`. The
+elements past `evl` are poison.
-(int_vp_fsub)=
+(int_vp_load)=
-#### '`llvm.vp.fsub.*`' Intrinsics
+#### '`llvm.vp.load`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x float> @llvm.vp.fsub.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.fsub.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.fsub.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare <4 x float> @llvm.vp.load.v4f32.p0(ptr %ptr, <4 x i1> %mask, i32 %evl)
+declare <vscale x 2 x i16> @llvm.vp.load.nxv2i16.p0(ptr %ptr, <vscale x 2 x i1> %mask, i32 %evl)
+declare <8 x float> @llvm.vp.load.v8f32.p1(ptr addrspace(1) %ptr, <8 x i1> %mask, i32 %evl)
+declare <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p6(ptr addrspace(6) %ptr, <vscale x 1 x i1> %mask, i32 %evl)
```
##### Overview:
-Predicated floating-point subtraction of two vectors of floating-point values.
-
+The '`llvm.vp.load.*`' intrinsic is the vector length predicated version of
+the {ref}`llvm.masked.load <int_mload>` intrinsic.
##### Arguments:
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the base pointer for the load. The second argument is a
+vector of boolean values with the same number of elements as the return type.
+The third is the explicit vector length of the operation. The return type and
+underlying type of the base pointer are the same vector types.
+
+The {ref}`align <attr_align>` parameter attribute can be provided for the first
+argument.
##### Semantics:
-The '`llvm.vp.fsub`' intrinsic performs floating-point subtraction ({ref}`fsub <i_fsub>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
+The '`llvm.vp.load`' intrinsic reads a vector from memory in the same way as
+the '`llvm.masked.load`' intrinsic, where the mask is taken from the
+combination of the '`mask`' and '`evl`' arguments in the usual VP way.
+Certain '`llvm.masked.load`' arguments do not have corresponding arguments in
+'`llvm.vp.load`': the '`passthru`' argument is implicitly `poison`; the
+'`alignment`' argument is taken as the `align` parameter attribute, if
+provided. The default alignment is taken as the ABI alignment of the return
+type as specified by the {ref}`datalayout string<langref_datalayout>`.
##### Examples:
-```llvm
-%r = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
+```text
+%r = call <8 x i8> @llvm.vp.load.v8i8.p0(ptr align 2 %ptr, <8 x i1> %mask, i32 %evl)
;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-%t = fsub <4 x float> %a, %b
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
+%also.r = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr align 2 %ptr, <8 x i1> %mask, <8 x i8> poison)
```
-(int_vp_fmul)=
+(int_vp_load_ff)=
-#### '`llvm.vp.fmul.*`' Intrinsics
+#### '`llvm.vp.load.ff`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x float> @llvm.vp.fmul.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.fmul.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.fmul.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare {<4 x float>, i32} @llvm.vp.load.ff.v4f32.p0(ptr %ptr, <4 x i1> %mask, i32 %evl)
+declare {<vscale x 2 x i16>, i32} @llvm.vp.load.ff.nxv2i16.p0(ptr %ptr, <vscale x 2 x i1> %mask, i32 %evl)
+declare {<8 x float>, i32} @llvm.vp.load.ff.v8f32.p1(ptr addrspace(1) %ptr, <8 x i1> %mask, i32 %evl)
+declare {<vscale x 1 x i64>, i32} @llvm.vp.load.ff.nxv1i64.p6(ptr addrspace(6) %ptr, <vscale x 1 x i1> %mask, i32 %evl)
```
##### Overview:
-Predicated floating-point multiplication of two vectors of floating-point values.
-
+The '`llvm.vp.load.ff.*`' intrinsic is similar to
+'`llvm.vp.load.*`', but will not trap if there are not `evl` readable
+lanes at the pointer. '`ff`' stands for first-fault or fault-only-first.
##### Arguments:
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the base pointer for the load. The second argument is a
+vector of boolean values with the same number of elements as the first return
+type. The third is the explicit vector length of the operation. The first
+return type and underlying type of the base pointer are the same vector types.
+
+The {ref}`align <attr_align>` parameter attribute can be provided for the first
+argument.
##### Semantics:
-The '`llvm.vp.fmul`' intrinsic performs floating-point multiplication ({ref}`fmul <i_fmul>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.fmul.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fmul <4 x float> %a, %b
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_fdiv)=
-
-#### '`llvm.vp.fdiv.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.fdiv.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.fdiv.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.fdiv.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point division of two vectors of floating-point values.
-
-
-##### Arguments:
-
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.fdiv`' intrinsic performs floating-point division ({ref}`fdiv <i_fdiv>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fdiv <4 x float> %a, %b
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_frem)=
-
-#### '`llvm.vp.frem.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.frem.v16f32 (<16 x float> <left_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.frem.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.frem.v256f64 (<256 x double> <left_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point remainder of two vectors of floating-point values.
-
-
-##### Arguments:
-
-The first two arguments and the result have the same vector of floating-point type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.frem`' intrinsic performs floating-point remainder ({ref}`frem <i_frem>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.frem.v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = frem <4 x float> %a, %b
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_fneg)=
-
-#### '`llvm.vp.fneg.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.fneg.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.fneg.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.fneg.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point negation of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.fneg`' intrinsic performs floating-point negation ({ref}`fneg <i_fneg>`)
-of the first vector argument on each enabled lane. The result on disabled lanes
-is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fneg <4 x float> %a
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_fabs)=
-
-#### '`llvm.vp.fabs.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.fabs.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.fabs.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.fabs.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point absolute value of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.fabs`' intrinsic performs floating-point absolute value
-({ref}`fabs <int_fabs>`) of the first vector argument on each enabled lane. The
-result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.fabs.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_sqrt)=
-
-#### '`llvm.vp.sqrt.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.sqrt.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.sqrt.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.sqrt.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point square root of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.sqrt`' intrinsic performs floating-point square root ({ref}`sqrt <int_sqrt>`) of
-the first vector argument on each enabled lane. The result on disabled lanes is
-a {ref}`poison value <poisonvalues>`. The operation is performed in the default
-floating-point environment.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.sqrt.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_fma)=
-
-#### '`llvm.vp.fma.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.fma.v16f32 (<16 x float> <left_op>, <16 x float> <middle_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.fma.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <middle_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.fma.v256f64 (<256 x double> <left_op>, <256 x double> <middle_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point fused multiply-add of two vectors of floating-point values.
-
-
-##### Arguments:
-
-The first three arguments and the result have the same vector of floating-point type. The
-fourth argument is the vector mask and has the same number of elements as the
-result vector type. The fifth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.fma`' intrinsic performs floating-point fused multiply-add ({ref}`llvm.fma <int_fma>`)
-of the first, second, and third vector argument on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.fma(<4 x float> %a, <4 x float> %b, <4 x float> %c)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_fmuladd)=
-
-#### '`llvm.vp.fmuladd.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.fmuladd.v16f32 (<16 x float> <left_op>, <16 x float> <middle_op>, <16 x float> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.fmuladd.nxv4f32 (<vscale x 4 x float> <left_op>, <vscale x 4 x float> <middle_op>, <vscale x 4 x float> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.fmuladd.v256f64 (<256 x double> <left_op>, <256 x double> <middle_op>, <256 x double> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point multiply-add of two vectors of floating-point values
-that can be fused if code generator determines that (a) the target instruction
-set has support for a fused operation, and (b) that the fused operation is more
-efficient than the equivalent, separate pair of mul and add instructions.
-
-##### Arguments:
-
-The first three arguments and the result have the same vector of floating-point
-type. The fourth argument is the vector mask and has the same number of elements
-as the result vector type. The fifth argument is the explicit vector length of
-the operation.
-
-##### Semantics:
-
-The '`llvm.vp.fmuladd`' intrinsic performs floating-point multiply-add ({ref}`llvm.fuladd <int_fmuladd>`)
-of the first, second, and third vector argument on each enabled lane. The result
-on disabled lanes is a {ref}`poison value <poisonvalues>`. The operation is
-performed in the default floating-point environment.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.fmuladd(<4 x float> %a, <4 x float> %b, <4 x float> %c)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_reduce_add)=
-
-#### '`llvm.vp.reduce.add.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.add.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.add.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated integer `ADD` reduction of a vector and a scalar starting value,
-returning the result as a scalar.
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.add`' intrinsic performs the integer `ADD` reduction
-({ref}`llvm.vector.reduce.add <int_vector_reduce_add>`) of the vector argument
-`val` on each enabled lane, adding it to the scalar `start_value`. Disabled
-lanes are treated as containing the neutral value `0` (i.e., having no effect
-on the reduction operation). If the vector length is zero, the result is equal
-to `start_value`.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i32 @llvm.vp.reduce.add.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> zeroinitializer
-%reduction = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %masked.a)
-%also.r = add i32 %reduction, %start
-```
-
-(int_vp_reduce_fadd)=
-
-#### '`llvm.vp.reduce.fadd.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare float @llvm.vp.reduce.fadd.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare double @llvm.vp.reduce.fadd.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point `ADD` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-floating-point type equal to the result type. The second argument is the vector
-on which the reduction is performed and must be a vector of floating-point
-values whose element type is the result/start type. The third argument is the
-vector mask and is a vector of boolean values with the same number of elements
-as the vector argument. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.fadd`' intrinsic performs the floating-point `ADD`
-reduction ({ref}`llvm.vector.reduce.fadd <int_vector_reduce_fadd>`) of the
-vector argument `val` on each enabled lane, adding it to the scalar
-`start_value`. Disabled lanes are treated as containing the neutral value
-`-0.0` (i.e., having no effect on the reduction operation). If no lanes are
-enabled, the resulting value will be equal to `start_value`.
-
-To ignore the start value, the neutral value can be used.
-
-See the unpredicated version ({ref}`llvm.vector.reduce.fadd <int_vector_reduce_fadd>`) for more detail on the semantics of the reduction.
-
-##### Examples:
-
-```llvm
-%r = call float @llvm.vp.reduce.fadd.v4f32(float %start, <4 x float> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>
-%also.r = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %masked.a)
-```
-
-(int_vp_reduce_mul)=
-
-#### '`llvm.vp.reduce.mul.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.mul.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.mul.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated integer `MUL` reduction of a vector and a scalar starting value,
-returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.mul`' intrinsic performs the integer `MUL` reduction
-({ref}`llvm.vector.reduce.mul <int_vector_reduce_mul>`) of the vector argument `val`
-on each enabled lane, multiplying it by the scalar `start_value`. Disabled
-lanes are treated as containing the neutral value `1` (i.e., having no effect
-on the reduction operation). If the vector length is zero, the result is the
-start value.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i32 @llvm.vp.reduce.mul.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-%reduction = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %masked.a)
-%also.r = mul i32 %reduction, %start
-```
-
-(int_vp_reduce_fmul)=
-
-#### '`llvm.vp.reduce.fmul.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare float @llvm.vp.reduce.fmul.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare double @llvm.vp.reduce.fmul.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point `MUL` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-floating-point type equal to the result type. The second argument is the vector
-on which the reduction is performed and must be a vector of floating-point
-values whose element type is the result/start type. The third argument is the
-vector mask and is a vector of boolean values with the same number of elements
-as the vector argument. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.fmul`' intrinsic performs the floating-point `MUL`
-reduction ({ref}`llvm.vector.reduce.fmul <int_vector_reduce_fmul>`) of the
-vector argument `val` on each enabled lane, multiplying it by the scalar
-`start_value`. Disabled lanes are treated as containing the neutral value
-`1.0` (i.e., having no effect on the reduction operation). If no lanes are
-enabled, the resulting value will be equal to the starting value.
-
-To ignore the start value, the neutral value can be used.
-
-See the unpredicated version ({ref}`llvm.vector.reduce.fmul <int_vector_reduce_fmul>`) for more detail on the semantics.
-
-##### Examples:
-
-```llvm
-%r = call float @llvm.vp.reduce.fmul.v4f32(float %start, <4 x float> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>
-%also.r = call float @llvm.vector.reduce.fmul.v4f32(float %start, <4 x float> %masked.a)
-```
-
-(int_vp_reduce_and)=
-
-#### '`llvm.vp.reduce.and.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.and.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.and.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated integer `AND` reduction of a vector and a scalar starting value,
-returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.and`' intrinsic performs the integer `AND` reduction
-({ref}`llvm.vector.reduce.and <int_vector_reduce_and>`) of the vector argument
-`val` on each enabled lane, performing an '`and`' of that with with the
-scalar `start_value`. Disabled lanes are treated as containing the neutral
-value `UINT_MAX`, or `-1` (i.e., having no effect on the reduction
-operation). If the vector length is zero, the result is the start value.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i32 @llvm.vp.reduce.and.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
-%reduction = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %masked.a)
-%also.r = and i32 %reduction, %start
-```
-
-(int_vp_reduce_or)=
-
-#### '`llvm.vp.reduce.or.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.or.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.or.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated integer `OR` reduction of a vector and a scalar starting value,
-returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.or`' intrinsic performs the integer `OR` reduction
-({ref}`llvm.vector.reduce.or <int_vector_reduce_or>`) of the vector argument
-`val` on each enabled lane, performing an '`or`' of that with the scalar
-`start_value`. Disabled lanes are treated as containing the neutral value
-`0` (i.e., having no effect on the reduction operation). If the vector length
-is zero, the result is the start value.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i32 @llvm.vp.reduce.or.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
-%reduction = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %masked.a)
-%also.r = or i32 %reduction, %start
-```
-
-(int_vp_reduce_xor)=
-
-#### '`llvm.vp.reduce.xor.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.xor.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.xor.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated integer `XOR` reduction of a vector and a scalar starting value,
-returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.xor`' intrinsic performs the integer `XOR` reduction
-({ref}`llvm.vector.reduce.xor <int_vector_reduce_xor>`) of the vector argument
-`val` on each enabled lane, performing an '`xor`' of that with the scalar
-`start_value`. Disabled lanes are treated as containing the neutral value
-`0` (i.e., having no effect on the reduction operation). If the vector length
-is zero, the result is the start value.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i32 @llvm.vp.reduce.xor.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
-%reduction = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %masked.a)
-%also.r = xor i32 %reduction, %start
-```
-
-(int_vp_reduce_smax)=
-
-#### '`llvm.vp.reduce.smax.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.smax.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.smax.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated signed-integer `MAX` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.smax`' intrinsic performs the signed-integer `MAX`
-reduction ({ref}`llvm.vector.reduce.smax <int_vector_reduce_smax>`) of the
-vector argument `val` on each enabled lane, and taking the maximum of that and
-the scalar `start_value`. Disabled lanes are treated as containing the
-neutral value `INT_MIN` (i.e., having no effect on the reduction operation).
-If the vector length is zero, the result is the start value.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i8 @llvm.vp.reduce.smax.v4i8(i8 %start, <4 x i8> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i8> %a, <4 x i8> <i8 -128, i8 -128, i8 -128, i8 -128>
-%reduction = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %masked.a)
-%also.r = call i8 @llvm.smax.i8(i8 %reduction, i8 %start)
-```
-
-(int_vp_reduce_smin)=
-
-#### '`llvm.vp.reduce.smin.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.smin.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.smin.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated signed-integer `MIN` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.smin`' intrinsic performs the signed-integer `MIN`
-reduction ({ref}`llvm.vector.reduce.smin <int_vector_reduce_smin>`) of the
-vector argument `val` on each enabled lane, and taking the minimum of that and
-the scalar `start_value`. Disabled lanes are treated as containing the
-neutral value `INT_MAX` (i.e., having no effect on the reduction operation).
-If the vector length is zero, the result is the start value.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i8 @llvm.vp.reduce.smin.v4i8(i8 %start, <4 x i8> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i8> %a, <4 x i8> <i8 127, i8 127, i8 127, i8 127>
-%reduction = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %masked.a)
-%also.r = call i8 @llvm.smin.i8(i8 %reduction, i8 %start)
-```
-
-(int_vp_reduce_umax)=
-
-#### '`llvm.vp.reduce.umax.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.umax.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.umax.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated unsigned-integer `MAX` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.umax`' intrinsic performs the unsigned-integer `MAX`
-reduction ({ref}`llvm.vector.reduce.umax <int_vector_reduce_umax>`) of the
-vector argument `val` on each enabled lane, and taking the maximum of that and
-the scalar `start_value`. Disabled lanes are treated as containing the
-neutral value `0` (i.e., having no effect on the reduction operation). If the
-vector length is zero, the result is the start value.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i32 @llvm.vp.reduce.umax.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
-%reduction = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %masked.a)
-%also.r = call i32 @llvm.umax.i32(i32 %reduction, i32 %start)
-```
-
-(int_vp_reduce_umin)=
-
-#### '`llvm.vp.reduce.umin.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare i32 @llvm.vp.reduce.umin.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare i16 @llvm.vp.reduce.umin.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated unsigned-integer `MIN` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-integer type equal to the result type. The second argument is the vector on
-which the reduction is performed and must be a vector of integer values whose
-element type is the result/start type. The third argument is the vector mask and
-is a vector of boolean values with the same number of elements as the vector
-argument. The fourth argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.umin`' intrinsic performs the unsigned-integer `MIN`
-reduction ({ref}`llvm.vector.reduce.umin <int_vector_reduce_umin>`) of the
-vector argument `val` on each enabled lane, taking the minimum of that and the
-scalar `start_value`. Disabled lanes are treated as containing the neutral
-value `UINT_MAX`, or `-1` (i.e., having no effect on the reduction
-operation). If the vector length is zero, the result is the start value.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call i32 @llvm.vp.reduce.umin.v4i32(i32 %start, <4 x i32> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
-%reduction = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %masked.a)
-%also.r = call i32 @llvm.umin.i32(i32 %reduction, i32 %start)
-```
-
-(int_vp_reduce_fmax)=
-
-#### '`llvm.vp.reduce.fmax.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare float @llvm.vp.reduce.fmax.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare double @llvm.vp.reduce.fmax.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point `MAX` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-floating-point type equal to the result type. The second argument is the vector
-on which the reduction is performed and must be a vector of floating-point
-values whose element type is the result/start type. The third argument is the
-vector mask and is a vector of boolean values with the same number of elements
-as the vector argument. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.fmax`' intrinsic performs the floating-point `MAX`
-reduction ({ref}`llvm.vector.reduce.fmax <int_vector_reduce_fmax>`) of the
-vector argument `val` on each enabled lane, taking the maximum of that and the
-scalar `start_value`. Disabled lanes are treated as containing the neutral
-value (i.e., having no effect on the reduction operation). If the vector length
-is zero, the result is the start value.
-
-The neutral value is dependent on the {ref}`fast-math flags <fastmath>`. If no
-flags are set, the neutral value is `-QNAN`. If `nnan` and `ninf` are
-both set, then the neutral value is the smallest floating-point value for the
-result type. If only `nnan` is set then the neutral value is `-Infinity`.
-
-This instruction has the same comparison semantics as the
-{ref}`llvm.vector.reduce.fmax <int_vector_reduce_fmax>` intrinsic (and thus the
-'`llvm.maxnum.*`' intrinsic).
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call float @llvm.vp.reduce.fmax.v4f32(float %float, <4 x float> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float QNAN, float QNAN, float QNAN, float QNAN>
-%reduction = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %masked.a)
-%also.r = call float @llvm.maxnum.f32(float %reduction, float %start)
-```
-
-(int_vp_reduce_fmin)=
-
-#### '`llvm.vp.reduce.fmin.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare float @llvm.vp.reduce.fmin.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare double @llvm.vp.reduce.fmin.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point `MIN` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-floating-point type equal to the result type. The second argument is the vector
-on which the reduction is performed and must be a vector of floating-point
-values whose element type is the result/start type. The third argument is the
-vector mask and is a vector of boolean values with the same number of elements
-as the vector argument. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.fmin`' intrinsic performs the floating-point `MIN`
-reduction ({ref}`llvm.vector.reduce.fmin <int_vector_reduce_fmin>`) of the
-vector argument `val` on each enabled lane, taking the minimum of that and the
-scalar `start_value`. Disabled lanes are treated as containing the neutral
-value (i.e., having no effect on the reduction operation). If the vector length
-is zero, the result is the start value.
-
-The neutral value is dependent on the {ref}`fast-math flags <fastmath>`. If no
-flags are set, the neutral value is `+QNAN`. If `nnan` and `ninf` are
-both set, then the neutral value is the largest floating-point value for the
-result type. If only `nnan` is set then the neutral value is `+Infinity`.
-
-This instruction has the same comparison semantics as the
-{ref}`llvm.vector.reduce.fmin <int_vector_reduce_fmin>` intrinsic (and thus the
-'`llvm.minnum.*`' intrinsic).
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call float @llvm.vp.reduce.fmin.v4f32(float %start, <4 x float> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float QNAN, float QNAN, float QNAN, float QNAN>
-%reduction = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %masked.a)
-%also.r = call float @llvm.minnum.f32(float %reduction, float %start)
-```
-
-(int_vp_reduce_fmaximum)=
-
-#### '`llvm.vp.reduce.fmaximum.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare float @llvm.vp.reduce.fmaximum.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare double @llvm.vp.reduce.fmaximum.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point `MAX` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-floating-point type equal to the result type. The second argument is the vector
-on which the reduction is performed and must be a vector of floating-point
-values whose element type is the result/start type. The third argument is the
-vector mask and is a vector of boolean values with the same number of elements
-as the vector argument. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.fmaximum`' intrinsic performs the floating-point `MAX`
-reduction ({ref}`llvm.vector.reduce.fmaximum <int_vector_reduce_fmaximum>`) of
-the vector argument `val` on each enabled lane, taking the maximum of that and
-the scalar `start_value`. Disabled lanes are treated as containing the
-neutral value (i.e., having no effect on the reduction operation). If the vector
-length is zero, the result is the start value.
-
-The neutral value is dependent on the {ref}`fast-math flags <fastmath>`. If no
-flags are set or only the `nnan` is set, the neutral value is `-Infinity`.
-If `ninf` is set, then the neutral value is the smallest floating-point value
-for the result type.
-
-This instruction has the same comparison semantics as the
-{ref}`llvm.vector.reduce.fmaximum <int_vector_reduce_fmaximum>` intrinsic (and
-thus the '`llvm.maximum.*`' intrinsic). That is, the result will always be a
-number unless any of the elements in the vector or the starting value is
-`NaN`. Namely, this intrinsic propagates `NaN`. Also, -0.0 is considered
-less than +0.0.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call float @llvm.vp.reduce.fmaximum.v4f32(float %float, <4 x float> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float -infinity, float -infinity, float -infinity, float -infinity>
-%reduction = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %masked.a)
-%also.r = call float @llvm.maximum.f32(float %reduction, float %start)
-```
-
-(int_vp_reduce_fminimum)=
-
-#### '`llvm.vp.reduce.fminimum.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare float @llvm.vp.reduce.fminimum.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, i32 <vector_length>)
-declare double @llvm.vp.reduce.fminimum.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vscale x 8 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point `MIN` reduction of a vector and a scalar starting
-value, returning the result as a scalar.
-
-
-##### Arguments:
-
-The first argument is the start value of the reduction, which must be a scalar
-floating-point type equal to the result type. The second argument is the vector
-on which the reduction is performed and must be a vector of floating-point
-values whose element type is the result/start type. The third argument is the
-vector mask and is a vector of boolean values with the same number of elements
-as the vector argument. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.reduce.fminimum`' intrinsic performs the floating-point `MIN`
-reduction ({ref}`llvm.vector.reduce.fminimum <int_vector_reduce_fminimum>`) of
-the vector argument `val` on each enabled lane, taking the minimum of that and
-the scalar `start_value`. Disabled lanes are treated as containing the neutral
-value (i.e., having no effect on the reduction operation). If the vector length
-is zero, the result is the start value.
-
-The neutral value is dependent on the {ref}`fast-math flags <fastmath>`. If no
-flags are set or only the `nnan` is set, the neutral value is `+Infinity`.
-If `ninf` is set, then the neutral value is the largest floating-point value
-for the result type.
-
-This instruction has the same comparison semantics as the
-{ref}`llvm.vector.reduce.fminimum <int_vector_reduce_fminimum>` intrinsic (and
-thus the '`llvm.minimum.*`' intrinsic). That is, the result will always be a
-number unless any of the elements in the vector or the starting value is
-`NaN`. Namely, this intrinsic propagates `NaN`. Also, -0.0 is considered
-less than +0.0.
-
-To ignore the start value, the neutral value can be used.
-
-##### Examples:
-
-```llvm
-%r = call float @llvm.vp.reduce.fminimum.v4f32(float %start, <4 x float> %a, <4 x i1> %mask, i32 %evl)
-; %r is equivalent to %also.r, where lanes greater than or equal to %evl
-; are treated as though %mask were false for those lanes.
-
-%masked.a = select <4 x i1> %mask, <4 x float> %a, <4 x float> <float infinity, float infinity, float infinity, float infinity>
-%reduction = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %masked.a)
-%also.r = call float @llvm.minimum.f32(float %reduction, float %start)
-```
-
-(int_experimental_vp_splice)=
-
-#### '`llvm.experimental.vp.splice`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %vec1, <2 x double> %vec2, i32 %imm, <2 x i1> %mask, i32 %evl1, i32 %evl2)
-declare <vscale x 4 x i32> @llvm.experimental.vp.splice.nxv4i32(<vscale x 4 x i32> %vec1, <vscale x 4 x i32> %vec2, i32 %imm, <vscale x 4 x i1> %mask, i32 %evl1, i32 %evl2)
-```
-
-##### Overview:
-
-The '`llvm.experimental.vp.splice.*`' intrinsic is the vector length
-predicated version of the '`llvm.vector.splice.*`' intrinsic.
-
-##### Arguments:
-
-The result and the first two arguments `vec1` and `vec2` are vectors with
-the same type. The third argument `imm` is an immediate signed integer that
-indicates the offset index. The fourth argument `mask` is a vector mask and
-has the same number of elements as the result. The last two arguments `evl1`
-and `evl2` are unsigned integers indicating the explicit vector lengths of
-`vec1` and `vec2` respectively. `imm`, `evl1` and `evl2` should
-respect the following constraints: `-evl1 <= imm < evl1`, `0 <= evl1 <= VL`
-and `0 <= evl2 <= VL`, where `VL` is the runtime vector factor. If these
-constraints are not satisfied the intrinsic has undefined behavior.
-
-##### Semantics:
-
-Effectively, this intrinsic concatenates `vec1[0..evl1-1]` and
-`vec2[0..evl2-1]` and creates the result vector by selecting the elements in a
-window of size `evl2`, starting at index `imm` (for a positive immediate) of
-the concatenated vector. Elements in the result vector beyond `evl2` are
-`undef`. If `imm` is negative the starting index is `evl1 + imm`. The result
-vector of active vector length `evl2` contains `evl1 - imm` (`-imm` for
-negative `imm`) elements from indices `[imm..evl1 - 1]`
-(`[evl1 + imm..evl1 -1]` for negative `imm`) of `vec1` followed by the
-first `evl2 - (evl1 - imm)` (`evl2 + imm` for negative `imm`) elements of
-`vec2`. If `evl1 - imm` (`-imm`) >= `evl2`, only the first `evl2`
-elements are considered and the remaining are `undef`. The lanes in the result
-vector disabled by `mask` are `poison`.
-
-##### Examples:
-
-```text
-llvm.experimental.vp.splice(<A,B,C,D>, <E,F,G,H>, 1, 2, 3); ==> <B, E, F, poison> index
-llvm.experimental.vp.splice(<A,B,C,D>, <E,F,G,H>, -2, 3, 2); ==> <B, C, poison, poison> trailing elements
-```
-
-(int_experimental_vp_reverse)=
-
-
-#### '`llvm.experimental.vp.reverse`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <2 x double> @llvm.experimental.vp.reverse.v2f64(<2 x double> %vec, <2 x i1> %mask, i32 %evl)
-declare <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> %vec, <vscale x 4 x i1> %mask, i32 %evl)
-```
-
-##### Overview:
-
-The '`llvm.experimental.vp.reverse.*`' intrinsic is the vector length
-predicated version of the '`llvm.vector.reverse.*`' intrinsic.
-
-##### Arguments:
-
-The result and the first argument `vec` are vectors with the same type.
-The second argument `mask` is a vector mask and has the same number of
-elements as the result. The third argument is the explicit vector length of
-the operation.
-
-##### Semantics:
-
-This intrinsic reverses the order of the first `evl` elements in a vector.
-The lanes in the result vector disabled by `mask` are `poison`. The
-elements past `evl` are poison.
-
-(int_vp_load)=
-
-#### '`llvm.vp.load`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <4 x float> @llvm.vp.load.v4f32.p0(ptr %ptr, <4 x i1> %mask, i32 %evl)
-declare <vscale x 2 x i16> @llvm.vp.load.nxv2i16.p0(ptr %ptr, <vscale x 2 x i1> %mask, i32 %evl)
-declare <8 x float> @llvm.vp.load.v8f32.p1(ptr addrspace(1) %ptr, <8 x i1> %mask, i32 %evl)
-declare <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p6(ptr addrspace(6) %ptr, <vscale x 1 x i1> %mask, i32 %evl)
-```
-
-##### Overview:
-
-The '`llvm.vp.load.*`' intrinsic is the vector length predicated version of
-the {ref}`llvm.masked.load <int_mload>` intrinsic.
-
-##### Arguments:
-
-The first argument is the base pointer for the load. The second argument is a
-vector of boolean values with the same number of elements as the return type.
-The third is the explicit vector length of the operation. The return type and
-underlying type of the base pointer are the same vector types.
-
-The {ref}`align <attr_align>` parameter attribute can be provided for the first
-argument.
-
-##### Semantics:
-
-The '`llvm.vp.load`' intrinsic reads a vector from memory in the same way as
-the '`llvm.masked.load`' intrinsic, where the mask is taken from the
-combination of the '`mask`' and '`evl`' arguments in the usual VP way.
-Certain '`llvm.masked.load`' arguments do not have corresponding arguments in
-'`llvm.vp.load`': the '`passthru`' argument is implicitly `poison`; the
-'`alignment`' argument is taken as the `align` parameter attribute, if
-provided. The default alignment is taken as the ABI alignment of the return
-type as specified by the {ref}`datalayout string<langref_datalayout>`.
-
-##### Examples:
-
-```text
-%r = call <8 x i8> @llvm.vp.load.v8i8.p0(ptr align 2 %ptr, <8 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%also.r = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr align 2 %ptr, <8 x i1> %mask, <8 x i8> poison)
-```
-
-(int_vp_load_ff)=
-
-#### '`llvm.vp.load.ff`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare {<4 x float>, i32} @llvm.vp.load.ff.v4f32.p0(ptr %ptr, <4 x i1> %mask, i32 %evl)
-declare {<vscale x 2 x i16>, i32} @llvm.vp.load.ff.nxv2i16.p0(ptr %ptr, <vscale x 2 x i1> %mask, i32 %evl)
-declare {<8 x float>, i32} @llvm.vp.load.ff.v8f32.p1(ptr addrspace(1) %ptr, <8 x i1> %mask, i32 %evl)
-declare {<vscale x 1 x i64>, i32} @llvm.vp.load.ff.nxv1i64.p6(ptr addrspace(6) %ptr, <vscale x 1 x i1> %mask, i32 %evl)
-```
-
-##### Overview:
-
-The '`llvm.vp.load.ff.*`' intrinsic is similar to
-'`llvm.vp.load.*`', but will not trap if there are not `evl` readable
-lanes at the pointer. '`ff`' stands for first-fault or fault-only-first.
-
-##### Arguments:
-
-The first argument is the base pointer for the load. The second argument is a
-vector of boolean values with the same number of elements as the first return
-type. The third is the explicit vector length of the operation. The first
-return type and underlying type of the base pointer are the same vector types.
-
-The {ref}`align <attr_align>` parameter attribute can be provided for the first
-argument.
-
-##### Semantics:
-
-The '`llvm.vp.load.ff`' is designed for reading vector lanes in a single
-IR operation where the number of lanes that can be read is not known and can
-only be determined by looking at the data. This is useful for vectorizing
-strcmp or strlen like loops where the data contains a null terminator. Some
-targets have a fault-only-first load instruction that this intrinsic can be
-lowered to. Other targets may support this intrinsic differently, for example by
-lowering to a single scalar load guarded by `evl!=0` and `mask[0]==1` and
-indicating only 1 lane could be read.
-
-Like '`llvm.vp.load`', this intrinsic reads memory based on a `mask` and an
-`evl`. If `evl` is non-zero and the first lane is masked-on, then the
-first lane of the vector needs to be inbounds of an allocation. The remaining
-masked-on lanes with index less than `evl` do not need to be inbounds of
-an the same allocation or any allocation.
-
-The second return value from the intrinsic indicates the index of the first
-lane that could not be read for some reason or `evl` if all lanes could be
-be read. Lanes at this index or higher in the first return value are
-{ref}`poison value <poisonvalues>`. If `evl` is non-zero, the result in the
-second return value must be at least 1, even if the first lane is masked-off.
-
-The second result is usually less than `evl` when an exception would occur
-for reading that lane, but it can be reduced for any reason. This facilitates
-emulating this intrinsic when the hardware only supports narrower vector
-types natively or when when hardware does not support fault-only-first loads.
-
-Masked-on lanes that are not inbounds of the allocation that contains the first
-lane are {ref}`poison value <poisonvalues>`. There should be a marker in the
-allocation that indicates where valid data stops such as a null terminator. The
-terminator should be checked for after calling this intrinsic to prevent using
-any lanes past the terminator. Even if second return value is less than
-`evl`, the terminator value may not have been read.
-
-This intrinsic will typically be called in a loop until a terminator is
-found. The second result should be used to indicates how many elements are
-valid to look for the null terminator. If the terminator is not found, the
-pointer should be advanced by the number of elements in the second result and
-the intrinsic called again.
-
-The default alignment is taken as the ABI alignment of the first return
-type as specified by the {ref}`datalayout string<langref_datalayout>`.
-
-##### Examples:
-
-```text
-%r = call {<8 x i8>, i32} @llvm.vp.load.ff.v8i8.p0(ptr align 2 %ptr, <8 x i1> %mask, i32 %evl)
-```
-
-(int_vp_store)=
-
-#### '`llvm.vp.store`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare void @llvm.vp.store.v4f32.p0(<4 x float> %val, ptr %ptr, <4 x i1> %mask, i32 %evl)
-declare void @llvm.vp.store.nxv2i16.p0(<vscale x 2 x i16> %val, ptr %ptr, <vscale x 2 x i1> %mask, i32 %evl)
-declare void @llvm.vp.store.v8f32.p1(<8 x float> %val, ptr addrspace(1) %ptr, <8 x i1> %mask, i32 %evl)
-declare void @llvm.vp.store.nxv1i64.p6(<vscale x 1 x i64> %val, ptr addrspace(6) %ptr, <vscale x 1 x i1> %mask, i32 %evl)
-```
-
-##### Overview:
-
-The '`llvm.vp.store.*`' intrinsic is the vector length predicated version of
-the {ref}`llvm.masked.store <int_mstore>` intrinsic.
-
-##### Arguments:
-
-The first argument is the vector value to be written to memory. The second
-argument is the base pointer for the store. It has the same underlying type as
-the value argument. The third argument is a vector of boolean values with the
-same number of elements as the return type. The fourth is the explicit vector
-length of the operation.
-
-The {ref}`align <attr_align>` parameter attribute can be provided for the
-second argument.
-
-##### Semantics:
-
-The '`llvm.vp.store`' intrinsic reads a vector from memory in the same way as
-the '`llvm.masked.store`' intrinsic, where the mask is taken from the
-combination of the '`mask`' and '`evl`' arguments in the usual VP way. The
-alignment of the operation (corresponding to the '`alignment`' argument of
-'`llvm.masked.store`') is specified by the `align` parameter attribute (see
-above). If it is not provided then the ABI alignment of the type of the
-'`value`' argument as specified by the {ref}`datalayout string<langref_datalayout>` is used instead.
-
-##### Examples:
-
-```text
-call void @llvm.vp.store.v8i8.p0(<8 x i8> %val, ptr align 4 %ptr, <8 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, the call above is lane-wise equivalent to the call below.
-
-call void @llvm.masked.store.v8i8.p0(<8 x i8> %val, ptr %ptr, i32 4, <8 x i1> %mask)
-```
-
-(int_experimental_vp_strided_load)=
-
-#### '`llvm.experimental.vp.strided.load`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <4 x float> @llvm.experimental.vp.strided.load.v4f32.i64(ptr %ptr, i64 %stride, <4 x i1> %mask, i32 %evl)
-declare <vscale x 2 x i16> @llvm.experimental.vp.strided.load.nxv2i16.i64(ptr %ptr, i64 %stride, <vscale x 2 x i1> %mask, i32 %evl)
-```
-
-##### Overview:
-
-The '`llvm.experimental.vp.strided.load`' intrinsic loads, into a vector, scalar values from
-memory locations evenly spaced apart by '`stride`' number of bytes, starting from '`ptr`'.
-
-##### Arguments:
-
-The first argument is the base pointer for the load. The second argument is the stride
-value expressed in bytes. The third argument is a vector of boolean values
-with the same number of elements as the return type. The fourth is the explicit
-vector length of the operation. The base pointer underlying type matches the type of the scalar
-elements of the return argument.
-
-The {ref}`align <attr_align>` parameter attribute can be provided for the first
-argument.
-
-##### Semantics:
-
-The '`llvm.experimental.vp.strided.load`' intrinsic loads, into a vector, multiple scalar
-values from memory in the same way as the {ref}`llvm.vp.gather <int_vp_gather>` intrinsic,
-where the vector of pointers is in the form:
-
-`%ptrs = <%ptr, %ptr + %stride, %ptr + 2 * %stride, ... >`,
-
-with '`ptr`' previously casted to a pointer '`i8`', '`stride`' always interpreted as a signed
-integer and all arithmetic occurring in the pointer type.
-
-##### Examples:
-
-```text
-%r = call <8 x i64> @llvm.experimental.vp.strided.load.v8i64.i64(i64* %ptr, i64 %stride, <8 x i64> %mask, i32 %evl)
-;; The operation can also be expressed like this:
-
-%addr = bitcast i64* %ptr to i8*
-;; Create a vector of pointers %addrs in the form:
-;; %addrs = <%addr, %addr + %stride, %addr + 2 * %stride, ...>
-%ptrs = bitcast <8 x i8* > %addrs to <8 x i64* >
-%also.r = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64* > %ptrs, <8 x i64> %mask, i32 %evl)
-```
-
-
-(int_experimental_vp_strided_store)=
-
-#### '`llvm.experimental.vp.strided.store`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare void @llvm.experimental.vp.strided.store.v4f32.i64(<4 x float> %val, ptr %ptr, i64 %stride, <4 x i1> %mask, i32 %evl)
-declare void @llvm.experimental.vp.strided.store.nxv2i16.i64(<vscale x 2 x i16> %val, ptr %ptr, i64 %stride, <vscale x 2 x i1> %mask, i32 %evl)
-```
-
-##### Overview:
-
-The '`@llvm.experimental.vp.strided.store`' intrinsic stores the elements of
-'`val`' into memory locations evenly spaced apart by '`stride`' number of
-bytes, starting from '`ptr`'.
-
-##### Arguments:
-
-The first argument is the vector value to be written to memory. The second
-argument is the base pointer for the store. Its underlying type matches the
-scalar element type of the value argument. The third argument is the stride value
-expressed in bytes. The fourth argument is a vector of boolean values with the
-same number of elements as the return type. The fifth is the explicit vector
-length of the operation.
-
-The {ref}`align <attr_align>` parameter attribute can be provided for the
-second argument.
-
-##### Semantics:
-
-The '`llvm.experimental.vp.strided.store`' intrinsic stores the elements of
-'`val`' in the same way as the {ref}`llvm.vp.scatter <int_vp_scatter>` intrinsic,
-where the vector of pointers is in the form:
-
-`%ptrs = <%ptr, %ptr + %stride, %ptr + 2 * %stride, ... >`,
-
-with '`ptr`' previously casted to a pointer '`i8`', '`stride`' always interpreted as a signed
-integer and all arithmetic occurring in the pointer type.
-
-##### Examples:
-
-```text
-call void @llvm.experimental.vp.strided.store.v8i64.i64(<8 x i64> %val, i64* %ptr, i64 %stride, <8 x i1> %mask, i32 %evl)
-;; The operation can also be expressed like this:
-
-%addr = bitcast i64* %ptr to i8*
-;; Create a vector of pointers %addrs in the form:
-;; %addrs = <%addr, %addr + %stride, %addr + 2 * %stride, ...>
-%ptrs = bitcast <8 x i8* > %addrs to <8 x i64* >
-call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %mask, i32 %evl)
-```
-
-
-(int_vp_gather)=
-
-#### '`llvm.vp.gather`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <4 x double> @llvm.vp.gather.v4f64.v4p0(<4 x ptr> %ptrs, <4 x i1> %mask, i32 %evl)
-declare <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %mask, i32 %evl)
-declare <2 x float> @llvm.vp.gather.v2f32.v2p2(<2 x ptr addrspace(2)> %ptrs, <2 x i1> %mask, i32 %evl)
-declare <vscale x 4 x i32> @llvm.vp.gather.nxv4i32.nxv4p4(<vscale x 4 x ptr addrspace(4)> %ptrs, <vscale x 4 x i1> %mask, i32 %evl)
-```
-
-##### Overview:
-
-The '`llvm.vp.gather.*`' intrinsic is the vector length predicated version of
-the {ref}`llvm.masked.gather <int_mgather>` intrinsic.
-
-##### Arguments:
-
-The first argument is a vector of pointers which holds all memory addresses to
-read. The second argument is a vector of boolean values with the same number of
-elements as the return type. The third is the explicit vector length of the
-operation. The return type and underlying type of the vector of pointers are
-the same vector types.
-
-The {ref}`align <attr_align>` parameter attribute can be provided for the first
-argument.
-
-##### Semantics:
-
-The '`llvm.vp.gather`' intrinsic reads multiple scalar values from memory in
-the same way as the '`llvm.masked.gather`' intrinsic, where the mask is taken
-from the combination of the '`mask`' and '`evl`' arguments in the usual VP
-way. Certain '`llvm.masked.gather`' arguments do not have corresponding
-arguments in '`llvm.vp.gather`': the '`passthru`' argument is implicitly
-`poison`; the '`alignment`' argument is taken as the `align` parameter, if
-provided. The default alignment is taken as the ABI alignment of the source
-addresses as specified by the {ref}`datalayout string<langref_datalayout>`.
-
-##### Examples:
-
-```text
-%r = call <8 x i8> @llvm.vp.gather.v8i8.v8p0(<8 x ptr> align 8 %ptrs, <8 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%also.r = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> align 8 %ptrs, <8 x i1> %mask, <8 x i8> poison)
-```
-
-(int_vp_scatter)=
-
-#### '`llvm.vp.scatter`' Intrinsic
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare void @llvm.vp.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, <4 x i1> %mask, i32 %evl)
-declare void @llvm.vp.scatter.nxv2i8.nxv2p0(<vscale x 2 x i8> %val, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %mask, i32 %evl)
-declare void @llvm.vp.scatter.v2f32.v2p2(<2 x float> %val, <2 x ptr addrspace(2)> %ptrs, <2 x i1> %mask, i32 %evl)
-declare void @llvm.vp.scatter.nxv4i32.nxv4p4(<vscale x 4 x i32> %val, <vscale x 4 x ptr addrspace(4)> %ptrs, <vscale x 4 x i1> %mask, i32 %evl)
-```
-
-##### Overview:
-
-The '`llvm.vp.scatter.*`' intrinsic is the vector length predicated version of
-the {ref}`llvm.masked.scatter <int_mscatter>` intrinsic.
-
-##### Arguments:
-
-The first argument is a vector value to be written to memory. The second argument
-is a vector of pointers, pointing to where the value elements should be stored.
-The third argument is a vector of boolean values with the same number of
-elements as the return type. The fourth is the explicit vector length of the
-operation.
-
-The {ref}`align <attr_align>` parameter attribute can be provided for the
-second argument.
-
-##### Semantics:
-
-The '`llvm.vp.scatter`' intrinsic writes multiple scalar values to memory in
-the same way as the '`llvm.masked.scatter`' intrinsic, where the mask is
-taken from the combination of the '`mask`' and '`evl`' arguments in the
-usual VP way. The '`alignment`' argument of the '`llvm.masked.scatter`' does
-not have a corresponding argument in '`llvm.vp.scatter`': it is instead
-provided via the optional `align` parameter attribute on the
-vector-of-pointers argument. Otherwise it is taken as the ABI alignment of the
-destination addresses as specified by the {ref}`datalayout string<langref_datalayout>`.
-
-##### Examples:
-
-```text
-call void @llvm.vp.scatter.v8i8.v8p0(<8 x i8> %val, <8 x ptr> align 1 %ptrs, <8 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, the call above is lane-wise equivalent to the call below.
-
-call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> %val, <8 x ptr> align 1 %ptrs, <8 x i1> %mask)
-```
-
-(int_vp_trunc)=
-
-#### '`llvm.vp.trunc.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i16> @llvm.vp.trunc.v16i16.v16i32 (<16 x i32> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i16> @llvm.vp.trunc.nxv4i16.nxv4i32 (<vscale x 4 x i32> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.trunc`' intrinsic truncates its first argument to the return
-type. The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.trunc`' intrinsic takes a value to cast as its first argument.
-The return type is the type to cast the value to. Both types must be vector of
-{ref}`integer <t_integer>` type. The bit size of the value must be larger than
-the bit size of the return type. The second argument is the vector mask. The
-return type, the value to cast, and the vector mask have the same number of
-elements. The third argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.trunc`' intrinsic truncates the high order bits in value and
-converts the remaining bits to return type. Since the source size must be larger
-than the destination size, '`llvm.vp.trunc`' cannot be a *no-op cast*. It will
-always truncate bits. The conversion is performed on lane positions below the
-explicit vector length and where the vector mask is true. Masked-off lanes are
-`poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i16> @llvm.vp.trunc.v4i16.v4i32(<4 x i32> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = trunc <4 x i32> %a to <4 x i16>
-%also.r = select <4 x i1> %mask, <4 x i16> %t, <4 x i16> poison
-```
-
-(int_vp_zext)=
-
-#### '`llvm.vp.zext.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.zext.v16i32.v16i16 (<16 x i16> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.zext.nxv4i32.nxv4i16 (<vscale x 4 x i16> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.zext`' intrinsic zero extends its first argument to the return
-type. The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.zext`' intrinsic takes a value to cast as its first argument.
-The return type is the type to cast the value to. Both types must be vectors of
-{ref}`integer <t_integer>` type. The bit size of the value must be smaller than
-the bit size of the return type. The second argument is the vector mask. The
-return type, the value to cast, and the vector mask have the same number of
-elements. The third argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.zext`' intrinsic fill the high order bits of the value with zero
-bits until it reaches the size of the return type. When zero extending from i1,
-the result will always be either 0 or 1. The conversion is performed on lane
-positions below the explicit vector length and where the vector mask is true.
-Masked-off lanes are `poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.zext.v4i32.v4i16(<4 x i16> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = zext <4 x i16> %a to <4 x i32>
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_sext)=
-
-#### '`llvm.vp.sext.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.sext.v16i32.v16i16 (<16 x i16> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.sext.nxv4i32.nxv4i16 (<vscale x 4 x i16> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.sext`' intrinsic sign extends its first argument to the return
-type. The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.sext`' intrinsic takes a value to cast as its first argument.
-The return type is the type to cast the value to. Both types must be vectors of
-{ref}`integer <t_integer>` type. The bit size of the value must be smaller than
-the bit size of the return type. The second argument is the vector mask. The
-return type, the value to cast, and the vector mask have the same number of
-elements. The third argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.sext`' intrinsic performs a sign extension by copying the sign
-bit (highest order bit) of the value until it reaches the size of the return
-type. When sign extending from i1, the result will always be either -1 or 0.
-The conversion is performed on lane positions below the explicit vector length
-and where the vector mask is true. Masked-off lanes are `poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.sext.v4i32.v4i16(<4 x i16> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = sext <4 x i16> %a to <4 x i32>
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_fptrunc)=
-
-#### '`llvm.vp.fptrunc.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.fptrunc.v16f32.v16f64 (<16 x double> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.trunc.nxv4f32.nxv4f64 (<vscale x 4 x double> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.fptrunc`' intrinsic truncates its first argument to the return
-type. The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.fptrunc`' intrinsic takes a value to cast as its first argument.
-The return type is the type to cast the value to. Both types must be vector of
-{ref}`floating-point <t_floating>` type. The bit size of the value must be
-larger than the bit size of the return type. This implies that
-'`llvm.vp.fptrunc`' cannot be used to make a *no-op cast*. The second argument
-is the vector mask. The return type, the value to cast, and the vector mask have
-the same number of elements. The third argument is the explicit vector length of
-the operation.
-
-##### Semantics:
-
-The '`llvm.vp.fptrunc`' intrinsic casts a `value` from a larger
-{ref}`floating-point <t_floating>` type to a smaller {ref}`floating-point <t_floating>` type.
-This instruction is assumed to execute in the default {ref}`floating-point environment <floatenv>`. The conversion is performed on lane positions below the
-explicit vector length and where the vector mask is true. Masked-off lanes are
-`poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.fptrunc.v4f32.v4f64(<4 x double> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fptrunc <4 x double> %a to <4 x float>
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_fpext)=
-
-#### '`llvm.vp.fpext.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x double> @llvm.vp.fpext.v16f64.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x double> @llvm.vp.fpext.nxv4f64.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.fpext`' intrinsic extends its first argument to the return
-type. The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.fpext`' intrinsic takes a value to cast as its first argument.
-The return type is the type to cast the value to. Both types must be vector of
-{ref}`floating-point <t_floating>` type. The bit size of the value must be
-smaller than the bit size of the return type. This implies that
-'`llvm.vp.fpext`' cannot be used to make a *no-op cast*. The second argument
-is the vector mask. The return type, the value to cast, and the vector mask have
-the same number of elements. The third argument is the explicit vector length of
-the operation.
-
-##### Semantics:
-
-The '`llvm.vp.fpext`' intrinsic extends the `value` from a smaller
-{ref}`floating-point <t_floating>` type to a larger {ref}`floating-point <t_floating>` type. The '`llvm.vp.fpext`' cannot be used to make a
-*no-op cast* because it always changes bits. Use `bitcast` to make a
-*no-op cast* for a floating-point cast.
-The conversion is performed on lane positions below the explicit vector length
-and where the vector mask is true. Masked-off lanes are `poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x double> @llvm.vp.fpext.v4f64.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fpext <4 x float> %a to <4 x double>
-%also.r = select <4 x i1> %mask, <4 x double> %t, <4 x double> poison
-```
-
-(int_vp_fptoui)=
-
-#### '`llvm.vp.fptoui.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.fptoui.v16i32.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.fptoui.nxv4i32.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.fptoui.v256i64.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.fptoui`' intrinsic converts the {ref}`floating-point <t_floating>` argument to the unsigned integer return type.
-The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.fptoui`' intrinsic takes a value to cast as its first argument.
-The value to cast must be a vector of {ref}`floating-point <t_floating>` type.
-The return type is the type to cast the value to. The return type must be
-vector of {ref}`integer <t_integer>` type. The second argument is the vector
-mask. The return type, the value to cast, and the vector mask have the same
-number of elements. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.fptoui`' intrinsic converts its {ref}`floating-point <t_floating>` argument into the nearest (rounding towards zero) unsigned integer
-value where the lane position is below the explicit vector length and the
-vector mask is true. Masked-off lanes are `poison`. On enabled lanes where
-conversion takes place and the value cannot fit in the return type, the result
-on that lane is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fptoui <4 x float> %a to <4 x i32>
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_fptosi)=
-
-#### '`llvm.vp.fptosi.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.fptosi.v16i32.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.fptosi.nxv4i32.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.fptosi.v256i64.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.fptosi`' intrinsic converts the {ref}`floating-point <t_floating>` argument to the signed integer return type.
-The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.fptosi`' intrinsic takes a value to cast as its first argument.
-The value to cast must be a vector of {ref}`floating-point <t_floating>` type.
-The return type is the type to cast the value to. The return type must be
-vector of {ref}`integer <t_integer>` type. The second argument is the vector
-mask. The return type, the value to cast, and the vector mask have the same
-number of elements. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.fptosi`' intrinsic converts its {ref}`floating-point <t_floating>` argument into the nearest (rounding towards zero) signed integer
-value where the lane position is below the explicit vector length and the
-vector mask is true. Masked-off lanes are `poison`. On enabled lanes where
-conversion takes place and the value cannot fit in the return type, the result
-on that lane is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fptosi <4 x float> %a to <4 x i32>
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_uitofp)=
-
-#### '`llvm.vp.uitofp.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.uitofp.v16f32.v16i32 (<16 x i32> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.uitofp.nxv4f32.nxv4i32 (<vscale x 4 x i32> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.uitofp.v256f64.v256i64 (<256 x i64> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.uitofp`' intrinsic converts its unsigned integer argument to the
-{ref}`floating-point <t_floating>` return type. The operation has a mask and
-an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.uitofp`' intrinsic takes a value to cast as its first argument.
-The value to cast must be vector of {ref}`integer <t_integer>` type. The
-return type is the type to cast the value to. The return type must be a vector
-of {ref}`floating-point <t_floating>` type. The second argument is the vector
-mask. The return type, the value to cast, and the vector mask have the same
-number of elements. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.uitofp`' intrinsic interprets its first argument as an unsigned
-integer quantity and converts it to the corresponding floating-point value. If
-the value cannot be exactly represented, it is rounded using the default
-rounding mode. The conversion is performed on lane positions below the
-explicit vector length and where the vector mask is true. Masked-off lanes are
-`poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.uitofp.v4f32.v4i32(<4 x i32> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = uitofp <4 x i32> %a to <4 x float>
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_sitofp)=
-
-#### '`llvm.vp.sitofp.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.sitofp.v16f32.v16i32 (<16 x i32> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.sitofp.nxv4f32.nxv4i32 (<vscale x 4 x i32> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.sitofp.v256f64.v256i64 (<256 x i64> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.sitofp`' intrinsic converts its signed integer argument to the
-{ref}`floating-point <t_floating>` return type. The operation has a mask and
-an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.sitofp`' intrinsic takes a value to cast as its first argument.
-The value to cast must be vector of {ref}`integer <t_integer>` type. The
-return type is the type to cast the value to. The return type must be a vector
-of {ref}`floating-point <t_floating>` type. The second argument is the vector
-mask. The return type, the value to cast, and the vector mask have the same
-number of elements. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.sitofp`' intrinsic interprets its first argument as a signed
-integer quantity and converts it to the corresponding floating-point value. If
-the value cannot be exactly represented, it is rounded using the default
-rounding mode. The conversion is performed on lane positions below the
-explicit vector length and where the vector mask is true. Masked-off lanes are
-`poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = sitofp <4 x i32> %a to <4 x float>
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_ptrtoint)=
-
-#### '`llvm.vp.ptrtoint.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i8> @llvm.vp.ptrtoint.v16i8.v16p0(<16 x ptr> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i8> @llvm.vp.ptrtoint.nxv4i8.nxv4p0(<vscale x 4 x ptr> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.ptrtoint.v16i64.v16p0(<256 x ptr> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.ptrtoint`' intrinsic converts its pointer to the integer return
-type. The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.ptrtoint`' intrinsic takes a value to cast as its first argument
-, which must be a vector of pointers, and a type to cast it to return type,
-which must be a vector of {ref}`integer <t_integer>` type.
-The second argument is the vector mask. The return type, the value to cast, and
-the vector mask have the same number of elements.
-The third argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.ptrtoint`' intrinsic converts value to return type by
-interpreting the pointer value as an integer and either truncating or zero
-extending that value to the size of the integer type.
-If `value` is smaller than return type, then a zero extension is done. If
-`value` is larger than return type, then a truncation is done. If they are
-the same size, then nothing is done (*no-op cast*) other than a type
-change.
-The conversion is performed on lane positions below the explicit vector length
-and where the vector mask is true. Masked-off lanes are `poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i8> @llvm.vp.ptrtoint.v4i8.v4p0i32(<4 x ptr> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = ptrtoint <4 x ptr> %a to <4 x i8>
-%also.r = select <4 x i1> %mask, <4 x i8> %t, <4 x i8> poison
-```
-
-(int_vp_inttoptr)=
-
-#### '`llvm.vp.inttoptr.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x ptr> @llvm.vp.inttoptr.v16p0.v16i32 (<16 x i32> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x ptr> @llvm.vp.inttoptr.nxv4p0.nxv4i32 (<vscale x 4 x i32> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x ptr> @llvm.vp.inttoptr.v256p0.v256i32 (<256 x i32> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.inttoptr`' intrinsic converts its integer value to the point
-return type. The operation has a mask and an explicit vector length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.inttoptr`' intrinsic takes a value to cast as its first argument
-, which must be a vector of {ref}`integer <t_integer>` type, and a type to cast
-it to return type, which must be a vector of pointers type.
-The second argument is the vector mask. The return type, the value to cast, and
-the vector mask have the same number of elements.
-The third argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.inttoptr`' intrinsic converts `value` to return type by
-applying either a zero extension or a truncation depending on the size of the
-integer `value`. If `value` is larger than the size of a pointer, then a
-truncation is done. If `value` is smaller than the size of a pointer, then a
-zero extension is done. If they are the same size, nothing is done (*no-op cast*).
-The conversion is performed on lane positions below the explicit vector length
-and where the vector mask is true. Masked-off lanes are `poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x ptr> @llvm.vp.inttoptr.v4p0i32.v4i32(<4 x i32> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = inttoptr <4 x i32> %a to <4 x ptr>
-%also.r = select <4 x i1> %mask, <4 x ptr> %t, <4 x ptr> poison
-```
-
-(int_vp_fcmp)=
-
-#### '`llvm.vp.fcmp.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i1> @llvm.vp.fcmp.v16f32(<16 x float> <left_op>, <16 x float> <right_op>, metadata <condition code>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i1> @llvm.vp.fcmp.nxv4f32(<vscale x 4 x float> <left_op>, <vscale x 4 x float> <right_op>, metadata <condition code>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i1> @llvm.vp.fcmp.v256f64(<256 x double> <left_op>, <256 x double> <right_op>, metadata <condition code>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.fcmp`' intrinsic returns a vector of boolean values based on
-the comparison of its arguments. The operation has a mask and an explicit vector
-length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.fcmp`' intrinsic takes the two values to compare as its first
-and second arguments. These two values must be vectors of {ref}`floating-point <t_floating>` types.
-The return type is the result of the comparison. The return type must be a
-vector of {ref}`i1 <t_integer>` type. The fourth argument is the vector mask.
-The return type, the values to compare, and the vector mask have the same
-number of elements. The third argument is the condition code indicating the kind
-of comparison to perform. It must be a metadata string with {ref}`one of the supported floating-point condition code values <fcmp_md_cc>`. The fifth argument
-is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.fcmp`' compares its first two arguments according to the
-condition code given as the third argument. The arguments are compared element by
-element on each enabled lane, where the semantics of the comparison are
-defined {ref}`according to the condition code <fcmp_md_cc_sem>`. Masked-off
-lanes are `poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i1> @llvm.vp.fcmp.v4f32(<4 x float> %a, <4 x float> %b, metadata !"oeq", <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = fcmp oeq <4 x float> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i1> %t, <4 x i1> poison
-```
-
-(int_vp_icmp)=
-
-#### '`llvm.vp.icmp.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <32 x i1> @llvm.vp.icmp.v32i32(<32 x i32> <left_op>, <32 x i32> <right_op>, metadata <condition code>, <32 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 2 x i1> @llvm.vp.icmp.nxv2i32(<vscale x 2 x i32> <left_op>, <vscale x 2 x i32> <right_op>, metadata <condition code>, <vscale x 2 x i1> <mask>, i32 <vector_length>)
-declare <128 x i1> @llvm.vp.icmp.v128i8(<128 x i8> <left_op>, <128 x i8> <right_op>, metadata <condition code>, <128 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-The '`llvm.vp.icmp`' intrinsic returns a vector of boolean values based on
-the comparison of its arguments. The operation has a mask and an explicit vector
-length parameter.
-
-
-##### Arguments:
-
-The '`llvm.vp.icmp`' intrinsic takes the two values to compare as its first
-and second arguments. These two values must be vectors of {ref}`integer <t_integer>` types.
-The return type is the result of the comparison. The return type must be a
-vector of {ref}`i1 <t_integer>` type. The fourth argument is the vector mask.
-The return type, the values to compare, and the vector mask have the same
-number of elements. The third argument is the condition code indicating the kind
-of comparison to perform. It must be a metadata string with {ref}`one of the supported integer condition code values <icmp_md_cc>`. The fifth argument is the
-explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.icmp`' compares its first two arguments according to the
-condition code given as the third argument. The arguments are compared element by
-element on each enabled lane, where the semantics of the comparison are
-defined {ref}`according to the condition code <icmp_md_cc_sem>`. Masked-off
-lanes are `poison`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i1> @llvm.vp.icmp.v4i32(<4 x i32> %a, <4 x i32> %b, metadata !"ne", <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = icmp ne <4 x i32> %a, %b
-%also.r = select <4 x i1> %mask, <4 x i1> %t, <4 x i1> poison
-```
-
-(int_vp_ceil)=
-
-#### '`llvm.vp.ceil.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.ceil.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.ceil.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.ceil.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point ceiling of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.ceil`' intrinsic performs floating-point ceiling
-({ref}`ceil <int_ceil>`) of the first vector argument on each enabled lane. The
-result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.ceil.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_floor)=
-
-#### '`llvm.vp.floor.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.floor.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.floor.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.floor.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point floor of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.floor`' intrinsic performs floating-point floor
-({ref}`floor <int_floor>`) of the first vector argument on each enabled lane.
-The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.floor.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.floor.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_rint)=
-
-#### '`llvm.vp.rint.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.rint.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.rint.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.rint.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point rint of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.rint`' intrinsic performs floating-point rint
-({ref}`rint <int_rint>`) of the first vector argument on each enabled lane.
-The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.rint.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.rint.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_nearbyint)=
-
-#### '`llvm.vp.nearbyint.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.nearbyint.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.nearbyint.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.nearbyint.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point nearbyint of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.nearbyint`' intrinsic performs floating-point nearbyint
-({ref}`nearbyint <int_nearbyint>`) of the first vector argument on each enabled lane.
-The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.nearbyint.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_round)=
-
-#### '`llvm.vp.round.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.round.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.round.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.round.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point round of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.round`' intrinsic performs floating-point round
-({ref}`round <int_round>`) of the first vector argument on each enabled lane.
-The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.round.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.round.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_roundeven)=
-
-#### '`llvm.vp.roundeven.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.roundeven.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.roundeven.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.roundeven.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point roundeven of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.roundeven`' intrinsic performs floating-point roundeven
-({ref}`roundeven <int_roundeven>`) of the first vector argument on each enabled
-lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.roundeven.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_roundtozero)=
-
-#### '`llvm.vp.roundtozero.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x float> @llvm.vp.roundtozero.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x float> @llvm.vp.roundtozero.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x double> @llvm.vp.roundtozero.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated floating-point round-to-zero of a vector of floating-point values.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of floating-point type.
-The second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.roundtozero`' intrinsic performs floating-point roundeven
-({ref}`llvm.trunc <int_llvm_trunc>`) of the first vector argument on each enabled lane. The
-result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x float> @llvm.vp.roundtozero.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
-```
-
-(int_vp_lrint)=
-
-#### '`llvm.vp.lrint.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.lrint.v16i32.v16f32(<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.lrint.nxv4i32.nxv4f32(<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.lrint.v256i64.v256f64(<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated lrint of a vector of floating-point values.
-
-
-##### Arguments:
-
-The result is an integer vector and the first argument is a vector of {ref}`floating-point <t_floating>`
-type with the same number of elements as the result vector type. The second
-argument is the vector mask and has the same number of elements as the result
-vector type. The third argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.lrint`' intrinsic performs lrint ({ref}`lrint <int_lrint>`) of
-the first vector argument on each enabled lane. The result on disabled lanes is a
-{ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.lrint.v4i32.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x i32> @llvm.lrint.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_llrint)=
-
-#### '`llvm.vp.llrint.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.llrint.v16i32.v16f32(<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.llrint.nxv4i32.nxv4f32(<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.llrint.v256i64.v256f64(<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated llrint of a vector of floating-point values.
-
-
-##### Arguments:
-The result is an integer vector and the first argument is a vector of {ref}`floating-point <t_floating>`
-type with the same number of elements as the result vector type. The second
-argument is the vector mask and has the same number of elements as the result
-vector type. The third argument is the explicit vector length of the operation.
-
-##### Semantics:
-
-The '`llvm.vp.llrint`' intrinsic performs lrint ({ref}`llrint <int_llrint>`) of
-the first vector argument on each enabled lane. The result on disabled lanes is a
-{ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.llrint.v4i32.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x i32> @llvm.llrint.v4f32(<4 x float> %a)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_bitreverse)=
-
-#### '`llvm.vp.bitreverse.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.bitreverse.v16i32 (<16 x i32> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.bitreverse.nxv4i32 (<vscale x 4 x i32> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.bitreverse.v256i64 (<256 x i64> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated bitreverse of a vector of integers.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of integer type. The
-second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.bitreverse`' intrinsic performs bitreverse ({ref}`bitreverse <int_bitreverse>`) of the first argument on each
-enabled lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.bitreverse.v4i32(<4 x i32> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %a)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_bswap)=
-
-#### '`llvm.vp.bswap.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.bswap.v16i32 (<16 x i32> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.bswap.nxv4i32 (<vscale x 4 x i32> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.bswap.v256i64 (<256 x i64> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated bswap of a vector of integers.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of integer type. The
-second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.bswap`' intrinsic performs bswap ({ref}`bswap <int_bswap>`) of the first argument on each
-enabled lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.bswap.v4i32(<4 x i32> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_ctpop)=
-
-#### '`llvm.vp.ctpop.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.ctpop.v16i32 (<16 x i32> <op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.ctpop.nxv4i32 (<vscale x 4 x i32> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.ctpop.v256i64 (<256 x i64> <op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated ctpop of a vector of integers.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of integer type. The
-second argument is the vector mask and has the same number of elements as the
-result vector type. The third argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.ctpop`' intrinsic performs ctpop ({ref}`ctpop <int_ctpop>`) of the first argument on each
-enabled lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.ctpop.v4i32(<4 x i32> %a, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_ctlz)=
-
-#### '`llvm.vp.ctlz.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.ctlz.v16i32 (<16 x i32> <op>, i1 <is_zero_poison>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32 (<vscale x 4 x i32> <op>, i1 <is_zero_poison>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.ctlz.v256i64 (<256 x i64> <op>, i1 <is_zero_poison>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated ctlz of a vector of integers.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of integer type. The
-second argument is a constant flag that indicates whether the intrinsic returns
-a valid result if the first argument is zero. The third argument is the vector
-mask and has the same number of elements as the result vector type. the fourth
-argument is the explicit vector length of the operation. If the first argument
-is zero and the second argument is true, the result is poison.
-
-##### Semantics:
-
-The '`llvm.vp.ctlz`' intrinsic performs ctlz ({ref}`ctlz <int_ctlz>`) of the first argument on each
-enabled lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %a, i1 false, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_cttz)=
-
-#### '`llvm.vp.cttz.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.cttz.v16i32 (<16 x i32> <op>, i1 <is_zero_poison>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32 (<vscale x 4 x i32> <op>, i1 <is_zero_poison>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.cttz.v256i64 (<256 x i64> <op>, i1 <is_zero_poison>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated cttz of a vector of integers.
-
-
-##### Arguments:
-
-The first argument and the result have the same vector of integer type. The
-second argument is a constant flag that indicates whether the intrinsic
-returns a valid result if the first argument is zero. The third argument is
-the vector mask and has the same number of elements as the result vector type.
-The fourth argument is the explicit vector length of the operation. If the
-first argument is zero and the second argument is true, the result is poison.
-
-##### Semantics:
-
-The '`llvm.vp.cttz`' intrinsic performs cttz ({ref}`cttz <int_cttz>`) of the first argument on each
-enabled lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
-
-##### Examples:
-
-```llvm
-%r = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %a, i1 false, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
-```
-
-(int_vp_cttz_elts)=
-
-#### '`llvm.vp.cttz.elts.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic. You can use `llvm.vp.cttz.elts` on any
-vector of integer elements, both fixed width and scalable.
-
-```
-declare i32 @llvm.vp.cttz.elts.i32.v16i32 (<16 x i32> <op>, i1 <is_zero_poison>, <16 x i1> <mask>, i32 <vector_length>)
-declare i64 @llvm.vp.cttz.elts.i64.nxv4i32 (<vscale x 4 x i32> <op>, i1 <is_zero_poison>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare i64 @llvm.vp.cttz.elts.i64.v256i1 (<256 x i1> <op>, i1 <is_zero_poison>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-This '`llvm.vp.cttz.elts`' intrinsic counts the number of trailing zero
-elements of a vector. This is basically the vector-predicated version of
-'`llvm.experimental.cttz.elts`'.
-
-##### Arguments:
-
-The first argument is the vector to be counted. This argument must be a vector
-with integer element type. The return type must also be an integer type which is
-wide enough to hold the maximum number of elements of the source vector. The
-result is a {ref}`poison value <poisonvalues>` if the return type is not wide
-enough for the number of elements in the input vector.
-
-The second argument is a constant flag that indicates whether the intrinsic
-returns a valid result if the first argument is all zero.
-
-The third argument is the vector mask and has the same number of elements as the
-input vector type. The fourth argument is the explicit vector length of the
-operation.
-
-##### Semantics:
-
-The '`llvm.vp.cttz.elts`' intrinsic counts the trailing (least
-significant / lowest-numbered) zero elements in the first argument on each
-enabled lane. If the first argument is all zero and the second argument is true,
-the result is poison. Otherwise, it returns the explicit vector length (i.e., the
-fourth argument).
-
-(int_vp_sadd_sat)=
-
-#### '`llvm.vp.sadd.sat.*`' Intrinsics
-
-##### Syntax:
-This is an overloaded intrinsic.
-
-```
-declare <16 x i32> @llvm.vp.sadd.sat.v16i32 (<16 x i32> <left_op> <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.sadd.sat.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
-```
-
-##### Overview:
-
-Predicated signed saturating addition of two vectors of integers.
+The '`llvm.vp.load.ff`' is designed for reading vector lanes in a single
+IR operation where the number of lanes that can be read is not known and can
+only be determined by looking at the data. This is useful for vectorizing
+strcmp or strlen like loops where the data contains a null terminator. Some
+targets have a fault-only-first load instruction that this intrinsic can be
+lowered to. Other targets may support this intrinsic differently, for example by
+lowering to a single scalar load guarded by `evl!=0` and `mask[0]==1` and
+indicating only 1 lane could be read.
+Like '`llvm.vp.load`', this intrinsic reads memory based on a `mask` and an
+`evl`. If `evl` is non-zero and the first lane is masked-on, then the
+first lane of the vector needs to be inbounds of an allocation. The remaining
+masked-on lanes with index less than `evl` do not need to be inbounds of
+an the same allocation or any allocation.
-##### Arguments:
+The second return value from the intrinsic indicates the index of the first
+lane that could not be read for some reason or `evl` if all lanes could be
+be read. Lanes at this index or higher in the first return value are
+{ref}`poison value <poisonvalues>`. If `evl` is non-zero, the result in the
+second return value must be at least 1, even if the first lane is masked-off.
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The second result is usually less than `evl` when an exception would occur
+for reading that lane, but it can be reduced for any reason. This facilitates
+emulating this intrinsic when the hardware only supports narrower vector
+types natively or when when hardware does not support fault-only-first loads.
-##### Semantics:
+Masked-on lanes that are not inbounds of the allocation that contains the first
+lane are {ref}`poison value <poisonvalues>`. There should be a marker in the
+allocation that indicates where valid data stops such as a null terminator. The
+terminator should be checked for after calling this intrinsic to prevent using
+any lanes past the terminator. Even if second return value is less than
+`evl`, the terminator value may not have been read.
-The '`llvm.vp.sadd.sat`' intrinsic performs sadd.sat ({ref}`sadd.sat <int_sadd_sat>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+This intrinsic will typically be called in a loop until a terminator is
+found. The second result should be used to indicates how many elements are
+valid to look for the null terminator. If the terminator is not found, the
+pointer should be advanced by the number of elements in the second result and
+the intrinsic called again.
+The default alignment is taken as the ABI alignment of the first return
+type as specified by the {ref}`datalayout string<langref_datalayout>`.
##### Examples:
-```llvm
-%r = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-
-%t = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+```text
+%r = call {<8 x i8>, i32} @llvm.vp.load.ff.v8i8.p0(ptr align 2 %ptr, <8 x i1> %mask, i32 %evl)
```
-(int_vp_uadd_sat)=
+(int_vp_store)=
-#### '`llvm.vp.uadd.sat.*`' Intrinsics
+#### '`llvm.vp.store`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.uadd.sat.v16i32 (<16 x i32> <left_op> <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.uadd.sat.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare void @llvm.vp.store.v4f32.p0(<4 x float> %val, ptr %ptr, <4 x i1> %mask, i32 %evl)
+declare void @llvm.vp.store.nxv2i16.p0(<vscale x 2 x i16> %val, ptr %ptr, <vscale x 2 x i1> %mask, i32 %evl)
+declare void @llvm.vp.store.v8f32.p1(<8 x float> %val, ptr addrspace(1) %ptr, <8 x i1> %mask, i32 %evl)
+declare void @llvm.vp.store.nxv1i64.p6(<vscale x 1 x i64> %val, ptr addrspace(6) %ptr, <vscale x 1 x i1> %mask, i32 %evl)
```
##### Overview:
-Predicated unsigned saturating addition of two vectors of integers.
-
+The '`llvm.vp.store.*`' intrinsic is the vector length predicated version of
+the {ref}`llvm.masked.store <int_mstore>` intrinsic.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the vector value to be written to memory. The second
+argument is the base pointer for the store. It has the same underlying type as
+the value argument. The third argument is a vector of boolean values with the
+same number of elements as the return type. The fourth is the explicit vector
+length of the operation.
-##### Semantics:
+The {ref}`align <attr_align>` parameter attribute can be provided for the
+second argument.
-The '`llvm.vp.uadd.sat`' intrinsic performs uadd.sat ({ref}`uadd.sat <int_uadd_sat>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+##### Semantics:
+The '`llvm.vp.store`' intrinsic reads a vector from memory in the same way as
+the '`llvm.masked.store`' intrinsic, where the mask is taken from the
+combination of the '`mask`' and '`evl`' arguments in the usual VP way. The
+alignment of the operation (corresponding to the '`alignment`' argument of
+'`llvm.masked.store`') is specified by the `align` parameter attribute (see
+above). If it is not provided then the ABI alignment of the type of the
+'`value`' argument as specified by the {ref}`datalayout string<langref_datalayout>` is used instead.
##### Examples:
-```llvm
-%r = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+```text
+call void @llvm.vp.store.v8i8.p0(<8 x i8> %val, ptr align 4 %ptr, <8 x i1> %mask, i32 %evl)
+;; For all lanes below %evl, the call above is lane-wise equivalent to the call below.
-%t = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+call void @llvm.masked.store.v8i8.p0(<8 x i8> %val, ptr %ptr, i32 4, <8 x i1> %mask)
```
-(int_vp_ssub_sat)=
+(int_experimental_vp_strided_load)=
-#### '`llvm.vp.ssub.sat.*`' Intrinsics
+#### '`llvm.experimental.vp.strided.load`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.ssub.sat.v16i32 (<16 x i32> <left_op> <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.ssub.sat.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare <4 x float> @llvm.experimental.vp.strided.load.v4f32.i64(ptr %ptr, i64 %stride, <4 x i1> %mask, i32 %evl)
+declare <vscale x 2 x i16> @llvm.experimental.vp.strided.load.nxv2i16.i64(ptr %ptr, i64 %stride, <vscale x 2 x i1> %mask, i32 %evl)
```
##### Overview:
-Predicated signed saturating subtraction of two vectors of integers.
-
+The '`llvm.experimental.vp.strided.load`' intrinsic loads, into a vector, scalar values from
+memory locations evenly spaced apart by '`stride`' number of bytes, starting from '`ptr`'.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the base pointer for the load. The second argument is the stride
+value expressed in bytes. The third argument is a vector of boolean values
+with the same number of elements as the return type. The fourth is the explicit
+vector length of the operation. The base pointer underlying type matches the type of the scalar
+elements of the return argument.
+
+The {ref}`align <attr_align>` parameter attribute can be provided for the first
+argument.
##### Semantics:
-The '`llvm.vp.ssub.sat`' intrinsic performs ssub.sat ({ref}`ssub.sat <int_ssub_sat>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.experimental.vp.strided.load`' intrinsic loads, into a vector, multiple scalar
+values from memory in the same way as the {ref}`llvm.vp.gather <int_vp_gather>` intrinsic,
+where the vector of pointers is in the form:
+
+`%ptrs = <%ptr, %ptr + %stride, %ptr + 2 * %stride, ... >`,
+with '`ptr`' previously casted to a pointer '`i8`', '`stride`' always interpreted as a signed
+integer and all arithmetic occurring in the pointer type.
##### Examples:
-```llvm
-%r = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+```text
+%r = call <8 x i64> @llvm.experimental.vp.strided.load.v8i64.i64(i64* %ptr, i64 %stride, <8 x i64> %mask, i32 %evl)
+;; The operation can also be expressed like this:
-%t = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%addr = bitcast i64* %ptr to i8*
+;; Create a vector of pointers %addrs in the form:
+;; %addrs = <%addr, %addr + %stride, %addr + 2 * %stride, ...>
+%ptrs = bitcast <8 x i8* > %addrs to <8 x i64* >
+%also.r = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64* > %ptrs, <8 x i64> %mask, i32 %evl)
```
-(int_vp_usub_sat)=
-#### '`llvm.vp.usub.sat.*`' Intrinsics
+(int_experimental_vp_strided_store)=
+
+#### '`llvm.experimental.vp.strided.store`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.usub.sat.v16i32 (<16 x i32> <left_op> <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.usub.sat.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare void @llvm.experimental.vp.strided.store.v4f32.i64(<4 x float> %val, ptr %ptr, i64 %stride, <4 x i1> %mask, i32 %evl)
+declare void @llvm.experimental.vp.strided.store.nxv2i16.i64(<vscale x 2 x i16> %val, ptr %ptr, i64 %stride, <vscale x 2 x i1> %mask, i32 %evl)
```
##### Overview:
-Predicated unsigned saturating subtraction of two vectors of integers.
-
+The '`@llvm.experimental.vp.strided.store`' intrinsic stores the elements of
+'`val`' into memory locations evenly spaced apart by '`stride`' number of
+bytes, starting from '`ptr`'.
##### Arguments:
-The first two arguments and the result have the same vector of integer type. The
-third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
-operation.
+The first argument is the vector value to be written to memory. The second
+argument is the base pointer for the store. Its underlying type matches the
+scalar element type of the value argument. The third argument is the stride value
+expressed in bytes. The fourth argument is a vector of boolean values with the
+same number of elements as the return type. The fifth is the explicit vector
+length of the operation.
+
+The {ref}`align <attr_align>` parameter attribute can be provided for the
+second argument.
##### Semantics:
-The '`llvm.vp.usub.sat`' intrinsic performs usub.sat ({ref}`usub.sat <int_usub_sat>`)
-of the first and second vector arguments on each enabled lane. The result on
-disabled lanes is a {ref}`poison value <poisonvalues>`.
+The '`llvm.experimental.vp.strided.store`' intrinsic stores the elements of
+'`val`' in the same way as the {ref}`llvm.vp.scatter <int_vp_scatter>` intrinsic,
+where the vector of pointers is in the form:
+
+`%ptrs = <%ptr, %ptr + %stride, %ptr + 2 * %stride, ... >`,
+with '`ptr`' previously casted to a pointer '`i8`', '`stride`' always interpreted as a signed
+integer and all arithmetic occurring in the pointer type.
##### Examples:
-```llvm
-%r = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+```text
+call void @llvm.experimental.vp.strided.store.v8i64.i64(<8 x i64> %val, i64* %ptr, i64 %stride, <8 x i1> %mask, i32 %evl)
+;; The operation can also be expressed like this:
-%t = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%addr = bitcast i64* %ptr to i8*
+;; Create a vector of pointers %addrs in the form:
+;; %addrs = <%addr, %addr + %stride, %addr + 2 * %stride, ...>
+%ptrs = bitcast <8 x i8* > %addrs to <8 x i64* >
+call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %mask, i32 %evl)
```
-(int_vp_fshl)=
-#### '`llvm.vp.fshl.*`' Intrinsics
+(int_vp_gather)=
+
+#### '`llvm.vp.gather`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.fshl.v16i32 (<16 x i32> <left_op>, <16 x i32> <middle_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.fshl.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <middle_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.fshl.v256i64 (<256 x i64> <left_op>, <256 x i64> <middle_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare <4 x double> @llvm.vp.gather.v4f64.v4p0(<4 x ptr> %ptrs, <4 x i1> %mask, i32 %evl)
+declare <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0(<vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %mask, i32 %evl)
+declare <2 x float> @llvm.vp.gather.v2f32.v2p2(<2 x ptr addrspace(2)> %ptrs, <2 x i1> %mask, i32 %evl)
+declare <vscale x 4 x i32> @llvm.vp.gather.nxv4i32.nxv4p4(<vscale x 4 x ptr addrspace(4)> %ptrs, <vscale x 4 x i1> %mask, i32 %evl)
```
##### Overview:
-Predicated fshl of three vectors of integers.
-
+The '`llvm.vp.gather.*`' intrinsic is the vector length predicated version of
+the {ref}`llvm.masked.gather <int_mgather>` intrinsic.
##### Arguments:
-The first three arguments and the result have the same vector of integer type. The
-fourth argument is the vector mask and has the same number of elements as the
-result vector type. The fifth argument is the explicit vector length of the
-operation.
+The first argument is a vector of pointers which holds all memory addresses to
+read. The second argument is a vector of boolean values with the same number of
+elements as the return type. The third is the explicit vector length of the
+operation. The return type and underlying type of the vector of pointers are
+the same vector types.
-##### Semantics:
+The {ref}`align <attr_align>` parameter attribute can be provided for the first
+argument.
-The '`llvm.vp.fshl`' intrinsic performs fshl ({ref}`fshl <int_fshl>`) of the first, second, and third
-vector argument on each enabled lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
+##### Semantics:
+The '`llvm.vp.gather`' intrinsic reads multiple scalar values from memory in
+the same way as the '`llvm.masked.gather`' intrinsic, where the mask is taken
+from the combination of the '`mask`' and '`evl`' arguments in the usual VP
+way. Certain '`llvm.masked.gather`' arguments do not have corresponding
+arguments in '`llvm.vp.gather`': the '`passthru`' argument is implicitly
+`poison`; the '`alignment`' argument is taken as the `align` parameter, if
+provided. The default alignment is taken as the ABI alignment of the source
+addresses as specified by the {ref}`datalayout string<langref_datalayout>`.
##### Examples:
-```llvm
-%r = call <4 x i32> @llvm.vp.fshl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %mask, i32 %evl)
+```text
+%r = call <8 x i8> @llvm.vp.gather.v8i8.v8p0(<8 x ptr> align 8 %ptrs, <8 x i1> %mask, i32 %evl)
;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
-%t = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+%also.r = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> align 8 %ptrs, <8 x i1> %mask, <8 x i8> poison)
```
-#### '`llvm.vp.fshr.*`' Intrinsics
+(int_vp_scatter)=
+
+#### '`llvm.vp.scatter`' Intrinsic
##### Syntax:
This is an overloaded intrinsic.
```
-declare <16 x i32> @llvm.vp.fshr.v16i32 (<16 x i32> <left_op>, <16 x i32> <middle_op>, <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
-declare <vscale x 4 x i32> @llvm.vp.fshr.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <middle_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
-declare <256 x i64> @llvm.vp.fshr.v256i64 (<256 x i64> <left_op>, <256 x i64> <middle_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
+declare void @llvm.vp.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, <4 x i1> %mask, i32 %evl)
+declare void @llvm.vp.scatter.nxv2i8.nxv2p0(<vscale x 2 x i8> %val, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %mask, i32 %evl)
+declare void @llvm.vp.scatter.v2f32.v2p2(<2 x float> %val, <2 x ptr addrspace(2)> %ptrs, <2 x i1> %mask, i32 %evl)
+declare void @llvm.vp.scatter.nxv4i32.nxv4p4(<vscale x 4 x i32> %val, <vscale x 4 x ptr addrspace(4)> %ptrs, <vscale x 4 x i1> %mask, i32 %evl)
```
##### Overview:
-Predicated fshr of three vectors of integers.
-
+The '`llvm.vp.scatter.*`' intrinsic is the vector length predicated version of
+the {ref}`llvm.masked.scatter <int_mscatter>` intrinsic.
##### Arguments:
-The first three arguments and the result have the same vector of integer type. The
-fourth argument is the vector mask and has the same number of elements as the
-result vector type. The fifth argument is the explicit vector length of the
+The first argument is a vector value to be written to memory. The second argument
+is a vector of pointers, pointing to where the value elements should be stored.
+The third argument is a vector of boolean values with the same number of
+elements as the return type. The fourth is the explicit vector length of the
operation.
-##### Semantics:
+The {ref}`align <attr_align>` parameter attribute can be provided for the
+second argument.
-The '`llvm.vp.fshr`' intrinsic performs fshr ({ref}`fshr <int_fshr>`) of the first, second, and third
-vector argument on each enabled lane. The result on disabled lanes is a {ref}`poison value <poisonvalues>`.
+##### Semantics:
+The '`llvm.vp.scatter`' intrinsic writes multiple scalar values to memory in
+the same way as the '`llvm.masked.scatter`' intrinsic, where the mask is
+taken from the combination of the '`mask`' and '`evl`' arguments in the
+usual VP way. The '`alignment`' argument of the '`llvm.masked.scatter`' does
+not have a corresponding argument in '`llvm.vp.scatter`': it is instead
+provided via the optional `align` parameter attribute on the
+vector-of-pointers argument. Otherwise it is taken as the ABI alignment of the
+destination addresses as specified by the {ref}`datalayout string<langref_datalayout>`.
##### Examples:
-```llvm
-%r = call <4 x i32> @llvm.vp.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %mask, i32 %evl)
-;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+```text
+call void @llvm.vp.scatter.v8i8.v8p0(<8 x i8> %val, <8 x ptr> align 1 %ptrs, <8 x i1> %mask, i32 %evl)
+;; For all lanes below %evl, the call above is lane-wise equivalent to the call below.
-%t = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
-%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
+call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> %val, <8 x ptr> align 1 %ptrs, <8 x i1> %mask)
```
-#### '`llvm.vp.is.fpclass.*`' Intrinsics
+(int_vp_cttz_elts)=
+
+#### '`llvm.vp.cttz.elts.*`' Intrinsics
##### Syntax:
-This is an overloaded intrinsic.
+This is an overloaded intrinsic. You can use `llvm.vp.cttz.elts` on any
+vector of integer elements, both fixed width and scalable.
```
-declare <vscale x 2 x i1> @llvm.vp.is.fpclass.nxv2f32(<vscale x 2 x float> <op>, i32 <test>, <vscale x 2 x i1> <mask>, i32 <vector_length>)
-declare <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half> <op>, i32 <test>, <2 x i1> <mask>, i32 <vector_length>)
+declare i32 @llvm.vp.cttz.elts.i32.v16i32 (<16 x i32> <op>, i1 <is_zero_poison>, <16 x i1> <mask>, i32 <vector_length>)
+declare i64 @llvm.vp.cttz.elts.i64.nxv4i32 (<vscale x 4 x i32> <op>, i1 <is_zero_poison>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
+declare i64 @llvm.vp.cttz.elts.i64.v256i1 (<256 x i1> <op>, i1 <is_zero_poison>, <256 x i1> <mask>, i32 <vector_length>)
```
##### Overview:
-Predicated `llvm.is.fpclass` {ref}`llvm.is.fpclass <llvm.is.fpclass>`
+This '`llvm.vp.cttz.elts`' intrinsic counts the number of trailing zero
+elements of a vector. This is basically the vector-predicated version of
+'`llvm.experimental.cttz.elts`'.
##### Arguments:
-The first argument is a floating-point vector, the result type is a vector of
-boolean with the same number of elements as the first argument. The second
-argument specifies, which tests to perform {ref}`llvm.is.fpclass <llvm.is.fpclass>`.
+The first argument is the vector to be counted. This argument must be a vector
+with integer element type. The return type must also be an integer type which is
+wide enough to hold the maximum number of elements of the source vector. The
+result is a {ref}`poison value <poisonvalues>` if the return type is not wide
+enough for the number of elements in the input vector.
+
+The second argument is a constant flag that indicates whether the intrinsic
+returns a valid result if the first argument is all zero.
+
The third argument is the vector mask and has the same number of elements as the
-result vector type. The fourth argument is the explicit vector length of the
+input vector type. The fourth argument is the explicit vector length of the
operation.
##### Semantics:
-The '`llvm.vp.is.fpclass`' intrinsic performs `llvm.is.fpclass` ({ref}`llvm.is.fpclass <llvm.is.fpclass>`).
-
-
-##### Examples:
+The '`llvm.vp.cttz.elts`' intrinsic counts the trailing (least
+significant / lowest-numbered) zero elements in the first argument on each
+enabled lane. If the first argument is all zero and the second argument is true,
+the result is poison. Otherwise, it returns the explicit vector length (i.e., the
+fourth argument).
-```llvm
-%r = call <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half> %x, i32 3, <2 x i1> %m, i32 %evl)
-%t = call <vscale x 2 x i1> @llvm.vp.is.fpclass.nxv2f16(<vscale x 2 x half> %x, i32 3, <vscale x 2 x i1> %m, i32 %evl)
-```
(int_mload_mstore)=
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 5b88859ba090b..87ad9d6516680 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1821,26 +1821,13 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
return thisT()->getMemoryOpCost(*FOp, ICA.getArgTypes()[0], Alignment,
AS, CostKind);
}
- if (VPBinOpIntrinsic::isVPBinOp(ICA.getID()) ||
- ICA.getID() == Intrinsic::vp_fneg) {
+ if (ICA.getID() == Intrinsic::vp_udiv ||
+ ICA.getID() == Intrinsic::vp_sdiv ||
+ ICA.getID() == Intrinsic::vp_urem ||
+ ICA.getID() == Intrinsic::vp_srem) {
return thisT()->getArithmeticInstrCost(*FOp, ICA.getReturnType(),
CostKind);
}
- if (VPCastIntrinsic::isVPCast(ICA.getID())) {
- return thisT()->getCastInstrCost(
- *FOp, ICA.getReturnType(), ICA.getArgTypes()[0],
- TTI::CastContextHint::None, CostKind);
- }
- if (VPCmpIntrinsic::isVPCmp(ICA.getID())) {
- // We can only handle vp_cmp intrinsics with underlying instructions.
- if (ICA.getInst()) {
- assert(FOp);
- auto *UI = cast<VPCmpIntrinsic>(ICA.getInst());
- return thisT()->getCmpSelInstrCost(*FOp, ICA.getArgTypes()[0],
- ICA.getReturnType(),
- UI->getPredicate(), CostKind);
- }
- }
}
if (ICA.getID() == Intrinsic::vp_load_ff) {
Type *RetTy = ICA.getReturnType();
@@ -1889,8 +1876,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
CostKind);
}
- if (ICA.getID() == Intrinsic::vp_select ||
- ICA.getID() == Intrinsic::vp_merge) {
+ if (ICA.getID() == Intrinsic::vp_merge) {
TTI::OperandValueInfo OpInfoX, OpInfoY;
if (!ICA.isTypeBasedOnly()) {
OpInfoX = TTI::getOperandInfo(ICA.getArgs()[0]);
diff --git a/llvm/include/llvm/IR/IntrinsicInst.h b/llvm/include/llvm/IR/IntrinsicInst.h
index 1f752c51f0b97..7c0d9889a6d1a 100644
--- a/llvm/include/llvm/IR/IntrinsicInst.h
+++ b/llvm/include/llvm/IR/IntrinsicInst.h
@@ -633,11 +633,6 @@ class VPIntrinsic : public IntrinsicInst {
return getFunctionalIntrinsicIDForVP(getIntrinsicID());
}
- // Equivalent non-predicated constrained ID
- std::optional<unsigned> getConstrainedIntrinsicID() const {
- return getConstrainedIntrinsicIDForVP(getIntrinsicID());
- }
-
// Equivalent non-predicated opcode
LLVM_ABI static std::optional<unsigned>
getFunctionalOpcodeForVP(Intrinsic::ID ID);
@@ -645,10 +640,6 @@ class VPIntrinsic : public IntrinsicInst {
// Equivalent non-predicated intrinsic ID
LLVM_ABI static std::optional<Intrinsic::ID>
getFunctionalIntrinsicIDForVP(Intrinsic::ID ID);
-
- // Equivalent non-predicated constrained ID
- LLVM_ABI static std::optional<Intrinsic::ID>
- getConstrainedIntrinsicIDForVP(Intrinsic::ID ID);
};
/// This represents vector predication reduction intrinsics.
@@ -673,54 +664,6 @@ class VPReductionIntrinsic : public VPIntrinsic {
/// @}
};
-class VPCastIntrinsic : public VPIntrinsic {
-public:
- LLVM_ABI static bool isVPCast(Intrinsic::ID ID);
-
- /// Methods for support type inquiry through isa, cast, and dyn_cast:
- /// @{
- static bool classof(const IntrinsicInst *I) {
- return VPCastIntrinsic::isVPCast(I->getIntrinsicID());
- }
- static bool classof(const Value *V) {
- return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
- }
- /// @}
-};
-
-class VPCmpIntrinsic : public VPIntrinsic {
-public:
- LLVM_ABI static bool isVPCmp(Intrinsic::ID ID);
-
- LLVM_ABI CmpInst::Predicate getPredicate() const;
-
- /// Methods for support type inquiry through isa, cast, and dyn_cast:
- /// @{
- static bool classof(const IntrinsicInst *I) {
- return VPCmpIntrinsic::isVPCmp(I->getIntrinsicID());
- }
- static bool classof(const Value *V) {
- return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
- }
- /// @}
-};
-
-class VPBinOpIntrinsic : public VPIntrinsic {
-public:
- LLVM_ABI static bool isVPBinOp(Intrinsic::ID ID);
-
- /// Methods for support type inquiry through isa, cast, and dyn_cast:
- /// @{
- static bool classof(const IntrinsicInst *I) {
- return VPBinOpIntrinsic::isVPBinOp(I->getIntrinsicID());
- }
- static bool classof(const Value *V) {
- return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
- }
- /// @}
-};
-
-
/// This is the common base class for constrained floating point intrinsics.
class ConstrainedFPIntrinsic : public IntrinsicInst {
public:
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 083b933e77d16..12211799e358c 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -2248,307 +2248,12 @@ def int_experimental_vector_extract_last_active:
// Operators
let IntrProperties = [IntrNoMem, IntrSpeculatable] in {
- // Integer arithmetic
- def int_vp_add : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_sub : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_mul : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_ashr : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_lshr : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_shl : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_or : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_and : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_xor : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_abs : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- llvm_i1_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_smin : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_smax : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_umin : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_umax : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_bswap : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_bitreverse : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_ctpop : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fshl : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fshr : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_sadd_sat : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_uadd_sat : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_ssub_sat : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_usub_sat : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
-
- // Floating-point arithmetic
- def int_vp_fadd : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fsub : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fmul : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fdiv : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_frem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fneg : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fabs : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_sqrt : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fma : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fmuladd : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_minnum : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_maxnum : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_minimum : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_maximum : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_copysign : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_ceil : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_floor : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_round : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_roundeven : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_roundtozero : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_rint : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_nearbyint : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_lrint : DefaultAttrsIntrinsic<[ llvm_any_vector_int_ty ],
- [ llvm_any_vector_float_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_llrint : DefaultAttrsIntrinsic<[ llvm_any_vector_int_ty ],
- [ llvm_any_vector_float_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
-
- // Casts
- def int_vp_trunc : DefaultAttrsIntrinsic<[ llvm_any_vector_int_ty ],
- [ llvm_any_vector_int_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_zext : DefaultAttrsIntrinsic<[ llvm_any_vector_int_ty ],
- [ llvm_any_vector_int_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_sext : DefaultAttrsIntrinsic<[ llvm_any_vector_int_ty ],
- [ llvm_any_vector_int_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fptrunc : DefaultAttrsIntrinsic<[ llvm_any_vector_float_ty ],
- [ llvm_any_vector_float_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fpext : DefaultAttrsIntrinsic<[ llvm_any_vector_float_ty ],
- [ llvm_any_vector_float_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fptoui : DefaultAttrsIntrinsic<[ llvm_any_vector_int_ty ],
- [ llvm_any_vector_float_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_fptosi : DefaultAttrsIntrinsic<[ llvm_any_vector_int_ty ],
- [ llvm_any_vector_float_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_uitofp : DefaultAttrsIntrinsic<[ llvm_any_vector_float_ty ],
- [ llvm_any_vector_int_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_sitofp : DefaultAttrsIntrinsic<[ llvm_any_vector_float_ty ],
- [ llvm_any_vector_int_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_ptrtoint : DefaultAttrsIntrinsic<[ llvm_any_vector_int_ty ],
- [ llvm_any_vector_ptr_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_inttoptr : DefaultAttrsIntrinsic<[ llvm_any_vector_ptr_ty ],
- [ llvm_any_vector_int_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- // Shuffles
- def int_vp_select : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- LLVMMatchType<0>,
- LLVMMatchType<0>,
- llvm_i32_ty]>;
def int_vp_merge : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<0>,
LLVMMatchType<0>,
llvm_i32_ty]>;
- // Comparisons
- def int_vp_fcmp : DefaultAttrsIntrinsic<
- [ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ],
- [ llvm_anyvector_ty,
- LLVMMatchType<0>,
- llvm_metadata_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_icmp : DefaultAttrsIntrinsic<
- [ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ],
- [ llvm_anyvector_ty,
- LLVMMatchType<0>,
- llvm_metadata_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
-
// Reductions
def int_vp_reduce_fadd : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[ LLVMVectorElementType<0>,
@@ -2649,24 +2354,12 @@ def int_vp_urem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty], [IntrNoMem]>;
-let IntrProperties = [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>] in {
- def int_vp_ctlz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- llvm_i1_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
- def int_vp_cttz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
- [ LLVMMatchType<0>,
- llvm_i1_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty]>;
-
+let IntrProperties = [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>] in
def int_vp_cttz_elts : DefaultAttrsIntrinsic<[ llvm_anyint_ty ],
[ llvm_anyvector_ty,
llvm_i1_ty,
LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>,
llvm_i32_ty]>;
-}
def int_loop_dependence_raw_mask:
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
@@ -2710,15 +2403,6 @@ def int_experimental_vp_reverse:
llvm_i32_ty],
[IntrNoMem, IntrSpeculatable]>;
-def int_vp_is_fpclass:
- DefaultAttrsIntrinsic<[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
- [ llvm_anyvector_ty,
- llvm_i32_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_i32_ty],
- [ IntrNoMem, IntrSpeculatable,
- ImmArg<ArgIndex<1>>]>;
-
//===-------------------------- Masked Intrinsics -------------------------===//
//
def int_masked_load:
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index 7015bd5a6f0ce..669343f5c2e5c 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -133,11 +133,10 @@
"The internal helper macro HELPER_REGISTER_BINARY_INT_VP is already defined!"
#endif
#define HELPER_REGISTER_BINARY_INT_VP(VPID, VPSD, IROPC, SDOPC) \
- BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, -1) \
- VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
+ BEGIN_REGISTER_VP_SDNODE(VPSD, -1, VPID, 2, 3) \
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
VP_PROPERTY_BINARYOP \
- END_REGISTER_VP(VPID, VPSD)
+ END_REGISTER_VP_SDNODE(VPSD)
// llvm.vp.add(x,y,mask,vlen)
HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add, ADD)
@@ -158,22 +157,38 @@ HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul, MUL)
HELPER_REGISTER_BINARY_INT_VP(vp_or, VP_OR, Or, OR)
// llvm.vp.sdiv(x,y,mask,vlen)
+BEGIN_REGISTER_VP_INTRINSIC(vp_sdiv, 2, 3)
+HELPER_MAP_VPID_TO_VPSD(vp_sdiv, VP_SDIV)
+VP_PROPERTY_FUNCTIONAL_OPC(SDiv)
HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv, SDIV)
+END_REGISTER_VP_INTRINSIC(vp_sdiv)
// llvm.vp.shl(x,y,mask,vlen)
HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl, SHL)
// llvm.vp.srem(x,y,mask,vlen)
+BEGIN_REGISTER_VP_INTRINSIC(vp_srem, 2, 3)
+HELPER_MAP_VPID_TO_VPSD(vp_srem, VP_SREM)
+VP_PROPERTY_FUNCTIONAL_OPC(SRem)
HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem, SREM)
+END_REGISTER_VP_INTRINSIC(vp_srem)
// llvm.vp.sub(x,y,mask,vlen)
HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub, SUB)
// llvm.vp.udiv(x,y,mask,vlen)
+BEGIN_REGISTER_VP_INTRINSIC(vp_udiv, 2, 3)
+HELPER_MAP_VPID_TO_VPSD(vp_udiv, VP_UDIV)
+VP_PROPERTY_FUNCTIONAL_OPC(UDiv)
HELPER_REGISTER_BINARY_INT_VP(vp_udiv, VP_UDIV, UDiv, UDIV)
+END_REGISTER_VP_INTRINSIC(vp_udiv)
// llvm.vp.urem(x,y,mask,vlen)
+BEGIN_REGISTER_VP_INTRINSIC(vp_urem, 2, 3)
+HELPER_MAP_VPID_TO_VPSD(vp_urem, VP_UREM)
+VP_PROPERTY_FUNCTIONAL_OPC(URem)
HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem, UREM)
+END_REGISTER_VP_INTRINSIC(vp_urem)
// llvm.vp.xor(x,y,mask,vlen)
HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor, XOR)
@@ -181,79 +196,63 @@ HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor, XOR)
#undef HELPER_REGISTER_BINARY_INT_VP
// llvm.vp.smin(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_smin, 2, 3, VP_SMIN, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_SMIN, -1, vp_smin, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(SMIN)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(smin)
-END_REGISTER_VP(vp_smin, VP_SMIN)
+END_REGISTER_VP_SDNODE(VP_SMIN)
// llvm.vp.smax(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_smax, 2, 3, VP_SMAX, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_SMAX, -1, vp_smax, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(SMAX)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(smax)
-END_REGISTER_VP(vp_smax, VP_SMAX)
+END_REGISTER_VP_SDNODE(VP_SMAX)
// llvm.vp.umin(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_umin, 2, 3, VP_UMIN, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_UMIN, -1, vp_umin, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(UMIN)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(umin)
-END_REGISTER_VP(vp_umin, VP_UMIN)
+END_REGISTER_VP_SDNODE(VP_UMIN)
// llvm.vp.umax(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_umax, 2, 3, VP_UMAX, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_UMAX, -1, vp_umax, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(UMAX)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(umax)
-END_REGISTER_VP(vp_umax, VP_UMAX)
+END_REGISTER_VP_SDNODE(VP_UMAX)
// llvm.vp.abs(x,is_int_min_poison,mask,vlen)
-BEGIN_REGISTER_VP_INTRINSIC(vp_abs, 2, 3)
BEGIN_REGISTER_VP_SDNODE(VP_ABS, -1, vp_abs, 1, 2)
-HELPER_MAP_VPID_TO_VPSD(vp_abs, VP_ABS)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(abs)
VP_PROPERTY_FUNCTIONAL_SDOPC(ABS)
-END_REGISTER_VP(vp_abs, VP_ABS)
+END_REGISTER_VP_SDNODE(VP_ABS)
// llvm.vp.bswap(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_bswap, 1, 2, VP_BSWAP, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(bswap)
+BEGIN_REGISTER_VP_SDNODE(VP_BSWAP, -1, vp_bswap, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(BSWAP)
-END_REGISTER_VP(vp_bswap, VP_BSWAP)
+END_REGISTER_VP_SDNODE(VP_BSWAP)
// llvm.vp.bitreverse(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_bitreverse, 1, 2, VP_BITREVERSE, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(bitreverse)
+BEGIN_REGISTER_VP_SDNODE(VP_BITREVERSE, -1, vp_bitreverse, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(BITREVERSE)
-END_REGISTER_VP(vp_bitreverse, VP_BITREVERSE)
+END_REGISTER_VP_SDNODE(VP_BITREVERSE)
// llvm.vp.ctpop(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_ctpop, 1, 2, VP_CTPOP, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctpop)
+BEGIN_REGISTER_VP_SDNODE(VP_CTPOP, -1, vp_ctpop, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(CTPOP)
-END_REGISTER_VP(vp_ctpop, VP_CTPOP)
+END_REGISTER_VP_SDNODE(VP_CTPOP)
// llvm.vp.ctlz(x,is_zero_poison,mask,vlen)
-BEGIN_REGISTER_VP_INTRINSIC(vp_ctlz, 2, 3)
BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(ctlz)
VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ)
END_REGISTER_VP_SDNODE(VP_CTLZ)
BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_POISON, -1, vp_ctlz_zero_poison, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(CTLZ_ZERO_POISON)
END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_POISON)
-END_REGISTER_VP_INTRINSIC(vp_ctlz)
// llvm.vp.cttz(x,is_zero_poison,mask,vlen)
-BEGIN_REGISTER_VP_INTRINSIC(vp_cttz, 2, 3)
BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(cttz)
VP_PROPERTY_FUNCTIONAL_SDOPC(CTTZ)
END_REGISTER_VP_SDNODE(VP_CTTZ)
BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_POISON, -1, vp_cttz_zero_poison, 1, 2)
END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_POISON)
-END_REGISTER_VP_INTRINSIC(vp_cttz)
// llvm.vp.cttz.elts(x,is_zero_poison,mask,vl)
BEGIN_REGISTER_VP_INTRINSIC(vp_cttz_elts, 2, 3)
@@ -265,44 +264,38 @@ END_REGISTER_VP_SDNODE(VP_CTTZ_ELTS_ZERO_POISON)
END_REGISTER_VP_INTRINSIC(vp_cttz_elts)
// llvm.vp.fshl(x,y,z,mask,vlen)
-BEGIN_REGISTER_VP(vp_fshl, 3, 4, VP_FSHL, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshl)
+BEGIN_REGISTER_VP_SDNODE(VP_FSHL, -1, vp_fshl, 3, 4)
VP_PROPERTY_FUNCTIONAL_SDOPC(FSHL)
-END_REGISTER_VP(vp_fshl, VP_FSHL)
+END_REGISTER_VP_SDNODE(VP_FSHL)
// llvm.vp.fshr(x,y,z,mask,vlen)
-BEGIN_REGISTER_VP(vp_fshr, 3, 4, VP_FSHR, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshr)
+BEGIN_REGISTER_VP_SDNODE(VP_FSHR, -1, vp_fshr, 3, 4)
VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR)
-END_REGISTER_VP(vp_fshr, VP_FSHR)
+END_REGISTER_VP_SDNODE(VP_FSHR)
// llvm.vp.sadd.sat(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_sadd_sat, 2, 3, VP_SADDSAT, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_SADDSAT, -1, vp_sadd_sat, 2, 3)
VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(sadd_sat)
VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT)
-END_REGISTER_VP(vp_sadd_sat, VP_SADDSAT)
+END_REGISTER_VP_SDNODE(VP_SADDSAT)
// llvm.vp.uadd.sat(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_uadd_sat, 2, 3, VP_UADDSAT, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_UADDSAT, -1, vp_uadd_sat, 2, 3)
VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(uadd_sat)
VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT)
-END_REGISTER_VP(vp_uadd_sat, VP_UADDSAT)
+END_REGISTER_VP_SDNODE(VP_UADDSAT)
// llvm.vp.ssub.sat(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_ssub_sat, 2, 3, VP_SSUBSAT, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_SSUBSAT, -1, vp_ssub_sat, 2, 3)
VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(ssub_sat)
VP_PROPERTY_FUNCTIONAL_SDOPC(SSUBSAT)
-END_REGISTER_VP(vp_ssub_sat, VP_SSUBSAT)
+END_REGISTER_VP_SDNODE(VP_SSUBSAT)
// llvm.vp.usub.sat(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_usub_sat, 2, 3, VP_USUBSAT, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_USUBSAT, -1, vp_usub_sat, 2, 3)
VP_PROPERTY_BINARYOP
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(usub_sat)
VP_PROPERTY_FUNCTIONAL_SDOPC(USUBSAT)
-END_REGISTER_VP(vp_usub_sat, VP_USUBSAT)
+END_REGISTER_VP_SDNODE(VP_USUBSAT)
///// } Integer Arithmetic
///// Floating-Point Arithmetic {
@@ -314,12 +307,11 @@ END_REGISTER_VP(vp_usub_sat, VP_USUBSAT)
"The internal helper macro HELPER_REGISTER_BINARY_FP_VP is already defined!"
#endif
#define HELPER_REGISTER_BINARY_FP_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
- BEGIN_REGISTER_VP(vp_##OPSUFFIX, 2, 3, VPSD, -1) \
- VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
+ BEGIN_REGISTER_VP_SDNODE(VPSD, -1, vp_##OPSUFFIX, 2, 3) \
VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_##OPSUFFIX) \
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
VP_PROPERTY_BINARYOP \
- END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
+ END_REGISTER_VP_SDNODE(VPSD)
// llvm.vp.fadd(x,y,mask,vlen)
HELPER_REGISTER_BINARY_FP_VP(fadd, VP_FADD, FAdd, FADD)
@@ -339,125 +331,106 @@ HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem, FREM)
#undef HELPER_REGISTER_BINARY_FP_VP
// llvm.vp.fneg(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_fneg, 1, 2, VP_FNEG, -1)
-VP_PROPERTY_FUNCTIONAL_OPC(FNeg)
+BEGIN_REGISTER_VP_SDNODE(VP_FNEG, -1, vp_fneg, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FNEG)
-END_REGISTER_VP(vp_fneg, VP_FNEG)
+END_REGISTER_VP_SDNODE(VP_FNEG)
// llvm.vp.fabs(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_fabs, 1, 2, VP_FABS, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(fabs)
+BEGIN_REGISTER_VP_SDNODE(VP_FABS, -1, vp_fabs, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FABS)
-END_REGISTER_VP(vp_fabs, VP_FABS)
+END_REGISTER_VP_SDNODE(VP_FABS)
// llvm.vp.sqrt(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_sqrt, 1, 2, VP_SQRT, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(sqrt)
+BEGIN_REGISTER_VP_SDNODE(VP_SQRT, -1, vp_sqrt, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FSQRT)
-END_REGISTER_VP(vp_sqrt, VP_SQRT)
+END_REGISTER_VP_SDNODE(VP_SQRT)
// llvm.vp.fma(x,y,z,mask,vlen)
-BEGIN_REGISTER_VP(vp_fma, 3, 4, VP_FMA, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_FMA, -1, vp_fma, 3, 4)
VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_fma)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(fma)
VP_PROPERTY_FUNCTIONAL_SDOPC(FMA)
-END_REGISTER_VP(vp_fma, VP_FMA)
+END_REGISTER_VP_SDNODE(VP_FMA)
// llvm.vp.fmuladd(x,y,z,mask,vlen)
-BEGIN_REGISTER_VP(vp_fmuladd, 3, 4, VP_FMULADD, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_FMULADD, -1, vp_fmuladd, 3, 4)
VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_fmuladd)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(fmuladd)
VP_PROPERTY_FUNCTIONAL_SDOPC(FMAD)
-END_REGISTER_VP(vp_fmuladd, VP_FMULADD)
+END_REGISTER_VP_SDNODE(VP_FMULADD)
// llvm.vp.copysign(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_copysign, 2, 3, VP_FCOPYSIGN, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_FCOPYSIGN, -1, vp_copysign, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(FCOPYSIGN)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(copysign)
-END_REGISTER_VP(vp_copysign, VP_FCOPYSIGN)
+END_REGISTER_VP_SDNODE(VP_FCOPYSIGN)
// llvm.vp.minnum(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_minnum, 2, 3, VP_FMINNUM, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_FMINNUM, -1, vp_minnum, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(FMINNUM)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(minnum)
-END_REGISTER_VP(vp_minnum, VP_FMINNUM)
+END_REGISTER_VP_SDNODE(VP_FMINNUM)
// llvm.vp.maxnum(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_maxnum, 2, 3, VP_FMAXNUM, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_FMAXNUM, -1, vp_maxnum, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXNUM)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(maxnum)
-END_REGISTER_VP(vp_maxnum, VP_FMAXNUM)
+END_REGISTER_VP_SDNODE(VP_FMAXNUM)
// llvm.vp.minimum(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_minimum, 2, 3, VP_FMINIMUM, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_FMINIMUM, -1, vp_minimum, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(FMINIMUM)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(minimum)
-END_REGISTER_VP(vp_minimum, VP_FMINIMUM)
+END_REGISTER_VP_SDNODE(VP_FMINIMUM)
// llvm.vp.maximum(x,y,mask,vlen)
-BEGIN_REGISTER_VP(vp_maximum, 2, 3, VP_FMAXIMUM, -1)
+BEGIN_REGISTER_VP_SDNODE(VP_FMAXIMUM, -1, vp_maximum, 2, 3)
VP_PROPERTY_BINARYOP
VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXIMUM)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(maximum)
-END_REGISTER_VP(vp_maximum, VP_FMAXIMUM)
+END_REGISTER_VP_SDNODE(VP_FMAXIMUM)
// llvm.vp.ceil(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_ceil, 1, 2, VP_FCEIL, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(ceil)
+BEGIN_REGISTER_VP_SDNODE(VP_FCEIL, -1, vp_ceil, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FCEIL)
-END_REGISTER_VP(vp_ceil, VP_FCEIL)
+END_REGISTER_VP_SDNODE(VP_FCEIL)
// llvm.vp.floor(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_floor, 1, 2, VP_FFLOOR, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(floor)
+BEGIN_REGISTER_VP_SDNODE(VP_FFLOOR, -1, vp_floor, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FFLOOR)
-END_REGISTER_VP(vp_floor, VP_FFLOOR)
+END_REGISTER_VP_SDNODE(VP_FFLOOR)
// llvm.vp.round(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_round, 1, 2, VP_FROUND, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(round)
+BEGIN_REGISTER_VP_SDNODE(VP_FROUND, -1, vp_round, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FROUND)
-END_REGISTER_VP(vp_round, VP_FROUND)
+END_REGISTER_VP_SDNODE(VP_FROUND)
// llvm.vp.roundeven(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_roundeven, 1, 2, VP_FROUNDEVEN, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(roundeven)
+BEGIN_REGISTER_VP_SDNODE(VP_FROUNDEVEN, -1, vp_roundeven, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FROUNDEVEN)
-END_REGISTER_VP(vp_roundeven, VP_FROUNDEVEN)
+END_REGISTER_VP_SDNODE(VP_FROUNDEVEN)
// llvm.vp.roundtozero(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_roundtozero, 1, 2, VP_FROUNDTOZERO, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(trunc)
+BEGIN_REGISTER_VP_SDNODE(VP_FROUNDTOZERO, -1, vp_roundtozero, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FTRUNC)
-END_REGISTER_VP(vp_roundtozero, VP_FROUNDTOZERO)
+END_REGISTER_VP_SDNODE(VP_FROUNDTOZERO)
// llvm.vp.rint(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_rint, 1, 2, VP_FRINT, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(rint)
+BEGIN_REGISTER_VP_SDNODE(VP_FRINT, -1, vp_rint, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FRINT)
-END_REGISTER_VP(vp_rint, VP_FRINT)
+END_REGISTER_VP_SDNODE(VP_FRINT)
// llvm.vp.nearbyint(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_nearbyint, 1, 2, VP_FNEARBYINT, -1)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(nearbyint)
+BEGIN_REGISTER_VP_SDNODE(VP_FNEARBYINT, -1, vp_nearbyint, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(FNEARBYINT)
-END_REGISTER_VP(vp_nearbyint, VP_FNEARBYINT)
+END_REGISTER_VP_SDNODE(VP_FNEARBYINT)
// llvm.vp.lrint(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_lrint, 1, 2, VP_LRINT, 0)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(lrint)
+BEGIN_REGISTER_VP_SDNODE(VP_LRINT, 0, vp_lrint, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(LRINT)
-END_REGISTER_VP(vp_lrint, VP_LRINT)
+END_REGISTER_VP_SDNODE(VP_LRINT)
// llvm.vp.llrint(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_llrint, 1, 2, VP_LLRINT, 0)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(llrint)
+BEGIN_REGISTER_VP_SDNODE(VP_LLRINT, 0, vp_llrint, 1, 2)
VP_PROPERTY_FUNCTIONAL_SDOPC(LLRINT)
-END_REGISTER_VP(vp_llrint, VP_LLRINT)
+END_REGISTER_VP_SDNODE(VP_LLRINT)
///// } Floating-Point Arithmetic
@@ -469,11 +442,10 @@ END_REGISTER_VP(vp_llrint, VP_LLRINT)
"The internal helper macro HELPER_REGISTER_FP_CAST_VP is already defined!"
#endif
#define HELPER_REGISTER_FP_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
- BEGIN_REGISTER_VP(vp_##OPSUFFIX, 1, 2, VPSD, -1) \
- VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
+ BEGIN_REGISTER_VP_SDNODE(VPSD, -1, vp_##OPSUFFIX, 1, 2) \
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_##OPSUFFIX) \
- END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
+ END_REGISTER_VP_SDNODE(VPSD)
// llvm.vp.fptoui(x,mask,vlen)
HELPER_REGISTER_FP_CAST_VP(fptoui, VP_FP_TO_UINT, FPToUI, FP_TO_UINT)
@@ -502,10 +474,9 @@ HELPER_REGISTER_FP_CAST_VP(fpext, VP_FP_EXTEND, FPExt, FP_EXTEND)
"The internal helper macro HELPER_REGISTER_INT_CAST_VP is already defined!"
#endif
#define HELPER_REGISTER_INT_CAST_VP(OPSUFFIX, VPSD, IROPC, SDOPC) \
- BEGIN_REGISTER_VP(vp_##OPSUFFIX, 1, 2, VPSD, -1) \
- VP_PROPERTY_FUNCTIONAL_OPC(IROPC) \
+ BEGIN_REGISTER_VP_SDNODE(VPSD, -1, vp_##OPSUFFIX, 1, 2) \
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
- END_REGISTER_VP(vp_##OPSUFFIX, VPSD)
+ END_REGISTER_VP_SDNODE(VPSD)
// llvm.vp.trunc(x,mask,vlen)
HELPER_REGISTER_INT_CAST_VP(trunc, VP_TRUNCATE, Trunc, TRUNCATE)
@@ -517,14 +488,12 @@ HELPER_REGISTER_INT_CAST_VP(zext, VP_ZERO_EXTEND, ZExt, ZERO_EXTEND)
HELPER_REGISTER_INT_CAST_VP(sext, VP_SIGN_EXTEND, SExt, SIGN_EXTEND)
// llvm.vp.ptrtoint(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_ptrtoint, 1, 2, VP_PTRTOINT, -1)
-VP_PROPERTY_FUNCTIONAL_OPC(PtrToInt)
-END_REGISTER_VP(vp_ptrtoint, VP_PTRTOINT)
+BEGIN_REGISTER_VP_SDNODE(VP_PTRTOINT, -1, vp_ptrtoint, 1, 2)
+END_REGISTER_VP_SDNODE(VP_PTRTOINT)
// llvm.vp.inttoptr(x,mask,vlen)
-BEGIN_REGISTER_VP(vp_inttoptr, 1, 2, VP_INTTOPTR, -1)
-VP_PROPERTY_FUNCTIONAL_OPC(IntToPtr)
-END_REGISTER_VP(vp_inttoptr, VP_INTTOPTR)
+BEGIN_REGISTER_VP_SDNODE(VP_INTTOPTR, -1, vp_inttoptr, 1, 2)
+END_REGISTER_VP_SDNODE(VP_INTTOPTR)
#undef HELPER_REGISTER_INT_CAST_VP
@@ -536,25 +505,11 @@ END_REGISTER_VP(vp_inttoptr, VP_INTTOPTR)
BEGIN_REGISTER_VP_SDNODE(VP_SETCC, 0, vp_setcc, 3, 4)
END_REGISTER_VP_SDNODE(VP_SETCC)
-// llvm.vp.fcmp(x,y,cc,mask,vlen)
-BEGIN_REGISTER_VP_INTRINSIC(vp_fcmp, 3, 4)
-HELPER_MAP_VPID_TO_VPSD(vp_fcmp, VP_SETCC)
-VP_PROPERTY_FUNCTIONAL_OPC(FCmp)
-VP_PROPERTY_CONSTRAINEDFP(experimental_constrained_fcmp)
-END_REGISTER_VP_INTRINSIC(vp_fcmp)
-
-// llvm.vp.icmp(x,y,cc,mask,vlen)
-BEGIN_REGISTER_VP_INTRINSIC(vp_icmp, 3, 4)
-HELPER_MAP_VPID_TO_VPSD(vp_icmp, VP_SETCC)
-VP_PROPERTY_FUNCTIONAL_OPC(ICmp)
-END_REGISTER_VP_INTRINSIC(vp_icmp)
-
///// } Comparisons
// llvm.vp.is.fpclass(on_true,on_false,mask,vlen)
-BEGIN_REGISTER_VP(vp_is_fpclass, 2, 3, VP_IS_FPCLASS, 0)
-VP_PROPERTY_FUNCTIONAL_INTRINSIC(is_fpclass)
-END_REGISTER_VP(vp_is_fpclass, VP_IS_FPCLASS)
+BEGIN_REGISTER_VP_SDNODE(VP_IS_FPCLASS, 0, vp_is_fpclass, 2, 3)
+END_REGISTER_VP_SDNODE(VP_IS_FPCLASS)
///// Memory Operations {
// llvm.vp.store(val,ptr,mask,vlen)
@@ -726,10 +681,9 @@ HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fmul, VP_REDUCE_FMUL,
// false.
//
// llvm.vp.select(cond,on_true,on_false,vlen)
-BEGIN_REGISTER_VP(vp_select, std::nullopt, 3, VP_SELECT, -1)
-VP_PROPERTY_FUNCTIONAL_OPC(Select)
+BEGIN_REGISTER_VP_SDNODE(VP_SELECT, -1, vp_select, std::nullopt, 3)
VP_PROPERTY_FUNCTIONAL_SDOPC(VSELECT)
-END_REGISTER_VP(vp_select, VP_SELECT)
+END_REGISTER_VP_SDNODE(VP_SELECT)
// llvm.vp.merge(cond,on_true,on_false,pivot)
BEGIN_REGISTER_VP(vp_merge, std::nullopt, 3, VP_MERGE, -1)
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 3fd1cb8a0a4d4..92874656fe899 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -6411,8 +6411,7 @@ bool llvm::canIgnoreSignBitOfZero(const Use &U) {
return true;
case Intrinsic::copysign:
return U.getOperandNo() == 0;
- case Intrinsic::is_fpclass:
- case Intrinsic::vp_is_fpclass: {
+ case Intrinsic::is_fpclass: {
auto Test =
static_cast<FPClassTest>(
cast<ConstantInt>(II->getArgOperand(1))->getZExtValue()) &
@@ -6482,7 +6481,6 @@ bool llvm::canIgnoreSignBitOfNaN(const Use &U) {
case Intrinsic::fptoui_sat:
case Intrinsic::fptosi_sat:
case Intrinsic::is_fpclass:
- case Intrinsic::vp_is_fpclass:
return true;
default:
return false;
diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp
index a33f17bf00755..251bf0d5f04be 100644
--- a/llvm/lib/Analysis/VectorUtils.cpp
+++ b/llvm/lib/Analysis/VectorUtils.cpp
@@ -150,13 +150,9 @@ bool llvm::isVectorIntrinsicWithScalarOpAtArg(Intrinsic::ID ID,
switch (ID) {
case Intrinsic::abs:
- case Intrinsic::vp_abs:
case Intrinsic::ctlz:
- case Intrinsic::vp_ctlz:
case Intrinsic::cttz:
- case Intrinsic::vp_cttz:
case Intrinsic::is_fpclass:
- case Intrinsic::vp_is_fpclass:
case Intrinsic::powi:
case Intrinsic::vector_extract:
return (ScalarOpdIdx == 1);
@@ -187,9 +183,6 @@ bool llvm::isVectorIntrinsicWithOverloadTypeAtArg(
if (TTI && Intrinsic::isTargetIntrinsic(ID))
return TTI->isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx);
- if (VPCastIntrinsic::isVPCast(ID))
- return OpdIdx == -1 || OpdIdx == 0;
-
switch (ID) {
case Intrinsic::fptosi_sat:
case Intrinsic::fptoui_sat:
@@ -197,8 +190,6 @@ bool llvm::isVectorIntrinsicWithOverloadTypeAtArg(
case Intrinsic::llround:
case Intrinsic::lrint:
case Intrinsic::llrint:
- case Intrinsic::vp_lrint:
- case Intrinsic::vp_llrint:
case Intrinsic::ucmp:
case Intrinsic::scmp:
case Intrinsic::vector_extract:
@@ -208,7 +199,6 @@ bool llvm::isVectorIntrinsicWithOverloadTypeAtArg(
case Intrinsic::sincos:
case Intrinsic::sincospi:
case Intrinsic::is_fpclass:
- case Intrinsic::vp_is_fpclass:
return OpdIdx == 0;
case Intrinsic::powi:
case Intrinsic::ldexp:
diff --git a/llvm/lib/CodeGen/ExpandVectorPredication.cpp b/llvm/lib/CodeGen/ExpandVectorPredication.cpp
index 57c033b37b024..c65004927cf91 100644
--- a/llvm/lib/CodeGen/ExpandVectorPredication.cpp
+++ b/llvm/lib/CodeGen/ExpandVectorPredication.cpp
@@ -165,27 +165,14 @@ struct CachingVPExpander {
/// Lower this VP binary operator to a unpredicated binary operator.
bool expandPredicationInBinaryOperator(IRBuilder<> &Builder, VPIntrinsic &PI);
- /// Lower this VP int call to a unpredicated int call.
- bool expandPredicationToIntCall(IRBuilder<> &Builder, VPIntrinsic &PI);
-
- /// Lower this VP fp call to a unpredicated fp call.
- bool expandPredicationToFPCall(IRBuilder<> &Builder, VPIntrinsic &PI,
- unsigned UnpredicatedIntrinsicID);
-
/// Lower this VP reduction to a call to an unpredicated reduction intrinsic.
bool expandPredicationInReduction(IRBuilder<> &Builder,
VPReductionIntrinsic &PI);
- /// Lower this VP cast operation to a non-VP intrinsic.
- bool expandPredicationToCastIntrinsic(IRBuilder<> &Builder, VPIntrinsic &VPI);
-
/// Lower this VP memory operation to a non-VP intrinsic.
bool expandPredicationInMemoryIntrinsic(IRBuilder<> &Builder,
VPIntrinsic &VPI);
- /// Lower this VP comparison to a call to an unpredicated comparison.
- bool expandPredicationInComparison(IRBuilder<> &Builder, VPCmpIntrinsic &PI);
-
/// Query TTI and expand the vector predication in \p P accordingly.
bool expandPredication(VPIntrinsic &PI);
@@ -263,75 +250,6 @@ bool CachingVPExpander::expandPredicationInBinaryOperator(IRBuilder<> &Builder,
return true;
}
-bool CachingVPExpander::expandPredicationToIntCall(IRBuilder<> &Builder,
- VPIntrinsic &VPI) {
- std::optional<unsigned> FID = VPI.getFunctionalIntrinsicID();
- if (!FID)
- return false;
- SmallVector<Value *, 2> Argument;
- for (unsigned i = 0; i < VPI.getNumOperands() - 3; i++) {
- Argument.push_back(VPI.getOperand(i));
- }
- Value *NewOp =
- Builder.CreateIntrinsic(FID.value(), {VPI.getType()}, Argument);
- replaceOperation(*NewOp, VPI);
- return true;
-}
-
-bool CachingVPExpander::expandPredicationToFPCall(
- IRBuilder<> &Builder, VPIntrinsic &VPI, unsigned UnpredicatedIntrinsicID) {
- assert((maySpeculateLanes(VPI) || VPI.canIgnoreVectorLengthParam()) &&
- "Implicitly dropping %evl in non-speculatable operator!");
-
- switch (UnpredicatedIntrinsicID) {
- case Intrinsic::fabs:
- case Intrinsic::copysign:
- case Intrinsic::sqrt:
- case Intrinsic::maxnum:
- case Intrinsic::minnum:
- case Intrinsic::maximum:
- case Intrinsic::minimum:
- case Intrinsic::ceil:
- case Intrinsic::floor:
- case Intrinsic::round:
- case Intrinsic::roundeven:
- case Intrinsic::trunc:
- case Intrinsic::rint:
- case Intrinsic::nearbyint:
- case Intrinsic::lrint:
- case Intrinsic::llrint:
- case Intrinsic::is_fpclass: {
- SmallVector<Value *, 2> Argument;
- for (unsigned i = 0; i < VPI.getNumOperands() - 3; i++) {
- Argument.push_back(VPI.getOperand(i));
- }
- Value *NewOp = Builder.CreateIntrinsic(VPI.getType(),
- UnpredicatedIntrinsicID, Argument);
- replaceOperation(*NewOp, VPI);
- return true;
- }
- case Intrinsic::fma:
- case Intrinsic::fmuladd:
- case Intrinsic::experimental_constrained_fma:
- case Intrinsic::experimental_constrained_fmuladd: {
- Value *Op0 = VPI.getOperand(0);
- Value *Op1 = VPI.getOperand(1);
- Value *Op2 = VPI.getOperand(2);
- Function *Fn = Intrinsic::getOrInsertDeclaration(
- VPI.getModule(), UnpredicatedIntrinsicID, {VPI.getType()});
- Value *NewOp;
- if (Intrinsic::isConstrainedFPIntrinsic(UnpredicatedIntrinsicID))
- NewOp = Builder.CreateConstrainedFPCall(Fn, {Op0, Op1, Op2});
- else
- NewOp = Builder.CreateCall(Fn, {Op0, Op1, Op2});
- replaceOperation(*NewOp, VPI);
- return true;
- }
- }
-
- return false;
-}
-
static Value *getNeutralReductionElement(const VPReductionIntrinsic &VPI,
Type *EltTy) {
Intrinsic::ID RdxID = *VPI.getFunctionalIntrinsicID();
@@ -400,18 +318,6 @@ bool CachingVPExpander::expandPredicationInReduction(
return true;
}
-bool CachingVPExpander::expandPredicationToCastIntrinsic(IRBuilder<> &Builder,
- VPIntrinsic &VPI) {
- Intrinsic::ID VPID = VPI.getIntrinsicID();
- unsigned CastOpcode = VPIntrinsic::getFunctionalOpcodeForVP(VPID).value();
- assert(Instruction::isCast(CastOpcode));
- Value *CastOp = Builder.CreateCast(Instruction::CastOps(CastOpcode),
- VPI.getOperand(0), VPI.getType());
-
- replaceOperation(*CastOp, VPI);
- return true;
-}
-
bool CachingVPExpander::expandPredicationInMemoryIntrinsic(IRBuilder<> &Builder,
VPIntrinsic &VPI) {
assert(VPI.canIgnoreVectorLengthParam());
@@ -476,24 +382,6 @@ bool CachingVPExpander::expandPredicationInMemoryIntrinsic(IRBuilder<> &Builder,
return true;
}
-bool CachingVPExpander::expandPredicationInComparison(IRBuilder<> &Builder,
- VPCmpIntrinsic &VPI) {
- assert((maySpeculateLanes(VPI) || VPI.canIgnoreVectorLengthParam()) &&
- "Implicitly dropping %evl in non-speculatable operator!");
-
- assert(*VPI.getFunctionalOpcode() == Instruction::ICmp ||
- *VPI.getFunctionalOpcode() == Instruction::FCmp);
-
- Value *Op0 = VPI.getOperand(0);
- Value *Op1 = VPI.getOperand(1);
- auto Pred = VPI.getPredicate();
-
- auto *NewCmp = Builder.CreateCmp(Pred, Op0, Op1);
-
- replaceOperation(*NewCmp, VPI);
- return true;
-}
-
bool CachingVPExpander::discardEVLParameter(VPIntrinsic &VPI) {
LLVM_DEBUG(dbgs() << "Discard EVL parameter in " << VPI << "\n");
@@ -532,8 +420,7 @@ bool CachingVPExpander::foldEVLIntoMask(VPIntrinsic &VPI) {
// Only VP intrinsics can have an %evl parameter.
Value *OldMaskParam = VPI.getMaskParam();
if (!OldMaskParam) {
- assert((VPI.getIntrinsicID() == Intrinsic::vp_merge ||
- VPI.getIntrinsicID() == Intrinsic::vp_select) &&
+ assert((VPI.getIntrinsicID() == Intrinsic::vp_merge) &&
"Unexpected VP intrinsic without mask operand");
OldMaskParam = VPI.getArgOperand(0);
}
@@ -549,8 +436,7 @@ bool CachingVPExpander::foldEVLIntoMask(VPIntrinsic &VPI) {
ElementCount ElemCount = VPI.getStaticVectorLength();
Value *VLMask = convertEVLToMask(Builder, OldEVLParam, ElemCount);
Value *NewMaskParam = Builder.CreateAnd(VLMask, OldMaskParam);
- if (VPI.getIntrinsicID() == Intrinsic::vp_merge ||
- VPI.getIntrinsicID() == Intrinsic::vp_select)
+ if (VPI.getIntrinsicID() == Intrinsic::vp_merge)
VPI.setArgOperand(0, NewMaskParam);
else
VPI.setMaskParam(NewMaskParam);
@@ -578,21 +464,9 @@ bool CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
if (auto *VPRI = dyn_cast<VPReductionIntrinsic>(&VPI))
return expandPredicationInReduction(Builder, *VPRI);
- if (auto *VPCmp = dyn_cast<VPCmpIntrinsic>(&VPI))
- return expandPredicationInComparison(Builder, *VPCmp);
-
- if (VPCastIntrinsic::isVPCast(VPI.getIntrinsicID()))
- return expandPredicationToCastIntrinsic(Builder, VPI);
-
switch (VPI.getIntrinsicID()) {
default:
break;
- case Intrinsic::vp_fneg: {
- Value *NewNegOp = Builder.CreateFNeg(VPI.getOperand(0));
- replaceOperation(*NewNegOp, VPI);
- return NewNegOp;
- }
- case Intrinsic::vp_select:
case Intrinsic::vp_merge: {
assert(maySpeculateLanes(VPI) || VPI.canIgnoreVectorLengthParam());
Value *NewSelectOp = Builder.CreateSelect(
@@ -600,44 +474,6 @@ bool CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
replaceOperation(*NewSelectOp, VPI);
return NewSelectOp;
}
- case Intrinsic::vp_abs:
- case Intrinsic::vp_smax:
- case Intrinsic::vp_smin:
- case Intrinsic::vp_umax:
- case Intrinsic::vp_umin:
- case Intrinsic::vp_bswap:
- case Intrinsic::vp_bitreverse:
- case Intrinsic::vp_ctpop:
- case Intrinsic::vp_ctlz:
- case Intrinsic::vp_cttz:
- case Intrinsic::vp_sadd_sat:
- case Intrinsic::vp_uadd_sat:
- case Intrinsic::vp_ssub_sat:
- case Intrinsic::vp_usub_sat:
- case Intrinsic::vp_fshl:
- case Intrinsic::vp_fshr:
- return expandPredicationToIntCall(Builder, VPI);
- case Intrinsic::vp_fabs:
- case Intrinsic::vp_copysign:
- case Intrinsic::vp_sqrt:
- case Intrinsic::vp_maxnum:
- case Intrinsic::vp_minnum:
- case Intrinsic::vp_maximum:
- case Intrinsic::vp_minimum:
- case Intrinsic::vp_ceil:
- case Intrinsic::vp_floor:
- case Intrinsic::vp_round:
- case Intrinsic::vp_roundeven:
- case Intrinsic::vp_roundtozero:
- case Intrinsic::vp_rint:
- case Intrinsic::vp_nearbyint:
- case Intrinsic::vp_lrint:
- case Intrinsic::vp_llrint:
- case Intrinsic::vp_fma:
- case Intrinsic::vp_fmuladd:
- case Intrinsic::vp_is_fpclass:
- return expandPredicationToFPCall(Builder, VPI,
- VPI.getFunctionalIntrinsicID().value());
case Intrinsic::vp_load:
case Intrinsic::vp_store:
case Intrinsic::vp_gather:
@@ -645,10 +481,6 @@ bool CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
return expandPredicationInMemoryIntrinsic(Builder, VPI);
}
- if (auto CID = VPI.getConstrainedIntrinsicID())
- if (expandPredicationToFPCall(Builder, VPI, *CID))
- return true;
-
return false;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index b2605ef54a9ea..81062dd6d3a11 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -8757,16 +8757,6 @@ void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) {
std::optional<unsigned> ResOPC;
switch (VPIntrin.getIntrinsicID()) {
- case Intrinsic::vp_ctlz: {
- bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
- ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_POISON : ISD::VP_CTLZ;
- break;
- }
- case Intrinsic::vp_cttz: {
- bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
- ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_POISON : ISD::VP_CTTZ;
- break;
- }
case Intrinsic::vp_cttz_elts: {
bool IsZeroPoison = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
ResOPC = IsZeroPoison ? ISD::VP_CTTZ_ELTS_ZERO_POISON : ISD::VP_CTTZ_ELTS;
@@ -9017,38 +9007,6 @@ void SelectionDAGBuilder::visitVPStridedStore(
setValue(&VPIntrin, ST);
}
-void SelectionDAGBuilder::visitVPCmp(const VPCmpIntrinsic &VPIntrin) {
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- SDLoc DL = getCurSDLoc();
-
- ISD::CondCode Condition;
- CmpInst::Predicate CondCode = VPIntrin.getPredicate();
-
- Value *Op1 = VPIntrin.getOperand(0);
- Value *Op2 = VPIntrin.getOperand(1);
- // #2 is the condition code
- SDValue MaskOp = getValue(VPIntrin.getOperand(3));
- SDValue EVL = getValue(VPIntrin.getOperand(4));
- MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy();
- assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) &&
- "Unexpected target EVL type");
- EVL = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, EVL);
-
- if (VPIntrin.getOperand(0)->getType()->isFPOrFPVectorTy()) {
- Condition = getFCmpCondCode(CondCode);
- SimplifyQuery SQ(DAG.getDataLayout(), &VPIntrin);
- if (isKnownNeverNaN(Op2, SQ) && isKnownNeverNaN(Op1, SQ))
- Condition = getFCmpCodeWithoutNaN(Condition);
- } else {
- Condition = getICmpCondCode(CondCode);
- }
-
- EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
- VPIntrin.getType());
- setValue(&VPIntrin, DAG.getSetCCVP(DL, DestVT, getValue(Op1), getValue(Op2),
- Condition, MaskOp, EVL));
-}
-
void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
const VPIntrinsic &VPIntrin) {
SDLoc DL = getCurSDLoc();
@@ -9056,9 +9014,6 @@ void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
auto IID = VPIntrin.getIntrinsicID();
- if (const auto *CmpI = dyn_cast<VPCmpIntrinsic>(&VPIntrin))
- return visitVPCmp(*CmpI);
-
SmallVector<EVT, 4> ValueVTs;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
ComputeValueVTs(TLI, DAG.getDataLayout(), VPIntrin.getType(), ValueVTs);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index 6c7711af078f0..e4e958cba5ac2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -672,7 +672,6 @@ class SelectionDAGBuilder {
const SmallVectorImpl<SDValue> &OpValues);
void visitVPStridedStore(const VPIntrinsic &VPIntrin,
const SmallVectorImpl<SDValue> &OpValues);
- void visitVPCmp(const VPCmpIntrinsic &VPIntrin);
void visitVectorPredicationIntrinsic(const VPIntrinsic &VPIntrin);
void visitVAStart(const CallInst &I);
diff --git a/llvm/lib/IR/IntrinsicInst.cpp b/llvm/lib/IR/IntrinsicInst.cpp
index 68ddf610dc3d0..684aaf1a8f2d3 100644
--- a/llvm/lib/IR/IntrinsicInst.cpp
+++ b/llvm/lib/IR/IntrinsicInst.cpp
@@ -363,8 +363,7 @@ ElementCount VPIntrinsic::getStaticVectorLength() const {
Value *VPMask = getMaskParam();
if (!VPMask) {
- assert((getIntrinsicID() == Intrinsic::vp_merge ||
- getIntrinsicID() == Intrinsic::vp_select) &&
+ assert((getIntrinsicID() == Intrinsic::vp_merge) &&
"Unexpected VP intrinsic without mask operand");
return GetVectorLengthOfType(getType());
}
@@ -545,20 +544,6 @@ constexpr static bool doesVPHaveNoFunctionalEquivalent(Intrinsic::ID ID) {
getFunctionalIntrinsicIDForVP(Intrinsic::VPID));
#include "llvm/IR/VPIntrinsics.def"
-// Equivalent non-predicated constrained intrinsic
-std::optional<Intrinsic::ID>
-VPIntrinsic::getConstrainedIntrinsicIDForVP(Intrinsic::ID ID) {
- switch (ID) {
- default:
- break;
-#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
-#define VP_PROPERTY_CONSTRAINEDFP(CID) return Intrinsic::CID;
-#define END_REGISTER_VP_INTRINSIC(VPID) break;
-#include "llvm/IR/VPIntrinsics.def"
- }
- return std::nullopt;
-}
-
bool VPIntrinsic::canIgnoreVectorLengthParam() const {
using namespace PatternMatch;
@@ -609,28 +594,11 @@ Function *VPIntrinsic::getOrInsertDeclarationForParams(
VPFunc = Intrinsic::getOrInsertDeclaration(M, VPID, OverloadTy);
break;
}
- case Intrinsic::vp_trunc:
- case Intrinsic::vp_sext:
- case Intrinsic::vp_zext:
- case Intrinsic::vp_fptoui:
- case Intrinsic::vp_fptosi:
- case Intrinsic::vp_uitofp:
- case Intrinsic::vp_sitofp:
- case Intrinsic::vp_fptrunc:
- case Intrinsic::vp_fpext:
- case Intrinsic::vp_ptrtoint:
- case Intrinsic::vp_inttoptr:
- case Intrinsic::vp_lrint:
- case Intrinsic::vp_llrint:
case Intrinsic::vp_cttz_elts:
VPFunc = Intrinsic::getOrInsertDeclaration(
M, VPID, {ReturnType, Params[0]->getType()});
break;
- case Intrinsic::vp_is_fpclass:
- VPFunc = Intrinsic::getOrInsertDeclaration(M, VPID, {Params[0]->getType()});
- break;
case Intrinsic::vp_merge:
- case Intrinsic::vp_select:
VPFunc = Intrinsic::getOrInsertDeclaration(M, VPID, {Params[1]->getType()});
break;
case Intrinsic::vp_load:
@@ -690,60 +658,6 @@ bool VPReductionIntrinsic::isVPReduction(Intrinsic::ID ID) {
}
}
-bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) {
- // All of the vp.casts correspond to instructions
- if (std::optional<unsigned> Opc = getFunctionalOpcodeForVP(ID))
- return Instruction::isCast(*Opc);
- return false;
-}
-
-bool VPCmpIntrinsic::isVPCmp(Intrinsic::ID ID) {
- switch (ID) {
- default:
- return false;
- case Intrinsic::vp_fcmp:
- case Intrinsic::vp_icmp:
- return true;
- }
-}
-
-bool VPBinOpIntrinsic::isVPBinOp(Intrinsic::ID ID) {
- switch (ID) {
- default:
- break;
-#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
-#define VP_PROPERTY_BINARYOP return true;
-#define END_REGISTER_VP_INTRINSIC(VPID) break;
-#include "llvm/IR/VPIntrinsics.def"
- }
- return false;
-}
-
-static ICmpInst::Predicate getIntPredicateFromMD(const Value *Op) {
- Metadata *MD = cast<MetadataAsValue>(Op)->getMetadata();
- if (!MD || !isa<MDString>(MD))
- return ICmpInst::BAD_ICMP_PREDICATE;
- return StringSwitch<ICmpInst::Predicate>(cast<MDString>(MD)->getString())
- .Case("eq", ICmpInst::ICMP_EQ)
- .Case("ne", ICmpInst::ICMP_NE)
- .Case("ugt", ICmpInst::ICMP_UGT)
- .Case("uge", ICmpInst::ICMP_UGE)
- .Case("ult", ICmpInst::ICMP_ULT)
- .Case("ule", ICmpInst::ICMP_ULE)
- .Case("sgt", ICmpInst::ICMP_SGT)
- .Case("sge", ICmpInst::ICMP_SGE)
- .Case("slt", ICmpInst::ICMP_SLT)
- .Case("sle", ICmpInst::ICMP_SLE)
- .Default(ICmpInst::BAD_ICMP_PREDICATE);
-}
-
-CmpInst::Predicate VPCmpIntrinsic::getPredicate() const {
- assert(isVPCmp(getIntrinsicID()));
- return getIntrinsicID() == Intrinsic::vp_fcmp
- ? getFPPredicateFromMD(getArgOperand(2))
- : getIntPredicateFromMD(getArgOperand(2));
-}
-
unsigned VPReductionIntrinsic::getVectorParamPos() const {
return *VPReductionIntrinsic::getVectorParamPos(getIntrinsicID());
}
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 18425ca1cb1c4..afaec253f7517 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -7290,64 +7290,7 @@ void Verifier::visit(DbgVariableRecord &DVR) {
}
void Verifier::visitVPIntrinsic(VPIntrinsic &VPI) {
- if (auto *VPCast = dyn_cast<VPCastIntrinsic>(&VPI)) {
- auto *RetTy = cast<VectorType>(VPCast->getType());
- auto *ValTy = cast<VectorType>(VPCast->getOperand(0)->getType());
- Check(RetTy->getElementCount() == ValTy->getElementCount(),
- "VP cast intrinsic first argument and result vector lengths must be "
- "equal",
- *VPCast);
-
- switch (VPCast->getIntrinsicID()) {
- case Intrinsic::vp_trunc:
- Check(RetTy->getScalarSizeInBits() < ValTy->getScalarSizeInBits(),
- "llvm.vp.trunc intrinsic the bit size of first argument must be "
- "larger than the bit size of the return type",
- *VPCast);
- break;
- case Intrinsic::vp_zext:
- case Intrinsic::vp_sext:
- Check(RetTy->getScalarSizeInBits() > ValTy->getScalarSizeInBits(),
- "llvm.vp.zext or llvm.vp.sext intrinsic the bit size of first "
- "argument must be smaller than the bit size of the return type",
- *VPCast);
- break;
- case Intrinsic::vp_fptrunc:
- Check(RetTy->getScalarSizeInBits() < ValTy->getScalarSizeInBits(),
- "llvm.vp.fptrunc intrinsic the bit size of first argument must be "
- "larger than the bit size of the return type",
- *VPCast);
- break;
- case Intrinsic::vp_fpext:
- Check(RetTy->getScalarSizeInBits() > ValTy->getScalarSizeInBits(),
- "llvm.vp.fpext intrinsic the bit size of first argument must be "
- "smaller than the bit size of the return type",
- *VPCast);
- break;
- default:
- break;
- }
- }
-
switch (VPI.getIntrinsicID()) {
- case Intrinsic::vp_fcmp: {
- auto Pred = cast<VPCmpIntrinsic>(&VPI)->getPredicate();
- Check(CmpInst::isFPPredicate(Pred),
- "invalid predicate for VP FP comparison intrinsic", &VPI);
- break;
- }
- case Intrinsic::vp_icmp: {
- auto Pred = cast<VPCmpIntrinsic>(&VPI)->getPredicate();
- Check(CmpInst::isIntPredicate(Pred),
- "invalid predicate for VP integer comparison intrinsic", &VPI);
- break;
- }
- case Intrinsic::vp_is_fpclass: {
- auto TestMask = cast<ConstantInt>(VPI.getOperand(1));
- Check((TestMask->getZExtValue() & ~static_cast<unsigned>(fcAllFlags)) == 0,
- "unsupported bits for llvm.vp.is.fpclass test mask");
- break;
- }
case Intrinsic::experimental_vp_splice: {
VectorType *VecTy = cast<VectorType>(VPI.getType());
int64_t Idx = cast<ConstantInt>(VPI.getArgOperand(2))->getSExtValue();
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 970b1605cc610..b9d63e9365c75 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1363,25 +1363,10 @@ static const CostTblEntry VectorIntrinsicCostTable[]{
{Intrinsic::bswap, MVT::i16, 3},
{Intrinsic::bswap, MVT::i32, 12},
{Intrinsic::bswap, MVT::i64, 31},
- {Intrinsic::vp_bswap, MVT::i16, 3},
- {Intrinsic::vp_bswap, MVT::i32, 12},
- {Intrinsic::vp_bswap, MVT::i64, 31},
- {Intrinsic::vp_fshl, MVT::i8, 7},
- {Intrinsic::vp_fshl, MVT::i16, 7},
- {Intrinsic::vp_fshl, MVT::i32, 7},
- {Intrinsic::vp_fshl, MVT::i64, 7},
- {Intrinsic::vp_fshr, MVT::i8, 7},
- {Intrinsic::vp_fshr, MVT::i16, 7},
- {Intrinsic::vp_fshr, MVT::i32, 7},
- {Intrinsic::vp_fshr, MVT::i64, 7},
{Intrinsic::bitreverse, MVT::i8, 17},
{Intrinsic::bitreverse, MVT::i16, 24},
{Intrinsic::bitreverse, MVT::i32, 33},
{Intrinsic::bitreverse, MVT::i64, 52},
- {Intrinsic::vp_bitreverse, MVT::i8, 17},
- {Intrinsic::vp_bitreverse, MVT::i16, 24},
- {Intrinsic::vp_bitreverse, MVT::i32, 33},
- {Intrinsic::vp_bitreverse, MVT::i64, 52},
{Intrinsic::ctpop, MVT::i8, 12},
{Intrinsic::ctpop, MVT::i16, 19},
{Intrinsic::ctpop, MVT::i32, 20},
@@ -1394,18 +1379,6 @@ static const CostTblEntry VectorIntrinsicCostTable[]{
{Intrinsic::cttz, MVT::i16, 23},
{Intrinsic::cttz, MVT::i32, 24},
{Intrinsic::cttz, MVT::i64, 25},
- {Intrinsic::vp_ctpop, MVT::i8, 12},
- {Intrinsic::vp_ctpop, MVT::i16, 19},
- {Intrinsic::vp_ctpop, MVT::i32, 20},
- {Intrinsic::vp_ctpop, MVT::i64, 21},
- {Intrinsic::vp_ctlz, MVT::i8, 19},
- {Intrinsic::vp_ctlz, MVT::i16, 28},
- {Intrinsic::vp_ctlz, MVT::i32, 31},
- {Intrinsic::vp_ctlz, MVT::i64, 35},
- {Intrinsic::vp_cttz, MVT::i8, 16},
- {Intrinsic::vp_cttz, MVT::i16, 23},
- {Intrinsic::vp_cttz, MVT::i32, 24},
- {Intrinsic::vp_cttz, MVT::i64, 25},
};
InstructionCost
@@ -3543,49 +3516,22 @@ bool RISCVTTIImpl::canSplatOperand(Instruction *I, int Operand) const {
switch (II->getIntrinsicID()) {
case Intrinsic::fma:
- case Intrinsic::vp_fma:
case Intrinsic::fmuladd:
- case Intrinsic::vp_fmuladd:
return Operand == 0 || Operand == 1;
- case Intrinsic::vp_shl:
- case Intrinsic::vp_lshr:
- case Intrinsic::vp_ashr:
case Intrinsic::vp_udiv:
case Intrinsic::vp_sdiv:
case Intrinsic::vp_urem:
case Intrinsic::vp_srem:
case Intrinsic::ssub_sat:
- case Intrinsic::vp_ssub_sat:
case Intrinsic::usub_sat:
- case Intrinsic::vp_usub_sat:
- case Intrinsic::vp_select:
return Operand == 1;
// These intrinsics are commutative.
- case Intrinsic::vp_add:
- case Intrinsic::vp_mul:
- case Intrinsic::vp_and:
- case Intrinsic::vp_or:
- case Intrinsic::vp_xor:
- case Intrinsic::vp_fadd:
- case Intrinsic::vp_fmul:
- case Intrinsic::vp_icmp:
- case Intrinsic::vp_fcmp:
case Intrinsic::smin:
- case Intrinsic::vp_smin:
case Intrinsic::umin:
- case Intrinsic::vp_umin:
case Intrinsic::smax:
- case Intrinsic::vp_smax:
case Intrinsic::umax:
- case Intrinsic::vp_umax:
case Intrinsic::sadd_sat:
- case Intrinsic::vp_sadd_sat:
case Intrinsic::uadd_sat:
- case Intrinsic::vp_uadd_sat:
- // These intrinsics have 'vr' versions.
- case Intrinsic::vp_sub:
- case Intrinsic::vp_fsub:
- case Intrinsic::vp_fdiv:
return Operand == 0 || Operand == 1;
default:
return false;
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
index 69f44e64b2de9..f40f3f5ebda93 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
@@ -1666,23 +1666,6 @@ class LLVM_VPBinaryBase<string mnem, Type element>
class LLVM_VPBinaryI<string mnem> : LLVM_VPBinaryBase<mnem, AnySignlessInteger>;
-class LLVM_VPBinaryF<string mnem> : LLVM_VPBinaryBase<mnem, AnyFloat>;
-
-class LLVM_VPUnaryBase<string mnem, Type element>
- : LLVM_OneResultIntrOp<"vp." # mnem, [0], [], [Pure]>,
- Arguments<(ins LLVM_VectorOf<element>:$op,
- LLVM_VectorOf<I1>:$mask, I32:$evl)>;
-
-class LLVM_VPUnaryF<string mnem> : LLVM_VPUnaryBase<mnem, AnyFloat>;
-
-class LLVM_VPTernaryBase<string mnem, Type element>
- : LLVM_OneResultIntrOp<"vp." # mnem, [0], [], [Pure]>,
- Arguments<(ins LLVM_VectorOf<element>:$op1, LLVM_VectorOf<element>:$op2,
- LLVM_VectorOf<element>:$op3, LLVM_VectorOf<I1>:$mask,
- I32:$evl)>;
-
-class LLVM_VPTernaryF<string mnem> : LLVM_VPTernaryBase<mnem, AnyFloat>;
-
class LLVM_VPReductionBase<string mnem, Type element>
: LLVM_OneResultIntrOp<"vp.reduce." # mnem, [], [1], [Pure]>,
Arguments<(ins element:$satrt_value, LLVM_VectorOf<element>:$val,
@@ -1697,49 +1680,11 @@ class LLVM_VPSelectBase<string mnem>
Arguments<(ins LLVM_VectorOf<I1>:$cond, LLVM_AnyVector:$true_val,
LLVM_AnyVector:$false_val, I32:$evl)>;
-class LLVM_VPCastBase<string mnem, Type element>
- : LLVM_OneResultIntrOp<"vp." # mnem, [0], [0], [Pure]>,
- Arguments<(ins LLVM_VectorOf<element>:$src,
- LLVM_VectorOf<I1>:$mask, I32:$evl)>;
-
-class LLVM_VPCastI<string mnem> : LLVM_VPCastBase<mnem, AnySignlessInteger>;
-
-class LLVM_VPCastF<string mnem> : LLVM_VPCastBase<mnem, AnyFloat>;
-
-class LLVM_VPCastPtr<string mnem> : LLVM_VPCastBase<mnem, LLVM_AnyPointer>;
-
// Integer Binary
-def LLVM_VPAddOp : LLVM_VPBinaryI<"add">;
-def LLVM_VPSubOp : LLVM_VPBinaryI<"sub">;
-def LLVM_VPMulOp : LLVM_VPBinaryI<"mul">;
def LLVM_VPSDivOp : LLVM_VPBinaryI<"sdiv">;
def LLVM_VPUDivOp : LLVM_VPBinaryI<"udiv">;
def LLVM_VPSRemOp : LLVM_VPBinaryI<"srem">;
def LLVM_VPURemOp : LLVM_VPBinaryI<"urem">;
-def LLVM_VPAShrOp : LLVM_VPBinaryI<"ashr">;
-def LLVM_VPLShrOp : LLVM_VPBinaryI<"lshr">;
-def LLVM_VPShlOp : LLVM_VPBinaryI<"shl">;
-def LLVM_VPOrOp : LLVM_VPBinaryI<"or">;
-def LLVM_VPAndOp : LLVM_VPBinaryI<"and">;
-def LLVM_VPXorOp : LLVM_VPBinaryI<"xor">;
-def LLVM_VPSMaxOp : LLVM_VPBinaryI<"smax">;
-def LLVM_VPSMinOp : LLVM_VPBinaryI<"smin">;
-def LLVM_VPUMaxOp : LLVM_VPBinaryI<"umax">;
-def LLVM_VPUMinOp : LLVM_VPBinaryI<"umin">;
-
-// Float Binary
-def LLVM_VPFAddOp : LLVM_VPBinaryF<"fadd">;
-def LLVM_VPFSubOp : LLVM_VPBinaryF<"fsub">;
-def LLVM_VPFMulOp : LLVM_VPBinaryF<"fmul">;
-def LLVM_VPFDivOp : LLVM_VPBinaryF<"fdiv">;
-def LLVM_VPFRemOp : LLVM_VPBinaryF<"frem">;
-
-// Float Unary
-def LLVM_VPFNegOp : LLVM_VPUnaryF<"fneg">;
-
-// Float Ternary
-def LLVM_VPFMulAddOp : LLVM_VPTernaryF<"fmuladd">;
-def LLVM_VPFmaOp : LLVM_VPTernaryF<"fma">;
// Integer Reduction
def LLVM_VPReduceAddOp : LLVM_VPReductionI<"add">;
@@ -1758,7 +1703,6 @@ def LLVM_VPReduceFMulOp : LLVM_VPReductionF<"fmul">;
def LLVM_VPReduceFMaxOp : LLVM_VPReductionF<"fmax">;
def LLVM_VPReduceFMinOp : LLVM_VPReductionF<"fmin">;
-def LLVM_VPSelectMinOp : LLVM_VPSelectBase<"select">;
def LLVM_VPMergeMinOp : LLVM_VPSelectBase<"merge">;
// Load/store
@@ -1784,20 +1728,4 @@ def LLVM_VPStridedStoreOp
Arguments<(ins LLVM_AnyVector:$val, LLVM_AnyPointer:$ptr,
AnySignlessInteger:$stride, LLVM_VectorOf<I1>:$mask, I32:$evl)>;
-def LLVM_VPTruncOp : LLVM_VPCastI<"trunc">;
-def LLVM_VPZExtOp : LLVM_VPCastI<"zext">;
-def LLVM_VPSExtOp : LLVM_VPCastI<"sext">;
-
-def LLVM_VPFPTruncOp : LLVM_VPCastF<"fptrunc">;
-def LLVM_VPFPExtOp : LLVM_VPCastF<"fpext">;
-
-def LLVM_VPFPToUIOp : LLVM_VPCastF<"fptoui">;
-def LLVM_VPFPToSIOp : LLVM_VPCastF<"fptosi">;
-
-def LLVM_VPUIToFPOp : LLVM_VPCastI<"uitofp">;
-def LLVM_VPSIToFPOp : LLVM_VPCastI<"sitofp">;
-
-def LLVM_VPPtrToIntOp : LLVM_VPCastPtr<"ptrtoint">;
-def LLVM_VPIntToPtrOp : LLVM_VPCastI<"inttoptr">;
-
#endif // LLVM_INTRINSIC_OP
>From d8708dc8f972754215091b08882e0edc09ddefe3 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Sat, 22 Aug 2026 00:01:24 +0800
Subject: [PATCH 2/2] Fix mlir test
---
.../test/Target/LLVMIR/llvmir-intrinsics.mlir | 127 ------------------
1 file changed, 127 deletions(-)
diff --git a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
index 13d4155e4ca04..b3776c9a99f97 100644
--- a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+++ b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
@@ -1032,15 +1032,6 @@ llvm.func @vector_predication_intrinsics(%A: vector<8xi32>, %B: vector<8xi32>,
%iptr : !llvm.ptr,
%fptr : !llvm.ptr,
%mask: vector<8xi1>, %evl: i32) {
- // CHECK: call <8 x i32> @llvm.vp.add.v8i32
- "llvm.intr.vp.add" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.sub.v8i32
- "llvm.intr.vp.sub" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.mul.v8i32
- "llvm.intr.vp.mul" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
// CHECK: call <8 x i32> @llvm.vp.sdiv.v8i32
"llvm.intr.vp.sdiv" (%A, %B, %mask, %evl) :
(vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
@@ -1053,61 +1044,6 @@ llvm.func @vector_predication_intrinsics(%A: vector<8xi32>, %B: vector<8xi32>,
// CHECK: call <8 x i32> @llvm.vp.urem.v8i32
"llvm.intr.vp.urem" (%A, %B, %mask, %evl) :
(vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.ashr.v8i32
- "llvm.intr.vp.ashr" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.lshr.v8i32
- "llvm.intr.vp.lshr" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.shl.v8i32
- "llvm.intr.vp.shl" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.or.v8i32
- "llvm.intr.vp.or" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.and.v8i32
- "llvm.intr.vp.and" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.xor.v8i32
- "llvm.intr.vp.xor" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.smax.v8i32
- "llvm.intr.vp.smax" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.smin.v8i32
- "llvm.intr.vp.smin" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.umax.v8i32
- "llvm.intr.vp.umax" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.umin.v8i32
- "llvm.intr.vp.umin" (%A, %B, %mask, %evl) :
- (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
-
- // CHECK: call <8 x float> @llvm.vp.fadd.v8f32
- "llvm.intr.vp.fadd" (%C, %D, %mask, %evl) :
- (vector<8xf32>, vector<8xf32>, vector<8xi1>, i32) -> vector<8xf32>
- // CHECK: call <8 x float> @llvm.vp.fsub.v8f32
- "llvm.intr.vp.fsub" (%C, %D, %mask, %evl) :
- (vector<8xf32>, vector<8xf32>, vector<8xi1>, i32) -> vector<8xf32>
- // CHECK: call <8 x float> @llvm.vp.fmul.v8f32
- "llvm.intr.vp.fmul" (%C, %D, %mask, %evl) :
- (vector<8xf32>, vector<8xf32>, vector<8xi1>, i32) -> vector<8xf32>
- // CHECK: call <8 x float> @llvm.vp.fdiv.v8f32
- "llvm.intr.vp.fdiv" (%C, %D, %mask, %evl) :
- (vector<8xf32>, vector<8xf32>, vector<8xi1>, i32) -> vector<8xf32>
- // CHECK: call <8 x float> @llvm.vp.frem.v8f32
- "llvm.intr.vp.frem" (%C, %D, %mask, %evl) :
- (vector<8xf32>, vector<8xf32>, vector<8xi1>, i32) -> vector<8xf32>
- // CHECK: call <8 x float> @llvm.vp.fneg.v8f32
- "llvm.intr.vp.fneg" (%C, %mask, %evl) :
- (vector<8xf32>, vector<8xi1>, i32) -> vector<8xf32>
- // CHECK: call <8 x float> @llvm.vp.fma.v8f32
- "llvm.intr.vp.fma" (%C, %D, %D, %mask, %evl) :
- (vector<8xf32>, vector<8xf32>, vector<8xf32>, vector<8xi1>, i32) -> vector<8xf32>
- // CHECK: call <8 x float> @llvm.vp.fmuladd.v8f32
- "llvm.intr.vp.fmuladd" (%C, %D, %D, %mask, %evl) :
- (vector<8xf32>, vector<8xf32>, vector<8xf32>, vector<8xi1>, i32) -> vector<8xf32>
// CHECK: call i32 @llvm.vp.reduce.add.v8i32
"llvm.intr.vp.reduce.add" (%i, %A, %mask, %evl) :
@@ -1150,9 +1086,6 @@ llvm.func @vector_predication_intrinsics(%A: vector<8xi32>, %B: vector<8xi32>,
"llvm.intr.vp.reduce.fmin" (%f, %C, %mask, %evl) :
(f32, vector<8xf32>, vector<8xi1>, i32) -> f32
- // CHECK: call <8 x i32> @llvm.vp.select.v8i32
- "llvm.intr.vp.select" (%mask, %A, %B, %evl) :
- (vector<8xi1>, vector<8xi32>, vector<8xi32>, i32) -> vector<8xi32>
// CHECK: call <8 x i32> @llvm.vp.merge.v8i32
"llvm.intr.vp.merge" (%mask, %A, %B, %evl) :
(vector<8xi1>, vector<8xi32>, vector<8xi32>, i32) -> vector<8xi32>
@@ -1170,36 +1103,6 @@ llvm.func @vector_predication_intrinsics(%A: vector<8xi32>, %B: vector<8xi32>,
"llvm.intr.experimental.vp.strided.load" (%iptr, %i, %mask, %evl) :
(!llvm.ptr, i32, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i32> @llvm.vp.trunc.v8i32.v8i64
- "llvm.intr.vp.trunc" (%E, %mask, %evl) :
- (vector<8xi64>, vector<8xi1>, i32) -> vector<8xi32>
- // CHECK: call <8 x i64> @llvm.vp.zext.v8i64.v8i32
- "llvm.intr.vp.zext" (%A, %mask, %evl) :
- (vector<8xi32>, vector<8xi1>, i32) -> vector<8xi64>
- // CHECK: call <8 x i64> @llvm.vp.sext.v8i64.v8i32
- "llvm.intr.vp.sext" (%A, %mask, %evl) :
- (vector<8xi32>, vector<8xi1>, i32) -> vector<8xi64>
-
- // CHECK: call <8 x float> @llvm.vp.fptrunc.v8f32.v8f64
- "llvm.intr.vp.fptrunc" (%F, %mask, %evl) :
- (vector<8xf64>, vector<8xi1>, i32) -> vector<8xf32>
- // CHECK: call <8 x double> @llvm.vp.fpext.v8f64.v8f32
- "llvm.intr.vp.fpext" (%C, %mask, %evl) :
- (vector<8xf32>, vector<8xi1>, i32) -> vector<8xf64>
-
- // CHECK: call <8 x i64> @llvm.vp.fptoui.v8i64.v8f64
- "llvm.intr.vp.fptoui" (%F, %mask, %evl) :
- (vector<8xf64>, vector<8xi1>, i32) -> vector<8xi64>
- // CHECK: call <8 x i64> @llvm.vp.fptosi.v8i64.v8f64
- "llvm.intr.vp.fptosi" (%F, %mask, %evl) :
- (vector<8xf64>, vector<8xi1>, i32) -> vector<8xi64>
-
- // CHECK: call <8 x i64> @llvm.vp.ptrtoint.v8i64.v8p0
- "llvm.intr.vp.ptrtoint" (%G, %mask, %evl) :
- (vector<8 x !llvm.ptr>, vector<8xi1>, i32) -> vector<8xi64>
- // CHECK: call <8 x ptr> @llvm.vp.inttoptr.v8p0.v8i64
- "llvm.intr.vp.inttoptr" (%E, %mask, %evl) :
- (vector<8xi64>, vector<8xi1>, i32) -> vector<8 x !llvm.ptr>
llvm.return
}
@@ -2163,30 +2066,10 @@ llvm.func @vector_scmp(%a: vector<4 x i32>, %b: vector<4 x i32>) -> vector<4 x i
// CHECK-DAG: declare void @llvm.coro.await.suspend.void(ptr, ptr, ptr)
// CHECK-DAG: declare i1 @llvm.coro.await.suspend.bool(ptr, ptr, ptr)
// CHECK-DAG: declare void @llvm.coro.await.suspend.handle(ptr, ptr, ptr)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.mul.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
// CHECK-DAG: declare <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
// CHECK-DAG: declare <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
// CHECK-DAG: declare <8 x i32> @llvm.vp.srem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
// CHECK-DAG: declare <8 x i32> @llvm.vp.urem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.shl.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.or.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.and.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.xor.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.smax.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.smin.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.umax.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.umin.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x float> @llvm.vp.fadd.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x float> @llvm.vp.fsub.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x float> @llvm.vp.fmul.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x float> @llvm.vp.fdiv.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x float> @llvm.vp.frem.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x float> @llvm.vp.fneg.v8f32(<8 x float>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x float> @llvm.vp.fma.v8f32(<8 x float>, <8 x float>, <8 x float>, <8 x i1>, i32)
// CHECK-DAG: declare i32 @llvm.vp.reduce.add.v8i32(i32, <8 x i32>, <8 x i1>, i32)
// CHECK-DAG: declare i32 @llvm.vp.reduce.mul.v8i32(i32, <8 x i32>, <8 x i1>, i32)
// CHECK-DAG: declare i32 @llvm.vp.reduce.and.v8i32(i32, <8 x i32>, <8 x i1>, i32)
@@ -2200,19 +2083,9 @@ llvm.func @vector_scmp(%a: vector<4 x i32>, %b: vector<4 x i32>) -> vector<4 x i
// CHECK-DAG: declare float @llvm.vp.reduce.fmul.v8f32(float, <8 x float>, <8 x i1>, i32)
// CHECK-DAG: declare float @llvm.vp.reduce.fmax.v8f32(float, <8 x float>, <8 x i1>, i32)
// CHECK-DAG: declare float @llvm.vp.reduce.fmin.v8f32(float, <8 x float>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.select.v8i32(<8 x i1>, <8 x i32>, <8 x i32>, i32)
// CHECK-DAG: declare <8 x i32> @llvm.vp.merge.v8i32(<8 x i1>, <8 x i32>, <8 x i32>, i32)
// CHECK-DAG: declare void @llvm.experimental.vp.strided.store.v8i32.p0.i32(<8 x i32>, ptr captures(none), i32, <8 x i1>, i32)
// CHECK-DAG: declare <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0.i32(ptr captures(none), i32, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i32> @llvm.vp.trunc.v8i32.v8i64(<8 x i64>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i64> @llvm.vp.zext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i64> @llvm.vp.sext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x float> @llvm.vp.fptrunc.v8f32.v8f64(<8 x double>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x double> @llvm.vp.fpext.v8f64.v8f32(<8 x float>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i64> @llvm.vp.fptoui.v8i64.v8f64(<8 x double>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i64> @llvm.vp.fptosi.v8i64.v8f64(<8 x double>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x i64> @llvm.vp.ptrtoint.v8i64.v8p0(<8 x ptr>, <8 x i1>, i32)
-// CHECK-DAG: declare <8 x ptr> @llvm.vp.inttoptr.v8p0.v8i64(<8 x i64>, <8 x i1>, i32)
// CHECK-DAG: declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v8i32(<vscale x 4 x i32>, <8 x i32>, i64 immarg)
// CHECK-DAG: declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64 immarg)
// CHECK-DAG: declare <8 x i32> @llvm.vector.insert.v8i32.v4i32(<8 x i32>, <4 x i32>, i64 immarg)
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