[Mlir-commits] [mlir] [MLIR][Vector] Enable strict property assembly format (PR #217288)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Wed Aug 19 03:52:03 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir-arith
Author: Mehdi Amini (joker-eph)
<details>
<summary>Changes</summary>
Enable strict property assembly format mode for the Vector dialect. Spell strided-slice, memory, and scan properties directly in the affected declarative assembly formats.
Refresh vector-related tests so inherent vector properties use direct syntax while ordinary attributes remain in attr-dict.
Assisted-by: Codex
---
Patch is 631.04 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/217288.diff
60 Files Affected:
- (modified) mlir/include/mlir/Dialect/Vector/IR/Vector.td (+1)
- (modified) mlir/include/mlir/Dialect/Vector/IR/VectorOps.td (+57-27)
- (modified) mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir (+6-6)
- (modified) mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir (+1-1)
- (modified) mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir (+1-1)
- (modified) mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir (+24-24)
- (modified) mlir/test/Conversion/ArithToAMDGPU/8-bit-floats.mlir (+24-24)
- (modified) mlir/test/Conversion/ArithToAMDGPU/scaling-extf.mlir (+68-68)
- (modified) mlir/test/Conversion/ArithToAMDGPU/scaling-truncf.mlir (+28-28)
- (modified) mlir/test/Conversion/ConvertToSPIRV/func-signature-vector-unroll.mlir (+60-60)
- (modified) mlir/test/Conversion/ConvertToSPIRV/vector.mlir (+1-1)
- (modified) mlir/test/Conversion/VectorToGPU/fold-arith-vector-to-mma-ops-mma-sync.mlir (+4-4)
- (modified) mlir/test/Conversion/VectorToGPU/vector-to-mma-ops-mma-sync.mlir (+12-12)
- (modified) mlir/test/Conversion/VectorToLLVM/use-vector-alignment.mlir (+6-6)
- (modified) mlir/test/Conversion/VectorToLLVM/vector-load-store-to-llvm.mlir (+6-6)
- (modified) mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir (+6-6)
- (modified) mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir (+14-14)
- (modified) mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir (+6-6)
- (modified) mlir/test/Dialect/AMDGPU/canonicalize.mlir (+4-4)
- (modified) mlir/test/Dialect/Arith/emulate-wide-int.mlir (+31-31)
- (modified) mlir/test/Dialect/ArmNeon/lower-to-arm-neon.mlir (+111-111)
- (modified) mlir/test/Dialect/ArmNeon/roundtrip.mlir (+2-2)
- (modified) mlir/test/Dialect/ArmNeon/vector-bfmmla.mlir (+48-48)
- (modified) mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir (+6-6)
- (modified) mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns-flatten.mlir (+19-19)
- (modified) mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns.mlir (+98-98)
- (modified) mlir/test/Dialect/Linalg/vectorization/convolution.mlir (+10-10)
- (modified) mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir (+8-8)
- (modified) mlir/test/Dialect/MemRef/invalid.mlir (+1-1)
- (modified) mlir/test/Dialect/Vector/canonicalize.mlir (+81-81)
- (modified) mlir/test/Dialect/Vector/invalid.mlir (+42-42)
- (modified) mlir/test/Dialect/Vector/linearize.mlir (+9-9)
- (modified) mlir/test/Dialect/Vector/mem2reg.mlir (+15-15)
- (modified) mlir/test/Dialect/Vector/ops.mlir (+13-13)
- (modified) mlir/test/Dialect/Vector/vector-break-down-bitcast.mlir (+12-12)
- (modified) mlir/test/Dialect/Vector/vector-dropleadunitdim-transforms.mlir (+10-10)
- (modified) mlir/test/Dialect/Vector/vector-emulate-masked-load-store.mlir (+2-2)
- (modified) mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned-non-atomic.mlir (+10-10)
- (modified) mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir (+22-22)
- (modified) mlir/test/Dialect/Vector/vector-extract-strided-slice-lowering.mlir (+2-2)
- (modified) mlir/test/Dialect/Vector/vector-gather-lowering.mlir (+8-8)
- (modified) mlir/test/Dialect/Vector/vector-scan-transforms.mlir (+43-43)
- (modified) mlir/test/Dialect/Vector/vector-shape-cast-lowering-transforms.mlir (+29-29)
- (modified) mlir/test/Dialect/Vector/vector-transfer-unroll.mlir (+102-102)
- (modified) mlir/test/Dialect/Vector/vector-transforms.mlir (+36-36)
- (modified) mlir/test/Dialect/Vector/vector-unroll-options.mlir (+152-152)
- (modified) mlir/test/Dialect/Vector/vector-warp-distribute.mlir (+8-8)
- (modified) mlir/test/Dialect/XeGPU/array-len-op-unit.mlir (+15-15)
- (modified) mlir/test/Dialect/XeGPU/peephole-optimize.mlir (+10-10)
- (modified) mlir/test/Dialect/XeGPU/propagate-layout.mlir (+12-12)
- (modified) mlir/test/Dialect/XeGPU/resolve-layout-conflicts.mlir (+3-3)
- (modified) mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir (+52-63)
- (modified) mlir/test/Dialect/XeGPU/xegpu-blocking.mlir (+16-16)
- (modified) mlir/test/Dialect/XeGPU/xegpu-vector-linearize.mlir (+4-4)
- (modified) mlir/test/Integration/Dialect/Vector/CPU/contraction.mlir (+2-2)
- (modified) mlir/test/Integration/Dialect/Vector/CPU/extract-strided-slice.mlir (+1-1)
- (modified) mlir/test/Integration/Dialect/Vector/CPU/insert-strided-slice.mlir (+4-4)
- (modified) mlir/test/Integration/Dialect/Vector/CPU/scan.mlir (+4-4)
- (modified) mlir/test/Integration/Dialect/Vector/CPU/transpose.mlir (+2-2)
- (modified) mlir/test/Integration/Dialect/XeVM/GPU/xevm_block_load_store_pack_register.mlir (+2-2)
``````````diff
diff --git a/mlir/include/mlir/Dialect/Vector/IR/Vector.td b/mlir/include/mlir/Dialect/Vector/IR/Vector.td
index 5125ae7c13717..f5e76c168f335 100644
--- a/mlir/include/mlir/Dialect/Vector/IR/Vector.td
+++ b/mlir/include/mlir/Dialect/Vector/IR/Vector.td
@@ -18,6 +18,7 @@ include "mlir/IR/OpBase.td"
def Vector_Dialect : Dialect {
let name = "vector";
let cppNamespace = "::mlir::vector";
+ let useStrictPropertiesInAssemblyFormat = 1;
let useDefaultAttributePrinterParser = 1;
let hasConstantMaterializer = 1;
diff --git a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
index 5f701cfcbd1b7..c73fc4e490fa8 100644
--- a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
+++ b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
@@ -1075,13 +1075,15 @@ def Vector_InsertStridedSliceOp :
```mlir
%2 = vector.insert_strided_slice %0, %1
- {offsets = [0, 0, 2], strides = [1, 1]}:
+ offsets = [0, 0, 2], strides = [1, 1] :
vector<2x4xf32> into vector<16x4x8xf32>
```
}];
let assemblyFormat = [{
- $valueToStore `,` $dest attr-dict `:` type($valueToStore) `into` type($dest)
+ $valueToStore `,` $dest
+ `offsets` `=` $offsets `,` `strides` `=` $strides attr-dict
+ `:` type($valueToStore) `into` type($dest)
}];
let builders = [
@@ -1217,7 +1219,7 @@ def Vector_ExtractStridedSliceOp :
```mlir
%1 = vector.extract_strided_slice %0
- {offsets = [0, 2], sizes = [2, 4], strides = [1, 1]}:
+ offsets = [0, 2], sizes = [2, 4], strides = [1, 1] :
vector<4x8x16xf32> to vector<2x4x16xf32>
// TODO: Evolve to a range form syntax similar to:
@@ -1245,7 +1247,10 @@ def Vector_ExtractStridedSliceOp :
let hasCanonicalizer = 1;
let hasFolder = 1;
let hasVerifier = 1;
- let assemblyFormat = "$source attr-dict `:` type($source) `to` type(results)";
+ let assemblyFormat = [{
+ $source `offsets` `=` $offsets `,` `sizes` `=` $sizes `,`
+ `strides` `=` $strides attr-dict `:` type($source) `to` type(results)
+ }];
}
// TODO: Tighten semantics so that masks and inbounds can't be used
@@ -1785,8 +1790,12 @@ def Vector_LoadOp : Vector_Op<"load", [
let hasFolder = 1;
let hasVerifier = 1;
- let assemblyFormat =
- "$base `[` $indices `]` attr-dict `:` type($base) `,` type($result)";
+ let assemblyFormat = [{
+ $base `[` $indices `]`
+ (`alignment` `=` $alignment^)?
+ (`nontemporal` `=` $nontemporal^)?
+ attr-dict `:` type($base) `,` type($result)
+ }];
}
// Promises IndexedAccessOpInterface.
@@ -1896,8 +1905,12 @@ def Vector_StoreOp : Vector_Op<"store", [
let hasFolder = 1;
let hasVerifier = 1;
- let assemblyFormat = "$valueToStore `,` $base `[` $indices `]` attr-dict "
- "`:` type($base) `,` type($valueToStore)";
+ let assemblyFormat = [{
+ $valueToStore `,` $base `[` $indices `]`
+ (`alignment` `=` $alignment^)?
+ (`nontemporal` `=` $nontemporal^)?
+ attr-dict `:` type($base) `,` type($valueToStore)
+ }];
}
// Promises IndexedAccessOpInterface.
@@ -1969,8 +1982,12 @@ def Vector_MaskedLoadOp :
return ::llvm::cast<VectorType>(getResult().getType());
}
}];
- let assemblyFormat = "$base `[` $indices `]` `,` $mask `,` $pass_thru attr-dict `:` "
- "type($base) `,` type($mask) `,` type($pass_thru) `into` type($result)";
+ let assemblyFormat = [{
+ $base `[` $indices `]` `,` $mask `,` $pass_thru
+ (`alignment` `=` $alignment^)?
+ attr-dict `:` type($base) `,` type($mask) `,`
+ type($pass_thru) `into` type($result)
+ }];
let hasCanonicalizer = 1;
let hasFolder = 1;
let hasVerifier = 1;
@@ -2064,9 +2081,11 @@ def Vector_MaskedStoreOp :
return ::llvm::cast<VectorType>(getValueToStore().getType());
}
}];
- let assemblyFormat =
- "$base `[` $indices `]` `,` $mask `,` $valueToStore "
- "attr-dict `:` type($base) `,` type($mask) `,` type($valueToStore)";
+ let assemblyFormat = [{
+ $base `[` $indices `]` `,` $mask `,` $valueToStore
+ (`alignment` `=` $alignment^)?
+ attr-dict `:` type($base) `,` type($mask) `,` type($valueToStore)
+ }];
let hasCanonicalizer = 1;
let hasFolder = 1;
let hasVerifier = 1;
@@ -2173,7 +2192,8 @@ def Vector_GatherOp :
let assemblyFormat =
"$base `[` $offsets `]` `[` $indices `]` `,` "
- "$mask `,` $pass_thru attr-dict `:` type($base) `,` "
+ "$mask `,` $pass_thru (`alignment` `=` $alignment^)? "
+ "attr-dict `:` type($base) `,` "
"type($indices) `,` type($mask) `,` type($pass_thru) "
"`into` type($result)";
let hasCanonicalizer = 1;
@@ -2264,10 +2284,12 @@ def Vector_ScatterOp
VectorType getVectorType() { return getValueToStore().getType(); }
}];
- let assemblyFormat = "$base `[` $offsets `]` `[` $indices `]` `,` "
- "$mask `,` $valueToStore attr-dict `:` type($base) `,` "
- "type($indices) `,` type($mask) `,` "
- "type($valueToStore) (`->` type($result)^)?";
+ let assemblyFormat = [{
+ $base `[` $offsets `]` `[` $indices `]` `,` $mask `,` $valueToStore
+ (`alignment` `=` $alignment^)?
+ attr-dict `:` type($base) `,` type($indices) `,` type($mask) `,`
+ type($valueToStore) (`->` type($result)^)?
+ }];
let hasCanonicalizer = 1;
let hasVerifier = 1;
@@ -2353,8 +2375,12 @@ def Vector_ExpandLoadOp :
return ::llvm::cast<VectorType>(getResult().getType());
}
}];
- let assemblyFormat = "$base `[` $indices `]` `,` $mask `,` $pass_thru attr-dict `:` "
- "type($base) `,` type($mask) `,` type($pass_thru) `into` type($result)";
+ let assemblyFormat = [{
+ $base `[` $indices `]` `,` $mask `,` $pass_thru
+ (`alignment` `=` $alignment^)?
+ attr-dict `:` type($base) `,` type($mask) `,`
+ type($pass_thru) `into` type($result)
+ }];
let hasCanonicalizer = 1;
let hasVerifier = 1;
@@ -2439,9 +2465,11 @@ def Vector_CompressStoreOp :
return ::llvm::cast<VectorType>(getValueToStore().getType());
}
}];
- let assemblyFormat =
- "$base `[` $indices `]` `,` $mask `,` $valueToStore attr-dict `:` "
- "type($base) `,` type($mask) `,` type($valueToStore)";
+ let assemblyFormat = [{
+ $base `[` $indices `]` `,` $mask `,` $valueToStore
+ (`alignment` `=` $alignment^)?
+ attr-dict `:` type($base) `,` type($mask) `,` type($valueToStore)
+ }];
let hasCanonicalizer = 1;
let hasVerifier = 1;
let builders = [
@@ -3008,7 +3036,7 @@ def Vector_ScanOp :
Example:
```mlir
- %1:2 = vector.scan <add>, %0, %acc {inclusive = false, reduction_dim = 1 : i64} :
+ %1:2 = vector.scan <add>, %0, %acc reduction_dim = 1, inclusive = false :
vector<4x8x16x32xf32>, vector<4x16x32xf32>
```
}];
@@ -3027,9 +3055,11 @@ def Vector_ScanOp :
return ::llvm::cast<VectorType>(getInitialValue().getType());
}
}];
- let assemblyFormat =
- "$kind `,` $source `,` $initial_value attr-dict `:` "
- "type($source) `,` type($initial_value) ";
+ let assemblyFormat = [{
+ $kind `,` $source `,` $initial_value
+ `reduction_dim` `=` $reduction_dim `,` `inclusive` `=` $inclusive
+ attr-dict `:` type($source) `,` type($initial_value)
+ }];
let hasVerifier = 1;
}
diff --git a/mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir b/mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir
index 8991506dee1df..6077ef349408f 100644
--- a/mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir
+++ b/mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir
@@ -28,23 +28,23 @@ func.func @vector_trunc_long(%v: vector<9xf32>) -> vector<9xf16> {
// CHECK: %[[elem0:.*]] = vector.extract %[[value]][0]
// CHECK: %[[elem1:.*]] = vector.extract %[[value]][1]
// CHECK: %[[packed0:.*]] = rocdl.cvt.pkrtz %[[elem0]], %[[elem1]] : vector<2xf16>
- // CHECK: %[[out0:.*]] = vector.insert_strided_slice %[[packed0]], {{.*}} {offsets = [0], strides = [1]} : vector<2xf16> into vector<9xf16>
+ // CHECK: %[[out0:.*]] = vector.insert_strided_slice %[[packed0]], {{.*}} offsets = [0], strides = [1] : vector<2xf16> into vector<9xf16>
// CHECK: %[[elem2:.*]] = vector.extract %[[value]][2]
// CHECK: %[[elem3:.*]] = vector.extract %[[value]][3]
// CHECK: %[[packed1:.*]] = rocdl.cvt.pkrtz %[[elem2]], %[[elem3]] : vector<2xf16>
- // CHECK: %[[out1:.*]] = vector.insert_strided_slice %[[packed1]], %[[out0]] {offsets = [2], strides = [1]} : vector<2xf16> into vector<9xf16>
+ // CHECK: %[[out1:.*]] = vector.insert_strided_slice %[[packed1]], %[[out0]] offsets = [2], strides = [1] : vector<2xf16> into vector<9xf16>
// CHECK: %[[elem4:.*]] = vector.extract %[[value]][4]
// CHECK: %[[elem5:.*]] = vector.extract %[[value]][5]
// CHECK: %[[packed2:.*]] = rocdl.cvt.pkrtz %[[elem4]], %[[elem5]] : vector<2xf16>
- // CHECK: %[[out2:.*]] = vector.insert_strided_slice %[[packed2]], %[[out1]] {offsets = [4], strides = [1]} : vector<2xf16> into vector<9xf16>
+ // CHECK: %[[out2:.*]] = vector.insert_strided_slice %[[packed2]], %[[out1]] offsets = [4], strides = [1] : vector<2xf16> into vector<9xf16>
// CHECK: %[[elem6:.*]] = vector.extract %[[value]]
// CHECK: %[[elem7:.*]] = vector.extract %[[value]]
// CHECK: %[[packed3:.*]] = rocdl.cvt.pkrtz %[[elem6]], %[[elem7]] : vector<2xf16>
- // CHECK: %[[out3:.*]] = vector.insert_strided_slice %[[packed3]], %[[out2]] {offsets = [6], strides = [1]} : vector<2xf16> into vector<9xf16>
+ // CHECK: %[[out3:.*]] = vector.insert_strided_slice %[[packed3]], %[[out2]] offsets = [6], strides = [1] : vector<2xf16> into vector<9xf16>
// CHECK: %[[elem8:.*]] = vector.extract %[[value]]
// CHECK: %[[packed4:.*]] = rocdl.cvt.pkrtz %[[elem8:.*]] : vector<2xf16>
- // CHECK: %[[slice:.*]] = vector.extract_strided_slice %[[packed4]] {offsets = [0], sizes = [1], strides = [1]} : vector<2xf16> to vector<1xf16>
- // CHECK: %[[out4:.*]] = vector.insert_strided_slice %[[slice]], %[[out3]] {offsets = [8], strides = [1]} : vector<1xf16> into vector<9xf16>
+ // CHECK: %[[slice:.*]] = vector.extract_strided_slice %[[packed4]] offsets = [0], sizes = [1], strides = [1] : vector<2xf16> to vector<1xf16>
+ // CHECK: %[[out4:.*]] = vector.insert_strided_slice %[[slice]], %[[out3]] offsets = [8], strides = [1] : vector<1xf16> into vector<9xf16>
// CHECK: return %[[out4]]
%w = arith.truncf %v : vector<9xf32> to vector<9xf16>
return %w : vector<9xf16>
diff --git a/mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir b/mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir
index 2df5f2fa1965f..e3c2ae9515939 100644
--- a/mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir
+++ b/mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir
@@ -50,7 +50,7 @@ func.func @scalar_trunc(%v: f16) -> f8E5M2 {
// CHECK: [[F0:%.+]] = vector.extract [[SATURATED]][0]
// CHECK: [[F1:%.+]] = vector.extract [[SATURATED]][1]
// CHECK: [[W0:%.+]] = amdgpu.packed_trunc_2xfp8 [[F0]], [[F1]] into undef[word 0] : f32 to vector<4xf8E4M3FN>
-// CHECK: [[W:%.+]] = vector.extract_strided_slice [[W0]] {offsets = [0], sizes = [2], strides = [1]} : vector<4xf8E4M3FN> to vector<2xf8E4M3FN>
+// CHECK: [[W:%.+]] = vector.extract_strided_slice [[W0]] offsets = [0], sizes = [2], strides = [1] : vector<4xf8E4M3FN> to vector<2xf8E4M3FN>
// CHECK: return [[W]] : vector<2xf8E4M3FN>
func.func @vector_trunc_short(%v: vector<2xf32>) -> vector<2xf8E4M3FN> {
%w = arith.truncf %v : vector<2xf32> to vector<2xf8E4M3FN>
diff --git a/mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir b/mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir
index 07a428566d488..b6eabe391c0cd 100644
--- a/mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir
+++ b/mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir
@@ -46,7 +46,7 @@ func.func @scalar_trunc(%v: f16) -> f8E5M2FNUZ {
// CHECK: [[F0:%.+]] = vector.extract [[SATURATED]][0]
// CHECK: [[F1:%.+]] = vector.extract [[SATURATED]][1]
// CHECK: [[W0:%.+]] = amdgpu.packed_trunc_2xfp8 [[F0]], [[F1]] into undef[word 0] : f32 to vector<4xf8E4M3FNUZ>
-// CHECK: [[W:%.+]] = vector.extract_strided_slice [[W0]] {offsets = [0], sizes = [2], strides = [1]} : vector<4xf8E4M3FNUZ> to vector<2xf8E4M3FNUZ>
+// CHECK: [[W:%.+]] = vector.extract_strided_slice [[W0]] offsets = [0], sizes = [2], strides = [1] : vector<4xf8E4M3FNUZ> to vector<2xf8E4M3FNUZ>
// CHECK: return [[W]] : vector<2xf8E4M3FNUZ>
func.func @vector_trunc_short(%v: vector<2xf32>) -> vector<2xf8E4M3FNUZ> {
%w = arith.truncf %v : vector<2xf32> to vector<2xf8E4M3FNUZ>
diff --git a/mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir b/mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir
index 7fb5fbfe0c89e..91a9a57898761 100644
--- a/mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir
+++ b/mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir
@@ -31,17 +31,17 @@ func.func @vector_ext_short(%v: vector<2xf8E5M2>) -> vector<2xf64> {
// CHECK-LABEL: func.func @vector_ext_long
// CHECK-SAME: ([[V:%.+]]: vector<9xf8E4M3FN>)
// CHECK: [[W0:%.+]] = arith.constant dense<0.000000e+00> : vector<9xf32>
-// CHECK: [[IN1:%.+]] = vector.extract_strided_slice [[V]] {offsets = [0], sizes = [4], strides = [1]} : vector<9xf8E4M3FN> to vector<4xf8E4M3FN>
+// CHECK: [[IN1:%.+]] = vector.extract_strided_slice [[V]] offsets = [0], sizes = [4], strides = [1] : vector<9xf8E4M3FN> to vector<4xf8E4M3FN>
// CHECK: [[FLOAT1:%.+]] = amdgpu.ext_packed_fp8 [[IN1]][0] : vector<4xf8E4M3FN> to vector<2xf32>
-// CHECK: [[W1:%.+]] = vector.insert_strided_slice [[FLOAT1]], [[W0]] {offsets = [0], strides = [1]} : vector<2xf32> into vector<9xf32>
+// CHECK: [[W1:%.+]] = vector.insert_strided_slice [[FLOAT1]], [[W0]] offsets = [0], strides = [1] : vector<2xf32> into vector<9xf32>
// CHECK: [[FLOAT2:%.+]] = amdgpu.ext_packed_fp8 [[IN1]][1] : vector<4xf8E4M3FN> to vector<2xf32>
-// CHECK: [[W2:%.+]] = vector.insert_strided_slice [[FLOAT2]], [[W1]] {offsets = [2], strides = [1]} : vector<2xf32> into vector<9xf32>
-// CHECK: [[IN2:%.+]] = vector.extract_strided_slice [[V]] {offsets = [4], sizes = [4], strides = [1]} : vector<9xf8E4M3FN> to vector<4xf8E4M3FN>
+// CHECK: [[W2:%.+]] = vector.insert_strided_slice [[FLOAT2]], [[W1]] offsets = [2], strides = [1] : vector<2xf32> into vector<9xf32>
+// CHECK: [[IN2:%.+]] = vector.extract_strided_slice [[V]] offsets = [4], sizes = [4], strides = [1] : vector<9xf8E4M3FN> to vector<4xf8E4M3FN>
// CHECK: [[FLOAT3:%.+]] = amdgpu.ext_packed_fp8 [[IN2]][0] : vector<4xf8E4M3FN> to vector<2xf32>
-// CHECK: [[W3:%.+]] = vector.insert_strided_slice [[FLOAT3]], [[W2]] {offsets = [4], strides = [1]} : vector<2xf32> into vector<9xf32>
+// CHECK: [[W3:%.+]] = vector.insert_strided_slice [[FLOAT3]], [[W2]] offsets = [4], strides = [1] : vector<2xf32> into vector<9xf32>
// CHECK: [[FLOAT4:%.+]] = amdgpu.ext_packed_fp8 [[IN2]][1] : vector<4xf8E4M3FN> to vector<2xf32>
-// CHECK: [[W4:%.+]] = vector.insert_strided_slice [[FLOAT4]], [[W3]] {offsets = [6], strides = [1]} : vector<2xf32> into vector<9xf32>
-// CHECK: [[IN3:%.+]] = vector.extract_strided_slice [[V]] {offsets = [8], sizes = [1], strides = [1]} : vector<9xf8E4M3FN> to vector<1xf8E4M3FN>
+// CHECK: [[W4:%.+]] = vector.insert_strided_slice [[FLOAT4]], [[W3]] offsets = [6], strides = [1] : vector<2xf32> into vector<9xf32>
+// CHECK: [[IN3:%.+]] = vector.extract_strided_slice [[V]] offsets = [8], sizes = [1], strides = [1] : vector<9xf8E4M3FN> to vector<1xf8E4M3FN>
// CHECK: [[FLOAT5:%.+]] = amdgpu.ext_packed_fp8 [[IN3]][0] : vector<1xf8E4M3FN> to f32
// CHECK: [[W5:%.+]] = vector.insert [[FLOAT5]], [[W4]] [8] : f32 into vector<9xf32>
// CHECK: return [[W5]]
@@ -74,7 +74,7 @@ func.func @scalar_trunc(%v: f16) -> f8E5M2 {
// CHECK: [[V1:%.+]] = vector.extract [[V]][1]
// CHECK: [[F1:%.+]] = arith.truncf [[V1]] : f64 to f32
// CHECK: [[W0:%.+]] = amdgpu.packed_trunc_2xfp8 [[F0]], [[F1]] into undef[word 0] : f32 to vector<4xf8E5M2>
-// CHECK: [[W:%.+]] = vector.extract_strided_slice [[W0]] {offsets = [0], sizes = [2], strides = [1]} : vector<4xf8E5M2> to vector<2xf8E5M2>
+// CHECK: [[W:%.+]] = vector.extract_strided_slice [[W0]] offsets = [0], sizes = [2], strides = [1] : vector<4xf8E5M2> to vector<2xf8E5M2>
// CHECK: return [[W]] : vector<2xf8E5M2>
func.func @vector_trunc_short(%v: vector<2xf64>) -> vector<2xf8E5M2> {
%w = arith.truncf %v : vector<2xf64> to vector<2xf8E5M2>
@@ -88,15 +88,15 @@ func.func @vector_trunc_short(%v: vector<2xf64>) -> vector<2xf8E5M2> {
// CHECK: [[ZEROES:%.+]] = arith.constant dense<0.000000e+00> : vector<9xf8E4M3FN>
// CHECK: [[T0:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, %{{.+}} into undef[word 0]
// CHECK: [[T1:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, %{{.+}} into [[T0]][word 1]
-// CHECK: [[W0:%.+]] = vector.insert_strided_slice [[T1]], [[ZEROES]] {offsets = [0], strides = [1]}
+// CHECK: [[W0:%.+]] = vector.insert_strided_slice [[T1]], [[ZEROES]] offsets = [0], strides = [1]
// CHECK: [[T2:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, %{{.+}} into undef[word 0]
// CHECK: [[T3:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, %{{.+}} into [[T2]][word 1]
-// CHECK: [[W1:%.+]] = vector.insert_strided_slice [[T3]], [[W0]] {offsets = [4], strides = [1]}
+// CHECK: [[W1:%.+]] = vector.insert_strided_slice [[T3]], [[W0]] offsets = [4], strides = [1]
// CHECK: [[T4:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, undef into undef[word 0]
-// CHECK: [[T4_SHORT:%.+]] = vector.extract_strided_slice [[T4]] {offsets = [0], sizes = [1], strides = [1]}
-// CHECK: [[W:%.+]] = vector.insert_strided_slice [[T4_SHORT]], [[W1]] {offsets = [8], strides = [1]}
+// CHECK: [[T4_SHORT:%.+]] = vector.extract_strided_slice [[T4]] offsets = [0], sizes = [1], strides = [1]
+// CHECK: [[W:%.+]] = vector.insert_strided_slice [[T4_SHORT]], [[W1]] offsets = [8], strides = [1]
// CHECK: return [[W]]
func.func @vector_trunc_long(%v: vector<9xf32>) -> vector<9xf8E4M3FN> {
%w = arith.truncf %v : vector<9xf32> to vector<9xf8E4M3FN>
@@ -110,15 +110,15 @@ func.func @vector_trunc_long(%v: vector<9xf32>) -> vector<9xf8E4M3FN> {
// CHECK: [[ZEROES:%.+]] = arith.constant dense<0.000000e+00> : vector<9xf8E4M3FN>
// CHECK: [[T0:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, %{{.+}} into undef[word 0]
// CHECK: [[T1:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, %{{.+}} into [[T0]][word 1]
-// CHECK: [[W0:%.+]] = vector.insert_strided_slice [[T1]], [[ZEROES]] {offsets = [0], strides = [1]}
+// CHECK: [[W0:%.+]] = vector.insert_strided_slice [[T1]], [[ZEROES]] offsets = [0], strides = [1]
// CHECK: [[T2:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, %{{.+}} into undef[word 0]
// CHECK: [[T3:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, %{{.+}} into [[T2]][word 1]
-// CHECK: [[W1:%.+]] = vector.insert_strided_slice [[T3]], [[W0]] {offsets = [4], strides = [1]}
+// CHECK: [[W1:%.+]] = vector.insert_strided_slice [[T3]], [[W0]] offsets = [4], strides = [1]
// CHECK: [[T4:%.+]] = amdgpu.packed_trunc_2xfp8 %{{.+}}, undef into undef[word 0]
-// CHECK: [[T4_SHORT:%.+]] = vector.extract_strided_slice [[T4]] {offsets = [0], sizes = [1], strides = [1]}
-// CHECK: [[W:%.+]] = vector.insert_strided_slice [[T4_SHORT]], [[W1]] {offsets = [8], strides = [1]}
+// CHECK: [[T4_SHORT:%.+]] = vector.extract_strided_slice [[T4]] offsets = [0], sizes = [1], strides = [1]
+// CHECK: [[W:%.+]] = vector.insert_strided_slice [[T4_SHORT]], [[W1]] offsets = [8], strides = [1]
// CHECK: [[RE:%.+]] = vector.shape_cast [[W]] : vector<9xf8E4M3FN> to vector<1x9xf8E4M3FN>
// CHECK: return [[RE]]
func.func @vector_trunc_long_2d(%v: vector<1x9xf32>) -> vector<1x9xf8E4M3FN> {
@@ -132,21 +132,21 @@ func.func @vector_trunc_long_2d(%v: vector<1x9xf32>) -> vector<1x9xf8E4M3FN> {
// CHECK-SAME: ([[V:%.+]]: vector<1x11xf8E4M3FN>)
// CHECK: [[CST:%.+]] = arith.constant dense<0.000000e+00> : vector<11xf32>
// CHECK: [[CAST:%.+]] = vector.shape_cast [[V]] : vector<1x11xf8E4M3FN> to vector<11xf8E4M3FN>
-// CHECK: [[V0:%.+]] = vector.extract_strided_slice [[CAST]] {offsets = [0], sizes = [4], strides = [1]}
+// CHECK: [[V0:%.+]] = vector.extract_strided_slice [[CAST]] offsets = [0], sizes = [4], strides = [1]
// CHECK: [[F0:%.+]] = amdgpu.ext_packed_fp8 [[V0]][0] : vector<4xf8E4M3FN> to vector<2xf32>
-// CHECK: [[W0:%.+]] = vector.insert_strided_slice [[F0]], [[CST]] {offsets = [0], strides = [1]} : vector<2xf32> into v...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/217288
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