[Mlir-commits] [mlir] [MLIR][XeGPU] Enable strict property assembly format (PR #217281)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Wed Aug 19 03:50:47 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir
Author: Mehdi Amini (joker-eph)
<details>
<summary>Changes</summary>
Enable strict property assembly format mode for XeGPU. Spell the DPAS and atomic layout properties directly in custom assembly formats so their syntax remains explicit under strict parsing.
Update XeGPU tests to use the direct layout spelling for those operations.
Assisted-by: Codex
---
Patch is 200.68 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/217281.diff
19 Files Affected:
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td (+1)
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td (+16-8)
- (modified) mlir/test/Conversion/XeGPUToXeVM/loadstore_matrix.mlir (+2-2)
- (modified) mlir/test/Dialect/XeGPU/invalid.mlir (+16-16)
- (modified) mlir/test/Dialect/XeGPU/peephole-optimize.mlir (+8-8)
- (modified) mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir (+13-13)
- (modified) mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir (+17-18)
- (modified) mlir/test/Dialect/XeGPU/propagate-layout.mlir (+7-7)
- (modified) mlir/test/Dialect/XeGPU/resolve-layout-conflicts.mlir (+7-7)
- (modified) mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir (+17-20)
- (modified) mlir/test/Dialect/XeGPU/sg-to-lane-distribute.mlir (+37-52)
- (modified) mlir/test/Dialect/XeGPU/transform-ops.mlir (+3-3)
- (modified) mlir/test/Dialect/XeGPU/xegpu-blocking.mlir (+79-79)
- (modified) mlir/test/Dialect/XeGPU/xegpu-recover-layout.mlir (+13-19)
- (modified) mlir/test/Dialect/XeGPU/xegpu-unroll-patterns.mlir (+4-4)
- (modified) mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir (+15-15)
- (modified) mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir (+23-26)
- (modified) mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir (+78-90)
- (modified) mlir/test/Integration/Dialect/XeGPU/WG/simple_gemm.mlir (+13-13)
``````````diff
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
index b1490c7742a26..652cf18ade580 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
@@ -36,6 +36,7 @@ def XeGPU_Dialect : Dialect {
let useDefaultTypePrinterParser = true;
let useDefaultAttributePrinterParser = true;
+ let useStrictPropertiesInAssemblyFormat = 1;
let extraClassDeclaration = [{
/// Checks if the given memref type represents shared local memory (SLM).
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
index 49b98922cee4c..a643e21b947e0 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
@@ -1010,11 +1010,12 @@ def XeGPU_DpasOp : XeGPU_Op<"dpas", [Pure, AllElementTypesMatch<["lhs", "rhs"]>,
Example 1 (Workgroup level, 2D):
```mlir
- %d = xegpu.dpas %a, %b, %c <{
- layout_a = #xegpu.layout<sg_layout = [4, 8], sg_data = [16, 128]>,
- layout_b = #xegpu.layout<sg_layout = [4, 8], sg_data = [128, 16]>,
- layout_cd = #xegpu.layout<sg_layout = [4, 8], sg_data = [16, 16]>}
- : vector<64x128xf16>, vector<128x128xf16>, vector<64x128xf32> -> vector<64x128xf32>
+ %d = xegpu.dpas %a, %b, %c
+ layout_a(#xegpu.layout<sg_layout = [4, 8], sg_data = [16, 128]>)
+ layout_b(#xegpu.layout<sg_layout = [4, 8], sg_data = [128, 16]>)
+ layout_cd(#xegpu.layout<sg_layout = [4, 8], sg_data = [16, 16]>)
+ : vector<64x128xf16>, vector<128x128xf16>, vector<64x128xf32>
+ -> vector<64x128xf32>
```
Example 2 (Lane level, 1D):
@@ -1077,7 +1078,12 @@ def XeGPU_DpasOp : XeGPU_Op<"dpas", [Pure, AllElementTypesMatch<["lhs", "rhs"]>,
}];
let assemblyFormat = [{
- $lhs `,` $rhs (`,` $acc^)? attr-dict `:` type($lhs)`,` type($rhs) (`,` type($acc)^)? `->` type($result)
+ $lhs `,` $rhs (`,` $acc^)?
+ (`layout_a` `(` $layout_a^ `)`)?
+ (`layout_b` `(` $layout_b^ `)`)?
+ (`layout_cd` `(` $layout_cd^ `)`)?
+ attr-dict `:`
+ type($lhs)`,` type($rhs) (`,` type($acc)^)? `->` type($result)
}];
let hasVerifier = 1;
@@ -1141,7 +1147,9 @@ def XeGPU_AtomicRMWOp: XeGPU_Op<"atomic_rmw", [Pure,
let results = (outs XeGPU_ValueType:$result);
let assemblyFormat = [{
- $kind $tensorDesc `,` $mask `,` $value attr-dict `:`
+ $kind $tensorDesc `,` $mask `,` $value
+ (`layout` `(` $layout^ `)`)?
+ attr-dict `:`
qualified(type($tensorDesc)) `,` type($mask) `,` type($value) `->` type($result)
}];
}
@@ -1678,7 +1686,7 @@ def XeGPU_DpasMxOp : XeGPU_Op<"dpas_mx", [Pure, AttrSizedOperandSegments,
$a `,` $b (`,` $acc^)?
(`scale_a` `=` $scale_a^)?
(`scale_b` `=` $scale_b^)?
- attr-dict `:` functional-type(operands, results)
+ prop-dict attr-dict `:` functional-type(operands, results)
}];
let hasVerifier = 1;
}
diff --git a/mlir/test/Conversion/XeGPUToXeVM/loadstore_matrix.mlir b/mlir/test/Conversion/XeGPUToXeVM/loadstore_matrix.mlir
index 07fb09fa2c24b..b7b8ab8c393e5 100644
--- a/mlir/test/Conversion/XeGPUToXeVM/loadstore_matrix.mlir
+++ b/mlir/test/Conversion/XeGPUToXeVM/loadstore_matrix.mlir
@@ -262,12 +262,12 @@ gpu.module @test_kernel [#xevm.target<chip = "pvc">] {
%c16 = arith.constant 16 : index
%c48 = arith.constant 48 : index
- %1 = xegpu.load_matrix %0[%c16, %c48] {subgroup_block_io}: !xegpu.mem_desc<32x64xf16, #xegpu.mem_layout<block = [16, 16]>>, index, index -> vector<8xf16>
+ %1 = xegpu.load_matrix %0[%c16, %c48] <{subgroup_block_io}>: !xegpu.mem_desc<32x64xf16, #xegpu.mem_layout<block = [16, 16]>>, index, index -> vector<8xf16>
//CHECK: %[[storeDataI16:.*]] = vector.bitcast %[[loaded]] : vector<8xf16> to vector<8xi16>
//CHECK: xevm.blockstore %[[ptr2:.*]], %[[storeDataI16]] : (!llvm.ptr<3>, vector<8xi16>)
- xegpu.store_matrix %1, %0[%c16, %c48] {subgroup_block_io}: vector<8xf16>, !xegpu.mem_desc<32x64xf16, #xegpu.mem_layout<block = [16, 16]>>, index, index
+ xegpu.store_matrix %1, %0[%c16, %c48] <{subgroup_block_io}>: vector<8xf16>, !xegpu.mem_desc<32x64xf16, #xegpu.mem_layout<block = [16, 16]>>, index, index
gpu.return %1: vector<8xf16>
}
diff --git a/mlir/test/Dialect/XeGPU/invalid.mlir b/mlir/test/Dialect/XeGPU/invalid.mlir
index dc68f5136b4a9..93e4ecd1d88f4 100644
--- a/mlir/test/Dialect/XeGPU/invalid.mlir
+++ b/mlir/test/Dialect/XeGPU/invalid.mlir
@@ -482,7 +482,7 @@ func.func @layout_rank_mismatch_sg_lane(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{expected sg_layout and lane_layout to have the same rank}}
- {layout = #xegpu.layout<sg_layout = [1, 1, 1], sg_data = [16, 2, 1], lane_layout = [8, 1], lane_data = [1, 2]>}
+ <{layout = #xegpu.layout<sg_layout = [1, 1, 1], sg_data = [16, 2, 1], lane_layout = [8, 1], lane_data = [1, 2]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -493,7 +493,7 @@ func.func @layout_rank_mismatch_sg_inst(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{expected sg_layout and inst_data to have the same rank}}
- {layout = #xegpu.layout<sg_layout = [1, 1, 1], sg_data = [16, 2, 1], inst_data = [16, 2]>}
+ <{layout = #xegpu.layout<sg_layout = [1, 1, 1], sg_data = [16, 2, 1], inst_data = [16, 2]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -504,7 +504,7 @@ func.func @layout_rank_mismatch_inst_lane(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{expected inst_data and lane_layout to have the same rank}}
- {layout = #xegpu.layout<inst_data = [16, 2, 1], lane_layout = [8, 1], lane_data = [1, 2]>}
+ <{layout = #xegpu.layout<inst_data = [16, 2, 1], lane_layout = [8, 1], lane_data = [1, 2]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -515,7 +515,7 @@ func.func @layout_rank_mismatch_lane_data(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{expected lane_data and lane_layout to have the same rank}}
- {layout = #xegpu.layout<inst_data = [16, 2], lane_layout = [8, 1], lane_data = [1, 2, 1]>}
+ <{layout = #xegpu.layout<inst_data = [16, 2], lane_layout = [8, 1], lane_data = [1, 2, 1]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -526,7 +526,7 @@ func.func @layout_rank_mismatch_sg_data(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{expected sg_data and sg_layout to have the same rank}}
- {layout = #xegpu.layout<sg_layout = [1, 1], sg_data = [16, 2, 1], inst_data = [16, 2]>}
+ <{layout = #xegpu.layout<sg_layout = [1, 1], sg_data = [16, 2, 1], inst_data = [16, 2]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -546,7 +546,7 @@ func.func @layout_sg_data_missing(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{sg_layout and sg_data must be used together}}
- {layout = #xegpu.layout<sg_layout = [2, 1], lane_layout = [8, 1], lane_data = [1, 2]>}
+ <{layout = #xegpu.layout<sg_layout = [2, 1], lane_layout = [8, 1], lane_data = [1, 2]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -557,7 +557,7 @@ func.func @layout_lane_data_missing(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{lane_layout and lane_data must be used together}}
- {layout = #xegpu.layout<inst_data = [16, 2], lane_layout = [16, 1]>}
+ <{layout = #xegpu.layout<inst_data = [16, 2], lane_layout = [16, 1]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -568,7 +568,7 @@ func.func @layout_order_without_layout(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{expected sg_layout/lane_layout being used with order}}
- {layout = #xegpu.layout<inst_data = [16, 2], order = [0, 1]>}
+ <{layout = #xegpu.layout<inst_data = [16, 2], order = [0, 1]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -579,7 +579,7 @@ func.func @layout_order_rank_mismatch_sg(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{expected order and sg_layout to have the same rank}}
- {layout = #xegpu.layout<sg_layout = [1, 1], sg_data = [16, 2], order = [0, 1, 2]>}
+ <{layout = #xegpu.layout<sg_layout = [1, 1], sg_data = [16, 2], order = [0, 1, 2]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -590,7 +590,7 @@ func.func @layout_order_rank_mismatch_lane(%src: memref<?xf32>) {
%mask = arith.constant dense<1>: vector<4xi1>
%2 = xegpu.load %src[%offsets], %mask
// expected-error at below {{expected order and lane_layout to have the same rank}}
- {layout = #xegpu.layout<lane_layout = [8, 1], lane_data = [1, 2], order = [0, 1, 2]>}
+ <{layout = #xegpu.layout<lane_layout = [8, 1], lane_data = [1, 2], order = [0, 1, 2]>}>
: memref<?xf32>, vector<4xindex>, vector<4xi1> -> vector<4xf32>
return
}
@@ -665,7 +665,7 @@ func.func @store_mem_desc_1d_exceeds_shape(%arg0: !xegpu.mem_desc<16xf16>, %arg1
// -----
func.func @simt_store_matrix_vector_nonlinear(%arg0: !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [32, 1]>>, %arg1: vector<2x16xf32>) {
// expected-error at +1 {{With subgroup_block_io, accessed data must be contiguous and coalesced}}
- xegpu.store_matrix %arg1, %arg0[0, 0] {subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [2, 1]>} :
+ xegpu.store_matrix %arg1, %arg0[0, 0] <{subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [2, 1]>}> :
vector<2x16xf32>, !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [32, 1]>>
return
}
@@ -673,7 +673,7 @@ func.func @simt_store_matrix_vector_nonlinear(%arg0: !xegpu.mem_desc<32x32xf32,
// -----
func.func @simt_store_matrix_vector_noncoalesced(%arg0: !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [1, 32], block = [1, 16]>>, %arg1: vector<16x2xf32>) {
// expected-error at +1 {{With subgroup_block_io, the distributed dimensions must be contiguous}}
- xegpu.store_matrix %arg1, %arg0[0, 0] {subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 2]>} :
+ xegpu.store_matrix %arg1, %arg0[0, 0] <{subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 2]>}> :
vector<16x2xf32>, !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [1, 32], block = [1, 16]>>
return
}
@@ -681,7 +681,7 @@ func.func @simt_store_matrix_vector_noncoalesced(%arg0: !xegpu.mem_desc<32x32xf3
// -----
func.func @simt_store_matrix_vector_noncoalesced(%arg0: !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [32, 1], block = [1, 17]>>, %arg1: vector<16x2xf32>) {
// expected-error at +1 {{With subgroup_block_io, the block shape must match the lane layout}}
- xegpu.store_matrix %arg1, %arg0[0, 0] {subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>} :
+ xegpu.store_matrix %arg1, %arg0[0, 0] <{subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>}> :
vector<16x2xf32>, !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [32, 1], block = [1, 17]>>
return
}
@@ -777,7 +777,7 @@ func.func @dpas_mx_scale_k_mismatch(%a : vector<8x16xf8E5M2>, %b: vector<16x16xf
#layout_cd = #xegpu.layout<sg_layout = [1, 1], sg_data = [8, 16]>
func.func @dpas_mx_layout_not_distributable(%a : vector<8x16xf8E5M2>, %b: vector<16x16xf8E5M2>) {
// expected-error at +1 {{A shape is not distributable with the layout}}
- %1 = xegpu.dpas_mx %a, %b {layout_a = #layout_a, layout_b = #layout_b, layout_cd = #layout_cd} : (vector<8x16xf8E5M2>, vector<16x16xf8E5M2>) -> vector<8x16xf32>
+ %1 = xegpu.dpas_mx %a, %b <{layout_a = #layout_a, layout_b = #layout_b, layout_cd = #layout_cd}> : (vector<8x16xf8E5M2>, vector<16x16xf8E5M2>) -> vector<8x16xf32>
return
}
@@ -785,7 +785,7 @@ func.func @dpas_mx_layout_not_distributable(%a : vector<8x16xf8E5M2>, %b: vector
#layout_a_scale_invalid = #xegpu.layout<sg_layout = [1, 1], sg_data = [5, 3]>
func.func @dpas_mx_scale_a_layout_not_distributable(%a : vector<8x16xf8E5M2>, %b: vector<16x16xf8E5M2>, %acc: vector<8x16xf32>, %scale_a_val: vector<8x2xf8E8M0FNU>) {
// expected-error at +1 {{ScaleA shape is not distributable with the layout}}
- %1 = xegpu.dpas_mx %a, %b, %acc scale_a = %scale_a_val {layout_a_scale = #layout_a_scale_invalid} : (vector<8x16xf8E5M2>, vector<16x16xf8E5M2>, vector<8x16xf32>, vector<8x2xf8E8M0FNU>) -> vector<8x16xf32>
+ %1 = xegpu.dpas_mx %a, %b, %acc scale_a = %scale_a_val <{layout_a_scale = #layout_a_scale_invalid}> : (vector<8x16xf8E5M2>, vector<16x16xf8E5M2>, vector<8x16xf32>, vector<8x2xf8E8M0FNU>) -> vector<8x16xf32>
return
}
@@ -793,7 +793,7 @@ func.func @dpas_mx_scale_a_layout_not_distributable(%a : vector<8x16xf8E5M2>, %b
#layout_b_scale_invalid = #xegpu.layout<sg_layout = [1, 1], sg_data = [3, 11]>
func.func @dpas_mx_scale_b_layout_not_distributable(%a : vector<8x16xf8E5M2>, %b: vector<16x16xf8E5M2>, %acc: vector<8x16xf32>, %scale_a_val: vector<8x2xf8E8M0FNU>, %scale_b_val: vector<2x16xf8E8M0FNU>) {
// expected-error at +1 {{ScaleB shape is not distributable with the layout}}
- %1 = xegpu.dpas_mx %a, %b, %acc scale_a = %scale_a_val scale_b = %scale_b_val {layout_b_scale = #layout_b_scale_invalid} : (vector<8x16xf8E5M2>, vector<16x16xf8E5M2>, vector<8x16xf32>, vector<8x2xf8E8M0FNU>, vector<2x16xf8E8M0FNU>) -> vector<8x16xf32>
+ %1 = xegpu.dpas_mx %a, %b, %acc scale_a = %scale_a_val scale_b = %scale_b_val <{layout_b_scale = #layout_b_scale_invalid}> : (vector<8x16xf8E5M2>, vector<16x16xf8E5M2>, vector<8x16xf32>, vector<8x2xf8E8M0FNU>, vector<2x16xf8E8M0FNU>) -> vector<8x16xf32>
return
}
diff --git a/mlir/test/Dialect/XeGPU/peephole-optimize.mlir b/mlir/test/Dialect/XeGPU/peephole-optimize.mlir
index fa5ff9ca56d34..cb1430d815e85 100644
--- a/mlir/test/Dialect/XeGPU/peephole-optimize.mlir
+++ b/mlir/test/Dialect/XeGPU/peephole-optimize.mlir
@@ -10,7 +10,7 @@
// CHECK: %[[BDESC:.*]] = xegpu.create_nd_tdesc %[[T0]], shape : [64, %[[C32]]], strides : [%[[C32]], 1] : i64
// CHECK-SAME: -> !xegpu.tensor_desc<16x8xi32, #xegpu.layout<lane_layout = [16, 1], lane_data = [1, 1], order = [0, 1]>>
// CHECK-NEXT: %[[B:.*]] = xegpu.load_nd %[[BDESC]][%{{.*}}, %[[C16]]]
-// CHECK-SAME: {layout = #xegpu.layout<lane_layout = [16, 1], lane_data = [1, 1], order = [0, 1]>}
+// CHECK-SAME: <{layout = #xegpu.layout<lane_layout = [16, 1], lane_data = [1, 1], order = [0, 1]>}>
// CHECK-SAME: : !xegpu.tensor_desc<16x8xi32, #xegpu.layout<lane_layout = [16, 1], lane_data = [1, 1], order = [0, 1]>>
// CHECK-SAME: -> vector<16x8xi32>
// CHECK: %[[BITCAST:.*]] = vector.bitcast %[[B]] : vector<16x8xi32> to vector<16x16xf16>
@@ -38,7 +38,7 @@ gpu.func @no_scf(%arg0: memref<64x64xf16>, %arg1: vector<8x16xf16>) -> vector<8x
// CHECK: %[[T1:.*]] = xegpu.create_nd_tdesc %[[T0]], shape : [64, %[[C16]]], strides : [%[[C16]], 1] : i64
// CHECK-SAME: -> !xegpu.tensor_desc<16x8xi32, #xegpu.layout<lane_layout = [16, 1], lane_data = [1, 1], order = [0, 1]>>
// CHECK: %[[T2:.*]] = xegpu.load_nd %[[T1]][%{{.*}}, %[[C16]]]
-// CHECK-SAME: {layout = #xegpu.layout<lane_layout = [16, 1], lane_data = [1, 1], order = [0, 1]>}
+// CHECK-SAME: <{layout = #xegpu.layout<lane_layout = [16, 1], lane_data = [1, 1], order = [0, 1]>}>
// CHECK-SAME: : !xegpu.tensor_desc<16x8xi32, #xegpu.layout<lane_layout = [16, 1], lane_data = [1, 1], order = [0, 1]>> -> vector<16x8xi32>
// CHECK: %[[T3:.*]] = vector.bitcast %[[T2]] : vector<16x8xi32> to vector<16x32xi8>
#a = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 2]>
@@ -284,12 +284,12 @@ gpu.func @array_length(%arg0: vector<8x16xf16>, %arg1: memref<256x256xf16>, %arg
%c32 = arith.constant 32 : index
%c256 = arith.constant 256 : index
%0 = xegpu.create_nd_tdesc %arg2 : memref<256x256xf32> -> !xegpu.tensor_desc<8x16xf32, #a>
- %1 = xegpu.load_nd %0[%c0, %c0] { layout = #a } : !xegpu.tensor_desc<8x16xf32, #a> -> vector<8x16xf32>
+ %1 = xegpu.load_nd %0[%c0, %c0] <{ layout = #a }> : !xegpu.tensor_desc<8x16xf32, #a> -> vector<8x16xf32>
%3 = xegpu.create_nd_tdesc %arg1 : memref<256x256xf16>
-> !xegpu.tensor_desc<32x16xf16, #b, #xegpu.block_tdesc_attr<array_length = 2 : i64>>
%4:4 = scf.for %arg3 = %c0 to %c256 step %c32 iter_args(%arg4 = %1, %arg5 = %1, %arg6 = %1, %arg7 = %1)
-> (vector<8x16xf32>, vector<8x16xf32>, vector<8x16xf32>, vector<8x16xf32>) {
- %6 = xegpu.load_nd %3[%c0, %arg3] { layout = #b }
+ %6 = xegpu.load_nd %3[%c0, %arg3] <{ layout = #b }>
: !xegpu.tensor_desc<32x16xf16, #b, #xegpu.block_tdesc_attr<array_length = 2 : i64>> -> vector<2x32x16xf16>
%19 = vector.extract %6[0] { layout_result_0 = #b } : vector<32x16xf16> from vector<2x32x16xf16>
%20 = vector.extract %6[1] { layout_result_0 = #b } : vector<32x16xf16> from vector<2x32x16xf16>
@@ -377,7 +377,7 @@ gpu.module @xevm_test {
%offset = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<0> : vector<16xindex>
%mask = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<1> : vector<16xi1>
- xegpu.store %reduce_bcast, %dst[%offset], %mask {layout = #xegpu.slice<#xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>, dims = [0]>} : vector<16xf32>, memref<256xf32>, vector<16xindex>, vector<16xi1>
+ xegpu.store %reduce_bcast, %dst[%offset], %mask <{layout = #xegpu.slice<#xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>, dims = [0]>}> : vector<16xf32>, memref<256xf32>, vector<16xindex>, vector<16xi1>
gpu.return
}
}
@@ -418,7 +418,7 @@ gpu.module @xevm_test {
%offset = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<0> : vector<16xindex>
%mask = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<1> : vector<16xi1>
- xegpu.store %reduce_bcast, %dst[%offset], %mask {layout = #xegpu.layout<lane_layout = [16], lane_data = [1]>} : vector<16xf32>, memref<256xf32>, vector<16xindex>, vector<16xi1>
+ xegpu.store %reduce_bcast, %dst[%offset], %mask <{layout = #xegpu.layout<lane_layout = [16], lane_data = [1]>}> : vector<16xf32>, memref<256xf32>, vector<16xindex>, vector<16xi1>
gpu.return
}
}
@@ -457,7 +457,7 @@ gpu.module @xevm_test {
%offset = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<0> : vector<16xindex>
%mask = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<1> : vector<16xi1>
- xegpu.store %reduce_bcast, %dst[%offset], %mask {layout = #xegpu.slice<#xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>, dims = [0]>} : vector<16xf32>, memref<256xf32>, vector<16xindex>, vector<16xi1>
+ xegpu.store %reduce_bcast, %dst[%offset], %mask <{layout = #xegpu.slice<#xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>, dims = [0]>}> : vector<16xf32>, memref<256xf32>, vector<16xindex>, vector<16xi1>
gpu.return
}
}
@@ -500,7 +500,7 @@ gpu.module @xevm_test {
%offset = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<0> : vector<16xindex>
%mask = arith.constant {layout_result_0 = #xegpu.layout<lane_layout = [16], lane_data = [1]>} dense<1> : vector<16xi1>
- xegpu.store %reduce_bcast, %dst[%offset], %...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/217281
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