[Mlir-commits] [mlir] [mlir][x86] Fix - Instrincs selection for hf8 and bf8. (PR #216647)

[Arun Thangamani]

https://github.com/arun-thmn created https://github.com/llvm/llvm-project/pull/216647

This patch fixes the error instrincs selection for `bf8` and `hf8` types.

- Intel AMX naming: `bf8 == E5M2`, `hf8 == E4M3FN`.

>From a6a208e7a293d666a7301a32745b8bd1f4c3f450 Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Sun, 16 Aug 2026 23:53:44 -0700
Subject: [PATCH] fix the llvm instrincs selection for hf8 and bf8.

---
 mlir/include/mlir/Dialect/X86/X86.td             | 4 ++--
 mlir/test/Dialect/X86/AMX/legalize-for-llvm.mlir | 8 ++++----
 mlir/test/Target/LLVMIR/amx.mlir                 | 6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/mlir/include/mlir/Dialect/X86/X86.td b/mlir/include/mlir/Dialect/X86/X86.td
index a152b5e7ae6db..20a0695126d4e 100644
--- a/mlir/include/mlir/Dialect/X86/X86.td
+++ b/mlir/include/mlir/Dialect/X86/X86.td
@@ -1005,9 +1005,9 @@ def TileMulFOp : AMX_Op<"tile_mulf", [Pure,
       } else if (elementType.isBF16()) {
         intr += "bf16";
       } else if (elementType.isF8E4M3FN() || elementType.isF8E5M2()) {
-        intr += elementType.isF8E4M3FN() ? "b" : "h";
+        intr += elementType.isF8E4M3FN() ? "h" : "b";
         if (elementType != elementTypeRhs)
-          intr += elementTypeRhs.isF8E4M3FN() ? "b" : "h";
+          intr += elementTypeRhs.isF8E4M3FN() ? "h" : "b";
         intr += "f8";
       }
 
diff --git a/mlir/test/Dialect/X86/AMX/legalize-for-llvm.mlir b/mlir/test/Dialect/X86/AMX/legalize-for-llvm.mlir
index 3b45135be35a7..a88a3b6b994c1 100644
--- a/mlir/test/Dialect/X86/AMX/legalize-for-llvm.mlir
+++ b/mlir/test/Dialect/X86/AMX/legalize-for-llvm.mlir
@@ -64,7 +64,7 @@ func.func @mulfp16(%arg0: memref<?x?xf16>, %arg1: memref<?x?xf32>) {
 // CHECK: llvm.call_intrinsic "llvm.x86.tilezero.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tileloadd64.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tileloadd64.internal"
-// CHECK: llvm.call_intrinsic "llvm.x86.tdpbf8ps.internal"
+// CHECK: llvm.call_intrinsic "llvm.x86.tdphf8ps.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tilestored64.internal"
 func.func @mulf8E4M3FN(%arg0: memref<?x?xf8E4M3FN>, %arg1: memref<?x?xf32>) {
   %0 = arith.constant 0 : index
@@ -80,7 +80,7 @@ func.func @mulf8E4M3FN(%arg0: memref<?x?xf8E4M3FN>, %arg1: memref<?x?xf32>) {
 // CHECK: llvm.call_intrinsic "llvm.x86.tilezero.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tileloadd64.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tileloadd64.internal"
-// CHECK: llvm.call_intrinsic "llvm.x86.tdpbhf8ps.internal"
+// CHECK: llvm.call_intrinsic "llvm.x86.tdphbf8ps.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tilestored64.internal"
 func.func @mulf8E4M3FNxf8E5M2(%arg0: memref<?x?xf8E5M2>, %arg1: memref<?x?xf32>) {
   %0 = arith.constant 0 : index
@@ -96,7 +96,7 @@ func.func @mulf8E4M3FNxf8E5M2(%arg0: memref<?x?xf8E5M2>, %arg1: memref<?x?xf32>)
 // CHECK: llvm.call_intrinsic "llvm.x86.tilezero.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tileloadd64.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tileloadd64.internal"
-// CHECK: llvm.call_intrinsic "llvm.x86.tdphbf8ps.internal"
+// CHECK: llvm.call_intrinsic "llvm.x86.tdpbhf8ps.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tilestored64.internal"
 func.func @mulf8E5M2xf8E4M3FN(%arg0: memref<?x?xf8E4M3FN>, %arg1: memref<?x?xf32>) {
   %0 = arith.constant 0 : index
@@ -112,7 +112,7 @@ func.func @mulf8E5M2xf8E4M3FN(%arg0: memref<?x?xf8E4M3FN>, %arg1: memref<?x?xf32
 // CHECK: llvm.call_intrinsic "llvm.x86.tilezero.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tileloadd64.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tileloadd64.internal"
-// CHECK: llvm.call_intrinsic "llvm.x86.tdphf8ps.internal"
+// CHECK: llvm.call_intrinsic "llvm.x86.tdpbf8ps.internal"
 // CHECK: llvm.call_intrinsic "llvm.x86.tilestored64.internal"
 func.func @mulf8E5M2(%arg0: memref<?x?xf8E5M2>, %arg1: memref<?x?xf32>) {
   %0 = arith.constant 0 : index
diff --git a/mlir/test/Target/LLVMIR/amx.mlir b/mlir/test/Target/LLVMIR/amx.mlir
index be74dc199af72..f41fc59cccd16 100644
--- a/mlir/test/Target/LLVMIR/amx.mlir
+++ b/mlir/test/Target/LLVMIR/amx.mlir
@@ -86,10 +86,10 @@ func.func @amx_tile_mulf_f8(
   %tB = x86.amx.tile_load %matB[%idx, %idx] : memref<?x?xf8E5M2> into !x86.amx.tile<16x64xf8E5M2>
   %tA1 = x86.amx.tile_load %matA[%c0, %c0] : memref<?x?xf8E4M3FN> into !x86.amx.tile<16x64xf8E4M3FN>
   %tB1 = x86.amx.tile_load %matB[%c0, %c0] : memref<?x?xf8E5M2> into !x86.amx.tile<16x64xf8E5M2>
-  // CHECK: call x86_amx @llvm.x86.tdpbf8ps.internal
-  // CHECK: call x86_amx @llvm.x86.tdpbhf8ps.internal
-  // CHECK: call x86_amx @llvm.x86.tdphbf8ps.internal
   // CHECK: call x86_amx @llvm.x86.tdphf8ps.internal
+  // CHECK: call x86_amx @llvm.x86.tdphbf8ps.internal
+  // CHECK: call x86_amx @llvm.x86.tdpbhf8ps.internal
+  // CHECK: call x86_amx @llvm.x86.tdpbf8ps.internal
   %tRes = x86.amx.tile_mulf %tA, %tA1, %acc
     : !x86.amx.tile<16x64xf8E4M3FN>, !x86.amx.tile<16x64xf8E4M3FN>, !x86.amx.tile<16x16xf32>
   %tRes1 = x86.amx.tile_mulf %tA, %tB, %acc