[Mlir-commits] [llvm] [mlir] [NVPTX] Add "exclusive" intrinsic variants for tcgen05.alloc/dealloc (PR #216016)

[Dharuni R Acharya]

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@@ -4977,17 +4977,12 @@ Tcgen05AllocOp::getIntrinsicIDAndArgs(Operation &op,
   auto curOp = cast<NVVM::Tcgen05AllocOp>(op);
   unsigned as = llvm::cast<LLVM::LLVMPointerType>(curOp.getAddr().getType())
                     .getAddressSpace();
-  bool isShared = as == NVVMMemorySpace::Shared;
+  assert((as == NVVMMemorySpace::Generic || as == NVVMMemorySpace::Shared) &&
+         "expected generic or shared memory address");
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DharuniRAcharya wrote:

Yes, you are right! Removed `assert` in the latest revision!

https://github.com/llvm/llvm-project/pull/216016