[Mlir-commits] [llvm] [mlir] [NVPTX] Add "exclusive" intrinsic variants for tcgen05.alloc/dealloc (PR #216016)

[Rajat Bajpai]

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@@ -2616,24 +2616,27 @@ For more information on tensor-memory load/store instructions, refer to [PTX ISA
 ##### Syntax:
 
 ```llvm
-declare void @llvm.nvvm.tcgen05.alloc.cg1(ptr %dst, i32 %ncols)
-declare void @llvm.nvvm.tcgen05.alloc.cg2(ptr %dst, i32 %ncols)
-declare void @llvm.nvvm.tcgen05.alloc.shared.cg1(ptr addrspace(3) %dst, i32 %ncols)
-declare void @llvm.nvvm.tcgen05.alloc.shared.cg2(ptr addrspace(3) %dst, i32 %ncols)
+declare void @llvm.nvvm.tcgen05.alloc.{cg1,cg2}.p0(ptr %dst, i32 %ncols)
+declare void @llvm.nvvm.tcgen05.alloc.{cg1,cg2}.p3(ptr addrspace(3) %dst, i32 %ncols)
+
+declare void @llvm.nvvm.tcgen05.alloc.exclusive.{cg1,cg2}.p0(ptr %dst, i32 %ncols)
+declare void @llvm.nvvm.tcgen05.alloc.exclusive.{cg1,cg2}.p3(ptr addrspace(3) %dst, i32 %ncols)
 ```
 
 ##### Overview:
 
 The '`@llvm.nvvm.tcgen05.alloc.*`' intrinsics correspond to the
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rajatbajpai wrote:

`@llvm.nvvm.tcgen05.alloc.*` => `@llvm.nvvm.tcgen05.alloc{.exclusive}.*`?

https://github.com/llvm/llvm-project/pull/216016