[Mlir-commits] [mlir] 4cd50b4 - [mlir][ArmSME] Enable native ArmSME integration testing on Darwin (#215296)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Thu Aug 13 23:46:40 PDT 2026
Author: Federico Bruzzone
Date: 2026-08-14T08:46:36+02:00
New Revision: 4cd50b42362ab4dd7a59246b7d34a609df12bca2
URL: https://github.com/llvm/llvm-project/commit/4cd50b42362ab4dd7a59246b7d34a609df12bca2
DIFF: https://github.com/llvm/llvm-project/commit/4cd50b42362ab4dd7a59246b7d34a609df12bca2.diff
LOG: [mlir][ArmSME] Enable native ArmSME integration testing on Darwin (#215296)
`MLIR_RUN_ARM_SME_TESTS=ON` could not exercise ArmSME integration tests
on real Apple Silicon SME hardware:
1. `check_hwcap` only detects CPU features via Linux's
`getauxval()`/`hwcap.h`, so it always required an emulator on Darwin,
even with real SME hardware present.
2. With `+sve` enabled, LLVM lowers `vector.vscale` to a bare
`cntd`/`cntb`, illegal outside streaming mode. Apple Silicon doesn't
expose base (non-streaming) SVE at EL0, so this traps (see #204853).
3. Some functions computing `vector.vscale` directly had no (or an
incorrectly unprefixed) streaming attribute, which is required for legal
`vscale` codegen and is silently dropped during `func.func` to
`llvm.func` conversion unless `llvm.`-prefixed (see #190864).
4. 6 tests force a specific streaming vector length via
`setArmSVLBits`/`setArmVLBits`, which isn't possible on real hardware
(SVL is fixed per core).
**Changes**
- Add `check_hwcap_darwin` (`sysctl`-based), used by `check_hwcap` on
Darwin.
- Drop `+sve` from the mattr of the 15 tests that don't need it.
`FeatureSME` doesn't imply `FeatureSVE`, so `-mattr=+sme` is enough.
- Add `attributes {llvm.arm_streaming}` / `{llvm.arm_locally_streaming}`
to the functions in `pack-unpack-mmt4d.mlir`,
`load-store-128-bit-tile.mlir`, and `ssve.mlir` that compute
`vector.vscale` directly.
- Mark the 6 VL-forcing tests `REQUIRES: arm-emulator`, matching the
existing tag on `test-setArmSVLBits.mlir`.
---
Verified on an M4 Pro: **16/22** ArmSME integration tests pass natively,
**6** correctly skip without an emulator, **0** are XFAIL.
I leveraged AI to work on this PR.
---------
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Added:
Modified:
mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
Removed:
################################################################################
diff --git a/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake b/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
index 7bc13287cd655..3aea591d885f7 100644
--- a/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
+++ b/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
@@ -1,6 +1,31 @@
# A collection of helper CMake functions to detect hardware capabilities. At
# the moment these are used when configuring MLIR integration tests.
+# Checks whether SME is supported by the host Darwin (macOS) system. This is
+# implemented via `sysctl`, since Darwin has no equivalent of Linux's
+# auxiliary vector feature bits (hwcap).
+#
+# check_sme_support_on_darwin(
+# output_var
+# )
+function(check_sme_support_on_darwin output)
+ execute_process(
+ COMMAND sysctl -n hw.optional.arm.FEAT_SME
+ OUTPUT_VARIABLE sysctl_output
+ OUTPUT_STRIP_TRAILING_WHITESPACE
+ ERROR_QUIET
+ RESULT_VARIABLE sysctl_result
+ )
+
+ if(sysctl_result EQUAL 0 AND sysctl_output STREQUAL "1")
+ set(local_result TRUE)
+ else()
+ set(local_result FALSE)
+ endif()
+ message(STATUS "Checking whether SME is supported by the host system (via sysctl hw.optional.arm.FEAT_SME): ${local_result}")
+ set(${output} ${local_result} PARENT_SCOPE)
+endfunction(check_sme_support_on_darwin)
+
# Checks whether the specified hardware capability is supported by the host
# Linux system. This is implemented by checking auxiliary vector feature
# provided by the Linux kernel.
@@ -88,7 +113,16 @@ function(check_emulator mlir_e2e_tests hwcap_spec emulator_exec)
return()
endif()
- check_hwcap(${hwcap_spec} emulator_not_required)
+ if(APPLE AND hwcap_spec STREQUAL "HWCAP2_SME")
+ check_sme_support_on_darwin(emulator_not_required)
+ elseif(APPLE)
+ # No Darwin mapping for anything other than SME (yet); conservatively
+ # assume an emulator is required.
+ set(emulator_not_required FALSE)
+ else()
+ check_hwcap(${hwcap_spec} emulator_not_required)
+ endif()
+
if (${emulator_not_required})
return()
endif()
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
index ed4342b7d50af..f323070157ceb 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
@@ -5,7 +5,7 @@
// RUN: -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=entry -entry-point-result=void \
-// RUN: -march=aarch64 -mattr="+sve,+sme" \
+// RUN: -march=aarch64 -mattr="+sme" \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
index d26853d14aec7..ba8e59ae779f5 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
@@ -4,7 +4,7 @@
// RUN: -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=main -entry-point-result=void \
-// RUN: -march=aarch64 -mattr="+sve,+sme" \
+// RUN: -march=aarch64 -mattr="+sme" \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
index 147ab7401c5cf..4f6202b7d3b5b 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
@@ -3,7 +3,7 @@
// RUN: -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=main -entry-point-result=void \
-// RUN: -march=aarch64 -mattr="+sve,+sme" \
+// RUN: -march=aarch64 -mattr="+sme" \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
index caa4d318f5f06..7b2fbd57d7b1b 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// RUN: mlir-opt %s \
// RUN: -transform-interpreter -test-transform-dialect-erase-schedule \
// RUN: -one-shot-bufferize="bufferize-function-boundaries" -canonicalize \
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
index 207d29858be52..1f364ea325b41 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// RUN: mlir-opt %s \
// RUN: -transform-interpreter -test-transform-dialect-erase-schedule \
// RUN: -one-shot-bufferize="bufferize-function-boundaries" -canonicalize \
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
index 73e286f960008..eb1e7a87d932f 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
@@ -123,7 +123,7 @@ func.func private @matmul(%A: tensor<7x16xf32>, %B: tensor<16x13xf32>, %C: tenso
// Implements packing for the A matrix (LHS) in matrix multiplication. The
// inner tile size for dim M is "scalable": 8 * vscale.
//===----------------------------------------------------------------------===//
-func.func private @pack_lhs(%A: tensor<7x16xf32>) -> tensor<1x16x?x1xf32> {
+func.func private @pack_lhs(%A: tensor<7x16xf32>) -> tensor<1x16x?x1xf32> attributes {llvm.arm_streaming} {
%pad = arith.constant 0.0 : f32
%vs = vector.vscale
@@ -146,7 +146,7 @@ func.func private @pack_lhs(%A: tensor<7x16xf32>) -> tensor<1x16x?x1xf32> {
// Implements packing for the B matrix (RHS) in matrix multiplication. The
// inner tile size for dim N is "scalable": 8 * vscale.
//===----------------------------------------------------------------------===//
-func.func private @pack_rhs(%B: tensor<16x13xf32>) -> tensor<?x16x?x1xf32> {
+func.func private @pack_rhs(%B: tensor<16x13xf32>) -> tensor<?x16x?x1xf32> attributes {llvm.arm_streaming} {
%pad = arith.constant 0.0 : f32
// Compute the outer tile size.
@@ -173,7 +173,7 @@ func.func private @pack_rhs(%B: tensor<16x13xf32>) -> tensor<?x16x?x1xf32> {
// Implements packing for the C matrix (accumulator) in matrix multiplication.
// The inner tile sizes are "scalable": 8 * vscale, 8 * vscale
//===----------------------------------------------------------------------===//
-func.func private @pack_acc(%C: tensor<7x13xf32>) -> tensor<1x?x?x?xf32> {
+func.func private @pack_acc(%C: tensor<7x13xf32>) -> tensor<1x?x?x?xf32> attributes {llvm.arm_streaming} {
%pad = arith.constant 0.0 : f32
// Compute the outer tile size.
@@ -199,7 +199,7 @@ func.func private @pack_acc(%C: tensor<7x13xf32>) -> tensor<1x?x?x?xf32> {
// Implements unpacking for the C matrix (accumulator) in matrix
// multiplication. The inner tile sizes are "scalable": 8 * vscale, 8 * vscale
//===----------------------------------------------------------------------===//
-func.func private @unpack_acc(%C_packed: tensor<1x?x?x?xf32>) -> tensor<7x13xf32> {
+func.func private @unpack_acc(%C_packed: tensor<1x?x?x?xf32>) -> tensor<7x13xf32> attributes {llvm.arm_streaming} {
%vs = vector.vscale
%c8 = arith.constant 8 : index
%vs_c8 = arith.muli %vs, %c8 : index
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
index 05eee31ccc6fa..abf0f6a2740c4 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
@@ -2,7 +2,7 @@
// RUN: -test-lower-to-arm-sme -test-lower-to-llvm -verify-diagnostics | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=main -entry-point-result=void \
-// RUN: -march=aarch64 -mattr="+sve,+sme" \
+// RUN: -march=aarch64 -mattr="+sme" \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
index f4275fdde3c78..11d0df993da00 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = test_load_store_zaq0
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
@@ -24,7 +24,7 @@ func.func @vector_copy_i128(%src: memref<?x?xi128>, %dst: memref<?x?xi128>) {
return
}
-func.func @test_load_store_zaq0() {
+func.func @test_load_store_zaq0() attributes {llvm.arm_locally_streaming} {
%c0 = arith.constant 0 : index
%min_elts_q = arith.constant 1 : index
%bytes_per_128_bit = arith.constant 16 : index
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
index 8d4b4a07994e2..74726c4c62780 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
index 7f1566d635cbb..e8294c7620722 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// RUN: mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=main -entry-point-result=void \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
index 886a990125b4c..123d6bd1ed672 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// DEFINE: %{opts} =
// DEFINE: %{entry} = main
// DEFINE: %{compile} = mlir-opt %s \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
index 219367a41d51a..6320a1f33697d 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
@@ -2,7 +2,7 @@
// DEFINE: %{compile} = mlir-opt %s \
// DEFINE: -test-lower-to-arm-sme -test-lower-to-llvm -o %t
// DEFINE: %{run} = %mcr_aarch64_cmd %t \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
index 059f24adbe721..232a2449e2498 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
@@ -2,7 +2,7 @@
// DEFINE: %{compile} = mlir-opt %s \
// DEFINE: -test-lower-to-arm-sme -test-lower-to-llvm -o %t
// DEFINE: %{run} = %mcr_aarch64_cmd %t \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme-f64f64 \
+// DEFINE: -march=aarch64 -mattr=+sme,+sme-f64f64 \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
index 74ddbc63380b7..1515672057d33 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// DEFINE: %{entry} = main
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
index aa8a2aa45d65b..a3a7eaab7bd52 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=i32 \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils
@@ -10,7 +10,7 @@
// RUN: %{compile} | %{run} | FileCheck %s
// VLA memcopy in streaming mode.
-func.func @streaming_kernel_copy(%src : memref<?xi64>, %dst : memref<?xi64>, %size : index) attributes {arm_streaming} {
+func.func @streaming_kernel_copy(%src : memref<?xi64>, %dst : memref<?xi64>, %size : index) attributes {llvm.arm_streaming} {
%c0 = arith.constant 0 : index
%c2 = arith.constant 2 : index
%vscale = vector.vscale
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
index b94345c70c713..fcef062dd18ac 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
@@ -1,6 +1,6 @@
// RUN: mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
-// RUN: -march=aarch64 -mattr=+sve,+sme \
+// RUN: -march=aarch64 -mattr=+sme \
// RUN: -e entry -entry-point-result=i32 \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
index 77f5a325728b3..fa65e03abb4bc 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
index bf6900ca810c2..7d55f6036a66f 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
index 8188e66ce0662..14dc38f2a0aa1 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
index eb9988666f4e5..e4c737a8af8a6 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = za0_d_f64
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=i32 \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
index ad8e321c0c8ae..eba3b50b016e5 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=+sme \
// DEFINE: -e %{entry_point} -entry-point-result=i32 \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
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