[Mlir-commits] [llvm] [mlir] [NVPTX] Add "exclusive" intrinsic variants for tcgen05.alloc/dealloc (PR #216016)

[Dharuni R Acharya]

================
@@ -5208,7 +5208,7 @@ def NVVM_Tcgen05AllocOp : NVVM_Op<"tcgen05.alloc", [NVVMRequiresSMf<[100, 101, 1
     llvm::SmallVector<llvm::Value *> args;
     auto id = NVVM::Tcgen05AllocOp::getIntrinsicIDAndArgs(
       *op, moduleTranslation, args);
-    createIntrinsicCall(builder, id, args);
+    createIntrinsicCall(builder, id, builder.getVoidTy(), args);
----------------
DharuniRAcharya wrote:

Yes, since making `alloc` overloaded on `llvm_anyptr_ty` requires updating the corresponding MLIR selects. However, the `exclusive` support in `tcgen05.alloc/dealloc` MLIR ops will be added in a separate PR.

https://github.com/llvm/llvm-project/pull/216016