[Mlir-commits] [llvm] [mlir] [NVPTX] Add tcgen05.mma kind::ti16 for sm_107f + mxf4{nvf4} for sm_107a (PR #215624)

[Kirill Vedernikov]

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@@ -6627,7 +6631,7 @@ class Tcgen05MMAWSInst<bit IsSparse, string ASpace, string Kind,
 // tcgen05.mma.ws
 foreach sparse = [0, 1] in {
   foreach space = ["shared", "tensor"] in {
-    foreach kind = ["f16", "tf32", "f8f6f4", "i8"] in {
+    foreach kind = ["f16", "tf32", "f8f6f4", "i8", "ti16"] in {
       foreach collector_buffer_b = [0, 1, 2, 3] in {
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kvederni wrote:

That's a good point. Let's do the cleanup in one of the following PRs. I have added this to my todo list. The intension of this PR is to enable `kind::ti16` for tcgen05.mma.

https://github.com/llvm/llvm-project/pull/215624