[Mlir-commits] [mlir] [mlir][ArmSME] Enable native ArmSME integration testing on Darwin (PR #215296)
Federico Bruzzone
llvmlistbot at llvm.org
Mon Aug 10 23:06:22 PDT 2026
https://github.com/FedericoBruzzone updated https://github.com/llvm/llvm-project/pull/215296
>From c5cb307e500097dd66a527bcd6e22972738559fe Mon Sep 17 00:00:00 2001
From: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Date: Mon, 10 Aug 2026 15:02:18 +0200
Subject: [PATCH] [mlir][ArmSME] Enable native ArmSME integration testing on
Darwin
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
---
.../modules/MLIRCheckHardwareFeatures.cmake | 48 ++++++++++++++++++-
.../Dialect/Linalg/CPU/ArmSME/fill-2d.mlir | 2 +-
.../Linalg/CPU/ArmSME/matmul-transpose-a.mlir | 2 +-
.../Dialect/Linalg/CPU/ArmSME/matmul.mlir | 2 +-
.../ArmSME/multi-tile-matmul-mixed-types.mlir | 2 +
.../Linalg/CPU/ArmSME/multi-tile-matmul.mlir | 2 +
.../Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir | 3 ++
.../Linalg/CPU/ArmSME/use-too-many-tiles.mlir | 2 +-
.../CPU/ArmSME/load-store-128-bit-tile.mlir | 5 +-
.../Vector/CPU/ArmSME/load-vertical.mlir | 2 +-
.../CPU/ArmSME/multi-tile-transpose.mlir | 2 +
.../CPU/ArmSME/outerproduct-f16f16f32.mlir | 2 +
.../Vector/CPU/ArmSME/outerproduct-f32.mlir | 2 +-
.../Vector/CPU/ArmSME/outerproduct-f64.mlir | 2 +-
.../CPU/ArmSME/outerproduct-i8i8i32.mlir | 2 +
.../Dialect/Vector/CPU/ArmSME/ssve.mlir | 6 ++-
.../Dialect/Vector/CPU/ArmSME/tile-fill.mlir | 2 +-
.../Vector/CPU/ArmSME/transfer-read-2d.mlir | 2 +-
.../Vector/CPU/ArmSME/transfer-write-2d.mlir | 2 +-
.../Dialect/Vector/CPU/ArmSME/transpose.mlir | 2 +-
.../Vector/CPU/ArmSME/vector-load-store.mlir | 2 +-
.../Dialect/Vector/CPU/ArmSME/vector-ops.mlir | 2 +-
mlir/test/Integration/lit.local.cfg | 14 ++++++
23 files changed, 95 insertions(+), 17 deletions(-)
diff --git a/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake b/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
index 7bc13287cd655..73cde69648911 100644
--- a/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
+++ b/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
@@ -2,8 +2,46 @@
# the moment these are used when configuring MLIR integration tests.
# Checks whether the specified hardware capability is supported by the host
-# Linux system. This is implemented by checking auxiliary vector feature
-# provided by the Linux kernel.
+# Darwin (macOS) system. This is implemented via `sysctl`, which is the
+# Darwin equivalent of Linux's auxiliary vector feature bits. Only the
+# mappings actually needed by callers in this file are provided; unmapped
+# hwcap_spec values conservatively report unsupported.
+#
+# check_hwcap_darwin(
+# hwcap_spec
+# output_var
+# )
+function(check_hwcap_darwin hwcap_spec output)
+ if(hwcap_spec STREQUAL "HWCAP2_SME")
+ set(sysctl_name "hw.optional.arm.FEAT_SME")
+ else()
+ message(STATUS "Checking whether ${hwcap_spec} is supported by the host system: FALSE (no Darwin mapping)")
+ set(${output} FALSE PARENT_SCOPE)
+ return()
+ endif()
+
+ execute_process(
+ COMMAND sysctl -n ${sysctl_name}
+ OUTPUT_VARIABLE sysctl_output
+ OUTPUT_STRIP_TRAILING_WHITESPACE
+ ERROR_QUIET
+ RESULT_VARIABLE sysctl_result
+ )
+
+ if(sysctl_result EQUAL 0 AND sysctl_output STREQUAL "1")
+ set(local_result TRUE)
+ else()
+ set(local_result FALSE)
+ endif()
+ message(STATUS "Checking whether ${hwcap_spec} is supported by the host system (via sysctl ${sysctl_name}): ${local_result}")
+ set(${output} ${local_result} PARENT_SCOPE)
+endfunction(check_hwcap_darwin)
+
+# Checks whether the specified hardware capability is supported by the host
+# system. On Linux this is implemented by checking auxiliary vector feature
+# provided by the Linux kernel. On Darwin (macOS) this is implemented via
+# `sysctl` (see check_hwcap_darwin). On other platforms this conservatively
+# reports unsupported.
#
# check_hwcap(
# hwcap_spec
@@ -21,6 +59,12 @@
# check_hwcap("HWCAP2_SME" SME_EMULATOR_REQUIRED)
#
function(check_hwcap hwcap_spec output)
+ if(APPLE)
+ check_hwcap_darwin(${hwcap_spec} local_output)
+ set(${output} ${local_output} PARENT_SCOPE)
+ return()
+ endif()
+
set(hwcap_test_src
[====[
#include <asm/hwcap.h>
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
index ed4342b7d50af..9d80b42285f20 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
@@ -5,7 +5,7 @@
// RUN: -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=entry -entry-point-result=void \
-// RUN: -march=aarch64 -mattr="+sve,+sme" \
+// RUN: -march=aarch64 -mattr="%arm_sme_mattr" \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
index d26853d14aec7..80256fee2b62f 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
@@ -4,7 +4,7 @@
// RUN: -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=main -entry-point-result=void \
-// RUN: -march=aarch64 -mattr="+sve,+sme" \
+// RUN: -march=aarch64 -mattr="%arm_sme_mattr" \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
index e2c0f1d22fea1..9ddb3f4b48dd1 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
@@ -3,7 +3,7 @@
// RUN: -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=main -entry-point-result=void \
-// RUN: -march=aarch64 -mattr="+sve,+sme" \
+// RUN: -march=aarch64 -mattr="%arm_sme_mattr" \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
index 71798a6affbbc..f6413721f6f04 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// RUN: mlir-opt %s \
// RUN: -transform-interpreter -test-transform-dialect-erase-schedule \
// RUN: -one-shot-bufferize="bufferize-function-boundaries" -canonicalize \
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
index 207d29858be52..1f364ea325b41 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// RUN: mlir-opt %s \
// RUN: -transform-interpreter -test-transform-dialect-erase-schedule \
// RUN: -one-shot-bufferize="bufferize-function-boundaries" -canonicalize \
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
index 73e286f960008..62f27d872386d 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
@@ -1,3 +1,6 @@
+// Fails to select `vscale`-based codegen natively on Apple Silicon.
+// XFAIL: target={{(arm64|aarch64)-apple-.*}}
+
// DEFINE: %{compile} = mlir-opt %s \
// DEFINE: -transform-interpreter -test-transform-dialect-erase-schedule \
// DEFINE: -canonicalize -test-lower-to-arm-sme -convert-vector-to-llvm="enable-arm-sve" \
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
index 05eee31ccc6fa..fc240009898a9 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
@@ -2,7 +2,7 @@
// RUN: -test-lower-to-arm-sme -test-lower-to-llvm -verify-diagnostics | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=main -entry-point-result=void \
-// RUN: -march=aarch64 -mattr="+sve,+sme" \
+// RUN: -march=aarch64 -mattr="%arm_sme_mattr" \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
index f4275fdde3c78..344b254ed8c22 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
@@ -1,7 +1,10 @@
+// Fails to select `vscale`-based codegen natively on Apple Silicon.
+// XFAIL: target={{(arm64|aarch64)-apple-.*}}
+
// DEFINE: %{entry_point} = test_load_store_zaq0
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
index 8d4b4a07994e2..377209f5eccd4 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
index 7f1566d635cbb..e8294c7620722 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// RUN: mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
// RUN: -e=main -entry-point-result=void \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
index 886a990125b4c..123d6bd1ed672 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// DEFINE: %{opts} =
// DEFINE: %{entry} = main
// DEFINE: %{compile} = mlir-opt %s \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
index 219367a41d51a..4defe5fea1491 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
@@ -2,7 +2,7 @@
// DEFINE: %{compile} = mlir-opt %s \
// DEFINE: -test-lower-to-arm-sme -test-lower-to-llvm -o %t
// DEFINE: %{run} = %mcr_aarch64_cmd %t \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
index 059f24adbe721..a37a225a30a12 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
@@ -2,7 +2,7 @@
// DEFINE: %{compile} = mlir-opt %s \
// DEFINE: -test-lower-to-arm-sme -test-lower-to-llvm -o %t
// DEFINE: %{run} = %mcr_aarch64_cmd %t \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme-f64f64 \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr,+sme-f64f64 \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
index 74ddbc63380b7..1515672057d33 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
// DEFINE: %{entry} = main
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
index aa8a2aa45d65b..2fe81220c4b73 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
@@ -1,7 +1,11 @@
+// Fails natively on Apple Silicon with "Scalarization of scalable
+// vectors is not supported".
+// XFAIL: target={{(arm64|aarch64)-apple-.*}}
+
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=i32 \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
index b94345c70c713..c622ad922d8b9 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
@@ -1,6 +1,6 @@
// RUN: mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm | \
// RUN: %mcr_aarch64_cmd \
-// RUN: -march=aarch64 -mattr=+sve,+sme \
+// RUN: -march=aarch64 -mattr=%arm_sme_mattr \
// RUN: -e entry -entry-point-result=i32 \
// RUN: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
// RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
index 77f5a325728b3..77c683e8b7e90 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
index bf6900ca810c2..2619e21ba6b3b 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
index 8188e66ce0662..cb5035646bc38 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=void \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
index eb9988666f4e5..9b5e03ee006bf 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = za0_d_f64
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=i32 \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
index ad8e321c0c8ae..f12dde752398a 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
@@ -1,7 +1,7 @@
// DEFINE: %{entry_point} = entry
// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
// DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -march=aarch64 -mattr=%arm_sme_mattr \
// DEFINE: -e %{entry_point} -entry-point-result=i32 \
// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
diff --git a/mlir/test/Integration/lit.local.cfg b/mlir/test/Integration/lit.local.cfg
index 5f16b1cc3cc43..324e63b8edaf2 100644
--- a/mlir/test/Integration/lit.local.cfg
+++ b/mlir/test/Integration/lit.local.cfg
@@ -4,6 +4,20 @@ if not config.mlir_include_integration_tests:
config.unsupported = True
+def configure_arm_sme_mattr():
+ # `+sve` is not required: FeatureSME does not imply FeatureSVE (see
+ # AArch64Features.td), and none of the tests using this substitution
+ # need base (non-streaming) SVE codegen. On Apple Silicon, which does
+ # not expose base SVE at EL0, requesting `+sve` makes LLVM select plain
+ # SVE instructions (e.g., `cntd`) that are illegal outside streaming
+ # mode and trap -- see #204853. Omitting it avoids that trap and is
+ # sufficient on every platform.
+ config.substitutions.append(("%arm_sme_mattr", "+sme,+sme2"))
+
+
+configure_arm_sme_mattr()
+
+
def configure_aarch64_mcr_cmd():
mcr_cmd = "mlir-runner"
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