[Mlir-commits] [mlir] [mlir][ArmSME] Enable native ArmSME integration testing on Darwin (PR #215296)

llvmlistbot at llvm.org llvmlistbot at llvm.org
Mon Aug 10 07:50:02 PDT 2026 

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-mlir-linalg

Author: Federico Bruzzone (FedericoBruzzone)

<details>
<summary>Changes</summary>

`MLIR_RUN_ARM_SME_TESTS=ON` could not actually exercise ArmSME integration tests on real Apple Silicon SME hardware. 
<details>
<summary>For three separate reasons...</summary>

1. **No native hardware detection on Darwin.** `check_hwcap` only detects CPU features via Linux's `getauxval()`/`hwcap.h`. On any non-Linux host it unconditionally falls through to requiring `ARM_EMULATOR_EXECUTABLE`, even when the host itself has real SME hardware.
2. **Illegal instruction selection on Apple Silicon.** Once an emulator requirement is bypassed and tests actually run natively, most crash with `SIGILL`. With `+sve` enabled, LLVM lowers `vector.vscale` to a bare `cntd`/`cntb`, which is only valid inside streaming mode. Apple Silicon does not expose base (non-streaming) SVE at EL0, so `cntd` traps there, even inside a function correctly marked `arm_locally_streaming` (see #<!-- -->204853).
3. **Some tests fundamentally cannot run natively at all.** 6 tests call `setArmSVLBits`/`setArmVLBits` to force a specific streaming vector length.
</details>

This PR solves these issues by:

1. Adding `check_hwcap_darwin`, using `sysctl`. Verified on an M4 Pro: `MLIR_RUN_ARM_SME_TESTS=ON` now configures cleanly without `ARM_EMULATOR_EXECUTABLE` set.
2. Adding a platform-aware `%arm_sme_mattr` lit substitution (`+sve,+sme` on Linux, `+sme,+sme2` on Darwin) and use it in the 15 ArmSME integration tests that don't force a specific vector length, avoiding the illegal `cntd`/`cntb` selection.
3. Marking the 6 VL-forcing tests `REQUIRES: arm-emulator`, matching the existing tag on `test-setArmSVLBits.mlir`, they correctly skip on native hardware instead of being silently attempted and failing.

The remaining 3 tests fail natively on Darwin for reasons unrelated to the above. We mark them `XFAIL` for Apple targets with a comment explaining why, rather than leaving them as silent failures.

The current status: **13/22** ArmSME integration tests pass natively, **6** correctly skip without an emulator, **3** are marked XFAIL with the root cause documented inline.

I leveraged AI to work on this PR.

---
Full diff: https://github.com/llvm/llvm-project/pull/215296.diff


23 Files Affected:

- (modified) mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake (+46-2) 
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir (+2) 
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir (+2) 
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir (+7) 
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir (+6-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir (+2) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir (+2) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir (+2) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir (+7-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir (+1-1) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir (+1-1) 
- (modified) mlir/test/Integration/lit.local.cfg (+17) 


``````````diff
diff --git a/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake b/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
index 7bc13287cd655..73cde69648911 100644
--- a/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
+++ b/mlir/cmake/modules/MLIRCheckHardwareFeatures.cmake
@@ -2,8 +2,46 @@
 # the moment these are used when configuring MLIR integration tests.
 
 # Checks whether the specified hardware capability is supported by the host
-# Linux system. This is implemented by checking auxiliary vector feature
-# provided by the Linux kernel.
+# Darwin (macOS) system. This is implemented via `sysctl`, which is the
+# Darwin equivalent of Linux's auxiliary vector feature bits. Only the
+# mappings actually needed by callers in this file are provided; unmapped
+# hwcap_spec values conservatively report unsupported.
+#
+# check_hwcap_darwin(
+#   hwcap_spec
+#   output_var
+# )
+function(check_hwcap_darwin hwcap_spec output)
+    if(hwcap_spec STREQUAL "HWCAP2_SME")
+      set(sysctl_name "hw.optional.arm.FEAT_SME")
+    else()
+      message(STATUS "Checking whether ${hwcap_spec} is supported by the host system: FALSE (no Darwin mapping)")
+      set(${output} FALSE PARENT_SCOPE)
+      return()
+    endif()
+
+    execute_process(
+        COMMAND sysctl -n ${sysctl_name}
+        OUTPUT_VARIABLE sysctl_output
+        OUTPUT_STRIP_TRAILING_WHITESPACE
+        ERROR_QUIET
+        RESULT_VARIABLE sysctl_result
+    )
+
+    if(sysctl_result EQUAL 0 AND sysctl_output STREQUAL "1")
+      set(local_result TRUE)
+    else()
+      set(local_result FALSE)
+    endif()
+    message(STATUS "Checking whether ${hwcap_spec} is supported by the host system (via sysctl ${sysctl_name}): ${local_result}")
+    set(${output} ${local_result} PARENT_SCOPE)
+endfunction(check_hwcap_darwin)
+
+# Checks whether the specified hardware capability is supported by the host
+# system. On Linux this is implemented by checking auxiliary vector feature
+# provided by the Linux kernel. On Darwin (macOS) this is implemented via
+# `sysctl` (see check_hwcap_darwin). On other platforms this conservatively
+# reports unsupported.
 #
 # check_hwcap(
 #   hwcap_spec
@@ -21,6 +59,12 @@
 # check_hwcap("HWCAP2_SME" SME_EMULATOR_REQUIRED)
 #
 function(check_hwcap hwcap_spec output)
+    if(APPLE)
+      check_hwcap_darwin(${hwcap_spec} local_output)
+      set(${output} ${local_output} PARENT_SCOPE)
+      return()
+    endif()
+
     set(hwcap_test_src
       [====[
       #include <asm/hwcap.h>
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
index ed4342b7d50af..9d80b42285f20 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
@@ -5,7 +5,7 @@
 // RUN:   -test-lower-to-arm-sme -test-lower-to-llvm | \
 // RUN: %mcr_aarch64_cmd \
 // RUN:   -e=entry -entry-point-result=void \
-// RUN:   -march=aarch64 -mattr="+sve,+sme" \
+// RUN:   -march=aarch64 -mattr="%arm_sme_mattr" \
 // RUN:   -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
 // RUN: FileCheck %s
 
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
index d26853d14aec7..80256fee2b62f 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
@@ -4,7 +4,7 @@
 // RUN:   -test-lower-to-arm-sme -test-lower-to-llvm | \
 // RUN: %mcr_aarch64_cmd \
 // RUN:   -e=main -entry-point-result=void \
-// RUN:   -march=aarch64 -mattr="+sve,+sme" \
+// RUN:   -march=aarch64 -mattr="%arm_sme_mattr" \
 // RUN:   -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
 // RUN: FileCheck %s
 
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
index e2c0f1d22fea1..9ddb3f4b48dd1 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
@@ -3,7 +3,7 @@
 // RUN:   -test-lower-to-arm-sme -test-lower-to-llvm | \
 // RUN: %mcr_aarch64_cmd \
 // RUN:   -e=main -entry-point-result=void \
-// RUN:   -march=aarch64 -mattr="+sve,+sme" \
+// RUN:   -march=aarch64 -mattr="%arm_sme_mattr" \
 // RUN:   -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
 // RUN: FileCheck %s
 
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
index 71798a6affbbc..f6413721f6f04 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
 // RUN: mlir-opt %s \
 // RUN:   -transform-interpreter -test-transform-dialect-erase-schedule  \
 // RUN:   -one-shot-bufferize="bufferize-function-boundaries" -canonicalize \
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
index 207d29858be52..1f364ea325b41 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
 // RUN: mlir-opt %s \
 // RUN:   -transform-interpreter -test-transform-dialect-erase-schedule  \
 // RUN:   -one-shot-bufferize="bufferize-function-boundaries" -canonicalize \
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
index 73e286f960008..acbdaacf6d78b 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
@@ -1,3 +1,10 @@
+// A helper function generated by the tiling/packing pipeline (e.g.
+// pack_lhs) uses scalable vector types without being marked
+// `arm_locally_streaming`. This requires base (non-streaming) SVE,
+// which Apple Silicon does not expose at EL0, so it crashes/fails to
+// select at native codegen time there.
+// XFAIL: target={{(arm64|aarch64)-apple-.*}}
+
 // DEFINE: %{compile} =  mlir-opt %s \
 // DEFINE:    -transform-interpreter -test-transform-dialect-erase-schedule \
 // DEFINE:    -canonicalize -test-lower-to-arm-sme -convert-vector-to-llvm="enable-arm-sve" \
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
index 05eee31ccc6fa..fc240009898a9 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
@@ -2,7 +2,7 @@
 // RUN:   -test-lower-to-arm-sme -test-lower-to-llvm -verify-diagnostics | \
 // RUN: %mcr_aarch64_cmd \
 // RUN:   -e=main -entry-point-result=void \
-// RUN:   -march=aarch64 -mattr="+sve,+sme" \
+// RUN:   -march=aarch64 -mattr="%arm_sme_mattr" \
 // RUN:   -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
 // RUN: FileCheck %s
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
index f4275fdde3c78..8051a4334cf4a 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
@@ -1,7 +1,12 @@
+// Fails to select `vscale`-based codegen natively on Apple Silicon even
+// though the function is `arm_locally_streaming` -- likely a separate,
+// deeper AArch64 backend gap around 128-bit (SME2 ZAQ) tile handling.
+// XFAIL: target={{(arm64|aarch64)-apple-.*}}
+
 // DEFINE: %{entry_point} = test_load_store_zaq0
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE:  -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:  -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:  -e %{entry_point} -entry-point-result=void \
 // DEFINE:  -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
index 8d4b4a07994e2..377209f5eccd4 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
@@ -1,7 +1,7 @@
 // DEFINE: %{entry_point} = entry
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE:   -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:   -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:   -e %{entry_point} -entry-point-result=void \
 // DEFINE:   -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
index 7f1566d635cbb..e8294c7620722 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
 // RUN: mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm | \
 // RUN: %mcr_aarch64_cmd \
 // RUN:   -e=main -entry-point-result=void \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
index 886a990125b4c..123d6bd1ed672 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
 // DEFINE: %{opts} =
 // DEFINE: %{entry} = main
 // DEFINE: %{compile} = mlir-opt %s \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
index 219367a41d51a..4defe5fea1491 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
@@ -2,7 +2,7 @@
 // DEFINE: %{compile} = mlir-opt %s \
 // DEFINE:   -test-lower-to-arm-sme -test-lower-to-llvm -o %t
 // DEFINE: %{run} = %mcr_aarch64_cmd %t \
-// DEFINE:   -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:   -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:   -e %{entry_point} -entry-point-result=void \
 // DEFINE:   -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
index 059f24adbe721..a37a225a30a12 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
@@ -2,7 +2,7 @@
 // DEFINE: %{compile} = mlir-opt %s \
 // DEFINE:   -test-lower-to-arm-sme -test-lower-to-llvm -o %t
 // DEFINE: %{run} = %mcr_aarch64_cmd %t \
-// DEFINE:   -march=aarch64 -mattr=+sve,+sme-f64f64 \
+// DEFINE:   -march=aarch64 -mattr=%arm_sme_mattr,+sme-f64f64 \
 // DEFINE:   -e %{entry_point} -entry-point-result=void \
 // DEFINE:   -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
index 74ddbc63380b7..1515672057d33 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
@@ -1,3 +1,5 @@
+// REQUIRES: arm-emulator
+
 // DEFINE: %{entry} = main
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
index aa8a2aa45d65b..b9516ff79c054 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
@@ -1,7 +1,13 @@
+// Fails natively on Apple Silicon with "Scalarization of scalable
+// vectors is not supported" -- a separate AArch64 backend gap, distinct
+// from the `+sve`/streaming-mode issue this file's %arm_sme_mattr works
+// around.
+// XFAIL: target={{(arm64|aarch64)-apple-.*}}
+
 // DEFINE: %{entry_point} = entry
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE:  -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:  -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:  -e %{entry_point} -entry-point-result=i32 \
 // DEFINE:  -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
index b94345c70c713..c622ad922d8b9 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
@@ -1,6 +1,6 @@
 // RUN: mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm | \
 // RUN: %mcr_aarch64_cmd \
-// RUN:  -march=aarch64 -mattr=+sve,+sme \
+// RUN:  -march=aarch64 -mattr=%arm_sme_mattr \
 // RUN:  -e entry -entry-point-result=i32 \
 // RUN:  -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib | \
 // RUN: FileCheck %s
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
index 77f5a325728b3..77c683e8b7e90 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
@@ -1,7 +1,7 @@
 // DEFINE: %{entry_point} = entry
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE:  -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:  -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:  -e %{entry_point} -entry-point-result=void \
 // DEFINE:  -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
index bf6900ca810c2..2619e21ba6b3b 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
@@ -1,7 +1,7 @@
 // DEFINE: %{entry_point} = entry
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE:  -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:  -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:  -e %{entry_point} -entry-point-result=void \
 // DEFINE:  -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
index 8188e66ce0662..cb5035646bc38 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
@@ -1,7 +1,7 @@
 // DEFINE: %{entry_point} = entry
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE:   -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:   -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:   -e %{entry_point} -entry-point-result=void \
 // DEFINE:   -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
index eb9988666f4e5..9b5e03ee006bf 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
@@ -1,7 +1,7 @@
 // DEFINE: %{entry_point} = za0_d_f64
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE:  -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:  -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:  -e %{entry_point} -entry-point-result=i32 \
 // DEFINE:  -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
index ad8e321c0c8ae..f12dde752398a 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir
@@ -1,7 +1,7 @@
 // DEFINE: %{entry_point} = entry
 // DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
 // DEFINE: %{run} = %mcr_aarch64_cmd \
-// DEFINE:  -march=aarch64 -mattr=+sve,+sme \
+// DEFINE:  -march=aarch64 -mattr=%arm_sme_mattr \
 // DEFINE:  -e %{entry_point} -entry-point-result=i32 \
 // DEFINE:  -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
 
diff --git a/mlir/test/Integration/lit.local.cfg b/mlir/test/Integration/lit.local.cfg
index 5f16b1cc3cc43..8a11deafd9d0a 100644
--- a/mlir/test/Integration/lit.local.cfg
+++ b/mlir/test/Integration/lit.local.cfg
@@ -1,9 +1,26 @@
+import sys
+
 from lit.llvm import llvm_config
 
 if not config.mlir_include_integration_tests:
     config.unsupported = True
 
 
+def configure_arm_sme_mattr():
+    # Apple Silicon (and Darwin in general) does not expose base
+    # (non-streaming) SVE at EL0, only SME/streaming-SVE. Requesting
+    # `+sve` there makes LLVM select plain SVE instructions (e.g., `cntd`)
+    # that are illegal outside streaming mode and trap. See #204853.
+    if sys.platform == "darwin":
+        mattr = "+sme,+sme2"
+    else:
+        mattr = "+sve,+sme"
+    config.substitutions.append(("%arm_sme_mattr", mattr))
+
+
+configure_arm_sme_mattr()
+
+
 def configure_aarch64_mcr_cmd():
     mcr_cmd = "mlir-runner"
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/215296

More information about the Mlir-commits mailing list