[Mlir-commits] [clang] [llvm] [mlir] [AMDGPU] Fix missing cache bypass scope on seq_cst buffer fat pointer atomics (PR #213585)

[Arseniy Obolenskiy]

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@@ -4937,6 +5019,81 @@ static Value *upgradeAMDGCNIntrinsicCall(StringRef Name, CallBase *CI,
     return UpgradeLegacyWMMAIUIntrinsicCall(F, CI, Builder, {T1, T2, T3, T4});
   }
 
+  // Legacy buffer atomic/store/atomic-load intrinsics missed the trailing
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aobolensk wrote:

Reworked the metadata operands, wording has also been updated

https://github.com/llvm/llvm-project/pull/213585