[Mlir-commits] [llvm] [mlir] [AMDGPU] Let LDSDMA ops cross a sched_barrier when the mask allows it (PR #203255)

[Krzysztof Drewniak]

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@@ -1906,10 +1906,16 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
                                                    - 0x0002: VALU instructions may be scheduled across sched_barrier.
                                                    - 0x0004: SALU instructions may be scheduled across sched_barrier.
                                                    - 0x0008: MFMA/WMMA instructions may be scheduled across sched_barrier.
-                                                   - 0x0010: All VMEM instructions may be scheduled across sched_barrier.
-                                                   - 0x0020: VMEM read instructions may be scheduled across sched_barrier.
-                                                   - 0x0040: VMEM write instructions may be scheduled across sched_barrier.
-                                                   - 0x0080: All DS instructions may be scheduled across sched_barrier.
+                                                   - 0x0010: All VMEM instructions may be scheduled across sched_barrier. This
+                                                     includes LDSDMA instructions.
+                                                   - 0x0020: VMEM read instructions may be scheduled across sched_barrier. This
+                                                     does not include LDSDMA instructions; only loads targeting VGPRs are
+                                                     allowed.
+                                                   - 0x0040: VMEM write instructions may be scheduled across sched_barrier. This
+                                                     does not include LDSDMA instructions; only stores sourcing from VGPRs are
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krzysz00 wrote:

You could argue that there's a write to global memory from DMAs?

https://github.com/llvm/llvm-project/pull/203255