[Mlir-commits] [clang] [llvm] [mlir] [AMDGPU] Fix missing cache bypass scope on seq_cst buffer fat pointer atomics (PR #213585)

[Krzysztof Drewniak]

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@@ -1509,6 +1533,12 @@ void SITargetLowering::getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
         Info.memVT = getValueType(MF.getDataLayout(), DataTy);
 
       Info.flags = Flags | MachineMemOperand::MOStore;
+      if (std::optional<SyncScope::ID> SSID = parseBufferAtomicScopeArg(CI)) {
+        // Pretend to be atomic so SIMemoryLegalizer::expandStore sets cache
+        // bypass bits, since atomic and plain buffer stores look identical.
+        Info.order = AtomicOrdering::Monotonic;
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krzysz00 wrote:

I'm not sure Monotonic is correct here?

https://github.com/llvm/llvm-project/pull/213585