[Mlir-commits] [mlir] [mlir][mem2reg] Promote whole-buffer memref to a vector SSA value (PR #211880)

[Andrzej Warzyński]

banach-space wrote:

Thank for you for the discussion and the updated summary, @Jianhui-Li ! 

> My understanding is that the existing hoisting mechanism only hoists the buffer out of loop if the buffer is loop-invariant memory location. But the case above has a branch inside so it breaks the assumption.

TBH, I have not analysed this case myself. It does feel a bit too complex for the hoisting logic, which gives us good rationale to extend mem2reg. No further objections from me!

> Since MLIR does not have a "default pipeline", nor a "canonical form evolution", it's not reasonable to expect all compilers to go through the same stages of IR forms. To be clear, I'm not advocating for duplicated code, but it's hard to argue for zero intersection between different passes. Not even LLVM has that promise.

Sure, but as maintainers we need to filter what goes in and what does not go into MLIR. Ultimately, that's additional code for us to maintain. To help with that, I always seek a good justification in the summary. For me that was missing. 

Btw, even in LLVM, there's usually justification for an overlap between passes/infra/other-logic. IMO, things become particularly tricky in MLIR - there's just so many small transformations scattered around.

https://github.com/llvm/llvm-project/pull/211880