[Mlir-commits] [mlir] [mlir][NVVM] Tighten result-type predicate on special-register ops (PR #195030)

[Bastian Hagedorn]

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@@ -2115,3 +2115,35 @@ module attributes { dlti.dl_spec = #dlti.dl_spec<
     %0 = llvm.ptrtoaddr %arg0 : !llvm.ptr to i64
   }
 }
+
+// -----
+
+func.func @nvvm_read_sreg_tid_x_wrong_type() {
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bastianhagedorn wrote:

Trimmed to two cases: one i32-expected (tid.x) and one i64-expected (clock64), which covers both directions and both base classes.

https://github.com/llvm/llvm-project/pull/195030