[Mlir-commits] [mlir] [mlir][NVVM] Tighten result-type predicate on special-register ops (PR #195030)

[Bastian Hagedorn]

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@@ -306,22 +306,28 @@ class NVVM_SingleResultIntrinsicOp<string mnemonic, list<Trait> traits = [], str
 // NVVM special register op definitions
 //===----------------------------------------------------------------------===//
 
-class NVVM_PureSpecialRegisterOp<string mnemonic, list<Trait> traits = []> :
+class NVVM_PureSpecialRegisterOp<string mnemonic, list<Trait> traits = [],
+                                 Type resultType = I32> :
   NVVM_IntrOp<mnemonic, !listconcat(traits, [Pure]), 1> {
   let arguments = (ins);
+  let results = (outs resultType:$res);
   let assemblyFormat = "attr-dict `:` type($res)";
 }
 
-class NVVM_SpecialRegisterOp<string mnemonic, list<Trait> traits = []> :
+class NVVM_SpecialRegisterOp<string mnemonic, list<Trait> traits = [],
+                             Type resultType = I32> :
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bastianhagedorn wrote:

Done, applied the swap. Drops the empty-list placeholder for the i64 ops too, so they read more naturally. 

https://github.com/llvm/llvm-project/pull/195030