[Mlir-commits] [clang] [flang] [llvm] [mlir] [AsmWriter] Change the output syntax of floating-point literals. (PR #190649)
Joshua Cranmer
llvmlistbot at llvm.org
Tue Apr 28 09:26:47 PDT 2026
https://github.com/jcranmer-intel updated https://github.com/llvm/llvm-project/pull/190649
>From 312e0a41adf2716f377f3481eb4a39ebadec440c Mon Sep 17 00:00:00 2001
From: Joshua Cranmer <joshua.cranmer at intel.com>
Date: Mon, 6 Apr 2026 10:15:20 -0700
Subject: [PATCH 1/2] [AsmWriter] Change the output syntax of floating-point
literals.
This makes infinities and NaNs return the new, more explicit outputs,
and extends the base decimal output literal to support non-double types.
In addition, the legacy hexadecimal floating-point literal format is no longer
output in any circumstance.
A script to change the output for most test files is available at
https://gist.github.com/jcranmer-intel/d279296ad91884c98b77fb23a9112a5a.
Full disclosure: the python portion of the script was written with the
use of AI tools. The C++ portion was written entirely by hand, reusing
LLVM's existing helpers for output.
The test changes included in this commit are *only* those which do not
work with that script, either because the script mangled the conversion
(e.g., intentionally matching only a prefix to allow some imprecision)
or because the tests were too unusual for the script to find the
floating-point literals being compared against.
---
clang/test/C/C2y/n3364.c | 18 +--
clang/test/CIR/CodeGen/inherited-ctors.cpp | 4 +-
.../test/CIR/CodeGen/long-double-inc-dec.cpp | 28 ++--
.../CodeGen/X86/long-double-config-size.c | 6 +-
clang/test/CodeGen/atomic.c | 4 +-
clang/test/CodeGen/builtin-complex.c | 4 +-
clang/test/CodeGen/builtin-nanf.c | 2 +-
clang/test/CodeGen/builtins.c | 62 +++-----
clang/test/CodeGen/catch-undef-behavior.c | 10 +-
clang/test/CodeGen/const-init.c | 2 +-
clang/test/Lexer/11-27-2007-FloatLiterals.c | 10 +-
clang/test/OpenMP/declare_reduction_codegen.c | 4 +-
.../complex-div-to-llvm-kind10.f90 | 46 +++---
.../test/Integration/complex-div-to-llvm.f90 | 136 +++++++++---------
llvm/docs/ReleaseNotes.md | 3 +
llvm/include/llvm/ADT/APFloat.h | 12 ++
llvm/lib/IR/AsmWriter.cpp | 133 +++++++----------
llvm/lib/Support/APFloat.cpp | 11 +-
llvm/test/Assembler/bfloat.ll | 14 +-
llvm/test/Assembler/float-literals.ll | 42 ++++--
llvm/test/Assembler/half-constprop.ll | 2 +-
llvm/test/Assembler/half-conv.ll | 2 +-
llvm/test/Transforms/EarlyCSE/math-1.ll | 22 +--
llvm/test/Transforms/EarlyCSE/math-2.ll | 4 +-
...2009-01-19-fmod-constant-float-specials.ll | 2 +-
.../2009-01-19-fmod-constant-float.ll | 4 +-
.../Transforms/InstCombine/bitcast-store.ll | 2 +-
llvm/test/Transforms/InstCombine/pow-exp.ll | 42 +++---
.../Transforms/InstCombine/pow_fp_int16.ll | 2 +-
.../InstSimplify/ConstProp/AMDGPU/cos.ll | 58 ++++----
.../InstSimplify/ConstProp/AMDGPU/sin.ll | 58 ++++----
.../ConstProp/calls-math-finite.ll | 28 ++--
llvm/test/tools/llubi/bitcast_be.ll | 6 +-
llvm/test/tools/llubi/bitcast_le.ll | 6 +-
.../Target/LLVMIR/llvmir-le-specific.mlir | 8 +-
mlir/test/Target/LLVMIR/llvmir.mlir | 12 +-
mlir/test/Target/LLVMIR/openmp-private.mlir | 2 +-
.../Target/LLVMIR/openmp-wsloop-private.mlir | 2 +-
38 files changed, 403 insertions(+), 410 deletions(-)
diff --git a/clang/test/C/C2y/n3364.c b/clang/test/C/C2y/n3364.c
index ccf7e8d491346..11c2999cb9be6 100644
--- a/clang/test/C/C2y/n3364.c
+++ b/clang/test/C/C2y/n3364.c
@@ -23,20 +23,20 @@
float f1 = FLT_SNAN;
float f2 = +FLT_SNAN;
float f3 = -FLT_SNAN;
-// CHECK: @f1 = {{.*}}global float 0x7FF4000000000000
-// CHECK: @f2 = {{.*}}global float 0x7FF4000000000000
-// CHECK: @f3 = {{.*}}global float 0xFFF4000000000000
+// CHECK: @f1 = {{.*}}global float +snan(0x200000)
+// CHECK: @f2 = {{.*}}global float +snan(0x200000)
+// CHECK: @f3 = {{.*}}global float -snan(0x200000)
double d1 = DBL_SNAN;
double d2 = +DBL_SNAN;
double d3 = -DBL_SNAN;
-// CHECK: @d1 = {{.*}}global double 0x7FF4000000000000
-// CHECK: @d2 = {{.*}}global double 0x7FF4000000000000
-// CHECK: @d3 = {{.*}}global double 0xFFF4000000000000
+// CHECK: @d1 = {{.*}}global double +snan(0x4000000000000)
+// CHECK: @d2 = {{.*}}global double +snan(0x4000000000000)
+// CHECK: @d3 = {{.*}}global double -snan(0x4000000000000)
long double ld1 = LDBL_SNAN;
long double ld2 = +LDBL_SNAN;
long double ld3 = -LDBL_SNAN;
-// CHECK: @ld1 = {{.*}}global {{double 0x7FF4000000000000|x86_fp80 0xK7FFFA000000000000000|fp128 0xL00000000000000007FFF400000000000|ppc_fp128 0xM7FF40000000000000000000000000000}}
-// CHECK: @ld2 = {{.*}}global {{double 0x7FF4000000000000|x86_fp80 0xK7FFFA000000000000000|fp128 0xL00000000000000007FFF400000000000|ppc_fp128 0xM7FF40000000000000000000000000000}}
-// CHECK: @ld3 = {{.*}}global {{double 0xFFF4000000000000|x86_fp80 0xKFFFFA000000000000000|fp128 0xL0000000000000000FFFF400000000000|ppc_fp128 0xMFFF40000000000008000000000000000}}
+// CHECK: @ld1 = {{.*}}global {{double|x86_fp80|fp128|ppc_fp128}} +snan(
+// CHECK: @ld2 = {{.*}}global {{double|x86_fp80|fp128|ppc_fp128}} +snan(
+// CHECK: @ld3 = {{.*}}global {{double|x86_fp80|fp128|ppc_fp128}} -snan(
diff --git a/clang/test/CIR/CodeGen/inherited-ctors.cpp b/clang/test/CIR/CodeGen/inherited-ctors.cpp
index 158bc9f11b94a..8684b2142b68f 100644
--- a/clang/test/CIR/CodeGen/inherited-ctors.cpp
+++ b/clang/test/CIR/CodeGen/inherited-ctors.cpp
@@ -78,7 +78,7 @@ void fallsthrough() {
// LLVM-LABEL: define dso_local void @_Z26cannotEmitDelegateCallArgsv()
// LLVM: %[[TMP_ALLOCA:.*]] = alloca ptr
// LLVM: %[[TMP_LOAD:.*]] = load ptr, ptr %[[TMP_ALLOCA]]
-// LLVM: call void (ptr, float, ...) @_ZN4BaseC2Efz(ptr {{.*}}%[[TMP_LOAD]], float {{.*}}0x3FF19999A{{.*}}, i32 {{.*}}2, double {{.*}}3.000000e+00)
+// LLVM: call void (ptr, float, ...) @_ZN4BaseC2Efz(ptr {{.*}}%[[TMP_LOAD]], float {{.*}}1.100000e+00, i32 {{.*}}2, double {{.*}}3.000000e+00)
//
// CIR-LABEL: cir.func no_inline comdat linkonce_odr @_ZN11VirtDerivedCI24BaseEi(%{{.*}}: !cir.ptr<!rec_VirtDerived> {{.*}}, %{{.*}}: !cir.ptr<!cir.ptr<!void>>{{.*}}) special_member<#cir.cxx_ctor<!rec_VirtDerived, custom>>
// CIR: %[[THIS_ALLOCA:.*]] = cir.alloca !cir.ptr<!rec_VirtDerived>, !cir.ptr<!cir.ptr<!rec_VirtDerived>>, ["this", init] {alignment = 8 : i64}
@@ -146,7 +146,7 @@ void fallsthrough() {
// OGCG-LABEL: define dso_local void @_Z26cannotEmitDelegateCallArgsv()
// OGCG: %[[TMP_ALLOCA:.*]] = alloca ptr
// OGCG: %[[TMP_LOAD:.*]] = load ptr, ptr %[[TMP_ALLOCA]]
-// OGCG: call void (ptr, float, ...) @_ZN4BaseC2Efz(ptr {{.*}}%[[TMP_LOAD]], float {{.*}}0x3FF19999A{{.*}}, i32 {{.*}}2, double {{.*}}3.000000e+00)
+// OGCG: call void (ptr, float, ...) @_ZN4BaseC2Efz(ptr {{.*}}%[[TMP_LOAD]], float {{.*}}1.100000e+00, i32 {{.*}}2, double {{.*}}3.000000e+00)
//
// OGCG-LABEL: declare void @_ZN4BaseC2Efz(ptr {{.*}}, float {{.*}}, ...)
//
diff --git a/clang/test/CIR/CodeGen/long-double-inc-dec.cpp b/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
index 9665e090f5dca..02a6c10c010b2 100644
--- a/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
+++ b/clang/test/CIR/CodeGen/long-double-inc-dec.cpp
@@ -1,23 +1,23 @@
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-64 -fclangir -emit-cir %s -o %t.cir
// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR -DLDTY=cir.double
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-64 -fclangir -emit-llvm %s -o %t-cir.ll
-// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM,LLVMCIR -DLDTY=double -DONE=1 -DNEGONE=-1
+// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM,LLVMCIR -DLDTY=double
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-64 -emit-llvm %s -o %t.ll
-// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,OGCG -DLDTY=double -DONE=1 -DNEGONE=-1
+// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,OGCG -DLDTY=double
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-80 -fclangir -emit-cir %s -o %t.cir
// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR -DLDTY=cir.f80
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-80 -fclangir -emit-llvm %s -o %t-cir.ll
-// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM,LLVMCIR -DLDTY=x86_fp80 -DONE=0xK3FFF8 -DNEGONE=0xKBFFF8
+// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM,LLVMCIR -DLDTY=x86_fp80
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-80 -emit-llvm %s -o %t.ll
-// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,OGCG -DLDTY=x86_fp80 -DONE=0xK3FFF8 -DNEGONE=0xKBFFF8
+// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,OGCG -DLDTY=x86_fp80
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-128 -fclangir -emit-cir %s -o %t.cir
// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR -DLDTY=cir.f128
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-128 -fclangir -emit-llvm %s -o %t-cir.ll
-// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM,LLVMCIR -DLDTY=fp128 -DONE=0xL00000000000000003FFF -DNEGONE=0xL0000000000000000BFFF
+// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM,LLVMCIR -DLDTY=fp128
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -mlong-double-128 -emit-llvm %s -o %t.ll
-// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,OGCG -DLDTY=fp128 -DONE=0xL00000000000000003FFF -DNEGONE=0xL0000000000000000BFFF
+// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,OGCG -DLDTY=fp128
extern "C" long double do_pre_inc(long double d) {
// CIR-LABEL: @do_pre_inc(
@@ -37,8 +37,8 @@ extern "C" long double do_pre_inc(long double d) {
// CIR: cir.return %[[LOAD_RET]] : !cir.long_double<![[LDTY]]>
//
// LLVM: %[[ARG_LOAD:.*]] = load [[LDTY]], ptr %[[ARG_ALLOCA]]
- // LLVMCIR: %[[ARG_INC:.*]] = fadd [[LDTY]] [[ONE]]{{.*}}, %[[ARG_LOAD]]
- // OGCG: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], [[ONE]]{{.*}}
+ // LLVMCIR: %[[ARG_INC:.*]] = fadd [[LDTY]] 1.000000e+00, %[[ARG_LOAD]]
+ // OGCG: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
// LLVM: store [[LDTY]] %[[ARG_INC]], ptr %[[ARG_ALLOCA]]
// LLVMCIR: store [[LDTY]] %[[ARG_INC]], ptr %[[RET_ALLOCA]]
// LLVMCIR: %[[LOAD_RET:.*]] = load [[LDTY]], ptr %[[RET_ALLOCA]]
@@ -63,8 +63,8 @@ extern "C" long double do_post_inc(long double d) {
// CIR: cir.return %[[LOAD_RET]] : !cir.long_double<![[LDTY]]>
//
// LLVM: %[[ARG_LOAD:.*]] = load [[LDTY]], ptr %[[ARG_ALLOCA]]
- // LLVMCIR: %[[ARG_INC:.*]] = fadd [[LDTY]] [[ONE]]{{.*}}, %[[ARG_LOAD]]
- // OGCG: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], [[ONE]]{{.*}}
+ // LLVMCIR: %[[ARG_INC:.*]] = fadd [[LDTY]] 1.000000e+00, %[[ARG_LOAD]]
+ // OGCG: %[[ARG_INC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], 1.000000e+00
// LLVM: store [[LDTY]] %[[ARG_INC]], ptr %[[ARG_ALLOCA]]
// LLVMCIR: store [[LDTY]] %[[ARG_LOAD]], ptr %[[RET_ALLOCA]]
// LLVMCIR: %[[LOAD_RET:.*]] = load [[LDTY]], ptr %[[RET_ALLOCA]]
@@ -90,8 +90,8 @@ extern "C" long double do_pre_dec(long double d) {
// CIR: cir.return %[[LOAD_RET]] : !cir.long_double<![[LDTY]]>
//
// LLVM: %[[ARG_LOAD:.*]] = load [[LDTY]], ptr %[[ARG_ALLOCA]]
- // LLVMCIR: %[[ARG_DEC:.*]] = fadd [[LDTY]] [[NEGONE]]{{.*}}, %[[ARG_LOAD]]
- // OGCG: %[[ARG_DEC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], [[NEGONE]]{{.*}}
+ // LLVMCIR: %[[ARG_DEC:.*]] = fadd [[LDTY]] -1.000000e+00, %[[ARG_LOAD]]
+ // OGCG: %[[ARG_DEC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], -1.000000e+00
// LLVM: store [[LDTY]] %[[ARG_DEC]], ptr %[[ARG_ALLOCA]]
// LLVMCIR: store [[LDTY]] %[[ARG_DEC]], ptr %[[RET_ALLOCA]]
// LLVMCIR: %[[LOAD_RET:.*]] = load [[LDTY]], ptr %[[RET_ALLOCA]]
@@ -116,8 +116,8 @@ extern "C" long double do_post_dec(long double d) {
// CIR: cir.return %[[LOAD_RET]] : !cir.long_double<![[LDTY]]>
//
// LLVM: %[[ARG_LOAD:.*]] = load [[LDTY]], ptr %[[ARG_ALLOCA]]
- // LLVMCIR: %[[ARG_DEC:.*]] = fadd [[LDTY]] [[NEGONE]]{{.*}}, %[[ARG_LOAD]]
- // OGCG: %[[ARG_DEC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], [[NEGONE]]{{.*}}
+ // LLVMCIR: %[[ARG_DEC:.*]] = fadd [[LDTY]] -1.000000e+00, %[[ARG_LOAD]]
+ // OGCG: %[[ARG_DEC:.*]] = fadd [[LDTY]] %[[ARG_LOAD]], -1.000000e+00
// LLVM: store [[LDTY]] %[[ARG_DEC]], ptr %[[ARG_ALLOCA]]
// LLVMCIR: store [[LDTY]] %[[ARG_LOAD]], ptr %[[RET_ALLOCA]]
// LLVMCIR: %[[LOAD_RET:.*]] = load [[LDTY]], ptr %[[RET_ALLOCA]]
diff --git a/clang/test/CodeGen/X86/long-double-config-size.c b/clang/test/CodeGen/X86/long-double-config-size.c
index 563a483ca8cd6..27b54e68032a9 100644
--- a/clang/test/CodeGen/X86/long-double-config-size.c
+++ b/clang/test/CodeGen/X86/long-double-config-size.c
@@ -5,9 +5,9 @@
// RUN: %clang_cc1 -triple x86_64-windows-msvc %s -emit-llvm -o - | FileCheck %s --check-prefix=SIZE64
long double global;
-// SIZE64: @global = dso_local global double 0
-// SIZE80: @global = dso_local global x86_fp80 0xK{{0+}}, align 16
-// SIZE128: @global = dso_local global fp128 0
+// SIZE64: @global = dso_local global double 0.0
+// SIZE80: @global = dso_local global x86_fp80 0.000000e+00, align 16
+// SIZE128: @global = dso_local global fp128 0.0
long double func(long double param) {
// SIZE64: define dso_local double @func(double noundef %param)
diff --git a/clang/test/CodeGen/atomic.c b/clang/test/CodeGen/atomic.c
index 16c29e282ddd9..36764a819fe12 100644
--- a/clang/test/CodeGen/atomic.c
+++ b/clang/test/CodeGen/atomic.c
@@ -7,8 +7,8 @@
// CHECK: @[[GLOB_INT:.+]] = internal global i32 0
// CHECK: @[[GLOB_FLT:.+]] = internal global float {{[0e\+-\.]+}}, align
// CHECK: @[[GLOB_DBL:.+]] = internal global double {{[0e\+-\.]+}}, align
-// X86: @[[GLOB_LONGDBL:.+]] = internal global x86_fp80 {{[0xK]+}}, align
-// SYSTEMZ: @[[GLOB_LONGDBL:.+]] = internal global fp128 {{[0xL]+}}, align
+// X86: @[[GLOB_LONGDBL:.+]] = internal global x86_fp80 {{[0e\+-\.]+}}, align
+// SYSTEMZ: @[[GLOB_LONGDBL:.+]] = internal global fp128 {{[0e\+-\.]+}}, align
int atomic(void) {
// non-sensical test for sync functions
diff --git a/clang/test/CodeGen/builtin-complex.c b/clang/test/CodeGen/builtin-complex.c
index f9c7144b59ccb..76208047d0a70 100644
--- a/clang/test/CodeGen/builtin-complex.c
+++ b/clang/test/CodeGen/builtin-complex.c
@@ -6,8 +6,8 @@
// CHECK-FLOAT: @global ={{.*}} global { [[T:float]], [[T]] } { [[T]] 1.0{{.*}}, [[T]] 2.0{{.*}} }
// CHECK-DOUBLE: @global ={{.*}} global { [[T:double]], [[T]] } { [[T]] 1.0{{.*}}, [[T]] 2.0{{.*}} }
-// CHECK-FP80: @global ={{.*}} global { [[T:x86_fp80]], [[T]] } { [[T]] 0xK3FFF8000000000000000, [[T]] 0xK40008000000000000000 }
-// CHECK-FP128: @global ={{.*}} global { [[T:fp128]], [[T]] } { [[T]] 0xL00000000000000003FFF000000000000, [[T]] 0xL00000000000000004000000000000000 }
+// CHECK-FP80: @global ={{.*}} global { [[T:x86_fp80]], [[T]] } { [[T]] 1.0{{.*}}, [[T]] 2.0{{.*}} }
+// CHECK-FP128: @global ={{.*}} global { [[T:fp128]], [[T]] } { [[T]] 1.0{{.*}}, [[T]] 2.0{{.*}} }
_Complex T global = __builtin_complex(1.0, 2.0);
// CHECK-LABEL: @test
diff --git a/clang/test/CodeGen/builtin-nanf.c b/clang/test/CodeGen/builtin-nanf.c
index ae37c9dc80779..dfce2b5b31c1e 100644
--- a/clang/test/CodeGen/builtin-nanf.c
+++ b/clang/test/CodeGen/builtin-nanf.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple x86_64-apple-darwin9 -emit-llvm -o %t %s
-// RUN: grep 'float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000020000000, float 0x7FF8000000000000, float 0x7FF80001E0000000, float 0x7FF8001E00000000, float 0x7FF801E000000000, float 0x7FF81E0000000000, float 0x7FF9E00000000000, float 0x7FFFFFFFE0000000' %t
+// RUN: grep 'float +qnan, float +qnan, float +nan(0x1), float +qnan, float +nan(0xF), float +nan(0xF0), float +nan(0xF00), float +nan(0xF000), float +nan(0xF0000), float +nan(0x3FFFFF)' %t
float n[] = {
__builtin_nanf("0"),
diff --git a/clang/test/CodeGen/builtins.c b/clang/test/CodeGen/builtins.c
index 4decb30b18e5f..64b22f782dccf 100644
--- a/clang/test/CodeGen/builtins.c
+++ b/clang/test/CodeGen/builtins.c
@@ -192,43 +192,27 @@ void bar(void) {
double d;
long double ld;
- // LLVM's hex representation of float constants is really unfortunate;
- // basically it does a float-to-double "conversion" and then prints the
- // hex form of that. That gives us weird artifacts like exponents
- // that aren't numerically similar to the original exponent and
- // significand bit-patterns that are offset by three bits (because
- // the exponent was expanded from 8 bits to 11).
- //
- // 0xAE98 == 1010111010011000
- // 0x15D3 == 1010111010011
-
- f = __builtin_huge_valf(); // CHECK: float 0x7FF0000000000000
- d = __builtin_huge_val(); // CHECK: double 0x7FF0000000000000
+ f = __builtin_huge_valf(); // CHECK: float +inf
+ d = __builtin_huge_val(); // CHECK: double +inf
ld = __builtin_huge_vall();
// While we can't manage the constants we use this test to give us LDTYPE
// for the rest of the tests
- // LD80: [[LDTYPE:x86_fp80]] [[LDHUGE:0xK7FFF8000000000000000]]
- // LD64: [[LDTYPE:double]] [[LDHUGE:0x7FF0000000000000]]
- f = __builtin_nanf(""); // CHECK: float 0x7FF8000000000000
- d = __builtin_nan(""); // CHECK: double 0x7FF8000000000000
- ld = __builtin_nanl("");
- // LD80: [[LDTYPE]] 0xK7FFFC000000000000000
- // LD64: [[LDTYPE]] 0x7FF8000000000000
- f = __builtin_nanf("0xAE98"); // CHECK: float 0x7FF815D300000000
- d = __builtin_nan("0xAE98"); // CHECK: double 0x7FF800000000AE98
- ld = __builtin_nanl("0xAE98");
- // LD80: [[LDTYPE]] 0xK7FFFC00000000000AE98
- // LD64: [[LDTYPE]] 0x7FF800000000AE98
- f = __builtin_nansf(""); // CHECK: float 0x7FF4000000000000
- d = __builtin_nans(""); // CHECK: double 0x7FF4000000000000
+ // LD80: [[LDTYPE:x86_fp80]] +inf
+ // LD64: [[LDTYPE:double]] +inf
+ f = __builtin_nanf(""); // CHECK: float +qnan
+ d = __builtin_nan(""); // CHECK: double +qnan
+ ld = __builtin_nanl(""); // CHECK: [[LDTYPE]] +qnan
+ f = __builtin_nanf("0xAE98"); // CHECK: float +nan(0xAE98)
+ d = __builtin_nan("0xAE98"); // CHECK: double +nan(0xAE98)
+ ld = __builtin_nanl("0xAE98"); // CHECK: [[LDTYPE]] +nan(0xAE98)
+ f = __builtin_nansf(""); // CHECK: float +snan(0x200000)
+ d = __builtin_nans(""); // CHECK: double +snan(0x4000000000000)
ld = __builtin_nansl("");
- // LD80: [[LDTYPE]] 0xK7FFFA000000000000000
- // LD64: [[LDTYPE]] 0x7FF4000000000000
- f = __builtin_nansf("0xAE98"); // CHECK: float 0x7FF015D300000000
- d = __builtin_nans("0xAE98"); // CHECK: double 0x7FF000000000AE98
- ld = __builtin_nansl("0xAE98");
- // LD80: [[LDTYPE]] 0xK7FFF800000000000AE98
- // LD64: [[LDTYPE]] 0x7FF000000000AE98
+ // LD80: [[LDTYPE]] +snan(0x2000000000000000)
+ // LD64: [[LDTYPE]] +snan(0x4000000000000)
+ f = __builtin_nansf("0xAE98"); // CHECK: float +snan(0xAE98)
+ d = __builtin_nans("0xAE98"); // CHECK: double +snan(0xAE98)
+ ld = __builtin_nansl("0xAE98");// CHECK: [[LDTYPE]] +snan(0xAE98)
}
// CHECK: }
@@ -284,7 +268,7 @@ void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
res = __builtin_isinf_sign(*H);
// CHECK: %[[ABS:.*]] = call half @llvm.fabs.f16(half %[[ARG:.*]])
- // CHECK: %[[ISINF:.*]] = fcmp oeq half %[[ABS]], 0xH7C00
+ // CHECK: %[[ISINF:.*]] = fcmp oeq half %[[ABS]], +inf
// CHECK: %[[BITCAST:.*]] = bitcast half %[[ARG]] to i16
// CHECK: %[[ISNEG:.*]] = icmp slt i16 %[[BITCAST]], 0
// CHECK: %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
@@ -292,7 +276,7 @@ void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
res = __builtin_isinf_sign(F);
// CHECK: %[[ABS:.*]] = call float @llvm.fabs.f32(float %[[ARG:.*]])
- // CHECK: %[[ISINF:.*]] = fcmp oeq float %[[ABS]], 0x7FF0000000000000
+ // CHECK: %[[ISINF:.*]] = fcmp oeq float %[[ABS]], +inf
// CHECK: %[[BITCAST:.*]] = bitcast float %[[ARG]] to i32
// CHECK: %[[ISNEG:.*]] = icmp slt i32 %[[BITCAST]], 0
// CHECK: %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
@@ -300,7 +284,7 @@ void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
res = __builtin_isinf_sign(D);
// CHECK: %[[ABS:.*]] = call double @llvm.fabs.f64(double %[[ARG:.*]])
- // CHECK: %[[ISINF:.*]] = fcmp oeq double %[[ABS]], 0x7FF0000000000000
+ // CHECK: %[[ISINF:.*]] = fcmp oeq double %[[ABS]], +inf
// CHECK: %[[BITCAST:.*]] = bitcast double %[[ARG]] to i64
// CHECK: %[[ISNEG:.*]] = icmp slt i64 %[[BITCAST]], 0
// CHECK: %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
@@ -308,7 +292,7 @@ void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
res = __builtin_isinf_sign(LD);
// CHECK: %[[ABS:.*]] = call [[LDTYPE]] @llvm.fabs.[[LDLLVMTY]]([[LDTYPE]] %[[ARG:.*]])
- // CHECK: %[[ISINF:.*]] = fcmp oeq [[LDTYPE]] %[[ABS]], [[LDHUGE]]
+ // CHECK: %[[ISINF:.*]] = fcmp oeq [[LDTYPE]] %[[ABS]], +inf
// LD80: %[[BITCAST:.*]] = bitcast [[LDTYPE]] %[[ARG]] to [[LDINTTY:i80]]
// LD64: %[[BITCAST:.*]] = bitcast [[LDTYPE]] %[[ARG]] to [[LDINTTY:i64]]
// CHECK: %[[ISNEG:.*]] = icmp slt [[LDINTTY]] %[[BITCAST]], 0
@@ -424,7 +408,7 @@ void test_float_builtin_ops(float F, double D, long double LD, int I) {
//FIXME: __builtin_fminimum_numl is not supported well yet.
resld = __builtin_fminimum_numl(1.0, 2.0);
- // LD80: store volatile x86_fp80 0xK3FFF8000000000000000, ptr %resld, align 16
+ // LD80: store volatile x86_fp80 1.000000e+00, ptr %resld, align 16
// LD64: store volatile double 1.000000e+00, ptr %resld
resf = __builtin_fmaximum_numf(F, F);
@@ -451,7 +435,7 @@ void test_float_builtin_ops(float F, double D, long double LD, int I) {
//FIXME: __builtin_fmaximum_numl is not supported well yet.
resld = __builtin_fmaximum_numl(1.0, 2.0);
- // LD80: store volatile x86_fp80 0xK40008000000000000000, ptr %resld, align 16
+ // LD80: store volatile x86_fp80 2.000000e+00, ptr %resld, align 16
// LD64: store volatile double 2.000000e+00, ptr %resld
resf = __builtin_fabsf(F);
diff --git a/clang/test/CodeGen/catch-undef-behavior.c b/clang/test/CodeGen/catch-undef-behavior.c
index 14cb7705c3783..f193a40d7b649 100644
--- a/clang/test/CodeGen/catch-undef-behavior.c
+++ b/clang/test/CodeGen/catch-undef-behavior.c
@@ -222,8 +222,8 @@ void int_fp16_overflow(int n, __fp16 *p) {
// CHECK-COMMON-LABEL: @float_int_overflow
int float_int_overflow(float f) {
- // CHECK-COMMON: %[[GE:.*]] = fcmp ogt float %[[F:.*]], 0xC1E0000020000000
- // CHECK-COMMON: %[[LE:.*]] = fcmp olt float %[[F]], 0x41E0000000000000
+ // CHECK-COMMON: %[[GE:.*]] = fcmp ogt float %[[F:.*]], f0xCF000001
+ // CHECK-COMMON: %[[LE:.*]] = fcmp olt float %[[F]], f0x4F000000
// CHECK-COMMON: %[[INBOUNDS:.*]] = and i1 %[[GE]], %[[LE]]
// CHECK-COMMON-NEXT: br i1 %[[INBOUNDS]]
@@ -241,8 +241,8 @@ int float_int_overflow(float f) {
int long_double_int_overflow(long double ld) {
// CHECK-UBSAN: alloca x86_fp80
- // CHECK-COMMON: %[[GE:.*]] = fcmp ogt x86_fp80 %[[F:.*]], 0xKC01E800000010000000
- // CHECK-COMMON: %[[LE:.*]] = fcmp olt x86_fp80 %[[F]], 0xK401E800000000000000
+ // CHECK-COMMON: %[[GE:.*]] = fcmp ogt x86_fp80 %[[F:.*]], f0xC01E8000000100000000
+ // CHECK-COMMON: %[[LE:.*]] = fcmp olt x86_fp80 %[[F]], f0x401E8000000000000000
// CHECK-COMMON: %[[INBOUNDS:.*]] = and i1 %[[GE]], %[[LE]]
// CHECK-COMMON-NEXT: br i1 %[[INBOUNDS]]
@@ -259,7 +259,7 @@ int long_double_int_overflow(long double ld) {
// CHECK-COMMON-LABEL: @float_uint_overflow
unsigned float_uint_overflow(float f) {
// CHECK-COMMON: %[[GE:.*]] = fcmp ogt float %[[F:.*]], -1.{{0*}}e+00
- // CHECK-COMMON: %[[LE:.*]] = fcmp olt float %[[F]], 0x41F0000000000000
+ // CHECK-COMMON: %[[LE:.*]] = fcmp olt float %[[F]], f0x4F800000
// CHECK-COMMON: %[[INBOUNDS:.*]] = and i1 %[[GE]], %[[LE]]
// CHECK-COMMON-NEXT: br i1 %[[INBOUNDS]]
diff --git a/clang/test/CodeGen/const-init.c b/clang/test/CodeGen/const-init.c
index 930cfab1e62b5..39def8e308976 100644
--- a/clang/test/CodeGen/const-init.c
+++ b/clang/test/CodeGen/const-init.c
@@ -188,7 +188,7 @@ void g31(void) {
// Clang should evaluate this in constant context, so floating point mode should
// have no effect.
-// CHECK: @.compoundliteral = internal global [1 x float] [float 0x3FB99999A0000000], align 4
+// CHECK: @.compoundliteral = internal global [1 x float] [float 1.000000e-01], align 4
struct { const float *floats; } compoundliteral = {
(float[1]) { 0.1, },
};
diff --git a/clang/test/Lexer/11-27-2007-FloatLiterals.c b/clang/test/Lexer/11-27-2007-FloatLiterals.c
index f3d978b06925c..a52cc5a818c92 100644
--- a/clang/test/Lexer/11-27-2007-FloatLiterals.c
+++ b/clang/test/Lexer/11-27-2007-FloatLiterals.c
@@ -1,10 +1,10 @@
// RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s
-// CHECK: 0x3BFD83C940000000
-// CHECK: 2.000000e+{{[0]*}}32
-// CHECK: 0x3BFD83C940000000
-// CHECK: 2.000000e+{{[0]*}}32
-// CHECK: 0x7FF0000000000000
+// CHECK: f0x1FEC1E4A
+// CHECK: 2.{{[0]*}}e+32
+// CHECK: f0x1FEC1E4A
+// CHECK: 2.{{[0]*}}e+32
+// CHECK: +inf
float F = 1e-19f;
double D = 2e32;
diff --git a/clang/test/OpenMP/declare_reduction_codegen.c b/clang/test/OpenMP/declare_reduction_codegen.c
index 1013290bc94a4..5df8bd0936107 100644
--- a/clang/test/OpenMP/declare_reduction_codegen.c
+++ b/clang/test/OpenMP/declare_reduction_codegen.c
@@ -56,7 +56,7 @@
// CHECK-NEXT: ret void
// CHECK-NEXT: }
// CHECK: define internal {{.*}}void @{{[^(]+}}(ptr noalias noundef %0, ptr noalias noundef %1)
-// CHECK: [[ADD:%.+]] = fadd float 1.5
+// CHECK: [[ADD:%.+]] = fadd float 1.500000e+01
// CHECK-NEXT: store float [[ADD]], ptr
// CHECK-NEXT: ret void
// CHECK-NEXT: }
@@ -66,7 +66,7 @@
// CHECK-LOAD-NEXT: ret void
// CHECK-LOAD-NEXT: }
// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(ptr noalias noundef %0, ptr noalias noundef %1)
-// CHECK-LOAD: [[ADD:%.+]] = fadd float 1.5
+// CHECK-LOAD: [[ADD:%.+]] = fadd float 1.500000e+01
// CHECK-LOAD-NEXT: store float [[ADD]], ptr
// CHECK-LOAD-NEXT: ret void
// CHECK-LOAD-NEXT: }
diff --git a/flang/test/Integration/complex-div-to-llvm-kind10.f90 b/flang/test/Integration/complex-div-to-llvm-kind10.f90
index 7211fed09296e..8ce920e3fc7e4 100644
--- a/flang/test/Integration/complex-div-to-llvm-kind10.f90
+++ b/flang/test/Integration/complex-div-to-llvm-kind10.f90
@@ -35,61 +35,61 @@
! Case 1. Zero denominator, numerator contains at most one NaN value.
! IMPRVD: %[[RHS_REAL_ABS:.*]] = call contract x86_fp80 @llvm.fabs.f80(x86_fp80 %[[RHS_REAL]])
-! IMPRVD: %[[RHS_REAL_ABS_IS_ZERO:.*]] = fcmp oeq x86_fp80 %[[RHS_REAL_ABS]], 0xK00000000000000000000
+! IMPRVD: %[[RHS_REAL_ABS_IS_ZERO:.*]] = fcmp oeq x86_fp80 %[[RHS_REAL_ABS]], 0.000000e+00
! IMPRVD: %[[RHS_IMAG_ABS:.*]] = call contract x86_fp80 @llvm.fabs.f80(x86_fp80 %[[RHS_IMAG]])
-! IMPRVD: %[[RHS_IMAG_ABS_IS_ZERO:.*]] = fcmp oeq x86_fp80 %[[RHS_IMAG_ABS]], 0xK00000000000000000000
-! IMPRVD: %[[LHS_REAL_IS_NOT_NAN:.*]] = fcmp ord x86_fp80 %[[LHS_REAL]], 0xK00000000000000000000
-! IMPRVD: %[[LHS_IMAG_IS_NOT_NAN:.*]] = fcmp ord x86_fp80 %[[LHS_IMAG]], 0xK00000000000000000000
+! IMPRVD: %[[RHS_IMAG_ABS_IS_ZERO:.*]] = fcmp oeq x86_fp80 %[[RHS_IMAG_ABS]], 0.000000e+00
+! IMPRVD: %[[LHS_REAL_IS_NOT_NAN:.*]] = fcmp ord x86_fp80 %[[LHS_REAL]], 0.000000e+00
+! IMPRVD: %[[LHS_IMAG_IS_NOT_NAN:.*]] = fcmp ord x86_fp80 %[[LHS_IMAG]], 0.000000e+00
! IMPRVD: %[[LHS_CONTAINS_NOT_NAN_VALUE:.*]] = or i1 %[[LHS_REAL_IS_NOT_NAN]], %[[LHS_IMAG_IS_NOT_NAN]]
! IMPRVD: %[[RHS_IS_ZERO:.*]] = and i1 %[[RHS_REAL_ABS_IS_ZERO]], %[[RHS_IMAG_ABS_IS_ZERO]]
! IMPRVD: %[[RESULT_IS_INFINITY:.*]] = and i1 %[[LHS_CONTAINS_NOT_NAN_VALUE]], %[[RHS_IS_ZERO]]
-! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 0xK7FFF8000000000000000, x86_fp80 %[[RHS_REAL]])
+! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 +inf, x86_fp80 %[[RHS_REAL]])
! IMPRVD: %[[INFINITY_RESULT_REAL:.*]] = fmul contract x86_fp80 %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_REAL]]
! IMPRVD: %[[INFINITY_RESULT_IMAG:.*]] = fmul contract x86_fp80 %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_IMAG]]
! Case 2. Infinite numerator, finite denominator.
-! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one x86_fp80 %[[RHS_REAL_ABS]], 0xK7FFF8000000000000000
-! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one x86_fp80 %[[RHS_IMAG_ABS]], 0xK7FFF8000000000000000
+! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one x86_fp80 %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one x86_fp80 %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_FINITE:.*]] = and i1 %[[RHS_REAL_FINITE]], %[[RHS_IMAG_FINITE]]
! IMPRVD: %[[LHS_REAL_ABS:.*]] = call contract x86_fp80 @llvm.fabs.f80(x86_fp80 %[[LHS_REAL]])
-! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq x86_fp80 %[[LHS_REAL_ABS]], 0xK7FFF8000000000000000
+! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq x86_fp80 %[[LHS_REAL_ABS]], +inf
! IMPRVD: %[[LHS_IMAG_ABS:.*]] = call contract x86_fp80 @llvm.fabs.f80(x86_fp80 %[[LHS_IMAG]])
-! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq x86_fp80 %[[LHS_IMAG_ABS]], 0xK7FFF8000000000000000
+! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq x86_fp80 %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_INFINITE:.*]] = or i1 %[[LHS_REAL_INFINITE]], %[[LHS_IMAG_INFINITE]]
! IMPRVD: %[[INF_NUM_FINITE_DENOM:.*]] = and i1 %[[LHS_IS_INFINITE]], %[[RHS_IS_FINITE]]
-! IMPRVD: %[[LHS_REAL_IS_INF:.*]] = select i1 %[[LHS_REAL_INFINITE]], x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK00000000000000000000
+! IMPRVD: %[[LHS_REAL_IS_INF:.*]] = select i1 %[[LHS_REAL_INFINITE]], x86_fp80 1.000000e+00, x86_fp80 0.000000e+00
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN:.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 %[[LHS_REAL_IS_INF]], x86_fp80 %[[LHS_REAL]])
-! IMPRVD: %[[LHS_IMAG_IS_INF:.*]] = select i1 %[[LHS_IMAG_INFINITE]], x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK00000000000000000000
+! IMPRVD: %[[LHS_IMAG_IS_INF:.*]] = select i1 %[[LHS_IMAG_INFINITE]], x86_fp80 1.000000e+00, x86_fp80 0.000000e+00
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN:.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 %[[LHS_IMAG_IS_INF]], x86_fp80 %[[LHS_IMAG]])
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract x86_fp80 %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract x86_fp80 %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[INF_MULTIPLICATOR_1:.*]] = fadd contract x86_fp80 %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract x86_fp80 %[[INF_MULTIPLICATOR_1]], 0xK7FFF8000000000000000
+! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract x86_fp80 %[[INF_MULTIPLICATOR_1]], +inf
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract x86_fp80 %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract x86_fp80 %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[INF_MULTIPLICATOR_2:.*]] = fsub contract x86_fp80 %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract x86_fp80 %[[INF_MULTIPLICATOR_2]], 0xK7FFF8000000000000000
+! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract x86_fp80 %[[INF_MULTIPLICATOR_2]], +inf
! Case 3. Finite numerator, infinite denominator.
-! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one x86_fp80 %[[LHS_REAL_ABS]], 0xK7FFF8000000000000000
-! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one x86_fp80 %[[LHS_IMAG_ABS]], 0xK7FFF8000000000000000
+! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one x86_fp80 %[[LHS_REAL_ABS]], +inf
+! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one x86_fp80 %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_FINITE:.*]] = and i1 %[[LHS_REAL_FINITE]], %[[LHS_IMAG_FINITE]]
-! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq x86_fp80 %[[RHS_REAL_ABS]], 0xK7FFF8000000000000000
-! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq x86_fp80 %[[RHS_IMAG_ABS]], 0xK7FFF8000000000000000
+! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq x86_fp80 %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq x86_fp80 %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_INFINITE:.*]] = or i1 %[[RHS_REAL_INFINITE]], %[[RHS_IMAG_INFINITE]]
! IMPRVD: %[[FINITE_NUM_INFINITE_DENOM:.*]] = and i1 %[[LHS_IS_FINITE]], %[[RHS_IS_INFINITE]]
-! IMPRVD: %[[RHS_REAL_IS_INF:.*]] = select i1 %[[RHS_REAL_INFINITE]], x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK00000000000000000000
+! IMPRVD: %[[RHS_REAL_IS_INF:.*]] = select i1 %[[RHS_REAL_INFINITE]], x86_fp80 1.000000e+00, x86_fp80 0.000000e+00
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN:.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 %[[RHS_REAL_IS_INF]], x86_fp80 %[[RHS_REAL]])
-! IMPRVD: %[[RHS_IMAG_IS_INF:.*]] = select i1 %[[RHS_IMAG_INFINITE]], x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK00000000000000000000
+! IMPRVD: %[[RHS_IMAG_IS_INF:.*]] = select i1 %[[RHS_IMAG_INFINITE]], x86_fp80 1.000000e+00, x86_fp80 0.000000e+00
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN:.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 %[[RHS_IMAG_IS_INF]], x86_fp80 %[[RHS_IMAG]])
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_REAL:.*]] = fmul contract x86_fp80 %[[LHS_REAL]], %[[RHS_REAL_IS_INF_WITH_SIGN]]
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_IMAG:.*]] = fmul contract x86_fp80 %[[LHS_IMAG]], %[[RHS_IMAG_IS_INF_WITH_SIGN]]
! IMPRVD: %[[ZERO_MULTIPLICATOR_1:.*]] = fadd contract x86_fp80 %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_REAL]], %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_IMAG]]
-! IMPRVD: %[[RESULT_REAL_4:.*]] = fmul contract x86_fp80 %[[ZERO_MULTIPLICATOR_1]], 0xK00000000000000000000
+! IMPRVD: %[[RESULT_REAL_4:.*]] = fmul contract x86_fp80 %[[ZERO_MULTIPLICATOR_1]], 0.000000e+00
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_IMAG:.*]] = fmul contract x86_fp80 %[[LHS_IMAG]], %[[RHS_REAL_IS_INF_WITH_SIGN]]
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_REAL:.*]] = fmul contract x86_fp80 %[[LHS_REAL]], %[[RHS_IMAG_IS_INF_WITH_SIGN]]
! IMPRVD: %[[ZERO_MULTIPLICATOR_2:.*]] = fsub contract x86_fp80 %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_IMAG]], %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_REAL]]
-! IMPRVD: %[[RESULT_IMAG_4:.*]] = fmul contract x86_fp80 %[[ZERO_MULTIPLICATOR_2]], 0xK00000000000000000000
+! IMPRVD: %[[RESULT_IMAG_4:.*]] = fmul contract x86_fp80 %[[ZERO_MULTIPLICATOR_2]], 0.000000e+00
! IMPRVD: %[[REAL_ABS_SMALLER_THAN_IMAG_ABS:.*]] = fcmp olt x86_fp80 %[[RHS_REAL_ABS]], %[[RHS_IMAG_ABS]]
! IMPRVD: %[[RESULT_REAL:.*]] = select i1 %[[REAL_ABS_SMALLER_THAN_IMAG_ABS]], x86_fp80 %[[RESULT_REAL_1]], x86_fp80 %[[RESULT_REAL_2]]
@@ -100,8 +100,8 @@
! IMPRVD: %[[RESULT_IMAG_SPECIAL_CASE_2:.*]] = select i1 %[[INF_NUM_FINITE_DENOM]], x86_fp80 %[[RESULT_IMAG_3]], x86_fp80 %[[RESULT_IMAG_SPECIAL_CASE_3]]
! IMPRVD: %[[RESULT_REAL_SPECIAL_CASE_1:.*]] = select i1 %[[RESULT_IS_INFINITY]], x86_fp80 %[[INFINITY_RESULT_REAL]], x86_fp80 %[[RESULT_REAL_SPECIAL_CASE_2]]
! IMPRVD: %[[RESULT_IMAG_SPECIAL_CASE_1:.*]] = select i1 %[[RESULT_IS_INFINITY]], x86_fp80 %[[INFINITY_RESULT_IMAG]], x86_fp80 %[[RESULT_IMAG_SPECIAL_CASE_2]]
-! IMPRVD: %[[RESULT_REAL_IS_NAN:.*]] = fcmp uno x86_fp80 %[[RESULT_REAL]], 0xK00000000000000000000
-! IMPRVD: %[[RESULT_IMAG_IS_NAN:.*]] = fcmp uno x86_fp80 %[[RESULT_IMAG]], 0xK00000000000000000000
+! IMPRVD: %[[RESULT_REAL_IS_NAN:.*]] = fcmp uno x86_fp80 %[[RESULT_REAL]], 0.000000e+00
+! IMPRVD: %[[RESULT_IMAG_IS_NAN:.*]] = fcmp uno x86_fp80 %[[RESULT_IMAG]], 0.000000e+00
! IMPRVD: %[[RESULT_IS_NAN:.*]] = and i1 %[[RESULT_REAL_IS_NAN]], %[[RESULT_IMAG_IS_NAN]]
! IMPRVD: %[[RESULT_REAL_WITH_SPECIAL_CASES:.*]] = select i1 %[[RESULT_IS_NAN]], x86_fp80 %[[RESULT_REAL_SPECIAL_CASE_1]], x86_fp80 %[[RESULT_REAL]]
! IMPRVD: %[[RESULT_IMAG_WITH_SPECIAL_CASES:.*]] = select i1 %[[RESULT_IS_NAN]], x86_fp80 %[[RESULT_IMAG_SPECIAL_CASE_1]], x86_fp80 %[[RESULT_IMAG]]
diff --git a/flang/test/Integration/complex-div-to-llvm.f90 b/flang/test/Integration/complex-div-to-llvm.f90
index 96af1e6bedb94..9a54812424e58 100644
--- a/flang/test/Integration/complex-div-to-llvm.f90
+++ b/flang/test/Integration/complex-div-to-llvm.f90
@@ -34,61 +34,61 @@
! Case 1. Zero denominator, numerator contains at most one NaN value.
! IMPRVD: %[[RHS_REAL_ABS:.*]] = call contract half @llvm.fabs.f16(half %[[RHS_REAL]])
-! IMPRVD: %[[RHS_REAL_ABS_IS_ZERO:.*]] = fcmp oeq half %[[RHS_REAL_ABS]], 0xH0000
+! IMPRVD: %[[RHS_REAL_ABS_IS_ZERO:.*]] = fcmp oeq half %[[RHS_REAL_ABS]], 0.000000e+00
! IMPRVD: %[[RHS_IMAG_ABS:.*]] = call contract half @llvm.fabs.f16(half %[[RHS_IMAG]])
-! IMPRVD: %[[RHS_IMAG_ABS_IS_ZERO:.*]] = fcmp oeq half %[[RHS_IMAG_ABS]], 0xH0000
-! IMPRVD: %[[LHS_REAL_IS_NOT_NAN:.*]] = fcmp ord half %[[LHS_REAL]], 0xH0000
-! IMPRVD: %[[LHS_IMAG_IS_NOT_NAN:.*]] = fcmp ord half %[[LHS_IMAG]], 0xH0000
+! IMPRVD: %[[RHS_IMAG_ABS_IS_ZERO:.*]] = fcmp oeq half %[[RHS_IMAG_ABS]], 0.000000e+00
+! IMPRVD: %[[LHS_REAL_IS_NOT_NAN:.*]] = fcmp ord half %[[LHS_REAL]], 0.000000e+00
+! IMPRVD: %[[LHS_IMAG_IS_NOT_NAN:.*]] = fcmp ord half %[[LHS_IMAG]], 0.000000e+00
! IMPRVD: %[[LHS_CONTAINS_NOT_NAN_VALUE:.*]] = or i1 %[[LHS_REAL_IS_NOT_NAN]], %[[LHS_IMAG_IS_NOT_NAN]]
! IMPRVD: %[[RHS_IS_ZERO:.*]] = and i1 %[[RHS_REAL_ABS_IS_ZERO]], %[[RHS_IMAG_ABS_IS_ZERO]]
! IMPRVD: %[[RESULT_IS_INFINITY:.*]] = and i1 %[[LHS_CONTAINS_NOT_NAN_VALUE]], %[[RHS_IS_ZERO]]
-! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call half @llvm.copysign.f16(half 0xH7C00, half %[[RHS_REAL]])
+! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call half @llvm.copysign.f16(half +inf, half %[[RHS_REAL]])
! IMPRVD: %[[INFINITY_RESULT_REAL:.*]] = fmul contract half %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_REAL]]
! IMPRVD: %[[INFINITY_RESULT_IMAG:.*]] = fmul contract half %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_IMAG]]
! Case 2. Infinite numerator, finite denominator.
-! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one half %[[RHS_REAL_ABS]], 0xH7C00
-! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one half %[[RHS_IMAG_ABS]], 0xH7C00
+! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one half %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one half %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_FINITE:.*]] = and i1 %[[RHS_REAL_FINITE]], %[[RHS_IMAG_FINITE]]
! IMPRVD: %[[LHS_REAL_ABS:.*]] = call contract half @llvm.fabs.f16(half %[[LHS_REAL]])
-! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq half %[[LHS_REAL_ABS]], 0xH7C00
+! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq half %[[LHS_REAL_ABS]], +inf
! IMPRVD: %[[LHS_IMAG_ABS:.*]] = call contract half @llvm.fabs.f16(half %[[LHS_IMAG]])
-! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq half %[[LHS_IMAG_ABS]], 0xH7C00
+! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq half %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_INFINITE:.*]] = or i1 %[[LHS_REAL_INFINITE]], %[[LHS_IMAG_INFINITE]]
! IMPRVD: %[[INF_NUM_FINITE_DENOM:.*]] = and i1 %[[LHS_IS_INFINITE]], %[[RHS_IS_FINITE]]
-! IMPRVD: %[[LHS_REAL_IS_INF:.*]] = select i1 %[[LHS_REAL_INFINITE]], half 0xH3C00, half 0xH0000
+! IMPRVD: %[[LHS_REAL_IS_INF:.*]] = select i1 %[[LHS_REAL_INFINITE]], half 1.000000e+00, half 0.000000e+00
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN:.*]] = call half @llvm.copysign.f16(half %[[LHS_REAL_IS_INF]], half %[[LHS_REAL]])
-! IMPRVD: %[[LHS_IMAG_IS_INF:.*]] = select i1 %[[LHS_IMAG_INFINITE]], half 0xH3C00, half 0xH0000
+! IMPRVD: %[[LHS_IMAG_IS_INF:.*]] = select i1 %[[LHS_IMAG_INFINITE]], half 1.000000e+00, half 0.000000e+00
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN:.*]] = call half @llvm.copysign.f16(half %[[LHS_IMAG_IS_INF]], half %[[LHS_IMAG]])
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract half %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract half %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[INF_MULTIPLICATOR_1:.*]] = fadd contract half %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract half %[[INF_MULTIPLICATOR_1]], 0xH7C00
+! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract half %[[INF_MULTIPLICATOR_1]], +inf
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract half %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract half %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[INF_MULTIPLICATOR_2:.*]] = fsub contract half %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract half %[[INF_MULTIPLICATOR_2]], 0xH7C00
+! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract half %[[INF_MULTIPLICATOR_2]], +inf
! Case 3. Finite numerator, infinite denominator.
-! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one half %[[LHS_REAL_ABS]], 0xH7C00
-! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one half %[[LHS_IMAG_ABS]], 0xH7C00
+! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one half %[[LHS_REAL_ABS]], +inf
+! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one half %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_FINITE:.*]] = and i1 %[[LHS_REAL_FINITE]], %[[LHS_IMAG_FINITE]]
-! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq half %[[RHS_REAL_ABS]], 0xH7C00
-! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq half %[[RHS_IMAG_ABS]], 0xH7C00
+! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq half %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq half %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_INFINITE:.*]] = or i1 %[[RHS_REAL_INFINITE]], %[[RHS_IMAG_INFINITE]]
! IMPRVD: %[[FINITE_NUM_INFINITE_DENOM:.*]] = and i1 %[[LHS_IS_FINITE]], %[[RHS_IS_INFINITE]]
-! IMPRVD: %[[RHS_REAL_IS_INF:.*]] = select i1 %[[RHS_REAL_INFINITE]], half 0xH3C00, half 0xH0000
+! IMPRVD: %[[RHS_REAL_IS_INF:.*]] = select i1 %[[RHS_REAL_INFINITE]], half 1.000000e+00, half 0.000000e+00
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN:.*]] = call half @llvm.copysign.f16(half %[[RHS_REAL_IS_INF]], half %[[RHS_REAL]])
-! IMPRVD: %[[RHS_IMAG_IS_INF:.*]] = select i1 %[[RHS_IMAG_INFINITE]], half 0xH3C00, half 0xH0000
+! IMPRVD: %[[RHS_IMAG_IS_INF:.*]] = select i1 %[[RHS_IMAG_INFINITE]], half 1.000000e+00, half 0.000000e+00
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN:.*]] = call half @llvm.copysign.f16(half %[[RHS_IMAG_IS_INF]], half %[[RHS_IMAG]])
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_REAL:.*]] = fmul contract half %[[LHS_REAL]], %[[RHS_REAL_IS_INF_WITH_SIGN]]
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_IMAG:.*]] = fmul contract half %[[LHS_IMAG]], %[[RHS_IMAG_IS_INF_WITH_SIGN]]
! IMPRVD: %[[ZERO_MULTIPLICATOR_1:.*]] = fadd contract half %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_REAL]], %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_IMAG]]
-! IMPRVD: %[[RESULT_REAL_4:.*]] = fmul contract half %[[ZERO_MULTIPLICATOR_1]], 0xH0000
+! IMPRVD: %[[RESULT_REAL_4:.*]] = fmul contract half %[[ZERO_MULTIPLICATOR_1]], 0.000000e+00
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_IMAG:.*]] = fmul contract half %[[LHS_IMAG]], %[[RHS_REAL_IS_INF_WITH_SIGN]]
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_REAL:.*]] = fmul contract half %[[LHS_REAL]], %[[RHS_IMAG_IS_INF_WITH_SIGN]]
! IMPRVD: %[[ZERO_MULTIPLICATOR_2:.*]] = fsub contract half %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_IMAG]], %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_REAL]]
-! IMPRVD: %[[RESULT_IMAG_4:.*]] = fmul contract half %[[ZERO_MULTIPLICATOR_2]], 0xH0000
+! IMPRVD: %[[RESULT_IMAG_4:.*]] = fmul contract half %[[ZERO_MULTIPLICATOR_2]], 0.000000e+00
! IMPRVD: %[[REAL_ABS_SMALLER_THAN_IMAG_ABS:.*]] = fcmp olt half %[[RHS_REAL_ABS]], %[[RHS_IMAG_ABS]]
! IMPRVD: %[[RESULT_REAL:.*]] = select i1 %[[REAL_ABS_SMALLER_THAN_IMAG_ABS]], half %[[RESULT_REAL_1]], half %[[RESULT_REAL_2]]
@@ -99,8 +99,8 @@
! IMPRVD: %[[RESULT_IMAG_SPECIAL_CASE_2:.*]] = select i1 %[[INF_NUM_FINITE_DENOM]], half %[[RESULT_IMAG_3]], half %[[RESULT_IMAG_SPECIAL_CASE_3]]
! IMPRVD: %[[RESULT_REAL_SPECIAL_CASE_1:.*]] = select i1 %[[RESULT_IS_INFINITY]], half %[[INFINITY_RESULT_REAL]], half %[[RESULT_REAL_SPECIAL_CASE_2]]
! IMPRVD: %[[RESULT_IMAG_SPECIAL_CASE_1:.*]] = select i1 %[[RESULT_IS_INFINITY]], half %[[INFINITY_RESULT_IMAG]], half %[[RESULT_IMAG_SPECIAL_CASE_2]]
-! IMPRVD: %[[RESULT_REAL_IS_NAN:.*]] = fcmp uno half %[[RESULT_REAL]], 0xH0000
-! IMPRVD: %[[RESULT_IMAG_IS_NAN:.*]] = fcmp uno half %[[RESULT_IMAG]], 0xH0000
+! IMPRVD: %[[RESULT_REAL_IS_NAN:.*]] = fcmp uno half %[[RESULT_REAL]], 0.000000e+00
+! IMPRVD: %[[RESULT_IMAG_IS_NAN:.*]] = fcmp uno half %[[RESULT_IMAG]], 0.000000e+00
! IMPRVD: %[[RESULT_IS_NAN:.*]] = and i1 %[[RESULT_REAL_IS_NAN]], %[[RESULT_IMAG_IS_NAN]]
! IMPRVD: %[[RESULT_REAL_WITH_SPECIAL_CASES:.*]] = select i1 %[[RESULT_IS_NAN]], half %[[RESULT_REAL_SPECIAL_CASE_1]], half %[[RESULT_REAL]]
! IMPRVD: %[[RESULT_IMAG_WITH_SPECIAL_CASES:.*]] = select i1 %[[RESULT_IS_NAN]], half %[[RESULT_IMAG_SPECIAL_CASE_1]], half %[[RESULT_IMAG]]
@@ -160,61 +160,61 @@ end subroutine div_test_half
! Case 1. Zero denominator, numerator contains at most one NaN value.
! IMPRVD: %[[RHS_REAL_ABS:.*]] = call contract bfloat @llvm.fabs.bf16(bfloat %[[RHS_REAL]])
-! IMPRVD: %[[RHS_REAL_ABS_IS_ZERO:.*]] = fcmp oeq bfloat %[[RHS_REAL_ABS]], 0xR0000
+! IMPRVD: %[[RHS_REAL_ABS_IS_ZERO:.*]] = fcmp oeq bfloat %[[RHS_REAL_ABS]], 0.000000e+00
! IMPRVD: %[[RHS_IMAG_ABS:.*]] = call contract bfloat @llvm.fabs.bf16(bfloat %[[RHS_IMAG]])
-! IMPRVD: %[[RHS_IMAG_ABS_IS_ZERO:.*]] = fcmp oeq bfloat %[[RHS_IMAG_ABS]], 0xR0000
-! IMPRVD: %[[LHS_REAL_IS_NOT_NAN:.*]] = fcmp ord bfloat %[[LHS_REAL]], 0xR0000
-! IMPRVD: %[[LHS_IMAG_IS_NOT_NAN:.*]] = fcmp ord bfloat %[[LHS_IMAG]], 0xR0000
+! IMPRVD: %[[RHS_IMAG_ABS_IS_ZERO:.*]] = fcmp oeq bfloat %[[RHS_IMAG_ABS]], 0.000000e+00
+! IMPRVD: %[[LHS_REAL_IS_NOT_NAN:.*]] = fcmp ord bfloat %[[LHS_REAL]], 0.000000e+00
+! IMPRVD: %[[LHS_IMAG_IS_NOT_NAN:.*]] = fcmp ord bfloat %[[LHS_IMAG]], 0.000000e+00
! IMPRVD: %[[LHS_CONTAINS_NOT_NAN_VALUE:.*]] = or i1 %[[LHS_REAL_IS_NOT_NAN]], %[[LHS_IMAG_IS_NOT_NAN]]
! IMPRVD: %[[RHS_IS_ZERO:.*]] = and i1 %[[RHS_REAL_ABS_IS_ZERO]], %[[RHS_IMAG_ABS_IS_ZERO]]
! IMPRVD: %[[RESULT_IS_INFINITY:.*]] = and i1 %[[LHS_CONTAINS_NOT_NAN_VALUE]], %[[RHS_IS_ZERO]]
-! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call bfloat @llvm.copysign.bf16(bfloat 0xR7F80, bfloat %[[RHS_REAL]])
+! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call bfloat @llvm.copysign.bf16(bfloat +inf, bfloat %[[RHS_REAL]])
! IMPRVD: %[[INFINITY_RESULT_REAL:.*]] = fmul contract bfloat %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_REAL]]
! IMPRVD: %[[INFINITY_RESULT_IMAG:.*]] = fmul contract bfloat %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_IMAG]]
! Case 2. Infinite numerator, finite denominator.
-! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one bfloat %[[RHS_REAL_ABS]], 0xR7F80
-! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one bfloat %[[RHS_IMAG_ABS]], 0xR7F80
+! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one bfloat %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one bfloat %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_FINITE:.*]] = and i1 %[[RHS_REAL_FINITE]], %[[RHS_IMAG_FINITE]]
! IMPRVD: %[[LHS_REAL_ABS:.*]] = call contract bfloat @llvm.fabs.bf16(bfloat %[[LHS_REAL]])
-! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq bfloat %[[LHS_REAL_ABS]], 0xR7F80
+! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq bfloat %[[LHS_REAL_ABS]], +inf
! IMPRVD: %[[LHS_IMAG_ABS:.*]] = call contract bfloat @llvm.fabs.bf16(bfloat %[[LHS_IMAG]])
-! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq bfloat %[[LHS_IMAG_ABS]], 0xR7F80
+! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq bfloat %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_INFINITE:.*]] = or i1 %[[LHS_REAL_INFINITE]], %[[LHS_IMAG_INFINITE]]
! IMPRVD: %[[INF_NUM_FINITE_DENOM:.*]] = and i1 %[[LHS_IS_INFINITE]], %[[RHS_IS_FINITE]]
-! IMPRVD: %[[LHS_REAL_IS_INF:.*]] = select i1 %[[LHS_REAL_INFINITE]], bfloat 0xR3F80, bfloat 0xR0000
+! IMPRVD: %[[LHS_REAL_IS_INF:.*]] = select i1 %[[LHS_REAL_INFINITE]], bfloat 1.000000e+00, bfloat 0.000000e+00
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN:.*]] = call bfloat @llvm.copysign.bf16(bfloat %[[LHS_REAL_IS_INF]], bfloat %[[LHS_REAL]])
-! IMPRVD: %[[LHS_IMAG_IS_INF:.*]] = select i1 %[[LHS_IMAG_INFINITE]], bfloat 0xR3F80, bfloat 0xR0000
+! IMPRVD: %[[LHS_IMAG_IS_INF:.*]] = select i1 %[[LHS_IMAG_INFINITE]], bfloat 1.000000e+00, bfloat 0.000000e+00
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN:.*]] = call bfloat @llvm.copysign.bf16(bfloat %[[LHS_IMAG_IS_INF]], bfloat %[[LHS_IMAG]])
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract bfloat %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract bfloat %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[INF_MULTIPLICATOR_1:.*]] = fadd contract bfloat %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract bfloat %[[INF_MULTIPLICATOR_1]], 0xR7F80
+! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract bfloat %[[INF_MULTIPLICATOR_1]], +inf
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract bfloat %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract bfloat %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[INF_MULTIPLICATOR_2:.*]] = fsub contract bfloat %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract bfloat %[[INF_MULTIPLICATOR_2]], 0xR7F80
+! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract bfloat %[[INF_MULTIPLICATOR_2]], +inf
! Case 3. Finite numerator, infinite denominator.
-! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one bfloat %[[LHS_REAL_ABS]], 0xR7F80
-! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one bfloat %[[LHS_IMAG_ABS]], 0xR7F80
+! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one bfloat %[[LHS_REAL_ABS]], +inf
+! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one bfloat %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_FINITE:.*]] = and i1 %[[LHS_REAL_FINITE]], %[[LHS_IMAG_FINITE]]
-! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq bfloat %[[RHS_REAL_ABS]], 0xR7F80
-! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq bfloat %[[RHS_IMAG_ABS]], 0xR7F80
+! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq bfloat %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq bfloat %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_INFINITE:.*]] = or i1 %[[RHS_REAL_INFINITE]], %[[RHS_IMAG_INFINITE]]
! IMPRVD: %[[FINITE_NUM_INFINITE_DENOM:.*]] = and i1 %[[LHS_IS_FINITE]], %[[RHS_IS_INFINITE]]
-! IMPRVD: %[[RHS_REAL_IS_INF:.*]] = select i1 %[[RHS_REAL_INFINITE]], bfloat 0xR3F80, bfloat 0xR0000
+! IMPRVD: %[[RHS_REAL_IS_INF:.*]] = select i1 %[[RHS_REAL_INFINITE]], bfloat 1.000000e+00, bfloat 0.000000e+00
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN:.*]] = call bfloat @llvm.copysign.bf16(bfloat %[[RHS_REAL_IS_INF]], bfloat %[[RHS_REAL]])
-! IMPRVD: %[[RHS_IMAG_IS_INF:.*]] = select i1 %[[RHS_IMAG_INFINITE]], bfloat 0xR3F80, bfloat 0xR0000
+! IMPRVD: %[[RHS_IMAG_IS_INF:.*]] = select i1 %[[RHS_IMAG_INFINITE]], bfloat 1.000000e+00, bfloat 0.000000e+00
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN:.*]] = call bfloat @llvm.copysign.bf16(bfloat %[[RHS_IMAG_IS_INF]], bfloat %[[RHS_IMAG]])
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_REAL:.*]] = fmul contract bfloat %[[LHS_REAL]], %[[RHS_REAL_IS_INF_WITH_SIGN]]
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_IMAG:.*]] = fmul contract bfloat %[[LHS_IMAG]], %[[RHS_IMAG_IS_INF_WITH_SIGN]]
! IMPRVD: %[[ZERO_MULTIPLICATOR_1:.*]] = fadd contract bfloat %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_REAL]], %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_IMAG]]
-! IMPRVD: %[[RESULT_REAL_4:.*]] = fmul contract bfloat %[[ZERO_MULTIPLICATOR_1]], 0xR0000
+! IMPRVD: %[[RESULT_REAL_4:.*]] = fmul contract bfloat %[[ZERO_MULTIPLICATOR_1]], 0.000000e+00
! IMPRVD: %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_IMAG:.*]] = fmul contract bfloat %[[LHS_IMAG]], %[[RHS_REAL_IS_INF_WITH_SIGN]]
! IMPRVD: %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_REAL:.*]] = fmul contract bfloat %[[LHS_REAL]], %[[RHS_IMAG_IS_INF_WITH_SIGN]]
! IMPRVD: %[[ZERO_MULTIPLICATOR_2:.*]] = fsub contract bfloat %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_IMAG]], %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_REAL]]
-! IMPRVD: %[[RESULT_IMAG_4:.*]] = fmul contract bfloat %[[ZERO_MULTIPLICATOR_2]], 0xR0000
+! IMPRVD: %[[RESULT_IMAG_4:.*]] = fmul contract bfloat %[[ZERO_MULTIPLICATOR_2]], 0.000000e+00
! IMPRVD: %[[REAL_ABS_SMALLER_THAN_IMAG_ABS:.*]] = fcmp olt bfloat %[[RHS_REAL_ABS]], %[[RHS_IMAG_ABS]]
! IMPRVD: %[[RESULT_REAL:.*]] = select i1 %[[REAL_ABS_SMALLER_THAN_IMAG_ABS]], bfloat %[[RESULT_REAL_1]], bfloat %[[RESULT_REAL_2]]
@@ -225,8 +225,8 @@ end subroutine div_test_half
! IMPRVD: %[[RESULT_IMAG_SPECIAL_CASE_2:.*]] = select i1 %[[INF_NUM_FINITE_DENOM]], bfloat %[[RESULT_IMAG_3]], bfloat %[[RESULT_IMAG_SPECIAL_CASE_3]]
! IMPRVD: %[[RESULT_REAL_SPECIAL_CASE_1:.*]] = select i1 %[[RESULT_IS_INFINITY]], bfloat %[[INFINITY_RESULT_REAL]], bfloat %[[RESULT_REAL_SPECIAL_CASE_2]]
! IMPRVD: %[[RESULT_IMAG_SPECIAL_CASE_1:.*]] = select i1 %[[RESULT_IS_INFINITY]], bfloat %[[INFINITY_RESULT_IMAG]], bfloat %[[RESULT_IMAG_SPECIAL_CASE_2]]
-! IMPRVD: %[[RESULT_REAL_IS_NAN:.*]] = fcmp uno bfloat %[[RESULT_REAL]], 0xR0000
-! IMPRVD: %[[RESULT_IMAG_IS_NAN:.*]] = fcmp uno bfloat %[[RESULT_IMAG]], 0xR0000
+! IMPRVD: %[[RESULT_REAL_IS_NAN:.*]] = fcmp uno bfloat %[[RESULT_REAL]], 0.000000e+00
+! IMPRVD: %[[RESULT_IMAG_IS_NAN:.*]] = fcmp uno bfloat %[[RESULT_IMAG]], 0.000000e+00
! IMPRVD: %[[RESULT_IS_NAN:.*]] = and i1 %[[RESULT_REAL_IS_NAN]], %[[RESULT_IMAG_IS_NAN]]
! IMPRVD: %[[RESULT_REAL_WITH_SPECIAL_CASES:.*]] = select i1 %[[RESULT_IS_NAN]], bfloat %[[RESULT_REAL_SPECIAL_CASE_1]], bfloat %[[RESULT_REAL]]
! IMPRVD: %[[RESULT_IMAG_WITH_SPECIAL_CASES:.*]] = select i1 %[[RESULT_IS_NAN]], bfloat %[[RESULT_IMAG_SPECIAL_CASE_1]], bfloat %[[RESULT_IMAG]]
@@ -294,18 +294,18 @@ end subroutine div_test_bfloat
! IMPRVD: %[[LHS_CONTAINS_NOT_NAN_VALUE:.*]] = or i1 %[[LHS_REAL_IS_NOT_NAN]], %[[LHS_IMAG_IS_NOT_NAN]]
! IMPRVD: %[[RHS_IS_ZERO:.*]] = and i1 %[[RHS_REAL_ABS_IS_ZERO]], %[[RHS_IMAG_ABS_IS_ZERO]]
! IMPRVD: %[[RESULT_IS_INFINITY:.*]] = and i1 %[[LHS_CONTAINS_NOT_NAN_VALUE]], %[[RHS_IS_ZERO]]
-! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call float @llvm.copysign.f32(float 0x7FF0000000000000, float %[[RHS_REAL]])
+! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call float @llvm.copysign.f32(float +inf, float %[[RHS_REAL]])
! IMPRVD: %[[INFINITY_RESULT_REAL:.*]] = fmul contract float %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_REAL]]
! IMPRVD: %[[INFINITY_RESULT_IMAG:.*]] = fmul contract float %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_IMAG]]
! Case 2. Infinite numerator, finite denominator.
-! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one float %[[RHS_REAL_ABS]], 0x7FF0000000000000
-! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one float %[[RHS_IMAG_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one float %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one float %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_FINITE:.*]] = and i1 %[[RHS_REAL_FINITE]], %[[RHS_IMAG_FINITE]]
! IMPRVD: %[[LHS_REAL_ABS:.*]] = call contract float @llvm.fabs.f32(float %[[LHS_REAL]])
-! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq float %[[LHS_REAL_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq float %[[LHS_REAL_ABS]], +inf
! IMPRVD: %[[LHS_IMAG_ABS:.*]] = call contract float @llvm.fabs.f32(float %[[LHS_IMAG]])
-! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq float %[[LHS_IMAG_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq float %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_INFINITE:.*]] = or i1 %[[LHS_REAL_INFINITE]], %[[LHS_IMAG_INFINITE]]
! IMPRVD: %[[INF_NUM_FINITE_DENOM:.*]] = and i1 %[[LHS_IS_INFINITE]], %[[RHS_IS_FINITE]]
! IMPRVD: %[[LHS_REAL_IS_INF:.*]] = select i1 %[[LHS_REAL_INFINITE]], float 1.000000e+00, float 0.000000e+00
@@ -315,18 +315,18 @@ end subroutine div_test_bfloat
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract float %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract float %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[INF_MULTIPLICATOR_1:.*]] = fadd contract float %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract float %[[INF_MULTIPLICATOR_1]], 0x7FF0000000000000
+! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract float %[[INF_MULTIPLICATOR_1]], +inf
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract float %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract float %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[INF_MULTIPLICATOR_2:.*]] = fsub contract float %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract float %[[INF_MULTIPLICATOR_2]], 0x7FF0000000000000
+! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract float %[[INF_MULTIPLICATOR_2]], +inf
! Case 3. Finite numerator, infinite denominator.
-! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one float %[[LHS_REAL_ABS]], 0x7FF0000000000000
-! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one float %[[LHS_IMAG_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one float %[[LHS_REAL_ABS]], +inf
+! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one float %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_FINITE:.*]] = and i1 %[[LHS_REAL_FINITE]], %[[LHS_IMAG_FINITE]]
-! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq float %[[RHS_REAL_ABS]], 0x7FF0000000000000
-! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq float %[[RHS_IMAG_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq float %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq float %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_INFINITE:.*]] = or i1 %[[RHS_REAL_INFINITE]], %[[RHS_IMAG_INFINITE]]
! IMPRVD: %[[FINITE_NUM_INFINITE_DENOM:.*]] = and i1 %[[LHS_IS_FINITE]], %[[RHS_IS_INFINITE]]
! IMPRVD: %[[RHS_REAL_IS_INF:.*]] = select i1 %[[RHS_REAL_INFINITE]], float 1.000000e+00, float 0.000000e+00
@@ -420,18 +420,18 @@ end subroutine div_test_single
! IMPRVD: %[[LHS_CONTAINS_NOT_NAN_VALUE:.*]] = or i1 %[[LHS_REAL_IS_NOT_NAN]], %[[LHS_IMAG_IS_NOT_NAN]]
! IMPRVD: %[[RHS_IS_ZERO:.*]] = and i1 %[[RHS_REAL_ABS_IS_ZERO]], %[[RHS_IMAG_ABS_IS_ZERO]]
! IMPRVD: %[[RESULT_IS_INFINITY:.*]] = and i1 %[[LHS_CONTAINS_NOT_NAN_VALUE]], %[[RHS_IS_ZERO]]
-! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call double @llvm.copysign.f64(double 0x7FF0000000000000, double %[[RHS_REAL]])
+! IMPRVD: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = call double @llvm.copysign.f64(double +inf, double %[[RHS_REAL]])
! IMPRVD: %[[INFINITY_RESULT_REAL:.*]] = fmul contract double %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_REAL]]
! IMPRVD: %[[INFINITY_RESULT_IMAG:.*]] = fmul contract double %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_IMAG]]
! Case 2. Infinite numerator, finite denominator.
-! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one double %[[RHS_REAL_ABS]], 0x7FF0000000000000
-! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one double %[[RHS_IMAG_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[RHS_REAL_FINITE:.*]] = fcmp one double %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_FINITE:.*]] = fcmp one double %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_FINITE:.*]] = and i1 %[[RHS_REAL_FINITE]], %[[RHS_IMAG_FINITE]]
! IMPRVD: %[[LHS_REAL_ABS:.*]] = call contract double @llvm.fabs.f64(double %[[LHS_REAL]])
-! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq double %[[LHS_REAL_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[LHS_REAL_INFINITE:.*]] = fcmp oeq double %[[LHS_REAL_ABS]], +inf
! IMPRVD: %[[LHS_IMAG_ABS:.*]] = call contract double @llvm.fabs.f64(double %[[LHS_IMAG]])
-! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq double %[[LHS_IMAG_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[LHS_IMAG_INFINITE:.*]] = fcmp oeq double %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_INFINITE:.*]] = or i1 %[[LHS_REAL_INFINITE]], %[[LHS_IMAG_INFINITE]]
! IMPRVD: %[[INF_NUM_FINITE_DENOM:.*]] = and i1 %[[LHS_IS_INFINITE]], %[[RHS_IS_FINITE]]
! IMPRVD: %[[LHS_REAL_IS_INF:.*]] = select i1 %[[LHS_REAL_INFINITE]], double 1.000000e+00, double 0.000000e+00
@@ -441,18 +441,18 @@ end subroutine div_test_single
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract double %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract double %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[INF_MULTIPLICATOR_1:.*]] = fadd contract double %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract double %[[INF_MULTIPLICATOR_1]], 0x7FF0000000000000
+! IMPRVD: %[[RESULT_REAL_3:.*]] = fmul contract double %[[INF_MULTIPLICATOR_1]], +inf
! IMPRVD: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = fmul contract double %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_IMAG]]
! IMPRVD: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = fmul contract double %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_REAL]]
! IMPRVD: %[[INF_MULTIPLICATOR_2:.*]] = fsub contract double %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]]
-! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract double %[[INF_MULTIPLICATOR_2]], 0x7FF0000000000000
+! IMPRVD: %[[RESULT_IMAG_3:.*]] = fmul contract double %[[INF_MULTIPLICATOR_2]], +inf
! Case 3. Finite numerator, infinite denominator.
-! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one double %[[LHS_REAL_ABS]], 0x7FF0000000000000
-! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one double %[[LHS_IMAG_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[LHS_REAL_FINITE:.*]] = fcmp one double %[[LHS_REAL_ABS]], +inf
+! IMPRVD: %[[LHS_IMAG_FINITE:.*]] = fcmp one double %[[LHS_IMAG_ABS]], +inf
! IMPRVD: %[[LHS_IS_FINITE:.*]] = and i1 %[[LHS_REAL_FINITE]], %[[LHS_IMAG_FINITE]]
-! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq double %[[RHS_REAL_ABS]], 0x7FF0000000000000
-! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq double %[[RHS_IMAG_ABS]], 0x7FF0000000000000
+! IMPRVD: %[[RHS_REAL_INFINITE:.*]] = fcmp oeq double %[[RHS_REAL_ABS]], +inf
+! IMPRVD: %[[RHS_IMAG_INFINITE:.*]] = fcmp oeq double %[[RHS_IMAG_ABS]], +inf
! IMPRVD: %[[RHS_IS_INFINITE:.*]] = or i1 %[[RHS_REAL_INFINITE]], %[[RHS_IMAG_INFINITE]]
! IMPRVD: %[[FINITE_NUM_INFINITE_DENOM:.*]] = and i1 %[[LHS_IS_FINITE]], %[[RHS_IS_INFINITE]]
! IMPRVD: %[[RHS_REAL_IS_INF:.*]] = select i1 %[[RHS_REAL_INFINITE]], double 1.000000e+00, double 0.000000e+00
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 5f9d6b93bf7d4..00032b2fa3c20 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -78,6 +78,9 @@ Changes to the LLVM IR
* Special values for infinities and NaNs, including NaN payloads, are added.
+* The standard textual output for floating-point literals is changed to take
+ advantage of the new floating-point literals formats.
+
Changes to LLVM infrastructure
------------------------------
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index 5a557ab5d4e5d..4e5a40d241d36 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -677,6 +677,8 @@ class IEEEFloat final {
LLVM_ABI cmpResult compareAbsoluteValue(const IEEEFloat &) const;
+ APInt getNaNPayload() const;
+
private:
/// \name Simple Queries
/// @{
@@ -923,6 +925,8 @@ class DoubleAPFloat final {
LLVM_ABI bool isLargest() const;
LLVM_ABI bool isInteger() const;
+ APInt getNaNPayload() const;
+
LLVM_ABI void toString(SmallVectorImpl<char> &Str, unsigned FormatPrecision,
unsigned FormatMaxPadding,
bool TruncateZero = true) const;
@@ -1554,6 +1558,14 @@ class APFloat : public APFloatBase {
APFLOAT_DISPATCH_ON_SEMANTICS(isSmallestNormalized());
}
+ /// If the value is a NaN value, return an integer containing the payload of
+ /// this value. This payload will include the quiet bit as part of the
+ /// returned integer.
+ APInt getNaNPayload() const {
+ assert(isNaN() && "Can only call this on a NaN value");
+ APFLOAT_DISPATCH_ON_SEMANTICS(getNaNPayload());
+ }
+
/// Return the FPClassTest which will return true for the value.
LLVM_ABI FPClassTest classify() const;
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index 7bff1e307237c..93324e5e55f9f 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -1536,97 +1536,68 @@ static void writeOptimizationInfo(raw_ostream &Out, const User *U) {
}
}
+static void WriteFullHexAPInt(raw_ostream &Out, const APInt &Val) {
+ SmallVector<char, 32> Bits;
+ Val.toStringUnsigned(Bits, 16);
+ unsigned NumDigits = std::max((Val.getBitWidth() + 3) / 4, 1U);
+ Out << "0x";
+ for (unsigned i = 0; i < NumDigits - Bits.size(); i++)
+ Out << '0';
+ Out << Bits;
+}
+
static void writeAPFloatInternal(raw_ostream &Out, const APFloat &APF) {
- if (&APF.getSemantics() == &APFloat::IEEEsingle() ||
- &APF.getSemantics() == &APFloat::IEEEdouble()) {
- // We would like to output the FP constant value in exponential notation,
- // but we cannot do this if doing so will lose precision. Check here to
- // make sure that we only output it in exponential format if we can parse
- // the value back and get the same value.
- //
- bool ignored;
- bool isDouble = &APF.getSemantics() == &APFloat::IEEEdouble();
- bool isInf = APF.isInfinity();
- bool isNaN = APF.isNaN();
-
- if (!isInf && !isNaN) {
- double Val = APF.convertToDouble();
- SmallString<128> StrVal;
- APF.toString(StrVal, 6, 0, false);
- // Check to make sure that the stringized number is not some string like
- // "Inf" or NaN, that atof will accept, but the lexer will not. Check
- // that the string matches the "[-+]?[0-9]" regex.
- //
- assert((isDigit(StrVal[0]) ||
- ((StrVal[0] == '-' || StrVal[0] == '+') && isDigit(StrVal[1]))) &&
- "[-+]?[0-9] regex does not match!");
- // Reparse stringized version!
- if (APFloat(APFloat::IEEEdouble(), StrVal).convertToDouble() == Val) {
- Out << StrVal;
- return;
- }
+ bool ForceBitwiseOutput = false;
+ if (&APF.getSemantics() == &APFloat::PPCDoubleDouble()) {
+ // ppc_fp128 types are double-double. The special cases set the second
+ // (high) double to +0.0, so if the high word is nonzero, force the use of
+ // bitwise output.
+ APInt HiWord = APF.bitcastToAPInt().lshr(64);
+ ForceBitwiseOutput = !HiWord.isZero();
+ }
+
+ if (!ForceBitwiseOutput) {
+ // Check for special values in APFloat.
+ if (APF.isInfinity()) {
+ Out << (APF.isNegative() ? '-' : '+') << "inf";
+ return;
}
- // Otherwise we could not reparse it to exactly the same value, so we must
- // output the string in hexadecimal format! Note that loading and storing
- // floating point types changes the bits of NaNs on some hosts, notably
- // x86, so we must not use these types.
- static_assert(sizeof(double) == sizeof(uint64_t),
- "assuming that double is 64 bits!");
- APFloat apf = APF;
-
- // Floats are represented in ASCII IR as double, convert.
- // FIXME: We should allow 32-bit hex float and remove this.
- if (!isDouble) {
- // A signaling NaN is quieted on conversion, so we need to recreate the
- // expected value after convert (quiet bit of the payload is clear).
- bool IsSNAN = apf.isSignaling();
- apf.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
- &ignored);
- if (IsSNAN) {
- APInt Payload = apf.bitcastToAPInt();
- apf =
- APFloat::getSNaN(APFloat::IEEEdouble(), apf.isNegative(), &Payload);
+ if (APF.isNaN()) {
+ Out << (APF.isNegative() ? '-' : '+');
+ APInt Payload = APF.getNaNPayload();
+ // The quiet bit of a NaN is the highest bit of the payload, so the
+ // preferred QNaN value happens to be the sign mask value.
+ if (Payload.isSignMask()) {
+ Out << "qnan";
+ } else {
+ if (APF.isSignaling())
+ Out << 's';
+ Out << "nan(";
+ // Clear out the signaling/quiet bit of the payload for output.
+ Payload.clearBit(Payload.getBitWidth() - 1);
+ // Trim the string to exclude leading 0's.
+ WriteFullHexAPInt(Out, Payload.trunc(Payload.getActiveBits()));
+ Out << ')';
}
+ return;
}
+ }
- Out << format_hex(apf.bitcastToAPInt().getZExtValue(), 0, /*Upper=*/true);
+ // Try for a decimal string output. If the value is convertible back to the
+ // same APFloat value, then we know that it is safe to use it. Otherwise, fall
+ // back onto the hexadecimal format.
+ SmallString<128> StrVal;
+ APF.toString(StrVal, 6, 0, false);
+ if (APFloat(APF.getSemantics(), StrVal) == APF) {
+ Out << StrVal;
return;
}
- // Either half, bfloat or some form of long double.
- // These appear as a magic letter identifying the type, then a
- // fixed number of hex digits.
- Out << "0x";
+ // Fallback to the hexadecimal format representing the bit string exactly.
+ Out << 'f';
APInt API = APF.bitcastToAPInt();
- if (&APF.getSemantics() == &APFloat::x87DoubleExtended()) {
- Out << 'K';
- Out << format_hex_no_prefix(API.getHiBits(16).getZExtValue(), 4,
- /*Upper=*/true);
- Out << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
- /*Upper=*/true);
- } else if (&APF.getSemantics() == &APFloat::IEEEquad()) {
- Out << 'L';
- Out << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
- /*Upper=*/true);
- Out << format_hex_no_prefix(API.getHiBits(64).getZExtValue(), 16,
- /*Upper=*/true);
- } else if (&APF.getSemantics() == &APFloat::PPCDoubleDouble()) {
- Out << 'M';
- Out << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
- /*Upper=*/true);
- Out << format_hex_no_prefix(API.getHiBits(64).getZExtValue(), 16,
- /*Upper=*/true);
- } else if (&APF.getSemantics() == &APFloat::IEEEhalf()) {
- Out << 'H';
- Out << format_hex_no_prefix(API.getZExtValue(), 4,
- /*Upper=*/true);
- } else if (&APF.getSemantics() == &APFloat::BFloat()) {
- Out << 'R';
- Out << format_hex_no_prefix(API.getZExtValue(), 4,
- /*Upper=*/true);
- } else
- llvm_unreachable("Unsupported floating point type");
+ WriteFullHexAPInt(Out, API);
}
static void writeConstantInternal(raw_ostream &Out, const Constant *CV,
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 9abb202f15e9e..8bb0069f77528 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -3703,7 +3703,8 @@ void IEEEFloat::initFromPPCDoubleDoubleLegacyAPInt(const APInt &api) {
initFromDoubleAPInt(APInt(64, i1));
[[maybe_unused]] opStatus fs = convert(APFloatBase::semPPCDoubleDoubleLegacy,
rmNearestTiesToEven, &losesInfo);
- assert(fs == opOK && !losesInfo);
+ // (convert may return opInvalidOp if i1 is an sNaN).
+ assert((fs == opOK || fs == opInvalidOp) && !losesInfo);
// Unless we have a special case, add in second double.
if (isFiniteNonZero()) {
@@ -4516,6 +4517,13 @@ APFloat::opStatus IEEEFloat::next(bool nextDown) {
return result;
}
+APInt IEEEFloat::getNaNPayload() const {
+ assert(isNaN() && "Can only be called on NaN values");
+ // Number of bits in the payload, excluding the (maybe implied) integer bit.
+ unsigned Bits = semantics->precision - 1;
+ return APInt(Bits, ArrayRef(significandParts(), partCountForBits(Bits)));
+}
+
APFloatBase::ExponentType IEEEFloat::exponentNaN() const {
return ::exponentNaN(*semantics);
}
@@ -5780,6 +5788,7 @@ DoubleAPFloat frexp(const DoubleAPFloat &Arg, int &Exp,
std::move(Second));
}
+APInt DoubleAPFloat::getNaNPayload() const { return Floats[0].getNaNPayload(); }
} // namespace detail
APFloat::Storage::Storage(IEEEFloat F, const fltSemantics &Semantics) {
diff --git a/llvm/test/Assembler/bfloat.ll b/llvm/test/Assembler/bfloat.ll
index 3a3b4c2b277db..c972c560c7b70 100644
--- a/llvm/test/Assembler/bfloat.ll
+++ b/llvm/test/Assembler/bfloat.ll
@@ -9,7 +9,7 @@ define bfloat @check_bfloat(bfloat %A) {
}
define bfloat @check_bfloat_literal() {
-; ASSEM-DISASS: ret bfloat 0xR3149
+; ASSEM-DISASS: ret bfloat 2.924930e-09
ret bfloat 0xR3149
}
@@ -27,36 +27,36 @@ define <vscale x 4 x bfloat> @check_vector() {
define bfloat @check_bfloat_constprop() {
%tmp = fadd bfloat 0xR40C0, 0xR40C0
-; OPT: 0xR4140
+; OPT: 1.200000e+01
ret bfloat %tmp
}
define float @check_bfloat_convert() {
%tmp = fpext bfloat 0xR4C8D to float
-; OPT: 0x4191A00000000000
+; OPT: f0x4C8D0000
ret float %tmp
}
; ASSEM-DISASS-LABEL @snan_bfloat
define bfloat @snan_bfloat() {
-; ASSEM-DISASS: ret bfloat 0xR7F81
+; ASSEM-DISASS: ret bfloat +snan(0x1)
ret bfloat 0xR7F81
}
; ASSEM-DISASS-LABEL @qnan_bfloat
define bfloat @qnan_bfloat() {
-; ASSEM-DISASS: ret bfloat 0xR7FC0
+; ASSEM-DISASS: ret bfloat +qnan
ret bfloat 0xR7FC0
}
; ASSEM-DISASS-LABEL @pos_inf_bfloat
define bfloat @pos_inf_bfloat() {
-; ASSEM-DISASS: ret bfloat 0xR7F80
+; ASSEM-DISASS: ret bfloat +inf
ret bfloat 0xR7F80
}
; ASSEM-DISASS-LABEL @neg_inf_bfloat
define bfloat @neg_inf_bfloat() {
-; ASSEM-DISASS: ret bfloat 0xRFF80
+; ASSEM-DISASS: ret bfloat -inf
ret bfloat 0xRFF80
}
diff --git a/llvm/test/Assembler/float-literals.ll b/llvm/test/Assembler/float-literals.ll
index 0ccaf7505c8ab..2a3e0ad8de515 100644
--- a/llvm/test/Assembler/float-literals.ll
+++ b/llvm/test/Assembler/float-literals.ll
@@ -12,32 +12,32 @@
@e = global float 0.e-1
; CHECK: @f = global float 0.000000e+00
@f = global float 0.e+1
-; CHECK: @g = global float 0x3DF0000000000000
+; CHECK: @g = global float f0x2F800000
@g = global float 0x1.0p-32
-; CHECK: @h = global float 0x41F0000000000000
+; CHECK: @h = global float f0x4F800000
@h = global float 0x1.0p+32
-; CHECK: @i = global float 0x41FC300000000000
+; CHECK: @i = global float f0x4FE18000
@i = global float 0x1.c3p32
-; CHECK: @j = global float 0x3FFFF00000000000
+; CHECK: @j = global float f0x3FFF8000
@j = global float 0x1.ffp0
-; CHECK: @k = global float 0xC0FFFFFFE0000000
+; CHECK: @k = global float f0xC7FFFFFF
@k = global float -0xfff.fffp5
-; CHECK: @l = global float 0x4080FDE000000000
+; CHECK: @l = global float f0x4407EF00
@l = global float +0x10.fdep5
-; CHECK: @0 = global double 0x7FF0000000000000
+; CHECK: @0 = global double +inf
@0 = global double +inf
-; CHECK: @1 = global ppc_fp128 0xMFFF00000000000000000000000000000
+; CHECK: @1 = global ppc_fp128 -inf
@1 = global ppc_fp128 -inf
-; CHECK: @2 = global half 0xHFE00
+; CHECK: @2 = global half -qnan
@2 = global half -qnan
-; CHECK: @3 = global bfloat 0xR7FC0
+; CHECK: @3 = global bfloat +qnan
@3 = global bfloat +qnan
-; CHECK: @4 = global fp128 0xL00000000DEADBEEF7FFF800000000000
+; CHECK: @4 = global fp128 +nan(0xDEADBEEF)
@4 = global fp128 +nan(0xdeadbeef)
-; CHECK: @5 = global float 0x7FF000002000000
+; CHECK: @5 = global float +snan(0x1)
@5 = global float +snan(0x1)
-; CHECK: @6 = global x86_fp80 0xK0001FFFF000000000000
+; CHECK: @6 = global x86_fp80 f0x0001FFFF000000000000
@6 = global x86_fp80 f0x0000ffff000000000000
; CHECK: @7 = global float 0xB810000000000000
@7 = global float -0x1.0p-126
@@ -49,5 +49,19 @@
@denormal.dec = global half 2.878904342651367875e-5
@denormal.bits = global half f0x01e3
-; CHECK: @legacy = global float 0x3FB99999A0000000
+; CHECK: @legacy = global float 1.000000e-01
@legacy = global float 0x3FB99999A0000000
+
+; PPC special cases
+; CHECK: @ppc.1 = global ppc_fp128 +inf
+ at ppc.1 = global ppc_fp128 f0x00000000000000007ff0000000000000
+; CHECK: @ppc.2 = global ppc_fp128 f0x80000000000000017FF0000000000000
+ at ppc.2 = global ppc_fp128 f0x80000000000000017ff0000000000000
+; CHECK: @ppc.3 = global ppc_fp128 +snan(0x1)
+ at ppc.3 = global ppc_fp128 f0x00000000000000007ff0000000000001
+; CHECK: @ppc.4 = global ppc_fp128 f0x00000000000000017FF0000000000001
+ at ppc.4 = global ppc_fp128 f0x00000000000000017ff0000000000001
+; CHECK: @ppc.5 = global ppc_fp128 +nan(0x1)
+ at ppc.5 = global ppc_fp128 f0x00000000000000007ff8000000000001
+; CHECK: @ppc.6 = global ppc_fp128 f0x0FFFF000010000007FF8000000000001
+ at ppc.6 = global ppc_fp128 f0x0ffff000010000007ff8000000000001
diff --git a/llvm/test/Assembler/half-constprop.ll b/llvm/test/Assembler/half-constprop.ll
index d26545d5584e0..220481dba6f56 100644
--- a/llvm/test/Assembler/half-constprop.ll
+++ b/llvm/test/Assembler/half-constprop.ll
@@ -12,7 +12,7 @@ entry:
%tmp = load half, ptr %a, align 2
%tmp1 = load half, ptr %b, align 2
%add = fadd half %tmp, %tmp1
-; CHECK: 0xH4C8D
+; CHECK: 1.820310e+01
ret half %add
}
diff --git a/llvm/test/Assembler/half-conv.ll b/llvm/test/Assembler/half-conv.ll
index 219c5b065611a..ae5246b47ec50 100644
--- a/llvm/test/Assembler/half-conv.ll
+++ b/llvm/test/Assembler/half-conv.ll
@@ -9,6 +9,6 @@ entry:
store half 0xH4C8D, ptr %a, align 2
%tmp = load half, ptr %a, align 2
%conv = fpext half %tmp to float
-; CHECK: 0x4032340000000000
+; CHECK: f0x4191A000
ret float %conv
}
diff --git a/llvm/test/Transforms/EarlyCSE/math-1.ll b/llvm/test/Transforms/EarlyCSE/math-1.ll
index d97207843435b..8e52975099fe6 100644
--- a/llvm/test/Transforms/EarlyCSE/math-1.ll
+++ b/llvm/test/Transforms/EarlyCSE/math-1.ll
@@ -13,7 +13,7 @@ define double @f_acos() {
declare float @asinf(float) #0
define float @f_asinf() {
; CHECK-LABEL: @f_asinf(
-; CHECK-NEXT: ret float 0x3FF921FB{{.+}}
+; CHECK-NEXT: ret float f0x3FC90FD{{.+}}
;
%res = tail call fast float @asinf(float 1.0)
ret float %res
@@ -22,7 +22,7 @@ define float @f_asinf() {
declare double @atan(double) #0
define double @f_atan() {
; CHECK-LABEL: @f_atan(
-; CHECK-NEXT: ret double 0x3FE921FB
+; CHECK-NEXT: ret double f0x3FE921FB{{.+}}
;
%res = tail call fast double @atan(double 1.0)
ret double %res
@@ -31,7 +31,7 @@ define double @f_atan() {
declare float @cosf(float) #0
define float @f_cosf() {
; CHECK-LABEL: @f_cosf(
-; CHECK-NEXT: ret float 0x3FE14A2{{.+}}
+; CHECK-NEXT: ret float f0x3F0A514{{.+}}
;
%res = tail call fast float @cosf(float 1.0)
ret float %res
@@ -40,7 +40,7 @@ define float @f_cosf() {
declare float @llvm.cos.f32(float)
define float @i_cosf() {
; CHECK-LABEL: @i_cosf(
-; CHECK-NEXT: ret float 0x3FE14A2
+; CHECK-NEXT: ret float f0x3F0A514{{.+}}
;
%res = tail call fast float @llvm.cos.f32(float 1.0)
ret float %res
@@ -49,7 +49,7 @@ define float @i_cosf() {
declare double @cosh(double) #0
define double @f_cosh() {
; CHECK-LABEL: @f_cosh(
-; CHECK-NEXT: ret double 0x3FF8B075{{.+}}
+; CHECK-NEXT: ret double f0x3FF8B075{{.+}}
;
%res = tail call fast double @cosh(double 1.0)
ret double %res
@@ -58,7 +58,7 @@ define double @f_cosh() {
declare float @expf(float) #0
define float @f_expf() {
; CHECK-LABEL: @f_expf(
-; CHECK-NEXT: ret float 0x4005BF0A{{.+}}
+; CHECK-NEXT: ret float f0x402DF85{{.+}}
;
%res = tail call fast float @expf(float 1.0)
ret float %res
@@ -67,7 +67,7 @@ define float @f_expf() {
declare float @llvm.exp.f32(float)
define float @i_expf() {
; CHECK-LABEL: @i_expf(
-; CHECK-NEXT: ret float 0x4005BF0A{{.+}}
+; CHECK-NEXT: ret float f0x402DF85{{.+}}
;
%res = tail call fast float @llvm.exp.f32(float 1.0)
ret float %res
@@ -150,7 +150,7 @@ define double @f_log10() {
declare float @sinf(float) #0
define float @f_sinf() {
; CHECK-LABEL: @f_sinf(
-; CHECK-NEXT: ret float 0x3FEAED54{{.+}}
+; CHECK-NEXT: ret float f0x3F576AA{{.+}}
;
%res = tail call fast float @sinf(float 1.0)
ret float %res
@@ -159,7 +159,7 @@ define float @f_sinf() {
declare double @sinh(double) #0
define double @f_sinh() {
; CHECK-LABEL: @f_sinh(
-; CHECK-NEXT: ret double 0x3FF2CD9F{{.+}}
+; CHECK-NEXT: ret double f0x3FF2CD9F{{.+}}
;
%res = tail call fast double @sinh(double 1.0)
ret double %res
@@ -177,7 +177,7 @@ define float @f_sqrtf() {
declare double @tan(double) #0
define double @f_tan() {
; CHECK-LABEL: @f_tan(
-; CHECK-NEXT: ret double 0x3FF8EB24{{.+}}
+; CHECK-NEXT: ret double f0x3FF8EB24{{.+}}
;
%res = tail call fast double @tan(double 1.0)
ret double %res
@@ -187,7 +187,7 @@ declare float @tanhf(float) #0
define float @f_tanhf() {
; CHECK-LABEL: @f_tanhf(
; CHECK-NEXT: [[RES:%.*]] = tail call fast float @tanhf(float 1.000000e+00)
-; CHECK-NEXT: ret float 0x3FE85EFA{{.+}}
+; CHECK-NEXT: ret float f0x3F42F7D{{.+}}
;
%res = tail call fast float @tanhf(float 1.0)
ret float %res
diff --git a/llvm/test/Transforms/EarlyCSE/math-2.ll b/llvm/test/Transforms/EarlyCSE/math-2.ll
index 0d55165e3662f..4a98a116abbb8 100644
--- a/llvm/test/Transforms/EarlyCSE/math-2.ll
+++ b/llvm/test/Transforms/EarlyCSE/math-2.ll
@@ -4,7 +4,7 @@
declare double @atan2(double, double) #0
define double @f_atan2() {
; CHECK-LABEL: @f_atan2(
-; CHECK-NEXT: ret double 0x3FDDAC6{{.+}}
+; CHECK-NEXT: ret double f0x3FDDAC6{{.+}}
;
%res = tail call fast double @atan2(double 1.0, double 2.0)
ret double %res
@@ -102,7 +102,7 @@ define double @i_powi() {
define half @pr98665() {
; CHECK-LABEL: @pr98665(
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
%x = call half @llvm.powi.f16.i32(half 0xH3C00, i32 1)
ret half %x
diff --git a/llvm/test/Transforms/InstCombine/2009-01-19-fmod-constant-float-specials.ll b/llvm/test/Transforms/InstCombine/2009-01-19-fmod-constant-float-specials.ll
index 373b431cc3f0d..b1d0fc8e35a28 100644
--- a/llvm/test/Transforms/InstCombine/2009-01-19-fmod-constant-float-specials.ll
+++ b/llvm/test/Transforms/InstCombine/2009-01-19-fmod-constant-float-specials.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -passes=simplifycfg,instcombine -simplifycfg-require-and-preserve-domtree=1 -S | grep 0x7FF8000000000000 | count 12
+; RUN: opt < %s -passes=simplifycfg,instcombine -simplifycfg-require-and-preserve-domtree=1 -S | grep "+qnan" | count 12
; RUN: opt < %s -passes=simplifycfg,instcombine -simplifycfg-require-and-preserve-domtree=1 -S | grep "0\.0" | count 3
; RUN: opt < %s -passes=simplifycfg,instcombine -simplifycfg-require-and-preserve-domtree=1 -S | grep "3\.5" | count 1
;
diff --git a/llvm/test/Transforms/InstCombine/2009-01-19-fmod-constant-float.ll b/llvm/test/Transforms/InstCombine/2009-01-19-fmod-constant-float.ll
index 1bce652ae5817..21901431e78ad 100644
--- a/llvm/test/Transforms/InstCombine/2009-01-19-fmod-constant-float.ll
+++ b/llvm/test/Transforms/InstCombine/2009-01-19-fmod-constant-float.ll
@@ -1,5 +1,5 @@
-; RUN: opt < %s -passes=simplifycfg,instcombine -simplifycfg-require-and-preserve-domtree=1 -S | grep 0x3FB99999A0000000 | count 2
-; RUN: opt < %s -passes=simplifycfg,instcombine -simplifycfg-require-and-preserve-domtree=1 -S | grep 0xBFB99999A0000000 | count 2
+; RUN: opt < %s -passes=simplifycfg,instcombine -simplifycfg-require-and-preserve-domtree=1 -S | grep '[^-]1.000000e-01' | count 2
+; RUN: opt < %s -passes=simplifycfg,instcombine -simplifycfg-require-and-preserve-domtree=1 -S | grep -- '-1.000000e-01' | count 2
; check constant folding for 'frem'. PR 3316.
; ModuleID = 'tt.c'
diff --git a/llvm/test/Transforms/InstCombine/bitcast-store.ll b/llvm/test/Transforms/InstCombine/bitcast-store.ll
index 3d4bd251e98a5..a387a60407d0b 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-store.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-store.ll
@@ -59,7 +59,7 @@ define void @ppcf128_ones_store(ptr %dest) {
; CHECK-LABEL: define void @ppcf128_ones_store
; CHECK-SAME: (ptr [[DEST:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: store ppc_fp128 0xMFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, ptr [[DEST]], align 16
+; CHECK-NEXT: store ppc_fp128 f0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, ptr [[DEST]], align 16
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/pow-exp.ll b/llvm/test/Transforms/InstCombine/pow-exp.ll
index 9d91ad2402eb1..ae6d25b4a1de1 100644
--- a/llvm/test/Transforms/InstCombine/pow-exp.ll
+++ b/llvm/test/Transforms/InstCombine/pow-exp.ll
@@ -216,7 +216,7 @@ declare void @use_f(float)
define double @pow_ok_base(double %e) {
; CHECK-LABEL: @pow_ok_base(
; Do not change 0xBFE0776{{.*}} to the exact constant, see PR42740
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0xBFE0776{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], f0xBFE0776{{.*}}
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -226,7 +226,7 @@ define double @pow_ok_base(double %e) {
define double @pow_ok_base_fast(double %e) {
; CHECK-LABEL: @pow_ok_base_fast(
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[E:%.*]], 0xBFE0776{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[E:%.*]], f0xBFE0776{{.*}}
; CHECK-NEXT: [[EXP2:%.*]] = tail call fast double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -236,7 +236,7 @@ define double @pow_ok_base_fast(double %e) {
define double @pow_ok_base2(double %e) {
; CHECK-LABEL: @pow_ok_base2(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x4010952{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], f0x4010952{{.*}}
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -246,7 +246,7 @@ define double @pow_ok_base2(double %e) {
define double @pow_ok_base3(double %e) {
; CHECK-LABEL: @pow_ok_base3(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x400AB0B5{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], f0x400AB0B5{{.*}}
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -256,7 +256,7 @@ define double @pow_ok_base3(double %e) {
define double @pow_ok_ten_base(double %e) {
; CHECK-LABEL: @pow_ok_ten_base(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x400A934F{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], f0x400A934F{{.*}}
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -266,7 +266,7 @@ define double @pow_ok_ten_base(double %e) {
define double @pow_ok_denorm_base(double %e) {
; CHECK-LABEL: @pow_ok_denorm_base(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0xC0904800000005C5
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], f0xC0904800000005C5
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -276,7 +276,7 @@ define double @pow_ok_denorm_base(double %e) {
define float @powf_ok_base(float %e) {
; CHECK-LABEL: @powf_ok_base(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0xBFE07762{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], f0xBF03BB1{{.*}}
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: ret float [[EXP2F]]
;
@@ -286,7 +286,7 @@ define float @powf_ok_base(float %e) {
define float @powf_ok_base2(float %e) {
; CHECK-LABEL: @powf_ok_base2(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x4010952{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], f0x4084A96{{.*}}
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: ret float [[EXP2F]]
;
@@ -296,7 +296,7 @@ define float @powf_ok_base2(float %e) {
define float @powf_ok_base3(float %e) {
; CHECK-LABEL: @powf_ok_base3(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x400AB0B5{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], f0x405585A{{.*}}
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: ret float [[EXP2F]]
;
@@ -306,7 +306,7 @@ define float @powf_ok_base3(float %e) {
define float @powf_ok_ten_base(float %e) {
; CHECK-LABEL: @powf_ok_ten_base(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x400A934{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], f0x40549A7{{.*}}
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: ret float [[EXP2F]]
;
@@ -346,7 +346,7 @@ define double @pow_zero_base2(double %e) {
define double @pow_inf_base(double %e) {
; CHECK-LABEL: @pow_inf_base(
-; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn double @pow(double 0x7FF0000000000000, double [[E:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn double @pow(double +inf, double [[E:%.*]])
; CHECK-NEXT: ret double [[CALL]]
;
%call = tail call afn nnan ninf double @pow(double 0x7FF0000000000000, double %e)
@@ -355,7 +355,7 @@ define double @pow_inf_base(double %e) {
define double @pow_nan_base(double %e) {
; CHECK-LABEL: @pow_nan_base(
-; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn double @pow(double 0x7FF8000000000000, double [[E:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn double @pow(double +qnan, double [[E:%.*]])
; CHECK-NEXT: ret double [[CALL]]
;
%call = tail call afn nnan ninf double @pow(double 0x7FF8000000000000, double %e)
@@ -373,7 +373,7 @@ define double @pow_negative_base(double %e) {
define double @pow_multiuse(double %e) {
; CHECK-LABEL: @pow_multiuse(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x4002934{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], f0x4002934{{.*}}
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: tail call void @use_d(double [[EXP2]])
; CHECK-NEXT: ret double [[EXP2]]
@@ -385,7 +385,7 @@ define double @pow_multiuse(double %e) {
define double @pow_ok_base_no_afn(double %e) {
; CHECK-LABEL: @pow_ok_base_no_afn(
-; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf double @pow(double 0x3FE6666666666666, double [[E:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf double @pow(double f0x3FE6666666666666, double [[E:%.*]])
; CHECK-NEXT: ret double [[CALL]]
;
%call = tail call nnan ninf double @pow(double 0x3FE6666666666666, double %e)
@@ -394,7 +394,7 @@ define double @pow_ok_base_no_afn(double %e) {
define double @pow_ok_base_no_nnan(double %e) {
; CHECK-LABEL: @pow_ok_base_no_nnan(
-; CHECK-NEXT: [[CALL:%.*]] = tail call ninf afn double @pow(double 0x3FE6666666666666, double [[E:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call ninf afn double @pow(double f0x3FE6666666666666, double [[E:%.*]])
; CHECK-NEXT: ret double [[CALL]]
;
%call = tail call afn ninf double @pow(double 0x3FE6666666666666, double %e)
@@ -403,7 +403,7 @@ define double @pow_ok_base_no_nnan(double %e) {
define double @pow_ok_base_no_ninf(double %e) {
; CHECK-LABEL: @pow_ok_base_no_ninf(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan afn double [[E:%.*]], 0xBFE0776{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan afn double [[E:%.*]], f0xBFE0776{{.*}}
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -431,7 +431,7 @@ define float @powf_zero_base2(float %e) {
define float @powf_inf_base(float %e) {
; CHECK-LABEL: @powf_inf_base(
-; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @powf(float 0x7FF0000000000000, float [[E:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @powf(float +inf, float [[E:%.*]])
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call afn nnan ninf float @powf(float 0x7FF0000000000000, float %e)
@@ -440,7 +440,7 @@ define float @powf_inf_base(float %e) {
define float @powf_nan_base(float %e) {
; CHECK-LABEL: @powf_nan_base(
-; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @powf(float 0x7FF8000000000000, float [[E:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @powf(float +qnan, float [[E:%.*]])
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call afn nnan ninf float @powf(float 0x7FF8000000000000, float %e)
@@ -458,7 +458,7 @@ define float @powf_negative_base(float %e) {
define float @powf_multiuse(float %e) {
; CHECK-LABEL: @powf_multiuse(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x4002934{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], f0x40149A7{{.*}}
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: tail call void @use_f(float [[EXP2F]])
; CHECK-NEXT: ret float [[EXP2F]]
@@ -470,7 +470,7 @@ define float @powf_multiuse(float %e) {
define float @powf_ok_base_no_afn(float %e) {
; CHECK-LABEL: @powf_ok_base_no_afn(
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @powf(float 0x3FE6666660000000, float [[E:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @powf(float f0x3F333333, float [[E:%.*]])
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call float @powf(float 0x3FE6666660000000, float %e)
@@ -479,7 +479,7 @@ define float @powf_ok_base_no_afn(float %e) {
define fp128 @powl_long_dbl_no_fold(fp128 %e) {
; CHECK-LABEL: @powl_long_dbl_no_fold(
-; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn fp128 @powl(fp128 0xL00000000000000005001000000000000, fp128 [[E:%.*]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn fp128 @powl(fp128 f0x50010000000000000000000000000000, fp128 [[E:%.*]])
; CHECK-NEXT: ret fp128 [[CALL]]
;
%call = tail call afn nnan ninf fp128 @powl(fp128 0xL00000000000000005001000000000000, fp128 %e)
diff --git a/llvm/test/Transforms/InstCombine/pow_fp_int16.ll b/llvm/test/Transforms/InstCombine/pow_fp_int16.ll
index 0335514ce1bbe..3d5c787363ea4 100644
--- a/llvm/test/Transforms/InstCombine/pow_fp_int16.ll
+++ b/llvm/test/Transforms/InstCombine/pow_fp_int16.ll
@@ -223,7 +223,7 @@ define double @powf_exp_const2_int_fast(double %base) {
define double @pow_uitofp_const_base_fast_i16(i16 %x) {
; CHECK-LABEL: @pow_uitofp_const_base_fast_i16(
; CHECK-NEXT: [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[SUBFP]], 0x4006757{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[SUBFP]], f0x4033ABB{{.*}}
; CHECK-NEXT: [[EXP2:%.*]] = tail call fast float @llvm.exp2.f32(float [[MUL]])
; CHECK-NEXT: [[RES:%.*]] = fpext float [[EXP2]] to double
; CHECK-NEXT: ret double [[RES]]
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/cos.ll b/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/cos.ll
index 5368da112ab46..f1d5780aacfd9 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/cos.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/cos.ll
@@ -7,27 +7,27 @@ declare double @llvm.amdgcn.cos.f64(double) #0
define void @test_f16(ptr %p) {
; CHECK-LABEL: @test_f16(
-; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P:%.*]], align 2
-; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH39A8, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH39A8, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xHBC00, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xHBC00, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P]], align 2
-; CHECK-NEXT: [[P1000:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xH63D0)
+; CHECK-NEXT: store volatile half 1.000000e+00, ptr [[P:%.*]], align 2
+; CHECK-NEXT: store volatile half 1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 7.070310e-01, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 7.070310e-01, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half -1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half -1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: [[P1000:%.*]] = call half @llvm.amdgcn.cos.f16(half 1.000000e+03)
; CHECK-NEXT: store volatile half [[P1000]], ptr [[P]], align 2
-; CHECK-NEXT: [[N1000:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xHE3D0)
+; CHECK-NEXT: [[N1000:%.*]] = call half @llvm.amdgcn.cos.f16(half -1.000000e+03)
; CHECK-NEXT: store volatile half [[N1000]], ptr [[P]], align 2
-; CHECK-NEXT: [[PINF:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xH7C00)
+; CHECK-NEXT: [[PINF:%.*]] = call half @llvm.amdgcn.cos.f16(half +inf)
; CHECK-NEXT: store volatile half [[PINF]], ptr [[P]], align 2
-; CHECK-NEXT: [[NINF:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xHFC00)
+; CHECK-NEXT: [[NINF:%.*]] = call half @llvm.amdgcn.cos.f16(half -inf)
; CHECK-NEXT: store volatile half [[NINF]], ptr [[P]], align 2
-; CHECK-NEXT: [[NAN:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xH7E00)
+; CHECK-NEXT: [[NAN:%.*]] = call half @llvm.amdgcn.cos.f16(half +qnan)
; CHECK-NEXT: store volatile half [[NAN]], ptr [[P]], align 2
; CHECK-NEXT: ret void
;
@@ -72,8 +72,8 @@ define void @test_f32(ptr %p) {
; CHECK-LABEL: @test_f32(
; CHECK-NEXT: store volatile float 1.000000e+00, ptr [[P:%.*]], align 4
; CHECK-NEXT: store volatile float 1.000000e+00, ptr [[P]], align 4
-; CHECK-NEXT: store volatile float 0x3FE6A09E60000000, ptr [[P]], align 4
-; CHECK-NEXT: store volatile float 0x3FE6A09E60000000, ptr [[P]], align 4
+; CHECK-NEXT: store volatile float f0x3F3504F3, ptr [[P]], align 4
+; CHECK-NEXT: store volatile float f0x3F3504F3, ptr [[P]], align 4
; CHECK-NEXT: store volatile float 0.000000e+00, ptr [[P]], align 4
; CHECK-NEXT: store volatile float 0.000000e+00, ptr [[P]], align 4
; CHECK-NEXT: store volatile float -1.000000e+00, ptr [[P]], align 4
@@ -86,11 +86,11 @@ define void @test_f32(ptr %p) {
; CHECK-NEXT: store volatile float [[P1000]], ptr [[P]], align 4
; CHECK-NEXT: [[N1000:%.*]] = call float @llvm.amdgcn.cos.f32(float -1.000000e+03)
; CHECK-NEXT: store volatile float [[N1000]], ptr [[P]], align 4
-; CHECK-NEXT: [[PINF:%.*]] = call float @llvm.amdgcn.cos.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[PINF:%.*]] = call float @llvm.amdgcn.cos.f32(float +inf)
; CHECK-NEXT: store volatile float [[PINF]], ptr [[P]], align 4
-; CHECK-NEXT: [[NINF:%.*]] = call float @llvm.amdgcn.cos.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[NINF:%.*]] = call float @llvm.amdgcn.cos.f32(float -inf)
; CHECK-NEXT: store volatile float [[NINF]], ptr [[P]], align 4
-; CHECK-NEXT: [[NAN:%.*]] = call float @llvm.amdgcn.cos.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[NAN:%.*]] = call float @llvm.amdgcn.cos.f32(float +qnan)
; CHECK-NEXT: store volatile float [[NAN]], ptr [[P]], align 4
; CHECK-NEXT: ret void
;
@@ -135,8 +135,8 @@ define void @test_f64(ptr %p) {
; CHECK-LABEL: @test_f64(
; CHECK-NEXT: store volatile double 1.000000e+00, ptr [[P:%.*]], align 8
; CHECK-NEXT: store volatile double 1.000000e+00, ptr [[P]], align 8
-; CHECK-NEXT: store volatile double 0x3FE6A09E667F3B{{.*}}, ptr [[P]], align 8
-; CHECK-NEXT: store volatile double 0x3FE6A09E667F3B{{.*}}, ptr [[P]], align 8
+; CHECK-NEXT: store volatile double f0x3FE6A09E667F3B{{.*}}, ptr [[P]], align 8
+; CHECK-NEXT: store volatile double f0x3FE6A09E667F3B{{.*}}, ptr [[P]], align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr [[P]], align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr [[P]], align 8
; CHECK-NEXT: store volatile double -1.000000e+00, ptr [[P]], align 8
@@ -149,11 +149,11 @@ define void @test_f64(ptr %p) {
; CHECK-NEXT: store volatile double [[P1000]], ptr [[P]], align 8
; CHECK-NEXT: [[N1000:%.*]] = call double @llvm.amdgcn.cos.f64(double -1.000000e+03)
; CHECK-NEXT: store volatile double [[N1000]], ptr [[P]], align 8
-; CHECK-NEXT: [[PINF:%.*]] = call double @llvm.amdgcn.cos.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[PINF:%.*]] = call double @llvm.amdgcn.cos.f64(double +inf)
; CHECK-NEXT: store volatile double [[PINF]], ptr [[P]], align 8
-; CHECK-NEXT: [[NINF:%.*]] = call double @llvm.amdgcn.cos.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[NINF:%.*]] = call double @llvm.amdgcn.cos.f64(double -inf)
; CHECK-NEXT: store volatile double [[NINF]], ptr [[P]], align 8
-; CHECK-NEXT: [[NAN:%.*]] = call double @llvm.amdgcn.cos.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[NAN:%.*]] = call double @llvm.amdgcn.cos.f64(double +qnan)
; CHECK-NEXT: store volatile double [[NAN]], ptr [[P]], align 8
; CHECK-NEXT: ret void
;
@@ -196,9 +196,9 @@ define void @test_f64(ptr %p) {
define void @test_f16_strictfp (ptr %p) #1 {
; CHECK-LABEL: @test_f16_strictfp(
-; CHECK-NEXT: [[P0:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xH0000) #1
+; CHECK-NEXT: [[P0:%.*]] = call half @llvm.amdgcn.cos.f16(half 0.000000e+00) #1
; CHECK-NEXT: store volatile half [[P0]], ptr [[P:%.*]], align 2
-; CHECK-NEXT: [[P025:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xH3400) #1
+; CHECK-NEXT: [[P025:%.*]] = call half @llvm.amdgcn.cos.f16(half 2.500000e-01) #1
; CHECK-NEXT: store volatile half [[P025]], ptr [[P]], align 2
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/sin.ll b/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/sin.ll
index 6aeecfff7c031..91984b3c0e5d9 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/sin.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/sin.ll
@@ -7,27 +7,27 @@ declare double @llvm.amdgcn.sin.f64(double) #0
define void @test_f16(ptr %p) {
; CHECK-LABEL: @test_f16(
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P:%.*]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH39A8, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xHB9A8, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH3C00, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xHBC00, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]], align 2
-; CHECK-NEXT: [[P1000:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xH63D0)
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P:%.*]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 7.070310e-01, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half -7.070310e-01, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half -1.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]], align 2
+; CHECK-NEXT: [[P1000:%.*]] = call half @llvm.amdgcn.sin.f16(half 1.000000e+03)
; CHECK-NEXT: store volatile half [[P1000]], ptr [[P]], align 2
-; CHECK-NEXT: [[N1000:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xHE3D0)
+; CHECK-NEXT: [[N1000:%.*]] = call half @llvm.amdgcn.sin.f16(half -1.000000e+03)
; CHECK-NEXT: store volatile half [[N1000]], ptr [[P]], align 2
-; CHECK-NEXT: [[PINF:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xH7C00)
+; CHECK-NEXT: [[PINF:%.*]] = call half @llvm.amdgcn.sin.f16(half +inf)
; CHECK-NEXT: store volatile half [[PINF]], ptr [[P]], align 2
-; CHECK-NEXT: [[NINF:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xHFC00)
+; CHECK-NEXT: [[NINF:%.*]] = call half @llvm.amdgcn.sin.f16(half -inf)
; CHECK-NEXT: store volatile half [[NINF]], ptr [[P]], align 2
-; CHECK-NEXT: [[NAN:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xH7E00)
+; CHECK-NEXT: [[NAN:%.*]] = call half @llvm.amdgcn.sin.f16(half +qnan)
; CHECK-NEXT: store volatile half [[NAN]], ptr [[P]], align 2
; CHECK-NEXT: ret void
;
@@ -72,8 +72,8 @@ define void @test_f32(ptr %p) {
; CHECK-LABEL: @test_f32(
; CHECK-NEXT: store volatile float 0.000000e+00, ptr [[P:%.*]], align 4
; CHECK-NEXT: store volatile float 0.000000e+00, ptr [[P]], align 4
-; CHECK-NEXT: store volatile float 0x3FE6A09E60000000, ptr [[P]], align 4
-; CHECK-NEXT: store volatile float 0xBFE6A09E60000000, ptr [[P]], align 4
+; CHECK-NEXT: store volatile float f0x3F3504F3, ptr [[P]], align 4
+; CHECK-NEXT: store volatile float f0xBF3504F3, ptr [[P]], align 4
; CHECK-NEXT: store volatile float 1.000000e+00, ptr [[P]], align 4
; CHECK-NEXT: store volatile float -1.000000e+00, ptr [[P]], align 4
; CHECK-NEXT: store volatile float 0.000000e+00, ptr [[P]], align 4
@@ -86,11 +86,11 @@ define void @test_f32(ptr %p) {
; CHECK-NEXT: store volatile float [[P1000]], ptr [[P]], align 4
; CHECK-NEXT: [[N1000:%.*]] = call float @llvm.amdgcn.sin.f32(float -1.000000e+03)
; CHECK-NEXT: store volatile float [[N1000]], ptr [[P]], align 4
-; CHECK-NEXT: [[PINF:%.*]] = call float @llvm.amdgcn.sin.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[PINF:%.*]] = call float @llvm.amdgcn.sin.f32(float +inf)
; CHECK-NEXT: store volatile float [[PINF]], ptr [[P]], align 4
-; CHECK-NEXT: [[NINF:%.*]] = call float @llvm.amdgcn.sin.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[NINF:%.*]] = call float @llvm.amdgcn.sin.f32(float -inf)
; CHECK-NEXT: store volatile float [[NINF]], ptr [[P]], align 4
-; CHECK-NEXT: [[NAN:%.*]] = call float @llvm.amdgcn.sin.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[NAN:%.*]] = call float @llvm.amdgcn.sin.f32(float +qnan)
; CHECK-NEXT: store volatile float [[NAN]], ptr [[P]], align 4
; CHECK-NEXT: ret void
;
@@ -135,8 +135,8 @@ define void @test_f64(ptr %p) {
; CHECK-LABEL: @test_f64(
; CHECK-NEXT: store volatile double 0.000000e+00, ptr [[P:%.*]], align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr [[P]], align 8
-; CHECK-NEXT: store volatile double 0x3FE6A09E667F3B{{.*}}, ptr [[P]], align 8
-; CHECK-NEXT: store volatile double 0xBFE6A09E667F3B{{.*}}, ptr [[P]], align 8
+; CHECK-NEXT: store volatile double f0x3FE6A09E667F3B{{.*}}, ptr [[P]], align 8
+; CHECK-NEXT: store volatile double f0xBFE6A09E667F3B{{.*}}, ptr [[P]], align 8
; CHECK-NEXT: store volatile double 1.000000e+00, ptr [[P]], align 8
; CHECK-NEXT: store volatile double -1.000000e+00, ptr [[P]], align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr [[P]], align 8
@@ -149,11 +149,11 @@ define void @test_f64(ptr %p) {
; CHECK-NEXT: store volatile double [[P1000]], ptr [[P]], align 8
; CHECK-NEXT: [[N1000:%.*]] = call double @llvm.amdgcn.sin.f64(double -1.000000e+03)
; CHECK-NEXT: store volatile double [[N1000]], ptr [[P]], align 8
-; CHECK-NEXT: [[PINF:%.*]] = call double @llvm.amdgcn.sin.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[PINF:%.*]] = call double @llvm.amdgcn.sin.f64(double +inf)
; CHECK-NEXT: store volatile double [[PINF]], ptr [[P]], align 8
-; CHECK-NEXT: [[NINF:%.*]] = call double @llvm.amdgcn.sin.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[NINF:%.*]] = call double @llvm.amdgcn.sin.f64(double -inf)
; CHECK-NEXT: store volatile double [[NINF]], ptr [[P]], align 8
-; CHECK-NEXT: [[NAN:%.*]] = call double @llvm.amdgcn.sin.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[NAN:%.*]] = call double @llvm.amdgcn.sin.f64(double +qnan)
; CHECK-NEXT: store volatile double [[NAN]], ptr [[P]], align 8
; CHECK-NEXT: ret void
;
@@ -196,9 +196,9 @@ define void @test_f64(ptr %p) {
define void @test_f16_strictfp (ptr %p) #1 {
; CHECK-LABEL: @test_f16_strictfp(
-; CHECK-NEXT: [[P0:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xH0000) #1
+; CHECK-NEXT: [[P0:%.*]] = call half @llvm.amdgcn.sin.f16(half 0.000000e+00) #1
; CHECK-NEXT: store volatile half [[P0]], ptr [[P:%.*]], align 2
-; CHECK-NEXT: [[P025:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xH3400) #1
+; CHECK-NEXT: [[P025:%.*]] = call half @llvm.amdgcn.sin.f16(half 2.500000e-01) #1
; CHECK-NEXT: store volatile half [[P025]], ptr [[P]], align 2
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/calls-math-finite.ll b/llvm/test/Transforms/InstSimplify/ConstProp/calls-math-finite.ll
index 2ec147c2ad79f..6e0793fa899cb 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/calls-math-finite.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/calls-math-finite.ll
@@ -37,25 +37,25 @@ define void @T() {
; CHECK-NEXT: [[SLOT:%.*]] = alloca double, align 8
; CHECK-NEXT: [[SLOTF:%.*]] = alloca float, align 4
; CHECK-NEXT: store double 0.000000e+00, ptr [[SLOT]], align 8
-; CHECK-NEXT: store double 0x3FF921FB54442D18, ptr [[SLOT]], align 8
-; CHECK-NEXT: store double 0x3FE4978FA3269EE1, ptr [[SLOT]], align 8
-; CHECK-NEXT: store double 0x402422A497D6185E, ptr [[SLOT]], align 8
-; CHECK-NEXT: store double 0x403415E5BF6FB106, ptr [[SLOT]], align 8
+; CHECK-NEXT: store double f0x3FF921FB54442D18, ptr [[SLOT]], align 8
+; CHECK-NEXT: store double f0x3FE4978FA3269EE1, ptr [[SLOT]], align 8
+; CHECK-NEXT: store double f0x402422A497D6185E, ptr [[SLOT]], align 8
+; CHECK-NEXT: store double f0x403415E5BF6FB106, ptr [[SLOT]], align 8
; CHECK-NEXT: store double 8.000000e+00, ptr [[SLOT]], align 8
-; CHECK-NEXT: store double 0x3FF193EA7AAD030{{[AB]}}, ptr [[SLOT]], align 8
-; CHECK-NEXT: store double 0x3FDE8927964FD5FD, ptr [[SLOT]], align 8
+; CHECK-NEXT: store double f0x3FF193EA7AAD030{{[AB]}}, ptr [[SLOT]], align 8
+; CHECK-NEXT: store double f0x3FDE8927964FD5FD, ptr [[SLOT]], align 8
; CHECK-NEXT: store double 1.000000e+00, ptr [[SLOT]], align 8
-; CHECK-NEXT: store double 0x40240926E70949AE, ptr [[SLOT]], align 8
+; CHECK-NEXT: store double f0x40240926E70949AE, ptr [[SLOT]], align 8
; CHECK-NEXT: store float 0.000000e+00, ptr [[SLOTF]], align 4
-; CHECK-NEXT: store float 0x3FF921FB60000000, ptr [[SLOTF]], align 4
-; CHECK-NEXT: store float 0x3FE4978FA0000000, ptr [[SLOTF]], align 4
-; CHECK-NEXT: store float 0x402422A4A0000000, ptr [[SLOTF]], align 4
-; CHECK-NEXT: store float 0x403415E5C0000000, ptr [[SLOTF]], align 4
+; CHECK-NEXT: store float f0x3FC90FDB, ptr [[SLOTF]], align 4
+; CHECK-NEXT: store float f0x3F24BC7D, ptr [[SLOTF]], align 4
+; CHECK-NEXT: store float f0x41211525, ptr [[SLOTF]], align 4
+; CHECK-NEXT: store float f0x41A0AF2E, ptr [[SLOTF]], align 4
; CHECK-NEXT: store float 8.000000e+00, ptr [[SLOTF]], align 4
-; CHECK-NEXT: store float 0x3FF193EA80000000, ptr [[SLOTF]], align 4
-; CHECK-NEXT: store float 0x3FDE8927A0000000, ptr [[SLOTF]], align 4
+; CHECK-NEXT: store float f0x3F8C9F54, ptr [[SLOTF]], align 4
+; CHECK-NEXT: store float f0x3EF4493D, ptr [[SLOTF]], align 4
; CHECK-NEXT: store float 8.100000e+01, ptr [[SLOTF]], align 4
-; CHECK-NEXT: store float 0x40240926E0000000, ptr [[SLOTF]], align 4
+; CHECK-NEXT: store float f0x41204937, ptr [[SLOTF]], align 4
; CHECK-NEXT: ret void
;
; MUSL-LABEL: @T(
diff --git a/llvm/test/tools/llubi/bitcast_be.ll b/llvm/test/tools/llubi/bitcast_be.ll
index 8e86f3f325251..d6e73041b25eb 100644
--- a/llvm/test/tools/llubi/bitcast_be.ll
+++ b/llvm/test/tools/llubi/bitcast_be.ll
@@ -38,9 +38,9 @@ entry:
; CHECK-NEXT: %bitcast_int2float1 = bitcast i32 0 to float => float 0.000000e+00
; CHECK-NEXT: %bitcast_int2float2 = bitcast i32 5033160 to float => float 0x004CCCC8
; CHECK-NEXT: %bitcast_float2float1 = bitcast float 2.000000e+00 to float => float 2.000000e+00
-; CHECK-NEXT: %bitcast_float2float2 = bitcast float 0x3FA9999900000000 to float => float 0x3D4CCCC8
+; CHECK-NEXT: %bitcast_float2float2 = bitcast float f0x3D4CCCC8 to float => float 0x3D4CCCC8
; CHECK-NEXT: %bitcast_float2int = bitcast float 2.000000e+00 to i32 => i32 1073741824
-; CHECK-NEXT: %bitcast_half2bf16 = bitcast half 0xH3C00 to bfloat => bfloat 7.812500e-03
+; CHECK-NEXT: %bitcast_half2bf16 = bitcast half 1.000000e+00 to bfloat => bfloat 7.812500e-03
; CHECK-NEXT: %ptr = alloca i32, align 4 => ptr 0x8 [ptr]
; CHECK-NEXT: %bitcast_ptr2ptr = bitcast ptr %ptr to ptr => ptr 0x8 [dangling]
; CHECK-NEXT: %bitcast_vec2scalar1 = bitcast <2 x i32> <i32 0, i32 1> to i64 => i64 1
@@ -54,6 +54,6 @@ entry:
; CHECK-NEXT: %bitcast_vec2vec_down2 = bitcast <4 x i32> <i32 0, i32 1, i32 2, i32 3> to <2 x i64> => { i64 1, i64 8589934595 }
; CHECK-NEXT: %bitcast_vec2vec_weird = bitcast <8 x i3> <i3 0, i3 1, i3 2, i3 3, i3 -4, i3 -3, i3 -2, i3 -1> to <3 x i8> => { i8 5, i8 57, i8 119 }
; CHECK-NEXT: %bitcast_intvec2floatvec = bitcast <2 x i32> <i32 1, i32 2> to <4 x half> => { half 0.000000e+00, half 5.960460e-08, half 0.000000e+00, half 1.192090e-07 }
-; CHECK-NEXT: %bitcast_floatvec2int = bitcast <4 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400> to i64 => i64 4323526012127167488
+; CHECK-NEXT: %bitcast_floatvec2int = bitcast <4 x half> <half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00> to i64 => i64 4323526012127167488
; CHECK-NEXT: ret void
; CHECK-NEXT: Exiting function: main
diff --git a/llvm/test/tools/llubi/bitcast_le.ll b/llvm/test/tools/llubi/bitcast_le.ll
index 773e10feaac99..307638183b1e2 100644
--- a/llvm/test/tools/llubi/bitcast_le.ll
+++ b/llvm/test/tools/llubi/bitcast_le.ll
@@ -38,9 +38,9 @@ entry:
; CHECK-NEXT: %bitcast_int2float1 = bitcast i32 0 to float => float 0.000000e+00
; CHECK-NEXT: %bitcast_int2float2 = bitcast i32 5033160 to float => float 0x004CCCC8
; CHECK-NEXT: %bitcast_float2float1 = bitcast float 2.000000e+00 to float => float 2.000000e+00
-; CHECK-NEXT: %bitcast_float2float2 = bitcast float 0x3FA9999900000000 to float => float 0x3D4CCCC8
+; CHECK-NEXT: %bitcast_float2float2 = bitcast float f0x3D4CCCC8 to float => float 0x3D4CCCC8
; CHECK-NEXT: %bitcast_float2int = bitcast float 2.000000e+00 to i32 => i32 1073741824
-; CHECK-NEXT: %bitcast_half2bf16 = bitcast half 0xH3C00 to bfloat => bfloat 7.812500e-03
+; CHECK-NEXT: %bitcast_half2bf16 = bitcast half 1.000000e+00 to bfloat => bfloat 7.812500e-03
; CHECK-NEXT: %ptr = alloca i32, align 4 => ptr 0x8 [ptr]
; CHECK-NEXT: %bitcast_ptr2ptr = bitcast ptr %ptr to ptr => ptr 0x8 [dangling]
; CHECK-NEXT: %bitcast_vec2scalar1 = bitcast <2 x i32> <i32 0, i32 1> to i64 => i64 4294967296
@@ -54,6 +54,6 @@ entry:
; CHECK-NEXT: %bitcast_vec2vec_down2 = bitcast <4 x i32> <i32 0, i32 1, i32 2, i32 3> to <2 x i64> => { i64 4294967296, i64 12884901890 }
; CHECK-NEXT: %bitcast_vec2vec_weird = bitcast <8 x i3> <i3 0, i3 1, i3 2, i3 3, i3 -4, i3 -3, i3 -2, i3 -1> to <3 x i8> => { i8 -120, i8 -58, i8 -6 }
; CHECK-NEXT: %bitcast_intvec2floatvec = bitcast <2 x i32> <i32 1, i32 2> to <4 x half> => { half 5.960460e-08, half 0.000000e+00, half 1.192090e-07, half 0.000000e+00 }
-; CHECK-NEXT: %bitcast_floatvec2int = bitcast <4 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400> to i64 => i64 4899988963420290048
+; CHECK-NEXT: %bitcast_floatvec2int = bitcast <4 x half> <half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00> to i64 => i64 4899988963420290048
; CHECK-NEXT: ret void
; CHECK-NEXT: Exiting function: main
diff --git a/mlir/test/Target/LLVMIR/llvmir-le-specific.mlir b/mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
index d03f3b70d0567..d2b96642c6428 100644
--- a/mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
+++ b/mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
@@ -4,17 +4,17 @@
// XFAIL: target={{(s390x|sparc.*)-.*}}
// XFAIL: system-aix
-// CHECK{LITERAL}: @dense_resource_tensor_constant = internal constant [5 x float] [float 0x3FCA034080000000, float 0xBFD0466300000000, float 0xBFD75DDF80000000, float 0xBFDE074F40000000, float 0x3FDDD3A1C0000000]
+// CHECK{LITERAL}: @dense_resource_tensor_constant = internal constant [5 x float] [float f0x3E501A04, float f0xBE823318, float f0xBEBAEEFC, float f0xBEF03A7A, float f0x3EEE9D0E]
llvm.mlir.global internal constant @dense_resource_tensor_constant(dense_resource<dense_resource_test_5xf32> : tensor<5xf32>) : !llvm.array<5 x f32>
-// CHECK{LITERAL}: @dense_resource_vector_constant = internal constant <5 x float> <float 0x3FCA034080000000, float 0xBFD0466300000000, float 0xBFD75DDF80000000, float 0xBFDE074F40000000, float 0x3FDDD3A1C0000000>
+// CHECK{LITERAL}: @dense_resource_vector_constant = internal constant <5 x float> <float f0x3E501A04, float f0xBE823318, float f0xBEBAEEFC, float f0xBEF03A7A, float f0x3EEE9D0E>
llvm.mlir.global internal constant @dense_resource_vector_constant(dense_resource<dense_resource_test_5xf32> : vector<5xf32>) : vector<5xf32>
-// CHECK{LITERAL}: @dense_resource_multidim_tensor_constant = internal constant [1 x [2 x [2 x float]]] [[2 x [2 x float]] [[2 x float] [float 0x3FD6B46A80000000, float 0x3FD6781AC0000000], [2 x float] [float 0xBFB45A2AA0000000, float 0x3FD77A5CA0000000]]]
+// CHECK{LITERAL}: @dense_resource_multidim_tensor_constant = internal constant [1 x [2 x [2 x float]]] [[2 x [2 x float]] [[2 x float] [float f0x3EB5A354, float f0x3EB3C0D6], [2 x float] [float f0xBDA2D155, float f0x3EBBD2E5]]]
llvm.mlir.global internal constant @dense_resource_multidim_tensor_constant(dense_resource<dense_resource_test_2x2xf32> : tensor<1x2x2xf32>) : !llvm.array<1 x !llvm.array<2 x !llvm.array<2 x f32>>>
-// CHECK{LITERAL}: @dense_resource_multidim_vector_constant = internal constant [1 x [2 x <2 x float>]] [[2 x <2 x float>] [<2 x float> <float 0x3FD6B46A80000000, float 0x3FD6781AC0000000>, <2 x float> <float 0xBFB45A2AA0000000, float 0x3FD77A5CA0000000>]]
+// CHECK{LITERAL}: @dense_resource_multidim_vector_constant = internal constant [1 x [2 x <2 x float>]] [[2 x <2 x float>] [<2 x float> <float f0x3EB5A354, float f0x3EB3C0D6>, <2 x float> <float f0xBDA2D155, float f0x3EBBD2E5>]]
llvm.mlir.global internal constant @dense_resource_multidim_vector_constant(dense_resource<dense_resource_test_2x2xf32> : vector<1x2x2xf32>) : !llvm.array<1 x !llvm.array<2 x vector<2 x f32>>>
// Resources are kept at end of file. New tests should be added above this.
diff --git a/mlir/test/Target/LLVMIR/llvmir.mlir b/mlir/test/Target/LLVMIR/llvmir.mlir
index e864197068dc3..58c08fed772b0 100644
--- a/mlir/test/Target/LLVMIR/llvmir.mlir
+++ b/mlir/test/Target/LLVMIR/llvmir.mlir
@@ -45,16 +45,16 @@ llvm.mlir.global internal @splat_neg_float_global_array(dense<-13.5> : tensor<4x
// CHECK: @splat_neg_double_global_array = internal global [3 x double] [double -1.350000e+01, double -1.350000e+01, double -1.350000e+01]
llvm.mlir.global internal @splat_neg_double_global_array(dense<-13.5> : tensor<3xf64>) : !llvm.array<3 x f64>
-// CHECK: @splat_half_global_array = internal global [4 x half] [half 0xH5140, half 0xH5140, half 0xH5140, half 0xH5140]
+// CHECK: @splat_half_global_array = internal global [4 x half] [half 4.200000e+01, half 4.200000e+01, half 4.200000e+01, half 4.200000e+01]
llvm.mlir.global internal @splat_half_global_array(dense<42.0> : tensor<4xf16>) : !llvm.array<4 x f16>
-// CHECK: @splat_bfloat_global_array = internal global [3 x bfloat] [bfloat 0xR4228, bfloat 0xR4228, bfloat 0xR4228]
+// CHECK: @splat_bfloat_global_array = internal global [3 x bfloat] [bfloat 4.200000e+01, bfloat 4.200000e+01, bfloat 4.200000e+01]
llvm.mlir.global internal @splat_bfloat_global_array(dense<42.0> : tensor<3xbf16>) : !llvm.array<3 x bf16>
-// CHECK: @splat_neg_half_global_array = internal global [4 x half] [half 0xHCAC0, half 0xHCAC0, half 0xHCAC0, half 0xHCAC0]
+// CHECK: @splat_neg_half_global_array = internal global [4 x half] [half -1.350000e+01, half -1.350000e+01, half -1.350000e+01, half -1.350000e+01]
llvm.mlir.global internal @splat_neg_half_global_array(dense<-13.5> : tensor<4xf16>) : !llvm.array<4 x f16>
-// CHECK: @splat_neg_bfloat_global_array = internal global [3 x bfloat] [bfloat 0xRC158, bfloat 0xRC158, bfloat 0xRC158]
+// CHECK: @splat_neg_bfloat_global_array = internal global [3 x bfloat] [bfloat -1.350000e+01, bfloat -1.350000e+01, bfloat -1.350000e+01]
llvm.mlir.global internal @splat_neg_bfloat_global_array(dense<-13.5> : tensor<3xbf16>) : !llvm.array<3 x bf16>
// CHECK: @string_const = internal constant [6 x i8] c"foobar"
@@ -1530,7 +1530,7 @@ llvm.func @alloca(%size : i64) {
// CHECK-LABEL: @constants
llvm.func @constants() -> vector<4xf32> {
- // CHECK: ret <4 x float> <float 4.2{{0*}}e+01, float 0.{{0*}}e+00, float 0.{{0*}}e+00, float 0.{{0*}}e+00>
+ // CHECK: ret <4 x float> <float 4.2{{0*}}e+01, float 0.0{{0*}}e+00, float 0.0{{0*}}e+00, float 0.0{{0*}}e+00>
%0 = llvm.mlir.constant(sparse<[0], [4.2e+01]> : vector<4xf32>) : vector<4xf32>
llvm.return %0 : vector<4xf32>
}
@@ -1908,7 +1908,7 @@ llvm.func @constant_bf16() -> bf16 {
llvm.return %0 : bf16
}
-// CHECK: ret bfloat 0xR4120
+// CHECK: ret bfloat 1.000000e+01
// -----
diff --git a/mlir/test/Target/LLVMIR/openmp-private.mlir b/mlir/test/Target/LLVMIR/openmp-private.mlir
index d46bfa529da6c..e93f246f80f70 100644
--- a/mlir/test/Target/LLVMIR/openmp-private.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-private.mlir
@@ -264,7 +264,7 @@ omp.private {type = firstprivate} @_QFequivalenceEx_firstprivate_ptr_f32 : f32 c
// Test that we initialize the firstprivate variable.
// CHECK: store float %[[HOST_VAL]], ptr %[[PRIV_ALLOC]], align 4
// Test that we inlined the body of the parallel region.
-// CHECK: store float 0x{{.*}}, ptr %[[PRIV_ALLOC]], align 4
+// CHECK: store float 3.140000e+00, ptr %[[PRIV_ALLOC]], align 4
// -----
diff --git a/mlir/test/Target/LLVMIR/openmp-wsloop-private.mlir b/mlir/test/Target/LLVMIR/openmp-wsloop-private.mlir
index 0b1f45ad7ce1c..878c6fe1da20f 100644
--- a/mlir/test/Target/LLVMIR/openmp-wsloop-private.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-wsloop-private.mlir
@@ -72,7 +72,7 @@ llvm.func @wsloop_private_(%arg0: !llvm.ptr {fir.bindc_name = "y"}) attributes {
// Third, check that reduction init took place.
// CHECK: [[RED_INIT_BB]]:
-// CHECK: store float 0x{{.*}}, ptr %[[FLT]], align 4
+// CHECK: store float f0x{{.*}}, ptr %[[FLT]], align 4
// Finally, check for the private dealloc region
// CHECK: call void @foo_free(ptr %[[CHR]])
>From 6e880884cd018d47f442794f96e1020b34ad27b4 Mon Sep 17 00:00:00 2001
From: Joshua Cranmer <joshua.cranmer at intel.com>
Date: Mon, 27 Apr 2026 10:59:35 -0700
Subject: [PATCH 2/2] Automated tool rewrites.
---
clang/test/AST/ByteCode/codegen.cpp | 2 +-
clang/test/AST/ByteCode/const-fpfeatures.cpp | 16 +-
clang/test/AST/const-fpfeatures.c | 26 +-
clang/test/AST/const-fpfeatures.cpp | 38 +-
clang/test/C/C11/n1396.c | 40 +-
clang/test/C/C2y/n3460_1.c | 4 +-
clang/test/CIR/CodeGen/atomic.c | 4 +-
clang/test/CIR/CodeGen/binassign.c | 4 +-
clang/test/CIR/CodeGen/comma.c | 4 +-
clang/test/CIR/CodeGen/complex.cpp | 8 +-
clang/test/CIR/CodeGen/throws.cpp | 6 +-
clang/test/CIR/CodeGen/union.c | 4 +-
clang/test/CIR/CodeGen/union.cpp | 4 +-
.../CodeGenBuiltins/X86/avx512fp16-builtins.c | 8 +-
.../X86/avx512vlfp16-builtins.c | 16 +-
.../test/CIR/CodeGenBuiltins/builtin-call.cpp | 16 +-
.../CIR/CodeGenBuiltins/builtin-isinf-sign.c | 2 +-
.../CIR/CodeGenBuiltins/builtin-signbit.c | 16 +-
clang/test/CIR/Lowering/global-var-simple.cpp | 16 +-
.../AArch64/atomic-ops-float-check-minmax.c | 12 +-
clang/test/CodeGen/AArch64/neon/fullfp16.c | 2 +-
.../v8.2a-fp16-intrinsics-constrained.c | 20 +-
.../CodeGen/AArch64/v8.2a-fp16-intrinsics.c | 8 +-
.../test/CodeGen/AMDGPU/amdgpu-atomic-float.c | 24 +-
.../CodeGen/PowerPC/ppc64-complex-parms.c | 8 +-
clang/test/CodeGen/RISCV/riscv64-vararg.c | 6 +-
.../CodeGen/SystemZ/atomic_is_lock_free.c | 2 +-
.../builtins-systemz-zvector-constrained.c | 8 +-
.../SystemZ/builtins-systemz-zvector.c | 8 +-
clang/test/CodeGen/X86/Float16-arithmetic.c | 2 +-
clang/test/CodeGen/X86/Float16-complex.c | 58 +-
clang/test/CodeGen/X86/avx512fp16-builtins.c | 20 +-
.../test/CodeGen/X86/avx512vlfp16-builtins.c | 22 +-
.../test/CodeGen/X86/x86-atomic-long_double.c | 40 +-
clang/test/CodeGen/X86/x86_64-longdouble.c | 8 +-
clang/test/CodeGen/attr-target-mv.c | 4 +-
clang/test/CodeGen/builtin-nan-exception.c | 6 +-
clang/test/CodeGen/builtin-nan-legacy.c | 4 +-
clang/test/CodeGen/builtin_Float16.c | 8 +-
.../test/CodeGen/builtins-elementwise-math.c | 2 +-
clang/test/CodeGen/builtins-nvptx.c | 40 +-
clang/test/CodeGen/builtins-reduction-math.c | 4 +-
clang/test/CodeGen/captured-statements.c | 2 +-
clang/test/CodeGen/complex-init-list.c | 2 +-
clang/test/CodeGen/complex_Float16.c | 2 +-
clang/test/CodeGen/conditional.c | 2 +-
.../CodeGen/constexpr-c23-internal-linkage.c | 2 +-
clang/test/CodeGen/cx-complex-range-real.c | 8 +-
clang/test/CodeGen/ext-vector.c | 2 +-
clang/test/CodeGen/fp-floatcontrol-pragma.cpp | 2 +-
clang/test/CodeGen/fp16-ops-strictfp.c | 12 +-
clang/test/CodeGen/fp16-ops.c | 6 +-
clang/test/CodeGen/isfpclass.c | 4 +-
clang/test/CodeGen/logb_scalbn.c | 204 +++---
clang/test/CodeGen/math-builtins-long.c | 16 +-
clang/test/CodeGen/mingw-long-double.c | 8 +-
clang/test/CodeGen/mips-unsupported-nan.c | 8 +-
clang/test/CodeGen/ppc-vec_ct-truncate.c | 16 +-
clang/test/CodeGen/rounding-math.c | 6 +-
clang/test/CodeGen/rounding-math.cpp | 24 +-
clang/test/CodeGen/spir-half-type.cpp | 40 +-
clang/test/CodeGen/strictfp_builtins.c | 6 +-
clang/test/CodeGenCUDA/long-double.cu | 2 +-
clang/test/CodeGenCUDA/printf.cu | 2 +-
clang/test/CodeGenCUDA/types.cu | 2 +-
clang/test/CodeGenCXX/auto-var-init.cpp | 58 +-
clang/test/CodeGenCXX/blocks-cxx11.cpp | 2 +-
clang/test/CodeGenCXX/const-init.cpp | 2 +-
.../CodeGenCXX/cxx11-user-defined-literal.cpp | 2 +-
.../test/CodeGenCXX/float128-declarations.cpp | 48 +-
.../test/CodeGenCXX/float16-declarations.cpp | 32 +-
clang/test/CodeGenCXX/ibm128-declarations.cpp | 2 +-
.../lambda-deterministic-captures.cpp | 6 +-
.../BasicFeatures/ArrayElementwiseCast.hlsl | 2 +-
.../BasicFeatures/frem_modulo.hlsl | 8 +-
.../CodeGenHLSL/Operators/logical-not.hlsl | 2 +-
clang/test/CodeGenHLSL/RootSignature.hlsl | 2 +-
.../builtins/D3DCOLORtoUBYTE4.hlsl | 2 +-
.../CodeGenHLSL/builtins/VectorSwizzles.hlsl | 2 +-
clang/test/CodeGenHLSL/builtins/dst.hlsl | 2 +-
.../CodeGenHLSL/builtins/faceforward.hlsl | 8 +-
clang/test/CodeGenHLSL/builtins/lit.hlsl | 12 +-
.../CodeGenHLSL/builtins/rcp-builtin.hlsl | 2 +-
clang/test/CodeGenHLSL/builtins/rcp.hlsl | 8 +-
clang/test/CodeGenHLSL/builtins/reflect.hlsl | 10 +-
clang/test/CodeGenHLSL/builtins/refract.hlsl | 20 +-
.../test/CodeGenHLSL/builtins/smoothstep.hlsl | 16 +-
.../resources-in-structs-inheritance.hlsl | 8 +-
.../resources/resources-in-structs.hlsl | 4 +-
.../vk-features/vk.spec-constant.hlsl | 4 +-
clang/test/CodeGenObjC/objc-literal-tests.m | 4 +-
.../objc2-constant-number-literal.m | 10 +-
clang/test/CodeGenOpenCL/amdgpu-alignment.cl | 8 +-
clang/test/CodeGenOpenCL/half.cl | 8 +-
clang/test/Frontend/fixed_point_compound.c | 14 +-
clang/test/Frontend/fixed_point_conversions.c | 20 +-
.../Frontend/fixed_point_conversions_const.c | 2 +-
.../Frontend/fixed_point_conversions_half.c | 42 +-
clang/test/Headers/__clang_hip_math.hip | 116 +--
clang/test/Headers/cuda_wrapper_algorithm.cu | 8 +-
clang/test/OpenMP/atomic_capture_codegen.cpp | 2 +-
clang/test/OpenMP/atomic_update_codegen.cpp | 2 +-
.../declare_target_constexpr_codegen.cpp | 2 +-
clang/test/OpenMP/for_reduction_codegen.cpp | 2 +-
.../OpenMP/parallel_reduction_codegen.cpp | 4 +-
.../OpenMP/sections_reduction_codegen.cpp | 2 +-
flang/test/Fir/target-complex16.f90 | 2 +-
.../Analysis/CostModel/AArch64/arith-bf16.ll | 24 +-
.../Analysis/CostModel/AArch64/arith-fp.ll | 16 +-
.../CostModel/AArch64/insert-extract.ll | 4 +-
.../Analysis/CostModel/AArch64/pow-special.ll | 24 +-
.../Analysis/CostModel/AArch64/reduce-fadd.ll | 96 +--
llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll | 160 ++---
llvm/test/Analysis/CostModel/ARM/divrem.ll | 80 +--
llvm/test/Analysis/CostModel/ARM/reduce-fp.ll | 96 +--
.../Analysis/CostModel/RISCV/phi-const.ll | 2 +-
.../Analysis/CostModel/RISCV/reduce-fadd.ll | 448 ++++++------
.../Analysis/CostModel/RISCV/reduce-fmul.ll | 252 +++----
.../Analysis/CostModel/RISCV/rvv-phi-const.ll | 6 +-
.../TypeBasedAliasAnalysis/dynamic-indices.ll | 2 +-
llvm/test/Assembler/2002-04-07-InfConstant.ll | 2 +-
.../2005-01-03-FPConstantDisassembly.ll | 2 +-
llvm/test/Assembler/constant-splat.ll | 10 +-
llvm/test/Assembler/float-literals.ll | 6 +-
llvm/test/Assembler/short-hexpair.ll | 2 +-
llvm/test/Bitcode/compatibility-3.6.ll | 2 +-
llvm/test/Bitcode/compatibility-3.7.ll | 2 +-
llvm/test/Bitcode/compatibility-3.8.ll | 6 +-
llvm/test/Bitcode/compatibility-3.9.ll | 6 +-
llvm/test/Bitcode/compatibility-4.0.ll | 6 +-
llvm/test/Bitcode/compatibility-5.0.ll | 6 +-
llvm/test/Bitcode/compatibility-6.0.ll | 6 +-
llvm/test/Bitcode/compatibility.ll | 6 +-
llvm/test/Bitcode/constant-splat.ll | 10 +-
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llvm/test/CodeGen/AArch64/convertphitype.ll | 2 +-
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.../AMDGPU/GlobalISel/legalize-fdiv.mir | 4 +-
.../AMDGPU/GlobalISel/legalize-fexp.mir | 132 ++--
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.../AMDGPU/GlobalISel/legalize-flog.mir | 52 +-
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.../AMDGPU/GlobalISel/legalize-fptoui.mir | 54 +-
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.../AMDGPU/GlobalISel/legalize-fshr.mir | 6 +-
.../AMDGPU/GlobalISel/legalize-fsin.mir | 60 +-
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.../AMDGPU/GlobalISel/legalize-rotl-rotr.mir | 6 +-
.../AMDGPU/GlobalISel/legalize-sdiv.mir | 144 ++--
.../AMDGPU/GlobalISel/legalize-sitofp.mir | 8 +-
.../AMDGPU/GlobalISel/legalize-srem.mir | 144 ++--
.../AMDGPU/GlobalISel/legalize-udiv.mir | 144 ++--
.../AMDGPU/GlobalISel/legalize-uitofp.mir | 8 +-
.../AMDGPU/GlobalISel/legalize-urem.mir | 144 ++--
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.../regbankcombiner-fmed3-minmax-const.mir | 20 +-
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.../AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll | 8 +-
.../AMDGPU/amdgpu-codegenprepare-fdiv.ll | 244 +++----
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.../AMDGPU/amdgpu-simplify-libcall-pow.ll | 658 +++++++++---------
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.../AMDGPU/amdgpu-simplify-libcall-pown.ll | 16 +-
.../AMDGPU/amdgpu-simplify-libcall-powr.ll | 500 ++++++-------
.../AMDGPU/amdgpu-simplify-libcall-rootn.ll | 110 +--
.../amdgpu-simplify-libcall-tdo-acos.ll | 12 +-
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llvm/test/CodeGen/AMDGPU/fract-match.ll | 298 ++++----
.../AMDGPU/global_atomic_optimizer_fp_rtn.ll | 84 +--
.../global_atomics_optimizer_fp_no_rtn.ll | 64 +-
llvm/test/CodeGen/AMDGPU/lower-module-lds.ll | 2 +-
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.../CodeGen/AMDGPU/promote-alloca-subvecs.ll | 16 +-
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llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll | 4 +-
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.../ARM/GlobalISel/arm-legalize-fp.mir | 4 +-
llvm/test/CodeGen/ARM/vector-promotion.ll | 8 +-
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llvm/test/CodeGen/DirectX/all.ll | 2 +-
llvm/test/CodeGen/DirectX/any.ll | 2 +-
llvm/test/CodeGen/DirectX/atan2.ll | 32 +-
llvm/test/CodeGen/DirectX/degrees.ll | 12 +-
llvm/test/CodeGen/DirectX/exp-vec.ll | 2 +-
llvm/test/CodeGen/DirectX/exp.ll | 4 +-
llvm/test/CodeGen/DirectX/log-vec.ll | 4 +-
llvm/test/CodeGen/DirectX/log.ll | 4 +-
llvm/test/CodeGen/DirectX/log10.ll | 4 +-
llvm/test/CodeGen/DirectX/radians.ll | 20 +-
llvm/test/CodeGen/DirectX/sign.ll | 4 +-
llvm/test/CodeGen/DirectX/step.ll | 8 +-
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.../CodeGen/MIR/Generic/bfloat-immediates.mir | 4 +-
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.../GlobalISel/legalizer/float_constants.mir | 8 +-
.../legalizer/fptosi_and_fptoui.mir | 24 +-
.../legalizer/sitofp_and_uitofp.mir | 24 +-
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.../CodeGen/PowerPC/ppc_fp128-bcwriter.ll | 2 +-
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.../aarch64-bf16-dotprod-intrinsics.ll | 4 +-
.../NumericalStabilitySanitizer/basic.ll | 36 +-
.../NumericalStabilitySanitizer/intrinsics.ll | 204 +++---
.../NumericalStabilitySanitizer/libfuncs.ll | 168 ++---
.../non_float_store.ll | 4 +-
.../AMDGPU/nofpclass-amdgcn-trig-preop.ll | 8 +-
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.../Attributor/nofpclass-canonicalize.ll | 48 +-
.../Transforms/Attributor/nofpclass-fmul.ll | 52 +-
.../Attributor/nofpclass-implied-by-fcmp.ll | 112 +--
.../Attributor/nofpclass-nan-fmul.ll | 2 +-
.../Transforms/Attributor/nofpclass-select.ll | 44 +-
llvm/test/Transforms/Attributor/nofpclass.ll | 40 +-
.../Attributor/value-simplify-pointer-info.ll | 36 +-
llvm/test/Transforms/DCE/calls-errno.ll | 4 +-
llvm/test/Transforms/EarlyCSE/atan.ll | 18 +-
.../ExpandIRInsts/AMDGPU/frem-inf.ll | 12 +-
.../Transforms/ExpandIRInsts/AMDGPU/frem.ll | 130 ++--
.../X86/expand-int-convert-small.ll | 10 +-
.../X86/expand-large-fp-convert-si129tofp.ll | 6 +-
.../X86/expand-large-fp-convert-ui129tofp.ll | 6 +-
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llvm/test/Transforms/Float2Int/pr167627.ll | 2 +-
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llvm/test/Transforms/FunctionAttrs/noundef.ll | 2 +-
llvm/test/Transforms/GVN/edge.ll | 2 +-
llvm/test/Transforms/GVN/no-mem-dep-info.ll | 4 +-
llvm/test/Transforms/GVNHoist/hoist-call.ll | 2 +-
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llvm/test/Transforms/Inline/simplify-fp128.ll | 4 +-
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.../AArch64/sve-intrinsic-simplify-binop.ll | 2 +-
.../InstCombine/AMDGPU/amdgcn-intrinsics.ll | 160 ++---
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.../InstCombine/AMDGPU/fmed3-fpext-fold.ll | 22 +-
.../Transforms/InstCombine/AMDGPU/fmed3.ll | 30 +-
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.../InstCombine/X86/x86-scalar-max-min.ll | 4 +-
llvm/test/Transforms/InstCombine/and-fcmp.ll | 68 +-
llvm/test/Transforms/InstCombine/atomicrmw.ll | 28 +-
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llvm/test/Transforms/InstCombine/bitcast.ll | 10 +-
.../InstCombine/canonicalize-const-to-bop.ll | 6 +-
.../InstCombine/canonicalize-fcmp-inf.ll | 40 +-
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.../InstCombine/constant-fold-libfunc.ll | 2 +-
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.../InstCombine/constant-fold-nextafter.ll | 38 +-
.../constant-fold-nexttoward-fp128.ll | 40 +-
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.../Transforms/InstCombine/constrained.ll | 4 +-
.../InstCombine/copysign-fneg-fabs.ll | 14 +-
llvm/test/Transforms/InstCombine/copysign.ll | 2 +-
.../create-class-from-logic-fcmp.ll | 228 +++---
.../InstCombine/double-float-shrink-2.ll | 4 +-
llvm/test/Transforms/InstCombine/erf.ll | 32 +-
llvm/test/Transforms/InstCombine/exp2-1.ll | 2 +-
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llvm/test/Transforms/InstCombine/fabs.ll | 16 +-
.../InstCombine/fadd-fsub-factor.ll | 10 +-
llvm/test/Transforms/InstCombine/fadd.ll | 6 +-
llvm/test/Transforms/InstCombine/fast-math.ll | 20 +-
.../InstCombine/fcmp-denormals-are-zero.ll | 32 +-
.../InstCombine/fcmp-range-check-idiom.ll | 54 +-
.../Transforms/InstCombine/fcmp-select.ll | 14 +-
.../Transforms/InstCombine/fcmp-special.ll | 4 +-
llvm/test/Transforms/InstCombine/fcmp.ll | 84 +--
llvm/test/Transforms/InstCombine/fdim.ll | 12 +-
.../Transforms/InstCombine/fdiv-cos-sin.ll | 2 +-
llvm/test/Transforms/InstCombine/fdiv.ll | 34 +-
llvm/test/Transforms/InstCombine/fma.ll | 52 +-
llvm/test/Transforms/InstCombine/fmod.ll | 2 +-
llvm/test/Transforms/InstCombine/fmul.ll | 24 +-
llvm/test/Transforms/InstCombine/fneg.ll | 14 +-
.../InstCombine/fold-bin-operand.ll | 2 +-
.../test/Transforms/InstCombine/fold-calls.ll | 4 +-
.../Transforms/InstCombine/fold-fcmp-trunc.ll | 102 +--
.../InstCombine/fold-fops-into-selects.ll | 2 +-
.../InstCombine/fold-select-fmul-if-zero.ll | 12 +-
.../InstCombine/fpclass-check-idioms.ll | 20 +-
.../InstCombine/fpclass-from-dom-cond.ll | 16 +-
llvm/test/Transforms/InstCombine/fpextend.ll | 6 +-
llvm/test/Transforms/InstCombine/fptrunc.ll | 6 +-
llvm/test/Transforms/InstCombine/frexp.ll | 26 +-
llvm/test/Transforms/InstCombine/fsub.ll | 2 +-
llvm/test/Transforms/InstCombine/ilogb.ll | 16 +-
.../InstCombine/intrinsic-select.ll | 8 +-
.../test/Transforms/InstCombine/is_fpclass.ll | 64 +-
.../test/Transforms/InstCombine/known-bits.ll | 6 +-
llvm/test/Transforms/InstCombine/ldexp.ll | 26 +-
.../InstCombine/load-store-forward.ll | 2 +-
llvm/test/Transforms/InstCombine/load.ll | 2 +-
llvm/test/Transforms/InstCombine/load3.ll | 2 +-
llvm/test/Transforms/InstCombine/log-pow.ll | 6 +-
.../InstCombine/log-to-intrinsic.ll | 12 +-
llvm/test/Transforms/InstCombine/log1p.ll | 32 +-
llvm/test/Transforms/InstCombine/logb.ll | 8 +-
llvm/test/Transforms/InstCombine/maximum.ll | 16 +-
llvm/test/Transforms/InstCombine/maxnum.ll | 4 +-
llvm/test/Transforms/InstCombine/minimum.ll | 16 +-
llvm/test/Transforms/InstCombine/minnum.ll | 4 +-
llvm/test/Transforms/InstCombine/nan.ll | 8 +-
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llvm/test/Transforms/InstCombine/nanl-fp80.ll | 6 +-
.../Transforms/InstCombine/nanl-ppc-fp128.ll | 6 +-
.../nanless-canonicalize-combine.ll | 38 +-
.../test/Transforms/InstCombine/opaque-ptr.ll | 2 +-
llvm/test/Transforms/InstCombine/pow-1.ll | 38 +-
llvm/test/Transforms/InstCombine/pow-3.ll | 4 +-
llvm/test/Transforms/InstCombine/pow-cbrt.ll | 24 +-
llvm/test/Transforms/InstCombine/pow-sqrt.ll | 18 +-
.../Transforms/InstCombine/pow-to-ldexp.ll | 14 +-
.../test/Transforms/InstCombine/pow_fp_int.ll | 6 +-
llvm/test/Transforms/InstCombine/remquo.ll | 8 +-
.../Transforms/InstCombine/remquol-fp128.ll | 2 +-
.../Transforms/InstCombine/remquol-fp80.ll | 2 +-
.../InstCombine/remquol-ppc-fp128.ll | 2 +-
.../InstCombine/scalarization-inseltpoison.ll | 4 +-
.../Transforms/InstCombine/scalarization.ll | 4 +-
.../select-fcmp-fmul-zero-absorbing-value.ll | 36 +-
.../select-with-extreme-eq-cond.ll | 4 +-
llvm/test/Transforms/InstCombine/select.ll | 2 +-
.../InstCombine/select_with_identical_phi.ll | 32 +-
.../shufflevec-constant-inseltpoison.ll | 2 +-
.../InstCombine/shufflevec-constant.ll | 2 +-
.../simplify-demanded-fpclass-aggregates.ll | 14 +-
.../simplify-demanded-fpclass-canonicalize.ll | 4 +-
.../simplify-demanded-fpclass-exp.ll | 24 +-
...implify-demanded-fpclass-extractelement.ll | 8 +-
.../simplify-demanded-fpclass-fadd.ll | 40 +-
.../simplify-demanded-fpclass-fdiv.ll | 186 ++---
.../simplify-demanded-fpclass-fma.ll | 16 +-
.../simplify-demanded-fpclass-fmul.ll | 36 +-
.../simplify-demanded-fpclass-fpext.ll | 12 +-
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.../simplify-demanded-fpclass-fptrunc.ll | 16 +-
.../simplify-demanded-fpclass-frexp.ll | 16 +-
.../simplify-demanded-fpclass-fsub.ll | 54 +-
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.../simplify-demanded-fpclass-ldexp.ll | 8 +-
.../simplify-demanded-fpclass-log.ll | 12 +-
.../simplify-demanded-fpclass-maximum.ll | 32 +-
.../simplify-demanded-fpclass-maximumnum.ll | 40 +-
.../simplify-demanded-fpclass-maxnum.ll | 40 +-
.../simplify-demanded-fpclass-minimum.ll | 32 +-
.../simplify-demanded-fpclass-minimumnum.ll | 40 +-
.../simplify-demanded-fpclass-minnum.ll | 40 +-
.../simplify-demanded-fpclass-phi.ll | 50 +-
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.../simplify-demanded-fpclass-sqrt.ll | 16 +-
.../InstCombine/simplify-demanded-fpclass.ll | 58 +-
llvm/test/Transforms/InstCombine/sqrt.ll | 2 +-
.../unordered-compare-and-ordered.ll | 62 +-
llvm/test/Transforms/InstCombine/win-fdim.ll | 2 +-
.../2011-09-05-InsertExtractValue.ll | 2 +-
.../InstSimplify/ConstProp/AMDGPU/fract.ll | 40 +-
.../ConstProp/WebAssembly/trunc.ll | 122 ++--
.../InstSimplify/ConstProp/atan-intrinsic.ll | 10 +-
.../InstSimplify/ConstProp/calls.ll | 26 +-
.../Transforms/InstSimplify/ConstProp/cast.ll | 10 +-
.../ConstProp/convert-from-fp16.ll | 14 +-
.../InstSimplify/ConstProp/copysign.ll | 18 +-
.../Transforms/InstSimplify/ConstProp/fma.ll | 48 +-
.../InstSimplify/ConstProp/fp-undef.ll | 136 ++--
.../InstSimplify/ConstProp/libfunc.ll | 2 +-
.../InstSimplify/ConstProp/loads.ll | 16 +-
.../InstSimplify/ConstProp/logf128.ll | 44 +-
.../InstSimplify/ConstProp/min-max.ll | 84 +--
.../ConstProp/sinh-cosh-intrinsics.ll | 16 +-
.../vector-undef-elts-inseltpoison.ll | 4 +-
.../ConstProp/vector-undef-elts.ll | 4 +-
.../ConstProp/vscale-inseltpoison.ll | 2 +-
.../InstSimplify/ConstProp/vscale.ll | 2 +-
.../InstSimplify/X86/fp-nan-strictfp.ll | 104 +--
.../assume-fcmp-constant-implies-class.ll | 30 +-
.../InstSimplify/bitcast-vector-fold.ll | 36 +-
llvm/test/Transforms/InstSimplify/call.ll | 40 +-
.../Transforms/InstSimplify/canonicalize.ll | 122 ++--
.../InstSimplify/const-fold-nvvm-add.ll | 96 +--
.../InstSimplify/const-fold-nvvm-div.ll | 120 ++--
.../InstSimplify/const-fold-nvvm-fma.ll | 92 +--
.../InstSimplify/const-fold-nvvm-fmin-fmax.ll | 120 ++--
.../InstSimplify/const-fold-nvvm-mul.ll | 92 +--
.../const-fold-nvvm-unary-arithmetic.ll | 38 +-
.../InstSimplify/constant-fold-fp-denormal.ll | 94 +--
.../InstSimplify/constfold-constrained.ll | 34 +-
.../InstSimplify/disable_folding.ll | 2 +-
llvm/test/Transforms/InstSimplify/exp10.ll | 28 +-
llvm/test/Transforms/InstSimplify/fcmp.ll | 2 +-
.../InstSimplify/floating-point-arithmetic.ll | 58 +-
.../InstSimplify/floating-point-compare.ll | 28 +-
.../Transforms/InstSimplify/fminmax-folds.ll | 146 ++--
.../InstSimplify/fold-bfloat-half-bitcasts.ll | 10 +-
llvm/test/Transforms/InstSimplify/fp-nan.ll | 56 +-
.../InstSimplify/fp-undef-poison-strictfp.ll | 26 +-
.../InstSimplify/fp-undef-poison.ll | 32 +-
.../InstSimplify/known-never-infinity.ll | 110 +--
.../InstSimplify/known-never-nan.ll | 4 +-
llvm/test/Transforms/InstSimplify/ldexp.ll | 90 +--
llvm/test/Transforms/InstSimplify/pr122582.ll | 16 +-
.../InstSimplify/select-equivalence-fp.ll | 4 +-
llvm/test/Transforms/InstSimplify/sincos.ll | 8 +-
.../Transforms/InstSimplify/strictfp-fadd.ll | 24 +-
.../InstSimplify/vscale-inseltpoison.ll | 2 +-
llvm/test/Transforms/InstSimplify/vscale.ll | 2 +-
llvm/test/Transforms/LICM/hoist-fast-fdiv.ll | 2 +-
.../AMDGPU/merge-stores.ll | 4 +-
.../X86/massive_indirection.ll | 8 +-
.../LoopLoadElim/type-mismatch-opaque-ptr.ll | 2 +-
.../Transforms/LoopLoadElim/type-mismatch.ll | 2 +-
.../X86/preserving-debugloc-phi-binop.ll | 2 +-
.../AArch64/early_exit_with_stores.ll | 2 +-
.../AArch64/partial-reduce-fdot-product.ll | 8 +-
.../AArch64/scalable-reduction-inloop-cond.ll | 2 +-
.../AArch64/scalable-reductions.ll | 2 +-
.../AArch64/scalar_interleave.ll | 2 +-
.../sve-epilog-vect-strict-reductions.ll | 6 +-
.../LoopVectorize/AArch64/sve-illegal-type.ll | 4 +-
.../LoopVectorize/AMDGPU/packed-math.ll | 6 +-
.../ARM/tail-folding-not-allowed.ll | 4 +-
.../RISCV/early_exit_with_stores.ll | 2 +-
.../LoopVectorize/RISCV/illegal-type.ll | 2 +-
.../LoopVectorize/RISCV/reductions.ll | 30 +-
.../RISCV/tail-folding-inloop-reduction.ll | 4 +-
.../LoopVectorize/X86/cast-costs.ll | 2 +-
.../LoopVectorize/X86/fp80-widest-type.ll | 4 +-
.../X86/x86_fp80-vector-store.ll | 6 +-
.../LoopVectorize/consecutive-ptr-uniforms.ll | 32 +-
.../LoopVectorize/early_exit_with_stores.ll | 2 +-
.../LoopVectorize/float-induction.ll | 26 +-
.../float-minmax-instruction-flag.ll | 2 +-
.../LoopVectorize/reduction-inloop-cond.ll | 2 +-
.../LoopVectorize/select-cmp-multiuse.ll | 6 +-
.../LoopVectorize/select-first-index-fp.ll | 24 +-
.../LoopVectorize/select-last-index-fp.ll | 20 +-
.../MemCpyOpt/2008-02-24-MultipleUseofSRet.ll | 4 +-
llvm/test/Transforms/MemCpyOpt/memcpy-tbaa.ll | 2 +-
llvm/test/Transforms/MemCpyOpt/memcpy.ll | 2 +-
llvm/test/Transforms/MemCpyOpt/sret.ll | 2 +-
.../OpenMP/parallel_region_merging.ll | 2 +-
.../Transforms/OpenMP/spmdization_assumes.ll | 2 +-
.../PhaseOrdering/X86/vector-reductions.ll | 4 +-
.../Transforms/PlaceSafepoints/libcall.ll | 2 +-
.../PreISelIntrinsicLowering/expand-vp.ll | 24 +-
.../pointer-collision-non-determinism.ll | 6 +-
llvm/test/Transforms/Reassociate/pr42349.ll | 2 +-
.../Reassociate/reassoc-intermediate-fnegs.ll | 6 +-
.../SCCP/float-denormal-simplification.ll | 2 +-
.../SCCP/float-nan-simplification.ll | 8 +-
llvm/test/Transforms/SCCP/loadtest.ll | 2 +-
...-fcmp-dynamic-denormal-mode-issue114947.ll | 12 +-
llvm/test/Transforms/SCCP/sitofp.ll | 2 +-
.../SLPVectorizer/AArch64/gather-load-128.ll | 8 +-
.../SLPVectorizer/AArch64/reduce-fadd.ll | 12 +-
...otriviallyvectorizableintrinsicoperands.ll | 36 +-
.../SLPVectorizer/AMDGPU/reduction.ll | 6 +-
.../SLPVectorizer/AMDGPU/slp-v2f16.ll | 38 +-
.../Transforms/SLPVectorizer/NVPTX/v2f16.ll | 12 +-
.../SLPVectorizer/RISCV/reductions.ll | 2 +-
.../Transforms/SLPVectorizer/RISCV/revec.ll | 2 +-
.../SLPVectorizer/X86/buildvector-shuffle.ll | 6 +-
.../Transforms/SLPVectorizer/X86/c-ray.ll | 12 +-
.../X86/cmp-values-non-full-registers.ll | 4 +-
.../SLPVectorizer/X86/crash_bullet3.ll | 4 +-
.../SLPVectorizer/X86/crash_smallpt.ll | 6 +-
.../X86/deleted-inst-reduction-attempt.ll | 2 +-
.../entry-no-bundle-but-extra-use-on-vec.ll | 2 +-
.../SLPVectorizer/X86/fabs-cost-softfp.ll | 2 +-
.../SLPVectorizer/X86/horizontal.ll | 14 +-
.../SLPVectorizer/X86/reduction2.ll | 8 +-
.../X86/split-node-full-match.ll | 2 +-
.../X86/stackrestore-dependence.ll | 2 +-
.../Transforms/SLPVectorizer/catchswitch.ll | 8 +-
llvm/test/Transforms/SROA/ppcf128-no-fold.ll | 4 +-
llvm/test/Transforms/SROA/select-load.ll | 8 +-
llvm/test/Transforms/SROA/vector-promotion.ll | 12 +-
llvm/test/Transforms/Scalarizer/min-bits.ll | 20 +-
.../SimplifyCFG/ARM/speculate-math.ll | 48 +-
.../RISCV/switch_to_lookup_table-rv32.ll | 4 +-
.../RISCV/switch_to_lookup_table-rv64.ll | 4 +-
.../SimplifyCFG/X86/switch_to_lookup_table.ll | 4 +-
.../X86/two-entry-phi-fold-unpredictable.ll | 8 +-
.../fold-branch-to-common-dest-phis.ll | 6 +-
.../SimplifyCFG/fold-branch-to-common-dest.ll | 4 +-
.../Transforms/SimplifyCFG/speculate-math.ll | 16 +-
.../SpeculativeExecution/spec-fp.ll | 2 +-
.../TypePromotion/AArch64/bitcast.ll | 2 +-
.../Util/libcalls-shrinkwrap-double.ll | 16 +-
.../Util/libcalls-shrinkwrap-float.ll | 16 +-
.../Util/libcalls-shrinkwrap-long-double.ll | 104 +--
.../AArch64/shuffletoidentity.ll | 4 +-
.../RISCV/vpintrin-scalarization.ll | 6 +-
.../X86/insert-binop-with-constant.ll | 24 +-
.../VectorCombine/X86/shuffle-of-fma-const.ll | 16 +-
llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll | 8 +-
.../tools/llvm-reduce/reduce-operands-fp.ll | 26 +-
.../LLVMIR/openmp-distribute-private.mlir | 4 +-
592 files changed, 6912 insertions(+), 6912 deletions(-)
diff --git a/clang/test/AST/ByteCode/codegen.cpp b/clang/test/AST/ByteCode/codegen.cpp
index cbb0504c89f13..c2d2a6ef22bdc 100644
--- a/clang/test/AST/ByteCode/codegen.cpp
+++ b/clang/test/AST/ByteCode/codegen.cpp
@@ -27,7 +27,7 @@ S s;
// CHECK: @sp = constant ptr getelementptr (i8, ptr @s, i64 16), align 8
float &sp = s.c[3];
-// CHECK: @PR9558 = global float 0.000000e+0
+// CHECK: @PR9558 = global float 0.000000e+00
float PR9558 = reinterpret_cast<const float&>("asd");
// CHECK: @i = constant ptr @PR9558
int &i = reinterpret_cast<int&>(PR9558);
diff --git a/clang/test/AST/ByteCode/const-fpfeatures.cpp b/clang/test/AST/ByteCode/const-fpfeatures.cpp
index 0764e3d8ba813..15f2af0bb4d0c 100644
--- a/clang/test/AST/ByteCode/const-fpfeatures.cpp
+++ b/clang/test/AST/ByteCode/const-fpfeatures.cpp
@@ -7,12 +7,12 @@
float F1u = 1.0F + 0x0.000002p0F;
float F2u = 1.0F + 0x0.000001p0F;
float F3u = 0x1.000001p0;
-// CHECK: @F1u = {{.*}} float 0x3FF0000020000000
-// CHECK: @F2u = {{.*}} float 0x3FF0000020000000
-// CHECK: @F3u = {{.*}} float 0x3FF0000020000000
+// CHECK: @F1u = {{.*}} float f0x3F800001
+// CHECK: @F2u = {{.*}} float f0x3F800001
+// CHECK: @F3u = {{.*}} float f0x3F800001
float FI1u = 0xFFFFFFFFU;
-// CHECK: @FI1u = {{.*}} float 0x41F0000000000000
+// CHECK: @FI1u = {{.*}} float f0x4F800000
#pragma STDC FENV_ROUND FE_DOWNWARD
@@ -20,13 +20,13 @@ float F1d = 1.0F + 0x0.000002p0F;
float F2d = 1.0F + 0x0.000001p0F;
float F3d = 0x1.000001p0;
-// CHECK: @F1d = {{.*}} float 0x3FF0000020000000
+// CHECK: @F1d = {{.*}} float f0x3F800001
// CHECK: @F2d = {{.*}} float 1.000000e+00
// CHECK: @F3d = {{.*}} float 1.000000e+00
float FI1d = 0xFFFFFFFFU;
-// CHECK: @FI1d = {{.*}} float 0x41EFFFFFE0000000
+// CHECK: @FI1d = {{.*}} float f0x4F7FFFFF
// nextUp(1.F) == 0x1.000002p0F
@@ -47,7 +47,7 @@ constexpr float add_round_up(float x, float y) {
float V1 = add_round_down(1.0F, 0x0.000001p0F);
float V2 = add_round_up(1.0F, 0x0.000001p0F);
// CHECK: @V1 = {{.*}} float 1.000000e+00
-// CHECK: @V2 = {{.*}} float 0x3FF0000020000000
+// CHECK: @V2 = {{.*}} float f0x3F800001
constexpr float add_cast_round_down(float x, double y) {
@@ -68,4 +68,4 @@ float V3 = add_cast_round_down(1.0F, 0x0.000001p0F);
float V4 = add_cast_round_up(1.0F, 0x0.000001p0F);
// CHECK: @V3 = {{.*}} float 1.000000e+00
-// CHECK: @V4 = {{.*}} float 0x3FF0000020000000
+// CHECK: @V4 = {{.*}} float f0x3F800001
diff --git a/clang/test/AST/const-fpfeatures.c b/clang/test/AST/const-fpfeatures.c
index 787bb989dd4a2..15dc607afe231 100644
--- a/clang/test/AST/const-fpfeatures.c
+++ b/clang/test/AST/const-fpfeatures.c
@@ -9,25 +9,25 @@ const double _Complex C0 = 0x1.000001p0 + 0x1.000001p0I;
float F1u = 1.0F + 0x0.000002p0F;
float F2u = 1.0F + 0x0.000001p0F;
float F3u = 0x1.000001p0;
-// CHECK: @F1u = {{.*}} float 0x3FF0000020000000
-// CHECK: @F2u = {{.*}} float 0x3FF0000020000000
-// CHECK: @F3u = {{.*}} float 0x3FF0000020000000
+// CHECK: @F1u = {{.*}} float f0x3F800001
+// CHECK: @F2u = {{.*}} float f0x3F800001
+// CHECK: @F3u = {{.*}} float f0x3F800001
float FI1u = 0xFFFFFFFFU;
-// CHECK: @FI1u = {{.*}} float 0x41F0000000000000
+// CHECK: @FI1u = {{.*}} float f0x4F800000
float _Complex C1u = C0;
-// CHECK: @C1u = {{.*}} { float, float } { float 0x3FF0000020000000, float 0x3FF0000020000000 }
+// CHECK: @C1u = {{.*}} { float, float } { float f0x3F800001, float f0x3F800001 }
float FLu = 0.1F;
-// CHECK: @FLu = {{.*}} float 0x3FB99999A0000000
+// CHECK: @FLu = {{.*}} float 1.000000e-01
typedef float vector2float __attribute__((__vector_size__(8)));
typedef double vector2double __attribute__((__vector_size__(16)));
const vector2float V2Fu = {1.0F + 0x0.000001p0F, 1.0F + 0x0.000002p0F};
vector2double V2Du = __builtin_convertvector(V2Fu, vector2double);
-// CHECK: @V2Fu = {{.*}} <2 x float> splat (float 0x3FF0000020000000)
-// CHECK: @V2Du = {{.*}} <2 x double> splat (double 0x3FF0000020000000)
+// CHECK: @V2Fu = {{.*}} <2 x float> splat (float f0x3F800001)
+// CHECK: @V2Du = {{.*}} <2 x double> splat (double f0x3FF0000020000000)
#pragma STDC FENV_ROUND FE_DOWNWARD
@@ -35,20 +35,20 @@ float F1d = 1.0F + 0x0.000002p0F;
float F2d = 1.0F + 0x0.000001p0F;
float F3d = 0x1.000001p0;
-// CHECK: @F1d = {{.*}} float 0x3FF0000020000000
+// CHECK: @F1d = {{.*}} float f0x3F800001
// CHECK: @F2d = {{.*}} float 1.000000e+00
// CHECK: @F3d = {{.*}} float 1.000000e+00
float FI1d = 0xFFFFFFFFU;
-// CHECK: @FI1d = {{.*}} float 0x41EFFFFFE0000000
+// CHECK: @FI1d = {{.*}} float f0x4F7FFFFF
float _Complex C1d = C0;
// CHECK: @C1d = {{.*}} { float, float } { float 1.000000e+00, float 1.000000e+00 }
float FLd = 0.1F;
-// CHECK: @FLd = {{.*}} float 0x3FB9999980000000
+// CHECK: @FLd = {{.*}} float f0x3DCCCCCC
const vector2float V2Fd = {1.0F + 0x0.000001p0F, 1.0F + 0x0.000002p0F};
vector2double V2Dd = __builtin_convertvector(V2Fd, vector2double);
-// CHECK: @V2Fd = {{.*}} <2 x float> <float 1.000000e+00, float 0x3FF0000020000000>
-// CHECK: @V2Dd = {{.*}} <2 x double> <double 1.000000e+00, double 0x3FF0000020000000>
+// CHECK: @V2Fd = {{.*}} <2 x float> <float 1.000000e+00, float f0x3F800001>
+// CHECK: @V2Dd = {{.*}} <2 x double> <double 1.000000e+00, double f0x3FF0000020000000>
diff --git a/clang/test/AST/const-fpfeatures.cpp b/clang/test/AST/const-fpfeatures.cpp
index 5e903c8c0e874..f5fdd3569a92c 100644
--- a/clang/test/AST/const-fpfeatures.cpp
+++ b/clang/test/AST/const-fpfeatures.cpp
@@ -19,7 +19,7 @@ constexpr float add_round_up(float x, float y) {
float V1 = add_round_down(1.0F, 0x0.000001p0F);
float V2 = add_round_up(1.0F, 0x0.000001p0F);
// CHECK: @V1 = {{.*}} float 1.000000e+00
-// CHECK: @V2 = {{.*}} float 0x3FF0000020000000
+// CHECK: @V2 = {{.*}} float f0x3F800001
constexpr float add_cast_round_down(float x, double y) {
#pragma STDC FENV_ROUND FE_DOWNWARD
@@ -39,7 +39,7 @@ float V3 = add_cast_round_down(1.0F, 0x0.000001p0F);
float V4 = add_cast_round_up(1.0F, 0x0.000001p0F);
// CHECK: @V3 = {{.*}} float 1.000000e+00
-// CHECK: @V4 = {{.*}} float 0x3FF0000020000000
+// CHECK: @V4 = {{.*}} float f0x3F800001
// The next three variables use the same function as initializer, only rounding
// modes differ.
@@ -54,7 +54,7 @@ float V5 = []() -> float {
}(1.0F, 0x0.000001p0F),
0x0.000001p0F);
}();
-// CHECK: @V5 = {{.*}} float 0x3FF0000040000000
+// CHECK: @V5 = {{.*}} float f0x3F800002
float V6 = []() -> float {
return [](float x, float y)->float {
@@ -66,7 +66,7 @@ float V6 = []() -> float {
}(1.0F, 0x0.000001p0F),
0x0.000001p0F);
}();
-// CHECK: @V6 = {{.*}} float 0x3FF0000020000000
+// CHECK: @V6 = {{.*}} float f0x3F800001
float V7 = []() -> float {
return [](float x, float y)->float {
@@ -89,11 +89,11 @@ template<float V> struct L {
#pragma STDC FENV_ROUND FE_DOWNWARD
L<0.1F> val_d;
-// CHECK: @val_d = {{.*}} { float 0x3FB9999980000000 }
+// CHECK: @val_d = {{.*}} { float f0x3DCCCCCC }
#pragma STDC FENV_ROUND FE_UPWARD
L<0.1F> val_u;
-// CHECK: @val_u = {{.*}} { float 0x3FB99999A0000000 }
+// CHECK: @val_u = {{.*}} { float 1.000000e-01 }
// Check literals in macros.
@@ -103,11 +103,11 @@ L<0.1F> val_u;
#pragma STDC FENV_ROUND FE_UPWARD
float C1_ru = CONSTANT_0_1;
-// CHECK: @C1_ru = {{.*}} float 0x3FB99999A0000000
+// CHECK: @C1_ru = {{.*}} float 1.000000e-01
#pragma STDC FENV_ROUND FE_DOWNWARD
float C1_rd = CONSTANT_0_1;
-// CHECK: @C1_rd = {{.*}} float 0x3FB9999980000000
+// CHECK: @C1_rd = {{.*}} float f0x3DCCCCCC
#pragma STDC FENV_ROUND FE_DOWNWARD
#define PRAGMA(x) _Pragma(#x)
@@ -116,14 +116,14 @@ float C1_rd = CONSTANT_0_1;
#pragma STDC FENV_ROUND FE_UPWARD
float C2_rd = CONSTANT_0_1_RM(0.1F, FE_DOWNWARD);
float C2_ru = CONSTANT_0_1_RM(0.1F, FE_UPWARD);
-// CHECK: @C2_rd = {{.*}} float 0x3FB9999980000000
-// CHECK: @C2_ru = {{.*}} float 0x3FB99999A0000000
+// CHECK: @C2_rd = {{.*}} float f0x3DCCCCCC
+// CHECK: @C2_ru = {{.*}} float 1.000000e-01
#pragma STDC FENV_ROUND FE_DOWNWARD
float C3_rd = CONSTANT_0_1_RM(0.1F, FE_DOWNWARD);
float C3_ru = CONSTANT_0_1_RM(0.1F, FE_UPWARD);
-// CHECK: @C3_rd = {{.*}} float 0x3FB9999980000000
-// CHECK: @C3_ru = {{.*}} float 0x3FB99999A0000000
+// CHECK: @C3_rd = {{.*}} float f0x3DCCCCCC
+// CHECK: @C3_ru = {{.*}} float 1.000000e-01
// Check literals in template instantiations.
@@ -136,11 +136,11 @@ constexpr T foo() {
#pragma STDC FENV_ROUND FE_DOWNWARD
float var_d = foo<float, 0.1F>();
-// CHECK: @var_d = {{.*}} float 0x3FB9999980000000
+// CHECK: @var_d = {{.*}} float f0x3DCCCCCC
#pragma STDC FENV_ROUND FE_UPWARD
float var_u = foo<float, 0.1F>();
-// CHECK: @var_u = {{.*}} float 0x3FB99999A0000000
+// CHECK: @var_u = {{.*}} float 1.000000e-01
#pragma STDC FENV_ROUND FE_DYNAMIC
@@ -159,10 +159,10 @@ void func_02() {
}
// CHECK-LABEL: define {{.*}} void @_Z4foo2IfTnT_Lf3dccccccEEvv()
-// CHECK: store float 0x3FB9999980000000, ptr
+// CHECK: store float f0x3DCCCCCC, ptr
// CHECK-LABEL: define {{.*}} void @_Z4foo2IfTnT_Lf3dcccccdEEvv()
-// CHECK: store float 0x3FB99999A0000000, ptr
+// CHECK: store float 1.000000e-01, ptr
#pragma STDC FENV_ROUND FE_DOWNWARD
@@ -172,15 +172,15 @@ float tfunc_01() {
}
template float tfunc_01<0>();
// CHECK-LABEL: define {{.*}} float @_Z8tfunc_01ILi0EEfv()
-// CHECK: ret float 0x3FB9999980000000
+// CHECK: ret float f0x3DCCCCCC
#pragma STDC FENV_ROUND FE_UPWARD
template float tfunc_01<1>();
// CHECK-LABEL: define {{.*}} float @_Z8tfunc_01ILi1EEfv()
-// CHECK: ret float 0x3FB9999980000000
+// CHECK: ret float f0x3DCCCCCC
template<> float tfunc_01<2>() {
return 0.1F;
}
// CHECK-LABEL: define {{.*}} float @_Z8tfunc_01ILi2EEfv()
-// CHECK: ret float 0x3FB99999A0000000
+// CHECK: ret float 1.000000e-01
diff --git a/clang/test/C/C11/n1396.c b/clang/test/C/C11/n1396.c
index 6f76cfe959496..7ccaaf02463d9 100644
--- a/clang/test/C/C11/n1396.c
+++ b/clang/test/C/C11/n1396.c
@@ -31,7 +31,7 @@
// CHECK-X64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-X64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-X64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to x86_fp80
-// CHECK-X64-NEXT: [[MUL:%.*]] = fmul x86_fp80 [[CONV]], 0xK3FFF8000000000000000
+// CHECK-X64-NEXT: [[MUL:%.*]] = fmul x86_fp80 [[CONV]], 1.000000e+00
// CHECK-X64-NEXT: [[CONV1:%.*]] = fptrunc x86_fp80 [[MUL]] to float
// CHECK-X64-NEXT: ret float [[CONV1]]
//
@@ -42,7 +42,7 @@
// CHECK-AARCH64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-AARCH64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-AARCH64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to fp128
-// CHECK-AARCH64-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 0xL00000000000000003FFF000000000000
+// CHECK-AARCH64-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 1.000000e+00
// CHECK-AARCH64-NEXT: [[CONV1:%.*]] = fptrunc fp128 [[MUL]] to float
// CHECK-AARCH64-NEXT: ret float [[CONV1]]
//
@@ -64,7 +64,7 @@
// CHECK-PPC32-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-PPC32-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-PPC32-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to ppc_fp128
-// CHECK-PPC32-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 0xM3FF00000000000000000000000000000
+// CHECK-PPC32-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 1.000000e+00
// CHECK-PPC32-NEXT: [[CONV1:%.*]] = fptrunc ppc_fp128 [[MUL]] to float
// CHECK-PPC32-NEXT: ret float [[CONV1]]
//
@@ -75,7 +75,7 @@
// CHECK-PPC64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-PPC64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-PPC64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to ppc_fp128
-// CHECK-PPC64-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 0xM3FF00000000000000000000000000000
+// CHECK-PPC64-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 1.000000e+00
// CHECK-PPC64-NEXT: [[CONV1:%.*]] = fptrunc ppc_fp128 [[MUL]] to float
// CHECK-PPC64-NEXT: ret float [[CONV1]]
//
@@ -86,7 +86,7 @@
// CHECK-SPARCV9-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-SPARCV9-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-SPARCV9-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to fp128
-// CHECK-SPARCV9-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 0xL00000000000000003FFF000000000000
+// CHECK-SPARCV9-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 1.000000e+00
// CHECK-SPARCV9-NEXT: [[CONV1:%.*]] = fptrunc fp128 [[MUL]] to float
// CHECK-SPARCV9-NEXT: ret float [[CONV1]]
//
@@ -102,7 +102,7 @@ float extended_float_func(float x) {
// CHECK-X64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-X64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-X64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to x86_fp80
-// CHECK-X64-NEXT: [[MUL:%.*]] = fmul x86_fp80 [[CONV]], 0xK3FFF8000000000000000
+// CHECK-X64-NEXT: [[MUL:%.*]] = fmul x86_fp80 [[CONV]], 1.000000e+00
// CHECK-X64-NEXT: [[CONV1:%.*]] = fptrunc x86_fp80 [[MUL]] to float
// CHECK-X64-NEXT: ret float [[CONV1]]
//
@@ -113,7 +113,7 @@ float extended_float_func(float x) {
// CHECK-AARCH64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-AARCH64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-AARCH64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to fp128
-// CHECK-AARCH64-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 0xL00000000000000003FFF000000000000
+// CHECK-AARCH64-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 1.000000e+00
// CHECK-AARCH64-NEXT: [[CONV1:%.*]] = fptrunc fp128 [[MUL]] to float
// CHECK-AARCH64-NEXT: ret float [[CONV1]]
//
@@ -135,7 +135,7 @@ float extended_float_func(float x) {
// CHECK-PPC32-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-PPC32-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-PPC32-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to ppc_fp128
-// CHECK-PPC32-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 0xM3FF00000000000000000000000000000
+// CHECK-PPC32-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 1.000000e+00
// CHECK-PPC32-NEXT: [[CONV1:%.*]] = fptrunc ppc_fp128 [[MUL]] to float
// CHECK-PPC32-NEXT: ret float [[CONV1]]
//
@@ -146,7 +146,7 @@ float extended_float_func(float x) {
// CHECK-PPC64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-PPC64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-PPC64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to ppc_fp128
-// CHECK-PPC64-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 0xM3FF00000000000000000000000000000
+// CHECK-PPC64-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 1.000000e+00
// CHECK-PPC64-NEXT: [[CONV1:%.*]] = fptrunc ppc_fp128 [[MUL]] to float
// CHECK-PPC64-NEXT: ret float [[CONV1]]
//
@@ -157,7 +157,7 @@ float extended_float_func(float x) {
// CHECK-SPARCV9-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-SPARCV9-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-SPARCV9-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to fp128
-// CHECK-SPARCV9-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 0xL00000000000000003FFF000000000000
+// CHECK-SPARCV9-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 1.000000e+00
// CHECK-SPARCV9-NEXT: [[CONV1:%.*]] = fptrunc fp128 [[MUL]] to float
// CHECK-SPARCV9-NEXT: ret float [[CONV1]]
//
@@ -173,7 +173,7 @@ float extended_float_func_cast(float x) {
// CHECK-X64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-X64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-X64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to x86_fp80
-// CHECK-X64-NEXT: [[MUL:%.*]] = fmul x86_fp80 [[CONV]], 0xK3FFF8000000000000000
+// CHECK-X64-NEXT: [[MUL:%.*]] = fmul x86_fp80 [[CONV]], 1.000000e+00
// CHECK-X64-NEXT: [[CONV1:%.*]] = fptrunc x86_fp80 [[MUL]] to float
// CHECK-X64-NEXT: ret float [[CONV1]]
//
@@ -184,7 +184,7 @@ float extended_float_func_cast(float x) {
// CHECK-AARCH64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-AARCH64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-AARCH64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to fp128
-// CHECK-AARCH64-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 0xL00000000000000003FFF000000000000
+// CHECK-AARCH64-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 1.000000e+00
// CHECK-AARCH64-NEXT: [[CONV1:%.*]] = fptrunc fp128 [[MUL]] to float
// CHECK-AARCH64-NEXT: ret float [[CONV1]]
//
@@ -206,7 +206,7 @@ float extended_float_func_cast(float x) {
// CHECK-PPC32-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-PPC32-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-PPC32-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to ppc_fp128
-// CHECK-PPC32-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 0xM3FF00000000000000000000000000000
+// CHECK-PPC32-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 1.000000e+00
// CHECK-PPC32-NEXT: [[CONV1:%.*]] = fptrunc ppc_fp128 [[MUL]] to float
// CHECK-PPC32-NEXT: ret float [[CONV1]]
//
@@ -217,7 +217,7 @@ float extended_float_func_cast(float x) {
// CHECK-PPC64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-PPC64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-PPC64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to ppc_fp128
-// CHECK-PPC64-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 0xM3FF00000000000000000000000000000
+// CHECK-PPC64-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 1.000000e+00
// CHECK-PPC64-NEXT: [[CONV1:%.*]] = fptrunc ppc_fp128 [[MUL]] to float
// CHECK-PPC64-NEXT: ret float [[CONV1]]
//
@@ -228,7 +228,7 @@ float extended_float_func_cast(float x) {
// CHECK-SPARCV9-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-SPARCV9-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-SPARCV9-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to fp128
-// CHECK-SPARCV9-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 0xL00000000000000003FFF000000000000
+// CHECK-SPARCV9-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 1.000000e+00
// CHECK-SPARCV9-NEXT: [[CONV1:%.*]] = fptrunc fp128 [[MUL]] to float
// CHECK-SPARCV9-NEXT: ret float [[CONV1]]
//
@@ -244,7 +244,7 @@ float extended_double_func(float x) {
// CHECK-X64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-X64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-X64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to x86_fp80
-// CHECK-X64-NEXT: [[MUL:%.*]] = fmul x86_fp80 [[CONV]], 0xK3FFF8000000000000000
+// CHECK-X64-NEXT: [[MUL:%.*]] = fmul x86_fp80 [[CONV]], 1.000000e+00
// CHECK-X64-NEXT: [[CONV1:%.*]] = fptrunc x86_fp80 [[MUL]] to float
// CHECK-X64-NEXT: ret float [[CONV1]]
//
@@ -255,7 +255,7 @@ float extended_double_func(float x) {
// CHECK-AARCH64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-AARCH64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-AARCH64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to fp128
-// CHECK-AARCH64-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 0xL00000000000000003FFF000000000000
+// CHECK-AARCH64-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 1.000000e+00
// CHECK-AARCH64-NEXT: [[CONV1:%.*]] = fptrunc fp128 [[MUL]] to float
// CHECK-AARCH64-NEXT: ret float [[CONV1]]
//
@@ -277,7 +277,7 @@ float extended_double_func(float x) {
// CHECK-PPC32-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-PPC32-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-PPC32-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to ppc_fp128
-// CHECK-PPC32-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 0xM3FF00000000000000000000000000000
+// CHECK-PPC32-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 1.000000e+00
// CHECK-PPC32-NEXT: [[CONV1:%.*]] = fptrunc ppc_fp128 [[MUL]] to float
// CHECK-PPC32-NEXT: ret float [[CONV1]]
//
@@ -288,7 +288,7 @@ float extended_double_func(float x) {
// CHECK-PPC64-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-PPC64-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-PPC64-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to ppc_fp128
-// CHECK-PPC64-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 0xM3FF00000000000000000000000000000
+// CHECK-PPC64-NEXT: [[MUL:%.*]] = fmul ppc_fp128 [[CONV]], 1.000000e+00
// CHECK-PPC64-NEXT: [[CONV1:%.*]] = fptrunc ppc_fp128 [[MUL]] to float
// CHECK-PPC64-NEXT: ret float [[CONV1]]
//
@@ -299,7 +299,7 @@ float extended_double_func(float x) {
// CHECK-SPARCV9-NEXT: store float [[X]], ptr [[X_ADDR]], align 4
// CHECK-SPARCV9-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR]], align 4
// CHECK-SPARCV9-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to fp128
-// CHECK-SPARCV9-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 0xL00000000000000003FFF000000000000
+// CHECK-SPARCV9-NEXT: [[MUL:%.*]] = fmul fp128 [[CONV]], 1.000000e+00
// CHECK-SPARCV9-NEXT: [[CONV1:%.*]] = fptrunc fp128 [[MUL]] to float
// CHECK-SPARCV9-NEXT: ret float [[CONV1]]
//
diff --git a/clang/test/C/C2y/n3460_1.c b/clang/test/C/C2y/n3460_1.c
index 2d50b3c23dae8..287a7bec85aa4 100644
--- a/clang/test/C/C2y/n3460_1.c
+++ b/clang/test/C/C2y/n3460_1.c
@@ -16,7 +16,7 @@
// CHECK-NEXT: [[A_REALP:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[A]], i32 0, i32 0
// CHECK-NEXT: [[A_IMAGP:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[A]], i32 0, i32 1
// CHECK-NEXT: store double 0.000000e+00, ptr [[A_REALP]], align 8
-// CHECK-NEXT: store double 0x7FF0000000000000, ptr [[A_IMAGP]], align 8
+// CHECK-NEXT: store double +inf, ptr [[A_IMAGP]], align 8
// CHECK-NEXT: [[B_REALP:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[B]], i32 0, i32 0
// CHECK-NEXT: [[B_IMAGP:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[B]], i32 0, i32 1
// CHECK-NEXT: store double -0.000000e+00, ptr [[B_REALP]], align 8
@@ -24,7 +24,7 @@
// CHECK-NEXT: [[C_REALP:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[C]], i32 0, i32 0
// CHECK-NEXT: [[C_IMAGP:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[C]], i32 0, i32 1
// CHECK-NEXT: store double 0.000000e+00, ptr [[C_REALP]], align 8
-// CHECK-NEXT: store double 0x7FF0000000000000, ptr [[C_IMAGP]], align 8
+// CHECK-NEXT: store double +inf, ptr [[C_IMAGP]], align 8
// CHECK-NEXT: [[D_REALP:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[D]], i32 0, i32 0
// CHECK-NEXT: [[D_IMAGP:%.*]] = getelementptr inbounds nuw { double, double }, ptr [[D]], i32 0, i32 1
// CHECK-NEXT: store double 4.000000e+00, ptr [[D_REALP]], align 8
diff --git a/clang/test/CIR/CodeGen/atomic.c b/clang/test/CIR/CodeGen/atomic.c
index abce1166cf9a2..f738244b607df 100644
--- a/clang/test/CIR/CodeGen/atomic.c
+++ b/clang/test/CIR/CodeGen/atomic.c
@@ -67,10 +67,10 @@ void f4(_Atomic(float) *p) {
// CIR: cir.store align(4) atomic(seq_cst) %{{.+}}, %{{.+}} : !cir.float, !cir.ptr<!cir.float>
// LLVM-LABEL: @f4
-// LLVM: store atomic float 0x40091EB860000000, ptr %{{.+}} seq_cst, align 4
+// LLVM: store atomic float 3.140000e+00, ptr %{{.+}} seq_cst, align 4
// OGCG-LABEL: @f4
-// OGCG: store atomic float 0x40091EB860000000, ptr %{{.+}} seq_cst, align 4
+// OGCG: store atomic float 3.140000e+00, ptr %{{.+}} seq_cst, align 4
void atomic_to_non_atomic(_Atomic int *ptr, _Atomic volatile int *vptr) {
// CIR-LABEL: @atomic_to_non_atomic
diff --git a/clang/test/CIR/CodeGen/binassign.c b/clang/test/CIR/CodeGen/binassign.c
index 9248ecf15e231..dda52a8e4f319 100644
--- a/clang/test/CIR/CodeGen/binassign.c
+++ b/clang/test/CIR/CodeGen/binassign.c
@@ -39,7 +39,7 @@ void binary_assign(void) {
// LLVM: %[[I_PTR:.*]] = alloca i32
// LLVM: store i8 1, ptr %[[B_PTR]]
// LLVM: store i8 65, ptr %[[C_PTR]]
-// LLVM: store float 0x40091EB860000000, ptr %[[F_PTR]]
+// LLVM: store float 3.140000e+00, ptr %[[F_PTR]]
// LLVM: store i32 42, ptr %[[I_PTR]]
// LLVM: ret void
@@ -50,7 +50,7 @@ void binary_assign(void) {
// OGCG: %[[I_PTR:.*]] = alloca i32
// OGCG: store i8 1, ptr %[[B_PTR]]
// OGCG: store i8 65, ptr %[[C_PTR]]
-// OGCG: store float 0x40091EB860000000, ptr %[[F_PTR]]
+// OGCG: store float 3.140000e+00, ptr %[[F_PTR]]
// OGCG: store i32 42, ptr %[[I_PTR]]
// OGCG: ret void
diff --git a/clang/test/CIR/CodeGen/comma.c b/clang/test/CIR/CodeGen/comma.c
index 764f724f9cf90..b09a479076a54 100644
--- a/clang/test/CIR/CodeGen/comma.c
+++ b/clang/test/CIR/CodeGen/comma.c
@@ -40,7 +40,7 @@ void comma(void) {
// LLVM: %[[I_PTR:.*]] = alloca i32
// LLVM: store i8 1, ptr %[[B_PTR]]
// LLVM: store i8 65, ptr %[[C_PTR]]
-// LLVM: store float 0x40091EB860000000, ptr %[[F_PTR]]
+// LLVM: store float 3.140000e+00, ptr %[[F_PTR]]
// LLVM: store i32 42, ptr %[[I_PTR]]
// LLVM: store i32 100, ptr %[[I_PTR]]
// LLVM: ret void
@@ -52,7 +52,7 @@ void comma(void) {
// OGCG: %[[I_PTR:.*]] = alloca i32
// OGCG: store i8 1, ptr %[[B_PTR]]
// OGCG: store i8 65, ptr %[[C_PTR]]
-// OGCG: store float 0x40091EB860000000, ptr %[[F_PTR]]
+// OGCG: store float 3.140000e+00, ptr %[[F_PTR]]
// OGCG: store i32 42, ptr %[[I_PTR]]
// OGCG: store i32 100, ptr %[[I_PTR]]
// OGCG: ret void
diff --git a/clang/test/CIR/CodeGen/complex.cpp b/clang/test/CIR/CodeGen/complex.cpp
index 1bbc8558cb540..472ad7aa4a3b1 100644
--- a/clang/test/CIR/CodeGen/complex.cpp
+++ b/clang/test/CIR/CodeGen/complex.cpp
@@ -1195,11 +1195,11 @@ void imag_on_scalar_with_type_promotion() {
// LLVM: %[[A_ADDR:.*]] = alloca half, i64 1, align 2
// LLVM: %[[B_ADDR:.*]] = alloca half, i64 1, align 2
-// LLVM: store half 0xH0000, ptr %[[B_ADDR]], align 2
+// LLVM: store half 0.000000e+00, ptr %[[B_ADDR]], align 2
// OGCG: %[[A_ADDR:.*]] = alloca half, align 2
// OGCG: %[[B_ADDR:.*]] = alloca half, align 2
-// OGCG: store half 0xH0000, ptr %[[B_ADDR]], align 2
+// OGCG: store half 0.000000e+00, ptr %[[B_ADDR]], align 2
void imag_on_const_scalar() {
float a;
@@ -1439,7 +1439,7 @@ void calling_function_with_default_arg() {
// TODO(CIR): the difference between the CIR LLVM and OGCG is because the lack of calling convention lowering,
// LLVM: %[[DEFAULT_ARG_ADDR:.*]] = alloca { float, float }, i64 1, align 4
-// LLVM: store { float, float } { float 1.000000e+00, float 0x40019999A0000000 }, ptr %[[DEFAULT_ARG_ADDR]], align 4
+// LLVM: store { float, float } { float 1.000000e+00, float 2.200000e+00 }, ptr %[[DEFAULT_ARG_ADDR]], align 4
// LLVM: %[[TMP_DEFAULT_ARG:.*]] = load { float, float }, ptr %[[DEFAULT_ARG_ADDR]], align 4
// LLVM: call void @_Z33function_with_complex_default_argCf({ float, float } {{.*}} %[[TMP_DEFAULT_ARG]])
@@ -1447,7 +1447,7 @@ void calling_function_with_default_arg() {
// OGCG: %[[DEFAULT_ARG_REAL_PTR:.*]] = getelementptr inbounds nuw { float, float }, ptr %[[DEFAULT_ARG_ADDR]], i32 0, i32 0
// OGCG: %[[DEFAULT_ARG_IMAG_PTR:.*]] = getelementptr inbounds nuw { float, float }, ptr %[[DEFAULT_ARG_ADDR]], i32 0, i32 1
// OGCG: store float 1.000000e+00, ptr %[[DEFAULT_ARG_REAL_PTR]], align 4
-// OGCG: store float 0x40019999A0000000, ptr %[[DEFAULT_ARG_IMAG_PTR]], align 4
+// OGCG: store float 2.200000e+00, ptr %[[DEFAULT_ARG_IMAG_PTR]], align 4
// OGCG: %[[TMP_DEFAULT_ARG:.*]] = load <2 x float>, ptr %[[DEFAULT_ARG_ADDR]], align 4
// OGCG: call void @_Z33function_with_complex_default_argCf(<2 x float> {{.*}} %[[TMP_DEFAULT_ARG]])
diff --git a/clang/test/CIR/CodeGen/throws.cpp b/clang/test/CIR/CodeGen/throws.cpp
index 0c11bffc2dd2e..8b415f386c00e 100644
--- a/clang/test/CIR/CodeGen/throws.cpp
+++ b/clang/test/CIR/CodeGen/throws.cpp
@@ -133,14 +133,14 @@ void throw_complex_expr() {
// CIR: cir.unreachable
// LLVM: %[[EXCEPTION_ADDR:.*]] = call ptr @__cxa_allocate_exception(i64 8)
-// LLVM: store { float, float } { float 0x3FF19999A0000000, float 0x40019999A0000000 }, ptr %[[EXCEPTION_ADDR]], align 16
+// LLVM: store { float, float } { float 1.100000e+00, float 2.200000e+00 }, ptr %[[EXCEPTION_ADDR]], align 16
// LLVM: call void @__cxa_throw(ptr %[[EXCEPTION_ADDR]], ptr @_ZTICf, ptr null)
// OGCG: %[[EXCEPTION_ADDR:.*]] = call ptr @__cxa_allocate_exception(i64 8)
// OGCG: %[[EXCEPTION_REAL:.*]] = getelementptr inbounds nuw { float, float }, ptr %[[EXCEPTION_ADDR]], i32 0, i32 0
// OGCG: %[[EXCEPTION_IMAG:.*]] = getelementptr inbounds nuw { float, float }, ptr %[[EXCEPTION_ADDR]], i32 0, i32 1
-// OGCG: store float 0x3FF19999A0000000, ptr %[[EXCEPTION_REAL]], align 16
-// OGCG: store float 0x40019999A0000000, ptr %[[EXCEPTION_IMAG]], align 4
+// OGCG: store float 1.100000e+00, ptr %[[EXCEPTION_REAL]], align 16
+// OGCG: store float 2.200000e+00, ptr %[[EXCEPTION_IMAG]], align 4
// OGCG: call void @__cxa_throw(ptr %[[EXCEPTION_ADDR]], ptr @_ZTICf, ptr null)
void throw_vector_type() {
diff --git a/clang/test/CIR/CodeGen/union.c b/clang/test/CIR/CodeGen/union.c
index 9acc802d218f4..5403982654067 100644
--- a/clang/test/CIR/CodeGen/union.c
+++ b/clang/test/CIR/CodeGen/union.c
@@ -144,7 +144,7 @@ void shouldGenerateUnionAccess(union U2 u) {
// LLVM-NEXT: %[[B_VAL:.*]] = load i8, ptr %[[U]], align 8
// LLVM-NEXT: store i32 1, ptr %[[U]], align 8
// LLVM-NEXT: %[[I_VAL:.*]] = load i32, ptr %[[U]], align 8
-// LLVM-NEXT: store float 0x3FB99999A0000000, ptr %[[U]], align 8
+// LLVM-NEXT: store float 1.000000e-01, ptr %[[U]], align 8
// LLVM-NEXT: %[[F_VAL:.*]] = load float, ptr %[[U]], align 8
// LLVM-NEXT: store double 1.000000e-01, ptr %[[U]], align 8
// LLVM-NEXT: %[[D_VAL:.*]] = load double, ptr %[[U]], align 8
@@ -159,7 +159,7 @@ void shouldGenerateUnionAccess(union U2 u) {
// OGCG-NEXT: %[[B_VAL:.*]] = load i8, ptr %[[U]], align 8
// OGCG-NEXT: store i32 1, ptr %[[U]], align 8
// OGCG-NEXT: %[[I_VAL:.*]] = load i32, ptr %[[U]], align 8
-// OGCG-NEXT: store float 0x3FB99999A0000000, ptr %[[U]], align 8
+// OGCG-NEXT: store float 1.000000e-01, ptr %[[U]], align 8
// OGCG-NEXT: %[[F_VAL:.*]] = load float, ptr %[[U]], align 8
// OGCG-NEXT: store double 1.000000e-01, ptr %[[U]], align 8
// OGCG-NEXT: %[[D_VAL:.*]] = load double, ptr %[[U]], align 8
diff --git a/clang/test/CIR/CodeGen/union.cpp b/clang/test/CIR/CodeGen/union.cpp
index e931587c16d98..4be82a39693b8 100644
--- a/clang/test/CIR/CodeGen/union.cpp
+++ b/clang/test/CIR/CodeGen/union.cpp
@@ -46,7 +46,7 @@ void shouldGenerateUnionAccess(union U u) {
// LLVM: store %union.U %{{.*}}, ptr %[[BASE]]
// LLVM: store i8 1, ptr %[[BASE]]
// LLVM: store i32 1, ptr %[[BASE]]
-// LLVM: store float 0x3FB99999A0000000, ptr %[[BASE]]
+// LLVM: store float 1.000000e-01, ptr %[[BASE]]
// LLVM: store double 1.000000e-01, ptr %[[BASE]]
// OGCG: define {{.*}}shouldGenerateUnionAccess
@@ -55,5 +55,5 @@ void shouldGenerateUnionAccess(union U u) {
// OGCG: store i64 %{{.*}}, ptr %[[DIVE]]
// OGCG: store i8 1, ptr %[[BASE]]
// OGCG: store i32 1, ptr %[[BASE]]
-// OGCG: store float 0x3FB99999A0000000, ptr %[[BASE]]
+// OGCG: store float 1.000000e-01, ptr %[[BASE]]
// OGCG: store double 1.000000e-01, ptr %[[BASE]]
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
index f040f4f1b41a7..8e696154c57f7 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
@@ -73,10 +73,10 @@ _Float16 test_mm512_reduce_add_ph(__m512h __W) {
// CIR: cir.call @_mm512_reduce_add_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<32 x !cir.f16>{{.*}}) -> !cir.f16
// LLVM-LABEL: test_mm512_reduce_add_ph
- // LLVM: call half @llvm.vector.reduce.fadd.v32f16(half 0xH8000, <32 x half> %{{.*}})
+ // LLVM: call half @llvm.vector.reduce.fadd.v32f16(half -0.000000e+00, <32 x half> %{{.*}})
// OGCG-LABEL: test_mm512_reduce_add_ph
- // OGCG: call reassoc {{.*}}half @llvm.vector.reduce.fadd.v32f16(half 0xH8000, <32 x half> %{{.*}})
+ // OGCG: call reassoc {{.*}}half @llvm.vector.reduce.fadd.v32f16(half -0.000000e+00, <32 x half> %{{.*}})
return _mm512_reduce_add_ph(__W);
}
@@ -88,10 +88,10 @@ _Float16 test_mm512_reduce_mul_ph(__m512h __W) {
// CIR: cir.call @_mm512_reduce_mul_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<32 x !cir.f16>{{.*}}) -> !cir.f16
// LLVM-LABEL: test_mm512_reduce_mul_ph
- // LLVM: call half @llvm.vector.reduce.fmul.v32f16(half 0xH3C00, <32 x half> %{{.*}})
+ // LLVM: call half @llvm.vector.reduce.fmul.v32f16(half 1.000000e+00, <32 x half> %{{.*}})
// OGCG-LABEL: test_mm512_reduce_mul_ph
- // OGCG: call reassoc {{.*}}half @llvm.vector.reduce.fmul.v32f16(half 0xH3C00, <32 x half> %{{.*}})
+ // OGCG: call reassoc {{.*}}half @llvm.vector.reduce.fmul.v32f16(half 1.000000e+00, <32 x half> %{{.*}})
return _mm512_reduce_mul_ph(__W);
}
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vlfp16-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512vlfp16-builtins.c
index 0cfe9447972f5..5ca315bc8317c 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vlfp16-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vlfp16-builtins.c
@@ -15,10 +15,10 @@ _Float16 test_mm256_reduce_add_ph(__m256h __W) {
// CIR: cir.call @_mm256_reduce_add_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.f16>{{.*}}) -> !cir.f16
// LLVM-LABEL: test_mm256_reduce_add_ph
- // LLVM: call half @llvm.vector.reduce.fadd.v16f16(half 0xH8000, <16 x half> %{{.*}})
+ // LLVM: call half @llvm.vector.reduce.fadd.v16f16(half -0.000000e+00, <16 x half> %{{.*}})
// OGCG-LABEL: test_mm256_reduce_add_ph
- // OGCG: call reassoc {{.*}}@llvm.vector.reduce.fadd.v16f16(half 0xH8000, <16 x half> %{{.*}})
+ // OGCG: call reassoc {{.*}}@llvm.vector.reduce.fadd.v16f16(half -0.000000e+00, <16 x half> %{{.*}})
return _mm256_reduce_add_ph(__W);
}
@@ -30,10 +30,10 @@ _Float16 test_mm256_reduce_mul_ph(__m256h __W) {
// CIR: cir.call @_mm256_reduce_mul_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.f16>{{.*}}) -> !cir.f16
// LLVM-LABEL: test_mm256_reduce_mul_ph
- // LLVM: call half @llvm.vector.reduce.fmul.v16f16(half 0xH3C00, <16 x half> %{{.*}})
+ // LLVM: call half @llvm.vector.reduce.fmul.v16f16(half 1.000000e+00, <16 x half> %{{.*}})
// OGCG-LABEL: test_mm256_reduce_mul_ph
- // OGCG: call reassoc {{.*}}@llvm.vector.reduce.fmul.v16f16(half 0xH3C00, <16 x half> %{{.*}})
+ // OGCG: call reassoc {{.*}}@llvm.vector.reduce.fmul.v16f16(half 1.000000e+00, <16 x half> %{{.*}})
return _mm256_reduce_mul_ph(__W);
}
@@ -75,10 +75,10 @@ _Float16 test_mm_reduce_add_ph(__m128h __W) {
// CIR: cir.call @_mm_reduce_add_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.f16>{{.*}}) -> !cir.f16
// LLVM-LABEL: test_mm_reduce_add_ph
- // LLVM: call half @llvm.vector.reduce.fadd.v8f16(half 0xH8000, <8 x half> %{{.*}})
+ // LLVM: call half @llvm.vector.reduce.fadd.v8f16(half -0.000000e+00, <8 x half> %{{.*}})
// OGCG-LABEL: test_mm_reduce_add_ph
- // OGCG: call reassoc {{.*}}@llvm.vector.reduce.fadd.v8f16(half 0xH8000, <8 x half> %{{.*}})
+ // OGCG: call reassoc {{.*}}@llvm.vector.reduce.fadd.v8f16(half -0.000000e+00, <8 x half> %{{.*}})
return _mm_reduce_add_ph(__W);
}
@@ -90,10 +90,10 @@ _Float16 test_mm_reduce_mul_ph(__m128h __W) {
// CIR: cir.call @_mm_reduce_mul_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.f16>{{.*}}) -> !cir.f16
// LLVM-LABEL: test_mm_reduce_mul_ph
- // LLVM: call half @llvm.vector.reduce.fmul.v8f16(half 0xH3C00, <8 x half> %{{.*}})
+ // LLVM: call half @llvm.vector.reduce.fmul.v8f16(half 1.000000e+00, <8 x half> %{{.*}})
// OGCG-LABEL: test_mm_reduce_mul_ph
- // OGCG: call reassoc {{.*}}@llvm.vector.reduce.fmul.v8f16(half 0xH3C00, <8 x half> %{{.*}})
+ // OGCG: call reassoc {{.*}}@llvm.vector.reduce.fmul.v8f16(half 1.000000e+00, <8 x half> %{{.*}})
return _mm_reduce_mul_ph(__W);
}
diff --git a/clang/test/CIR/CodeGenBuiltins/builtin-call.cpp b/clang/test/CIR/CodeGenBuiltins/builtin-call.cpp
index d6f72b115f183..86a96be8b21c3 100644
--- a/clang/test/CIR/CodeGenBuiltins/builtin-call.cpp
+++ b/clang/test/CIR/CodeGenBuiltins/builtin-call.cpp
@@ -14,14 +14,14 @@ constexpr extern int cx_var = __builtin_is_constant_evaluated();
constexpr extern float cx_var_single = __builtin_huge_valf();
// CIR: cir.global {{.*}} @cx_var_single = #cir.fp<0x7F800000> : !cir.float
-// LLVM: @cx_var_single = {{.*}} float 0x7FF0000000000000
-// OGCG: @cx_var_single = {{.*}} float 0x7FF0000000000000
+// LLVM: @cx_var_single = {{.*}} float +inf
+// OGCG: @cx_var_single = {{.*}} float +inf
constexpr extern long double cx_var_ld = __builtin_huge_vall();
// CIR: cir.global {{.*}} @cx_var_ld = #cir.fp<0x7FFF8000000000000000> : !cir.long_double<!cir.f80>
-// LLVM: @cx_var_ld = {{.*}} x86_fp80 0xK7FFF8000000000000000
-// OGCG: @cx_var_ld = {{.*}} x86_fp80 0xK7FFF8000000000000000
+// LLVM: @cx_var_ld = {{.*}} x86_fp80 +inf
+// OGCG: @cx_var_ld = {{.*}} x86_fp80 +inf
bool is_constant_evaluated() {
return __builtin_is_constant_evaluated();
@@ -51,13 +51,13 @@ long double constant_fp_builtin_ld() {
// LLVM: define {{.*}}x86_fp80 @_Z22constant_fp_builtin_ldv()
// LLVM: %[[MEM:.+]] = alloca x86_fp80
-// LLVM: store x86_fp80 0xK3FFBCCCCCCCCCCCCCCCD, ptr %[[MEM]]
+// LLVM: store x86_fp80 1.000000e-01, ptr %[[MEM]]
// LLVM: %[[RETVAL:.+]] = load x86_fp80, ptr %[[MEM]]
// LLVM: ret x86_fp80 %[[RETVAL]]
// LLVM: }
// OGCG: define {{.*}}x86_fp80 @_Z22constant_fp_builtin_ldv()
-// OGCG: ret x86_fp80 0xK3FFBCCCCCCCCCCCCCCCD
+// OGCG: ret x86_fp80 1.000000e-01
// OGCG: }
float constant_fp_builtin_single() {
@@ -69,13 +69,13 @@ float constant_fp_builtin_single() {
// LLVM: define {{.*}}float @_Z26constant_fp_builtin_singlev()
// LLVM: %[[MEM:.+]] = alloca float
-// LLVM: store float 0x3FB99999A0000000, ptr %[[MEM]]
+// LLVM: store float 1.000000e-01, ptr %[[MEM]]
// LLVM: %[[RETVAL:.+]] = load float, ptr %[[MEM]]
// LLVM: ret float %[[RETVAL]]
// LLVM: }
// OGCG: define {{.*}}float @_Z26constant_fp_builtin_singlev()
-// OGCG: ret float 0x3FB99999A0000000
+// OGCG: ret float 1.000000e-01
// OGCG: }
void library_builtins() {
diff --git a/clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c b/clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
index 27c6730ca996a..91f9b4cc99e1a 100644
--- a/clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
+++ b/clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
@@ -29,7 +29,7 @@ int test_float_isinf_sign(float x) {
// OGCG-LABEL: test_float_isinf_sign
// OGCG: %[[ARG:.*]] = load float, ptr %{{.*}}
// OGCG: %[[ABS:.*]] = call float @llvm.fabs.f32(float %[[ARG]])
- // OGCG: %[[IS_INF:.*]] = fcmp oeq float %[[ABS]], 0x7FF0000000000000
+ // OGCG: %[[IS_INF:.*]] = fcmp oeq float %[[ABS]], +inf
// OGCG: %[[BITCAST:.*]] = bitcast float %[[ARG]] to i32
// OGCG: %[[IS_NEG:.*]] = icmp slt i32 %[[BITCAST]], 0
// OGCG: %[[SIGN:.*]] = select i1 %[[IS_NEG]], i32 -1, i32 1
diff --git a/clang/test/CIR/CodeGenBuiltins/builtin-signbit.c b/clang/test/CIR/CodeGenBuiltins/builtin-signbit.c
index 2cf7579fcf077..ae4f96c445658 100644
--- a/clang/test/CIR/CodeGenBuiltins/builtin-signbit.c
+++ b/clang/test/CIR/CodeGenBuiltins/builtin-signbit.c
@@ -89,12 +89,12 @@ void test_signbit_positive_nan(){
// CIR: cir.signbit {{.*}} : !cir.double -> !cir.bool
// CIR: cir.cast bool_to_int {{.*}} : !cir.bool -> !s32i
-// LLVM: store double 0x7FF8000000000000, ptr %{{.*}}
+// LLVM: store double +qnan, ptr %{{.*}}
// LLVM: bitcast double %{{.*}} to i64
// LLVM: icmp slt i64 %{{.*}}, 0
// LLVM: zext i1 %{{.*}} to i32
-// OGCG: store double 0x7FF8000000000000, ptr %{{.*}}
+// OGCG: store double +qnan, ptr %{{.*}}
// OGCG: bitcast double %{{.*}} to i64
// OGCG: icmp slt i64 %{{.*}}, 0
// OGCG: zext i1 %{{.*}} to i32
@@ -108,12 +108,12 @@ void test_signbit_negative_nan(){
// CIR: cir.signbit {{.*}} : !cir.double -> !cir.bool
// CIR: cir.cast bool_to_int {{.*}} : !cir.bool -> !s32i
-// LLVM: store double 0xFFF8000000000000, ptr %{{.*}}
+// LLVM: store double -qnan, ptr %{{.*}}
// LLVM: bitcast double %{{.*}} to i64
// LLVM: icmp slt i64 %{{.*}}, 0
// LLVM: zext i1 %{{.*}} to i32
-// OGCG: store double 0xFFF8000000000000, ptr %{{.*}}
+// OGCG: store double -qnan, ptr %{{.*}}
// OGCG: bitcast double %{{.*}} to i64
// OGCG: icmp slt i64 %{{.*}}, 0
// OGCG: zext i1 %{{.*}} to i32
@@ -127,12 +127,12 @@ void test_signbit_positive_infinity(){
// CIR: cir.signbit {{.*}} : !cir.double -> !cir.bool
// CIR: cir.cast bool_to_int {{.*}} : !cir.bool -> !s32i
-// LLVM: store double 0x7FF0000000000000, ptr %{{.*}}
+// LLVM: store double +inf, ptr %{{.*}}
// LLVM: bitcast double %{{.*}} to i64
// LLVM: icmp slt i64 %{{.*}}, 0
// LLVM: zext i1 %{{.*}} to i32
-// OGCG: store double 0x7FF0000000000000, ptr %{{.*}}
+// OGCG: store double +inf, ptr %{{.*}}
// OGCG: bitcast double %{{.*}} to i64
// OGCG: icmp slt i64 %{{.*}}, 0
// OGCG: zext i1 %{{.*}} to i32
@@ -146,12 +146,12 @@ void test_signbit_negative_infinity(){
// CIR: cir.signbit {{.*}} : !cir.double -> !cir.bool
// CIR: cir.cast bool_to_int {{.*}} : !cir.bool -> !s32i
-// LLVM: store double 0xFFF0000000000000, ptr %{{.*}}
+// LLVM: store double -inf, ptr %{{.*}}
// LLVM: bitcast double %{{.*}} to i64
// LLVM: icmp slt i64 %{{.*}}, 0
// LLVM: zext i1 %{{.*}} to i32
-// OGCG: store double 0xFFF0000000000000, ptr %{{.*}}
+// OGCG: store double -inf, ptr %{{.*}}
// OGCG: bitcast double %{{.*}} to i64
// OGCG: icmp slt i64 %{{.*}}, 0
// OGCG: zext i1 %{{.*}} to i32
diff --git a/clang/test/CIR/Lowering/global-var-simple.cpp b/clang/test/CIR/Lowering/global-var-simple.cpp
index ecb766694ab50..c470e9b5f06f0 100644
--- a/clang/test/CIR/Lowering/global-var-simple.cpp
+++ b/clang/test/CIR/Lowering/global-var-simple.cpp
@@ -88,12 +88,12 @@ bool boolfalse = false;
// OGCG: @boolfalse = global i8 0, align 1
_Float16 f16;
-// CHECK: @f16 = global half 0xH0000, align 2
-// OGCG: @f16 = global half 0xH0000, align 2
+// CHECK: @f16 = global half 0.000000e+00, align 2
+// OGCG: @f16 = global half 0.000000e+00, align 2
__bf16 bf16;
-// CHECK: @bf16 = global bfloat 0xR0000, align 2
-// OGCG: @bf16 = global bfloat 0xR0000, align 2
+// CHECK: @bf16 = global bfloat 0.000000e+00, align 2
+// OGCG: @bf16 = global bfloat 0.000000e+00, align 2
float f;
// CHECK: @f = global float 0.000000e+00, align 4
@@ -104,12 +104,12 @@ double d = 1.25;
// OGCG: @d = global double 1.250000e+00, align 8
long double ld;
-// CHECK: @ld = global x86_fp80 0xK00000000000000000000, align 16
-// OGCG: @ld = global x86_fp80 0xK00000000000000000000, align 16
+// CHECK: @ld = global x86_fp80 0.000000e+00, align 16
+// OGCG: @ld = global x86_fp80 0.000000e+00, align 16
__float128 f128;
-// CHECK: @f128 = global fp128 0xL00000000000000000000000000000000, align 16
-// OGCG: @f128 = global fp128 0xL00000000000000000000000000000000, align 16
+// CHECK: @f128 = global fp128 0.000000e+00, align 16
+// OGCG: @f128 = global fp128 0.000000e+00, align 16
void *vp;
// CHECK: @vp = global ptr null, align 8
diff --git a/clang/test/CodeGen/AArch64/atomic-ops-float-check-minmax.c b/clang/test/CodeGen/AArch64/atomic-ops-float-check-minmax.c
index 4d9b29b789507..3bf5cddb160e4 100644
--- a/clang/test/CodeGen/AArch64/atomic-ops-float-check-minmax.c
+++ b/clang/test/CodeGen/AArch64/atomic-ops-float-check-minmax.c
@@ -41,7 +41,7 @@
// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[F64_ADDR]], align 8
// CHECK-NEXT: store double [[TMP3]], ptr [[TMP4]], align 8
// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[F32_ADDR]], align 8
-// CHECK-NEXT: store float 0x40450CCCC0000000, ptr [[DOTATOMICTMP1]], align 4
+// CHECK-NEXT: store float 4.210000e+01, ptr [[DOTATOMICTMP1]], align 4
// CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[DOTATOMICTMP1]], align 4
// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw fmax ptr [[TMP5]], float [[TMP6]] release, align 4
// CHECK-NEXT: [[NEWVAL3:%.*]] = call float @llvm.maxnum.f32(float [[TMP7]], float [[TMP6]])
@@ -50,7 +50,7 @@
// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[F32_ADDR]], align 8
// CHECK-NEXT: store float [[TMP8]], ptr [[TMP9]], align 4
// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[F16_ADDR]], align 8
-// CHECK-NEXT: store half 0xH5143, ptr [[DOTATOMICTMP4]], align 2
+// CHECK-NEXT: store half 4.209380e+01, ptr [[DOTATOMICTMP4]], align 2
// CHECK-NEXT: [[TMP11:%.*]] = load half, ptr [[DOTATOMICTMP4]], align 2
// CHECK-NEXT: [[TMP12:%.*]] = atomicrmw fmax ptr [[TMP10]], half [[TMP11]] release, align 2
// CHECK-NEXT: [[NEWVAL6:%.*]] = call half @llvm.maxnum.f16(half [[TMP12]], half [[TMP11]])
@@ -59,7 +59,7 @@
// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[F16_ADDR]], align 8
// CHECK-NEXT: store half [[TMP13]], ptr [[TMP14]], align 2
// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[BF16_ADDR]], align 8
-// CHECK-NEXT: store bfloat 0xR4228, ptr [[DOTATOMICTMP7]], align 2
+// CHECK-NEXT: store bfloat 4.200000e+01, ptr [[DOTATOMICTMP7]], align 2
// CHECK-NEXT: [[TMP16:%.*]] = load bfloat, ptr [[DOTATOMICTMP7]], align 2
// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw fmax ptr [[TMP15]], bfloat [[TMP16]] release, align 2
// CHECK-NEXT: [[NEWVAL9:%.*]] = call bfloat @llvm.maxnum.bf16(bfloat [[TMP17]], bfloat [[TMP16]])
@@ -77,7 +77,7 @@
// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[F64_ADDR]], align 8
// CHECK-NEXT: store double [[TMP23]], ptr [[TMP24]], align 8
// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[F32_ADDR]], align 8
-// CHECK-NEXT: store float 0x40450CCCC0000000, ptr [[DOTATOMICTMP13]], align 4
+// CHECK-NEXT: store float 4.210000e+01, ptr [[DOTATOMICTMP13]], align 4
// CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[DOTATOMICTMP13]], align 4
// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw fmin ptr [[TMP25]], float [[TMP26]] release, align 4
// CHECK-NEXT: [[NEWVAL15:%.*]] = call float @llvm.minnum.f32(float [[TMP27]], float [[TMP26]])
@@ -86,7 +86,7 @@
// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[F32_ADDR]], align 8
// CHECK-NEXT: store float [[TMP28]], ptr [[TMP29]], align 4
// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[F16_ADDR]], align 8
-// CHECK-NEXT: store half 0xH5143, ptr [[DOTATOMICTMP16]], align 2
+// CHECK-NEXT: store half 4.209380e+01, ptr [[DOTATOMICTMP16]], align 2
// CHECK-NEXT: [[TMP31:%.*]] = load half, ptr [[DOTATOMICTMP16]], align 2
// CHECK-NEXT: [[TMP32:%.*]] = atomicrmw fmin ptr [[TMP30]], half [[TMP31]] release, align 2
// CHECK-NEXT: [[NEWVAL18:%.*]] = call half @llvm.minnum.f16(half [[TMP32]], half [[TMP31]])
@@ -95,7 +95,7 @@
// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[F16_ADDR]], align 8
// CHECK-NEXT: store half [[TMP33]], ptr [[TMP34]], align 2
// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[BF16_ADDR]], align 8
-// CHECK-NEXT: store bfloat 0xR4228, ptr [[DOTATOMICTMP19]], align 2
+// CHECK-NEXT: store bfloat 4.200000e+01, ptr [[DOTATOMICTMP19]], align 2
// CHECK-NEXT: [[TMP36:%.*]] = load bfloat, ptr [[DOTATOMICTMP19]], align 2
// CHECK-NEXT: [[TMP37:%.*]] = atomicrmw fmin ptr [[TMP35]], bfloat [[TMP36]] release, align 2
// CHECK-NEXT: [[NEWVAL21:%.*]] = call bfloat @llvm.minnum.bf16(bfloat [[TMP37]], bfloat [[TMP36]])
diff --git a/clang/test/CodeGen/AArch64/neon/fullfp16.c b/clang/test/CodeGen/AArch64/neon/fullfp16.c
index db0b20fe62799..6add232666efd 100644
--- a/clang/test/CodeGen/AArch64/neon/fullfp16.c
+++ b/clang/test/CodeGen/AArch64/neon/fullfp16.c
@@ -96,7 +96,7 @@ uint16_t test_vceqzh_f16(float16_t a) {
// CIR: cir.cast integral [[RES]] : !cir.int<s, 1> -> !u16i
// LLVM-SAME: (half {{.*}} [[A:%.*]])
-// LLVM: [[TMP1:%.*]] = fcmp oeq half [[A]], 0xH0000
+// LLVM: [[TMP1:%.*]] = fcmp oeq half [[A]], 0.000000e+00
// LLVM: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// LLVM: ret i16 [[TMP2]]
return vceqzh_f16(a);
diff --git a/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c b/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
index 1bee8c8d90872..c9d5071c4eb83 100644
--- a/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
+++ b/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
@@ -12,8 +12,8 @@
#include <arm_fp16.h>
// COMMON-LABEL: test_vceqzh_f16
-// UNCONSTRAINED: [[TMP1:%.*]] = fcmp oeq half %a, 0xH0000
-// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half 0xH0000, metadata !"oeq", metadata !"fpexcept.strict")
+// UNCONSTRAINED: [[TMP1:%.*]] = fcmp oeq half %a, 0.000000e+00
+// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict")
// COMMONIR: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// COMMONIR: ret i16 [[TMP2]]
uint16_t test_vceqzh_f16(float16_t a) {
@@ -21,8 +21,8 @@ uint16_t test_vceqzh_f16(float16_t a) {
}
// COMMON-LABEL: test_vcgezh_f16
-// UNCONSTRAINED: [[TMP1:%.*]] = fcmp oge half %a, 0xH0000
-// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half 0xH0000, metadata !"oge", metadata !"fpexcept.strict")
+// UNCONSTRAINED: [[TMP1:%.*]] = fcmp oge half %a, 0.000000e+00
+// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half 0.000000e+00, metadata !"oge", metadata !"fpexcept.strict")
// COMMONIR: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// COMMONIR: ret i16 [[TMP2]]
uint16_t test_vcgezh_f16(float16_t a) {
@@ -30,8 +30,8 @@ uint16_t test_vcgezh_f16(float16_t a) {
}
// COMMON-LABEL: test_vcgtzh_f16
-// UNCONSTRAINED: [[TMP1:%.*]] = fcmp ogt half %a, 0xH0000
-// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half 0xH0000, metadata !"ogt", metadata !"fpexcept.strict")
+// UNCONSTRAINED: [[TMP1:%.*]] = fcmp ogt half %a, 0.000000e+00
+// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half 0.000000e+00, metadata !"ogt", metadata !"fpexcept.strict")
// COMMONIR: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// COMMONIR: ret i16 [[TMP2]]
uint16_t test_vcgtzh_f16(float16_t a) {
@@ -39,8 +39,8 @@ uint16_t test_vcgtzh_f16(float16_t a) {
}
// COMMON-LABEL: test_vclezh_f16
-// UNCONSTRAINED: [[TMP1:%.*]] = fcmp ole half %a, 0xH0000
-// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half 0xH0000, metadata !"ole", metadata !"fpexcept.strict")
+// UNCONSTRAINED: [[TMP1:%.*]] = fcmp ole half %a, 0.000000e+00
+// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
// COMMONIR: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// COMMONIR: ret i16 [[TMP2]]
uint16_t test_vclezh_f16(float16_t a) {
@@ -48,8 +48,8 @@ uint16_t test_vclezh_f16(float16_t a) {
}
// COMMON-LABEL: test_vcltzh_f16
-// UNCONSTRAINED: [[TMP1:%.*]] = fcmp olt half %a, 0xH0000
-// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half 0xH0000, metadata !"olt", metadata !"fpexcept.strict")
+// UNCONSTRAINED: [[TMP1:%.*]] = fcmp olt half %a, 0.000000e+00
+// CONSTRAINED: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
// COMMONIR: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// COMMONIR: ret i16 [[TMP2]]
uint16_t test_vcltzh_f16(float16_t a) {
diff --git a/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c b/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
index a6f830fd48ee3..0b0282a71150e 100644
--- a/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
@@ -8,7 +8,7 @@
#include <arm_fp16.h>
// CHECK-LABEL: test_vcgezh_f16
-// CHECK: [[TMP1:%.*]] = fcmp oge half %a, 0xH0000
+// CHECK: [[TMP1:%.*]] = fcmp oge half %a, 0.000000e+00
// CHECK: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// CHECK: ret i16 [[TMP2]]
uint16_t test_vcgezh_f16(float16_t a) {
@@ -16,7 +16,7 @@ uint16_t test_vcgezh_f16(float16_t a) {
}
// CHECK-LABEL: test_vcgtzh_f16
-// CHECK: [[TMP1:%.*]] = fcmp ogt half %a, 0xH0000
+// CHECK: [[TMP1:%.*]] = fcmp ogt half %a, 0.000000e+00
// CHECK: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// CHECK: ret i16 [[TMP2]]
uint16_t test_vcgtzh_f16(float16_t a) {
@@ -24,7 +24,7 @@ uint16_t test_vcgtzh_f16(float16_t a) {
}
// CHECK-LABEL: test_vclezh_f16
-// CHECK: [[TMP1:%.*]] = fcmp ole half %a, 0xH0000
+// CHECK: [[TMP1:%.*]] = fcmp ole half %a, 0.000000e+00
// CHECK: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// CHECK: ret i16 [[TMP2]]
uint16_t test_vclezh_f16(float16_t a) {
@@ -32,7 +32,7 @@ uint16_t test_vclezh_f16(float16_t a) {
}
// CHECK-LABEL: test_vcltzh_f16
-// CHECK: [[TMP1:%.*]] = fcmp olt half %a, 0xH0000
+// CHECK: [[TMP1:%.*]] = fcmp olt half %a, 0.000000e+00
// CHECK: [[TMP2:%.*]] = sext i1 [[TMP1]] to i16
// CHECK: ret i16 [[TMP2]]
uint16_t test_vcltzh_f16(float16_t a) {
diff --git a/clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c b/clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
index 42eeb7dddd913..3bfe45804fb78 100644
--- a/clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
+++ b/clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
@@ -185,13 +185,13 @@ double test_double_pre_inc()
// CHECK-LABEL: define dso_local half @test__Float16_post_inc(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test__Float16_post_inc.n to ptr), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
+// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test__Float16_post_inc.n to ptr), half 1.000000e+00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
// CHECK-NEXT: ret half [[TMP0]]
//
// CHECK-SPIRV-LABEL: define spir_func half @test__Float16_post_inc(
// CHECK-SPIRV-SAME: ) addrspace(4) #[[ATTR0]] {
// CHECK-SPIRV-NEXT: [[ENTRY:.*:]]
-// CHECK-SPIRV-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspace(4) addrspacecast (ptr addrspace(1) @test__Float16_post_inc.n to ptr addrspace(4)), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
+// CHECK-SPIRV-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspace(4) addrspacecast (ptr addrspace(1) @test__Float16_post_inc.n to ptr addrspace(4)), half 1.000000e+00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
// CHECK-SPIRV-NEXT: ret half [[TMP0]]
//
_Float16 test__Float16_post_inc()
@@ -203,13 +203,13 @@ _Float16 test__Float16_post_inc()
// CHECK-LABEL: define dso_local half @test__Float16_post_dc(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test__Float16_post_dc.n to ptr), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
+// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test__Float16_post_dc.n to ptr), half 1.000000e+00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
// CHECK-NEXT: ret half [[TMP0]]
//
// CHECK-SPIRV-LABEL: define spir_func half @test__Float16_post_dc(
// CHECK-SPIRV-SAME: ) addrspace(4) #[[ATTR0]] {
// CHECK-SPIRV-NEXT: [[ENTRY:.*:]]
-// CHECK-SPIRV-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspace(4) addrspacecast (ptr addrspace(1) @test__Float16_post_dc.n to ptr addrspace(4)), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
+// CHECK-SPIRV-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspace(4) addrspacecast (ptr addrspace(1) @test__Float16_post_dc.n to ptr addrspace(4)), half 1.000000e+00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
// CHECK-SPIRV-NEXT: ret half [[TMP0]]
//
_Float16 test__Float16_post_dc()
@@ -221,15 +221,15 @@ _Float16 test__Float16_post_dc()
// CHECK-LABEL: define dso_local half @test__Float16_pre_dc(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test__Float16_pre_dc.n to ptr), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
-// CHECK-NEXT: [[TMP1:%.*]] = fsub half [[TMP0]], 0xH3C00
+// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test__Float16_pre_dc.n to ptr), half 1.000000e+00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
+// CHECK-NEXT: [[TMP1:%.*]] = fsub half [[TMP0]], 1.000000e+00
// CHECK-NEXT: ret half [[TMP1]]
//
// CHECK-SPIRV-LABEL: define spir_func half @test__Float16_pre_dc(
// CHECK-SPIRV-SAME: ) addrspace(4) #[[ATTR0]] {
// CHECK-SPIRV-NEXT: [[ENTRY:.*:]]
-// CHECK-SPIRV-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspace(4) addrspacecast (ptr addrspace(1) @test__Float16_pre_dc.n to ptr addrspace(4)), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
-// CHECK-SPIRV-NEXT: [[TMP1:%.*]] = fsub half [[TMP0]], 0xH3C00
+// CHECK-SPIRV-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspace(4) addrspacecast (ptr addrspace(1) @test__Float16_pre_dc.n to ptr addrspace(4)), half 1.000000e+00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
+// CHECK-SPIRV-NEXT: [[TMP1:%.*]] = fsub half [[TMP0]], 1.000000e+00
// CHECK-SPIRV-NEXT: ret half [[TMP1]]
//
_Float16 test__Float16_pre_dc()
@@ -241,15 +241,15 @@ _Float16 test__Float16_pre_dc()
// CHECK-LABEL: define dso_local half @test__Float16_pre_inc(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test__Float16_pre_inc.n to ptr), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
-// CHECK-NEXT: [[TMP1:%.*]] = fadd half [[TMP0]], 0xH3C00
+// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test__Float16_pre_inc.n to ptr), half 1.000000e+00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
+// CHECK-NEXT: [[TMP1:%.*]] = fadd half [[TMP0]], 1.000000e+00
// CHECK-NEXT: ret half [[TMP1]]
//
// CHECK-SPIRV-LABEL: define spir_func half @test__Float16_pre_inc(
// CHECK-SPIRV-SAME: ) addrspace(4) #[[ATTR0]] {
// CHECK-SPIRV-NEXT: [[ENTRY:.*:]]
-// CHECK-SPIRV-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspace(4) addrspacecast (ptr addrspace(1) @test__Float16_pre_inc.n to ptr addrspace(4)), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
-// CHECK-SPIRV-NEXT: [[TMP1:%.*]] = fadd half [[TMP0]], 0xH3C00
+// CHECK-SPIRV-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspace(4) addrspacecast (ptr addrspace(1) @test__Float16_pre_inc.n to ptr addrspace(4)), half 1.000000e+00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META2]], !amdgpu.no.remote.memory [[META2]]
+// CHECK-SPIRV-NEXT: [[TMP1:%.*]] = fadd half [[TMP0]], 1.000000e+00
// CHECK-SPIRV-NEXT: ret half [[TMP1]]
//
_Float16 test__Float16_pre_inc()
diff --git a/clang/test/CodeGen/PowerPC/ppc64-complex-parms.c b/clang/test/CodeGen/PowerPC/ppc64-complex-parms.c
index b8f59f57b2dcd..bd3a0222286d3 100644
--- a/clang/test/CodeGen/PowerPC/ppc64-complex-parms.c
+++ b/clang/test/CodeGen/PowerPC/ppc64-complex-parms.c
@@ -110,8 +110,8 @@ void bar_long_double(void) {
// CHECK: %[[VAR21:[A-Za-z0-9.]+]] = alloca { ppc_fp128, ppc_fp128 }, align 16
// CHECK: %[[VAR22:[A-Za-z0-9.]+]] = getelementptr inbounds nuw { ppc_fp128, ppc_fp128 }, ptr %[[VAR21]], i32 0, i32 0
// CHECK: %[[VAR23:[A-Za-z0-9.]+]] = getelementptr inbounds nuw { ppc_fp128, ppc_fp128 }, ptr %[[VAR21]], i32 0, i32 1
-// CHECK: store ppc_fp128 0xM40000000000000000000000000000000, ptr %[[VAR22]]
-// CHECK: store ppc_fp128 0xMC0040000000000008000000000000000, ptr %[[VAR23]]
+// CHECK: store ppc_fp128 2.000000e+00, ptr %[[VAR22]]
+// CHECK: store ppc_fp128 -2.500000e+00, ptr %[[VAR23]]
// CHECK: %[[VAR24:[A-Za-z0-9.]+]] = getelementptr inbounds nuw { ppc_fp128, ppc_fp128 }, ptr %[[VAR21]], i32 0, i32 0
// CHECK: %[[VAR25:[A-Za-z0-9.]+]] = load ppc_fp128, ptr %[[VAR24]], align 16
// CHECK: %[[VAR26:[A-Za-z0-9.]+]] = getelementptr inbounds nuw { ppc_fp128, ppc_fp128 }, ptr %[[VAR21]], i32 0, i32 1
@@ -126,8 +126,8 @@ void bar_ibm128(void) {
// CHECK: %[[VAR21:[A-Za-z0-9.]+]] = alloca { ppc_fp128, ppc_fp128 }, align 16
// CHECK: %[[VAR22:[A-Za-z0-9.]+]] = getelementptr inbounds nuw { ppc_fp128, ppc_fp128 }, ptr %[[VAR21]], i32 0, i32 0
// CHECK: %[[VAR23:[A-Za-z0-9.]+]] = getelementptr inbounds nuw { ppc_fp128, ppc_fp128 }, ptr %[[VAR21]], i32 0, i32 1
-// CHECK: store ppc_fp128 0xM40000000000000000000000000000000, ptr %[[VAR22]]
-// CHECK: store ppc_fp128 0xMC0040000000000008000000000000000, ptr %[[VAR23]]
+// CHECK: store ppc_fp128 2.000000e+00, ptr %[[VAR22]]
+// CHECK: store ppc_fp128 -2.500000e+00, ptr %[[VAR23]]
// CHECK: %[[VAR24:[A-Za-z0-9.]+]] = getelementptr inbounds nuw { ppc_fp128, ppc_fp128 }, ptr %[[VAR21]], i32 0, i32 0
// CHECK: %[[VAR25:[A-Za-z0-9.]+]] = load ppc_fp128, ptr %[[VAR24]], align 16
// CHECK: %[[VAR26:[A-Za-z0-9.]+]] = getelementptr inbounds nuw { ppc_fp128, ppc_fp128 }, ptr %[[VAR21]], i32 0, i32 1
diff --git a/clang/test/CodeGen/RISCV/riscv64-vararg.c b/clang/test/CodeGen/RISCV/riscv64-vararg.c
index 51ffc19e41d30..f43bcae40ab8b 100644
--- a/clang/test/CodeGen/RISCV/riscv64-vararg.c
+++ b/clang/test/CodeGen/RISCV/riscv64-vararg.c
@@ -75,7 +75,7 @@ int f_va_callee(int, ...);
// CHECK-NEXT: [[TMP2:%.*]] = load i128, ptr [[COERCE_DIVE]], align 16
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[BYVAL_TEMP]], ptr align 8 [[DOTCOMPOUNDLITERAL6]], i64 32, i1 false)
// CHECK-NEXT: [[CALL:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i64 noundef 3, double noundef 4.000000e+00, double noundef 5.000000e+00, i64 [[TMP0]], [2 x i64] [[TMP1]], i128 [[TMP2]], ptr noundef dead_on_return [[BYVAL_TEMP]])
-// CHECK-NEXT: [[CALL11:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, fp128 noundef 0xL00000000000000004001400000000000, i32 noundef signext 6, i32 noundef signext 7, i32 noundef signext 8, i32 noundef signext 9)
+// CHECK-NEXT: [[CALL11:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, fp128 noundef 5.000000e+00, i32 noundef signext 6, i32 noundef signext 7, i32 noundef signext 8, i32 noundef signext 9)
// CHECK-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL_ALIGNED]], ptr [[DOTCOMPOUNDLITERAL12]], i32 0, i32 0
// CHECK-NEXT: store i128 5, ptr [[A13]], align 16
// CHECK-NEXT: [[COERCE_DIVE14:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL_ALIGNED]], ptr [[DOTCOMPOUNDLITERAL12]], i32 0, i32 0
@@ -87,7 +87,7 @@ int f_va_callee(int, ...);
// CHECK-NEXT: store ptr null, ptr [[B18]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load [2 x i64], ptr [[DOTCOMPOUNDLITERAL16]], align 8
// CHECK-NEXT: [[CALL19:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, [2 x i64] [[TMP4]], i32 noundef signext 6, i32 noundef signext 7, i32 noundef signext 8, i32 noundef signext 9)
-// CHECK-NEXT: [[CALL20:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, fp128 noundef 0xL00000000000000004001800000000000, i32 noundef signext 7, i32 noundef signext 8, i32 noundef signext 9)
+// CHECK-NEXT: [[CALL20:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, fp128 noundef 6.000000e+00, i32 noundef signext 7, i32 noundef signext 8, i32 noundef signext 9)
// CHECK-NEXT: [[A22:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL_ALIGNED]], ptr [[DOTCOMPOUNDLITERAL21]], i32 0, i32 0
// CHECK-NEXT: store i128 6, ptr [[A22]], align 16
// CHECK-NEXT: [[COERCE_DIVE23:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL_ALIGNED]], ptr [[DOTCOMPOUNDLITERAL21]], i32 0, i32 0
@@ -99,7 +99,7 @@ int f_va_callee(int, ...);
// CHECK-NEXT: store ptr null, ptr [[B27]], align 8
// CHECK-NEXT: [[TMP6:%.*]] = load [2 x i64], ptr [[DOTCOMPOUNDLITERAL25]], align 8
// CHECK-NEXT: [[CALL28:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, [2 x i64] [[TMP6]], i32 noundef signext 7, i32 noundef signext 8, i32 noundef signext 9)
-// CHECK-NEXT: [[CALL29:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, fp128 noundef 0xL00000000000000004001C00000000000, i32 noundef signext 8, i32 noundef signext 9)
+// CHECK-NEXT: [[CALL29:%.*]] = call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, fp128 noundef 7.000000e+00, i32 noundef signext 8, i32 noundef signext 9)
// CHECK-NEXT: [[A31:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL_ALIGNED]], ptr [[DOTCOMPOUNDLITERAL30]], i32 0, i32 0
// CHECK-NEXT: store i128 7, ptr [[A31]], align 16
// CHECK-NEXT: [[COERCE_DIVE32:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL_ALIGNED]], ptr [[DOTCOMPOUNDLITERAL30]], i32 0, i32 0
diff --git a/clang/test/CodeGen/SystemZ/atomic_is_lock_free.c b/clang/test/CodeGen/SystemZ/atomic_is_lock_free.c
index 32c436eaf36dd..c45c0a7c0f97f 100644
--- a/clang/test/CodeGen/SystemZ/atomic_is_lock_free.c
+++ b/clang/test/CodeGen/SystemZ/atomic_is_lock_free.c
@@ -22,7 +22,7 @@ _Atomic long double Atomic_fp128; // Also check the alignment of this.
// CHECK: @Int128_Atomic = {{.*}} i128 0, align 16
// CHECK: @Int128_Al16 = {{.*}} i128 0, align 16
// CHECK: @AtomicStruct = {{.*}} { %struct.anon, [4 x i8] } zeroinitializer, align 16
-// CHECK: @Atomic_fp128 = {{.*}} fp128 0xL00000000000000000000000000000000, align 16
+// CHECK: @Atomic_fp128 = {{.*}} fp128 0.000000e+00, align 16
// CHECK-LABEL: @fun0
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
index 050fded6bedd4..8d674ce1607df 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
@@ -235,11 +235,11 @@ void test_float(void) {
// (emulated)
vd = vec_ctd(vsl, 31);
// CHECK: [[VAL:%[^ ]+]] = tail call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i64(<2 x i64> %{{.*}}, metadata !{{.*}})
- // CHECK: call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> [[VAL]], <2 x double> splat (double 0x3E00000000000000), metadata !{{.*}})
+ // CHECK: call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> [[VAL]], <2 x double> splat (double f0x3E00000000000000), metadata !{{.*}})
// (emulated)
vd = vec_ctd(vul, 31);
// CHECK: [[VAL:%[^ ]+]] = tail call <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i64(<2 x i64> %{{.*}}, metadata !{{.*}})
- // CHECK: call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> [[VAL]], <2 x double> splat (double 0x3E00000000000000), metadata !{{.*}})
+ // CHECK: call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> [[VAL]], <2 x double> splat (double f0x3E00000000000000), metadata !{{.*}})
// (emulated)
vsl = vec_ctsl(vd, 0);
@@ -257,11 +257,11 @@ void test_float(void) {
// CHECK: call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(<2 x double> [[VAL]], metadata !{{.*}})
// (emulated)
vsl = vec_ctsl(vd, 31);
- // CHECK: [[VAL:%[^ ]+]] = tail call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %{{.*}}, <2 x double> splat (double 0x41E0000000000000), metadata !{{.*}})
+ // CHECK: [[VAL:%[^ ]+]] = tail call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %{{.*}}, <2 x double> splat (double f0x41E0000000000000), metadata !{{.*}})
// CHECK: call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(<2 x double> [[VAL]], metadata !{{.*}})
// (emulated)
vul = vec_ctul(vd, 31);
- // CHECK: [[VAL:%[^ ]+]] = tail call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %{{.*}}, <2 x double> splat (double 0x41E0000000000000), metadata !{{.*}})
+ // CHECK: [[VAL:%[^ ]+]] = tail call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %{{.*}}, <2 x double> splat (double f0x41E0000000000000), metadata !{{.*}})
// CHECK: call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(<2 x double> [[VAL]], metadata !{{.*}})
// (emulated)
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
index 66349a4316d8e..a78eaf3606a53 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
@@ -4850,11 +4850,11 @@ void test_float(void) {
// (emulated)
vd = vec_ctd(vsl, 31);
// CHECK: [[VAL:%[^ ]+]] = sitofp <2 x i64> %{{.*}} to <2 x double>
- // CHECK: fmul nnan <2 x double> [[VAL]], splat (double 0x3E00000000000000)
+ // CHECK: fmul nnan <2 x double> [[VAL]], splat (double f0x3E00000000000000)
// (emulated)
vd = vec_ctd(vul, 31);
// CHECK: [[VAL:%[^ ]+]] = uitofp <2 x i64> %{{.*}} to <2 x double>
- // CHECK: fmul nnan <2 x double> [[VAL]], splat (double 0x3E00000000000000)
+ // CHECK: fmul nnan <2 x double> [[VAL]], splat (double f0x3E00000000000000)
// (emulated)
vsl = vec_ctsl(vd, 0);
@@ -4872,11 +4872,11 @@ void test_float(void) {
// CHECK: fptoui <2 x double> [[VAL]] to <2 x i64>
// (emulated)
vsl = vec_ctsl(vd, 31);
- // CHECK: [[VAL:%[^ ]+]] = fmul <2 x double> %{{.*}}, splat (double 0x41E0000000000000)
+ // CHECK: [[VAL:%[^ ]+]] = fmul <2 x double> %{{.*}}, splat (double f0x41E0000000000000)
// CHECK: fptosi <2 x double> [[VAL]] to <2 x i64>
// (emulated)
vul = vec_ctul(vd, 31);
- // CHECK: [[VAL:%[^ ]+]] = fmul <2 x double> %{{.*}}, splat (double 0x41E0000000000000)
+ // CHECK: [[VAL:%[^ ]+]] = fmul <2 x double> %{{.*}}, splat (double f0x41E0000000000000)
// CHECK: fptoui <2 x double> [[VAL]] to <2 x i64>
// (emulated)
diff --git a/clang/test/CodeGen/X86/Float16-arithmetic.c b/clang/test/CodeGen/X86/Float16-arithmetic.c
index 064a85d5ee126..7dd558a47cb22 100644
--- a/clang/test/CodeGen/X86/Float16-arithmetic.c
+++ b/clang/test/CodeGen/X86/Float16-arithmetic.c
@@ -230,7 +230,7 @@ _Float16 RealOp_c(_Float16 _Complex a) {
// CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
// CHECK-NEXT: [[EXT:%.*]] = fpext half [[TMP0]] to float
-// CHECK-NEXT: ret half 0xH0000
+// CHECK-NEXT: ret half 0.000000e+00
//
_Float16 ImagOp(_Float16 a) {
return __imag a;
diff --git a/clang/test/CodeGen/X86/Float16-complex.c b/clang/test/CodeGen/X86/Float16-complex.c
index 53d44f3ae966b..16370a1b08e34 100644
--- a/clang/test/CodeGen/X86/Float16-complex.c
+++ b/clang/test/CodeGen/X86/Float16-complex.c
@@ -15,7 +15,7 @@
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[ADD]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP2]]
//
@@ -35,7 +35,7 @@
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP2]]
//
@@ -216,7 +216,7 @@ _Float16 _Complex add_half_cc(_Float16 _Complex a, _Float16 _Complex b) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[ADD1]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP3]]
//
@@ -241,7 +241,7 @@ _Float16 _Complex add_half_cc(_Float16 _Complex a, _Float16 _Complex b) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP3]]
//
@@ -655,7 +655,7 @@ _Float16 _Complex add2_haff_ccc(_Float16 _Complex a, _Float16 _Complex b, _Float
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[SUB]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP2]]
//
@@ -675,7 +675,7 @@ _Float16 _Complex add2_haff_ccc(_Float16 _Complex a, _Float16 _Complex b, _Float
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP2]]
//
@@ -854,7 +854,7 @@ _Float16 _Complex sub_half_cc(_Float16 _Complex a, _Float16 _Complex b) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[MUL]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP2]]
//
@@ -874,7 +874,7 @@ _Float16 _Complex sub_half_cc(_Float16 _Complex a, _Float16 _Complex b) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP2]]
//
@@ -1096,7 +1096,7 @@ _Float16 _Complex mul_half_cc(_Float16 _Complex a, _Float16 _Complex b) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[DIV]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP2]]
//
@@ -1116,7 +1116,7 @@ _Float16 _Complex mul_half_cc(_Float16 _Complex a, _Float16 _Complex b) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP2]]
//
@@ -1187,7 +1187,7 @@ _Float16 _Complex div_half_cr(_Float16 _Complex a, _Float16 b) {
// AVX-NEXT: [[B_REAL:%.*]] = load half, ptr [[B_REALP]], align 2
// AVX-NEXT: [[B_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[B]], i32 0, i32 1
// AVX-NEXT: [[B_IMAG:%.*]] = load half, ptr [[B_IMAGP]], align 2
-// AVX-NEXT: [[CALL:%.*]] = call <2 x half> @__divhc3(half noundef [[TMP0]], half noundef 0xH0000, half noundef [[B_REAL]], half noundef [[B_IMAG]]) #[[ATTR1]]
+// AVX-NEXT: [[CALL:%.*]] = call <2 x half> @__divhc3(half noundef [[TMP0]], half noundef 0.000000e+00, half noundef [[B_REAL]], half noundef [[B_IMAG]]) #[[ATTR1]]
// AVX-NEXT: store <2 x half> [[CALL]], ptr [[COERCE]], align 2
// AVX-NEXT: [[COERCE_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[COERCE]], i32 0, i32 0
// AVX-NEXT: [[COERCE_REAL:%.*]] = load half, ptr [[COERCE_REALP]], align 2
@@ -1318,7 +1318,7 @@ _Float16 _Complex div_half_cc(_Float16 _Complex a, _Float16 _Complex b) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[TMP2]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP3]]
//
@@ -1340,7 +1340,7 @@ _Float16 _Complex div_half_cc(_Float16 _Complex a, _Float16 _Complex b) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[TMP2]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP3]]
//
@@ -1367,7 +1367,7 @@ _Float16 _Complex addcompound_half_rr(_Float16 a, _Float16 c) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[TMP1]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP2]]
//
@@ -1393,7 +1393,7 @@ _Float16 _Complex addcompound_half_rr(_Float16 a, _Float16 c) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[TMP1]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP2]]
//
@@ -1553,7 +1553,7 @@ _Float16 _Complex addcompound_half_cc(_Float16 _Complex a, _Float16 _Complex c)
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[FNEG]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1569,7 +1569,7 @@ _Float16 _Complex addcompound_half_cc(_Float16 _Complex a, _Float16 _Complex c)
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1630,7 +1630,7 @@ _Float16 _Complex MinusOp_c(_Float16 _Complex a) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[TMP0]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1645,7 +1645,7 @@ _Float16 _Complex MinusOp_c(_Float16 _Complex a) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1702,7 +1702,7 @@ _Float16 _Complex PlusOp_c(_Float16 _Complex a) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[TMP0]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1717,7 +1717,7 @@ _Float16 _Complex PlusOp_c(_Float16 _Complex a) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1735,7 +1735,7 @@ _Float16 _Complex RealOp_r(_Float16 a) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[TMP0]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1751,7 +1751,7 @@ _Float16 _Complex RealOp_r(_Float16 a) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP0]]
//
@@ -1767,8 +1767,8 @@ _Float16 _Complex RealOp_c(_Float16 _Complex a) {
// AVX-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_REALP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1781,8 +1781,8 @@ _Float16 _Complex RealOp_c(_Float16 _Complex a) {
// X86-NEXT: [[EXT:%.*]] = fpext half [[TMP0]] to float
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_REALP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1800,7 +1800,7 @@ _Float16 _Complex ImagOp_r(_Float16 a) {
// AVX-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// AVX-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// AVX-NEXT: store half [[TMP0]], ptr [[RETVAL_REALP]], align 2
-// AVX-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// AVX-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// AVX-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// AVX-NEXT: ret <2 x half> [[TMP1]]
//
@@ -1816,7 +1816,7 @@ _Float16 _Complex ImagOp_r(_Float16 a) {
// X86-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
// X86-NEXT: [[RETVAL_IMAGP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 1
// X86-NEXT: store half [[UNPROMOTION]], ptr [[RETVAL_REALP]], align 2
-// X86-NEXT: store half 0xH0000, ptr [[RETVAL_IMAGP]], align 2
+// X86-NEXT: store half 0.000000e+00, ptr [[RETVAL_IMAGP]], align 2
// X86-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr [[RETVAL]], align 2
// X86-NEXT: ret <2 x half> [[TMP0]]
//
diff --git a/clang/test/CodeGen/X86/avx512fp16-builtins.c b/clang/test/CodeGen/X86/avx512fp16-builtins.c
index 840ada8f30bcd..d3443d0fda9e3 100644
--- a/clang/test/CodeGen/X86/avx512fp16-builtins.c
+++ b/clang/test/CodeGen/X86/avx512fp16-builtins.c
@@ -3782,7 +3782,7 @@ __m128h test_mm_maskz_fmadd_sh(__mmask8 __U, __m128h __A, __m128h __B, __m128h _
// CHECK-NEXT: [[FMA:%.+]] = call half @llvm.fma.f16(half [[A]], half [[B]], half [[C]])
// CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
// CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
- // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0xH0000
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0.000000e+00
// CHECK-NEXT: insertelement <8 x half> [[ORIGA]], half [[SEL]], i64 0
return _mm_maskz_fmadd_sh(__U, __A, __B, __C);
}
@@ -3795,7 +3795,7 @@ __m128h test_mm_maskz_fmadd_round_sh(__mmask8 __U, __m128h __A, __m128h __B, __m
// CHECK-NEXT: [[FMA:%.+]] = call half @llvm.x86.avx512fp16.vfmadd.f16(half [[A]], half [[B]], half [[C]], i32 11)
// CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
// CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
- // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0xH0000
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0.000000e+00
// CHECK-NEXT: insertelement <8 x half> [[ORIGA]], half [[SEL]], i64 0
return _mm_maskz_fmadd_round_sh(__U, __A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
}
@@ -3889,7 +3889,7 @@ __m128h test_mm_maskz_fmsub_sh(__mmask8 __U, __m128h __A, __m128h __B, __m128h _
// CHECK-NEXT: %{{.*}} = call half @llvm.fma.f16(half %{{.*}}, half %{{.*}}, half %{{.*}})
// CHECK-NEXT: %{{.*}} = bitcast i8 %{{.*}} to <8 x i1>
// CHECK-NEXT: %{{.*}} = extractelement <8 x i1> %{{.*}}, i64 0
- // CHECK-NEXT: %{{.*}} = select i1 %{{.*}}, half %{{.*}}, half 0xH0000
+ // CHECK-NEXT: %{{.*}} = select i1 %{{.*}}, half %{{.*}}, half 0.000000e+00
// CHECK-NEXT: %{{.*}} = insertelement <8 x half> %{{.*}}, half %{{.*}}, i64 0
// CHECK-NEXT: ret <8 x half> %{{.*}}
return _mm_maskz_fmsub_sh(__U, __A, __B, __C);
@@ -3904,7 +3904,7 @@ __m128h test_mm_maskz_fmsub_round_sh(__mmask8 __U, __m128h __A, __m128h __B, __m
// CHECK-NEXT: %{{.*}} = call half @llvm.x86.avx512fp16.vfmadd.f16(half %{{.*}}, half %{{.*}}, half %{{.*}}, i32 11)
// CHECK-NEXT: %{{.*}} = bitcast i8 %{{.*}} to <8 x i1>
// CHECK-NEXT: %{{.*}} = extractelement <8 x i1> %{{.*}}, i64 0
- // CHECK-NEXT: %{{.*}} = select i1 %{{.*}}, half %{{.*}}, half 0xH0000
+ // CHECK-NEXT: %{{.*}} = select i1 %{{.*}}, half %{{.*}}, half 0.000000e+00
// CHECK-NEXT: %{{.*}} = insertelement <8 x half> %{{.*}}, half %{{.*}}, i64 0
// CHECK-NEXT: ret <8 x half> %{{.*}}
return _mm_maskz_fmsub_round_sh(__U, __A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
@@ -3998,7 +3998,7 @@ __m128h test_mm_maskz_fnmadd_sh(__mmask8 __U, __m128h __A, __m128h __B, __m128h
// CHECK-NEXT: [[FMA:%.+]] = call half @llvm.fma.f16(half [[A]], half [[B]], half [[C]])
// CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
// CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
- // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0xH0000
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0.000000e+00
// CHECK-NEXT: insertelement <8 x half> [[ORIGA]], half [[SEL]], i64 0
return _mm_maskz_fnmadd_sh(__U, __A, __B, __C);
}
@@ -4012,7 +4012,7 @@ __m128h test_mm_maskz_fnmadd_round_sh(__mmask8 __U, __m128h __A, __m128h __B, __
// CHECK-NEXT: [[FMA:%.+]] = call half @llvm.x86.avx512fp16.vfmadd.f16(half [[A]], half [[B]], half [[C]], i32 11)
// CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
// CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
- // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0xH0000
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0.000000e+00
// CHECK-NEXT: insertelement <8 x half> [[ORIGA]], half [[SEL]], i64 0
return _mm_maskz_fnmadd_round_sh(__U, __A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
}
@@ -4108,7 +4108,7 @@ __m128h test_mm_maskz_fnmsub_sh(__mmask8 __U, __m128h __A, __m128h __B, __m128h
// CHECK-NEXT: [[FMA:%.+]] = call half @llvm.fma.f16(half [[A]], half [[B]], half [[C]])
// CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
// CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
- // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0xH0000
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0.000000e+00
// CHECK-NEXT: insertelement <8 x half> [[ORIGA]], half [[SEL]], i64 0
return _mm_maskz_fnmsub_sh(__U, __A, __B, __C);
}
@@ -4123,7 +4123,7 @@ __m128h test_mm_maskz_fnmsub_round_sh(__mmask8 __U, __m128h __A, __m128h __B, __
// CHECK-NEXT: [[FMA:%.+]] = call half @llvm.x86.avx512fp16.vfmadd.f16(half [[A]], half [[B]], half [[C]], i32 11)
// CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
// CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
- // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0xH0000
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, half [[FMA]], half 0.000000e+00
// CHECK-NEXT: insertelement <8 x half> [[ORIGA]], half [[SEL]], i64 0
return _mm_maskz_fnmsub_round_sh(__U, __A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
}
@@ -4534,13 +4534,13 @@ __m128h test_mm_maskz_fmul_round_sch(__mmask8 __U, __m128h __A, __m128h __B) {
_Float16 test_mm512_reduce_add_ph(__m512h __W) {
// CHECK-LABEL: test_mm512_reduce_add_ph
- // CHECK: @llvm.vector.reduce.fadd.v32f16(half 0xH8000, <32 x half> %{{.*}})
+ // CHECK: @llvm.vector.reduce.fadd.v32f16(half -0.000000e+00, <32 x half> %{{.*}})
return _mm512_reduce_add_ph(__W);
}
_Float16 test_mm512_reduce_mul_ph(__m512h __W) {
// CHECK-LABEL: test_mm512_reduce_mul_ph
- // CHECK: @llvm.vector.reduce.fmul.v32f16(half 0xH3C00, <32 x half> %{{.*}})
+ // CHECK: @llvm.vector.reduce.fmul.v32f16(half 1.000000e+00, <32 x half> %{{.*}})
return _mm512_reduce_mul_ph(__W);
}
diff --git a/clang/test/CodeGen/X86/avx512vlfp16-builtins.c b/clang/test/CodeGen/X86/avx512vlfp16-builtins.c
index 4aec29838f4a6..4385057c1cfd9 100644
--- a/clang/test/CodeGen/X86/avx512vlfp16-builtins.c
+++ b/clang/test/CodeGen/X86/avx512vlfp16-builtins.c
@@ -29,13 +29,13 @@ TEST_CONSTEXPR(_mm256_cvtsh_h((__m256h){-32.0, 31.0, -30.0, 29.0, -28.0, 27.0, -
__m128h test_mm_set_sh(_Float16 __h) {
// CHECK-LABEL: test_mm_set_sh
// CHECK: insertelement <8 x half> {{.*}}, i32 0
- // CHECK: insertelement <8 x half> %{{.*}}, half 0xH0000, i32 1
- // CHECK: insertelement <8 x half> %{{.*}}, half 0xH0000, i32 2
- // CHECK: insertelement <8 x half> %{{.*}}, half 0xH0000, i32 3
- // CHECK: insertelement <8 x half> %{{.*}}, half 0xH0000, i32 4
- // CHECK: insertelement <8 x half> %{{.*}}, half 0xH0000, i32 5
- // CHECK: insertelement <8 x half> %{{.*}}, half 0xH0000, i32 6
- // CHECK: insertelement <8 x half> %{{.*}}, half 0xH0000, i32 7
+ // CHECK: insertelement <8 x half> %{{.*}}, half 0.000000e+00, i32 1
+ // CHECK: insertelement <8 x half> %{{.*}}, half 0.000000e+00, i32 2
+ // CHECK: insertelement <8 x half> %{{.*}}, half 0.000000e+00, i32 3
+ // CHECK: insertelement <8 x half> %{{.*}}, half 0.000000e+00, i32 4
+ // CHECK: insertelement <8 x half> %{{.*}}, half 0.000000e+00, i32 5
+ // CHECK: insertelement <8 x half> %{{.*}}, half 0.000000e+00, i32 6
+ // CHECK: insertelement <8 x half> %{{.*}}, half 0.000000e+00, i32 7
return _mm_set_sh(__h);
}
@@ -3156,13 +3156,13 @@ __m256h test_mm256_permutexvar_ph(__m256i __A, __m256h __B) {
_Float16 test_mm256_reduce_add_ph(__m256h __W) {
// CHECK-LABEL: test_mm256_reduce_add_ph
- // CHECK: @llvm.vector.reduce.fadd.v16f16(half 0xH8000, <16 x half> %{{.*}})
+ // CHECK: @llvm.vector.reduce.fadd.v16f16(half -0.000000e+00, <16 x half> %{{.*}})
return _mm256_reduce_add_ph(__W);
}
_Float16 test_mm256_reduce_mul_ph(__m256h __W) {
// CHECK-LABEL: test_mm256_reduce_mul_ph
- // CHECK: @llvm.vector.reduce.fmul.v16f16(half 0xH3C00, <16 x half> %{{.*}})
+ // CHECK: @llvm.vector.reduce.fmul.v16f16(half 1.000000e+00, <16 x half> %{{.*}})
return _mm256_reduce_mul_ph(__W);
}
@@ -3180,13 +3180,13 @@ _Float16 test_mm256_reduce_min_ph(__m256h __W) {
_Float16 test_mm_reduce_add_ph(__m128h __W) {
// CHECK-LABEL: test_mm_reduce_add_ph
- // CHECK: @llvm.vector.reduce.fadd.v8f16(half 0xH8000, <8 x half> %{{.*}})
+ // CHECK: @llvm.vector.reduce.fadd.v8f16(half -0.000000e+00, <8 x half> %{{.*}})
return _mm_reduce_add_ph(__W);
}
_Float16 test_mm_reduce_mul_ph(__m128h __W) {
// CHECK-LABEL: test_mm_reduce_mul_ph
- // CHECK: @llvm.vector.reduce.fmul.v8f16(half 0xH3C00, <8 x half> %{{.*}})
+ // CHECK: @llvm.vector.reduce.fmul.v8f16(half 1.000000e+00, <8 x half> %{{.*}})
return _mm_reduce_mul_ph(__W);
}
diff --git a/clang/test/CodeGen/X86/x86-atomic-long_double.c b/clang/test/CodeGen/X86/x86-atomic-long_double.c
index 9c82784807dac..298107049da70 100644
--- a/clang/test/CodeGen/X86/x86-atomic-long_double.c
+++ b/clang/test/CodeGen/X86/x86-atomic-long_double.c
@@ -18,7 +18,7 @@
// X64-NEXT: br label %[[ATOMIC_OP:.*]]
// X64: [[ATOMIC_OP]]:
// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
-// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000
+// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 1.000000e+00
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
@@ -48,7 +48,7 @@
// X86-NEXT: br label %[[ATOMIC_OP:.*]]
// X86: [[ATOMIC_OP]]:
// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
-// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000
+// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 1.000000e+00
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
@@ -80,7 +80,7 @@ long double testinc(_Atomic long double *addr) {
// X64-NEXT: br label %[[ATOMIC_OP:.*]]
// X64: [[ATOMIC_OP]]:
// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
-// X64-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000
+// X64-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], -1.000000e+00
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
@@ -110,7 +110,7 @@ long double testinc(_Atomic long double *addr) {
// X86-NEXT: br label %[[ATOMIC_OP:.*]]
// X86: [[ATOMIC_OP]]:
// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
-// X86-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000
+// X86-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], -1.000000e+00
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
@@ -143,7 +143,7 @@ long double testdec(_Atomic long double *addr) {
// X64-NEXT: br label %[[ATOMIC_OP:.*]]
// X64: [[ATOMIC_OP]]:
// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
-// X64-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 0xK4003C800000000000000
+// X64-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 2.500000e+01
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
@@ -178,7 +178,7 @@ long double testdec(_Atomic long double *addr) {
// X86-NEXT: br label %[[ATOMIC_OP:.*]]
// X86: [[ATOMIC_OP]]:
// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
-// X86-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 0xK4003C800000000000000
+// X86-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 2.500000e+01
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
@@ -206,7 +206,7 @@ long double testcompassign(_Atomic long double *addr) {
// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8
// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP]], i8 0, i64 16, i1 false)
-// X64-NEXT: store x86_fp80 0xK4005E600000000000000, ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: store x86_fp80 1.150000e+02, ptr [[ATOMIC_TEMP]], align 16
// X64-NEXT: [[TMP1:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 16
// X64-NEXT: store atomic i128 [[TMP1]], ptr [[TMP0]] seq_cst, align 16
// X64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8
@@ -224,7 +224,7 @@ long double testcompassign(_Atomic long double *addr) {
// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4
// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP]], i8 0, i64 12, i1 false)
-// X86-NEXT: store x86_fp80 0xK4005E600000000000000, ptr [[ATOMIC_TEMP]], align 4
+// X86-NEXT: store x86_fp80 1.150000e+02, ptr [[ATOMIC_TEMP]], align 4
// X86-NEXT: call void @__atomic_store(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)
// X86-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4
// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP1]], i32 noundef 5)
@@ -253,7 +253,7 @@ long double testassign(_Atomic long double *addr) {
// X64-NEXT: br label %[[ATOMIC_OP:.*]]
// X64: [[ATOMIC_OP]]:
// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
-// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000
+// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 1.000000e+00
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
@@ -283,7 +283,7 @@ long double testassign(_Atomic long double *addr) {
// X86-NEXT: br label %[[ATOMIC_OP:.*]]
// X86: [[ATOMIC_OP]]:
// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
-// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000
+// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 1.000000e+00
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
@@ -314,7 +314,7 @@ long double test_volatile_inc(volatile _Atomic long double *addr) {
// X64-NEXT: br label %[[ATOMIC_OP:.*]]
// X64: [[ATOMIC_OP]]:
// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
-// X64-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000
+// X64-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], -1.000000e+00
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
@@ -344,7 +344,7 @@ long double test_volatile_inc(volatile _Atomic long double *addr) {
// X86-NEXT: br label %[[ATOMIC_OP:.*]]
// X86: [[ATOMIC_OP]]:
// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
-// X86-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000
+// X86-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], -1.000000e+00
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
@@ -376,7 +376,7 @@ long double test_volatile_dec(volatile _Atomic long double *addr) {
// X64-NEXT: br label %[[ATOMIC_OP:.*]]
// X64: [[ATOMIC_OP]]:
// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
-// X64-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 0xK4003C800000000000000
+// X64-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 2.500000e+01
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
@@ -411,7 +411,7 @@ long double test_volatile_dec(volatile _Atomic long double *addr) {
// X86-NEXT: br label %[[ATOMIC_OP:.*]]
// X86: [[ATOMIC_OP]]:
// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
-// X86-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 0xK4003C800000000000000
+// X86-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 2.500000e+01
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
@@ -439,7 +439,7 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) {
// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8
// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP]], i8 0, i64 16, i1 false)
-// X64-NEXT: store x86_fp80 0xK4005E600000000000000, ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: store x86_fp80 1.150000e+02, ptr [[ATOMIC_TEMP]], align 16
// X64-NEXT: [[TMP1:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 16
// X64-NEXT: store atomic volatile i128 [[TMP1]], ptr [[TMP0]] seq_cst, align 16
// X64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8
@@ -457,7 +457,7 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) {
// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4
// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP]], i8 0, i64 12, i1 false)
-// X86-NEXT: store x86_fp80 0xK4005E600000000000000, ptr [[ATOMIC_TEMP]], align 4
+// X86-NEXT: store x86_fp80 1.150000e+02, ptr [[ATOMIC_TEMP]], align 4
// X86-NEXT: call void @__atomic_store(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)
// X86-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4
// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP1]], i32 noundef 5)
@@ -483,7 +483,7 @@ long double test_volatile_assign(volatile _Atomic long double *addr) {
// X64-NEXT: br label %[[ATOMIC_OP:.*]]
// X64: [[ATOMIC_OP]]:
// X64-NEXT: [[TMP1:%.*]] = phi x86_fp80 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP7:%.*]], %[[ATOMIC_OP]] ]
-// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP1]], 0xK3FFF8000000000000000
+// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP1]], 1.000000e+00
// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
// X64-NEXT: store x86_fp80 [[TMP1]], ptr [[ATOMIC_TEMP1]], align 16
// X64-NEXT: [[TMP2:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
@@ -497,7 +497,7 @@ long double test_volatile_assign(volatile _Atomic long double *addr) {
// X64-NEXT: [[TMP7]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16
// X64-NEXT: br i1 [[TMP6]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
// X64: [[ATOMIC_CONT]]:
-// X64-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[INC]], 0xK3FFF8000000000000000
+// X64-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[INC]], 1.000000e+00
// X64-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
// X64-NEXT: ret i32 [[CONV]]
//
@@ -512,7 +512,7 @@ long double test_volatile_assign(volatile _Atomic long double *addr) {
// X86-NEXT: br label %[[ATOMIC_OP:.*]]
// X86: [[ATOMIC_OP]]:
// X86-NEXT: [[TMP1:%.*]] = phi x86_fp80 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP2:%.*]], %[[ATOMIC_OP]] ]
-// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP1]], 0xK3FFF8000000000000000
+// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP1]], 1.000000e+00
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
// X86-NEXT: store x86_fp80 [[TMP1]], ptr [[ATOMIC_TEMP1]], align 4
// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
@@ -521,7 +521,7 @@ long double test_volatile_assign(volatile _Atomic long double *addr) {
// X86-NEXT: [[TMP2]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4
// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
// X86: [[ATOMIC_CONT]]:
-// X86-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[INC]], 0xK3FFF8000000000000000
+// X86-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[INC]], 1.000000e+00
// X86-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
// X86-NEXT: ret i32 [[CONV]]
//
diff --git a/clang/test/CodeGen/X86/x86_64-longdouble.c b/clang/test/CodeGen/X86/x86_64-longdouble.c
index 5287640e4ed30..7bc543b08f1bc 100644
--- a/clang/test/CodeGen/X86/x86_64-longdouble.c
+++ b/clang/test/CodeGen/X86/x86_64-longdouble.c
@@ -8,12 +8,12 @@
// Android uses fp128 for long double but other x86_64 targets use x86_fp80.
long double dataLD = 1.0L;
-// ANDROID: @dataLD ={{.*}} local_unnamed_addr global fp128 0xL00000000000000003FFF000000000000, align 16
-// GNU: @dataLD ={{.*}} local_unnamed_addr global x86_fp80 0xK3FFF8000000000000000, align 16
+// ANDROID: @dataLD ={{.*}} local_unnamed_addr global fp128 1.000000e+00, align 16
+// GNU: @dataLD ={{.*}} local_unnamed_addr global x86_fp80 1.000000e+00, align 16
long double _Complex dataLDC = {1.0L, 1.0L};
-// ANDROID: @dataLDC ={{.*}} local_unnamed_addr global { fp128, fp128 } { fp128 0xL00000000000000003FFF000000000000, fp128 0xL00000000000000003FFF000000000000 }, align 16
-// GNU: @dataLDC ={{.*}} local_unnamed_addr global { x86_fp80, x86_fp80 } { x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000 }, align 16
+// ANDROID: @dataLDC ={{.*}} local_unnamed_addr global { fp128, fp128 } { fp128 1.000000e+00, fp128 1.000000e+00 }, align 16
+// GNU: @dataLDC ={{.*}} local_unnamed_addr global { x86_fp80, x86_fp80 } { x86_fp80 1.000000e+00, x86_fp80 1.000000e+00 }, align 16
long double TestLD(long double x) {
return x * x;
diff --git a/clang/test/CodeGen/attr-target-mv.c b/clang/test/CodeGen/attr-target-mv.c
index 4ab5d6f950ccd..68af3c7476b32 100644
--- a/clang/test/CodeGen/attr-target-mv.c
+++ b/clang/test/CodeGen/attr-target-mv.c
@@ -334,10 +334,10 @@ void calls_pr50025c(void) { pr50025c(); }
// WINDOWS: call void @foo_decls
// ITANIUM: define{{.*}} void @bar4()
-// ITANIUM: call void @foo_multi.ifunc(i32 noundef 1, double noundef 5.{{[0+e]*}})
+// ITANIUM: call void @foo_multi.ifunc(i32 noundef 1, double noundef 5.000000e+00{{[0+e]*}})
// WINDOWS: define dso_local void @bar4()
-// WINDOWS: call void @foo_multi.resolver(i32 noundef 1, double noundef 5.{{[0+e]*}})
+// WINDOWS: call void @foo_multi.resolver(i32 noundef 1, double noundef 5.000000e+00{{[0+e]*}})
// ITANIUM: define weak_odr ptr @foo_multi.resolver() #[[ATTR_RESOLVER]]
// LINUX-SAME: comdat
diff --git a/clang/test/CodeGen/builtin-nan-exception.c b/clang/test/CodeGen/builtin-nan-exception.c
index 7445411ddf89e..9b1cd2c75ae3c 100644
--- a/clang/test/CodeGen/builtin-nan-exception.c
+++ b/clang/test/CodeGen/builtin-nan-exception.c
@@ -8,7 +8,7 @@
// An SNaN with no payload is formed by setting the bit after the
// the quiet bit (MSB of the significand).
-// CHECK: float 0x7FF8000000000000, float 0x7FF4000000000000
+// CHECK: float +qnan, float +snan(0x200000)
float f[] = {
__builtin_nanf(""),
@@ -22,14 +22,14 @@ float f[] = {
// but that should not cause a compilation error in the default
// (ignore FP exceptions) mode.
-// CHECK: float 0x7FF8000000000000, float 0x7FFC000000000000
+// CHECK: float +qnan, float +nan(0x200000)
float converted_to_float[] = {
__builtin_nan(""),
__builtin_nans(""),
};
-// CHECK: double 0x7FF8000000000000, double 0x7FF4000000000000
+// CHECK: double +qnan, double +snan(0x4000000000000)
double d[] = {
__builtin_nan(""),
diff --git a/clang/test/CodeGen/builtin-nan-legacy.c b/clang/test/CodeGen/builtin-nan-legacy.c
index de6c15379a4dd..bc0a6ae6dd77a 100644
--- a/clang/test/CodeGen/builtin-nan-legacy.c
+++ b/clang/test/CodeGen/builtin-nan-legacy.c
@@ -1,6 +1,6 @@
// RUN: %clang -target mipsel-unknown-linux -mnan=legacy -emit-llvm -S %s -o - | FileCheck %s
-// CHECK: float 0x7FFC000000000000, float 0x7FF8000000000000
-// CHECK: double 0x7FF4000000000000, double 0x7FF8000000000000
+// CHECK: float +nan(0x200000), float +qnan
+// CHECK: double +snan(0x4000000000000), double +qnan
// The first line shows an unintended consequence.
// __builtin_nan() creates a legacy QNAN double with an empty payload
diff --git a/clang/test/CodeGen/builtin_Float16.c b/clang/test/CodeGen/builtin_Float16.c
index 099d2ad5697e3..86c342e91e89c 100644
--- a/clang/test/CodeGen/builtin_Float16.c
+++ b/clang/test/CodeGen/builtin_Float16.c
@@ -6,12 +6,12 @@
void test_float16_builtins(void) {
volatile _Float16 res;
- // CHECK: store volatile half 0xH7C00, ptr %res, align 2
+ // CHECK: store volatile half +inf, ptr %res, align 2
res = __builtin_huge_valf16();
- // CHECK: store volatile half 0xH7C00, ptr %res, align 2
+ // CHECK: store volatile half +inf, ptr %res, align 2
res = __builtin_inff16();
- // CHECK: store volatile half 0xH7E00, ptr %res, align 2
+ // CHECK: store volatile half +qnan, ptr %res, align 2
res = __builtin_nanf16("");
- // CHECK: store volatile half 0xH7D00, ptr %res, align 2
+ // CHECK: store volatile half +snan(0x100), ptr %res, align 2
res = __builtin_nansf16("");
}
diff --git a/clang/test/CodeGen/builtins-elementwise-math.c b/clang/test/CodeGen/builtins-elementwise-math.c
index 2df485f0155c3..ff6338a8b85e7 100644
--- a/clang/test/CodeGen/builtins-elementwise-math.c
+++ b/clang/test/CodeGen/builtins-elementwise-math.c
@@ -1206,7 +1206,7 @@ void test_builtin_elementwise_fma(float f32, double f64,
// CHECK: [[V2F16_0:%.+]] = load <2 x half>, ptr %v2f16.addr
// CHECK-NEXT: [[V2F16_1:%.+]] = load <2 x half>, ptr %v2f16.addr
- // CHECK-NEXT: call <2 x half> @llvm.fma.v2f16(<2 x half> [[V2F16_0]], <2 x half> [[V2F16_1]], <2 x half> splat (half 0xH4400))
+ // CHECK-NEXT: call <2 x half> @llvm.fma.v2f16(<2 x half> [[V2F16_0]], <2 x half> [[V2F16_1]], <2 x half> splat (half 4.000000e+00))
half2 tmp2_v2f16 = __builtin_elementwise_fma(v2f16, v2f16, (half2)4.0);
}
diff --git a/clang/test/CodeGen/builtins-nvptx.c b/clang/test/CodeGen/builtins-nvptx.c
index f1b41ba557426..86907f8452fa1 100644
--- a/clang/test/CodeGen/builtins-nvptx.c
+++ b/clang/test/CodeGen/builtins-nvptx.c
@@ -1121,13 +1121,13 @@ __device__ void nvvm_cvt_sm89() {
// CHECK_PTX81_SM89: call i16 @llvm.nvvm.ff.to.e5m2x2.rn.relu(float 1.000000e+00, float 1.000000e+00)
__nvvm_ff_to_e5m2x2_rn_relu(1.0f, 1.0f);
- // CHECK_PTX81_SM89: call i16 @llvm.nvvm.f16x2.to.e4m3x2.rn(<2 x half> splat (half 0xH3C00))
+ // CHECK_PTX81_SM89: call i16 @llvm.nvvm.f16x2.to.e4m3x2.rn(<2 x half> splat (half 1.000000e+00))
__nvvm_f16x2_to_e4m3x2_rn({1.0f16, 1.0f16});
- // CHECK_PTX81_SM89: call i16 @llvm.nvvm.f16x2.to.e4m3x2.rn.relu(<2 x half> splat (half 0xH3C00))
+ // CHECK_PTX81_SM89: call i16 @llvm.nvvm.f16x2.to.e4m3x2.rn.relu(<2 x half> splat (half 1.000000e+00))
__nvvm_f16x2_to_e4m3x2_rn_relu({1.0f16, 1.0f16});
- // CHECK_PTX81_SM89: call i16 @llvm.nvvm.f16x2.to.e5m2x2.rn(<2 x half> splat (half 0xH3C00))
+ // CHECK_PTX81_SM89: call i16 @llvm.nvvm.f16x2.to.e5m2x2.rn(<2 x half> splat (half 1.000000e+00))
__nvvm_f16x2_to_e5m2x2_rn({1.0f16, 1.0f16});
- // CHECK_PTX81_SM89: call i16 @llvm.nvvm.f16x2.to.e5m2x2.rn.relu(<2 x half> splat (half 0xH3C00))
+ // CHECK_PTX81_SM89: call i16 @llvm.nvvm.f16x2.to.e5m2x2.rn.relu(<2 x half> splat (half 1.000000e+00))
__nvvm_f16x2_to_e5m2x2_rn_relu({1.0f16, 1.0f16});
// CHECK_PTX81_SM89: call <2 x half> @llvm.nvvm.e4m3x2.to.f16x2.rn(i16 18504)
@@ -1257,24 +1257,24 @@ __device__ void nvvm_cvt_sm100a_sm101a_sm120a() {
// CHECK_PTX86_SM120a: call i16 @llvm.nvvm.ff.to.ue8m0x2.rp.satfinite(float 1.000000e+00, float 1.000000e+00)
__nvvm_ff_to_ue8m0x2_rp_satfinite(1.0f, 1.0f);
- // CHECK_PTX86_SM100a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> splat (bfloat 0xR3DCD)
- // CHECK_PTX86_SM101a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> splat (bfloat 0xR3DCD)
- // CHECK_PTX86_SM120a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> splat (bfloat 0xR3DCD)
+ // CHECK_PTX86_SM100a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> splat (bfloat 1.000980e-01)
+ // CHECK_PTX86_SM101a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> splat (bfloat 1.000980e-01)
+ // CHECK_PTX86_SM120a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> splat (bfloat 1.000980e-01)
__nvvm_bf16x2_to_ue8m0x2_rz({(__bf16)0.1f, (__bf16)0.1f});
- // CHECK_PTX86_SM100a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite(<2 x bfloat> splat (bfloat 0xR3DCD)
- // CHECK_PTX86_SM101a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite(<2 x bfloat> splat (bfloat 0xR3DCD)
- // CHECK_PTX86_SM120a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite(<2 x bfloat> splat (bfloat 0xR3DCD)
+ // CHECK_PTX86_SM100a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite(<2 x bfloat> splat (bfloat 1.000980e-01)
+ // CHECK_PTX86_SM101a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite(<2 x bfloat> splat (bfloat 1.000980e-01)
+ // CHECK_PTX86_SM120a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite(<2 x bfloat> splat (bfloat 1.000980e-01)
__nvvm_bf16x2_to_ue8m0x2_rz_satfinite({(__bf16)0.1f, (__bf16)0.1f});
- // CHECK_PTX86_SM100a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp(<2 x bfloat> splat (bfloat 0xR3DCD)
- // CHECK_PTX86_SM101a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp(<2 x bfloat> splat (bfloat 0xR3DCD)
- // CHECK_PTX86_SM120a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp(<2 x bfloat> splat (bfloat 0xR3DCD)
+ // CHECK_PTX86_SM100a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp(<2 x bfloat> splat (bfloat 1.000980e-01)
+ // CHECK_PTX86_SM101a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp(<2 x bfloat> splat (bfloat 1.000980e-01)
+ // CHECK_PTX86_SM120a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp(<2 x bfloat> splat (bfloat 1.000980e-01)
__nvvm_bf16x2_to_ue8m0x2_rp({(__bf16)0.1f, (__bf16)0.1f});
- // CHECK_PTX86_SM100a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> splat (bfloat 0xR3DCD)
- // CHECK_PTX86_SM101a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> splat (bfloat 0xR3DCD)
- // CHECK_PTX86_SM120a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> splat (bfloat 0xR3DCD)
+ // CHECK_PTX86_SM100a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> splat (bfloat 1.000980e-01)
+ // CHECK_PTX86_SM101a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> splat (bfloat 1.000980e-01)
+ // CHECK_PTX86_SM120a: call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> splat (bfloat 1.000980e-01)
__nvvm_bf16x2_to_ue8m0x2_rp_satfinite({(__bf16)0.1f, (__bf16)0.1f});
// CHECK_PTX86_SM100a: call <2 x bfloat> @llvm.nvvm.ue8m0x2.to.bf16x2(i16 19532)
@@ -1416,14 +1416,14 @@ __device__ void nvvm_cvt_sm100a_sm103a() {
__device__ void nvvm_abs_neg_bf16_bf16x2_sm80() {
#if __CUDA_ARCH__ >= 800
- // CHECK_PTX70_SM80: call bfloat @llvm.nvvm.fabs.bf16(bfloat 0xR3DCD)
+ // CHECK_PTX70_SM80: call bfloat @llvm.nvvm.fabs.bf16(bfloat 1.000980e-01)
__nvvm_abs_bf16(BF16);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fabs.v2bf16(<2 x bfloat> splat (bfloat 0xR3DCD))
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fabs.v2bf16(<2 x bfloat> splat (bfloat 1.000980e-01))
__nvvm_abs_bf16x2(BF16X2);
- // CHECK_PTX70_SM80: call bfloat @llvm.nvvm.neg.bf16(bfloat 0xR3DCD)
+ // CHECK_PTX70_SM80: call bfloat @llvm.nvvm.neg.bf16(bfloat 1.000980e-01)
__nvvm_neg_bf16(BF16);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.neg.bf16x2(<2 x bfloat> splat (bfloat 0xR3DCD))
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.neg.bf16x2(<2 x bfloat> splat (bfloat 1.000980e-01))
__nvvm_neg_bf16x2(BF16X2);
#endif
// CHECK: ret void
diff --git a/clang/test/CodeGen/builtins-reduction-math.c b/clang/test/CodeGen/builtins-reduction-math.c
index 187f42068905a..2e9c7b66ee095 100644
--- a/clang/test/CodeGen/builtins-reduction-math.c
+++ b/clang/test/CodeGen/builtins-reduction-math.c
@@ -176,11 +176,11 @@ void test_builtin_reduce_addf(float4 vf1, half8 vf2, float start) {
float r2 = __builtin_reduce_in_order_fadd(vf1, 2.0f);
// CHECK: [[V2:%.+]] = load <8 x half>, ptr %vf2.addr, align 16
- // CHECK-NEXT: call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0xH8000, <8 x half> [[V2:%.+]])
+ // CHECK-NEXT: call reassoc half @llvm.vector.reduce.fadd.v8f16(half -0.000000e+00, <8 x half> [[V2:%.+]])
_Float16 r3 = __builtin_reduce_assoc_fadd(vf2);
// CHECK: [[V3:%.+]] = load <8 x half>, ptr %vf2.addr, align 16
- // CHECK-NEXT: [[RDX:%.+]] = call half @llvm.vector.reduce.fadd.v8f16(half 0xH8000, <8 x half> [[V3]])
+ // CHECK-NEXT: [[RDX:%.+]] = call half @llvm.vector.reduce.fadd.v8f16(half -0.000000e+00, <8 x half> [[V3]])
// CHECK-NEXT: fpext half [[RDX]] to float
float r4 = __builtin_reduce_in_order_fadd(vf2, -0.0f);
diff --git a/clang/test/CodeGen/captured-statements.c b/clang/test/CodeGen/captured-statements.c
index ef0812a29341d..b4562785ffb89 100644
--- a/clang/test/CodeGen/captured-statements.c
+++ b/clang/test/CodeGen/captured-statements.c
@@ -19,7 +19,7 @@ void test1(void) {
i++;
}
// CHECK-1: %struct.anon = type { ptr }
- // CHECK-1: {{.+}} global float 3.0
+ // CHECK-1: {{.+}} global float 3.000000e+00
//
// CHECK-1: @test1(
// CHECK-1: alloca %struct.anon
diff --git a/clang/test/CodeGen/complex-init-list.c b/clang/test/CodeGen/complex-init-list.c
index 262b44d213b3f..957dff02f658c 100644
--- a/clang/test/CodeGen/complex-init-list.c
+++ b/clang/test/CodeGen/complex-init-list.c
@@ -5,7 +5,7 @@
// extensive description and test in test/Sema/complex-init-list.c.)
_Complex float x = { 1.0f, 1.0f/0.0f };
-// CHECK: @x ={{.*}} global { float, float } { float 1.000000e+00, float 0x7FF0000000000000 }, align 4
+// CHECK: @x ={{.*}} global { float, float } { float 1.000000e+00, float +inf }, align 4
_Complex float f(float x, float y) { _Complex float z = { x, y }; return z; }
// CHECK-LABEL: define{{.*}} <2 x float> @f
diff --git a/clang/test/CodeGen/complex_Float16.c b/clang/test/CodeGen/complex_Float16.c
index d2552074bc7cd..08e5053b7bf70 100644
--- a/clang/test/CodeGen/complex_Float16.c
+++ b/clang/test/CodeGen/complex_Float16.c
@@ -6,7 +6,7 @@
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[RETVAL:%.*]] = alloca { half, half }, align 2
// CHECK-NEXT: [[A:%.*]] = alloca half, align 2
-// CHECK-NEXT: store half 0xH0000, ptr [[A]], align 2
+// CHECK-NEXT: store half 0.000000e+00, ptr [[A]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[A]], align 2
// CHECK-NEXT: [[RETVAL_REALP:%.*]] = getelementptr inbounds nuw { half, half }, ptr [[RETVAL]], i32 0, i32 0
diff --git a/clang/test/CodeGen/conditional.c b/clang/test/CodeGen/conditional.c
index 70c87848b6c1e..ec1be2d327687 100644
--- a/clang/test/CodeGen/conditional.c
+++ b/clang/test/CodeGen/conditional.c
@@ -62,7 +62,7 @@ int test11(int c) {
}
// CHECK: @test12
-// CHECK: select i1 {{.*}}, double 4.0{{.*}}, double 2.0
+// CHECK: select i1 {{.*}}, double 4.000000e+00{{.*}}, double 2.000000e+00
double test12(int c) {
return c ? 4.0 : 2.0;
}
diff --git a/clang/test/CodeGen/constexpr-c23-internal-linkage.c b/clang/test/CodeGen/constexpr-c23-internal-linkage.c
index 1236062272a2d..2ccf627800b5c 100644
--- a/clang/test/CodeGen/constexpr-c23-internal-linkage.c
+++ b/clang/test/CodeGen/constexpr-c23-internal-linkage.c
@@ -13,6 +13,6 @@ const float *p_f = &var_float;
/*
CHECK: @var_int = internal constant i32 1{{.*}}
CHECK: @var_char = internal constant i8 97{{.*}}
-CHECK: @var_float = internal constant float 2.5{{.*}}
+CHECK: @var_float = internal constant float 2.500000e+00{{.*}}
*/
diff --git a/clang/test/CodeGen/cx-complex-range-real.c b/clang/test/CodeGen/cx-complex-range-real.c
index 06786d376f0fb..d3fb4f2a5cc53 100644
--- a/clang/test/CodeGen/cx-complex-range-real.c
+++ b/clang/test/CodeGen/cx-complex-range-real.c
@@ -381,12 +381,12 @@ _Complex double divd(_Complex double a, double b) {
// PRMTD-NEXT: [[EXT1:%.*]] = fpext double [[B_COERCE0]] to x86_fp80
// PRMTD-NEXT: [[EXT2:%.*]] = fpext double [[B_COERCE1]] to x86_fp80
// PRMTD-NEXT: [[TMP0:%.*]] = fmul x86_fp80 [[EXT]], [[EXT1]]
-// PRMTD-NEXT: [[TMP1:%.*]] = fmul x86_fp80 0xK00000000000000000000, [[EXT2]]
+// PRMTD-NEXT: [[TMP1:%.*]] = fmul x86_fp80 0.000000e+00, [[EXT2]]
// PRMTD-NEXT: [[TMP2:%.*]] = fadd x86_fp80 [[TMP0]], [[TMP1]]
// PRMTD-NEXT: [[TMP3:%.*]] = fmul x86_fp80 [[EXT1]], [[EXT1]]
// PRMTD-NEXT: [[TMP4:%.*]] = fmul x86_fp80 [[EXT2]], [[EXT2]]
// PRMTD-NEXT: [[TMP5:%.*]] = fadd x86_fp80 [[TMP3]], [[TMP4]]
-// PRMTD-NEXT: [[TMP6:%.*]] = fmul x86_fp80 0xK00000000000000000000, [[EXT1]]
+// PRMTD-NEXT: [[TMP6:%.*]] = fmul x86_fp80 0.000000e+00, [[EXT1]]
// PRMTD-NEXT: [[TMP7:%.*]] = fmul x86_fp80 [[EXT]], [[EXT2]]
// PRMTD-NEXT: [[TMP8:%.*]] = fsub x86_fp80 [[TMP6]], [[TMP7]]
// PRMTD-NEXT: [[TMP9:%.*]] = fdiv x86_fp80 [[TMP2]], [[TMP5]]
@@ -406,12 +406,12 @@ _Complex double divd(_Complex double a, double b) {
// PRMTD_STRICT-NEXT: [[EXT1:%.*]] = call x86_fp80 @llvm.experimental.constrained.fpext.f80.f64(double [[B_COERCE0]], metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[EXT2:%.*]] = call x86_fp80 @llvm.experimental.constrained.fpext.f80.f64(double [[B_COERCE1]], metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.experimental.constrained.fmul.f80(x86_fp80 [[EXT]], x86_fp80 [[EXT1]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
-// PRMTD_STRICT-NEXT: [[TMP1:%.*]] = call x86_fp80 @llvm.experimental.constrained.fmul.f80(x86_fp80 0xK00000000000000000000, x86_fp80 [[EXT2]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
+// PRMTD_STRICT-NEXT: [[TMP1:%.*]] = call x86_fp80 @llvm.experimental.constrained.fmul.f80(x86_fp80 0.000000e+00, x86_fp80 [[EXT2]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[TMP2:%.*]] = call x86_fp80 @llvm.experimental.constrained.fadd.f80(x86_fp80 [[TMP0]], x86_fp80 [[TMP1]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[TMP3:%.*]] = call x86_fp80 @llvm.experimental.constrained.fmul.f80(x86_fp80 [[EXT1]], x86_fp80 [[EXT1]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[TMP4:%.*]] = call x86_fp80 @llvm.experimental.constrained.fmul.f80(x86_fp80 [[EXT2]], x86_fp80 [[EXT2]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[TMP5:%.*]] = call x86_fp80 @llvm.experimental.constrained.fadd.f80(x86_fp80 [[TMP3]], x86_fp80 [[TMP4]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
-// PRMTD_STRICT-NEXT: [[TMP6:%.*]] = call x86_fp80 @llvm.experimental.constrained.fmul.f80(x86_fp80 0xK00000000000000000000, x86_fp80 [[EXT1]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
+// PRMTD_STRICT-NEXT: [[TMP6:%.*]] = call x86_fp80 @llvm.experimental.constrained.fmul.f80(x86_fp80 0.000000e+00, x86_fp80 [[EXT1]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[TMP7:%.*]] = call x86_fp80 @llvm.experimental.constrained.fmul.f80(x86_fp80 [[EXT]], x86_fp80 [[EXT2]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[TMP8:%.*]] = call x86_fp80 @llvm.experimental.constrained.fsub.f80(x86_fp80 [[TMP6]], x86_fp80 [[TMP7]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
// PRMTD_STRICT-NEXT: [[TMP9:%.*]] = call x86_fp80 @llvm.experimental.constrained.fdiv.f80(x86_fp80 [[TMP2]], x86_fp80 [[TMP5]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
diff --git a/clang/test/CodeGen/ext-vector.c b/clang/test/CodeGen/ext-vector.c
index db8baf054ac7b..d41c4b296ecae 100644
--- a/clang/test/CodeGen/ext-vector.c
+++ b/clang/test/CodeGen/ext-vector.c
@@ -8,7 +8,7 @@ typedef __attribute__(( ext_vector_type(4) )) unsigned int uint4;
// CHECK: @foo = {{(dso_local )?}}global <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
float4 foo = (float4){ 1.0, 2.0, 3.0, 4.0 };
-// CHECK: @bar = {{(dso_local )?}}constant <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 0x7FF0000000000000>
+// CHECK: @bar = {{(dso_local )?}}constant <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float +inf>
const float4 bar = (float4){ 1.0, 2.0, 3.0, __builtin_inff() };
// CHECK: @test1
diff --git a/clang/test/CodeGen/fp-floatcontrol-pragma.cpp b/clang/test/CodeGen/fp-floatcontrol-pragma.cpp
index 966eaf6053970..53bc3191d2f96 100644
--- a/clang/test/CodeGen/fp-floatcontrol-pragma.cpp
+++ b/clang/test/CodeGen/fp-floatcontrol-pragma.cpp
@@ -200,7 +200,7 @@ float myAdd(int i, float f) {
return 1.0 + 2.0;
// Check that floating point constant folding doesn't occur if
// #pragma STC FENV_ACCESS is enabled.
- //CHECK-FENV: llvm.experimental.constrained.fadd{{.*}}double 1.0{{.*}}double 2.0{{.*}}
+ //CHECK-FENV: llvm.experimental.constrained.fadd{{.*}}double 1.000000e+00{{.*}}double 2.000000e+00{{.*}}
//CHECK: store float 3.0{{.*}}retval{{.*}}
static double v = 1.0 / 3.0;
//CHECK-FENV: llvm.experimental.constrained.fptrunc.f32.f64{{.*}}
diff --git a/clang/test/CodeGen/fp16-ops-strictfp.c b/clang/test/CodeGen/fp16-ops-strictfp.c
index 830be6256456e..96e6d72551acb 100644
--- a/clang/test/CodeGen/fp16-ops-strictfp.c
+++ b/clang/test/CodeGen/fp16-ops-strictfp.c
@@ -39,7 +39,7 @@ void foo(void) {
// CHECK: store {{.*}} half {{.*}}, ptr
h0 = (test);
- // NATIVE-HALF: call i1 @llvm.experimental.constrained.fcmp.f16(half %{{.*}}, half 0xH0000, metadata !"une", metadata !"fpexcept.strict")
+ // NATIVE-HALF: call i1 @llvm.experimental.constrained.fcmp.f16(half %{{.*}}, half 0.000000e+00, metadata !"une", metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fpext.f32.f16(half %{{.*}}, metadata !"fpexcept.strict")
// NOTNATIVE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float 0.000000e+00, metadata !"une", metadata !"fpexcept.strict")
// CHECK: store {{.*}} i32 {{.*}}, ptr
@@ -59,28 +59,28 @@ void foo(void) {
// NOTNATIVE: store {{.*}} half {{.*}}, ptr
h1 = +h1;
- // NATIVE-HALF: call half @llvm.experimental.constrained.fadd.f16(half %{{.*}}, half 0xH3C00, metadata !"round.tonearest", metadata !"fpexcept.strict")
+ // NATIVE-HALF: call half @llvm.experimental.constrained.fadd.f16(half %{{.*}}, half 1.000000e+00, metadata !"round.tonearest", metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fpext.f32.f16(half %{{.*}}, metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fadd.f32(float %{{.*}}, float {{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
// NOTNATIVE: call half @llvm.experimental.constrained.fptrunc.f16.f32(float %{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
// CHECK: store {{.*}} half {{.*}}, ptr
h1++;
- // NATIVE-HALF: call half @llvm.experimental.constrained.fadd.f16(half %{{.*}}, half 0xH3C00, metadata !"round.tonearest", metadata !"fpexcept.strict")
+ // NATIVE-HALF: call half @llvm.experimental.constrained.fadd.f16(half %{{.*}}, half 1.000000e+00, metadata !"round.tonearest", metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fpext.f32.f16(half %{{.*}}, metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fadd.f32(float %{{.*}}, float {{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
// NOTNATIVE: call half @llvm.experimental.constrained.fptrunc.f16.f32(float %{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
// CHECK: store {{.*}} half {{.*}}, ptr
++h1;
- // NATIVE-HALF: call half @llvm.experimental.constrained.fadd.f16(half %{{.*}}, half 0xHBC00, metadata !"round.tonearest", metadata !"fpexcept.strict")
+ // NATIVE-HALF: call half @llvm.experimental.constrained.fadd.f16(half %{{.*}}, half -1.000000e+00, metadata !"round.tonearest", metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fpext.f32.f16(half %{{.*}}, metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fadd.f32(float %{{.*}}, float {{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
// NOTNATIVE: call half @llvm.experimental.constrained.fptrunc.f16.f32(float %{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
// CHECK: store {{.*}} half {{.*}}, ptr
--h1;
- // NATIVE-HALF: call half @llvm.experimental.constrained.fadd.f16(half %{{.*}}, half 0xHBC00, metadata !"round.tonearest", metadata !"fpexcept.strict")
+ // NATIVE-HALF: call half @llvm.experimental.constrained.fadd.f16(half %{{.*}}, half -1.000000e+00, metadata !"round.tonearest", metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fpext.f32.f16(half %{{.*}}, metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fadd.f32(float %{{.*}}, float {{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
// NOTNATIVE: call half @llvm.experimental.constrained.fptrunc.f16.f32(float %{{.*}}, metadata !"round.tonearest", metadata !"fpexcept.strict")
@@ -491,7 +491,7 @@ void foo(void) {
// CHECK: store {{.*}} i32 {{.*}}, ptr
test = (h0 != i0);
- // NATIVE-HALF: call i1 @llvm.experimental.constrained.fcmp.f16(half %{{.*}}, half 0xH0000, metadata !"une", metadata !"fpexcept.strict")
+ // NATIVE-HALF: call i1 @llvm.experimental.constrained.fcmp.f16(half %{{.*}}, half 0.000000e+00, metadata !"une", metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fpext.f32.f16(half %{{.*}}, metadata !"fpexcept.strict")
// NOTNATIVE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float {{.*}}, metadata !"une", metadata !"fpexcept.strict")
// NOTNATIVE: call float @llvm.experimental.constrained.fpext.f32.f16(half %{{.*}}, metadata !"fpexcept.strict")
diff --git a/clang/test/CodeGen/fp16-ops.c b/clang/test/CodeGen/fp16-ops.c
index 4c206690a7518..cead681d8eab6 100644
--- a/clang/test/CodeGen/fp16-ops.c
+++ b/clang/test/CodeGen/fp16-ops.c
@@ -355,12 +355,12 @@ void foo(void) {
// CHECK: [[F16TOF32]]
// CHECK: [[F16TOF32]]
// CHECK: [[F32TOF16]]
- // NATIVE-HALF: fcmp une half {{.*}}, 0xH0000
+ // NATIVE-HALF: fcmp une half {{.*}}, 0.000000e+00
h1 = (h1 ? h2 : h0);
// Check assignments (inc. compound)
h0 = h1;
- // NOTNATIVE: store {{.*}} half 0xHC000
- // NATIVE-HALF: store {{.*}} half 0xHC000
+ // NOTNATIVE: store {{.*}} half -2.000000e+00
+ // NATIVE-HALF: store {{.*}} half -2.000000e+00
h0 = (__fp16)-2.0f;
// CHECK: [[F32TOF16]]
// NATIVE-HALF: fptrunc float
diff --git a/clang/test/CodeGen/isfpclass.c b/clang/test/CodeGen/isfpclass.c
index 4c6d556e008e5..68ad4fd0e2fb7 100644
--- a/clang/test/CodeGen/isfpclass.c
+++ b/clang/test/CodeGen/isfpclass.c
@@ -5,7 +5,7 @@
// CHECK-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-// CHECK-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], 0x7FF0000000000000
+// CHECK-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], +inf
// CHECK-NEXT: ret i1 [[TMP1]]
//
_Bool check_isfpclass_finite(float x) {
@@ -68,7 +68,7 @@ _Bool check_isfpclass_snan_f64_strict(double x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isfpclass_zero_f16(
// CHECK-SAME: half noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = fcmp oeq half [[X]], 0xH0000
+// CHECK-NEXT: [[TMP0:%.*]] = fcmp oeq half [[X]], 0.000000e+00
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isfpclass_zero_f16(_Float16 x) {
diff --git a/clang/test/CodeGen/logb_scalbn.c b/clang/test/CodeGen/logb_scalbn.c
index 52c52bcb292be..3210bf5c9077b 100644
--- a/clang/test/CodeGen/logb_scalbn.c
+++ b/clang/test/CodeGen/logb_scalbn.c
@@ -15,14 +15,14 @@
// DEFAULT-NEXT: [[ENTRY:.*:]]
// DEFAULT-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// DEFAULT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// DEFAULT-NEXT: [[TMP0:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float 0x40301999A0000000)
+// DEFAULT-NEXT: [[TMP0:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float 1.610000e+01)
// DEFAULT-NEXT: [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
// DEFAULT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// DEFAULT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
-// DEFAULT-NEXT: [[TMP4:%.*]] = call float @llvm.fabs.f32(float 0x40301999A0000000)
-// DEFAULT-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP4:%.*]] = call float @llvm.fabs.f32(float 1.610000e+01)
+// DEFAULT-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], +inf
// DEFAULT-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
-// DEFAULT-NEXT: [[TMP7:%.*]] = select i1 false, float 0xFFF0000000000000, float [[TMP6]]
+// DEFAULT-NEXT: [[TMP7:%.*]] = select i1 false, float -inf, float [[TMP6]]
// DEFAULT-NEXT: store float [[TMP7]], ptr [[D1_ASCAST]], align 4
// DEFAULT-NEXT: ret void
//
@@ -31,14 +31,14 @@
// IGNORE-NEXT: [[ENTRY:.*:]]
// IGNORE-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// IGNORE-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// IGNORE-NEXT: [[TMP0:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float 0x40301999A0000000)
+// IGNORE-NEXT: [[TMP0:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float 1.610000e+01)
// IGNORE-NEXT: [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
// IGNORE-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// IGNORE-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
-// IGNORE-NEXT: [[TMP4:%.*]] = call float @llvm.fabs.f32(float 0x40301999A0000000)
-// IGNORE-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], 0x7FF0000000000000
+// IGNORE-NEXT: [[TMP4:%.*]] = call float @llvm.fabs.f32(float 1.610000e+01)
+// IGNORE-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], +inf
// IGNORE-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
-// IGNORE-NEXT: [[TMP7:%.*]] = select i1 false, float 0xFFF0000000000000, float [[TMP6]]
+// IGNORE-NEXT: [[TMP7:%.*]] = select i1 false, float -inf, float [[TMP6]]
// IGNORE-NEXT: store float [[TMP7]], ptr [[D1_ASCAST]], align 4
// IGNORE-NEXT: ret void
//
@@ -47,14 +47,14 @@
// STRICT-NEXT: [[ENTRY:.*:]]
// STRICT-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// STRICT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// STRICT-NEXT: [[TMP0:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float 0x40301999A0000000)
+// STRICT-NEXT: [[TMP0:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float 1.610000e+01)
// STRICT-NEXT: [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
// STRICT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// STRICT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
-// STRICT-NEXT: [[TMP4:%.*]] = call float @llvm.fabs.f32(float 0x40301999A0000000)
-// STRICT-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], 0x7FF0000000000000
+// STRICT-NEXT: [[TMP4:%.*]] = call float @llvm.fabs.f32(float 1.610000e+01)
+// STRICT-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], +inf
// STRICT-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
-// STRICT-NEXT: [[TMP7:%.*]] = select i1 false, float 0xFFF0000000000000, float [[TMP6]]
+// STRICT-NEXT: [[TMP7:%.*]] = select i1 false, float -inf, float [[TMP6]]
// STRICT-NEXT: store float [[TMP7]], ptr [[D1_ASCAST]], align 4
// STRICT-NEXT: ret void
//
@@ -63,14 +63,14 @@
// MAYTRAP-NEXT: [[ENTRY:.*:]]
// MAYTRAP-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// MAYTRAP-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// MAYTRAP-NEXT: [[TMP0:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float 0x40301999A0000000)
+// MAYTRAP-NEXT: [[TMP0:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float 1.610000e+01)
// MAYTRAP-NEXT: [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
// MAYTRAP-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// MAYTRAP-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
-// MAYTRAP-NEXT: [[TMP4:%.*]] = call float @llvm.fabs.f32(float 0x40301999A0000000)
-// MAYTRAP-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], 0x7FF0000000000000
+// MAYTRAP-NEXT: [[TMP4:%.*]] = call float @llvm.fabs.f32(float 1.610000e+01)
+// MAYTRAP-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], +inf
// MAYTRAP-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
-// MAYTRAP-NEXT: [[TMP7:%.*]] = select i1 false, float 0xFFF0000000000000, float [[TMP6]]
+// MAYTRAP-NEXT: [[TMP7:%.*]] = select i1 false, float -inf, float [[TMP6]]
// MAYTRAP-NEXT: store float [[TMP7]], ptr [[D1_ASCAST]], align 4
// MAYTRAP-NEXT: ret void
//
@@ -79,7 +79,7 @@
// ERRNO-NEXT: [[ENTRY:.*:]]
// ERRNO-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// ERRNO-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// ERRNO-NEXT: [[CALL:%.*]] = call float @logbf(float noundef 0x40301999A0000000) #[[ATTR2:[0-9]+]]
+// ERRNO-NEXT: [[CALL:%.*]] = call float @logbf(float noundef 1.610000e+01) #[[ATTR2:[0-9]+]]
// ERRNO-NEXT: store float [[CALL]], ptr [[D1_ASCAST]], align 4
// ERRNO-NEXT: ret void
//
@@ -88,14 +88,14 @@
// AMDGCNSPIRV-DEFAULT-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-DEFAULT-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-DEFAULT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP0:%.*]] = call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float 0x40301999A0000000)
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP0:%.*]] = call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float 1.610000e+01)
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP4:%.*]] = call addrspace(4) float @llvm.fabs.f32(float 0x40301999A0000000)
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP4:%.*]] = call addrspace(4) float @llvm.fabs.f32(float 1.610000e+01)
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], +inf
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP7:%.*]] = select i1 false, float 0xFFF0000000000000, float [[TMP6]]
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP7:%.*]] = select i1 false, float -inf, float [[TMP6]]
// AMDGCNSPIRV-DEFAULT-NEXT: store float [[TMP7]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-DEFAULT-NEXT: ret void
//
@@ -104,14 +104,14 @@
// AMDGCNSPIRV-IGNORE-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-IGNORE-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-IGNORE-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP0:%.*]] = call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float 0x40301999A0000000)
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP0:%.*]] = call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float 1.610000e+01)
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP4:%.*]] = call addrspace(4) float @llvm.fabs.f32(float 0x40301999A0000000)
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP4:%.*]] = call addrspace(4) float @llvm.fabs.f32(float 1.610000e+01)
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], +inf
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP7:%.*]] = select i1 false, float 0xFFF0000000000000, float [[TMP6]]
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP7:%.*]] = select i1 false, float -inf, float [[TMP6]]
// AMDGCNSPIRV-IGNORE-NEXT: store float [[TMP7]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-IGNORE-NEXT: ret void
//
@@ -120,14 +120,14 @@
// AMDGCNSPIRV-STRICT-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-STRICT-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-STRICT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP0:%.*]] = call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float 0x40301999A0000000)
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP0:%.*]] = call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float 1.610000e+01)
// AMDGCNSPIRV-STRICT-NEXT: [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
// AMDGCNSPIRV-STRICT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-STRICT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP4:%.*]] = call addrspace(4) float @llvm.fabs.f32(float 0x40301999A0000000)
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP4:%.*]] = call addrspace(4) float @llvm.fabs.f32(float 1.610000e+01)
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], +inf
// AMDGCNSPIRV-STRICT-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP7:%.*]] = select i1 false, float 0xFFF0000000000000, float [[TMP6]]
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP7:%.*]] = select i1 false, float -inf, float [[TMP6]]
// AMDGCNSPIRV-STRICT-NEXT: store float [[TMP7]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-STRICT-NEXT: ret void
//
@@ -136,14 +136,14 @@
// AMDGCNSPIRV-MAYTRAP-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-MAYTRAP-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-MAYTRAP-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP0:%.*]] = call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float 0x40301999A0000000)
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP0:%.*]] = call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float 1.610000e+01)
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP4:%.*]] = call addrspace(4) float @llvm.fabs.f32(float 0x40301999A0000000)
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP4:%.*]] = call addrspace(4) float @llvm.fabs.f32(float 1.610000e+01)
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP5:%.*]] = fcmp one float [[TMP4]], +inf
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP7:%.*]] = select i1 false, float 0xFFF0000000000000, float [[TMP6]]
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP7:%.*]] = select i1 false, float -inf, float [[TMP6]]
// AMDGCNSPIRV-MAYTRAP-NEXT: store float [[TMP7]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-MAYTRAP-NEXT: ret void
//
@@ -152,7 +152,7 @@
// AMDGCNSPIRV-ERRNO-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-ERRNO-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-ERRNO-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-ERRNO-NEXT: [[CALL:%.*]] = call spir_func addrspace(4) float @logbf(float noundef 0x40301999A0000000) #[[ATTR2:[0-9]+]]
+// AMDGCNSPIRV-ERRNO-NEXT: [[CALL:%.*]] = call spir_func addrspace(4) float @logbf(float noundef 1.610000e+01) #[[ATTR2:[0-9]+]]
// AMDGCNSPIRV-ERRNO-NEXT: store float [[CALL]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-ERRNO-NEXT: ret void
//
@@ -174,10 +174,10 @@ void test_logbf() {
// DEFAULT-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to float
// DEFAULT-NEXT: [[TMP5:%.*]] = load float, ptr [[A_ADDR_ASCAST]], align 4
// DEFAULT-NEXT: [[TMP6:%.*]] = call float @llvm.fabs.f32(float [[TMP5]])
-// DEFAULT-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], +inf
// DEFAULT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], float [[TMP4]], float [[TMP6]]
// DEFAULT-NEXT: [[TMP9:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
-// DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float 0xFFF0000000000000, float [[TMP8]]
+// DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float -inf, float [[TMP8]]
// DEFAULT-NEXT: store float [[TMP10]], ptr [[D1_ASCAST]], align 4
// DEFAULT-NEXT: ret void
//
@@ -196,10 +196,10 @@ void test_logbf() {
// IGNORE-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to float
// IGNORE-NEXT: [[TMP5:%.*]] = load float, ptr [[A_ADDR_ASCAST]], align 4
// IGNORE-NEXT: [[TMP6:%.*]] = call float @llvm.fabs.f32(float [[TMP5]])
-// IGNORE-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], 0x7FF0000000000000
+// IGNORE-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], +inf
// IGNORE-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], float [[TMP4]], float [[TMP6]]
// IGNORE-NEXT: [[TMP9:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
-// IGNORE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float 0xFFF0000000000000, float [[TMP8]]
+// IGNORE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float -inf, float [[TMP8]]
// IGNORE-NEXT: store float [[TMP10]], ptr [[D1_ASCAST]], align 4
// IGNORE-NEXT: ret void
//
@@ -218,10 +218,10 @@ void test_logbf() {
// STRICT-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to float
// STRICT-NEXT: [[TMP5:%.*]] = load float, ptr [[A_ADDR_ASCAST]], align 4
// STRICT-NEXT: [[TMP6:%.*]] = call float @llvm.fabs.f32(float [[TMP5]])
-// STRICT-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], 0x7FF0000000000000
+// STRICT-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], +inf
// STRICT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], float [[TMP4]], float [[TMP6]]
// STRICT-NEXT: [[TMP9:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
-// STRICT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float 0xFFF0000000000000, float [[TMP8]]
+// STRICT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float -inf, float [[TMP8]]
// STRICT-NEXT: store float [[TMP10]], ptr [[D1_ASCAST]], align 4
// STRICT-NEXT: ret void
//
@@ -240,10 +240,10 @@ void test_logbf() {
// MAYTRAP-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to float
// MAYTRAP-NEXT: [[TMP5:%.*]] = load float, ptr [[A_ADDR_ASCAST]], align 4
// MAYTRAP-NEXT: [[TMP6:%.*]] = call float @llvm.fabs.f32(float [[TMP5]])
-// MAYTRAP-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], 0x7FF0000000000000
+// MAYTRAP-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], +inf
// MAYTRAP-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], float [[TMP4]], float [[TMP6]]
// MAYTRAP-NEXT: [[TMP9:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
-// MAYTRAP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float 0xFFF0000000000000, float [[TMP8]]
+// MAYTRAP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float -inf, float [[TMP8]]
// MAYTRAP-NEXT: store float [[TMP10]], ptr [[D1_ASCAST]], align 4
// MAYTRAP-NEXT: ret void
//
@@ -275,10 +275,10 @@ void test_logbf() {
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to float
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP5:%.*]] = load float, ptr addrspace(4) [[A_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP6:%.*]] = call addrspace(4) float @llvm.fabs.f32(float [[TMP5]])
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], 0x7FF0000000000000
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], +inf
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], float [[TMP4]], float [[TMP6]]
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP9:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float 0xFFF0000000000000, float [[TMP8]]
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float -inf, float [[TMP8]]
// AMDGCNSPIRV-DEFAULT-NEXT: store float [[TMP10]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-DEFAULT-NEXT: ret void
//
@@ -297,10 +297,10 @@ void test_logbf() {
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to float
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP5:%.*]] = load float, ptr addrspace(4) [[A_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP6:%.*]] = call addrspace(4) float @llvm.fabs.f32(float [[TMP5]])
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], 0x7FF0000000000000
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], +inf
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], float [[TMP4]], float [[TMP6]]
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP9:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float 0xFFF0000000000000, float [[TMP8]]
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float -inf, float [[TMP8]]
// AMDGCNSPIRV-IGNORE-NEXT: store float [[TMP10]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-IGNORE-NEXT: ret void
//
@@ -319,10 +319,10 @@ void test_logbf() {
// AMDGCNSPIRV-STRICT-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to float
// AMDGCNSPIRV-STRICT-NEXT: [[TMP5:%.*]] = load float, ptr addrspace(4) [[A_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-STRICT-NEXT: [[TMP6:%.*]] = call addrspace(4) float @llvm.fabs.f32(float [[TMP5]])
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], 0x7FF0000000000000
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], +inf
// AMDGCNSPIRV-STRICT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], float [[TMP4]], float [[TMP6]]
// AMDGCNSPIRV-STRICT-NEXT: [[TMP9:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float 0xFFF0000000000000, float [[TMP8]]
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float -inf, float [[TMP8]]
// AMDGCNSPIRV-STRICT-NEXT: store float [[TMP10]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-STRICT-NEXT: ret void
//
@@ -341,10 +341,10 @@ void test_logbf() {
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to float
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP5:%.*]] = load float, ptr addrspace(4) [[A_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP6:%.*]] = call addrspace(4) float @llvm.fabs.f32(float [[TMP5]])
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], 0x7FF0000000000000
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP7:%.*]] = fcmp one float [[TMP6]], +inf
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], float [[TMP4]], float [[TMP6]]
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP9:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float 0xFFF0000000000000, float [[TMP8]]
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], float -inf, float [[TMP8]]
// AMDGCNSPIRV-MAYTRAP-NEXT: store float [[TMP10]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-MAYTRAP-NEXT: ret void
//
@@ -389,9 +389,9 @@ void test_logbf_var(float a) {
// DEFAULT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// DEFAULT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// DEFAULT-NEXT: [[TMP4:%.*]] = call double @llvm.fabs.f64(double 1.510000e+01)
-// DEFAULT-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], +inf
// DEFAULT-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
-// DEFAULT-NEXT: [[TMP7:%.*]] = select i1 false, double 0xFFF0000000000000, double [[TMP6]]
+// DEFAULT-NEXT: [[TMP7:%.*]] = select i1 false, double -inf, double [[TMP6]]
// DEFAULT-NEXT: store double [[TMP7]], ptr [[D1_ASCAST]], align 8
// DEFAULT-NEXT: ret void
//
@@ -405,9 +405,9 @@ void test_logbf_var(float a) {
// IGNORE-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// IGNORE-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// IGNORE-NEXT: [[TMP4:%.*]] = call double @llvm.fabs.f64(double 1.510000e+01)
-// IGNORE-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], 0x7FF0000000000000
+// IGNORE-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], +inf
// IGNORE-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
-// IGNORE-NEXT: [[TMP7:%.*]] = select i1 false, double 0xFFF0000000000000, double [[TMP6]]
+// IGNORE-NEXT: [[TMP7:%.*]] = select i1 false, double -inf, double [[TMP6]]
// IGNORE-NEXT: store double [[TMP7]], ptr [[D1_ASCAST]], align 8
// IGNORE-NEXT: ret void
//
@@ -421,9 +421,9 @@ void test_logbf_var(float a) {
// STRICT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// STRICT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// STRICT-NEXT: [[TMP4:%.*]] = call double @llvm.fabs.f64(double 1.510000e+01)
-// STRICT-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], 0x7FF0000000000000
+// STRICT-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], +inf
// STRICT-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
-// STRICT-NEXT: [[TMP7:%.*]] = select i1 false, double 0xFFF0000000000000, double [[TMP6]]
+// STRICT-NEXT: [[TMP7:%.*]] = select i1 false, double -inf, double [[TMP6]]
// STRICT-NEXT: store double [[TMP7]], ptr [[D1_ASCAST]], align 8
// STRICT-NEXT: ret void
//
@@ -437,9 +437,9 @@ void test_logbf_var(float a) {
// MAYTRAP-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// MAYTRAP-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// MAYTRAP-NEXT: [[TMP4:%.*]] = call double @llvm.fabs.f64(double 1.510000e+01)
-// MAYTRAP-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], 0x7FF0000000000000
+// MAYTRAP-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], +inf
// MAYTRAP-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
-// MAYTRAP-NEXT: [[TMP7:%.*]] = select i1 false, double 0xFFF0000000000000, double [[TMP6]]
+// MAYTRAP-NEXT: [[TMP7:%.*]] = select i1 false, double -inf, double [[TMP6]]
// MAYTRAP-NEXT: store double [[TMP7]], ptr [[D1_ASCAST]], align 8
// MAYTRAP-NEXT: ret void
//
@@ -462,9 +462,9 @@ void test_logbf_var(float a) {
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP4:%.*]] = call addrspace(4) double @llvm.fabs.f64(double 1.510000e+01)
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], +inf
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP7:%.*]] = select i1 false, double 0xFFF0000000000000, double [[TMP6]]
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP7:%.*]] = select i1 false, double -inf, double [[TMP6]]
// AMDGCNSPIRV-DEFAULT-NEXT: store double [[TMP7]], ptr addrspace(4) [[D1_ASCAST]], align 8
// AMDGCNSPIRV-DEFAULT-NEXT: ret void
//
@@ -478,9 +478,9 @@ void test_logbf_var(float a) {
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP4:%.*]] = call addrspace(4) double @llvm.fabs.f64(double 1.510000e+01)
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], +inf
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP7:%.*]] = select i1 false, double 0xFFF0000000000000, double [[TMP6]]
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP7:%.*]] = select i1 false, double -inf, double [[TMP6]]
// AMDGCNSPIRV-IGNORE-NEXT: store double [[TMP7]], ptr addrspace(4) [[D1_ASCAST]], align 8
// AMDGCNSPIRV-IGNORE-NEXT: ret void
//
@@ -494,9 +494,9 @@ void test_logbf_var(float a) {
// AMDGCNSPIRV-STRICT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-STRICT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// AMDGCNSPIRV-STRICT-NEXT: [[TMP4:%.*]] = call addrspace(4) double @llvm.fabs.f64(double 1.510000e+01)
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], +inf
// AMDGCNSPIRV-STRICT-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP7:%.*]] = select i1 false, double 0xFFF0000000000000, double [[TMP6]]
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP7:%.*]] = select i1 false, double -inf, double [[TMP6]]
// AMDGCNSPIRV-STRICT-NEXT: store double [[TMP7]], ptr addrspace(4) [[D1_ASCAST]], align 8
// AMDGCNSPIRV-STRICT-NEXT: ret void
//
@@ -510,9 +510,9 @@ void test_logbf_var(float a) {
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP4:%.*]] = call addrspace(4) double @llvm.fabs.f64(double 1.510000e+01)
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP5:%.*]] = fcmp one double [[TMP4]], +inf
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP7:%.*]] = select i1 false, double 0xFFF0000000000000, double [[TMP6]]
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP7:%.*]] = select i1 false, double -inf, double [[TMP6]]
// AMDGCNSPIRV-MAYTRAP-NEXT: store double [[TMP7]], ptr addrspace(4) [[D1_ASCAST]], align 8
// AMDGCNSPIRV-MAYTRAP-NEXT: ret void
//
@@ -564,10 +564,10 @@ void test_logb() {
// DEFAULT-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to double
// DEFAULT-NEXT: [[TMP5:%.*]] = load double, ptr [[A_ADDR_ASCAST]], align 8
// DEFAULT-NEXT: [[TMP6:%.*]] = call double @llvm.fabs.f64(double [[TMP5]])
-// DEFAULT-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], +inf
// DEFAULT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], double [[TMP4]], double [[TMP6]]
// DEFAULT-NEXT: [[TMP9:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
-// DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double 0xFFF0000000000000, double [[TMP8]]
+// DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double -inf, double [[TMP8]]
// DEFAULT-NEXT: store double [[TMP10]], ptr [[D1_ASCAST]], align 8
// DEFAULT-NEXT: ret void
//
@@ -586,10 +586,10 @@ void test_logb() {
// IGNORE-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to double
// IGNORE-NEXT: [[TMP5:%.*]] = load double, ptr [[A_ADDR_ASCAST]], align 8
// IGNORE-NEXT: [[TMP6:%.*]] = call double @llvm.fabs.f64(double [[TMP5]])
-// IGNORE-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], 0x7FF0000000000000
+// IGNORE-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], +inf
// IGNORE-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], double [[TMP4]], double [[TMP6]]
// IGNORE-NEXT: [[TMP9:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
-// IGNORE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double 0xFFF0000000000000, double [[TMP8]]
+// IGNORE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double -inf, double [[TMP8]]
// IGNORE-NEXT: store double [[TMP10]], ptr [[D1_ASCAST]], align 8
// IGNORE-NEXT: ret void
//
@@ -608,10 +608,10 @@ void test_logb() {
// STRICT-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to double
// STRICT-NEXT: [[TMP5:%.*]] = load double, ptr [[A_ADDR_ASCAST]], align 8
// STRICT-NEXT: [[TMP6:%.*]] = call double @llvm.fabs.f64(double [[TMP5]])
-// STRICT-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], 0x7FF0000000000000
+// STRICT-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], +inf
// STRICT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], double [[TMP4]], double [[TMP6]]
// STRICT-NEXT: [[TMP9:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
-// STRICT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double 0xFFF0000000000000, double [[TMP8]]
+// STRICT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double -inf, double [[TMP8]]
// STRICT-NEXT: store double [[TMP10]], ptr [[D1_ASCAST]], align 8
// STRICT-NEXT: ret void
//
@@ -630,10 +630,10 @@ void test_logb() {
// MAYTRAP-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to double
// MAYTRAP-NEXT: [[TMP5:%.*]] = load double, ptr [[A_ADDR_ASCAST]], align 8
// MAYTRAP-NEXT: [[TMP6:%.*]] = call double @llvm.fabs.f64(double [[TMP5]])
-// MAYTRAP-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], 0x7FF0000000000000
+// MAYTRAP-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], +inf
// MAYTRAP-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], double [[TMP4]], double [[TMP6]]
// MAYTRAP-NEXT: [[TMP9:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
-// MAYTRAP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double 0xFFF0000000000000, double [[TMP8]]
+// MAYTRAP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double -inf, double [[TMP8]]
// MAYTRAP-NEXT: store double [[TMP10]], ptr [[D1_ASCAST]], align 8
// MAYTRAP-NEXT: ret void
//
@@ -665,10 +665,10 @@ void test_logb() {
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to double
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP5:%.*]] = load double, ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP6:%.*]] = call addrspace(4) double @llvm.fabs.f64(double [[TMP5]])
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], 0x7FF0000000000000
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], +inf
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], double [[TMP4]], double [[TMP6]]
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP9:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double 0xFFF0000000000000, double [[TMP8]]
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double -inf, double [[TMP8]]
// AMDGCNSPIRV-DEFAULT-NEXT: store double [[TMP10]], ptr addrspace(4) [[D1_ASCAST]], align 8
// AMDGCNSPIRV-DEFAULT-NEXT: ret void
//
@@ -687,10 +687,10 @@ void test_logb() {
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to double
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP5:%.*]] = load double, ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP6:%.*]] = call addrspace(4) double @llvm.fabs.f64(double [[TMP5]])
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], 0x7FF0000000000000
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], +inf
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], double [[TMP4]], double [[TMP6]]
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP9:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double 0xFFF0000000000000, double [[TMP8]]
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double -inf, double [[TMP8]]
// AMDGCNSPIRV-IGNORE-NEXT: store double [[TMP10]], ptr addrspace(4) [[D1_ASCAST]], align 8
// AMDGCNSPIRV-IGNORE-NEXT: ret void
//
@@ -709,10 +709,10 @@ void test_logb() {
// AMDGCNSPIRV-STRICT-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to double
// AMDGCNSPIRV-STRICT-NEXT: [[TMP5:%.*]] = load double, ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
// AMDGCNSPIRV-STRICT-NEXT: [[TMP6:%.*]] = call addrspace(4) double @llvm.fabs.f64(double [[TMP5]])
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], 0x7FF0000000000000
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], +inf
// AMDGCNSPIRV-STRICT-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], double [[TMP4]], double [[TMP6]]
// AMDGCNSPIRV-STRICT-NEXT: [[TMP9:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double 0xFFF0000000000000, double [[TMP8]]
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double -inf, double [[TMP8]]
// AMDGCNSPIRV-STRICT-NEXT: store double [[TMP10]], ptr addrspace(4) [[D1_ASCAST]], align 8
// AMDGCNSPIRV-STRICT-NEXT: ret void
//
@@ -731,10 +731,10 @@ void test_logb() {
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP4:%.*]] = sitofp i32 [[TMP3]] to double
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP5:%.*]] = load double, ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP6:%.*]] = call addrspace(4) double @llvm.fabs.f64(double [[TMP5]])
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], 0x7FF0000000000000
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP7:%.*]] = fcmp one double [[TMP6]], +inf
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], double [[TMP4]], double [[TMP6]]
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP9:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double 0xFFF0000000000000, double [[TMP8]]
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], double -inf, double [[TMP8]]
// AMDGCNSPIRV-MAYTRAP-NEXT: store double [[TMP10]], ptr addrspace(4) [[D1_ASCAST]], align 8
// AMDGCNSPIRV-MAYTRAP-NEXT: ret void
//
@@ -768,7 +768,7 @@ void test_logb_var(double a) {
// DEFAULT-NEXT: [[ENTRY:.*:]]
// DEFAULT-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// DEFAULT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// DEFAULT-NEXT: [[TMP0:%.*]] = call float @llvm.ldexp.f32.i32(float 0x4030B33340000000, i32 10)
+// DEFAULT-NEXT: [[TMP0:%.*]] = call float @llvm.ldexp.f32.i32(float 1.670000e+01, i32 10)
// DEFAULT-NEXT: store float [[TMP0]], ptr [[D1_ASCAST]], align 4
// DEFAULT-NEXT: ret void
//
@@ -777,7 +777,7 @@ void test_logb_var(double a) {
// IGNORE-NEXT: [[ENTRY:.*:]]
// IGNORE-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// IGNORE-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// IGNORE-NEXT: [[TMP0:%.*]] = call float @llvm.ldexp.f32.i32(float 0x4030B33340000000, i32 10)
+// IGNORE-NEXT: [[TMP0:%.*]] = call float @llvm.ldexp.f32.i32(float 1.670000e+01, i32 10)
// IGNORE-NEXT: store float [[TMP0]], ptr [[D1_ASCAST]], align 4
// IGNORE-NEXT: ret void
//
@@ -786,7 +786,7 @@ void test_logb_var(double a) {
// STRICT-NEXT: [[ENTRY:.*:]]
// STRICT-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// STRICT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// STRICT-NEXT: [[TMP0:%.*]] = call float @llvm.ldexp.f32.i32(float 0x4030B33340000000, i32 10)
+// STRICT-NEXT: [[TMP0:%.*]] = call float @llvm.ldexp.f32.i32(float 1.670000e+01, i32 10)
// STRICT-NEXT: store float [[TMP0]], ptr [[D1_ASCAST]], align 4
// STRICT-NEXT: ret void
//
@@ -795,7 +795,7 @@ void test_logb_var(double a) {
// MAYTRAP-NEXT: [[ENTRY:.*:]]
// MAYTRAP-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// MAYTRAP-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// MAYTRAP-NEXT: [[TMP0:%.*]] = call float @llvm.ldexp.f32.i32(float 0x4030B33340000000, i32 10)
+// MAYTRAP-NEXT: [[TMP0:%.*]] = call float @llvm.ldexp.f32.i32(float 1.670000e+01, i32 10)
// MAYTRAP-NEXT: store float [[TMP0]], ptr [[D1_ASCAST]], align 4
// MAYTRAP-NEXT: ret void
//
@@ -804,7 +804,7 @@ void test_logb_var(double a) {
// ERRNO-NEXT: [[ENTRY:.*:]]
// ERRNO-NEXT: [[D1:%.*]] = alloca float, align 4, addrspace(5)
// ERRNO-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
-// ERRNO-NEXT: [[CALL:%.*]] = call float @scalbnf(float noundef 0x4030B33340000000, i32 noundef 10) #[[ATTR2]]
+// ERRNO-NEXT: [[CALL:%.*]] = call float @scalbnf(float noundef 1.670000e+01, i32 noundef 10) #[[ATTR2]]
// ERRNO-NEXT: store float [[CALL]], ptr [[D1_ASCAST]], align 4
// ERRNO-NEXT: ret void
//
@@ -813,7 +813,7 @@ void test_logb_var(double a) {
// AMDGCNSPIRV-DEFAULT-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-DEFAULT-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-DEFAULT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP0:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 0x4030B33340000000, i32 10)
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP0:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 1.670000e+01, i32 10)
// AMDGCNSPIRV-DEFAULT-NEXT: store float [[TMP0]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-DEFAULT-NEXT: ret void
//
@@ -822,7 +822,7 @@ void test_logb_var(double a) {
// AMDGCNSPIRV-IGNORE-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-IGNORE-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-IGNORE-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP0:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 0x4030B33340000000, i32 10)
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP0:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 1.670000e+01, i32 10)
// AMDGCNSPIRV-IGNORE-NEXT: store float [[TMP0]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-IGNORE-NEXT: ret void
//
@@ -831,7 +831,7 @@ void test_logb_var(double a) {
// AMDGCNSPIRV-STRICT-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-STRICT-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-STRICT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP0:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 0x4030B33340000000, i32 10)
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP0:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 1.670000e+01, i32 10)
// AMDGCNSPIRV-STRICT-NEXT: store float [[TMP0]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-STRICT-NEXT: ret void
//
@@ -840,7 +840,7 @@ void test_logb_var(double a) {
// AMDGCNSPIRV-MAYTRAP-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-MAYTRAP-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-MAYTRAP-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP0:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 0x4030B33340000000, i32 10)
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP0:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 1.670000e+01, i32 10)
// AMDGCNSPIRV-MAYTRAP-NEXT: store float [[TMP0]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-MAYTRAP-NEXT: ret void
//
@@ -849,7 +849,7 @@ void test_logb_var(double a) {
// AMDGCNSPIRV-ERRNO-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-ERRNO-NEXT: [[D1:%.*]] = alloca float, align 4
// AMDGCNSPIRV-ERRNO-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
-// AMDGCNSPIRV-ERRNO-NEXT: [[CALL:%.*]] = call spir_func addrspace(4) float @scalbnf(float noundef 0x4030B33340000000, i32 noundef 10) #[[ATTR2]]
+// AMDGCNSPIRV-ERRNO-NEXT: [[CALL:%.*]] = call spir_func addrspace(4) float @scalbnf(float noundef 1.670000e+01, i32 noundef 10) #[[ATTR2]]
// AMDGCNSPIRV-ERRNO-NEXT: store float [[CALL]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-ERRNO-NEXT: ret void
//
@@ -1022,7 +1022,7 @@ void test_scalbnf_var1(float a) {
// DEFAULT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
// DEFAULT-NEXT: store i32 [[B]], ptr [[B_ADDR_ASCAST]], align 4
// DEFAULT-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
-// DEFAULT-NEXT: [[TMP1:%.*]] = call float @llvm.ldexp.f32.i32(float 0x402E666660000000, i32 [[TMP0]])
+// DEFAULT-NEXT: [[TMP1:%.*]] = call float @llvm.ldexp.f32.i32(float 1.520000e+01, i32 [[TMP0]])
// DEFAULT-NEXT: store float [[TMP1]], ptr [[D1_ASCAST]], align 4
// DEFAULT-NEXT: ret void
//
@@ -1035,7 +1035,7 @@ void test_scalbnf_var1(float a) {
// IGNORE-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
// IGNORE-NEXT: store i32 [[B]], ptr [[B_ADDR_ASCAST]], align 4
// IGNORE-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
-// IGNORE-NEXT: [[TMP1:%.*]] = call float @llvm.ldexp.f32.i32(float 0x402E666660000000, i32 [[TMP0]])
+// IGNORE-NEXT: [[TMP1:%.*]] = call float @llvm.ldexp.f32.i32(float 1.520000e+01, i32 [[TMP0]])
// IGNORE-NEXT: store float [[TMP1]], ptr [[D1_ASCAST]], align 4
// IGNORE-NEXT: ret void
//
@@ -1048,7 +1048,7 @@ void test_scalbnf_var1(float a) {
// STRICT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
// STRICT-NEXT: store i32 [[B]], ptr [[B_ADDR_ASCAST]], align 4
// STRICT-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
-// STRICT-NEXT: [[TMP1:%.*]] = call float @llvm.ldexp.f32.i32(float 0x402E666660000000, i32 [[TMP0]])
+// STRICT-NEXT: [[TMP1:%.*]] = call float @llvm.ldexp.f32.i32(float 1.520000e+01, i32 [[TMP0]])
// STRICT-NEXT: store float [[TMP1]], ptr [[D1_ASCAST]], align 4
// STRICT-NEXT: ret void
//
@@ -1061,7 +1061,7 @@ void test_scalbnf_var1(float a) {
// MAYTRAP-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
// MAYTRAP-NEXT: store i32 [[B]], ptr [[B_ADDR_ASCAST]], align 4
// MAYTRAP-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
-// MAYTRAP-NEXT: [[TMP1:%.*]] = call float @llvm.ldexp.f32.i32(float 0x402E666660000000, i32 [[TMP0]])
+// MAYTRAP-NEXT: [[TMP1:%.*]] = call float @llvm.ldexp.f32.i32(float 1.520000e+01, i32 [[TMP0]])
// MAYTRAP-NEXT: store float [[TMP1]], ptr [[D1_ASCAST]], align 4
// MAYTRAP-NEXT: ret void
//
@@ -1074,7 +1074,7 @@ void test_scalbnf_var1(float a) {
// ERRNO-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D1]] to ptr
// ERRNO-NEXT: store i32 [[B]], ptr [[B_ADDR_ASCAST]], align 4
// ERRNO-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
-// ERRNO-NEXT: [[CALL:%.*]] = call float @scalbnf(float noundef 0x402E666660000000, i32 noundef [[TMP0]]) #[[ATTR2]]
+// ERRNO-NEXT: [[CALL:%.*]] = call float @scalbnf(float noundef 1.520000e+01, i32 noundef [[TMP0]]) #[[ATTR2]]
// ERRNO-NEXT: store float [[CALL]], ptr [[D1_ASCAST]], align 4
// ERRNO-NEXT: ret void
//
@@ -1087,7 +1087,7 @@ void test_scalbnf_var1(float a) {
// AMDGCNSPIRV-DEFAULT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
// AMDGCNSPIRV-DEFAULT-NEXT: store i32 [[B]], ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
-// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP1:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 0x402E666660000000, i32 [[TMP0]])
+// AMDGCNSPIRV-DEFAULT-NEXT: [[TMP1:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 1.520000e+01, i32 [[TMP0]])
// AMDGCNSPIRV-DEFAULT-NEXT: store float [[TMP1]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-DEFAULT-NEXT: ret void
//
@@ -1100,7 +1100,7 @@ void test_scalbnf_var1(float a) {
// AMDGCNSPIRV-IGNORE-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
// AMDGCNSPIRV-IGNORE-NEXT: store i32 [[B]], ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-IGNORE-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
-// AMDGCNSPIRV-IGNORE-NEXT: [[TMP1:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 0x402E666660000000, i32 [[TMP0]])
+// AMDGCNSPIRV-IGNORE-NEXT: [[TMP1:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 1.520000e+01, i32 [[TMP0]])
// AMDGCNSPIRV-IGNORE-NEXT: store float [[TMP1]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-IGNORE-NEXT: ret void
//
@@ -1113,7 +1113,7 @@ void test_scalbnf_var1(float a) {
// AMDGCNSPIRV-STRICT-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
// AMDGCNSPIRV-STRICT-NEXT: store i32 [[B]], ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-STRICT-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
-// AMDGCNSPIRV-STRICT-NEXT: [[TMP1:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 0x402E666660000000, i32 [[TMP0]])
+// AMDGCNSPIRV-STRICT-NEXT: [[TMP1:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 1.520000e+01, i32 [[TMP0]])
// AMDGCNSPIRV-STRICT-NEXT: store float [[TMP1]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-STRICT-NEXT: ret void
//
@@ -1126,7 +1126,7 @@ void test_scalbnf_var1(float a) {
// AMDGCNSPIRV-MAYTRAP-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
// AMDGCNSPIRV-MAYTRAP-NEXT: store i32 [[B]], ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
-// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP1:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 0x402E666660000000, i32 [[TMP0]])
+// AMDGCNSPIRV-MAYTRAP-NEXT: [[TMP1:%.*]] = call addrspace(4) float @llvm.ldexp.f32.i32(float 1.520000e+01, i32 [[TMP0]])
// AMDGCNSPIRV-MAYTRAP-NEXT: store float [[TMP1]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-MAYTRAP-NEXT: ret void
//
@@ -1139,7 +1139,7 @@ void test_scalbnf_var1(float a) {
// AMDGCNSPIRV-ERRNO-NEXT: [[D1_ASCAST:%.*]] = addrspacecast ptr [[D1]] to ptr addrspace(4)
// AMDGCNSPIRV-ERRNO-NEXT: store i32 [[B]], ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
// AMDGCNSPIRV-ERRNO-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) [[B_ADDR_ASCAST]], align 4
-// AMDGCNSPIRV-ERRNO-NEXT: [[CALL:%.*]] = call spir_func addrspace(4) float @scalbnf(float noundef 0x402E666660000000, i32 noundef [[TMP0]]) #[[ATTR2]]
+// AMDGCNSPIRV-ERRNO-NEXT: [[CALL:%.*]] = call spir_func addrspace(4) float @scalbnf(float noundef 1.520000e+01, i32 noundef [[TMP0]]) #[[ATTR2]]
// AMDGCNSPIRV-ERRNO-NEXT: store float [[CALL]], ptr addrspace(4) [[D1_ASCAST]], align 4
// AMDGCNSPIRV-ERRNO-NEXT: ret void
//
diff --git a/clang/test/CodeGen/math-builtins-long.c b/clang/test/CodeGen/math-builtins-long.c
index 28a4e8893d5bd..13b5a180ea12d 100644
--- a/clang/test/CodeGen/math-builtins-long.c
+++ b/clang/test/CodeGen/math-builtins-long.c
@@ -40,16 +40,16 @@ void foo(long double f, long double *l, int *i, const char *c) {
// PPCF128: call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %{{.+}})
__builtin_frexpl(f,i);
- // F80: store x86_fp80 0xK7FFF8000000000000000, ptr
- // PPC: store ppc_fp128 0xM7FF00000000000000000000000000000, ptr
- // X86F128: store fp128 0xL00000000000000007FFF000000000000, ptr
- // PPCF128: store fp128 0xL00000000000000007FFF000000000000, ptr
+ // F80: store x86_fp80 +inf, ptr
+ // PPC: store ppc_fp128 +inf, ptr
+ // X86F128: store fp128 +inf, ptr
+ // PPCF128: store fp128 +inf, ptr
*l = __builtin_huge_vall();
- // F80: store x86_fp80 0xK7FFF8000000000000000, ptr
- // PPC: store ppc_fp128 0xM7FF00000000000000000000000000000, ptr
- // X86F128: store fp128 0xL00000000000000007FFF000000000000, ptr
- // PPCF128: store fp128 0xL00000000000000007FFF000000000000, ptr
+ // F80: store x86_fp80 +inf, ptr
+ // PPC: store ppc_fp128 +inf, ptr
+ // X86F128: store fp128 +inf, ptr
+ // PPCF128: store fp128 +inf, ptr
*l = __builtin_infl();
// F80: call x86_fp80 @ldexpl(x86_fp80 noundef %{{.+}}, i32 noundef %{{.+}})
diff --git a/clang/test/CodeGen/mingw-long-double.c b/clang/test/CodeGen/mingw-long-double.c
index 82f970f99d850..040a3ba8e044e 100644
--- a/clang/test/CodeGen/mingw-long-double.c
+++ b/clang/test/CodeGen/mingw-long-double.c
@@ -16,13 +16,13 @@ struct {
// MSC64: @agggregate_LD = dso_local global { i8, [7 x i8], double } zeroinitializer, align 8
long double dataLD = 1.0L;
-// GNU32: @dataLD = dso_local global x86_fp80 0xK3FFF8000000000000000, align 4
-// GNU64: @dataLD = dso_local global x86_fp80 0xK3FFF8000000000000000, align 16
+// GNU32: @dataLD = dso_local global x86_fp80 1.000000e+00, align 4
+// GNU64: @dataLD = dso_local global x86_fp80 1.000000e+00, align 16
// MSC64: @dataLD = dso_local global double 1.000000e+00, align 8
long double _Complex dataLDC = {1.0L, 1.0L};
-// GNU32: @dataLDC = dso_local global { x86_fp80, x86_fp80 } { x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000 }, align 4
-// GNU64: @dataLDC = dso_local global { x86_fp80, x86_fp80 } { x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000 }, align 16
+// GNU32: @dataLDC = dso_local global { x86_fp80, x86_fp80 } { x86_fp80 1.000000e+00, x86_fp80 1.000000e+00 }, align 4
+// GNU64: @dataLDC = dso_local global { x86_fp80, x86_fp80 } { x86_fp80 1.000000e+00, x86_fp80 1.000000e+00 }, align 16
// MSC64: @dataLDC = dso_local global { double, double } { double 1.000000e+00, double 1.000000e+00 }, align 8
long double TestLD(long double x) {
diff --git a/clang/test/CodeGen/mips-unsupported-nan.c b/clang/test/CodeGen/mips-unsupported-nan.c
index 16cea3c2e7e18..0aadab84651e9 100644
--- a/clang/test/CodeGen/mips-unsupported-nan.c
+++ b/clang/test/CodeGen/mips-unsupported-nan.c
@@ -44,8 +44,8 @@
// so the next highest bit is set to maintain NAN (not infinity).
// In regular (2008) mode, the quiet bit is set to indicate QNAN.
-// CHECK-NANLEGACY: double 0x7FF4000000000000
-// CHECK-NAN2008: double 0x7FF8000000000000
+// CHECK-NANLEGACY: double +snan(0x4000000000000)
+// CHECK-NAN2008: double +qnan
double d = __builtin_nan("");
@@ -53,7 +53,7 @@ double d = __builtin_nan("");
// llvm::APFloat does not know about the inverted quiet bit, so it sets the
// quiet bit on conversion independently of the setting in clang.
-// CHECK-NANLEGACY: float 0x7FFC000000000000
-// CHECK-NAN2008: float 0x7FF8000000000000
+// CHECK-NANLEGACY: float +nan(0x200000)
+// CHECK-NAN2008: float +qnan
float f = __builtin_nan("");
diff --git a/clang/test/CodeGen/ppc-vec_ct-truncate.c b/clang/test/CodeGen/ppc-vec_ct-truncate.c
index e3a0f11618759..463a1cdc6f5b5 100644
--- a/clang/test/CodeGen/ppc-vec_ct-truncate.c
+++ b/clang/test/CodeGen/ppc-vec_ct-truncate.c
@@ -30,11 +30,11 @@ void test(void) {
res_vsi = vec_cts(a1, 31);
// CHECK: [[TMP0:%.*]] = load <2 x double>, ptr @a1, align 16
- // CHECK-NEXT: fmul <2 x double> [[TMP0]], splat (double 0x41E0000000000000)
+ // CHECK-NEXT: fmul <2 x double> [[TMP0]], splat (double f0x41E0000000000000)
res_vsi = vec_cts(a1, 500);
// CHECK: [[TMP4:%.*]] = load <2 x double>, ptr @a1, align 16
- // CHECK-NEXT: fmul <2 x double> [[TMP4]], splat (double 0x4130000000000000)
+ // CHECK-NEXT: fmul <2 x double> [[TMP4]], splat (double f0x4130000000000000)
res_vsi = vec_ctu(vf1, 31);
// CHECK: [[TMP8:%.*]] = load <4 x float>, ptr @vf1, align 16
@@ -46,19 +46,19 @@ void test(void) {
res_vull = vec_ctul(vf1, 31);
// CHECK: [[TMP12:%.*]] = load <4 x float>, ptr @vf1, align 16
- // CHECK-NEXT: fmul <4 x float> [[TMP12]], splat (float 0x41E0000000000000)
+ // CHECK-NEXT: fmul <4 x float> [[TMP12]], splat (float f0x4F000000)
res_vull = vec_ctul(vf1, 500);
// CHECK: [[TMP21:%.*]] = load <4 x float>, ptr @vf1, align 16
- // CHECK-NEXT: fmul <4 x float> [[TMP21]], splat (float 0x4130000000000000)
+ // CHECK-NEXT: fmul <4 x float> [[TMP21]], splat (float f0x49800000)
res_vsll = vec_ctsl(vf1, 31);
// CHECK: [[TMP30:%.*]] = load <4 x float>, ptr @vf1, align 16
- // CHECK-NEXT: fmul <4 x float> [[TMP30]], splat (float 0x41E0000000000000)
+ // CHECK-NEXT: fmul <4 x float> [[TMP30]], splat (float f0x4F000000)
res_vsll = vec_ctsl(vf1, 500);
// CHECK: [[TMP39:%.*]] = load <4 x float>, ptr @vf1, align 16
- // CHECK-NEXT: fmul <4 x float> [[TMP39]], splat (float 0x4130000000000000)
+ // CHECK-NEXT: fmul <4 x float> [[TMP39]], splat (float f0x49800000)
res_vf = vec_ctf(vsi1, 31);
// CHECK: [[TMP48:%.*]] = load <4 x i32>, ptr @vsi1, align 16
@@ -71,10 +71,10 @@ void test(void) {
res_vd = vec_ctd(vsi1, 31);
// CHECK: [[TMP53:%.*]] = load <4 x i32>, ptr @vsi1, align 16
// CHECK: [[TMP83:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP82:%.*]])
- // CHECK-NEXT: fmul <2 x double> [[TMP83]], splat (double 0x3E00000000000000)
+ // CHECK-NEXT: fmul <2 x double> [[TMP83]], splat (double f0x3E00000000000000)
res_vd = vec_ctd(vsi1, 500);
// CHECK: [[TMP84:%.*]] = load <4 x i32>, ptr @vsi1, align 16
// CHECK: [[TMP115:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP114:%.*]])
- // CHECK-NEXT: fmul <2 x double> [[TMP115]], splat (double 0x3EB0000000000000)
+ // CHECK-NEXT: fmul <2 x double> [[TMP115]], splat (double f0x3EB0000000000000)
}
diff --git a/clang/test/CodeGen/rounding-math.c b/clang/test/CodeGen/rounding-math.c
index fbbf06b647335..77d4fd046dfc5 100644
--- a/clang/test/CodeGen/rounding-math.c
+++ b/clang/test/CodeGen/rounding-math.c
@@ -39,7 +39,7 @@ struct S *func_06(void) {
return &var_06;
}
-// CHECK: @var_04 = {{.*}} %struct.S { float 0x3FF0000020000000 }
-// CHECK: @var_05 = {{.*}} %struct.S { float 0x3FF0000020000000 }
-// CHECK: @func_06.var_06 = {{.*}} %struct.S { float 0x3FF0000020000000 }
+// CHECK: @var_04 = {{.*}} %struct.S { float f0x3F800001 }
+// CHECK: @var_05 = {{.*}} %struct.S { float f0x3F800001 }
+// CHECK: @func_06.var_06 = {{.*}} %struct.S { float f0x3F800001 }
diff --git a/clang/test/CodeGen/rounding-math.cpp b/clang/test/CodeGen/rounding-math.cpp
index 5c44fd31242c6..7570affe85968 100644
--- a/clang/test/CodeGen/rounding-math.cpp
+++ b/clang/test/CodeGen/rounding-math.cpp
@@ -16,14 +16,14 @@ void test_builtin_elementwise_fma_round_upward() {
#pragma STDC FENV_ACCESS ON
#pragma STDC FENV_ROUND FE_UPWARD
- // CHECK: store float 0x4018000100000000, ptr %f1
- // CHECK: store float 0x4018000100000000, ptr %f2
+ // CHECK: store float f0x40C00008, ptr %f1
+ // CHECK: store float f0x40C00008, ptr %f2
constexpr float f1 = __builtin_elementwise_fma(2.0F, 3.000001F, 0.000001F);
constexpr float f2 = 2.0F * 3.000001F + 0.000001F;
static_assert(f1 == f2);
static_assert(f1 == 6.00000381F);
- // CHECK: store double 0x40180000C9539B89, ptr %d1
- // CHECK: store double 0x40180000C9539B89, ptr %d2
+ // CHECK: store double f0x40180000C9539B89, ptr %d1
+ // CHECK: store double f0x40180000C9539B89, ptr %d2
constexpr double d1 = __builtin_elementwise_fma(2.0, 3.000001, 0.000001);
constexpr double d2 = 2.0 * 3.000001 + 0.000001;
static_assert(d1 == d2);
@@ -34,13 +34,13 @@ void test_builtin_elementwise_fma_round_downward() {
#pragma STDC FENV_ACCESS ON
#pragma STDC FENV_ROUND FE_DOWNWARD
- // CHECK: store float 0x40180000C0000000, ptr %f3
- // CHECK: store float 0x40180000C0000000, ptr %f4
+ // CHECK: store float f0x40C00006, ptr %f3
+ // CHECK: store float f0x40C00006, ptr %f4
constexpr float f3 = __builtin_elementwise_fma(2.0F, 3.000001F, 0.000001F);
constexpr float f4 = 2.0F * 3.000001F + 0.000001F;
static_assert(f3 == f4);
- // CHECK: store double 0x40180000C9539B87, ptr %d3
- // CHECK: store double 0x40180000C9539B87, ptr %d4
+ // CHECK: store double f0x40180000C9539B87, ptr %d3
+ // CHECK: store double f0x40180000C9539B87, ptr %d4
constexpr double d3 = __builtin_elementwise_fma(2.0, 3.000001, 0.000001);
constexpr double d4 = 2.0 * 3.000001 + 0.000001;
static_assert(d3 == d4);
@@ -50,14 +50,14 @@ void test_builtin_elementwise_fma_round_nearest() {
#pragma STDC FENV_ACCESS ON
#pragma STDC FENV_ROUND FE_TONEAREST
- // CHECK: store float 0x40180000C0000000, ptr %f5
- // CHECK: store float 0x40180000C0000000, ptr %f6
+ // CHECK: store float f0x40C00006, ptr %f5
+ // CHECK: store float f0x40C00006, ptr %f6
constexpr float f5 = __builtin_elementwise_fma(2.0F, 3.000001F, 0.000001F);
constexpr float f6 = 2.0F * 3.000001F + 0.000001F;
static_assert(f5 == f6);
static_assert(f5 == 6.00000286F);
- // CHECK: store double 0x40180000C9539B89, ptr %d5
- // CHECK: store double 0x40180000C9539B89, ptr %d6
+ // CHECK: store double f0x40180000C9539B89, ptr %d5
+ // CHECK: store double f0x40180000C9539B89, ptr %d6
constexpr double d5 = __builtin_elementwise_fma(2.0, 3.000001, 0.000001);
constexpr double d6 = 2.0 * 3.000001 + 0.000001;
static_assert(d5 == d6);
diff --git a/clang/test/CodeGen/spir-half-type.cpp b/clang/test/CodeGen/spir-half-type.cpp
index d7c8bd9240abb..f02ee8182bb93 100644
--- a/clang/test/CodeGen/spir-half-type.cpp
+++ b/clang/test/CodeGen/spir-half-type.cpp
@@ -15,40 +15,40 @@ bool fcmp_const() {
// CHECK-NOT: llvm.convert.from.fp16
// CHECK: [[REG1:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp olt half [[REG1]], 0xH3C00
+ // CHECK-NEXT: fcmp olt half [[REG1]], 1.000000e+00
// CHECK: [[REG2:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp olt half [[REG2]], 0xH4000
+ // CHECK-NEXT: fcmp olt half [[REG2]], 2.000000e+00
// CHECK: [[REG3:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp ogt half [[REG3]], 0xH3C00
+ // CHECK-NEXT: fcmp ogt half [[REG3]], 1.000000e+00
// CHECK: [[REG4:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp ogt half [[REG4]], 0xH4200
+ // CHECK-NEXT: fcmp ogt half [[REG4]], 3.000000e+00
// CHECK: [[REG5:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp oeq half [[REG5]], 0xH3C00
+ // CHECK-NEXT: fcmp oeq half [[REG5]], 1.000000e+00
// CHECK: [[REG7:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp oeq half [[REG7]], 0xH4400
+ // CHECK-NEXT: fcmp oeq half [[REG7]], 4.000000e+00
// CHECK: [[REG8:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp une half [[REG8]], 0xH3C00
+ // CHECK-NEXT: fcmp une half [[REG8]], 1.000000e+00
// CHECK: [[REG9:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp une half [[REG9]], 0xH4500
+ // CHECK-NEXT: fcmp une half [[REG9]], 5.000000e+00
// CHECK: [[REG10:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp ole half [[REG10]], 0xH3C00
+ // CHECK-NEXT: fcmp ole half [[REG10]], 1.000000e+00
// CHECK: [[REG11:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp ole half [[REG11]], 0xH4600
+ // CHECK-NEXT: fcmp ole half [[REG11]], 6.000000e+00
// CHECK: [[REG12:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp oge half [[REG12]], 0xH3C00
+ // CHECK-NEXT: fcmp oge half [[REG12]], 1.000000e+00
// CHECK: [[REG13:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: fcmp oge half [[REG13]], 0xH4700
+ // CHECK-NEXT: fcmp oge half [[REG13]], 7.000000e+00
return a < b || a < 2.0f16 || a > b || a > 3.0f16 || a == b || a == 4.0f16 ||
a != b || a != 5.0f16 || a <= b || a <= 6.0f16 || a >= b ||
a >= 7.0f16;
@@ -94,8 +94,8 @@ _Float16 fadd() {
// CHECK-NOT: llvm.convert.from.fp16
// CHECK: [[REG1:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: [[REG2:%.*]] = fadd half [[REG1]], 0xH4000
- // CHECK-NEXT: [[REG3:%.*]] = fadd half [[REG2]], 0xH4200
+ // CHECK-NEXT: [[REG2:%.*]] = fadd half [[REG1]], 2.000000e+00
+ // CHECK-NEXT: [[REG3:%.*]] = fadd half [[REG2]], 3.000000e+00
// CHECK-NEXT: ret half [[REG3]]
return a + b + 3.0f16;
}
@@ -108,8 +108,8 @@ _Float16 fsub() {
// CHECK-NOT: llvm.convert.from.fp16
// CHECK: [[REG1:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: [[REG2:%.*]] = fsub half [[REG1]], 0xH4000
- // CHECK-NEXT: [[REG3:%.*]] = fsub half [[REG2]], 0xH4200
+ // CHECK-NEXT: [[REG2:%.*]] = fsub half [[REG1]], 2.000000e+00
+ // CHECK-NEXT: [[REG3:%.*]] = fsub half [[REG2]], 3.000000e+00
// CHECK-NEXT: ret half [[REG3]]
return a - b - 3.0f16;
}
@@ -125,8 +125,8 @@ _Float16 fmul(_Float16 arg) {
// CHECK: [[REG1:%.*]] = load half, ptr %a, align 2
// CHECK-NEXT: [[REG2:%.*]] = load half, ptr %arg.addr, align 2
// CHECK-NEXT: [[REG3:%.*]] = fmul half [[REG1]], [[REG2]]
- // CHECK-NEXT: [[REG4:%.*]] = fmul half [[REG3]], 0xH4000
- // CHECK-NEXT: [[REG5:%.*]] = fmul half [[REG4]], 0xH4200
+ // CHECK-NEXT: [[REG4:%.*]] = fmul half [[REG3]], 2.000000e+00
+ // CHECK-NEXT: [[REG5:%.*]] = fmul half [[REG4]], 3.000000e+00
// CHECK-NEXT: ret half [[REG5]]
return a * arg * b * 3.0f16;
}
@@ -139,8 +139,8 @@ _Float16 fdiv() {
// CHECK-NOT: llvm.convert.from.fp16
// CHECK: [[REG1:%.*]] = load half, ptr %a, align 2
- // CHECK-NEXT: [[REG2:%.*]] = fdiv half [[REG1]], 0xH4000
- // CHECK-NEXT: [[REG3:%.*]] = fdiv half [[REG2]], 0xH4200
+ // CHECK-NEXT: [[REG2:%.*]] = fdiv half [[REG1]], 2.000000e+00
+ // CHECK-NEXT: [[REG3:%.*]] = fdiv half [[REG2]], 3.000000e+00
// CHECK-NEXT: ret half [[REG3]]
return a / b / 3.0f16;
}
diff --git a/clang/test/CodeGen/strictfp_builtins.c b/clang/test/CodeGen/strictfp_builtins.c
index 58815c7de4fa9..8b6cdcc38c8af 100644
--- a/clang/test/CodeGen/strictfp_builtins.c
+++ b/clang/test/CodeGen/strictfp_builtins.c
@@ -42,10 +42,10 @@ void p(char *str, int x) {
// CHECK-NEXT: br i1 [[CMP]], label [[FPCLASSIFY_END]], label [[FPCLASSIFY_NOT_NAN]]
// CHECK: fpclassify_not_nan:
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) #[[ATTR5:[0-9]+]]
-// CHECK-NEXT: [[ISINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR4]]
+// CHECK-NEXT: [[ISINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double +inf, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR4]]
// CHECK-NEXT: br i1 [[ISINF]], label [[FPCLASSIFY_END]], label [[FPCLASSIFY_NOT_INF]]
// CHECK: fpclassify_not_inf:
-// CHECK-NEXT: [[ISNORMAL:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x10000000000000, metadata !"uge", metadata !"fpexcept.strict") #[[ATTR4]]
+// CHECK-NEXT: [[ISNORMAL:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double f0x0010000000000000, metadata !"uge", metadata !"fpexcept.strict") #[[ATTR4]]
// CHECK-NEXT: [[TMP2]] = select i1 [[ISNORMAL]], i32 2, i32 3
// CHECK-NEXT: br label [[FPCLASSIFY_END]]
//
@@ -157,7 +157,7 @@ void test_double_isfinite(double d) {
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) #[[ATTR5]]
-// CHECK-NEXT: [[ISINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR4]]
+// CHECK-NEXT: [[ISINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double +inf, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = bitcast double [[TMP0]] to i64
// CHECK-NEXT: [[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0
// CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 -1, i32 1
diff --git a/clang/test/CodeGenCUDA/long-double.cu b/clang/test/CodeGenCUDA/long-double.cu
index 898afcac124b5..2e669ad7de8f8 100644
--- a/clang/test/CodeGenCUDA/long-double.cu
+++ b/clang/test/CodeGenCUDA/long-double.cu
@@ -10,7 +10,7 @@
// RUN: -aux-triple x86_64-unknown-gnu-linux -fcuda-is-device \
// RUN: -emit-llvm -o - %s 2>&1 | FileCheck %s
-// CHECK: @_ZN15infinity_helperIeE5valueE = {{.*}} double 0x47EFFFFFD586B834,{{.*}} align 8
+// CHECK: @_ZN15infinity_helperIeE5valueE = {{.*}} double f0x47EFFFFFD586B834,{{.*}} align 8
// CHECK: @size = {{.*}} i32 8
#include "Inputs/cuda.h"
diff --git a/clang/test/CodeGenCUDA/printf.cu b/clang/test/CodeGenCUDA/printf.cu
index 6e01001209e17..ba796eabcbbe7 100644
--- a/clang/test/CodeGenCUDA/printf.cu
+++ b/clang/test/CodeGenCUDA/printf.cu
@@ -19,7 +19,7 @@ __device__ int CheckSimple() {
// CHECK: [[PTR1:%[0-9]+]] = getelementptr inbounds nuw [[SIMPLE_PRINTF_TY]], ptr [[BUF]], i32 0, i32 1
// CHECK: store i64 2, ptr [[PTR1]], align 8
// CHECK: [[PTR2:%[0-9]+]] = getelementptr inbounds nuw [[SIMPLE_PRINTF_TY]], ptr [[BUF]], i32 0, i32 2
- // CHECK: store double 3.0{{[^,]*}}, ptr [[PTR2]], align 8
+ // CHECK: store double 3.000000e+00{{[^,]*}}, ptr [[PTR2]], align 8
// CHECK: [[RET:%[0-9]+]] = call i32 @vprintf(ptr [[FMT]], ptr [[BUF]])
// CHECK: ret i32 [[RET]]
return printf(fmt, 1, 2ll, 3.0);
diff --git a/clang/test/CodeGenCUDA/types.cu b/clang/test/CodeGenCUDA/types.cu
index ee7ab717aac5a..2d5d1b29d77a7 100644
--- a/clang/test/CodeGenCUDA/types.cu
+++ b/clang/test/CodeGenCUDA/types.cu
@@ -3,7 +3,7 @@
#include "Inputs/cuda.h"
-// HOST: @ld_host ={{.*}} global x86_fp80 0xK00000000000000000000
+// HOST: @ld_host ={{.*}} global x86_fp80 0.000000e+00
long double ld_host;
// DEV: @ld_device ={{.*}} addrspace(1) externally_initialized global double 0.000000e+00
diff --git a/clang/test/CodeGenCXX/auto-var-init.cpp b/clang/test/CodeGenCXX/auto-var-init.cpp
index 67bc5d417bce9..a0d1dbcd57b26 100644
--- a/clang/test/CodeGenCXX/auto-var-init.cpp
+++ b/clang/test/CodeGenCXX/auto-var-init.cpp
@@ -144,9 +144,9 @@ struct notlockfree { long long a[4]; };
// PATTERN-O1-NOT: @__const.test_atomicpadded_uninit.uninit
// PATTERN-O0: @__const.test_atomictailpad_uninit.uninit = private unnamed_addr constant { i16, i8, [1 x i8] } { i16 [[I16]], i8 [[I8]], [1 x i8] c"\[[IC]]" }, align 4
// PATTERN-O1-NOT: @__const.test_atomictailpad_uninit.uninit
-// PATTERN-O0: @__const.test_complexfloat_uninit.uninit = private unnamed_addr constant { float, float } { float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000 }, align 4
+// PATTERN-O0: @__const.test_complexfloat_uninit.uninit = private unnamed_addr constant { float, float } { float -nan(0x3FFFFF), float -nan(0x3FFFFF) }, align 4
// PATTERN-O1-NOT: @__const.test_complexfloat_uninit.uninit
-// PATTERN-O0: @__const.test_complexdouble_uninit.uninit = private unnamed_addr constant { double, double } { double 0xFFFFFFFFFFFFFFFF, double 0xFFFFFFFFFFFFFFFF }, align 8
+// PATTERN-O0: @__const.test_complexdouble_uninit.uninit = private unnamed_addr constant { double, double } { double -nan(0x7FFFFFFFFFFFF), double -nan(0x7FFFFFFFFFFFF) }, align 8
// PATTERN-O1-NOT: @__const.test_complexdouble_uninit.uninit
// PATTERN-O0: @__const.test_semivolatile_uninit.uninit = private unnamed_addr constant %struct.semivolatile { i32 [[I32]], i32 [[I32]] }, align 4
// PATTERN-O0: @__const.test_semivolatile_custom.custom = private unnamed_addr constant %struct.semivolatile { i32 1145324612, i32 1145324612 }, align 4
@@ -183,7 +183,7 @@ struct virtualderived : public virtual base, public virtual derived {};
// ZERO-O0: @__const.test_matching_custom.custom = private unnamed_addr constant { float } { float 6.145500e+04 }, align 4
// ZERO-O1-NOT: @__const.test_matching_custom.custom
union matching { int i; float f; };
-// PATTERN-O0: @__const.test_matchingreverse_uninit.uninit = private unnamed_addr constant %union.matchingreverse { float 0xFFFFFFFFE0000000 }, align 4
+// PATTERN-O0: @__const.test_matchingreverse_uninit.uninit = private unnamed_addr constant %union.matchingreverse { float -nan(0x3FFFFF) }, align 4
// PATTERN-O1-NOT: @__const.test_matchingreverse_uninit.uninit
// PATTERN-O0: @__const.test_matchingreverse_custom.custom = private unnamed_addr constant { i32 } { i32 61455 }, align 4
// PATTERN-O1-NOT: @__const.test_matchingreverse_custom.custom
@@ -204,11 +204,11 @@ union unmatched { char c; int i; };
// ZERO-O0: @__const.test_unmatchedreverse_custom.custom = private unnamed_addr constant { i8, [3 x i8] } { i8 42, [3 x i8] zeroinitializer }, align 4
// ZERO-O1-NOT: @__const.test_unmatchedreverse_custom.custom
union unmatchedreverse { int i; char c; };
-// PATTERN-O0: @__const.test_unmatchedfp_uninit.uninit = private unnamed_addr constant %union.unmatchedfp { double 0xFFFFFFFFFFFFFFFF }, align
+// PATTERN-O0: @__const.test_unmatchedfp_uninit.uninit = private unnamed_addr constant %union.unmatchedfp { double -nan(0x7FFFFFFFFFFFF) }, align
// PATTERN-O1-NOT: @__const.test_unmatchedfp_uninit.uninit
-// PATTERN-O0: @__const.test_unmatchedfp_custom.custom = private unnamed_addr constant %union.unmatchedfp { double 0x400921FB54442D18 }, align
+// PATTERN-O0: @__const.test_unmatchedfp_custom.custom = private unnamed_addr constant %union.unmatchedfp { double f0x400921FB54442D18 }, align
// PATTERN-O1-NOT: @__const.test_unmatchedfp_custom.custom
-// ZERO-O0: @__const.test_unmatchedfp_custom.custom = private unnamed_addr constant %union.unmatchedfp { double 0x400921FB54442D18 }, align 8
+// ZERO-O0: @__const.test_unmatchedfp_custom.custom = private unnamed_addr constant %union.unmatchedfp { double f0x400921FB54442D18 }, align 8
// ZERO-O1-NOT: @__const.test_unmatchedfp_custom.custom
union unmatchedfp { float f; double d; };
enum emptyenum {};
@@ -443,14 +443,14 @@ TEST_UNINIT(fp16, __fp16);
// CHECK: %uninit = alloca half, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_fp16_uninit()
-// PATTERN: store half 0xHFFFF, ptr %uninit, align 2, !annotation [[AUTO_INIT]]
+// PATTERN: store half -nan(0x1FF), ptr %uninit, align 2, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_fp16_uninit()
-// ZERO: store half 0xH0000, ptr %uninit, align 2, !annotation [[AUTO_INIT]]
+// ZERO: store half 0.000000e+00, ptr %uninit, align 2, !annotation [[AUTO_INIT]]
TEST_BRACES(fp16, __fp16);
// CHECK-LABEL: @test_fp16_braces()
// CHECK: %braces = alloca half, align [[ALIGN:[0-9]*]]
-// CHECK-NEXT: store half 0xH0000, ptr %braces, align [[ALIGN]]
+// CHECK-NEXT: store half 0.000000e+00, ptr %braces, align [[ALIGN]]
// CHECK-NOT: !annotation
// CHECK-NEXT: call void @{{.*}}used{{.*}}%braces)
@@ -459,7 +459,7 @@ TEST_UNINIT(float, float);
// CHECK: %uninit = alloca float, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_float_uninit()
-// PATTERN: store float 0xFFFFFFFFE0000000, ptr %uninit, align 4, !annotation [[AUTO_INIT]]
+// PATTERN: store float -nan(0x3FFFFF), ptr %uninit, align 4, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_float_uninit()
// ZERO: store float 0.000000e+00, ptr %uninit, align 4, !annotation [[AUTO_INIT]]
@@ -475,7 +475,7 @@ TEST_UNINIT(double, double);
// CHECK: %uninit = alloca double, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_double_uninit()
-// PATTERN: store double 0xFFFFFFFFFFFFFFFF, ptr %uninit, align 8, !annotation [[AUTO_INIT]]
+// PATTERN: store double -nan(0x7FFFFFFFFFFFF), ptr %uninit, align 8, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_double_uninit()
// ZERO: store double 0.000000e+00, ptr %uninit, align 8, !annotation [[AUTO_INIT]]
@@ -491,14 +491,14 @@ TEST_UNINIT(longdouble, long double);
// CHECK: %uninit = alloca x86_fp80, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_longdouble_uninit()
-// PATTERN: store x86_fp80 0xKFFFFFFFFFFFFFFFFFFFF, ptr %uninit, align {{.+}}, !annotation [[AUTO_INIT]]
+// PATTERN: store x86_fp80 -nan(0x3FFFFFFFFFFFFFFF), ptr %uninit, align {{.+}}, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_longdouble_uninit()
-// ZERO: store x86_fp80 0xK00000000000000000000, ptr %uninit, align {{.+}}, !annotation [[AUTO_INIT]]
+// ZERO: store x86_fp80 0.000000e+00, ptr %uninit, align {{.+}}, !annotation [[AUTO_INIT]]
TEST_BRACES(longdouble, long double);
// CHECK-LABEL: @test_longdouble_braces()
// CHECK: %braces = alloca x86_fp80, align [[ALIGN:[0-9]*]]
-// CHECK-NEXT: store x86_fp80 0xK00000000000000000000, ptr %braces, align [[ALIGN]]
+// CHECK-NEXT: store x86_fp80 0.000000e+00, ptr %braces, align [[ALIGN]]
// CHECK-NOT: !annotation
// CHECK-NEXT: call void @{{.*}}used{{.*}}%braces)
@@ -1151,7 +1151,7 @@ TEST_UNINIT(atomicdouble, _Atomic(double));
// CHECK: %uninit = alloca double, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_atomicdouble_uninit()
-// PATTERN: store double 0xFFFFFFFFFFFFFFFF, ptr %uninit, align 8, !annotation [[AUTO_INIT]]
+// PATTERN: store double -nan(0x7FFFFFFFFFFFF), ptr %uninit, align 8, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_atomicdouble_uninit()
// ZERO: store double 0.000000e+00, ptr %uninit, align 8, !annotation [[AUTO_INIT]]
@@ -1195,9 +1195,9 @@ TEST_UNINIT(complexfloat, _Complex float);
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_complexfloat_uninit()
// PATTERN-O0: call void @llvm.memcpy{{.*}} @__const.test_complexfloat_uninit.uninit{{.+}}), !annotation [[AUTO_INIT]]
-// PATTERN-O1: store float 0xFFFFFFFFE0000000, ptr %uninit, align {{.+}}, !annotation [[AUTO_INIT]]
+// PATTERN-O1: store float -nan(0x3FFFFF), ptr %uninit, align {{.+}}, !annotation [[AUTO_INIT]]
// PATTERN-O1: %[[F2:[^ ]*]] = getelementptr inbounds {{.*}}%uninit, i64 4
-// PATTERN-O1: store float 0xFFFFFFFFE0000000, ptr %[[F2]], align {{.+}}, !annotation [[AUTO_INIT]]
+// PATTERN-O1: store float -nan(0x3FFFFF), ptr %[[F2]], align {{.+}}, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_complexfloat_uninit()
// ZERO-O0: call void @llvm.memset{{.*}}, i8 0, {{.+}}), !annotation [[AUTO_INIT]]
@@ -1219,9 +1219,9 @@ TEST_CUSTOM(complexfloat, _Complex float, { 3.1415926535897932384626433, 3.14159
// CHECK: %custom = alloca { float, float }, align [[ALIGN:[0-9]*]]
// CHECK-NEXT: %[[R:[^ ]*]] = getelementptr inbounds nuw { float, float }, ptr %custom, i32 0, i32 0
// CHECK-NEXT: %[[I:[^ ]*]] = getelementptr inbounds nuw { float, float }, ptr %custom, i32 0, i32 1
-// CHECK-NEXT: store float 0x400921FB60000000, ptr %[[R]], align [[ALIGN]]
+// CHECK-NEXT: store float f0x40490FDB, ptr %[[R]], align [[ALIGN]]
// CHECK-NOT: !annotation
-// CHECK-NEXT: store float 0x400921FB60000000, ptr %[[I]], align [[ALIGN]]
+// CHECK-NEXT: store float f0x40490FDB, ptr %[[I]], align [[ALIGN]]
// CHECK-NOT: !annotation
// CHECK-NEXT: call void @{{.*}}used{{.*}}%custom)
@@ -1250,9 +1250,9 @@ TEST_CUSTOM(complexdouble, _Complex double, { 3.1415926535897932384626433, 3.141
// CHECK: %custom = alloca { double, double }, align [[ALIGN:[0-9]*]]
// CHECK-NEXT: %[[R:[^ ]*]] = getelementptr inbounds nuw { double, double }, ptr %custom, i32 0, i32 0
// CHECK-NEXT: %[[I:[^ ]*]] = getelementptr inbounds nuw { double, double }, ptr %custom, i32 0, i32 1
-// CHECK-NEXT: store double 0x400921FB54442D18, ptr %[[R]], align [[ALIGN]]
+// CHECK-NEXT: store double f0x400921FB54442D18, ptr %[[R]], align [[ALIGN]]
// CHECK-NOT: !annotation
-// CHECK-NEXT: store double 0x400921FB54442D18, ptr %[[I]], align [[ALIGN]]
+// CHECK-NEXT: store double f0x400921FB54442D18, ptr %[[I]], align [[ALIGN]]
// CHECK-NOT: !annotation
// CHECK-NEXT: call void @{{.*}}used{{.*}}%custom)
@@ -1422,7 +1422,7 @@ TEST_UNINIT(matchingreverse, matchingreverse);
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_matchingreverse_uninit()
// PATTERN-O0: call void @llvm.memcpy{{.*}} @__const.test_matchingreverse_uninit.uninit{{.+}}), !annotation [[AUTO_INIT]]
-// PATTERN-O1: store float 0xFFFFFFFFE0000000, {{.+}}, !annotation [[AUTO_INIT]]
+// PATTERN-O1: store float -nan(0x3FFFFF), {{.+}}, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_matchingreverse_uninit()
// ZERO-O0: call void @llvm.memset{{.*}}, i8 0,{{.+}}), !annotation [[AUTO_INIT]]
// ZERO-O1: store i32 0, {{.*}} align 4, !annotation [[AUTO_INIT]]
@@ -1526,7 +1526,7 @@ TEST_CUSTOM(unmatchedfp, unmatchedfp, { .d = 3.1415926535897932384626433 });
// CHECK-O0: call void @llvm.memcpy
// CHECK-NOT: !annotation
// CHECK-O0: call void @{{.*}}used{{.*}}%custom)
-// PATTERN-O1: store double 0x400921FB54442D18, ptr %custom, align 8
+// PATTERN-O1: store double f0x400921FB54442D18, ptr %custom, align 8
// ZERO-O1: store i64 4614256656552045848, ptr %custom, align 8
// CHECK-NOT: !annotation
@@ -1627,7 +1627,7 @@ TEST_UNINIT(floatvec16, float __attribute__((vector_size(16))));
// CHECK: %uninit = alloca <4 x float>, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_floatvec16_uninit()
-// PATTERN: store <4 x float> splat (float 0xFFFFFFFFE0000000), ptr %uninit, align 16, !annotation [[AUTO_INIT]]
+// PATTERN: store <4 x float> splat (float -nan(0x3FFFFF)), ptr %uninit, align 16, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_floatvec16_uninit()
// ZERO: store <4 x float> zeroinitializer, ptr %uninit, align 16, !annotation [[AUTO_INIT]]
@@ -1641,7 +1641,7 @@ TEST_BRACES(floatvec16, float __attribute__((vector_size(16))));
TEST_CUSTOM(floatvec16, float __attribute__((vector_size(16))), { 3.1415926535897932384626433, 3.1415926535897932384626433, 3.1415926535897932384626433, 3.1415926535897932384626433 });
// CHECK-LABEL: @test_floatvec16_custom()
// CHECK: %custom = alloca <4 x float>, align [[ALIGN:[0-9]*]]
-// CHECK-NEXT: store <4 x float> splat (float 0x400921FB60000000), ptr %custom, align [[ALIGN]]
+// CHECK-NEXT: store <4 x float> splat (float f0x40490FDB), ptr %custom, align [[ALIGN]]
// CHECK-NOT: !annotation
// CHECK-NEXT: call void @{{.*}}used{{.*}}%custom)
@@ -1650,7 +1650,7 @@ TEST_UNINIT(doublevec32, double __attribute__((vector_size(32))));
// CHECK: %uninit = alloca <4 x double>, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_doublevec32_uninit()
-// PATTERN: store <4 x double> splat (double 0xFFFFFFFFFFFFFFFF), ptr %uninit, align 32, !annotation [[AUTO_INIT]]
+// PATTERN: store <4 x double> splat (double -nan(0x7FFFFFFFFFFFF)), ptr %uninit, align 32, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_doublevec32_uninit()
// ZERO: store <4 x double> zeroinitializer, ptr %uninit, align 32, !annotation [[AUTO_INIT]]
@@ -1664,7 +1664,7 @@ TEST_BRACES(doublevec32, double __attribute__((vector_size(32))));
TEST_CUSTOM(doublevec32, double __attribute__((vector_size(32))), { 3.1415926535897932384626433, 3.1415926535897932384626433, 3.1415926535897932384626433, 3.1415926535897932384626433 });
// CHECK-LABEL: @test_doublevec32_custom()
// CHECK: %custom = alloca <4 x double>, align [[ALIGN:[0-9]*]]
-// CHECK-NEXT: store <4 x double> splat (double 0x400921FB54442D18), ptr %custom, align [[ALIGN]]
+// CHECK-NEXT: store <4 x double> splat (double f0x400921FB54442D18), ptr %custom, align [[ALIGN]]
// CHECK-NOT: !annotation
// CHECK-NEXT: call void @{{.*}}used{{.*}}%custom)
@@ -1674,7 +1674,7 @@ TEST_UNINIT(doublevec24, double __attribute__((vector_size(24))));
// CHECK: %uninit = alloca <3 x double>, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_doublevec24_uninit()
-// PATTERN: store <3 x double> splat (double 0xFFFFFFFFFFFFFFFF), ptr %uninit, align 32, !annotation [[AUTO_INIT]]
+// PATTERN: store <3 x double> splat (double -nan(0x7FFFFFFFFFFFF)), ptr %uninit, align 32, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_doublevec24_uninit()
// ZERO: store <3 x double> zeroinitializer, ptr %uninit, align 32, !annotation [[AUTO_INIT]]
@@ -1684,7 +1684,7 @@ TEST_UNINIT(longdoublevec32, long double __attribute__((vector_size(sizeof(long
// CHECK: %uninit = alloca <2 x x86_fp80>, align
// CHECK-NEXT: call void @{{.*}}used{{.*}}%uninit)
// PATTERN-LABEL: @test_longdoublevec32_uninit()
-// PATTERN: store <2 x x86_fp80> splat (x86_fp80 0xKFFFFFFFFFFFFFFFFFFFF), ptr %uninit, align 32, !annotation [[AUTO_INIT]]
+// PATTERN: store <2 x x86_fp80> splat (x86_fp80 -nan(0x3FFFFFFFFFFFFFFF)), ptr %uninit, align 32, !annotation [[AUTO_INIT]]
// ZERO-LABEL: @test_longdoublevec32_uninit()
// ZERO: store <2 x x86_fp80> zeroinitializer, ptr %uninit, align 32, !annotation [[AUTO_INIT]]
diff --git a/clang/test/CodeGenCXX/blocks-cxx11.cpp b/clang/test/CodeGenCXX/blocks-cxx11.cpp
index 660aa5f50f472..c39a96bd7da9e 100644
--- a/clang/test/CodeGenCXX/blocks-cxx11.cpp
+++ b/clang/test/CodeGenCXX/blocks-cxx11.cpp
@@ -26,7 +26,7 @@ namespace test_float {
void test() {
const float x = 1;
takeABlock(^{ takeItByValue(x); });
- // CHECK: call void @_Z13takeItByValueIfEvT_(float noundef 1.0
+ // CHECK: call void @_Z13takeItByValueIfEvT_(float noundef 1.000000e+00
}
}
diff --git a/clang/test/CodeGenCXX/const-init.cpp b/clang/test/CodeGenCXX/const-init.cpp
index 18ed3df22f425..d915ea8488d42 100644
--- a/clang/test/CodeGenCXX/const-init.cpp
+++ b/clang/test/CodeGenCXX/const-init.cpp
@@ -56,7 +56,7 @@ namespace test2 {
}
// We don't expect to fold this in the frontend, but make sure it doesn't crash.
-// CHECK: @PR9558 = global float 0.000000e+0
+// CHECK: @PR9558 = global float 0.000000e+00
float PR9558 = reinterpret_cast<const float&>("asd");
// An initialized const automatic variable cannot be promoted to a constant
diff --git a/clang/test/CodeGenCXX/cxx11-user-defined-literal.cpp b/clang/test/CodeGenCXX/cxx11-user-defined-literal.cpp
index c8ab43194350e..3b18a9ad811c3 100644
--- a/clang/test/CodeGenCXX/cxx11-user-defined-literal.cpp
+++ b/clang/test/CodeGenCXX/cxx11-user-defined-literal.cpp
@@ -20,7 +20,7 @@ void f() {
// CHECK: call void @_Zli2_xPKcm({{.*}}, ptr noundef @[[s_bar]], i64 noundef 3)
// CHECK: call void @_Zli2_yw({{.*}} 97)
// CHECK: call void @_Zli2_zy({{.*}} 42)
- // CHECK: call void @_Zli2_fe({{.*}} x86_fp80 noundef 0xK3FFF8000000000000000)
+ // CHECK: call void @_Zli2_fe({{.*}} x86_fp80 noundef 1.000000e+00)
// CHECK: call void @_ZN1SD1Ev({{.*}})
// CHECK: call void @_ZN1SD1Ev({{.*}})
// CHECK: call void @_ZN1SD1Ev({{.*}})
diff --git a/clang/test/CodeGenCXX/float128-declarations.cpp b/clang/test/CodeGenCXX/float128-declarations.cpp
index 0f2e82bbfcd43..9652b336b5be0 100644
--- a/clang/test/CodeGenCXX/float128-declarations.cpp
+++ b/clang/test/CodeGenCXX/float128-declarations.cpp
@@ -92,46 +92,46 @@ int main(void) {
__float128 f8l = f4l++;
__float128 arr1l[] = { -1.q, -0.q, -11.q };
}
-// CHECK-DAG: @_ZN12_GLOBAL__N_13f1nE = internal global fp128 0xL00000000000000000000000000000000
-// CHECK-DAG: @_ZN12_GLOBAL__N_13f2nE = internal global fp128 0xL00000000000000004004080000000000
+// CHECK-DAG: @_ZN12_GLOBAL__N_13f1nE = internal global fp128 0.000000e+00
+// CHECK-DAG: @_ZN12_GLOBAL__N_13f2nE = internal global fp128 3.300000e+01
// CHECK-DAG: @_ZN12_GLOBAL__N_15arr1nE = internal global [10 x fp128]
-// CHECK-DAG: @_ZN12_GLOBAL__N_15arr2nE = internal global [3 x fp128] [fp128 0xL33333333333333333FFF333333333333, fp128 0xL00000000000000004000800000000000, fp128 0xL00000000000000004025176592E00000]
+// CHECK-DAG: @_ZN12_GLOBAL__N_15arr2nE = internal global [3 x fp128] [fp128 1.200000e+00, fp128 3.000000e+00, fp128 3.000000e+11]
// CHECK-DAG: define internal noundef fp128 @_ZN12_GLOBAL__N_16func1nERKu9__ieee128(ptr
-// CHECK-DAG: @f1f ={{.*}} global fp128 0xL00000000000000000000000000000000
-// CHECK-DAG: @f2f ={{.*}} global fp128 0xL33333333333333334004033333333333
+// CHECK-DAG: @f1f ={{.*}} global fp128 0.000000e+00
+// CHECK-DAG: @f2f ={{.*}} global fp128 3.240000e+01
// CHECK-DAG: @arr1f ={{.*}} global [10 x fp128]
-// CHECK-DAG: @arr2f ={{.*}} global [3 x fp128] [fp128 0xL3333333333333333BFFF333333333333, fp128 0xL0000000000000000C000800000000000, fp128 0xL0000000000000000C025176592E00000]
+// CHECK-DAG: @arr2f ={{.*}} global [3 x fp128] [fp128 -1.200000e+00, fp128 -3.000000e+00, fp128 -3.000000e+11]
// CHECK-DAG: declare noundef fp128 @_Z6func1fu9__ieee128(fp128 noundef)
// CHECK-DAG: define linkonce_odr void @_ZN2C1C2Eu9__ieee128(ptr {{[^,]*}} %this, fp128 noundef %arg)
// CHECK-DAG: define linkonce_odr noundef fp128 @_ZN2C16func2cEu9__ieee128(fp128 noundef %arg)
// CHECK-DAG: define linkonce_odr noundef fp128 @_Z6func1tIu9__ieee128ET_S0_(fp128 noundef %arg)
-// CHECK-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { fp128 0xL00000000000000004006080000000000 }
-// CHECK-DAG: store fp128 0xLF0AFD0EBFF292DCE42E0B38CDD83F26F, ptr %f1l, align 16
-// CHECK-DAG: store fp128 0xL00000000000000008000000000000000, ptr %f2l, align 16
-// CHECK-DAG: store fp128 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF, ptr %f3l, align 16
-// CHECK-DAG: store fp128 0xL0000000000000000BFFF000000000000, ptr %f5l, align 16
+// CHECK-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { fp128 1.320000e+02 }
+// CHECK-DAG: store fp128 1.230000e+222, ptr %f1l, align 16
+// CHECK-DAG: store fp128 -0.000000e+00, ptr %f2l, align 16
+// CHECK-DAG: store fp128 f0x7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF, ptr %f3l, align 16
+// CHECK-DAG: store fp128 -1.000000e+00, ptr %f5l, align 16
// CHECK-DAG: [[F4L:%[a-z0-9]+]] = load fp128, ptr %f4l
-// CHECK-DAG: [[INC:%[a-z0-9]+]] = fadd fp128 [[F4L]], 0xL00000000000000003FFF000000000000
+// CHECK-DAG: [[INC:%[a-z0-9]+]] = fadd fp128 [[F4L]], 1.000000e+00
// CHECK-DAG: store fp128 [[INC]], ptr %f4l
-// CHECK-X86-DAG: @_ZN12_GLOBAL__N_13f1nE = internal global fp128 0xL00000000000000000000000000000000
-// CHECK-X86-DAG: @_ZN12_GLOBAL__N_13f2nE = internal global fp128 0xL00000000000000004004080000000000
+// CHECK-X86-DAG: @_ZN12_GLOBAL__N_13f1nE = internal global fp128 0.000000e+00
+// CHECK-X86-DAG: @_ZN12_GLOBAL__N_13f2nE = internal global fp128 3.300000e+01
// CHECK-X86-DAG: @_ZN12_GLOBAL__N_15arr1nE = internal global [10 x fp128]
-// CHECK-X86-DAG: @_ZN12_GLOBAL__N_15arr2nE = internal global [3 x fp128] [fp128 0xL33333333333333333FFF333333333333, fp128 0xL00000000000000004000800000000000, fp128 0xL00000000000000004025176592E00000]
+// CHECK-X86-DAG: @_ZN12_GLOBAL__N_15arr2nE = internal global [3 x fp128] [fp128 1.200000e+00, fp128 3.000000e+00, fp128 3.000000e+11]
// CHECK-X86-DAG: define internal noundef fp128 @_ZN12_GLOBAL__N_16func1nERKg(ptr
-// CHECK-X86-DAG: @f1f ={{.*}} global fp128 0xL00000000000000000000000000000000
-// CHECK-X86-DAG: @f2f ={{.*}} global fp128 0xL33333333333333334004033333333333
+// CHECK-X86-DAG: @f1f ={{.*}} global fp128 0.000000e+00
+// CHECK-X86-DAG: @f2f ={{.*}} global fp128 3.240000e+01
// CHECK-X86-DAG: @arr1f ={{.*}} global [10 x fp128]
-// CHECK-X86-DAG: @arr2f ={{.*}} global [3 x fp128] [fp128 0xL3333333333333333BFFF333333333333, fp128 0xL0000000000000000C000800000000000, fp128 0xL0000000000000000C025176592E00000]
+// CHECK-X86-DAG: @arr2f ={{.*}} global [3 x fp128] [fp128 -1.200000e+00, fp128 -3.000000e+00, fp128 -3.000000e+11]
// CHECK-X86-DAG: declare noundef fp128 @_Z6func1fg(fp128 noundef)
// CHECK-X86-DAG: define linkonce_odr void @_ZN2C1C2Eg(ptr {{[^,]*}} %this, fp128 noundef %arg)
// CHECK-X86-DAG: define linkonce_odr noundef fp128 @_ZN2C16func2cEg(fp128 noundef %arg)
// CHECK-X86-DAG: define linkonce_odr noundef fp128 @_Z6func1tIgET_S0_(fp128 noundef %arg)
-// CHECK-X86-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { fp128 0xL00000000000000004006080000000000 }
-// CHECK-X86-DAG: store fp128 0xLF0AFD0EBFF292DCE42E0B38CDD83F26F, ptr %f1l, align 16
-// CHECK-X86-DAG: store fp128 0xL00000000000000008000000000000000, ptr %f2l, align 16
-// CHECK-X86-DAG: store fp128 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF, ptr %f3l, align 16
-// CHECK-X86-DAG: store fp128 0xL0000000000000000BFFF000000000000, ptr %f5l, align 16
+// CHECK-X86-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { fp128 1.320000e+02 }
+// CHECK-X86-DAG: store fp128 1.230000e+222, ptr %f1l, align 16
+// CHECK-X86-DAG: store fp128 -0.000000e+00, ptr %f2l, align 16
+// CHECK-X86-DAG: store fp128 f0x7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF, ptr %f3l, align 16
+// CHECK-X86-DAG: store fp128 -1.000000e+00, ptr %f5l, align 16
// CHECK-X86-DAG: [[F4L:%[a-z0-9]+]] = load fp128, ptr %f4l
-// CHECK-X86-DAG: [[INC:%[a-z0-9]+]] = fadd fp128 [[F4L]], 0xL00000000000000003FFF000000000000
+// CHECK-X86-DAG: [[INC:%[a-z0-9]+]] = fadd fp128 [[F4L]], 1.000000e+00
// CHECK-X86-DAG: store fp128 [[INC]], ptr %f4l
diff --git a/clang/test/CodeGenCXX/float16-declarations.cpp b/clang/test/CodeGenCXX/float16-declarations.cpp
index b395beb263e15..afcaafa1545f7 100644
--- a/clang/test/CodeGenCXX/float16-declarations.cpp
+++ b/clang/test/CodeGenCXX/float16-declarations.cpp
@@ -7,16 +7,16 @@
namespace {
_Float16 f1n;
-// CHECK-DAG: @_ZN12_GLOBAL__N_13f1nE = internal global half 0xH0000, align 2
+// CHECK-DAG: @_ZN12_GLOBAL__N_13f1nE = internal global half 0.000000e+00, align 2
_Float16 f2n = 33.f16;
-// CHECK-DAG: @_ZN12_GLOBAL__N_13f2nE = internal global half 0xH5020, align 2
+// CHECK-DAG: @_ZN12_GLOBAL__N_13f2nE = internal global half 3.300000e+01, align 2
_Float16 arr1n[10];
// CHECK-AARCH64-DAG: @_ZN12_GLOBAL__N_15arr1nE = internal global [10 x half] zeroinitializer, align 2
_Float16 arr2n[] = { 1.2, 3.0, 3.e4 };
-// CHECK-DAG: @_ZN12_GLOBAL__N_15arr2nE = internal global [3 x half] [half 0xH3CCD, half 0xH4200, half 0xH7753], align 2
+// CHECK-DAG: @_ZN12_GLOBAL__N_15arr2nE = internal global [3 x half] [half 1.200200e+00, half 3.000000e+00, half 3.000000e+04], align 2
const volatile _Float16 func1n(const _Float16 &arg) {
return arg + f2n + arr1n[4] - arr2n[1];
@@ -27,16 +27,16 @@ namespace {
/* File */
_Float16 f1f;
-// CHECK-AARCH64-DAG: @f1f = dso_local global half 0xH0000, align 2
+// CHECK-AARCH64-DAG: @f1f = dso_local global half 0.000000e+00, align 2
_Float16 f2f = 32.4;
-// CHECK-DAG: @f2f = dso_local global half 0xH500D, align 2
+// CHECK-DAG: @f2f = dso_local global half 3.240630e+01, align 2
_Float16 arr1f[10];
// CHECK-AARCH64-DAG: @arr1f = dso_local global [10 x half] zeroinitializer, align 2
_Float16 arr2f[] = { -1.2, -3.0, -3.e4 };
-// CHECK-DAG: @arr2f = dso_local global [3 x half] [half 0xHBCCD, half 0xHC200, half 0xHF753], align 2
+// CHECK-DAG: @arr2f = dso_local global [3 x half] [half -1.200200e+00, half -3.000000e+00, half -3.000000e+04], align 2
_Float16 func1f(_Float16 arg);
@@ -89,36 +89,36 @@ extern int printf (const char *__restrict __format, ...);
int main(void) {
_Float16 f1l = 1e3f16;
-// CHECK-DAG: store half 0xH63D0, ptr %{{.*}}, align 2
+// CHECK-DAG: store half 1.000000e+03, ptr %{{.*}}, align 2
_Float16 f2l = -0.f16;
-// CHECK-DAG: store half 0xH8000, ptr %{{.*}}, align 2
+// CHECK-DAG: store half -0.000000e+00, ptr %{{.*}}, align 2
_Float16 f3l = 1.000976562;
-// CHECK-DAG: store half 0xH3C01, ptr %{{.*}}, align 2
+// CHECK-DAG: store half 1.000980e+00, ptr %{{.*}}, align 2
C1 c1(f1l);
// CHECK-DAG: [[F1L:%[a-z0-9]+]] = load half, ptr %{{.*}}, align 2
// CHECK-DAG: call void @_ZN2C1C2EDF16_(ptr {{[^,]*}} %{{.*}}, half noundef %{{.*}})
S1<_Float16> s1 = { 132.f16 };
-// CHECK-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { half 0xH5820 }, align 2
+// CHECK-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { half 1.320000e+02 }, align 2
// CHECK-DAG: call void @llvm.memcpy.p0.p0.i64(ptr align 2 %{{.*}}, ptr align 2 @__const.main.s1, i64 2, i1 false)
_Float16 f4l = func1n(f1l) + func1f(f2l) + c1.func1c(f3l) + c1.func2c(f1l) +
func1t(f1l) + s1.mem2 - f1n + f2n;
auto f5l = -1.f16, *f6l = &f2l, f7l = func1t(f3l);
-// CHECK-DAG: store half 0xHBC00, ptr %{{.*}}, align 2
+// CHECK-DAG: store half -1.000000e+00, ptr %{{.*}}, align 2
// CHECK-DAG: store ptr %{{.*}}, ptr %{{.*}}, align 8
_Float16 f8l = f4l++;
// CHECK-DAG: %{{.*}} = load half, ptr %{{.*}}, align 2
-// CHECK-DAG: [[INC:%[a-z0-9]+]] = fadd half {{.*}}, 0xH3C00
+// CHECK-DAG: [[INC:%[a-z0-9]+]] = fadd half {{.*}}, 1.000000e+00
// CHECK-DAG: store half [[INC]], ptr %{{.*}}, align 2
_Float16 arr1l[] = { -1.f16, -0.f16, -11.f16 };
-// CHECK-DAG: @__const.main.arr1l = private unnamed_addr constant [3 x half] [half 0xHBC00, half 0xH8000, half 0xHC980], align 2
+// CHECK-DAG: @__const.main.arr1l = private unnamed_addr constant [3 x half] [half -1.000000e+00, half -0.000000e+00, half -1.100000e+01], align 2
float cvtf = f2n;
//CHECK-DAG: [[H2F:%[a-z0-9]+]] = fpext half {{%[0-9]+}} to float
@@ -134,9 +134,9 @@ int main(void) {
//CHECK-AARCh64-DAG: store fp128 [[H2LD]], ptr %{{.*}}, align 16
_Float16 f2h = 42.0f;
-//CHECK-DAG: store half 0xH5140, ptr %{{.*}}, align 2
+//CHECK-DAG: store half 4.200000e+01, ptr %{{.*}}, align 2
_Float16 d2h = 42.0;
-//CHECK-DAG: store half 0xH5140, ptr %{{.*}}, align 2
+//CHECK-DAG: store half 4.200000e+01, ptr %{{.*}}, align 2
_Float16 ld2h = 42.0l;
-//CHECK-DAG:store half 0xH5140, ptr %{{.*}}, align 2
+//CHECK-DAG:store half 4.200000e+01, ptr %{{.*}}, align 2
}
diff --git a/clang/test/CodeGenCXX/ibm128-declarations.cpp b/clang/test/CodeGenCXX/ibm128-declarations.cpp
index 61ff6fff2d0a7..e1735b5372afe 100644
--- a/clang/test/CodeGenCXX/ibm128-declarations.cpp
+++ b/clang/test/CodeGenCXX/ibm128-declarations.cpp
@@ -76,7 +76,7 @@ int main(void) {
// CHECK: %struct.T1 = type { ppc_fp128 }
// CHECK: @arrgf = global [10 x ppc_fp128] zeroinitializer, align 16
-// CHECK: @gf = global ppc_fp128 0xM40080000000000000000000000000000, align 16
+// CHECK: @gf = global ppc_fp128 3.000000e+00, align 16
// CHECK: @_ZN5CTest3scfE = external constant ppc_fp128, align 16
// CHECK: define dso_local noundef ppc_fp128 @_Z10func_arithggg(ppc_fp128 noundef %a, ppc_fp128 noundef %b, ppc_fp128 noundef %c)
diff --git a/clang/test/CodeGenCXX/lambda-deterministic-captures.cpp b/clang/test/CodeGenCXX/lambda-deterministic-captures.cpp
index ab44f43720832..d9b4002a94c89 100644
--- a/clang/test/CodeGenCXX/lambda-deterministic-captures.cpp
+++ b/clang/test/CodeGenCXX/lambda-deterministic-captures.cpp
@@ -17,11 +17,11 @@ void foo() {
// CHECK: define{{.*}} void @_Z3foov
// CHECK: getelementptr inbounds nuw %{{.+}}, ptr %{{.+}}, i32 0, i32 1
-// CHECK-NEXT: store float 0.000
+// CHECK-NEXT: store float 0.000000e+00
// CHECK-NEXT: getelementptr inbounds nuw %{{.+}}, ptr %{{.+}}, i32 0, i32 2
-// CHECK-NEXT: store float 1.000
+// CHECK-NEXT: store float 1.000000e+00
// CHECK-NEXT: getelementptr inbounds nuw %{{.+}}, ptr %{{.+}}, i32 0, i32 3
-// CHECK-NEXT: store float 2.000
+// CHECK-NEXT: store float 2.000000e+00
// The lambda body. Reverse iteration when the captures aren't deterministic
// causes these to be laid out differently in the lambda.
diff --git a/clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
index 740b80afdb609..4bba5ccf47ef0 100644
--- a/clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
+++ b/clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
@@ -59,7 +59,7 @@ export void call2() {
// CHECK-LABEL: define void {{.*}}call3
// CHECK: [[A:%.*]] = alloca <1 x float>, align 4
// CHECK-NEXT: [[B:%.*]] = alloca [1 x i32], align 4
-// CHECK-NEXT: store <1 x float> splat (float 0x3FF3333340000000), ptr [[A]], align 4
+// CHECK-NEXT: store <1 x float> splat (float 1.200000e+00), ptr [[A]], align 4
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B]], ptr align 4 {{.*}}, i32 4, i1 false)
// CHECK-NEXT: [[C:%.*]] = load <1 x float>, ptr [[A]], align 4
// CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [1 x i32], ptr [[B]], i32 0, i32 0
diff --git a/clang/test/CodeGenHLSL/BasicFeatures/frem_modulo.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/frem_modulo.hlsl
index 393efcc360d08..db37e7a02d38e 100644
--- a/clang/test/CodeGenHLSL/BasicFeatures/frem_modulo.hlsl
+++ b/clang/test/CodeGenHLSL/BasicFeatures/frem_modulo.hlsl
@@ -7,13 +7,13 @@
half2 half_vec_mod_by_int(half2 p1) {
// CHECK-LABEL: half_vec_mod_by_int
-// CHECK: %rem = frem reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}, splat (half 0xH4000)
+// CHECK: %rem = frem reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}, splat (half 2.000000e+00)
return p1 % 2;
}
half2 half_vec_mod_by_float(half2 p1) {
// CHECK-LABEL: half_vec_mod_by_float
-// CHECK: %rem = frem reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}, splat (half 0xH4000)
+// CHECK: %rem = frem reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}, splat (half 2.000000e+00)
return p1 % (half)2.0;
}
@@ -33,13 +33,13 @@
half half_vec_mod_by_int(half p1) {
// CHECK-LABEL: half_vec_mod_by_int
-// CHECK: %rem = frem reassoc nnan ninf nsz arcp afn half %{{.*}}, 0xH4000
+// CHECK: %rem = frem reassoc nnan ninf nsz arcp afn half %{{.*}}, 2.000000e+00
return p1 % 2;
}
half half_mod_by_float(half p1) {
// CHECK-LABEL: half_mod_by_float
-// CHECK: %rem = frem reassoc nnan ninf nsz arcp afn half %{{.*}}, 0xH4000
+// CHECK: %rem = frem reassoc nnan ninf nsz arcp afn half %{{.*}}, 2.000000e+00
return p1 % (half)2.0;
}
diff --git a/clang/test/CodeGenHLSL/Operators/logical-not.hlsl b/clang/test/CodeGenHLSL/Operators/logical-not.hlsl
index d5130ab88ea64..20d3b0edf3807 100644
--- a/clang/test/CodeGenHLSL/Operators/logical-not.hlsl
+++ b/clang/test/CodeGenHLSL/Operators/logical-not.hlsl
@@ -17,7 +17,7 @@ export int32_t3 case2(int32_t3 b) {
}
// CHECK-LABEL: case3
-// CHECK: [[ToBool:%.*]] = fcmp reassoc nnan ninf nsz arcp afn une half {{.*}}, 0xH0000
+// CHECK: [[ToBool:%.*]] = fcmp reassoc nnan ninf nsz arcp afn une half {{.*}}, 0.000000e+00
// CHECK-NEXT: [[BoolCmp:%.*]] = xor i1 [[ToBool]], true
// CHECK-NEXT: {{.*}} = uitofp i1 [[BoolCmp]] to half
export float16_t case3(float16_t b) {
diff --git a/clang/test/CodeGenHLSL/RootSignature.hlsl b/clang/test/CodeGenHLSL/RootSignature.hlsl
index eaff3a9e73305..018da5226e1eb 100644
--- a/clang/test/CodeGenHLSL/RootSignature.hlsl
+++ b/clang/test/CodeGenHLSL/RootSignature.hlsl
@@ -77,7 +77,7 @@ void RootDescriptorsEntry() {}
// checking mipLODBias, maxAnisotropy, comparisonFunc, borderColor
// note: the hex value is the float bit representation of 12.45
-// CHECK-SAME: float 0x4028E66660000000, i32 9, i32 3, i32 2,
+// CHECK-SAME: float 1.245000e+01, i32 9, i32 3, i32 2,
// checking minLOD, maxLOD
// CHECK-SAME: float -1.280000e+02, float 1.280000e+02,
diff --git a/clang/test/CodeGenHLSL/builtins/D3DCOLORtoUBYTE4.hlsl b/clang/test/CodeGenHLSL/builtins/D3DCOLORtoUBYTE4.hlsl
index 3c9e35a2543a7..576cf217efc67 100644
--- a/clang/test/CodeGenHLSL/builtins/D3DCOLORtoUBYTE4.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/D3DCOLORtoUBYTE4.hlsl
@@ -4,7 +4,7 @@
// CHECK-LABEL: D3DCOLORtoUBYTE4
int4 test_D3DCOLORtoUBYTE4(float4 p1) {
- // CHECK: %[[SCALED:.*]] = fmul [[FMFLAGS:.*]][[FLOAT_TYPE:<4 x float>]] %{{.*}}, splat (float 0x406FE01000000000)
+ // CHECK: %[[SCALED:.*]] = fmul [[FMFLAGS:.*]][[FLOAT_TYPE:<4 x float>]] %{{.*}}, splat (float f0x437F0080)
// CHECK: %[[CONVERTED:.*]] = fptosi [[FLOAT_TYPE]] %[[SCALED]] to [[INT_TYPE:<4 x i32>]]
// CHECK: %[[SHUFFLED:.*]] = shufflevector [[INT_TYPE]] %[[CONVERTED]], [[INT_TYPE]] poison, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
// CHECK: ret [[INT_TYPE]] %[[SHUFFLED]]
diff --git a/clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl b/clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
index 06645f2294cde..94f9f58cfd29f 100644
--- a/clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/VectorSwizzles.hlsl
@@ -70,7 +70,7 @@ float3 Double(float3 vec, float a, float b) {
// CHECK-NEXT: [[TmpVec0:%.*]] = insertelement <4 x half> poison, half [[A]], i32 0
// CHECK-NEXT: [[B:%.*]] = load half, ptr [[BAddr]], align 2
// CHECK-NEXT: [[TmpVec1:%.*]] = insertelement <4 x half> [[TmpVec0]], half [[B]], i32 1
-// CHECK-NEXT: [[TmpVec2:%.*]] = insertelement <4 x half> %vecinit1, half 0xH4ADF, i32 2
+// CHECK-NEXT: [[TmpVec2:%.*]] = insertelement <4 x half> %vecinit1, half 1.374220e+01, i32 2
// CHECK-NEXT: [[A:%.*]] = load half, ptr [[AAddr]], align 2
// CHECK-NEXT: [[TmpVec3:%.*]] = insertelement <4 x half> [[TmpVec2]], half [[A]], i32 3
diff --git a/clang/test/CodeGenHLSL/builtins/dst.hlsl b/clang/test/CodeGenHLSL/builtins/dst.hlsl
index 681eb65fb7a48..911da2775a6e3 100644
--- a/clang/test/CodeGenHLSL/builtins/dst.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/dst.hlsl
@@ -22,7 +22,7 @@ float4 dstWithFloat(float4 p1, float4 p2)
// CHECK: [[VECEXT:%.*]] = extractelement <4 x half> [[PADDR:%.*]], i32 1
// CHECK: [[VECEXT1:%.*]] = extractelement <4 x half> [[QADDR:%.*]], i32 1
// CHECK: [[MULRES:%.*]] = fmul {{[A-Za-z ]*}} half [[VECEXT]], [[VECEXT1]]
-// CHECK: [[VECINIT:%.*]] = insertelement <4 x half> <half 0xH3C00, half poison, half poison, half poison>, half [[MULRES]], i32 1
+// CHECK: [[VECINIT:%.*]] = insertelement <4 x half> <half 1.000000e+00, half poison, half poison, half poison>, half [[MULRES]], i32 1
// CHECK: [[VECINIT2:%.*]] = extractelement <4 x half> [[PADDR2:%.*]], i32 2
// CHECK: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT]], half [[VECINIT2]], i32 2
// CHECK: [[VECINIT4:%.*]] = extractelement <4 x half> [[QADDR3:%.*]], i32 3
diff --git a/clang/test/CodeGenHLSL/builtins/faceforward.hlsl b/clang/test/CodeGenHLSL/builtins/faceforward.hlsl
index 261454e8bc152..be0baf20deffb 100644
--- a/clang/test/CodeGenHLSL/builtins/faceforward.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/faceforward.hlsl
@@ -7,7 +7,7 @@
// CHECK-LABEL: test_faceforward_half
// CHECK: %hlsl.dot.i = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
-// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %hlsl.dot.i, 0xH0000
+// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %hlsl.dot.i, 0.000000e+00
// CHECK: %fneg.i = fneg reassoc nnan ninf nsz arcp afn half %{{.*}}
// CHECK: %hlsl.select.i = select reassoc nnan ninf nsz arcp afn i1 %cmp.i, half %{{.*}}, half %fneg.i
// CHECK: ret half %hlsl.select.i
@@ -16,7 +16,7 @@ half test_faceforward_half(half N, half I, half Ng) { return faceforward(N, I, N
// CHECK-LABEL: test_faceforward_half2
// DXCHECK: %hlsl.dot.i = call reassoc nnan ninf nsz arcp afn half @llvm.[[ICF:dx]].fdot.v2f16(<2 x half> %{{.*}}, <2 x half> %{{.*}})
// SPVCHECK: %hlsl.dot.i = call reassoc nnan ninf nsz arcp afn half @llvm.[[ICF:spv]].fdot.v2f16(<2 x half> %{{.*}}, <2 x half> %{{.*}})
-// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %hlsl.dot.i, 0xH0000
+// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %hlsl.dot.i, 0.000000e+00
// CHECK: %fneg.i = fneg reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}
// CHECK: %hlsl.select.i = select reassoc nnan ninf nsz arcp afn i1 %cmp.i, <2 x half> %{{.*}}, <2 x half> %fneg.i
// CHECK: ret <2 x half> %hlsl.select.i
@@ -24,7 +24,7 @@ half2 test_faceforward_half2(half2 N, half2 I, half2 Ng) { return faceforward(N,
// CHECK-LABEL: test_faceforward_half3
// CHECK: %hlsl.dot.i = call reassoc nnan ninf nsz arcp afn half @llvm.[[ICF]].fdot.v3f16(<3 x half> %{{.*}}, <3 x half> %{{.*}})
-// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %hlsl.dot.i, 0xH0000
+// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %hlsl.dot.i, 0.000000e+00
// CHECK: %fneg.i = fneg reassoc nnan ninf nsz arcp afn <3 x half> %{{.*}}
// CHECK: %hlsl.select.i = select reassoc nnan ninf nsz arcp afn i1 %cmp.i, <3 x half> %{{.*}}, <3 x half> %fneg.i
// CHECK: ret <3 x half> %hlsl.select.i
@@ -32,7 +32,7 @@ half3 test_faceforward_half3(half3 N, half3 I, half3 Ng) { return faceforward(N,
// CHECK-LABEL: test_faceforward_half4
// CHECK: %hlsl.dot.i = call reassoc nnan ninf nsz arcp afn half @llvm.[[ICF]].fdot.v4f16(<4 x half> %{{.*}}, <4 x half> %{{.*}})
-// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %hlsl.dot.i, 0xH0000
+// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %hlsl.dot.i, 0.000000e+00
// CHECK: %fneg.i = fneg reassoc nnan ninf nsz arcp afn <4 x half> %{{.*}}
// CHECK: %hlsl.select.i = select reassoc nnan ninf nsz arcp afn i1 %cmp.i, <4 x half> %{{.*}}, <4 x half> %fneg.i
// CHECK: ret <4 x half> %hlsl.select.i
diff --git a/clang/test/CodeGenHLSL/builtins/lit.hlsl b/clang/test/CodeGenHLSL/builtins/lit.hlsl
index 364c2e8794ea2..541b332bf5cad 100644
--- a/clang/test/CodeGenHLSL/builtins/lit.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/lit.hlsl
@@ -1,16 +1,16 @@
// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple dxil-pc-shadermodel6.3-library %s -fnative-half-type -fnative-int16-type -emit-llvm -o - | FileCheck %s
// CHECK-LABEL: test_lit_half
-// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %{{.*}}, 0xH0000
-// CHECK: %hlsl.select.i = select reassoc nnan ninf nsz arcp afn i1 %{{.*}}, half 0xH0000, half %{{.*}}
-// CHECK: %vecinit.i = insertelement <4 x half> <half 0xH3C00, half poison, half poison, half poison>, half %{{.*}}, i32 1
-// CHECK: %vecinit2.i = insertelement <4 x half> %{{.*}}, half 0xH3C00, i32 3
-// CHECK: %cmp4.i = fcmp reassoc nnan ninf nsz arcp afn olt half %{{.*}}, 0xH0000
+// CHECK: %cmp.i = fcmp reassoc nnan ninf nsz arcp afn olt half %{{.*}}, 0.000000e+00
+// CHECK: %hlsl.select.i = select reassoc nnan ninf nsz arcp afn i1 %{{.*}}, half 0.000000e+00, half %{{.*}}
+// CHECK: %vecinit.i = insertelement <4 x half> <half 1.000000e+00, half poison, half poison, half poison>, half %{{.*}}, i32 1
+// CHECK: %vecinit2.i = insertelement <4 x half> %{{.*}}, half 1.000000e+00, i32 3
+// CHECK: %cmp4.i = fcmp reassoc nnan ninf nsz arcp afn olt half %{{.*}}, 0.000000e+00
// CHECK: %hlsl.or.i = or i1 %{{.*}}, %cmp4.i
// CHECK: [[LOG:%.*]] = call reassoc nnan ninf nsz arcp afn half @llvm.log.f16(half %{{.*}})
// CHECK: %mul.i = fmul reassoc nnan ninf nsz arcp afn half [[LOG]], %{{.*}}
// CHECK: [[EXP:%.*]] = call reassoc nnan ninf nsz arcp afn half @llvm.exp.f16(half %mul.i)
-// CHECK: %hlsl.select7.i = select reassoc nnan ninf nsz arcp afn i1 %{{.*}}, half 0xH0000, half %{{.*}}
+// CHECK: %hlsl.select7.i = select reassoc nnan ninf nsz arcp afn i1 %{{.*}}, half 0.000000e+00, half %{{.*}}
// CHECK: [[PTR:%.*]] = getelementptr <4 x half>, ptr %Result.i, i32 0, i32 2
// CHECK: store half %hlsl.select7.i, ptr [[PTR]], align 2
// CHECK: ret <4 x half> %{{.*}}
diff --git a/clang/test/CodeGenHLSL/builtins/rcp-builtin.hlsl b/clang/test/CodeGenHLSL/builtins/rcp-builtin.hlsl
index 2cc38203bd060..6e6f4a964b4ac 100644
--- a/clang/test/CodeGenHLSL/builtins/rcp-builtin.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/rcp-builtin.hlsl
@@ -2,7 +2,7 @@
// CHECK-LABEL: builtin_rcp_half
-// CHECK: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn half 0xH3C00, %{{.*}}
+// CHECK: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn half 1.000000e+00, %{{.*}}
// CHECK: ret half %hlsl.rcp
half builtin_rcp_half(half p0) {
return __builtin_hlsl_elementwise_rcp(p0);
diff --git a/clang/test/CodeGenHLSL/builtins/rcp.hlsl b/clang/test/CodeGenHLSL/builtins/rcp.hlsl
index c9c47c737114d..a18de8dea462e 100644
--- a/clang/test/CodeGenHLSL/builtins/rcp.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/rcp.hlsl
@@ -15,7 +15,7 @@
// DXIL_NATIVE_HALF: define hidden noundef nofpclass(nan inf) half @
// SPIR_NATIVE_HALF: define hidden spir_func noundef nofpclass(nan inf) half @
-// NATIVE_HALF: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn half 0xH3C00, %{{.*}}
+// NATIVE_HALF: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn half 1.000000e+00, %{{.*}}
// NATIVE_HALF: ret half %hlsl.rcp
// DXIL_NO_HALF: define hidden noundef nofpclass(nan inf) float @
// SPIR_NO_HALF: define hidden spir_func noundef nofpclass(nan inf) float @
@@ -25,7 +25,7 @@ half test_rcp_half(half p0) { return rcp(p0); }
// DXIL_NATIVE_HALF: define hidden noundef nofpclass(nan inf) <2 x half> @
// SPIR_NATIVE_HALF: define hidden spir_func noundef nofpclass(nan inf) <2 x half> @
-// NATIVE_HALF: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn <2 x half> splat (half 0xH3C00), %{{.*}}
+// NATIVE_HALF: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn <2 x half> splat (half 1.000000e+00), %{{.*}}
// NATIVE_HALF: ret <2 x half> %hlsl.rcp
// DXIL_NO_HALF: define hidden noundef nofpclass(nan inf) <2 x float> @
// SPIR_NO_HALF: define hidden spir_func noundef nofpclass(nan inf) <2 x float> @
@@ -35,7 +35,7 @@ half2 test_rcp_half2(half2 p0) { return rcp(p0); }
// DXIL_NATIVE_HALF: define hidden noundef nofpclass(nan inf) <3 x half> @
// SPIR_NATIVE_HALF: define hidden spir_func noundef nofpclass(nan inf) <3 x half> @
-// NATIVE_HALF: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn <3 x half> splat (half 0xH3C00), %{{.*}}
+// NATIVE_HALF: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn <3 x half> splat (half 1.000000e+00), %{{.*}}
// NATIVE_HALF: ret <3 x half> %hlsl.rcp
// DXIL_NO_HALF: define hidden noundef nofpclass(nan inf) <3 x float> @
// SPIR_NO_HALF: define hidden spir_func noundef nofpclass(nan inf) <3 x float> @
@@ -45,7 +45,7 @@ half3 test_rcp_half3(half3 p0) { return rcp(p0); }
// DXIL_NATIVE_HALF: define hidden noundef nofpclass(nan inf) <4 x half> @
// SPIR_NATIVE_HALF: define hidden spir_func noundef nofpclass(nan inf) <4 x half> @
-// NATIVE_HALF: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn <4 x half> splat (half 0xH3C00), %{{.*}}
+// NATIVE_HALF: %hlsl.rcp = fdiv reassoc nnan ninf nsz arcp afn <4 x half> splat (half 1.000000e+00), %{{.*}}
// NATIVE_HALF: ret <4 x half> %hlsl.rcp
// DXIL_NO_HALF: define hidden noundef nofpclass(nan inf) <4 x float> @
// SPIR_NO_HALF: define hidden spir_func noundef nofpclass(nan inf) <4 x float> @
diff --git a/clang/test/CodeGenHLSL/builtins/reflect.hlsl b/clang/test/CodeGenHLSL/builtins/reflect.hlsl
index 259490afb1c78..b794ea6b33f3a 100644
--- a/clang/test/CodeGenHLSL/builtins/reflect.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/reflect.hlsl
@@ -9,7 +9,7 @@
// CHECK-LABEL: define hidden noundef nofpclass(nan inf) half @_Z17test_reflect_halfDhDh(
// CHECK-SAME: half noundef nofpclass(nan inf) [[I:%.*]], half noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[I]], 0xH4000
+// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[I]], 2.000000e+00
// CHECK-NEXT: [[TMP0:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[N]], [[N]]
// CHECK-NEXT: [[MUL2_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[TMP0]], [[MUL_I]]
// CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half [[I]], [[MUL2_I]]
@@ -18,7 +18,7 @@
// SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z17test_reflect_halfDhDh(
// SPVCHECK-SAME: half noundef nofpclass(nan inf) [[I:%.*]], half noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// SPVCHECK-NEXT: [[ENTRY:.*:]]
-// SPVCHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[I]], 0xH4000
+// SPVCHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[I]], 2.000000e+00
// SPVCHECK-NEXT: [[TMP0:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[N]], [[N]]
// SPVCHECK-NEXT: [[MUL2_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[TMP0]], [[MUL_I]]
// SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half [[I]], [[MUL2_I]]
@@ -32,7 +32,7 @@ half test_reflect_half(half I, half N) {
// CHECK-SAME: <2 x half> noundef nofpclass(nan inf) [[I:%.*]], <2 x half> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v2f16(<2 x half> nofpclass(nan inf) [[I]], <2 x half> nofpclass(nan inf) [[N]])
-// CHECK-NEXT: [[DOTSCALAR:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_DOT_I]], 0xH4000
+// CHECK-NEXT: [[DOTSCALAR:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_DOT_I]], 2.000000e+00
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x half> poison, half [[DOTSCALAR]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x half> [[TMP0]], <2 x half> poison, <2 x i32> zeroinitializer
// CHECK-NEXT: [[MUL1_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> [[TMP1]], [[N]]
@@ -53,7 +53,7 @@ half2 test_reflect_half2(half2 I, half2 N) {
// CHECK-SAME: <3 x half> noundef nofpclass(nan inf) [[I:%.*]], <3 x half> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v3f16(<3 x half> nofpclass(nan inf) [[I]], <3 x half> nofpclass(nan inf) [[N]])
-// CHECK-NEXT: [[DOTSCALAR:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_DOT_I]], 0xH4000
+// CHECK-NEXT: [[DOTSCALAR:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_DOT_I]], 2.000000e+00
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <3 x half> poison, half [[DOTSCALAR]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x half> [[TMP0]], <3 x half> poison, <3 x i32> zeroinitializer
// CHECK-NEXT: [[MUL1_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> [[TMP1]], [[N]]
@@ -74,7 +74,7 @@ half3 test_reflect_half3(half3 I, half3 N) {
// CHECK-SAME: <4 x half> noundef nofpclass(nan inf) [[I:%.*]], <4 x half> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v4f16(<4 x half> nofpclass(nan inf) [[I]], <4 x half> nofpclass(nan inf) [[N]])
-// CHECK-NEXT: [[DOTSCALAR:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_DOT_I]], 0xH4000
+// CHECK-NEXT: [[DOTSCALAR:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_DOT_I]], 2.000000e+00
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x half> poison, half [[DOTSCALAR]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x half> [[TMP0]], <4 x half> poison, <4 x i32> zeroinitializer
// CHECK-NEXT: [[MUL1_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> [[TMP1]], [[N]]
diff --git a/clang/test/CodeGenHLSL/builtins/refract.hlsl b/clang/test/CodeGenHLSL/builtins/refract.hlsl
index ecc36d5c7aadf..1bb75a25f3c7b 100644
--- a/clang/test/CodeGenHLSL/builtins/refract.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/refract.hlsl
@@ -11,17 +11,17 @@
// CHECK: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
// CHECK: [[MUL1_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
// CHECK: [[MUL2_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
-// CHECK: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half 0xH3C00, [[MUL2_I]]
+// CHECK: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half 1.000000e+00, [[MUL2_I]]
// CHECK: [[MUL3_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[MUL1_I]], [[SUB_I]]
-// CHECK: [[SUB4_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half 0xH3C00, [[MUL3_I]]
+// CHECK: [[SUB4_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half 1.000000e+00, [[MUL3_I]]
// CHECK: [[MUL5_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
// CHECK: [[MUL6_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
// CHECK: [[TMP0:%.*]] = call reassoc nnan ninf nsz arcp afn half @llvm.sqrt.f16(half %{{.*}})
// CHECK: [[ADD_I:%.*]] = fadd reassoc nnan ninf nsz arcp afn half [[MUL6_I]], %{{.*}}
// CHECK: [[MUL7_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[ADD_I]], %{{.*}}
// CHECK: [[SUB8_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half %{{.*}}, [[MUL7_I]]
-// CHECK: [[CMP_I:%.*]] = fcmp reassoc nnan ninf nsz arcp afn olt half %{{.*}}, 0xH0000
-// CHECK: [[HLSL_SELECT_I:%.*]] = select reassoc nnan ninf nsz arcp afn i1 [[CMP_I]], half 0xH0000, half %{{.*}}
+// CHECK: [[CMP_I:%.*]] = fcmp reassoc nnan ninf nsz arcp afn olt half %{{.*}}, 0.000000e+00
+// CHECK: [[HLSL_SELECT_I:%.*]] = select reassoc nnan ninf nsz arcp afn i1 [[CMP_I]], half 0.000000e+00, half %{{.*}}
// CHECK: ret half [[HLSL_SELECT_I]]
//
// SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z17test_refract_halfDhDhDh(
@@ -40,9 +40,9 @@ half test_refract_half(half I, half N, half ETA) {
// CHECK: [[HLSL_DOT_I:%.*]] = call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v2f16(<2 x half> %{{.*}}, <2 x half> %{{.*}})
// CHECK: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
// CHECK: [[MUL3_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}, %{{.*}}
-// CHECK: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> splat (half 0xH3C00), [[MUL3_I]]
+// CHECK: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> splat (half 1.000000e+00), [[MUL3_I]]
// CHECK: [[MUL4_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}, [[SUB_I]]
-// CHECK: [[SUB5_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> splat (half 0xH3C00), [[MUL4_I]]
+// CHECK: [[SUB5_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> splat (half 1.000000e+00), [[MUL4_I]]
// CHECK: [[MUL8_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}, %{{.*}}
// CHECK: [[MUL11_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> %{{.*}}, %{{.*}}
// CHECK: [[TMP17:%.*]] = call reassoc nnan ninf nsz arcp afn <2 x half> @llvm.sqrt.v2f16(<2 x half> %{{.*}})
@@ -70,9 +70,9 @@ half2 test_refract_half2(half2 I, half2 N, half ETA) {
// CHECK: [[HLSL_DOT_I:%.*]] = call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v3f16(<3 x half> %{{.*}}, <3 x half> %{{.*}})
// CHECK: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
// CHECK: [[MUL3_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> %{{.*}}, %{{.*}}
-// CHECK: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> splat (half 0xH3C00), [[MUL3_I]]
+// CHECK: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> splat (half 1.000000e+00), [[MUL3_I]]
// CHECK: [[MUL4_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> %{{.*}}, [[SUB_I]]
-// CHECK: [[SUB5_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> splat (half 0xH3C00), [[MUL4_I]]
+// CHECK: [[SUB5_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> splat (half 1.000000e+00), [[MUL4_I]]
// CHECK: [[MUL8_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> %{{.*}}, %{{.*}}
// CHECK: [[MUL11_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> %{{.*}}, %{{.*}}
// CHECK: [[TMP17:%.*]] = call reassoc nnan ninf nsz arcp afn <3 x half> @llvm.sqrt.v3f16(<3 x half> %{{.*}})
@@ -100,9 +100,9 @@ half3 test_refract_half3(half3 I, half3 N, half ETA) {
// CHECK: [[HLSL_DOT_I:%.*]] = call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v4f16(<4 x half> %{{.*}}, <4 x half> %{{.*}})
// CHECK: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half %{{.*}}, %{{.*}}
// CHECK: [[MUL3_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> %{{.*}}, %{{.*}}
-// CHECK: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> splat (half 0xH3C00), [[MUL3_I]]
+// CHECK: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> splat (half 1.000000e+00), [[MUL3_I]]
// CHECK: [[MUL4_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> %{{.*}}, [[SUB_I]]
-// CHECK: [[SUB5_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> splat (half 0xH3C00), [[MUL4_I]]
+// CHECK: [[SUB5_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> splat (half 1.000000e+00), [[MUL4_I]]
// CHECK: [[MUL8_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> %{{.*}}, %{{.*}}
// CHECK: [[MUL11_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> %{{.*}}, %{{.*}}
// CHECK: [[TMP17:%.*]] = call reassoc nnan ninf nsz arcp afn <4 x half> @llvm.sqrt.v4f16(<4 x half> %{{.*}})
diff --git a/clang/test/CodeGenHLSL/builtins/smoothstep.hlsl b/clang/test/CodeGenHLSL/builtins/smoothstep.hlsl
index c39261cfb7915..a4aee0e7dc995 100644
--- a/clang/test/CodeGenHLSL/builtins/smoothstep.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/smoothstep.hlsl
@@ -13,8 +13,8 @@
// CHECK-NEXT: [[SUB1_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half [[MAX]], [[MIN]]
// CHECK-NEXT: [[DIV_I:%.*]] = fdiv reassoc nnan ninf nsz arcp afn half [[SUB_I]], [[SUB1_I]]
// CHECK-NEXT: [[HLSL_SATURATE_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.saturate.f16(half [[DIV_I]])
-// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_SATURATE_I]], 0xH4000
-// CHECK-NEXT: [[SUB2_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half 0xH4200, [[MUL_I]]
+// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_SATURATE_I]], 2.000000e+00
+// CHECK-NEXT: [[SUB2_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half 3.000000e+00, [[MUL_I]]
// CHECK-NEXT: [[TMP0:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[HLSL_SATURATE_I]], [[HLSL_SATURATE_I]]
// CHECK-NEXT: [[MUL4_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn half [[TMP0]], [[SUB2_I]]
// CHECK-NEXT: ret half [[MUL4_I]]
@@ -34,8 +34,8 @@ half test_smoothstep_half(half Min, half Max, half X) { return smoothstep(Min, M
// CHECK-NEXT: [[SUB1_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> [[MAX]], [[MIN]]
// CHECK-NEXT: [[DIV_I:%.*]] = fdiv reassoc nnan ninf nsz arcp afn <2 x half> [[SUB_I]], [[SUB1_I]]
// CHECK-NEXT: [[HLSL_SATURATE_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn <2 x half> @llvm.dx.saturate.v2f16(<2 x half> [[DIV_I]])
-// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> [[HLSL_SATURATE_I]], splat (half 0xH4000)
-// CHECK-NEXT: [[SUB2_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> splat (half 0xH4200), [[MUL_I]]
+// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> [[HLSL_SATURATE_I]], splat (half 2.000000e+00)
+// CHECK-NEXT: [[SUB2_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> splat (half 3.000000e+00), [[MUL_I]]
// CHECK-NEXT: [[TMP0:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> [[HLSL_SATURATE_I]], [[HLSL_SATURATE_I]]
// CHECK-NEXT: [[MUL4_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <2 x half> [[TMP0]], [[SUB2_I]]
// CHECK-NEXT: ret <2 x half> [[MUL4_I]]
@@ -55,8 +55,8 @@ half2 test_smoothstep_half2(half2 Min, half2 Max, half2 X) { return smoothstep(M
// CHECK-NEXT: [[SUB1_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> [[MAX]], [[MIN]]
// CHECK-NEXT: [[DIV_I:%.*]] = fdiv reassoc nnan ninf nsz arcp afn <3 x half> [[SUB_I]], [[SUB1_I]]
// CHECK-NEXT: [[HLSL_SATURATE_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn <3 x half> @llvm.dx.saturate.v3f16(<3 x half> [[DIV_I]])
-// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> [[HLSL_SATURATE_I]], splat (half 0xH4000)
-// CHECK-NEXT: [[SUB2_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> splat (half 0xH4200), [[MUL_I]]
+// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> [[HLSL_SATURATE_I]], splat (half 2.000000e+00)
+// CHECK-NEXT: [[SUB2_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> splat (half 3.000000e+00), [[MUL_I]]
// CHECK-NEXT: [[TMP0:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> [[HLSL_SATURATE_I]], [[HLSL_SATURATE_I]]
// CHECK-NEXT: [[MUL4_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <3 x half> [[TMP0]], [[SUB2_I]]
// CHECK-NEXT: ret <3 x half> [[MUL4_I]]
@@ -76,8 +76,8 @@ half3 test_smoothstep_half3(half3 Min, half3 Max, half3 X) { return smoothstep(M
// CHECK-NEXT: [[SUB1_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> [[MAX]], [[MIN]]
// CHECK-NEXT: [[DIV_I:%.*]] = fdiv reassoc nnan ninf nsz arcp afn <4 x half> [[SUB_I]], [[SUB1_I]]
// CHECK-NEXT: [[HLSL_SATURATE_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn <4 x half> @llvm.dx.saturate.v4f16(<4 x half> [[DIV_I]])
-// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> [[HLSL_SATURATE_I]], splat (half 0xH4000)
-// CHECK-NEXT: [[SUB2_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> splat (half 0xH4200), [[MUL_I]]
+// CHECK-NEXT: [[MUL_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> [[HLSL_SATURATE_I]], splat (half 2.000000e+00)
+// CHECK-NEXT: [[SUB2_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> splat (half 3.000000e+00), [[MUL_I]]
// CHECK-NEXT: [[TMP0:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> [[HLSL_SATURATE_I]], [[HLSL_SATURATE_I]]
// CHECK-NEXT: [[MUL4_I:%.*]] = fmul reassoc nnan ninf nsz arcp afn <4 x half> [[TMP0]], [[SUB2_I]]
// CHECK-NEXT: ret <4 x half> [[MUL4_I]]
diff --git a/clang/test/CodeGenHLSL/resources/resources-in-structs-inheritance.hlsl b/clang/test/CodeGenHLSL/resources/resources-in-structs-inheritance.hlsl
index 5b5b8270f8e86..40d2ebeb7407d 100644
--- a/clang/test/CodeGenHLSL/resources/resources-in-structs-inheritance.hlsl
+++ b/clang/test/CodeGenHLSL/resources/resources-in-structs-inheritance.hlsl
@@ -98,19 +98,19 @@ void main() {
// CHECK-NEXT: %a = alloca float
// CHECK-NEXT: %[[PTR1:.*]] = call {{.*}} ptr @hlsl::RWBuffer<float>::operator[](unsigned int)(ptr {{.*}} @"_ZL8c.A::Buf", i32 noundef 0)
-// CHECK-NEXT: store float 0x3FF3AE1480000000, ptr %[[PTR1:]]
+// CHECK-NEXT: store float 1.230000e+00, ptr %[[PTR1:]]
c.Buf[0] = 1.230f;
// CHECK-NEXT: %[[PTR2:.*]] = call {{.*}} ptr @hlsl::RWBuffer<float>::operator[](unsigned int)(ptr {{.*}} @c.Buf2, i32 noundef 0)
-// CHECK-NEXT: store float 0x4002B851E0000000, ptr %[[PTR2:]]
+// CHECK-NEXT: store float 2.340000e+00, ptr %[[PTR2:]]
c.Buf2[0] = 2.340f;
// CHECK-NEXT: %[[PTR3:.*]] = call {{.*}} ptr @hlsl::RWBuffer<float>::operator[](unsigned int)(ptr {{.*}} @"_ZL8d.A::Buf", i32 noundef 0)
-// CHECK-NEXT: store float 0x400B9999A0000000, ptr %[[PTR3:]]
+// CHECK-NEXT: store float 3.450000e+00, ptr %[[PTR3:]]
d.Buf[0] = 3.450f;
// CHECK-NEXT: %[[PTR4:.*]] = call {{.*}} ptr @hlsl::RWBuffer<float>::operator[](unsigned int)(ptr {{.*}} @d.A.Buf, i32 noundef 0)
-// CHECK-NEXT: store float 0x40123D70A0000000, ptr %[[PTR4:]]
+// CHECK-NEXT: store float 4.560000e+00, ptr %[[PTR4:]]
d.A.Buf[0] = 4.560f;
// Resource array access - initilized on demand:
diff --git a/clang/test/CodeGenHLSL/resources/resources-in-structs.hlsl b/clang/test/CodeGenHLSL/resources/resources-in-structs.hlsl
index 3502f1d7eca66..33eb061e07c6b 100644
--- a/clang/test/CodeGenHLSL/resources/resources-in-structs.hlsl
+++ b/clang/test/CodeGenHLSL/resources/resources-in-structs.hlsl
@@ -60,14 +60,14 @@ C c : register(t10);
void main() {
// CHECK: %[[PTR1:.*]] = call {{.*}} ptr @hlsl::RWBuffer<float>::operator[](unsigned int)(ptr noundef nonnull align 4 dereferenceable(4) @a.Buf, i32 noundef 0)
-// CHECK-NEXT: store float 0x3FF3AE1480000000, ptr %[[PTR1]], align 4
+// CHECK-NEXT: store float 1.230000e+00, ptr %[[PTR1]], align 4
a.Buf[0] = 1.230f;
// Resource array access - first create the resource from binding, then access the element and store to it.
// CHECK: call void @hlsl::RWBuffer<float>::__createFromBinding(unsigned int, unsigned int, int, unsigned int, char const*)
// CHECK-SAME: (ptr {{.*}} sret(%"class.hlsl::RWBuffer") align 4 %[[TMP1]], i32 noundef 2, i32 noundef 0, i32 noundef 10, i32 noundef 5, ptr noundef @[[bBufsStr]])
// CHECK-NEXT: %[[PTR2:.*]] = call {{.*}} ptr @hlsl::RWBuffer<float>::operator[](unsigned int)(ptr {{.*}} %[[TMP1]], i32 noundef 0)
-// CHECK-NEXT: store float 0x40123D70A0000000, ptr %[[PTR2]], align 4
+// CHECK-NEXT: store float 4.560000e+00, ptr %[[PTR2]], align 4
b.Bufs[5][0] = 4.56f;
// CHECK: %[[PTR3:.*]] = call {{.*}} ptr @hlsl::StructuredBuffer<float>::operator[](unsigned int) const(ptr noundef nonnull align 4 dereferenceable(4) @c.BufOne, i32 noundef 0)
diff --git a/clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl b/clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
index 3f7c59916316d..3d7ced93f42fa 100644
--- a/clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
+++ b/clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
@@ -195,7 +195,7 @@ void main() {
// CHECK-SAME: ) #[[ATTR3]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = call token @llvm.experimental.convergence.entry()
-// CHECK-NEXT: [[TMP1:%.*]] = call reassoc nnan ninf nsz arcp afn float @_Z20__spirv_SpecConstantiDh(i32 8, float 0x4044333340000000)
+// CHECK-NEXT: [[TMP1:%.*]] = call reassoc nnan ninf nsz arcp afn float @_Z20__spirv_SpecConstantiDh(i32 8, float 4.040000e+01)
// CHECK-NEXT: store float [[TMP1]], ptr addrspace(10) @_ZL10half_const, align 4
// CHECK-NEXT: ret void
//
@@ -213,7 +213,7 @@ void main() {
// CHECK-SAME: ) #[[ATTR3]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = call token @llvm.experimental.convergence.entry()
-// CHECK-NEXT: [[TMP1:%.*]] = call reassoc nnan ninf nsz arcp afn double @_Z20__spirv_SpecConstantid(i32 9, double 0x40590CCCC0000000)
+// CHECK-NEXT: [[TMP1:%.*]] = call reassoc nnan ninf nsz arcp afn double @_Z20__spirv_SpecConstantid(i32 9, double f0x40590CCCC0000000)
// CHECK-NEXT: store double [[TMP1]], ptr addrspace(10) @_ZL12double_const, align 8
// CHECK-NEXT: ret void
//
diff --git a/clang/test/CodeGenObjC/objc-literal-tests.m b/clang/test/CodeGenObjC/objc-literal-tests.m
index 653848bd07c3e..00118acea206e 100644
--- a/clang/test/CodeGenObjC/objc-literal-tests.m
+++ b/clang/test/CodeGenObjC/objc-literal-tests.m
@@ -68,9 +68,9 @@ int main(void) {
NSNumber *fortyTwoLong = @42l;
// CHECK: call{{.*}}@objc_msgSend{{.*}}i64 noundef 42
NSNumber *fortyTwoLongLong = @42ll;
- // CHECK: call{{.*}}@objc_msgSend{{.*}}float noundef 0x400921FB60000000
+ // CHECK: call{{.*}}@objc_msgSend{{.*}}float noundef f0x40490FDB
NSNumber *piFloat = @3.141592654f;
- // CHECK: call{{.*}}@objc_msgSend{{.*}}double noundef 0x400921FB54411744
+ // CHECK: call{{.*}}@objc_msgSend{{.*}}double noundef f0x400921FB54411744
NSNumber *piDouble = @3.1415926535;
// CHECK: call{{.*}}@objc_msgSend{{.*}}i8 noundef signext 1
NSNumber *yesNumber = @__objc_yes;
diff --git a/clang/test/CodeGenObjC/objc2-constant-number-literal.m b/clang/test/CodeGenObjC/objc2-constant-number-literal.m
index 34736cc1a47e1..989dbe0947011 100644
--- a/clang/test/CodeGenObjC/objc2-constant-number-literal.m
+++ b/clang/test/CodeGenObjC/objc2-constant-number-literal.m
@@ -32,16 +32,16 @@
// CHECK: @_unnamed_nsconstantintegernumber_.7 = private constant %struct.__builtin_NSConstantIntegerNumber { ptr @"OBJC_CLASS_$_NSConstantIntegerNumber", ptr @.str.6, i64 42 }, section "__DATA,__objc_intobj,regular,no_dead_strip", align 8 #[[ATTR0]]
// CHECK: @_unnamed_nsconstantintegernumber_.8 = private constant %struct.__builtin_NSConstantIntegerNumber { ptr @"OBJC_CLASS_$_NSConstantIntegerNumber", ptr @.str.6, i64 42 }, section "__DATA,__objc_intobj,regular,no_dead_strip", align 8 #[[ATTR0]]
// CHECK: @"OBJC_CLASS_$_NSConstantFloatNumber" = external global %struct._class_t
-// CHECK: @_unnamed_nsconstantfloatnumber_ = private constant %struct.__builtin_NSConstantFloatNumber { ptr @"OBJC_CLASS_$_NSConstantFloatNumber", float 0x400921FB60000000 }, section "__DATA,__objc_floatobj,regular,no_dead_strip", align 8 #[[ATTR0]]
+// CHECK: @_unnamed_nsconstantfloatnumber_ = private constant %struct.__builtin_NSConstantFloatNumber { ptr @"OBJC_CLASS_$_NSConstantFloatNumber", float f0x40490FDB }, section "__DATA,__objc_floatobj,regular,no_dead_strip", align 8 #[[ATTR0]]
// CHECK: @"OBJC_CLASS_$_NSConstantDoubleNumber" = external global %struct._class_t
-// CHECK: @_unnamed_nsconstantdoublenumber_ = private constant %struct.__builtin_NSConstantDoubleNumber { ptr @"OBJC_CLASS_$_NSConstantDoubleNumber", double 0x400921FB54411744 }, section "__DATA,__objc_doubleobj,regular,no_dead_strip", align 8 #[[ATTR0]]
+// CHECK: @_unnamed_nsconstantdoublenumber_ = private constant %struct.__builtin_NSConstantDoubleNumber { ptr @"OBJC_CLASS_$_NSConstantDoubleNumber", double f0x400921FB54411744 }, section "__DATA,__objc_doubleobj,regular,no_dead_strip", align 8 #[[ATTR0]]
// CHECK: @__kCFBooleanTrue = external global ptr #0
// CHECK: @__kCFBooleanFalse = external global ptr #0
// CHECK: @_unnamed_nsconstantintegernumber_.9 = private constant %struct.__builtin_NSConstantIntegerNumber { ptr @"OBJC_CLASS_$_NSConstantIntegerNumber", ptr @.str.1, i64 1 }, section "__DATA,__objc_intobj,regular,no_dead_strip", align 8 #0
// CHECK: @_unnamed_nsconstantintegernumber_.10 = private constant %struct.__builtin_NSConstantIntegerNumber { ptr @"OBJC_CLASS_$_NSConstantIntegerNumber", ptr @.str.1, i64 0 }, section "__DATA,__objc_intobj,regular,no_dead_strip", align 8 #0
-// CHECK: @_unnamed_nsconstantfloatnumber_.11 = private constant %struct.__builtin_NSConstantFloatNumber { ptr @"OBJC_CLASS_$_NSConstantFloatNumber", float 0x7FF8000000000000 }, section "__DATA,__objc_floatobj,regular,no_dead_strip", align 8 #0
-// CHECK: @_unnamed_nsconstantfloatnumber_.12 = private constant %struct.__builtin_NSConstantFloatNumber { ptr @"OBJC_CLASS_$_NSConstantFloatNumber", float 0x7FF0000000000000 }, section "__DATA,__objc_floatobj,regular,no_dead_strip", align 8 #0
-// CHECK: @_unnamed_nsconstantfloatnumber_.13 = private constant %struct.__builtin_NSConstantFloatNumber { ptr @"OBJC_CLASS_$_NSConstantFloatNumber", float 0xFFF0000000000000 }, section "__DATA,__objc_floatobj,regular,no_dead_strip", align 8 #0
+// CHECK: @_unnamed_nsconstantfloatnumber_.11 = private constant %struct.__builtin_NSConstantFloatNumber { ptr @"OBJC_CLASS_$_NSConstantFloatNumber", float +qnan }, section "__DATA,__objc_floatobj,regular,no_dead_strip", align 8 #0
+// CHECK: @_unnamed_nsconstantfloatnumber_.12 = private constant %struct.__builtin_NSConstantFloatNumber { ptr @"OBJC_CLASS_$_NSConstantFloatNumber", float +inf }, section "__DATA,__objc_floatobj,regular,no_dead_strip", align 8 #0
+// CHECK: @_unnamed_nsconstantfloatnumber_.13 = private constant %struct.__builtin_NSConstantFloatNumber { ptr @"OBJC_CLASS_$_NSConstantFloatNumber", float -inf }, section "__DATA,__objc_floatobj,regular,no_dead_strip", align 8 #0
// NOTE: We expect `@((NSUInteger)2046)` to have an encoding of "Q" or `kCFNumberSInt128Type` on 64bit platforms. Since that isn't a public type `CFNumberType` will detect that and return
// CHECK: @.str.14 = private unnamed_addr constant [2 x i8] c"Q\00", align 1
// CHECK: @_unnamed_nsconstantintegernumber_.15 = private constant %struct.__builtin_NSConstantIntegerNumber { ptr @"OBJC_CLASS_$_NSConstantIntegerNumber", ptr @.str.14, i64 2049 }, section "__DATA,__objc_intobj,regular,no_dead_strip", align 8 #0
diff --git a/clang/test/CodeGenOpenCL/amdgpu-alignment.cl b/clang/test/CodeGenOpenCL/amdgpu-alignment.cl
index 3c2653bf34124..548a2f6b4d3f8 100644
--- a/clang/test/CodeGenOpenCL/amdgpu-alignment.cl
+++ b/clang/test/CodeGenOpenCL/amdgpu-alignment.cl
@@ -116,9 +116,9 @@ typedef double __attribute__((ext_vector_type(16))) double16;
// CHECK: store volatile <4 x i64> zeroinitializer, ptr addrspace(3) @local_memory_alignment_global.lds_v4i64, align 32
// CHECK: store volatile <8 x i64> zeroinitializer, ptr addrspace(3) @local_memory_alignment_global.lds_v8i64, align 64
// CHECK: store volatile <16 x i64> zeroinitializer, ptr addrspace(3) @local_memory_alignment_global.lds_v16i64, align 128
-// CHECK: store volatile half 0xH0000, ptr addrspace(3) @local_memory_alignment_global.lds_f16, align 2
+// CHECK: store volatile half 0.000000e+00, ptr addrspace(3) @local_memory_alignment_global.lds_f16, align 2
// CHECK: store volatile <2 x half> zeroinitializer, ptr addrspace(3) @local_memory_alignment_global.lds_v2f16, align 4
-// CHECK: store volatile <4 x half> <half 0xH0000, half 0xH0000, half 0xH0000, half undef>, ptr addrspace(3) @local_memory_alignment_global.lds_v3f16, align 8
+// CHECK: store volatile <4 x half> <half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half undef>, ptr addrspace(3) @local_memory_alignment_global.lds_v3f16, align 8
// CHECK: store volatile <4 x half> zeroinitializer, ptr addrspace(3) @local_memory_alignment_global.lds_v4f16, align 8
// CHECK: store volatile <8 x half> zeroinitializer, ptr addrspace(3) @local_memory_alignment_global.lds_v8f16, align 16
// CHECK: store volatile <16 x half> zeroinitializer, ptr addrspace(3) @local_memory_alignment_global.lds_v16f16, align 32
@@ -403,9 +403,9 @@ kernel void local_memory_alignment_arg(
// CHECK: store volatile <4 x i64> zeroinitializer, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 32
// CHECK: store volatile <8 x i64> zeroinitializer, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 64
// CHECK: store volatile <16 x i64> zeroinitializer, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 128
-// CHECK: store volatile half 0xH0000, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 2
+// CHECK: store volatile half 0.000000e+00, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 2
// CHECK: store volatile <2 x half> zeroinitializer, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 4
-// CHECK: store volatile <4 x half> <half 0xH0000, half 0xH0000, half 0xH0000, half undef>, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 8
+// CHECK: store volatile <4 x half> <half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half undef>, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 8
// CHECK: store volatile <4 x half> zeroinitializer, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 8
// CHECK: store volatile <8 x half> zeroinitializer, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 16
// CHECK: store volatile <16 x half> zeroinitializer, ptr addrspace(5) %arraydecay{{[0-9]+}}, align 32
diff --git a/clang/test/CodeGenOpenCL/half.cl b/clang/test/CodeGenOpenCL/half.cl
index 6ade7e691aa93..f82a4da717715 100644
--- a/clang/test/CodeGenOpenCL/half.cl
+++ b/clang/test/CodeGenOpenCL/half.cl
@@ -12,11 +12,11 @@ half test()
half y = x + x;
half z = y * 1.0f;
return z;
-// CHECK: half 0xH3260
+// CHECK: half 1.992190e-01
}
// CHECK-LABEL: @test_inc(half noundef %x)
-// CHECK: [[INC:%.*]] = fadd half %x, 0xH3C00
+// CHECK: [[INC:%.*]] = fadd half %x, 1.000000e+00
// CHECK: ret half [[INC]]
half test_inc(half x)
{
@@ -30,12 +30,12 @@ __attribute__((overloadable)) float min(float, float);
__kernel void foo( __global half* buf, __global float* buf2 )
{
buf[0] = min( buf[0], 1.5h );
-// CHECK: half noundef 0xH3E00
+// CHECK: half noundef 1.500000e+00
buf[0] = min( buf2[0], 1.5f );
// CHECK: float noundef 1.500000e+00
const half one = 1.6666;
buf[1] = min( buf[1], one );
-// CHECK: half noundef 0xH3EAB
+// CHECK: half noundef 1.666990e+00
}
diff --git a/clang/test/Frontend/fixed_point_compound.c b/clang/test/Frontend/fixed_point_compound.c
index b507cbf1f6db0..5de289f95ceb0 100644
--- a/clang/test/Frontend/fixed_point_compound.c
+++ b/clang/test/Frontend/fixed_point_compound.c
@@ -365,7 +365,7 @@ void add_sshsuf(void) {
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4
// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float
-// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000
+// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], f0x38000000
// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP0]]
// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[ADD]], 3.276800e+04
// CHECK-NEXT: [[TMP5:%.*]] = fptosi float [[TMP4]] to i32
@@ -380,7 +380,7 @@ void add_afl(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x38000000
// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr @fl, align 4
// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP2]]
// CHECK-NEXT: store float [[ADD]], ptr @fl, align 4
@@ -395,7 +395,7 @@ void add_fla(void) {
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @sa, align 4
// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float
-// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000
+// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], f0x38000000
// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP0]]
// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[ADD]], 3.276800e+04
// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.fptosi.sat.i32.f32(float [[TMP4]])
@@ -410,7 +410,7 @@ void add_safl(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @sa, align 4
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x38000000
// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr @fl, align 4
// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP2]]
// CHECK-NEXT: store float [[ADD]], ptr @fl, align 4
@@ -496,7 +496,7 @@ void sub_csa(void) {
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4
// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float
-// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000
+// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], f0x38000000
// CHECK-NEXT: [[SUB:%.*]] = fsub float [[TMP3]], [[TMP0]]
// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[SUB]], 3.276800e+04
// CHECK-NEXT: [[TMP5:%.*]] = fptosi float [[TMP4]] to i32
@@ -581,7 +581,7 @@ void mul_csa(void) {
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4
// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float
-// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000
+// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], f0x38000000
// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP0]]
// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[MUL]], 3.276800e+04
// CHECK-NEXT: [[TMP5:%.*]] = fptosi float [[TMP4]] to i32
@@ -666,7 +666,7 @@ void div_csa(void) {
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4
// CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to float
-// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], 0x3F00000000000000
+// CHECK-NEXT: [[TMP3:%.*]] = fmul float [[TMP2]], f0x38000000
// CHECK-NEXT: [[DIV:%.*]] = fdiv float [[TMP3]], [[TMP0]]
// CHECK-NEXT: [[TMP4:%.*]] = fmul float [[DIV]], 3.276800e+04
// CHECK-NEXT: [[TMP5:%.*]] = fptosi float [[TMP4]] to i32
diff --git a/clang/test/Frontend/fixed_point_conversions.c b/clang/test/Frontend/fixed_point_conversions.c
index 1d053068232bc..61c5c1354d328 100644
--- a/clang/test/Frontend/fixed_point_conversions.c
+++ b/clang/test/Frontend/fixed_point_conversions.c
@@ -734,7 +734,7 @@ void float_fix2(void) {
// CHECK-LABEL: @float_fix3(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4
-// CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 0x41E0000000000000
+// CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], f0x4F000000
// CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i64
// CHECK-NEXT: store i64 [[TMP2]], ptr @la, align 8
// CHECK-NEXT: ret void
@@ -758,7 +758,7 @@ void float_fix4(void) {
// CHECK-LABEL: @float_fix5(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4
-// CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 0x41E0000000000000
+// CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], f0x4F000000
// CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i32
// CHECK-NEXT: store i32 [[TMP2]], ptr @lf, align 4
// CHECK-NEXT: ret void
@@ -824,7 +824,7 @@ void fix_float1(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x38000000
// CHECK-NEXT: store float [[TMP2]], ptr @fl, align 4
// CHECK-NEXT: ret void
//
@@ -836,7 +836,7 @@ void fix_float2(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @la, align 8
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i64 [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x30000000
// CHECK-NEXT: store float [[TMP2]], ptr @fl, align 4
// CHECK-NEXT: ret void
//
@@ -860,7 +860,7 @@ void fix_float4(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @lf, align 4
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x30000000
// CHECK-NEXT: store float [[TMP2]], ptr @fl, align 4
// CHECK-NEXT: ret void
//
@@ -872,7 +872,7 @@ void fix_float5(void) {
// SIGNED-NEXT: entry:
// SIGNED-NEXT: [[TMP0:%.*]] = load i32, ptr @ua, align 4
// SIGNED-NEXT: [[TMP1:%.*]] = uitofp i32 [[TMP0]] to float
-// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3EF0000000000000
+// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x37800000
// SIGNED-NEXT: store float [[TMP2]], ptr @fl, align 4
// SIGNED-NEXT: ret void
//
@@ -880,7 +880,7 @@ void fix_float5(void) {
// UNSIGNED-NEXT: entry:
// UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, ptr @ua, align 4
// UNSIGNED-NEXT: [[TMP1:%.*]] = uitofp i32 [[TMP0]] to float
-// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000
+// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x38000000
// UNSIGNED-NEXT: store float [[TMP2]], ptr @fl, align 4
// UNSIGNED-NEXT: ret void
//
@@ -892,7 +892,7 @@ void fix_float6(void) {
// SIGNED-NEXT: entry:
// SIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 2
// SIGNED-NEXT: [[TMP1:%.*]] = uitofp i16 [[TMP0]] to float
-// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3EF0000000000000
+// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x37800000
// SIGNED-NEXT: store float [[TMP2]], ptr @fl, align 4
// SIGNED-NEXT: ret void
//
@@ -900,7 +900,7 @@ void fix_float6(void) {
// UNSIGNED-NEXT: entry:
// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @uf, align 2
// UNSIGNED-NEXT: [[TMP1:%.*]] = uitofp i16 [[TMP0]] to float
-// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000
+// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x38000000
// UNSIGNED-NEXT: store float [[TMP2]], ptr @fl, align 4
// UNSIGNED-NEXT: ret void
//
@@ -936,7 +936,7 @@ void float_sat2(void) {
// CHECK-LABEL: @float_sat3(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @fl, align 4
-// CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 0x41E0000000000000
+// CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], f0x4F000000
// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.fptosi.sat.i64.f32(float [[TMP1]])
// CHECK-NEXT: store i64 [[TMP2]], ptr @sat_la, align 8
// CHECK-NEXT: ret void
diff --git a/clang/test/Frontend/fixed_point_conversions_const.c b/clang/test/Frontend/fixed_point_conversions_const.c
index 889486e5eb806..ded3f7a5f6a28 100644
--- a/clang/test/Frontend/fixed_point_conversions_const.c
+++ b/clang/test/Frontend/fixed_point_conversions_const.c
@@ -52,7 +52,7 @@ float fl_const = 1.0hk;
float fl_const2 = -128.0k;
// CHECK-DAG: @fl_const2 = {{.*}}global float -1.280000e+02, align 4
float fl_const3 = 0.0872802734375k;
-// CHECK-DAG: @fl_const3 = {{.*}}global float 0x3FB6580000000000, align 4
+// CHECK-DAG: @fl_const3 = {{.*}}global float f0x3DB2C000, align 4
float fl_const4 = 192.5k;
// CHECK-DAG: @fl_const4 = {{.*}}global float 1.925000e+02, align 4
float fl_const5 = -192.5k;
diff --git a/clang/test/Frontend/fixed_point_conversions_half.c b/clang/test/Frontend/fixed_point_conversions_half.c
index 38b99123b867f..b51c058fdc132 100644
--- a/clang/test/Frontend/fixed_point_conversions_half.c
+++ b/clang/test/Frontend/fixed_point_conversions_half.c
@@ -26,7 +26,7 @@ _Float16 h;
// CHECK-LABEL: @half_fix1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
-// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800
+// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 1.280000e+02
// CHECK-NEXT: [[TMP2:%.*]] = fptosi half [[TMP1]] to i8
// CHECK-NEXT: store i8 [[TMP2]], ptr @sf, align 1
// CHECK-NEXT: ret void
@@ -39,7 +39,7 @@ void half_fix1(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
// CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x4F000000
// CHECK-NEXT: [[TMP3:%.*]] = fptosi float [[TMP2]] to i32
// CHECK-NEXT: store i32 [[TMP3]], ptr @lf, align 4
// CHECK-NEXT: ret void
@@ -51,7 +51,7 @@ void half_fix2(void) {
// CHECK-LABEL: @half_fix3(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
-// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800
+// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 1.280000e+02
// CHECK-NEXT: [[TMP2:%.*]] = fptosi half [[TMP1]] to i16
// CHECK-NEXT: store i16 [[TMP2]], ptr @sa, align 2
// CHECK-NEXT: ret void
@@ -64,7 +64,7 @@ void half_fix3(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
// CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x4F000000
// CHECK-NEXT: [[TMP3:%.*]] = fptosi float [[TMP2]] to i64
// CHECK-NEXT: store i64 [[TMP3]], ptr @la, align 8
// CHECK-NEXT: ret void
@@ -85,7 +85,7 @@ void half_fix4(void) {
// UNSIGNED-LABEL: @half_fix5(
// UNSIGNED-NEXT: entry:
// UNSIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
-// UNSIGNED-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800
+// UNSIGNED-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 1.280000e+02
// UNSIGNED-NEXT: [[TMP2:%.*]] = fptosi half [[TMP1]] to i16
// UNSIGNED-NEXT: store i16 [[TMP2]], ptr @usa, align 2
// UNSIGNED-NEXT: ret void
@@ -98,7 +98,7 @@ void half_fix5(void) {
// SIGNED-NEXT: entry:
// SIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
// SIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float
-// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41F0000000000000
+// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x4F800000
// SIGNED-NEXT: [[TMP3:%.*]] = fptoui float [[TMP2]] to i64
// SIGNED-NEXT: store i64 [[TMP3]], ptr @ula, align 8
// SIGNED-NEXT: ret void
@@ -107,7 +107,7 @@ void half_fix5(void) {
// UNSIGNED-NEXT: entry:
// UNSIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
// UNSIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float
-// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000
+// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x4F000000
// UNSIGNED-NEXT: [[TMP3:%.*]] = fptosi float [[TMP2]] to i64
// UNSIGNED-NEXT: store i64 [[TMP3]], ptr @ula, align 8
// UNSIGNED-NEXT: ret void
@@ -120,7 +120,7 @@ void half_fix6(void) {
// CHECK-LABEL: @half_sat1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
-// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800
+// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 1.280000e+02
// CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.fptosi.sat.i8.f16(half [[TMP1]])
// CHECK-NEXT: store i8 [[TMP2]], ptr @sf_sat, align 1
// CHECK-NEXT: ret void
@@ -133,7 +133,7 @@ void half_sat1(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
// CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x4F000000
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.fptosi.sat.i32.f32(float [[TMP2]])
// CHECK-NEXT: store i32 [[TMP3]], ptr @lf_sat, align 4
// CHECK-NEXT: ret void
@@ -145,7 +145,7 @@ void half_sat2(void) {
// CHECK-LABEL: @half_sat3(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
-// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800
+// CHECK-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 1.280000e+02
// CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.fptosi.sat.i16.f16(half [[TMP1]])
// CHECK-NEXT: store i16 [[TMP2]], ptr @sa_sat, align 2
// CHECK-NEXT: ret void
@@ -158,7 +158,7 @@ void half_sat3(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
// CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x4F000000
// CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.fptosi.sat.i64.f32(float [[TMP2]])
// CHECK-NEXT: store i64 [[TMP3]], ptr @la_sat, align 8
// CHECK-NEXT: ret void
@@ -179,7 +179,7 @@ void half_sat4(void) {
// UNSIGNED-LABEL: @half_sat5(
// UNSIGNED-NEXT: entry:
// UNSIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
-// UNSIGNED-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 0xH5800
+// UNSIGNED-NEXT: [[TMP1:%.*]] = fmul half [[TMP0]], 1.280000e+02
// UNSIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.fptosi.sat.i16.f16(half [[TMP1]])
// UNSIGNED-NEXT: [[TMP3:%.*]] = icmp slt i16 [[TMP2]], 0
// UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP3]], i16 0, i16 [[TMP2]]
@@ -194,7 +194,7 @@ void half_sat5(void) {
// SIGNED-NEXT: entry:
// SIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
// SIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float
-// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41F0000000000000
+// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x4F800000
// SIGNED-NEXT: [[TMP3:%.*]] = call i64 @llvm.fptoui.sat.i64.f32(float [[TMP2]])
// SIGNED-NEXT: store i64 [[TMP3]], ptr @ula_sat, align 8
// SIGNED-NEXT: ret void
@@ -203,7 +203,7 @@ void half_sat5(void) {
// UNSIGNED-NEXT: entry:
// UNSIGNED-NEXT: [[TMP0:%.*]] = load half, ptr @h, align 2
// UNSIGNED-NEXT: [[TMP1:%.*]] = fpext half [[TMP0]] to float
-// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x41E0000000000000
+// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x4F000000
// UNSIGNED-NEXT: [[TMP3:%.*]] = call i64 @llvm.fptosi.sat.i64.f32(float [[TMP2]])
// UNSIGNED-NEXT: [[TMP4:%.*]] = icmp slt i64 [[TMP3]], 0
// UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
@@ -219,7 +219,7 @@ void half_sat6(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr @sf, align 1
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i8 [[TMP0]] to half
-// CHECK-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 0xH2000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 7.812500e-03
// CHECK-NEXT: store half [[TMP2]], ptr @h, align 2
// CHECK-NEXT: ret void
//
@@ -231,7 +231,7 @@ void fix_half1(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @lf, align 4
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x30000000
// CHECK-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half
// CHECK-NEXT: store half [[TMP3]], ptr @h, align 2
// CHECK-NEXT: ret void
@@ -244,7 +244,7 @@ void fix_half2(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @sa, align 2
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i16 [[TMP0]] to half
-// CHECK-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 0xH2000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 7.812500e-03
// CHECK-NEXT: store half [[TMP2]], ptr @h, align 2
// CHECK-NEXT: ret void
//
@@ -256,7 +256,7 @@ void fix_half3(void) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @la, align 8
// CHECK-NEXT: [[TMP1:%.*]] = sitofp i64 [[TMP0]] to float
-// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000
+// CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x30000000
// CHECK-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half
// CHECK-NEXT: store half [[TMP3]], ptr @h, align 2
// CHECK-NEXT: ret void
@@ -278,7 +278,7 @@ void fix_half4(void) {
// UNSIGNED-NEXT: entry:
// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, ptr @usa, align 2
// UNSIGNED-NEXT: [[TMP1:%.*]] = uitofp i16 [[TMP0]] to half
-// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 0xH2000
+// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul half [[TMP1]], 7.812500e-03
// UNSIGNED-NEXT: store half [[TMP2]], ptr @h, align 2
// UNSIGNED-NEXT: ret void
//
@@ -290,7 +290,7 @@ void fix_half5(void) {
// SIGNED-NEXT: entry:
// SIGNED-NEXT: [[TMP0:%.*]] = load i64, ptr @ula, align 8
// SIGNED-NEXT: [[TMP1:%.*]] = uitofp i64 [[TMP0]] to float
-// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3DF0000000000000
+// SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x2F800000
// SIGNED-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half
// SIGNED-NEXT: store half [[TMP3]], ptr @h, align 2
// SIGNED-NEXT: ret void
@@ -299,7 +299,7 @@ void fix_half5(void) {
// UNSIGNED-NEXT: entry:
// UNSIGNED-NEXT: [[TMP0:%.*]] = load i64, ptr @ula, align 8
// UNSIGNED-NEXT: [[TMP1:%.*]] = uitofp i64 [[TMP0]] to float
-// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000
+// UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], f0x30000000
// UNSIGNED-NEXT: [[TMP3:%.*]] = fptrunc float [[TMP2]] to half
// UNSIGNED-NEXT: store half [[TMP3]], ptr @h, align 2
// UNSIGNED-NEXT: ret void
diff --git a/clang/test/Headers/__clang_hip_math.hip b/clang/test/Headers/__clang_hip_math.hip
index 3c15336584501..4ee6038e97897 100644
--- a/clang/test/Headers/__clang_hip_math.hip
+++ b/clang/test/Headers/__clang_hip_math.hip
@@ -2684,7 +2684,7 @@ extern "C" __device__ int test_ilogb(double x) {
// DEFAULT-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
// DEFAULT-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-// DEFAULT-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], +inf
// DEFAULT-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// DEFAULT-NEXT: ret i32 [[CONV]]
//
@@ -2697,7 +2697,7 @@ extern "C" __device__ int test_ilogb(double x) {
// APPROX-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
// APPROX-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-// APPROX-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], 0x7FF0000000000000
+// APPROX-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], +inf
// APPROX-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// APPROX-NEXT: ret i32 [[CONV]]
//
@@ -2705,7 +2705,7 @@ extern "C" __device__ int test_ilogb(double x) {
// NCRDIV-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
// NCRDIV-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-// NCRDIV-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], 0x7FF0000000000000
+// NCRDIV-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], +inf
// NCRDIV-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// NCRDIV-NEXT: ret i32 [[CONV]]
//
@@ -2713,7 +2713,7 @@ extern "C" __device__ int test_ilogb(double x) {
// AMDGCNSPIRV-SAME: float noundef [[X:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = tail call addrspace(4) float @llvm.fabs.f32(float [[X]])
-// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], 0x7FF0000000000000
+// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = fcmp one float [[TMP0]], +inf
// AMDGCNSPIRV-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// AMDGCNSPIRV-NEXT: ret i32 [[CONV]]
//
@@ -2725,7 +2725,7 @@ extern "C" __device__ BOOL_TYPE test___finitef(float x) {
// DEFAULT-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
// DEFAULT-NEXT: [[TMP0:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-// DEFAULT-NEXT: [[TMP1:%.*]] = fcmp one double [[TMP0]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP1:%.*]] = fcmp one double [[TMP0]], +inf
// DEFAULT-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// DEFAULT-NEXT: ret i32 [[CONV]]
//
@@ -2738,7 +2738,7 @@ extern "C" __device__ BOOL_TYPE test___finitef(float x) {
// APPROX-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
// APPROX-NEXT: [[TMP0:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-// APPROX-NEXT: [[TMP1:%.*]] = fcmp one double [[TMP0]], 0x7FF0000000000000
+// APPROX-NEXT: [[TMP1:%.*]] = fcmp one double [[TMP0]], +inf
// APPROX-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// APPROX-NEXT: ret i32 [[CONV]]
//
@@ -2746,7 +2746,7 @@ extern "C" __device__ BOOL_TYPE test___finitef(float x) {
// NCRDIV-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
// NCRDIV-NEXT: [[TMP0:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-// NCRDIV-NEXT: [[TMP1:%.*]] = fcmp one double [[TMP0]], 0x7FF0000000000000
+// NCRDIV-NEXT: [[TMP1:%.*]] = fcmp one double [[TMP0]], +inf
// NCRDIV-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// NCRDIV-NEXT: ret i32 [[CONV]]
//
@@ -2754,7 +2754,7 @@ extern "C" __device__ BOOL_TYPE test___finitef(float x) {
// AMDGCNSPIRV-SAME: double noundef [[X:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = tail call addrspace(4) double @llvm.fabs.f64(double [[X]])
-// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = fcmp one double [[TMP0]], 0x7FF0000000000000
+// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = fcmp one double [[TMP0]], +inf
// AMDGCNSPIRV-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// AMDGCNSPIRV-NEXT: ret i32 [[CONV]]
//
@@ -2766,7 +2766,7 @@ extern "C" __device__ BOOL_TYPE test___finite(double x) {
// DEFAULT-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
// DEFAULT-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-// DEFAULT-NEXT: [[TMP1:%.*]] = fcmp oeq float [[TMP0]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP1:%.*]] = fcmp oeq float [[TMP0]], +inf
// DEFAULT-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// DEFAULT-NEXT: ret i32 [[CONV]]
//
@@ -2779,7 +2779,7 @@ extern "C" __device__ BOOL_TYPE test___finite(double x) {
// APPROX-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
// APPROX-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-// APPROX-NEXT: [[TMP1:%.*]] = fcmp oeq float [[TMP0]], 0x7FF0000000000000
+// APPROX-NEXT: [[TMP1:%.*]] = fcmp oeq float [[TMP0]], +inf
// APPROX-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// APPROX-NEXT: ret i32 [[CONV]]
//
@@ -2787,7 +2787,7 @@ extern "C" __device__ BOOL_TYPE test___finite(double x) {
// NCRDIV-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
// NCRDIV-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-// NCRDIV-NEXT: [[TMP1:%.*]] = fcmp oeq float [[TMP0]], 0x7FF0000000000000
+// NCRDIV-NEXT: [[TMP1:%.*]] = fcmp oeq float [[TMP0]], +inf
// NCRDIV-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// NCRDIV-NEXT: ret i32 [[CONV]]
//
@@ -2795,7 +2795,7 @@ extern "C" __device__ BOOL_TYPE test___finite(double x) {
// AMDGCNSPIRV-SAME: float noundef [[X:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = tail call addrspace(4) float @llvm.fabs.f32(float [[X]])
-// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = fcmp oeq float [[TMP0]], 0x7FF0000000000000
+// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = fcmp oeq float [[TMP0]], +inf
// AMDGCNSPIRV-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// AMDGCNSPIRV-NEXT: ret i32 [[CONV]]
//
@@ -2807,7 +2807,7 @@ extern "C" __device__ BOOL_TYPE test___isinff(float x) {
// DEFAULT-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
// DEFAULT-NEXT: [[TMP0:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-// DEFAULT-NEXT: [[TMP1:%.*]] = fcmp oeq double [[TMP0]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP1:%.*]] = fcmp oeq double [[TMP0]], +inf
// DEFAULT-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// DEFAULT-NEXT: ret i32 [[CONV]]
//
@@ -2820,7 +2820,7 @@ extern "C" __device__ BOOL_TYPE test___isinff(float x) {
// APPROX-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
// APPROX-NEXT: [[TMP0:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-// APPROX-NEXT: [[TMP1:%.*]] = fcmp oeq double [[TMP0]], 0x7FF0000000000000
+// APPROX-NEXT: [[TMP1:%.*]] = fcmp oeq double [[TMP0]], +inf
// APPROX-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// APPROX-NEXT: ret i32 [[CONV]]
//
@@ -2828,7 +2828,7 @@ extern "C" __device__ BOOL_TYPE test___isinff(float x) {
// NCRDIV-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
// NCRDIV-NEXT: [[TMP0:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-// NCRDIV-NEXT: [[TMP1:%.*]] = fcmp oeq double [[TMP0]], 0x7FF0000000000000
+// NCRDIV-NEXT: [[TMP1:%.*]] = fcmp oeq double [[TMP0]], +inf
// NCRDIV-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// NCRDIV-NEXT: ret i32 [[CONV]]
//
@@ -2836,7 +2836,7 @@ extern "C" __device__ BOOL_TYPE test___isinff(float x) {
// AMDGCNSPIRV-SAME: double noundef [[X:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = tail call addrspace(4) double @llvm.fabs.f64(double [[X]])
-// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = fcmp oeq double [[TMP0]], 0x7FF0000000000000
+// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = fcmp oeq double [[TMP0]], +inf
// AMDGCNSPIRV-NEXT: [[CONV:%.*]] = zext i1 [[TMP1]] to i32
// AMDGCNSPIRV-NEXT: ret i32 [[CONV]]
//
@@ -3906,10 +3906,10 @@ extern "C" __device__ double test_log2(double x) {
// DEFAULT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// DEFAULT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
// DEFAULT-NEXT: [[TMP4:%.*]] = tail call contract float @llvm.fabs.f32(float [[X]])
-// DEFAULT-NEXT: [[TMP5:%.*]] = fcmp contract one float [[TMP4]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP5:%.*]] = fcmp contract one float [[TMP4]], +inf
// DEFAULT-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
// DEFAULT-NEXT: [[TMP7:%.*]] = fcmp contract oeq float [[X]], 0.000000e+00
-// DEFAULT-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], float 0xFFF0000000000000, float [[TMP6]]
+// DEFAULT-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], float -inf, float [[TMP6]]
// DEFAULT-NEXT: ret float [[TMP8]]
//
// FINITEONLY-LABEL: define dso_local nofpclass(nan inf) float @test_logbf(
@@ -3929,10 +3929,10 @@ extern "C" __device__ double test_log2(double x) {
// APPROX-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// APPROX-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
// APPROX-NEXT: [[TMP4:%.*]] = tail call contract float @llvm.fabs.f32(float [[X]])
-// APPROX-NEXT: [[TMP5:%.*]] = fcmp contract one float [[TMP4]], 0x7FF0000000000000
+// APPROX-NEXT: [[TMP5:%.*]] = fcmp contract one float [[TMP4]], +inf
// APPROX-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
// APPROX-NEXT: [[TMP7:%.*]] = fcmp contract oeq float [[X]], 0.000000e+00
-// APPROX-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], float 0xFFF0000000000000, float [[TMP6]]
+// APPROX-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], float -inf, float [[TMP6]]
// APPROX-NEXT: ret float [[TMP8]]
//
// NCRDIV-LABEL: define dso_local float @test_logbf(
@@ -3943,10 +3943,10 @@ extern "C" __device__ double test_log2(double x) {
// NCRDIV-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// NCRDIV-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
// NCRDIV-NEXT: [[TMP4:%.*]] = tail call contract float @llvm.fabs.f32(float [[X]])
-// NCRDIV-NEXT: [[TMP5:%.*]] = fcmp contract one float [[TMP4]], 0x7FF0000000000000
+// NCRDIV-NEXT: [[TMP5:%.*]] = fcmp contract one float [[TMP4]], +inf
// NCRDIV-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
// NCRDIV-NEXT: [[TMP7:%.*]] = fcmp contract oeq float [[X]], 0.000000e+00
-// NCRDIV-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], float 0xFFF0000000000000, float [[TMP6]]
+// NCRDIV-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], float -inf, float [[TMP6]]
// NCRDIV-NEXT: ret float [[TMP8]]
//
// AMDGCNSPIRV-LABEL: define spir_func float @test_logbf(
@@ -3957,10 +3957,10 @@ extern "C" __device__ double test_log2(double x) {
// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = tail call contract addrspace(4) float @llvm.fabs.f32(float [[X]])
-// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = fcmp contract one float [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = fcmp contract one float [[TMP4]], +inf
// AMDGCNSPIRV-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
// AMDGCNSPIRV-NEXT: [[TMP7:%.*]] = fcmp contract oeq float [[X]], 0.000000e+00
-// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], float 0xFFF0000000000000, float [[TMP6]]
+// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], float -inf, float [[TMP6]]
// AMDGCNSPIRV-NEXT: ret float [[TMP8]]
//
extern "C" __device__ float test_logbf(float x) {
@@ -3975,10 +3975,10 @@ extern "C" __device__ float test_logbf(float x) {
// DEFAULT-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// DEFAULT-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// DEFAULT-NEXT: [[TMP4:%.*]] = tail call contract double @llvm.fabs.f64(double [[X]])
-// DEFAULT-NEXT: [[TMP5:%.*]] = fcmp contract one double [[TMP4]], 0x7FF0000000000000
+// DEFAULT-NEXT: [[TMP5:%.*]] = fcmp contract one double [[TMP4]], +inf
// DEFAULT-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
// DEFAULT-NEXT: [[TMP7:%.*]] = fcmp contract oeq double [[X]], 0.000000e+00
-// DEFAULT-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], double 0xFFF0000000000000, double [[TMP6]]
+// DEFAULT-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], double -inf, double [[TMP6]]
// DEFAULT-NEXT: ret double [[TMP8]]
//
// FINITEONLY-LABEL: define dso_local nofpclass(nan inf) double @test_logb(
@@ -3998,10 +3998,10 @@ extern "C" __device__ float test_logbf(float x) {
// APPROX-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// APPROX-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// APPROX-NEXT: [[TMP4:%.*]] = tail call contract double @llvm.fabs.f64(double [[X]])
-// APPROX-NEXT: [[TMP5:%.*]] = fcmp contract one double [[TMP4]], 0x7FF0000000000000
+// APPROX-NEXT: [[TMP5:%.*]] = fcmp contract one double [[TMP4]], +inf
// APPROX-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
// APPROX-NEXT: [[TMP7:%.*]] = fcmp contract oeq double [[X]], 0.000000e+00
-// APPROX-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], double 0xFFF0000000000000, double [[TMP6]]
+// APPROX-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], double -inf, double [[TMP6]]
// APPROX-NEXT: ret double [[TMP8]]
//
// NCRDIV-LABEL: define dso_local double @test_logb(
@@ -4012,10 +4012,10 @@ extern "C" __device__ float test_logbf(float x) {
// NCRDIV-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// NCRDIV-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// NCRDIV-NEXT: [[TMP4:%.*]] = tail call contract double @llvm.fabs.f64(double [[X]])
-// NCRDIV-NEXT: [[TMP5:%.*]] = fcmp contract one double [[TMP4]], 0x7FF0000000000000
+// NCRDIV-NEXT: [[TMP5:%.*]] = fcmp contract one double [[TMP4]], +inf
// NCRDIV-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
// NCRDIV-NEXT: [[TMP7:%.*]] = fcmp contract oeq double [[X]], 0.000000e+00
-// NCRDIV-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], double 0xFFF0000000000000, double [[TMP6]]
+// NCRDIV-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], double -inf, double [[TMP6]]
// NCRDIV-NEXT: ret double [[TMP8]]
//
// AMDGCNSPIRV-LABEL: define spir_func double @test_logb(
@@ -4026,10 +4026,10 @@ extern "C" __device__ float test_logbf(float x) {
// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to double
// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = tail call contract addrspace(4) double @llvm.fabs.f64(double [[X]])
-// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = fcmp contract one double [[TMP4]], 0x7FF0000000000000
+// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = fcmp contract one double [[TMP4]], +inf
// AMDGCNSPIRV-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], double [[TMP3]], double [[TMP4]]
// AMDGCNSPIRV-NEXT: [[TMP7:%.*]] = fcmp contract oeq double [[X]], 0.000000e+00
-// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], double 0xFFF0000000000000, double [[TMP6]]
+// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = select contract i1 [[TMP7]], double -inf, double [[TMP6]]
// AMDGCNSPIRV-NEXT: ret double [[TMP8]]
//
extern "C" __device__ double test_logb(double x) {
@@ -5115,7 +5115,7 @@ extern "C" __device__ double test_nan(const char *tag) {
// DEFAULT-LABEL: define dso_local noundef float @test_nanf_emptystr(
// DEFAULT-SAME: ) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
-// DEFAULT-NEXT: ret float 0x7FF8000000000000
+// DEFAULT-NEXT: ret float +qnan
//
// FINITEONLY-LABEL: define dso_local nofpclass(nan inf) float @test_nanf_emptystr(
// FINITEONLY-SAME: ) local_unnamed_addr #[[ATTR3]] {
@@ -5125,17 +5125,17 @@ extern "C" __device__ double test_nan(const char *tag) {
// APPROX-LABEL: define dso_local noundef float @test_nanf_emptystr(
// APPROX-SAME: ) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
-// APPROX-NEXT: ret float 0x7FF8000000000000
+// APPROX-NEXT: ret float +qnan
//
// NCRDIV-LABEL: define dso_local noundef float @test_nanf_emptystr(
// NCRDIV-SAME: ) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
-// NCRDIV-NEXT: ret float 0x7FF8000000000000
+// NCRDIV-NEXT: ret float +qnan
//
// AMDGCNSPIRV-LABEL: define spir_func noundef float @test_nanf_emptystr(
// AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
-// AMDGCNSPIRV-NEXT: ret float 0x7FF8000000000000
+// AMDGCNSPIRV-NEXT: ret float +qnan
//
extern "C" __device__ float test_nanf_emptystr() {
return nanf("");
@@ -5144,7 +5144,7 @@ extern "C" __device__ float test_nanf_emptystr() {
// DEFAULT-LABEL: define dso_local noundef double @test_nan_emptystr(
// DEFAULT-SAME: ) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
-// DEFAULT-NEXT: ret double 0x7FF8000000000000
+// DEFAULT-NEXT: ret double +qnan
//
// FINITEONLY-LABEL: define dso_local nofpclass(nan inf) double @test_nan_emptystr(
// FINITEONLY-SAME: ) local_unnamed_addr #[[ATTR3]] {
@@ -5154,17 +5154,17 @@ extern "C" __device__ float test_nanf_emptystr() {
// APPROX-LABEL: define dso_local noundef double @test_nan_emptystr(
// APPROX-SAME: ) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
-// APPROX-NEXT: ret double 0x7FF8000000000000
+// APPROX-NEXT: ret double +qnan
//
// NCRDIV-LABEL: define dso_local noundef double @test_nan_emptystr(
// NCRDIV-SAME: ) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
-// NCRDIV-NEXT: ret double 0x7FF8000000000000
+// NCRDIV-NEXT: ret double +qnan
//
// AMDGCNSPIRV-LABEL: define spir_func noundef double @test_nan_emptystr(
// AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
-// AMDGCNSPIRV-NEXT: ret double 0x7FF8000000000000
+// AMDGCNSPIRV-NEXT: ret double +qnan
//
extern "C" __device__ double test_nan_emptystr() {
return nan("");
@@ -5173,7 +5173,7 @@ extern "C" __device__ double test_nan_emptystr() {
// DEFAULT-LABEL: define dso_local noundef float @test_nanf_fill(
// DEFAULT-SAME: ) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
-// DEFAULT-NEXT: ret float 0x7FF8000000000000
+// DEFAULT-NEXT: ret float +qnan
//
// FINITEONLY-LABEL: define dso_local nofpclass(nan inf) float @test_nanf_fill(
// FINITEONLY-SAME: ) local_unnamed_addr #[[ATTR3]] {
@@ -5183,17 +5183,17 @@ extern "C" __device__ double test_nan_emptystr() {
// APPROX-LABEL: define dso_local noundef float @test_nanf_fill(
// APPROX-SAME: ) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
-// APPROX-NEXT: ret float 0x7FF8000000000000
+// APPROX-NEXT: ret float +qnan
//
// NCRDIV-LABEL: define dso_local noundef float @test_nanf_fill(
// NCRDIV-SAME: ) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
-// NCRDIV-NEXT: ret float 0x7FF8000000000000
+// NCRDIV-NEXT: ret float +qnan
//
// AMDGCNSPIRV-LABEL: define spir_func noundef float @test_nanf_fill(
// AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
-// AMDGCNSPIRV-NEXT: ret float 0x7FF8000000000000
+// AMDGCNSPIRV-NEXT: ret float +qnan
//
extern "C" __device__ float test_nanf_fill() {
return nanf("0x456");
@@ -5202,7 +5202,7 @@ extern "C" __device__ float test_nanf_fill() {
// DEFAULT-LABEL: define dso_local noundef double @test_nan_fill(
// DEFAULT-SAME: ) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
-// DEFAULT-NEXT: ret double 0x7FF8000000000000
+// DEFAULT-NEXT: ret double +qnan
//
// FINITEONLY-LABEL: define dso_local nofpclass(nan inf) double @test_nan_fill(
// FINITEONLY-SAME: ) local_unnamed_addr #[[ATTR3]] {
@@ -5212,17 +5212,17 @@ extern "C" __device__ float test_nanf_fill() {
// APPROX-LABEL: define dso_local noundef double @test_nan_fill(
// APPROX-SAME: ) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
-// APPROX-NEXT: ret double 0x7FF8000000000000
+// APPROX-NEXT: ret double +qnan
//
// NCRDIV-LABEL: define dso_local noundef double @test_nan_fill(
// NCRDIV-SAME: ) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
-// NCRDIV-NEXT: ret double 0x7FF8000000000000
+// NCRDIV-NEXT: ret double +qnan
//
// AMDGCNSPIRV-LABEL: define spir_func noundef double @test_nan_fill(
// AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
-// AMDGCNSPIRV-NEXT: ret double 0x7FF8000000000000
+// AMDGCNSPIRV-NEXT: ret double +qnan
//
extern "C" __device__ double test_nan_fill() {
return nan("0x123");
@@ -8388,35 +8388,35 @@ extern "C" __device__ float test___cosf(float x) {
// DEFAULT-LABEL: define dso_local noundef float @test___exp10f(
// DEFAULT-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
-// DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], 0x400A934F00000000
+// DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], f0x40549A78
// DEFAULT-NEXT: [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// DEFAULT-NEXT: ret float [[TMP0]]
//
// FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test___exp10f(
// FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// FINITEONLY-NEXT: [[ENTRY:.*:]]
-// FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[X]], 0x400A934F00000000
+// FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[X]], f0x40549A78
// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// FINITEONLY-NEXT: ret float [[TMP0]]
//
// APPROX-LABEL: define dso_local noundef float @test___exp10f(
// APPROX-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
-// APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], 0x400A934F00000000
+// APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], f0x40549A78
// APPROX-NEXT: [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// APPROX-NEXT: ret float [[TMP0]]
//
// NCRDIV-LABEL: define dso_local noundef float @test___exp10f(
// NCRDIV-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
-// NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], 0x400A934F00000000
+// NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], f0x40549A78
// NCRDIV-NEXT: [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// NCRDIV-NEXT: ret float [[TMP0]]
//
// AMDGCNSPIRV-LABEL: define spir_func noundef float @test___exp10f(
// AMDGCNSPIRV-SAME: float noundef [[X:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
-// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], 0x400A934F00000000
+// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], f0x40549A78
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// AMDGCNSPIRV-NEXT: ret float [[TMP0]]
//
@@ -8427,35 +8427,35 @@ extern "C" __device__ float test___exp10f(float x) {
// DEFAULT-LABEL: define dso_local noundef float @test___expf(
// DEFAULT-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// DEFAULT-NEXT: [[ENTRY:.*:]]
-// DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], 0x3FF7154760000000
+// DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], f0x3FB8AA3B
// DEFAULT-NEXT: [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// DEFAULT-NEXT: ret float [[TMP0]]
//
// FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test___expf(
// FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// FINITEONLY-NEXT: [[ENTRY:.*:]]
-// FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[X]], 0x3FF7154760000000
+// FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[X]], f0x3FB8AA3B
// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// FINITEONLY-NEXT: ret float [[TMP0]]
//
// APPROX-LABEL: define dso_local noundef float @test___expf(
// APPROX-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// APPROX-NEXT: [[ENTRY:.*:]]
-// APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], 0x3FF7154760000000
+// APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], f0x3FB8AA3B
// APPROX-NEXT: [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// APPROX-NEXT: ret float [[TMP0]]
//
// NCRDIV-LABEL: define dso_local noundef float @test___expf(
// NCRDIV-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR3]] {
// NCRDIV-NEXT: [[ENTRY:.*:]]
-// NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], 0x3FF7154760000000
+// NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], f0x3FB8AA3B
// NCRDIV-NEXT: [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// NCRDIV-NEXT: ret float [[TMP0]]
//
// AMDGCNSPIRV-LABEL: define spir_func noundef float @test___expf(
// AMDGCNSPIRV-SAME: float noundef [[X:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR3]] {
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
-// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], 0x3FF7154760000000
+// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract float [[X]], f0x3FB8AA3B
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
// AMDGCNSPIRV-NEXT: ret float [[TMP0]]
//
diff --git a/clang/test/Headers/cuda_wrapper_algorithm.cu b/clang/test/Headers/cuda_wrapper_algorithm.cu
index d514285f7e17b..0d7cff08eb277 100644
--- a/clang/test/Headers/cuda_wrapper_algorithm.cu
+++ b/clang/test/Headers/cuda_wrapper_algorithm.cu
@@ -16,7 +16,7 @@ extern "C" bool cmp(double a, double b) { return a<b; }
// CHECK-LABEL: @test_std_min(
// CHECK-NEXT: entry:
-// CHECK-NEXT: ret double 0x7FF8000000000000
+// CHECK-NEXT: ret double +qnan
//
extern "C" double test_std_min() {
return std::min(__builtin_nan(""), 0.0);
@@ -24,7 +24,7 @@ extern "C" double test_std_min() {
// CHECK-LABEL: @test_std_min_cmp(
// CHECK-NEXT: entry:
-// CHECK-NEXT: ret double 0x7FF8000000000000
+// CHECK-NEXT: ret double +qnan
//
extern "C" double test_std_min_cmp() {
return std::min(__builtin_nan(""), 0.0, cmp);
@@ -32,7 +32,7 @@ extern "C" double test_std_min_cmp() {
// CHECK-LABEL: @test_std_max(
// CHECK-NEXT: entry:
-// CHECK-NEXT: ret double 0x7FF8000000000000
+// CHECK-NEXT: ret double +qnan
//
extern "C" double test_std_max() {
return std::max(__builtin_nan(""), 0.0);
@@ -40,7 +40,7 @@ extern "C" double test_std_max() {
// CHECK-LABEL: @test_std_max_cmp(
// CHECK-NEXT: entry:
-// CHECK-NEXT: ret double 0x7FF8000000000000
+// CHECK-NEXT: ret double +qnan
//
extern "C" double test_std_max_cmp() {
return std::max(__builtin_nan(""), 0.0, cmp);
diff --git a/clang/test/OpenMP/atomic_capture_codegen.cpp b/clang/test/OpenMP/atomic_capture_codegen.cpp
index 77312c2dac708..4573dfbadc7f6 100644
--- a/clang/test/OpenMP/atomic_capture_codegen.cpp
+++ b/clang/test/OpenMP/atomic_capture_codegen.cpp
@@ -553,7 +553,7 @@ int main(void) {
// CHECK: [[CONV:%.+]] = zext i1 [[BOOL_EXPECTED]] to i32
// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CONV]] to x86_fp80
// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[EXPR]], [[X_RVAL]]
-// CHECK: [[BOOL_DESIRED:%.+]] = fcmp une x86_fp80 [[MUL]], 0xK00000000000000000000
+// CHECK: [[BOOL_DESIRED:%.+]] = fcmp une x86_fp80 [[MUL]], 0.000000e+00
// CHECK: [[DESIRED:%.+]] = zext i1 [[BOOL_DESIRED]] to i8
// CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]],
// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]],
diff --git a/clang/test/OpenMP/atomic_update_codegen.cpp b/clang/test/OpenMP/atomic_update_codegen.cpp
index eeb7657ca90d3..0e1951aab7228 100644
--- a/clang/test/OpenMP/atomic_update_codegen.cpp
+++ b/clang/test/OpenMP/atomic_update_codegen.cpp
@@ -491,7 +491,7 @@ int main(void) {
// CHECK: [[CONV:%.+]] = zext i1 [[BOOL_EXPECTED]] to i32
// CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CONV]] to x86_fp80
// CHECK: [[MUL:%.+]] = fmul x86_fp80 [[EXPR]], [[X_RVAL]]
-// CHECK: [[BOOL_DESIRED:%.+]] = fcmp une x86_fp80 [[MUL]], 0xK00000000000000000000
+// CHECK: [[BOOL_DESIRED:%.+]] = fcmp une x86_fp80 [[MUL]], 0.000000e+00
// CHECK: [[DESIRED:%.+]] = zext i1 [[BOOL_DESIRED]] to i8
// CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]]
// CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]]
diff --git a/clang/test/OpenMP/declare_target_constexpr_codegen.cpp b/clang/test/OpenMP/declare_target_constexpr_codegen.cpp
index 0acd98129394b..ebe6064cab478 100644
--- a/clang/test/OpenMP/declare_target_constexpr_codegen.cpp
+++ b/clang/test/OpenMP/declare_target_constexpr_codegen.cpp
@@ -16,7 +16,7 @@ class A {
public:
static constexpr double pi = 3.141592653589793116;
//.
-// CHECK: @_ZN1A2piE = linkonce_odr constant double 0x400921FB54442D18, comdat, align 8
+// CHECK: @_ZN1A2piE = linkonce_odr constant double f0x400921FB54442D18, comdat, align 8
// CHECK: @_ZL9anotherPi = internal constant double 3.140000e+00, align 8
// CHECK: @llvm.compiler.used = appending global [2 x ptr] [ptr @"__ZN1A2piE$ref", ptr @"__ZL9anotherPi$ref"], section "llvm.metadata"
//.
diff --git a/clang/test/OpenMP/for_reduction_codegen.cpp b/clang/test/OpenMP/for_reduction_codegen.cpp
index 503f512c04de9..8d45693728c58 100644
--- a/clang/test/OpenMP/for_reduction_codegen.cpp
+++ b/clang/test/OpenMP/for_reduction_codegen.cpp
@@ -862,7 +862,7 @@ int main() {
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]])
// CHECK1-NEXT: store ptr [[VAR4]], ptr [[_TMP5]], align 8
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR16]])
-// CHECK1-NEXT: store float 0x47EFFFFFE0000000, ptr [[T_VAR17]], align 4
+// CHECK1-NEXT: store float f0x7F7FFFFF, ptr [[T_VAR17]], align 4
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
diff --git a/clang/test/OpenMP/parallel_reduction_codegen.cpp b/clang/test/OpenMP/parallel_reduction_codegen.cpp
index 15c4b45dd8883..4bec2dbc8a209 100644
--- a/clang/test/OpenMP/parallel_reduction_codegen.cpp
+++ b/clang/test/OpenMP/parallel_reduction_codegen.cpp
@@ -617,7 +617,7 @@ int main() {
// CHECK1-NEXT: store float 0.000000e+00, ptr [[T_VAR2]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
-// CHECK1-NEXT: store float 0x47EFFFFFE0000000, ptr [[T_VAR15]], align 4
+// CHECK1-NEXT: store float f0x7F7FFFFF, ptr [[T_VAR15]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load float, ptr [[T_VAR2]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 0
@@ -852,7 +852,7 @@ int main() {
// CHECK1-NEXT: store float 0.000000e+00, ptr [[T_VAR2]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
-// CHECK1-NEXT: store float 0x47EFFFFFE0000000, ptr [[T_VAR15]], align 4
+// CHECK1-NEXT: store float f0x7F7FFFFF, ptr [[T_VAR15]], align 4
// CHECK1-NEXT: br label [[WHILE_COND:%.*]]
// CHECK1: while.cond:
// CHECK1-NEXT: br label [[WHILE_BODY:%.*]]
diff --git a/clang/test/OpenMP/sections_reduction_codegen.cpp b/clang/test/OpenMP/sections_reduction_codegen.cpp
index f18603f9e3fb3..de3fb4ca1c5bf 100644
--- a/clang/test/OpenMP/sections_reduction_codegen.cpp
+++ b/clang/test/OpenMP/sections_reduction_codegen.cpp
@@ -290,7 +290,7 @@ int main() {
// CHECK1-NEXT: store float 0.000000e+00, ptr [[T_VAR2]], align 4
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
-// CHECK1-NEXT: store float 0x47EFFFFFE0000000, ptr [[T_VAR15]], align 4
+// CHECK1-NEXT: store float f0x7F7FFFFF, ptr [[T_VAR15]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)
diff --git a/flang/test/Fir/target-complex16.f90 b/flang/test/Fir/target-complex16.f90
index 243302ddf6c67..dae688722190a 100644
--- a/flang/test/Fir/target-complex16.f90
+++ b/flang/test/Fir/target-complex16.f90
@@ -7,7 +7,7 @@
%2 = arith.constant 1.0 : f128
%3 = arith.constant -4.0 : f128
%c0 = arith.constant 0 : i32
- // AARCH64: store { fp128, fp128 } { fp128 0xL0000000000000000C001000000000000, fp128 0xL00000000000000003FFF000000000000 }, ptr %[[VAL1]], align 16
+ // AARCH64: store { fp128, fp128 } { fp128 -4.000000e+00, fp128 1.000000e+00 }, ptr %[[VAL1]], align 16
%4 = fir.insert_value %1, %3, [0 : index] : (complex<f128>, f128) -> complex<f128>
%c1 = arith.constant 1 : i32
%5 = fir.insert_value %4, %2, [1 : index] : (complex<f128>, f128) -> complex<f128>
diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-bf16.ll b/llvm/test/Analysis/CostModel/AArch64/arith-bf16.ll
index 08f0bc89fefdd..d1cb3ddd52d82 100644
--- a/llvm/test/Analysis/CostModel/AArch64/arith-bf16.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/arith-bf16.ll
@@ -65,24 +65,24 @@ define void @fsub_bf16() {
define void @fneg_idiom_bf16() {
; CHECK-BASE-LABEL: 'fneg_idiom_bf16'
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:1 Lat:3 SizeLat:1 for: %BF16 = fsub bfloat 0xR8000, poison
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:1 Lat:3 SizeLat:1 for: %V4BF16 = fsub <4 x bfloat> splat (bfloat 0xR8000), poison
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:19 CodeSize:1 Lat:3 SizeLat:1 for: %V8BF16 = fsub <8 x bfloat> splat (bfloat 0xR8000), poison
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:38 CodeSize:1 Lat:3 SizeLat:1 for: %V16BF16 = fsub <16 x bfloat> splat (bfloat 0xR8000), poison
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:1 Lat:3 SizeLat:1 for: %BF16 = fsub bfloat -0.000000e+00, poison
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:1 Lat:3 SizeLat:1 for: %V4BF16 = fsub <4 x bfloat> splat (bfloat -0.000000e+00), poison
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:19 CodeSize:1 Lat:3 SizeLat:1 for: %V8BF16 = fsub <8 x bfloat> splat (bfloat -0.000000e+00), poison
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:38 CodeSize:1 Lat:3 SizeLat:1 for: %V16BF16 = fsub <16 x bfloat> splat (bfloat -0.000000e+00), poison
; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-BF16-LABEL: 'fneg_idiom_bf16'
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:3 CodeSize:1 Lat:3 SizeLat:1 for: %BF16 = fsub bfloat 0xR8000, poison
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:3 CodeSize:1 Lat:3 SizeLat:1 for: %V4BF16 = fsub <4 x bfloat> splat (bfloat 0xR8000), poison
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:6 CodeSize:1 Lat:3 SizeLat:1 for: %V8BF16 = fsub <8 x bfloat> splat (bfloat 0xR8000), poison
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:3 SizeLat:1 for: %V16BF16 = fsub <16 x bfloat> splat (bfloat 0xR8000), poison
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:3 CodeSize:1 Lat:3 SizeLat:1 for: %BF16 = fsub bfloat -0.000000e+00, poison
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:3 CodeSize:1 Lat:3 SizeLat:1 for: %V4BF16 = fsub <4 x bfloat> splat (bfloat -0.000000e+00), poison
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:6 CodeSize:1 Lat:3 SizeLat:1 for: %V8BF16 = fsub <8 x bfloat> splat (bfloat -0.000000e+00), poison
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:12 CodeSize:1 Lat:3 SizeLat:1 for: %V16BF16 = fsub <16 x bfloat> splat (bfloat -0.000000e+00), poison
; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-SVE-B16B16-LABEL: 'fneg_idiom_bf16'
-; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %BF16 = fsub bfloat 0xR8000, poison
-; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V4BF16 = fsub <4 x bfloat> splat (bfloat 0xR8000), poison
-; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V8BF16 = fsub <8 x bfloat> splat (bfloat 0xR8000), poison
-; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:3 SizeLat:1 for: %V16BF16 = fsub <16 x bfloat> splat (bfloat 0xR8000), poison
+; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %BF16 = fsub bfloat -0.000000e+00, poison
+; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V4BF16 = fsub <4 x bfloat> splat (bfloat -0.000000e+00), poison
+; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V8BF16 = fsub <8 x bfloat> splat (bfloat -0.000000e+00), poison
+; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:3 SizeLat:1 for: %V16BF16 = fsub <16 x bfloat> splat (bfloat -0.000000e+00), poison
; CHECK-SVE-B16B16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%BF16 = fsub bfloat -0.0, poison
diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-fp.ll b/llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
index f4721f1468ddf..41faf77a40e5e 100644
--- a/llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
@@ -113,8 +113,8 @@ define void @fneg_idiom() {
; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %F64 = fsub double -0.000000e+00, undef
; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V2F64 = fsub <2 x double> splat (double -0.000000e+00), undef
; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:3 SizeLat:1 for: %V4F64 = fsub <4 x double> splat (double -0.000000e+00), undef
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:3 SizeLat:1 for: %F128 = fsub fp128 0xL00000000000000008000000000000000, undef
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:3 SizeLat:1 for: %V2F129 = fsub <2 x fp128> splat (fp128 0xL00000000000000008000000000000000), undef
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:3 SizeLat:1 for: %F128 = fsub fp128 -0.000000e+00, undef
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:3 SizeLat:1 for: %V2F129 = fsub <2 x fp128> splat (fp128 -0.000000e+00), undef
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%F32 = fsub float -0.0, undef
@@ -134,15 +134,15 @@ define void @fneg_idiom() {
define void @fneg_idiom_fp16() {
; CHECK-BASE-LABEL: 'fneg_idiom_fp16'
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:1 Lat:3 SizeLat:1 for: %F16 = fsub half 0xH8000, undef
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:1 Lat:3 SizeLat:1 for: %V4F16 = fsub <4 x half> splat (half 0xH8000), undef
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:1 Lat:3 SizeLat:1 for: %V8F16 = fsub <8 x half> splat (half 0xH8000), undef
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:1 Lat:3 SizeLat:1 for: %F16 = fsub half -0.000000e+00, undef
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:1 Lat:3 SizeLat:1 for: %V4F16 = fsub <4 x half> splat (half -0.000000e+00), undef
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:1 Lat:3 SizeLat:1 for: %V8F16 = fsub <8 x half> splat (half -0.000000e+00), undef
; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-FP16-LABEL: 'fneg_idiom_fp16'
-; CHECK-FP16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %F16 = fsub half 0xH8000, undef
-; CHECK-FP16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V4F16 = fsub <4 x half> splat (half 0xH8000), undef
-; CHECK-FP16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V8F16 = fsub <8 x half> splat (half 0xH8000), undef
+; CHECK-FP16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %F16 = fsub half -0.000000e+00, undef
+; CHECK-FP16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V4F16 = fsub <4 x half> splat (half -0.000000e+00), undef
+; CHECK-FP16-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V8F16 = fsub <8 x half> splat (half -0.000000e+00), undef
; CHECK-FP16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%F16 = fsub half -0.0, undef
diff --git a/llvm/test/Analysis/CostModel/AArch64/insert-extract.ll b/llvm/test/Analysis/CostModel/AArch64/insert-extract.ll
index 55a14b8695a18..8cd5b54c2a4d7 100644
--- a/llvm/test/Analysis/CostModel/AArch64/insert-extract.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/insert-extract.ll
@@ -44,8 +44,8 @@ define void @vectorInstrCost() {
; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %t80 = insertelement <2 x i32> undef, i32 5, i32 1
; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %t90 = insertelement <2 x i64> undef, i64 6, i32 0
; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %t100 = insertelement <2 x i64> undef, i64 7, i32 1
-; CHECK-NEXT: Cost Model: Found costs of 0 for: %t110 = insertelement <4 x half> zeroinitializer, half 0xH0000, i64 0
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %t120 = insertelement <4 x half> zeroinitializer, half 0xH0000, i64 1
+; CHECK-NEXT: Cost Model: Found costs of 0 for: %t110 = insertelement <4 x half> zeroinitializer, half 0.000000e+00, i64 0
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %t120 = insertelement <4 x half> zeroinitializer, half 0.000000e+00, i64 1
; CHECK-NEXT: Cost Model: Found costs of 0 for: %t130 = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 0
; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %t140 = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 1
; CHECK-NEXT: Cost Model: Found costs of 0 for: %t150 = insertelement <2 x double> zeroinitializer, double 0.000000e+00, i64 0
diff --git a/llvm/test/Analysis/CostModel/AArch64/pow-special.ll b/llvm/test/Analysis/CostModel/AArch64/pow-special.ll
index 784d71bf5bc35..1c45480d109f5 100644
--- a/llvm/test/Analysis/CostModel/AArch64/pow-special.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/pow-special.ll
@@ -12,19 +12,19 @@
define void @pow_f32_f64(float %a, double %b) {
; CHECK-NO-ARMPL-LABEL: 'pow_f32_f64'
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_f32 = call fast float @llvm.pow.f32(float %a, float 2.500000e-01)
-; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_f32 = call fast float @llvm.pow.f32(float %a, float 0x3FD5555560000000)
+; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_f32 = call fast float @llvm.pow.f32(float %a, float f0x3EAAAAAB)
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_f32 = call fast float @llvm.pow.f32(float %a, float 7.500000e-01)
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_f64 = call fast double @llvm.pow.f64(double %b, double 2.500000e-01)
-; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_f64 = call fast double @llvm.pow.f64(double %b, double 0x3FD5555555555555)
+; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_f64 = call fast double @llvm.pow.f64(double %b, double f0x3FD5555555555555)
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_f64 = call fast double @llvm.pow.f64(double %b, double 7.500000e-01)
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-ARMPL-LABEL: 'pow_f32_f64'
; CHECK-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_f32 = call fast float @llvm.pow.f32(float %a, float 2.500000e-01)
-; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_f32 = call fast float @llvm.pow.f32(float %a, float 0x3FD5555560000000)
+; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_f32 = call fast float @llvm.pow.f32(float %a, float f0x3EAAAAAB)
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_f32 = call fast float @llvm.pow.f32(float %a, float 7.500000e-01)
; CHECK-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_f64 = call fast double @llvm.pow.f64(double %b, double 2.500000e-01)
-; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_f64 = call fast double @llvm.pow.f64(double %b, double 0x3FD5555555555555)
+; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_f64 = call fast double @llvm.pow.f64(double %b, double f0x3FD5555555555555)
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_f64 = call fast double @llvm.pow.f64(double %b, double 7.500000e-01)
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
@@ -42,13 +42,13 @@ define void @pow_f32_f64(float %a, double %b) {
define void @pow_v4f32(<4 x float> %a) {
; CHECK-NO-ARMPL-LABEL: 'pow_v4f32'
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_v4f32 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %a, <4 x float> splat (float 2.500000e-01))
-; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:52 CodeSize:46 Lat:52 SizeLat:52 for: %pow_one_third_v4f32 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %a, <4 x float> splat (float 0x3FD5555560000000))
+; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:52 CodeSize:46 Lat:52 SizeLat:52 for: %pow_one_third_v4f32 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %a, <4 x float> splat (float f0x3EAAAAAB))
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_v4f32 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %a, <4 x float> splat (float 7.500000e-01))
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-ARMPL-LABEL: 'pow_v4f32'
; CHECK-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_v4f32 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %a, <4 x float> splat (float 2.500000e-01))
-; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_v4f32 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %a, <4 x float> splat (float 0x3FD5555560000000))
+; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_v4f32 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %a, <4 x float> splat (float f0x3EAAAAAB))
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_v4f32 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %a, <4 x float> splat (float 7.500000e-01))
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
@@ -62,13 +62,13 @@ define void @pow_v4f32(<4 x float> %a) {
define void @pow_v2f64(<2 x double> %a) {
; CHECK-NO-ARMPL-LABEL: 'pow_v2f64'
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_v2f64 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %a, <2 x double> splat (double 2.500000e-01))
-; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:24 CodeSize:22 Lat:24 SizeLat:24 for: %pow_one_third_v2f64 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %a, <2 x double> splat (double 0x3FD5555555555555))
+; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:24 CodeSize:22 Lat:24 SizeLat:24 for: %pow_one_third_v2f64 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %a, <2 x double> splat (double f0x3FD5555555555555))
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_v2f64 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %a, <2 x double> splat (double 7.500000e-01))
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-ARMPL-LABEL: 'pow_v2f64'
; CHECK-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_v2f64 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %a, <2 x double> splat (double 2.500000e-01))
-; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_v2f64 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %a, <2 x double> splat (double 0x3FD5555555555555))
+; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_v2f64 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %a, <2 x double> splat (double f0x3FD5555555555555))
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_v2f64 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %a, <2 x double> splat (double 7.500000e-01))
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
@@ -82,13 +82,13 @@ define void @pow_v2f64(<2 x double> %a) {
define void @pow_nxv4f32(<vscale x 4 x float> %a) {
; CHECK-NO-ARMPL-LABEL: 'pow_nxv4f32'
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of Invalid for: %pow_0p25_nxv4f32 = call fast <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> splat (float 2.500000e-01))
-; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of Invalid for: %pow_one_third_nxv4f32 = call fast <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> splat (float 0x3FD5555560000000))
+; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of Invalid for: %pow_one_third_nxv4f32 = call fast <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> splat (float f0x3EAAAAAB))
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of Invalid for: %pow_0p75_nxv4f32 = call fast <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> splat (float 7.500000e-01))
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-ARMPL-LABEL: 'pow_nxv4f32'
; CHECK-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_nxv4f32 = call fast <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> splat (float 2.500000e-01))
-; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_nxv4f32 = call fast <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> splat (float 0x3FD5555560000000))
+; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_nxv4f32 = call fast <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> splat (float f0x3EAAAAAB))
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_nxv4f32 = call fast <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> splat (float 7.500000e-01))
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
@@ -102,13 +102,13 @@ define void @pow_nxv4f32(<vscale x 4 x float> %a) {
define void @pow_nxv2f64(<vscale x 2 x double> %a) {
; CHECK-NO-ARMPL-LABEL: 'pow_nxv2f64'
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of Invalid for: %pow_0p25_nxv2f64 = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> splat (double 2.500000e-01))
-; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of Invalid for: %pow_one_third_nxv2f64 = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> splat (double 0x3FD5555555555555))
+; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of Invalid for: %pow_one_third_nxv2f64 = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> splat (double f0x3FD5555555555555))
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of Invalid for: %pow_0p75_nxv2f64 = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> splat (double 7.500000e-01))
; CHECK-NO-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-ARMPL-LABEL: 'pow_nxv2f64'
; CHECK-ARMPL-NEXT: Cost Model: Found costs of 2 for: %pow_0p25_nxv2f64 = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> splat (double 2.500000e-01))
-; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_nxv2f64 = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> splat (double 0x3FD5555555555555))
+; CHECK-ARMPL-NEXT: Cost Model: Found costs of 10 for: %pow_one_third_nxv2f64 = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> splat (double f0x3FD5555555555555))
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:5 SizeLat:3 for: %pow_0p75_nxv2f64 = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> splat (double 7.500000e-01))
; CHECK-ARMPL-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
diff --git a/llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll b/llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
index c4236d2cf41b8..197d5424da656 100644
--- a/llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
@@ -26,24 +26,24 @@ define void @strict_fp_reductions() {
define void @strict_fp_reductions_fp16() {
; CHECK-NOFP16-LABEL: 'strict_fp_reductions_fp16'
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:12 CodeSize:5 Lat:10 SizeLat:6 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:26 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:54 CodeSize:23 Lat:46 SizeLat:30 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:108 CodeSize:46 Lat:92 SizeLat:60 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:12 CodeSize:5 Lat:10 SizeLat:6 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:26 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:54 CodeSize:23 Lat:46 SizeLat:30 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:108 CodeSize:46 Lat:92 SizeLat:60 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-F16-LABEL: 'strict_fp_reductions_fp16'
-; CHECK-F16-NEXT: Cost Model: Found costs of RThru:6 CodeSize:5 Lat:10 SizeLat:6 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of RThru:30 CodeSize:23 Lat:46 SizeLat:30 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of RThru:60 CodeSize:46 Lat:92 SizeLat:60 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of RThru:6 CodeSize:5 Lat:10 SizeLat:6 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of RThru:30 CodeSize:23 Lat:46 SizeLat:30 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of RThru:60 CodeSize:46 Lat:92 SizeLat:60 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-F16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-BF16-LABEL: 'strict_fp_reductions_fp16'
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:12 CodeSize:5 Lat:10 SizeLat:6 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:26 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:54 CodeSize:23 Lat:46 SizeLat:30 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:108 CodeSize:46 Lat:92 SizeLat:60 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:12 CodeSize:5 Lat:10 SizeLat:6 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:26 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:54 CodeSize:23 Lat:46 SizeLat:30 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:108 CodeSize:46 Lat:92 SizeLat:60 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0.0, <2 x half> undef)
@@ -55,15 +55,15 @@ define void @strict_fp_reductions_fp16() {
define void @strict_fp_reductions_bf16() {
; CHECK-NOFP16-LABEL: 'strict_fp_reductions_bf16'
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:54 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f8 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:54 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f8 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-F16-LABEL: 'strict_fp_reductions_bf16'
-; CHECK-F16-NEXT: Cost Model: Found costs of RThru:54 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f8 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of RThru:54 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f8 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
; CHECK-F16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-BF16-LABEL: 'strict_fp_reductions_bf16'
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:26 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f8 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:26 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f8 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%fadd_v4f8 = call bfloat @llvm.vector.reduce.fadd.v4f8(bfloat 0.0, <4 x bfloat> undef)
@@ -117,42 +117,42 @@ define void @fast_fp_reductions() {
define void @fast_fp_reductions_fp16() {
; CHECK-NOFP16-LABEL: 'fast_fp_reductions_fp16'
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:6 SizeLat:4 for: %fadd_v2f16_fast = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:6 SizeLat:4 for: %fadd_v2f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f16_fast = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:48 CodeSize:27 Lat:33 SizeLat:27 for: %fadd_v8f16 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:48 CodeSize:27 Lat:33 SizeLat:27 for: %fadd_v8f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:72 CodeSize:44 Lat:52 SizeLat:44 for: %fadd_v16f16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:72 CodeSize:44 Lat:52 SizeLat:44 for: %fadd_v16f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:203 CodeSize:35 Lat:41 SizeLat:35 for: %fadd_v11f16 = call fast half @llvm.vector.reduce.fadd.v11f16(half 0xH0000, <11 x half> undef)
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:248 CodeSize:35 Lat:41 SizeLat:35 for: %fadd_v13f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v13f16(half 0xH0000, <13 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:6 SizeLat:4 for: %fadd_v2f16_fast = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:6 SizeLat:4 for: %fadd_v2f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f16_fast = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:48 CodeSize:27 Lat:33 SizeLat:27 for: %fadd_v8f16 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:48 CodeSize:27 Lat:33 SizeLat:27 for: %fadd_v8f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:72 CodeSize:44 Lat:52 SizeLat:44 for: %fadd_v16f16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:72 CodeSize:44 Lat:52 SizeLat:44 for: %fadd_v16f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:203 CodeSize:35 Lat:41 SizeLat:35 for: %fadd_v11f16 = call fast half @llvm.vector.reduce.fadd.v11f16(half 0.000000e+00, <11 x half> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:248 CodeSize:35 Lat:41 SizeLat:35 for: %fadd_v13f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v13f16(half 0.000000e+00, <13 x half> undef)
; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-F16-LABEL: 'fast_fp_reductions_fp16'
-; CHECK-F16-NEXT: Cost Model: Found costs of 2 for: %fadd_v2f16_fast = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 2 for: %fadd_v2f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 2 for: %fadd_v4f16_fast = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 2 for: %fadd_v4f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 3 for: %fadd_v8f16 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 3 for: %fadd_v8f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 4 for: %fadd_v16f16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 4 for: %fadd_v16f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 4 for: %fadd_v11f16 = call fast half @llvm.vector.reduce.fadd.v11f16(half 0xH0000, <11 x half> undef)
-; CHECK-F16-NEXT: Cost Model: Found costs of 4 for: %fadd_v13f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v13f16(half 0xH0000, <13 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 2 for: %fadd_v2f16_fast = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 2 for: %fadd_v2f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 2 for: %fadd_v4f16_fast = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 2 for: %fadd_v4f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 3 for: %fadd_v8f16 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 3 for: %fadd_v8f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 4 for: %fadd_v16f16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 4 for: %fadd_v16f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 4 for: %fadd_v11f16 = call fast half @llvm.vector.reduce.fadd.v11f16(half 0.000000e+00, <11 x half> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of 4 for: %fadd_v13f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v13f16(half 0.000000e+00, <13 x half> undef)
; CHECK-F16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-BF16-LABEL: 'fast_fp_reductions_fp16'
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:6 SizeLat:4 for: %fadd_v2f16_fast = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:6 SizeLat:4 for: %fadd_v2f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f16_fast = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:48 CodeSize:27 Lat:33 SizeLat:27 for: %fadd_v8f16 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:48 CodeSize:27 Lat:33 SizeLat:27 for: %fadd_v8f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:72 CodeSize:44 Lat:52 SizeLat:44 for: %fadd_v16f16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:72 CodeSize:44 Lat:52 SizeLat:44 for: %fadd_v16f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:203 CodeSize:35 Lat:41 SizeLat:35 for: %fadd_v11f16 = call fast half @llvm.vector.reduce.fadd.v11f16(half 0xH0000, <11 x half> undef)
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:248 CodeSize:35 Lat:41 SizeLat:35 for: %fadd_v13f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v13f16(half 0xH0000, <13 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:6 SizeLat:4 for: %fadd_v2f16_fast = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:6 SizeLat:4 for: %fadd_v2f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f16_fast = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:48 CodeSize:27 Lat:33 SizeLat:27 for: %fadd_v8f16 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:48 CodeSize:27 Lat:33 SizeLat:27 for: %fadd_v8f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:72 CodeSize:44 Lat:52 SizeLat:44 for: %fadd_v16f16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:72 CodeSize:44 Lat:52 SizeLat:44 for: %fadd_v16f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:203 CodeSize:35 Lat:41 SizeLat:35 for: %fadd_v11f16 = call fast half @llvm.vector.reduce.fadd.v11f16(half 0.000000e+00, <11 x half> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:248 CodeSize:35 Lat:41 SizeLat:35 for: %fadd_v13f16_reassoc = call reassoc half @llvm.vector.reduce.fadd.v13f16(half 0.000000e+00, <13 x half> undef)
; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%fadd_v2f16_fast = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.0, <2 x half> undef)
@@ -175,15 +175,15 @@ define void @fast_fp_reductions_fp16() {
define void @fast_fp_reductions_bf16() {
; CHECK-NOFP16-LABEL: 'fast_fp_reductions_bf16'
-; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:28 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f8 = call reassoc bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR8000, <4 x bfloat> undef)
+; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:28 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f8 = call reassoc bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat -0.000000e+00, <4 x bfloat> undef)
; CHECK-NOFP16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-F16-LABEL: 'fast_fp_reductions_bf16'
-; CHECK-F16-NEXT: Cost Model: Found costs of RThru:28 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f8 = call reassoc bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR8000, <4 x bfloat> undef)
+; CHECK-F16-NEXT: Cost Model: Found costs of RThru:28 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f8 = call reassoc bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat -0.000000e+00, <4 x bfloat> undef)
; CHECK-F16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-BF16-LABEL: 'fast_fp_reductions_bf16'
-; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f8 = call reassoc bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR8000, <4 x bfloat> undef)
+; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:14 CodeSize:8 Lat:12 SizeLat:8 for: %fadd_v4f8 = call reassoc bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat -0.000000e+00, <4 x bfloat> undef)
; CHECK-BF16-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%fadd_v4f8 = call reassoc bfloat @llvm.vector.reduce.fadd.v4f8(bfloat -0.0, <4 x bfloat> undef)
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll b/llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
index 99a9bc2ec04f7..22441a6fe7cb8 100644
--- a/llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
+++ b/llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
@@ -313,11 +313,11 @@ define amdgpu_kernel void @fdiv_f16_f32ftzdaz() #1 {
define amdgpu_kernel void @rcp_ieee() #0 {
; CIFASTF64-LABEL: 'rcp_ieee'
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f16 = fdiv half 0xH3C00, undef
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f32 = fdiv float 1.000000e+00, undef
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -331,11 +331,11 @@ define amdgpu_kernel void @rcp_ieee() #0 {
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; CISLOWF64-LABEL: 'rcp_ieee'
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f16 = fdiv half 0xH3C00, undef
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f32 = fdiv float 1.000000e+00, undef
; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -349,11 +349,11 @@ define amdgpu_kernel void @rcp_ieee() #0 {
; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; SIFASTF64-LABEL: 'rcp_ieee'
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f16 = fdiv half 0xH3C00, undef
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f32 = fdiv float 1.000000e+00, undef
; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -367,11 +367,11 @@ define amdgpu_kernel void @rcp_ieee() #0 {
; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; SISLOWF64-LABEL: 'rcp_ieee'
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f16 = fdiv half 0xH3C00, undef
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f32 = fdiv float 1.000000e+00, undef
; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -385,11 +385,11 @@ define amdgpu_kernel void @rcp_ieee() #0 {
; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; FP16-LABEL: 'rcp_ieee'
-; FP16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 0xH3C00, undef
-; FP16-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; FP16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; FP16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; FP16-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; FP16-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %f32 = fdiv float 1.000000e+00, undef
; FP16-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; FP16-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -403,11 +403,11 @@ define amdgpu_kernel void @rcp_ieee() #0 {
; FP16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; CI-SIZE-LABEL: 'rcp_ieee'
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f16 = fdiv half 0xH3C00, undef
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f32 = fdiv float 1.000000e+00, undef
; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -421,11 +421,11 @@ define amdgpu_kernel void @rcp_ieee() #0 {
; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; SI-SIZE-LABEL: 'rcp_ieee'
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f16 = fdiv half 0xH3C00, undef
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f32 = fdiv float 1.000000e+00, undef
; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -439,11 +439,11 @@ define amdgpu_kernel void @rcp_ieee() #0 {
; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; FP16-SIZE-LABEL: 'rcp_ieee'
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = fdiv half 0xH3C00, undef
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f32 = fdiv float 1.000000e+00, undef
; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -476,11 +476,11 @@ define amdgpu_kernel void @rcp_ieee() #0 {
define amdgpu_kernel void @rcp_ftzdaz() #1 {
; CIFASTF64-LABEL: 'rcp_ftzdaz'
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 0xH3C00, undef
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f32 = fdiv float 1.000000e+00, undef
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -494,11 +494,11 @@ define amdgpu_kernel void @rcp_ftzdaz() #1 {
; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; CISLOWF64-LABEL: 'rcp_ftzdaz'
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 0xH3C00, undef
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f32 = fdiv float 1.000000e+00, undef
; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -512,11 +512,11 @@ define amdgpu_kernel void @rcp_ftzdaz() #1 {
; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; SIFASTF64-LABEL: 'rcp_ftzdaz'
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 0xH3C00, undef
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f32 = fdiv float 1.000000e+00, undef
; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -530,11 +530,11 @@ define amdgpu_kernel void @rcp_ftzdaz() #1 {
; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; SISLOWF64-LABEL: 'rcp_ftzdaz'
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 0xH3C00, undef
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f32 = fdiv float 1.000000e+00, undef
; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -548,11 +548,11 @@ define amdgpu_kernel void @rcp_ftzdaz() #1 {
; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; FP16-LABEL: 'rcp_ftzdaz'
-; FP16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 0xH3C00, undef
-; FP16-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; FP16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; FP16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; FP16-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; FP16-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; FP16-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f32 = fdiv float 1.000000e+00, undef
; FP16-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; FP16-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -566,11 +566,11 @@ define amdgpu_kernel void @rcp_ftzdaz() #1 {
; FP16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; CI-SIZE-LABEL: 'rcp_ftzdaz'
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = fdiv half 0xH3C00, undef
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f32 = fdiv float 1.000000e+00, undef
; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -584,11 +584,11 @@ define amdgpu_kernel void @rcp_ftzdaz() #1 {
; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; SI-SIZE-LABEL: 'rcp_ftzdaz'
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = fdiv half 0xH3C00, undef
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f32 = fdiv float 1.000000e+00, undef
; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
@@ -602,11 +602,11 @@ define amdgpu_kernel void @rcp_ftzdaz() #1 {
; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; FP16-SIZE-LABEL: 'rcp_ftzdaz'
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = fdiv half 0xH3C00, undef
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = fdiv <2 x half> splat (half 0xH3C00), undef
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v3f16 = fdiv <3 x half> splat (half 0xH3C00), undef
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = fdiv <4 x half> splat (half 0xH3C00), undef
-; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5f16 = fdiv <5 x half> splat (half 0xH3C00), undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = fdiv half 1.000000e+00, undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = fdiv <2 x half> splat (half 1.000000e+00), undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v3f16 = fdiv <3 x half> splat (half 1.000000e+00), undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = fdiv <4 x half> splat (half 1.000000e+00), undef
+; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v5f16 = fdiv <5 x half> splat (half 1.000000e+00), undef
; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f32 = fdiv float 1.000000e+00, undef
; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f32 = fdiv <2 x float> splat (float 1.000000e+00), undef
; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f32 = fdiv <3 x float> splat (float 1.000000e+00), undef
diff --git a/llvm/test/Analysis/CostModel/ARM/divrem.ll b/llvm/test/Analysis/CostModel/ARM/divrem.ll
index 461ad9d7d253b..31b5dba9df81f 100644
--- a/llvm/test/Analysis/CostModel/ARM/divrem.ll
+++ b/llvm/test/Analysis/CostModel/ARM/divrem.ll
@@ -279,36 +279,36 @@ define void @f16() {
; CHECK-NEON-LABEL: 'f16'
; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %1 = fdiv half undef, undef
; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %2 = frem half undef, undef
-; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %3 = fdiv half undef, 0xH4000
-; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %4 = frem half undef, 0xH4000
+; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %3 = fdiv half undef, 2.000000e+00
+; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %4 = frem half undef, 2.000000e+00
; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVE-LABEL: 'f16'
; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %1 = fdiv half undef, undef
; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %2 = frem half undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %3 = fdiv half undef, 0xH4000
-; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %4 = frem half undef, 0xH4000
+; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %3 = fdiv half undef, 2.000000e+00
+; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %4 = frem half undef, 2.000000e+00
; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-V8M-MAIN-LABEL: 'f16'
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %1 = fdiv half undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %2 = frem half undef, undef
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %3 = fdiv half undef, 0xH4000
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %4 = frem half undef, 0xH4000
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %3 = fdiv half undef, 2.000000e+00
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %4 = frem half undef, 2.000000e+00
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: ret void
;
; CHECK-V8M-BASE-LABEL: 'f16'
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %1 = fdiv half undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %2 = frem half undef, undef
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %3 = fdiv half undef, 0xH4000
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %4 = frem half undef, 0xH4000
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %3 = fdiv half undef, 2.000000e+00
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %4 = frem half undef, 2.000000e+00
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: ret void
;
; CHECK-V8R-LABEL: 'f16'
; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %1 = fdiv half undef, undef
; CHECK-V8R-NEXT: Cost Model: Found costs of 4 for: %2 = frem half undef, undef
-; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %3 = fdiv half undef, 0xH4000
-; CHECK-V8R-NEXT: Cost Model: Found costs of 4 for: %4 = frem half undef, 0xH4000
+; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %3 = fdiv half undef, 2.000000e+00
+; CHECK-V8R-NEXT: Cost Model: Found costs of 4 for: %4 = frem half undef, 2.000000e+00
; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%1 = fdiv half undef, undef
@@ -1491,48 +1491,48 @@ define void @vi64_2() {
define void @vf16_2() {
; CHECK-NEON-LABEL: 'vf16_2'
-; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %1 = fdiv <2 x half> undef, splat (half 0xH4000)
-; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %2 = frem <2 x half> undef, splat (half 0xH4000)
-; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %3 = fdiv <4 x half> undef, splat (half 0xH4000)
-; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %4 = frem <4 x half> undef, splat (half 0xH4000)
-; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %5 = fdiv <8 x half> undef, splat (half 0xH4000)
-; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %6 = frem <8 x half> undef, splat (half 0xH4000)
+; CHECK-NEON-NEXT: Cost Model: Found costs of 4 for: %1 = fdiv <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %2 = frem <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %3 = fdiv <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %4 = frem <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %5 = fdiv <8 x half> undef, splat (half 2.000000e+00)
+; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %6 = frem <8 x half> undef, splat (half 2.000000e+00)
; CHECK-NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVE-LABEL: 'vf16_2'
-; CHECK-MVE-NEXT: Cost Model: Found costs of 4 for: %1 = fdiv <2 x half> undef, splat (half 0xH4000)
-; CHECK-MVE-NEXT: Cost Model: Found costs of 4 for: %2 = frem <2 x half> undef, splat (half 0xH4000)
-; CHECK-MVE-NEXT: Cost Model: Found costs of 8 for: %3 = fdiv <4 x half> undef, splat (half 0xH4000)
-; CHECK-MVE-NEXT: Cost Model: Found costs of 8 for: %4 = frem <4 x half> undef, splat (half 0xH4000)
-; CHECK-MVE-NEXT: Cost Model: Found costs of 16 for: %5 = fdiv <8 x half> undef, splat (half 0xH4000)
-; CHECK-MVE-NEXT: Cost Model: Found costs of 16 for: %6 = frem <8 x half> undef, splat (half 0xH4000)
+; CHECK-MVE-NEXT: Cost Model: Found costs of 4 for: %1 = fdiv <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-MVE-NEXT: Cost Model: Found costs of 4 for: %2 = frem <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-MVE-NEXT: Cost Model: Found costs of 8 for: %3 = fdiv <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-MVE-NEXT: Cost Model: Found costs of 8 for: %4 = frem <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-MVE-NEXT: Cost Model: Found costs of 16 for: %5 = fdiv <8 x half> undef, splat (half 2.000000e+00)
+; CHECK-MVE-NEXT: Cost Model: Found costs of 16 for: %6 = frem <8 x half> undef, splat (half 2.000000e+00)
; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-V8M-MAIN-LABEL: 'vf16_2'
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 2 for: %1 = fdiv <2 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 2 for: %2 = frem <2 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 4 for: %3 = fdiv <4 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 4 for: %4 = frem <4 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 8 for: %5 = fdiv <8 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 8 for: %6 = frem <8 x half> undef, splat (half 0xH4000)
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 2 for: %1 = fdiv <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 2 for: %2 = frem <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 4 for: %3 = fdiv <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 4 for: %4 = frem <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 8 for: %5 = fdiv <8 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 8 for: %6 = frem <8 x half> undef, splat (half 2.000000e+00)
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: ret void
;
; CHECK-V8M-BASE-LABEL: 'vf16_2'
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 2 for: %1 = fdiv <2 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 2 for: %2 = frem <2 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 4 for: %3 = fdiv <4 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 4 for: %4 = frem <4 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 8 for: %5 = fdiv <8 x half> undef, splat (half 0xH4000)
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 8 for: %6 = frem <8 x half> undef, splat (half 0xH4000)
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 2 for: %1 = fdiv <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 2 for: %2 = frem <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 4 for: %3 = fdiv <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 4 for: %4 = frem <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 8 for: %5 = fdiv <8 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 8 for: %6 = frem <8 x half> undef, splat (half 2.000000e+00)
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: ret void
;
; CHECK-V8R-LABEL: 'vf16_2'
-; CHECK-V8R-NEXT: Cost Model: Found costs of 4 for: %1 = fdiv <2 x half> undef, splat (half 0xH4000)
-; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %2 = frem <2 x half> undef, splat (half 0xH4000)
-; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %3 = fdiv <4 x half> undef, splat (half 0xH4000)
-; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %4 = frem <4 x half> undef, splat (half 0xH4000)
-; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %5 = fdiv <8 x half> undef, splat (half 0xH4000)
-; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %6 = frem <8 x half> undef, splat (half 0xH4000)
+; CHECK-V8R-NEXT: Cost Model: Found costs of 4 for: %1 = fdiv <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %2 = frem <2 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %3 = fdiv <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %4 = frem <4 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %5 = fdiv <8 x half> undef, splat (half 2.000000e+00)
+; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %6 = frem <8 x half> undef, splat (half 2.000000e+00)
; CHECK-V8R-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%1 = fdiv <2 x half> undef, <half 2., half 2.>
diff --git a/llvm/test/Analysis/CostModel/ARM/reduce-fp.ll b/llvm/test/Analysis/CostModel/ARM/reduce-fp.ll
index 392ef5e694883..a5d891743e76b 100644
--- a/llvm/test/Analysis/CostModel/ARM/reduce-fp.ll
+++ b/llvm/test/Analysis/CostModel/ARM/reduce-fp.ll
@@ -7,10 +7,10 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
define void @fadd_strict() {
; CHECK-V8-LABEL: 'fadd_strict'
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:10 SizeLat:6 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:16 CodeSize:12 Lat:20 SizeLat:12 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:32 CodeSize:24 Lat:40 SizeLat:24 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:64 CodeSize:48 Lat:80 SizeLat:48 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:10 SizeLat:6 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:16 CodeSize:12 Lat:20 SizeLat:12 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:32 CodeSize:24 Lat:40 SizeLat:24 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:64 CodeSize:48 Lat:80 SizeLat:48 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:6 SizeLat:2 for: %fadd_v2f32 = call float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:12 SizeLat:4 for: %fadd_v4f32 = call float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:24 SizeLat:8 for: %fadd_v8f32 = call float @llvm.vector.reduce.fadd.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -20,10 +20,10 @@ define void @fadd_strict() {
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVEFP-LABEL: 'fadd_strict'
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 6 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 12 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 24 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 6 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 12 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 24 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 2 for: %fadd_v2f32 = call float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 4 for: %fadd_v4f32 = call float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 8 for: %fadd_v8f32 = call float @llvm.vector.reduce.fadd.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -33,10 +33,10 @@ define void @fadd_strict() {
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVEI-LABEL: 'fadd_strict'
-; CHECK-MVEI-NEXT: Cost Model: Found costs of 4 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of 8 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of 16 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of 32 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of 4 for: %fadd_v2f16 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of 8 for: %fadd_v4f16 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of 16 for: %fadd_v8f16 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of 32 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of 4 for: %fadd_v2f32 = call float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of 8 for: %fadd_v4f32 = call float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of 16 for: %fadd_v8f32 = call float @llvm.vector.reduce.fadd.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -61,10 +61,10 @@ define void @fadd_strict() {
define void @fadd_unordered() {
; CHECK-V8-LABEL: 'fadd_unordered'
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:9 SizeLat:7 for: %fadd_v2f16 = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:20 CodeSize:16 Lat:20 SizeLat:16 for: %fadd_v4f16 = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:44 CodeSize:33 Lat:39 SizeLat:33 for: %fadd_v8f16 = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:92 CodeSize:66 Lat:74 SizeLat:66 for: %fadd_v16f16 = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:9 SizeLat:7 for: %fadd_v2f16 = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:20 CodeSize:16 Lat:20 SizeLat:16 for: %fadd_v4f16 = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:44 CodeSize:33 Lat:39 SizeLat:33 for: %fadd_v8f16 = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:92 CodeSize:66 Lat:74 SizeLat:66 for: %fadd_v16f16 = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:6 SizeLat:2 for: %fadd_v2f32 = call reassoc float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:6 CodeSize:3 Lat:9 SizeLat:3 for: %fadd_v4f32 = call reassoc float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:12 SizeLat:4 for: %fadd_v8f32 = call reassoc float @llvm.vector.reduce.fadd.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -74,10 +74,10 @@ define void @fadd_unordered() {
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVEFP-LABEL: 'fadd_unordered'
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %fadd_v2f16 = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 6 for: %fadd_v4f16 = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:8 SizeLat:8 for: %fadd_v8f16 = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:10 CodeSize:7 Lat:10 SizeLat:10 for: %fadd_v16f16 = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %fadd_v2f16 = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 6 for: %fadd_v4f16 = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:8 SizeLat:8 for: %fadd_v8f16 = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:10 CodeSize:7 Lat:10 SizeLat:10 for: %fadd_v16f16 = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 2 for: %fadd_v2f32 = call reassoc float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 4 for: %fadd_v4f32 = call reassoc float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:6 CodeSize:5 Lat:6 SizeLat:6 for: %fadd_v8f32 = call reassoc float @llvm.vector.reduce.fadd.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -87,10 +87,10 @@ define void @fadd_unordered() {
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVEI-LABEL: 'fadd_unordered'
-; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:15 CodeSize:11 Lat:15 SizeLat:15 for: %fadd_v2f16 = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:57 CodeSize:41 Lat:57 SizeLat:57 for: %fadd_v4f16 = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:169 CodeSize:121 Lat:169 SizeLat:169 for: %fadd_v8f16 = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:225 CodeSize:161 Lat:225 SizeLat:225 for: %fadd_v16f16 = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:15 CodeSize:11 Lat:15 SizeLat:15 for: %fadd_v2f16 = call reassoc half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:57 CodeSize:41 Lat:57 SizeLat:57 for: %fadd_v4f16 = call reassoc half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:169 CodeSize:121 Lat:169 SizeLat:169 for: %fadd_v8f16 = call reassoc half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:225 CodeSize:161 Lat:225 SizeLat:225 for: %fadd_v16f16 = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:15 CodeSize:11 Lat:15 SizeLat:15 for: %fadd_v2f32 = call reassoc float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:57 CodeSize:41 Lat:57 SizeLat:57 for: %fadd_v4f32 = call reassoc float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:85 CodeSize:61 Lat:85 SizeLat:85 for: %fadd_v8f32 = call reassoc float @llvm.vector.reduce.fadd.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -114,10 +114,10 @@ define void @fadd_unordered() {
define void @fmul_strict() {
; CHECK-V8-LABEL: 'fmul_strict'
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:10 SizeLat:6 for: %fmul_v2f16 = call half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:16 CodeSize:12 Lat:20 SizeLat:12 for: %fmul_v4f16 = call half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:32 CodeSize:24 Lat:40 SizeLat:24 for: %fmul_v8f16 = call half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:64 CodeSize:48 Lat:80 SizeLat:48 for: %fmul_v16f16 = call half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:10 SizeLat:6 for: %fmul_v2f16 = call half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:16 CodeSize:12 Lat:20 SizeLat:12 for: %fmul_v4f16 = call half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:32 CodeSize:24 Lat:40 SizeLat:24 for: %fmul_v8f16 = call half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:64 CodeSize:48 Lat:80 SizeLat:48 for: %fmul_v16f16 = call half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:6 SizeLat:2 for: %fmul_v2f32 = call float @llvm.vector.reduce.fmul.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:12 SizeLat:4 for: %fmul_v4f32 = call float @llvm.vector.reduce.fmul.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:16 CodeSize:8 Lat:24 SizeLat:8 for: %fmul_v8f32 = call float @llvm.vector.reduce.fmul.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -127,10 +127,10 @@ define void @fmul_strict() {
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVEFP-LABEL: 'fmul_strict'
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %fmul_v2f16 = call half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 6 for: %fmul_v4f16 = call half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 12 for: %fmul_v8f16 = call half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 24 for: %fmul_v16f16 = call half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %fmul_v2f16 = call half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 6 for: %fmul_v4f16 = call half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 12 for: %fmul_v8f16 = call half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 24 for: %fmul_v16f16 = call half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 2 for: %fmul_v2f32 = call float @llvm.vector.reduce.fmul.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 4 for: %fmul_v4f32 = call float @llvm.vector.reduce.fmul.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 8 for: %fmul_v8f32 = call float @llvm.vector.reduce.fmul.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -140,10 +140,10 @@ define void @fmul_strict() {
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVEI-LABEL: 'fmul_strict'
-; CHECK-MVEI-NEXT: Cost Model: Found costs of 4 for: %fmul_v2f16 = call half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of 8 for: %fmul_v4f16 = call half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of 16 for: %fmul_v8f16 = call half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of 32 for: %fmul_v16f16 = call half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of 4 for: %fmul_v2f16 = call half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of 8 for: %fmul_v4f16 = call half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of 16 for: %fmul_v8f16 = call half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of 32 for: %fmul_v16f16 = call half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of 4 for: %fmul_v2f32 = call float @llvm.vector.reduce.fmul.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of 8 for: %fmul_v4f32 = call float @llvm.vector.reduce.fmul.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of 16 for: %fmul_v8f32 = call float @llvm.vector.reduce.fmul.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -168,10 +168,10 @@ define void @fmul_strict() {
define void @fmul_unordered() {
; CHECK-V8-LABEL: 'fmul_unordered'
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:9 SizeLat:7 for: %fmul_v2f16 = call reassoc half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:20 CodeSize:16 Lat:20 SizeLat:16 for: %fmul_v4f16 = call reassoc half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:44 CodeSize:33 Lat:39 SizeLat:33 for: %fmul_v8f16 = call reassoc half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-V8-NEXT: Cost Model: Found costs of RThru:92 CodeSize:66 Lat:74 SizeLat:66 for: %fmul_v16f16 = call reassoc half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:9 SizeLat:7 for: %fmul_v2f16 = call reassoc half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:20 CodeSize:16 Lat:20 SizeLat:16 for: %fmul_v4f16 = call reassoc half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:44 CodeSize:33 Lat:39 SizeLat:33 for: %fmul_v8f16 = call reassoc half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-V8-NEXT: Cost Model: Found costs of RThru:92 CodeSize:66 Lat:74 SizeLat:66 for: %fmul_v16f16 = call reassoc half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:6 SizeLat:2 for: %fmul_v2f32 = call reassoc float @llvm.vector.reduce.fmul.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:6 CodeSize:3 Lat:9 SizeLat:3 for: %fmul_v4f32 = call reassoc float @llvm.vector.reduce.fmul.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:12 SizeLat:4 for: %fmul_v8f32 = call reassoc float @llvm.vector.reduce.fmul.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -181,10 +181,10 @@ define void @fmul_unordered() {
; CHECK-V8-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVEFP-LABEL: 'fmul_unordered'
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %fmul_v2f16 = call reassoc half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of 6 for: %fmul_v4f16 = call reassoc half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:8 SizeLat:8 for: %fmul_v8f16 = call reassoc half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:10 CodeSize:7 Lat:10 SizeLat:10 for: %fmul_v16f16 = call reassoc half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %fmul_v2f16 = call reassoc half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of 6 for: %fmul_v4f16 = call reassoc half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:8 SizeLat:8 for: %fmul_v8f16 = call reassoc half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:10 CodeSize:7 Lat:10 SizeLat:10 for: %fmul_v16f16 = call reassoc half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 2 for: %fmul_v2f32 = call reassoc float @llvm.vector.reduce.fmul.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 4 for: %fmul_v4f32 = call reassoc float @llvm.vector.reduce.fmul.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:6 CodeSize:5 Lat:6 SizeLat:6 for: %fmul_v8f32 = call reassoc float @llvm.vector.reduce.fmul.v8f32(float 0.000000e+00, <8 x float> undef)
@@ -194,10 +194,10 @@ define void @fmul_unordered() {
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-MVEI-LABEL: 'fmul_unordered'
-; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:15 CodeSize:11 Lat:15 SizeLat:15 for: %fmul_v2f16 = call reassoc half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:57 CodeSize:41 Lat:57 SizeLat:57 for: %fmul_v4f16 = call reassoc half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:169 CodeSize:121 Lat:169 SizeLat:169 for: %fmul_v8f16 = call reassoc half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:225 CodeSize:161 Lat:225 SizeLat:225 for: %fmul_v16f16 = call reassoc half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:15 CodeSize:11 Lat:15 SizeLat:15 for: %fmul_v2f16 = call reassoc half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:57 CodeSize:41 Lat:57 SizeLat:57 for: %fmul_v4f16 = call reassoc half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:169 CodeSize:121 Lat:169 SizeLat:169 for: %fmul_v8f16 = call reassoc half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:225 CodeSize:161 Lat:225 SizeLat:225 for: %fmul_v16f16 = call reassoc half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:15 CodeSize:11 Lat:15 SizeLat:15 for: %fmul_v2f32 = call reassoc float @llvm.vector.reduce.fmul.v2f32(float 0.000000e+00, <2 x float> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:57 CodeSize:41 Lat:57 SizeLat:57 for: %fmul_v4f32 = call reassoc float @llvm.vector.reduce.fmul.v4f32(float 0.000000e+00, <4 x float> undef)
; CHECK-MVEI-NEXT: Cost Model: Found costs of RThru:85 CodeSize:61 Lat:85 SizeLat:85 for: %fmul_v8f32 = call reassoc float @llvm.vector.reduce.fmul.v8f32(float 0.000000e+00, <8 x float> undef)
diff --git a/llvm/test/Analysis/CostModel/RISCV/phi-const.ll b/llvm/test/Analysis/CostModel/RISCV/phi-const.ll
index 00ff1925fc06c..d8b7764ac9e37 100644
--- a/llvm/test/Analysis/CostModel/RISCV/phi-const.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/phi-const.ll
@@ -132,7 +132,7 @@ define half @phi_f16(i1 %c) {
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br i1 %c, label %a, label %b
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br label %d
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br label %d
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %x = phi half [ 0xHE3CE, %a ], [ 0xH5144, %b ]
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %x = phi half [ -9.990000e+02, %a ], [ 4.212500e+01, %b ]
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret half %x
;
br i1 %c, label %a, label %b
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
index 71685b4acc822..9ee33d4b5a31e 100644
--- a/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
@@ -6,71 +6,71 @@
define void @reduce_fadd_bfloat() {
; FP-REDUCE-ZVFH-LABEL: 'reduce_fadd_bfloat'
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_fadd_bfloat'
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-LABEL: 'reduce_fadd_bfloat'
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_fadd_bfloat'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.0, <1 x bfloat> undef)
@@ -92,71 +92,71 @@ define void @reduce_fadd_bfloat() {
define void @reduce_fadd_half() {
; FP-REDUCE-ZVFH-LABEL: 'reduce_fadd_half'
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_fadd_half'
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-LABEL: 'reduce_fadd_half'
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_fadd_half'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0.000000e+00, <1 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0.000000e+00, <64 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0.000000e+00, <128 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0.0, <1 x half> undef)
@@ -273,71 +273,71 @@ define void @reduce_fadd_double() {
define void @reduce_ordered_fadd_bfloat() {
; FP-REDUCE-ZVFH-LABEL: 'reduce_ordered_fadd_bfloat'
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_ordered_fadd_bfloat'
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-LABEL: 'reduce_ordered_fadd_bfloat'
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_ordered_fadd_bfloat'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V8 = call bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V16 = call bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V8 = call bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V16 = call bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.0, <1 x bfloat> undef)
@@ -359,71 +359,71 @@ define void @reduce_ordered_fadd_bfloat() {
define void @reduce_ordered_fadd_half() {
; FP-REDUCE-ZVFH-LABEL: 'reduce_ordered_fadd_half'
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_ordered_fadd_half'
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-LABEL: 'reduce_ordered_fadd_half'
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-NO-ZFHMIN-NO-ZFBFMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_ordered_fadd_half'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8 = call half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0.000000e+00, <1 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8 = call half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0.000000e+00, <64 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0.000000e+00, <128 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0.0, <1 x half> undef)
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll
index 211bcb1343eea..2fb74b479e94a 100644
--- a/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll
@@ -5,37 +5,37 @@
define void @reduce_fmul_bfloat() {
; FP-REDUCE-LABEL: 'reduce_fmul_bfloat'
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fmul.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fmul.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fmul.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fmul.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fmul.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fmul.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fmul.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fmul.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_fmul_bfloat'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fmul.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fmul.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fmul.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fmul.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call fast bfloat @llvm.vector.reduce.fmul.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call fast bfloat @llvm.vector.reduce.fmul.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call fast bfloat @llvm.vector.reduce.fmul.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call fast bfloat @llvm.vector.reduce.fmul.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%V1 = call fast bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.0, <1 x bfloat> undef)
@@ -57,54 +57,54 @@ define void @reduce_fmul_bfloat() {
define void @reduce_fmul_half() {
; FP-REDUCE-ZVFH-LABEL: 'reduce_fmul_half'
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call fast half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V4 = call fast half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8 = call fast half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V16 = call fast half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 151 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call fast half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V4 = call fast half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8 = call fast half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V16 = call fast half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 151 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_fmul_half'
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call fast half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call fast half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call fast half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call fast half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_fmul_half'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0xH0000, <1 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call fast half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call fast half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call fast half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call fast half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0.000000e+00, <1 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call fast half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call fast half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call fast half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call fast half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0.000000e+00, <32 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0.000000e+00, <64 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0.000000e+00, <128 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0.0, <1 x half> undef)
@@ -221,37 +221,37 @@ define void @reduce_fmul_double() {
define void @reduce_ordered_fmul_bfloat() {
; FP-REDUCE-LABEL: 'reduce_ordered_fmul_bfloat'
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call bfloat @llvm.vector.reduce.fmul.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call bfloat @llvm.vector.reduce.fmul.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call bfloat @llvm.vector.reduce.fmul.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call bfloat @llvm.vector.reduce.fmul.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call bfloat @llvm.vector.reduce.fmul.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call bfloat @llvm.vector.reduce.fmul.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call bfloat @llvm.vector.reduce.fmul.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call bfloat @llvm.vector.reduce.fmul.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_ordered_fmul_bfloat'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0xR0000, <1 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call bfloat @llvm.vector.reduce.fmul.v2bf16(bfloat 0xR0000, <2 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call bfloat @llvm.vector.reduce.fmul.v4bf16(bfloat 0xR0000, <4 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V8 = call bfloat @llvm.vector.reduce.fmul.v8bf16(bfloat 0xR0000, <8 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V16 = call bfloat @llvm.vector.reduce.fmul.v16bf16(bfloat 0xR0000, <16 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, <vscale x 1 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, <vscale x 2 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, <vscale x 4 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, <vscale x 8 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, <vscale x 16 x bfloat> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, <vscale x 32 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.000000e+00, <1 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call bfloat @llvm.vector.reduce.fmul.v2bf16(bfloat 0.000000e+00, <2 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call bfloat @llvm.vector.reduce.fmul.v4bf16(bfloat 0.000000e+00, <4 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V8 = call bfloat @llvm.vector.reduce.fmul.v8bf16(bfloat 0.000000e+00, <8 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V16 = call bfloat @llvm.vector.reduce.fmul.v16bf16(bfloat 0.000000e+00, <16 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0.000000e+00, <32 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0.000000e+00, <64 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0.000000e+00, <128 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0.000000e+00, <vscale x 1 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0.000000e+00, <vscale x 2 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0.000000e+00, <vscale x 4 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0.000000e+00, <vscale x 8 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0.000000e+00, <vscale x 16 x bfloat> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0.000000e+00, <vscale x 32 x bfloat> undef)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%V1 = call bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.0, <1 x bfloat> undef)
@@ -273,37 +273,37 @@ define void @reduce_ordered_fmul_bfloat() {
define void @reduce_ordered_fmul_half() {
; FP-REDUCE-LABEL: 'reduce_ordered_fmul_half'
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fmul.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fmul.v1f16(half 0.000000e+00, <1 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8 = call half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16 = call half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0.000000e+00, <32 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0.000000e+00, <64 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0.000000e+00, <128 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_ordered_fmul_half'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call half @llvm.vector.reduce.fmul.v1f16(half 0xH0000, <1 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call half @llvm.vector.reduce.fmul.v2f16(half 0xH0000, <2 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call half @llvm.vector.reduce.fmul.v4f16(half 0xH0000, <4 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V8 = call half @llvm.vector.reduce.fmul.v8f16(half 0xH0000, <8 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V16 = call half @llvm.vector.reduce.fmul.v16f16(half 0xH0000, <16 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, <vscale x 1 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, <vscale x 2 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, <vscale x 4 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, <vscale x 8 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, <vscale x 16 x half> undef)
-; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, <vscale x 32 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call half @llvm.vector.reduce.fmul.v1f16(half 0.000000e+00, <1 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call half @llvm.vector.reduce.fmul.v2f16(half 0.000000e+00, <2 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call half @llvm.vector.reduce.fmul.v4f16(half 0.000000e+00, <4 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V8 = call half @llvm.vector.reduce.fmul.v8f16(half 0.000000e+00, <8 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V16 = call half @llvm.vector.reduce.fmul.v16f16(half 0.000000e+00, <16 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0.000000e+00, <32 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0.000000e+00, <64 x half> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0.000000e+00, <128 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0.000000e+00, <vscale x 1 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0.000000e+00, <vscale x 2 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0.000000e+00, <vscale x 4 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0.000000e+00, <vscale x 8 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0.000000e+00, <vscale x 16 x half> undef)
+; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0.000000e+00, <vscale x 32 x half> undef)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%V1 = call half @llvm.vector.reduce.fmul.v1f16(half 0.0, <1 x half> undef)
diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll
index 344a34fa9a630..7be85beb88247 100644
--- a/llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll
@@ -316,7 +316,7 @@ define <4 x half> @phi_v4f16_splat(i1 %c) {
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br i1 %c, label %a, label %b
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br label %d
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br label %d
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %x = phi <4 x half> [ splat (half 0xH3C00), %a ], [ <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4D00>, %b ]
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %x = phi <4 x half> [ splat (half 1.000000e+00), %a ], [ <half 2.000000e+00, half 2.000000e+00, half 2.000000e+00, half 2.000000e+01>, %b ]
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x half> %x
;
br i1 %c, label %a, label %b
@@ -334,7 +334,7 @@ define <4 x half> @phi_v4f16(i1 %c) {
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br i1 %c, label %a, label %b
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br label %d
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br label %d
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %x = phi <4 x half> [ <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400>, %a ], [ <half 0xH4000, half 0xH4400, half 0xH4600, half 0xH4800>, %b ]
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %x = phi <4 x half> [ <half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00>, %a ], [ <half 2.000000e+00, half 4.000000e+00, half 6.000000e+00, half 8.000000e+00>, %b ]
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x half> %x
;
br i1 %c, label %a, label %b
@@ -353,7 +353,7 @@ define <4 x half> @phi_v4f16_cheap_and_expensive(i1 %c) {
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br i1 %c, label %a, label %b
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br label %d
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: br label %d
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %x = phi <4 x half> [ splat (half 0xH3C00), %a ], [ <half 0xH6F42, half 0xHECB8, half 0xH5DF6, half 0xH4A40>, %b ]
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %x = phi <4 x half> [ splat (half 1.000000e+00), %a ], [ <half 7.432000e+03, half -4.832000e+03, half 3.815000e+02, half 1.250000e+01>, %b ]
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x half> %x
;
br i1 %c, label %a, label %b
diff --git a/llvm/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll b/llvm/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll
index 09b7ff5836d2a..279c22d041846 100644
--- a/llvm/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll
+++ b/llvm/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll
@@ -91,7 +91,7 @@ for.end: ; preds = %for.body
; CHECK: define float @test1(
-; CHECK: ret float 0x3FD3333340000000
+; CHECK: ret float 3.000000e-01
define float @test1(ptr %a) nounwind {
entry:
diff --git a/llvm/test/Assembler/2002-04-07-InfConstant.ll b/llvm/test/Assembler/2002-04-07-InfConstant.ll
index d5cbfa755f39b..5a5470f463f5e 100644
--- a/llvm/test/Assembler/2002-04-07-InfConstant.ll
+++ b/llvm/test/Assembler/2002-04-07-InfConstant.ll
@@ -3,7 +3,7 @@
; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
; RUN: verify-uselistorder %s
-; CHECK: fmul float 0x7FF0000000000000, 1.000000e+01
+; CHECK: fmul float +inf, 1.000000e+01
define float @test() {
%tmp = fmul float 0x7FF0000000000000, 1.000000e+01 ; <float> [#uses=1]
ret float %tmp
diff --git a/llvm/test/Assembler/2005-01-03-FPConstantDisassembly.ll b/llvm/test/Assembler/2005-01-03-FPConstantDisassembly.ll
index 643d04c84b3fb..0de6339db1dec 100644
--- a/llvm/test/Assembler/2005-01-03-FPConstantDisassembly.ll
+++ b/llvm/test/Assembler/2005-01-03-FPConstantDisassembly.ll
@@ -2,7 +2,7 @@
; RUN: verify-uselistorder %s
define double @test() {
-; CHECK: ret double 1.0
+; CHECK: ret double 1.000000e+00
ret double 1.0 ;; This should not require hex notation
}
diff --git a/llvm/test/Assembler/constant-splat.ll b/llvm/test/Assembler/constant-splat.ll
index 82e25adda0e10..4592119cea7bc 100644
--- a/llvm/test/Assembler/constant-splat.ll
+++ b/llvm/test/Assembler/constant-splat.ll
@@ -15,7 +15,7 @@
; CHECK: @constant.splat.i128 = constant <2 x i128> splat (i128 85070591730234615870450834276742070272)
@constant.splat.i128 = constant <2 x i128> splat (i128 85070591730234615870450834276742070272)
-; CHECK: @constant.splat.f16 = constant <4 x half> splat (half 0xHBC00)
+; CHECK: @constant.splat.f16 = constant <4 x half> splat (half -1.000000e+00)
@constant.splat.f16 = constant <4 x half> splat (half 0xHBC00)
; CHECK: @constant.splat.f32 = constant <5 x float> splat (float -2.000000e+00)
@@ -24,16 +24,16 @@
; CHECK: @constant.splat.f64 = constant <3 x double> splat (double -3.000000e+00)
@constant.splat.f64 = constant <3 x double> splat (double -3.000000e+00)
-; CHECK: @constant.splat.128 = constant <2 x fp128> splat (fp128 0xL00000000000000018000000000000000)
+; CHECK: @constant.splat.128 = constant <2 x fp128> splat (fp128 -6.475180e-4966)
@constant.splat.128 = constant <2 x fp128> splat (fp128 0xL00000000000000018000000000000000)
-; CHECK: @constant.splat.bf16 = constant <4 x bfloat> splat (bfloat 0xRC0A0)
+; CHECK: @constant.splat.bf16 = constant <4 x bfloat> splat (bfloat -5.000000e+00)
@constant.splat.bf16 = constant <4 x bfloat> splat (bfloat 0xRC0A0)
-; CHECK: @constant.splat.x86_fp80 = constant <3 x x86_fp80> splat (x86_fp80 0xK4000C8F5C28F5C28F800)
+; CHECK: @constant.splat.x86_fp80 = constant <3 x x86_fp80> splat (x86_fp80 f0x4000C8F5C28F5C28F800)
@constant.splat.x86_fp80 = constant <3 x x86_fp80> splat (x86_fp80 0xK4000C8F5C28F5C28F800)
-; CHECK: @constant.splat.ppc_fp128 = constant <1 x ppc_fp128> splat (ppc_fp128 0xM80000000000000000000000000000000)
+; CHECK: @constant.splat.ppc_fp128 = constant <1 x ppc_fp128> splat (ppc_fp128 -0.000000e+00)
@constant.splat.ppc_fp128 = constant <1 x ppc_fp128> splat (ppc_fp128 0xM80000000000000000000000000000000)
; CHECK: @constant.splat.global.ptr = constant <4 x ptr> <ptr @my_global, ptr @my_global, ptr @my_global, ptr @my_global>
diff --git a/llvm/test/Assembler/float-literals.ll b/llvm/test/Assembler/float-literals.ll
index 2a3e0ad8de515..6a136f195e8db 100644
--- a/llvm/test/Assembler/float-literals.ll
+++ b/llvm/test/Assembler/float-literals.ll
@@ -39,12 +39,12 @@
@5 = global float +snan(0x1)
; CHECK: @6 = global x86_fp80 f0x0001FFFF000000000000
@6 = global x86_fp80 f0x0000ffff000000000000
-; CHECK: @7 = global float 0xB810000000000000
+; CHECK: @7 = global float f0x80800000
@7 = global float -0x1.0p-126
-; CHECK: @8 = global double 0x7FEFFFFFFFFFFFFF
+; CHECK: @8 = global double f0x7FEFFFFFFFFFFFFF
@8 = global double 1.79769313486231570815e+308
-; CHECK-COUNT-3: global half 0xH01E3
+; CHECK-COUNT-3: global half 2.878900e-05
@denormal.hex = global half +0x1.e3p-16
@denormal.dec = global half 2.878904342651367875e-5
@denormal.bits = global half f0x01e3
diff --git a/llvm/test/Assembler/short-hexpair.ll b/llvm/test/Assembler/short-hexpair.ll
index 067ea30b0ddb3..830c503810031 100644
--- a/llvm/test/Assembler/short-hexpair.ll
+++ b/llvm/test/Assembler/short-hexpair.ll
@@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
@x = global fp128 0xL01
-; CHECK: @x = global fp128 0xL00000000000000000000000000000001
+; CHECK: @x = global fp128 f0x00000000000000010000000000000000
diff --git a/llvm/test/Bitcode/compatibility-3.6.ll b/llvm/test/Bitcode/compatibility-3.6.ll
index 987017e9f2793..288e0fc50a9ba 100644
--- a/llvm/test/Bitcode/compatibility-3.6.ll
+++ b/llvm/test/Bitcode/compatibility-3.6.ll
@@ -56,7 +56,7 @@ $comdat2 = comdat any
@const.int = constant i32 zeroinitializer
; CHECK: @const.int = constant i32 0
@const.float = constant double 0.0
-; CHECK: @const.float = constant double 0.0
+; CHECK: @const.float = constant double 0.000000e+00
@const.null = constant i8* null
; CHECK: @const.null = constant ptr null
%const.struct.type = type { i32, i8 }
diff --git a/llvm/test/Bitcode/compatibility-3.7.ll b/llvm/test/Bitcode/compatibility-3.7.ll
index 0e6668d871ca0..ef9490310fe5d 100644
--- a/llvm/test/Bitcode/compatibility-3.7.ll
+++ b/llvm/test/Bitcode/compatibility-3.7.ll
@@ -36,7 +36,7 @@ $comdat.samesize = comdat samesize
@const.int = constant i32 zeroinitializer
; CHECK: @const.int = constant i32 0
@const.float = constant double 0.0
-; CHECK: @const.float = constant double 0.0
+; CHECK: @const.float = constant double 0.000000e+00
@const.null = constant i8* null
; CHECK: @const.null = constant ptr null
%const.struct.type = type { i32, i8 }
diff --git a/llvm/test/Bitcode/compatibility-3.8.ll b/llvm/test/Bitcode/compatibility-3.8.ll
index 553abc6efd778..538d6101b3994 100644
--- a/llvm/test/Bitcode/compatibility-3.8.ll
+++ b/llvm/test/Bitcode/compatibility-3.8.ll
@@ -35,7 +35,7 @@ $comdat.samesize = comdat samesize
@const.int = constant i32 zeroinitializer
; CHECK: @const.int = constant i32 0
@const.float = constant double 0.0
-; CHECK: @const.float = constant double 0.0
+; CHECK: @const.float = constant double 0.000000e+00
@const.null = constant i8* null
; CHECK: @const.null = constant ptr null
%const.struct.type = type { i32, i8 }
@@ -53,7 +53,7 @@ $comdat.samesize = comdat samesize
@constant.array.i32 = constant [3 x i32] [i32 -0, i32 1, i32 0]
; CHECK: @constant.array.i64 = constant [3 x i64] [i64 0, i64 1, i64 0]
@constant.array.i64 = constant [3 x i64] [i64 -0, i64 1, i64 0]
-; CHECK: @constant.array.f16 = constant [3 x half] [half 0xH8000, half 0xH3C00, half 0xH0000]
+; CHECK: @constant.array.f16 = constant [3 x half] [half -0.000000e+00, half 1.000000e+00, half 0.000000e+00]
@constant.array.f16 = constant [3 x half] [half -0.0, half 1.0, half 0.0]
; CHECK: @constant.array.f32 = constant [3 x float] [float -0.000000e+00, float 1.000000e+00, float 0.000000e+00]
@constant.array.f32 = constant [3 x float] [float -0.0, float 1.0, float 0.0]
@@ -68,7 +68,7 @@ $comdat.samesize = comdat samesize
@constant.vector.i32 = constant <3 x i32> <i32 -0, i32 1, i32 0>
; CHECK: @constant.vector.i64 = constant <3 x i64> <i64 0, i64 1, i64 0>
@constant.vector.i64 = constant <3 x i64> <i64 -0, i64 1, i64 0>
-; CHECK: @constant.vector.f16 = constant <3 x half> <half 0xH8000, half 0xH3C00, half 0xH0000>
+; CHECK: @constant.vector.f16 = constant <3 x half> <half -0.000000e+00, half 1.000000e+00, half 0.000000e+00>
@constant.vector.f16 = constant <3 x half> <half -0.0, half 1.0, half 0.0>
; CHECK: @constant.vector.f32 = constant <3 x float> <float -0.000000e+00, float 1.000000e+00, float 0.000000e+00>
@constant.vector.f32 = constant <3 x float> <float -0.0, float 1.0, float 0.0>
diff --git a/llvm/test/Bitcode/compatibility-3.9.ll b/llvm/test/Bitcode/compatibility-3.9.ll
index 10652265082ad..3bfef73e485dd 100644
--- a/llvm/test/Bitcode/compatibility-3.9.ll
+++ b/llvm/test/Bitcode/compatibility-3.9.ll
@@ -35,7 +35,7 @@ $comdat.samesize = comdat samesize
@const.int = constant i32 zeroinitializer
; CHECK: @const.int = constant i32 0
@const.float = constant double 0.0
-; CHECK: @const.float = constant double 0.0
+; CHECK: @const.float = constant double 0.000000e+00
@const.null = constant i8* null
; CHECK: @const.null = constant ptr null
%const.struct.type = type { i32, i8 }
@@ -53,7 +53,7 @@ $comdat.samesize = comdat samesize
@constant.array.i32 = constant [3 x i32] [i32 -0, i32 1, i32 0]
; CHECK: @constant.array.i64 = constant [3 x i64] [i64 0, i64 1, i64 0]
@constant.array.i64 = constant [3 x i64] [i64 -0, i64 1, i64 0]
-; CHECK: @constant.array.f16 = constant [3 x half] [half 0xH8000, half 0xH3C00, half 0xH0000]
+; CHECK: @constant.array.f16 = constant [3 x half] [half -0.000000e+00, half 1.000000e+00, half 0.000000e+00]
@constant.array.f16 = constant [3 x half] [half -0.0, half 1.0, half 0.0]
; CHECK: @constant.array.f32 = constant [3 x float] [float -0.000000e+00, float 1.000000e+00, float 0.000000e+00]
@constant.array.f32 = constant [3 x float] [float -0.0, float 1.0, float 0.0]
@@ -68,7 +68,7 @@ $comdat.samesize = comdat samesize
@constant.vector.i32 = constant <3 x i32> <i32 -0, i32 1, i32 0>
; CHECK: @constant.vector.i64 = constant <3 x i64> <i64 0, i64 1, i64 0>
@constant.vector.i64 = constant <3 x i64> <i64 -0, i64 1, i64 0>
-; CHECK: @constant.vector.f16 = constant <3 x half> <half 0xH8000, half 0xH3C00, half 0xH0000>
+; CHECK: @constant.vector.f16 = constant <3 x half> <half -0.000000e+00, half 1.000000e+00, half 0.000000e+00>
@constant.vector.f16 = constant <3 x half> <half -0.0, half 1.0, half 0.0>
; CHECK: @constant.vector.f32 = constant <3 x float> <float -0.000000e+00, float 1.000000e+00, float 0.000000e+00>
@constant.vector.f32 = constant <3 x float> <float -0.0, float 1.0, float 0.0>
diff --git a/llvm/test/Bitcode/compatibility-4.0.ll b/llvm/test/Bitcode/compatibility-4.0.ll
index d9b6360e1d0eb..aaf9fe5492171 100644
--- a/llvm/test/Bitcode/compatibility-4.0.ll
+++ b/llvm/test/Bitcode/compatibility-4.0.ll
@@ -35,7 +35,7 @@ $comdat.samesize = comdat samesize
@const.int = constant i32 zeroinitializer
; CHECK: @const.int = constant i32 0
@const.float = constant double 0.0
-; CHECK: @const.float = constant double 0.0
+; CHECK: @const.float = constant double 0.000000e+00
@const.null = constant i8* null
; CHECK: @const.null = constant ptr null
%const.struct.type = type { i32, i8 }
@@ -53,7 +53,7 @@ $comdat.samesize = comdat samesize
@constant.array.i32 = constant [3 x i32] [i32 -0, i32 1, i32 0]
; CHECK: @constant.array.i64 = constant [3 x i64] [i64 0, i64 1, i64 0]
@constant.array.i64 = constant [3 x i64] [i64 -0, i64 1, i64 0]
-; CHECK: @constant.array.f16 = constant [3 x half] [half 0xH8000, half 0xH3C00, half 0xH0000]
+; CHECK: @constant.array.f16 = constant [3 x half] [half -0.000000e+00, half 1.000000e+00, half 0.000000e+00]
@constant.array.f16 = constant [3 x half] [half -0.0, half 1.0, half 0.0]
; CHECK: @constant.array.f32 = constant [3 x float] [float -0.000000e+00, float 1.000000e+00, float 0.000000e+00]
@constant.array.f32 = constant [3 x float] [float -0.0, float 1.0, float 0.0]
@@ -68,7 +68,7 @@ $comdat.samesize = comdat samesize
@constant.vector.i32 = constant <3 x i32> <i32 -0, i32 1, i32 0>
; CHECK: @constant.vector.i64 = constant <3 x i64> <i64 0, i64 1, i64 0>
@constant.vector.i64 = constant <3 x i64> <i64 -0, i64 1, i64 0>
-; CHECK: @constant.vector.f16 = constant <3 x half> <half 0xH8000, half 0xH3C00, half 0xH0000>
+; CHECK: @constant.vector.f16 = constant <3 x half> <half -0.000000e+00, half 1.000000e+00, half 0.000000e+00>
@constant.vector.f16 = constant <3 x half> <half -0.0, half 1.0, half 0.0>
; CHECK: @constant.vector.f32 = constant <3 x float> <float -0.000000e+00, float 1.000000e+00, float 0.000000e+00>
@constant.vector.f32 = constant <3 x float> <float -0.0, float 1.0, float 0.0>
diff --git a/llvm/test/Bitcode/compatibility-5.0.ll b/llvm/test/Bitcode/compatibility-5.0.ll
index 95d05acb4ea47..b820417107e8b 100644
--- a/llvm/test/Bitcode/compatibility-5.0.ll
+++ b/llvm/test/Bitcode/compatibility-5.0.ll
@@ -35,7 +35,7 @@ $comdat.samesize = comdat samesize
@const.int = constant i32 zeroinitializer
; CHECK: @const.int = constant i32 0
@const.float = constant double 0.0
-; CHECK: @const.float = constant double 0.0
+; CHECK: @const.float = constant double 0.000000e+00
@const.null = constant i8* null
; CHECK: @const.null = constant ptr null
%const.struct.type = type { i32, i8 }
@@ -53,7 +53,7 @@ $comdat.samesize = comdat samesize
@constant.array.i32 = constant [3 x i32] [i32 -0, i32 1, i32 0]
; CHECK: @constant.array.i64 = constant [3 x i64] [i64 0, i64 1, i64 0]
@constant.array.i64 = constant [3 x i64] [i64 -0, i64 1, i64 0]
-; CHECK: @constant.array.f16 = constant [3 x half] [half 0xH8000, half 0xH3C00, half 0xH0000]
+; CHECK: @constant.array.f16 = constant [3 x half] [half -0.000000e+00, half 1.000000e+00, half 0.000000e+00]
@constant.array.f16 = constant [3 x half] [half -0.0, half 1.0, half 0.0]
; CHECK: @constant.array.f32 = constant [3 x float] [float -0.000000e+00, float 1.000000e+00, float 0.000000e+00]
@constant.array.f32 = constant [3 x float] [float -0.0, float 1.0, float 0.0]
@@ -68,7 +68,7 @@ $comdat.samesize = comdat samesize
@constant.vector.i32 = constant <3 x i32> <i32 -0, i32 1, i32 0>
; CHECK: @constant.vector.i64 = constant <3 x i64> <i64 0, i64 1, i64 0>
@constant.vector.i64 = constant <3 x i64> <i64 -0, i64 1, i64 0>
-; CHECK: @constant.vector.f16 = constant <3 x half> <half 0xH8000, half 0xH3C00, half 0xH0000>
+; CHECK: @constant.vector.f16 = constant <3 x half> <half -0.000000e+00, half 1.000000e+00, half 0.000000e+00>
@constant.vector.f16 = constant <3 x half> <half -0.0, half 1.0, half 0.0>
; CHECK: @constant.vector.f32 = constant <3 x float> <float -0.000000e+00, float 1.000000e+00, float 0.000000e+00>
@constant.vector.f32 = constant <3 x float> <float -0.0, float 1.0, float 0.0>
diff --git a/llvm/test/Bitcode/compatibility-6.0.ll b/llvm/test/Bitcode/compatibility-6.0.ll
index e82a0b31a1d79..67e96c7277cc3 100644
--- a/llvm/test/Bitcode/compatibility-6.0.ll
+++ b/llvm/test/Bitcode/compatibility-6.0.ll
@@ -35,7 +35,7 @@ $comdat.samesize = comdat samesize
@const.int = constant i32 zeroinitializer
; CHECK: @const.int = constant i32 0
@const.float = constant double 0.0
-; CHECK: @const.float = constant double 0.0
+; CHECK: @const.float = constant double 0.000000e+00
@const.null = constant i8* null
; CHECK: @const.null = constant ptr null
%const.struct.type = type { i32, i8 }
@@ -53,7 +53,7 @@ $comdat.samesize = comdat samesize
@constant.array.i32 = constant [3 x i32] [i32 -0, i32 1, i32 0]
; CHECK: @constant.array.i64 = constant [3 x i64] [i64 0, i64 1, i64 0]
@constant.array.i64 = constant [3 x i64] [i64 -0, i64 1, i64 0]
-; CHECK: @constant.array.f16 = constant [3 x half] [half 0xH8000, half 0xH3C00, half 0xH0000]
+; CHECK: @constant.array.f16 = constant [3 x half] [half -0.000000e+00, half 1.000000e+00, half 0.000000e+00]
@constant.array.f16 = constant [3 x half] [half -0.0, half 1.0, half 0.0]
; CHECK: @constant.array.f32 = constant [3 x float] [float -0.000000e+00, float 1.000000e+00, float 0.000000e+00]
@constant.array.f32 = constant [3 x float] [float -0.0, float 1.0, float 0.0]
@@ -68,7 +68,7 @@ $comdat.samesize = comdat samesize
@constant.vector.i32 = constant <3 x i32> <i32 -0, i32 1, i32 0>
; CHECK: @constant.vector.i64 = constant <3 x i64> <i64 0, i64 1, i64 0>
@constant.vector.i64 = constant <3 x i64> <i64 -0, i64 1, i64 0>
-; CHECK: @constant.vector.f16 = constant <3 x half> <half 0xH8000, half 0xH3C00, half 0xH0000>
+; CHECK: @constant.vector.f16 = constant <3 x half> <half -0.000000e+00, half 1.000000e+00, half 0.000000e+00>
@constant.vector.f16 = constant <3 x half> <half -0.0, half 1.0, half 0.0>
; CHECK: @constant.vector.f32 = constant <3 x float> <float -0.000000e+00, float 1.000000e+00, float 0.000000e+00>
@constant.vector.f32 = constant <3 x float> <float -0.0, float 1.0, float 0.0>
diff --git a/llvm/test/Bitcode/compatibility.ll b/llvm/test/Bitcode/compatibility.ll
index 3c154633740ee..c9a048e58e6d1 100644
--- a/llvm/test/Bitcode/compatibility.ll
+++ b/llvm/test/Bitcode/compatibility.ll
@@ -38,7 +38,7 @@ $comdat.samesize = comdat samesize
@const.int = constant i32 zeroinitializer
; CHECK: @const.int = constant i32 0
@const.float = constant double 0.0
-; CHECK: @const.float = constant double 0.0
+; CHECK: @const.float = constant double 0.000000e+00
@const.null = constant ptr null
; CHECK: @const.null = constant ptr null
%const.struct.type = type { i32, i8, i64 }
@@ -56,7 +56,7 @@ $comdat.samesize = comdat samesize
@constant.array.i32 = constant [3 x i32] [i32 -0, i32 1, i32 0]
; CHECK: @constant.array.i64 = constant [3 x i64] [i64 0, i64 1, i64 0]
@constant.array.i64 = constant [3 x i64] [i64 -0, i64 1, i64 0]
-; CHECK: @constant.array.f16 = constant [3 x half] [half 0xH8000, half 0xH3C00, half 0xH0000]
+; CHECK: @constant.array.f16 = constant [3 x half] [half -0.000000e+00, half 1.000000e+00, half 0.000000e+00]
@constant.array.f16 = constant [3 x half] [half -0.0, half 1.0, half 0.0]
; CHECK: @constant.array.f32 = constant [3 x float] [float -0.000000e+00, float 1.000000e+00, float 0.000000e+00]
@constant.array.f32 = constant [3 x float] [float -0.0, float 1.0, float 0.0]
@@ -71,7 +71,7 @@ $comdat.samesize = comdat samesize
@constant.vector.i32 = constant <3 x i32> <i32 -0, i32 1, i32 0>
; CHECK: @constant.vector.i64 = constant <3 x i64> <i64 0, i64 1, i64 0>
@constant.vector.i64 = constant <3 x i64> <i64 -0, i64 1, i64 0>
-; CHECK: @constant.vector.f16 = constant <3 x half> <half 0xH8000, half 0xH3C00, half 0xH0000>
+; CHECK: @constant.vector.f16 = constant <3 x half> <half -0.000000e+00, half 1.000000e+00, half 0.000000e+00>
@constant.vector.f16 = constant <3 x half> <half -0.0, half 1.0, half 0.0>
; CHECK: @constant.vector.f32 = constant <3 x float> <float -0.000000e+00, float 1.000000e+00, float 0.000000e+00>
@constant.vector.f32 = constant <3 x float> <float -0.0, float 1.0, float 0.0>
diff --git a/llvm/test/Bitcode/constant-splat.ll b/llvm/test/Bitcode/constant-splat.ll
index 2bcc3ddf3e4f3..6bc2b7cdb99ea 100644
--- a/llvm/test/Bitcode/constant-splat.ll
+++ b/llvm/test/Bitcode/constant-splat.ll
@@ -17,7 +17,7 @@
; CHECK: @constant.splat.i128 = constant <7 x i128> splat (i128 85070591730234615870450834276742070272)
@constant.splat.i128 = constant <7 x i128> splat (i128 85070591730234615870450834276742070272)
-; CHECK: @constant.splat.f16 = constant <2 x half> splat (half 0xHBC00)
+; CHECK: @constant.splat.f16 = constant <2 x half> splat (half -1.000000e+00)
@constant.splat.f16 = constant <2 x half> splat (half 0xHBC00)
; CHECK: @constant.splat.f32 = constant <4 x float> splat (float -2.000000e+00)
@@ -26,16 +26,16 @@
; CHECK: @constant.splat.f64 = constant <6 x double> splat (double -3.000000e+00)
@constant.splat.f64 = constant <6 x double> splat (double -3.000000e+00)
-; CHECK: @constant.splat.128 = constant <8 x fp128> splat (fp128 0xL00000000000000018000000000000000)
+; CHECK: @constant.splat.128 = constant <8 x fp128> splat (fp128 -6.475180e-4966)
@constant.splat.128 = constant <8 x fp128> splat (fp128 0xL00000000000000018000000000000000)
-; CHECK: @constant.splat.bf16 = constant <1 x bfloat> splat (bfloat 0xRC0A0)
+; CHECK: @constant.splat.bf16 = constant <1 x bfloat> splat (bfloat -5.000000e+00)
@constant.splat.bf16 = constant <1 x bfloat> splat (bfloat 0xRC0A0)
-; CHECK: @constant.splat.x86_fp80 = constant <3 x x86_fp80> splat (x86_fp80 0xK4000C8F5C28F5C28F800)
+; CHECK: @constant.splat.x86_fp80 = constant <3 x x86_fp80> splat (x86_fp80 f0x4000C8F5C28F5C28F800)
@constant.splat.x86_fp80 = constant <3 x x86_fp80> splat (x86_fp80 0xK4000C8F5C28F5C28F800)
-; CHECK: @constant.splat.ppc_fp128 = constant <7 x ppc_fp128> splat (ppc_fp128 0xM80000000000000000000000000000000)
+; CHECK: @constant.splat.ppc_fp128 = constant <7 x ppc_fp128> splat (ppc_fp128 -0.000000e+00)
@constant.splat.ppc_fp128 = constant <7 x ppc_fp128> splat (ppc_fp128 0xM80000000000000000000000000000000)
define void @add_fixed_lenth_vector_splat_i32(<4 x i32> %a) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 35d8eac910861..be18264454efa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1828,7 +1828,7 @@ define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2)
; CHECK-LABEL: test_constant_vector
; CHECK: [[UNDEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
-; CHECK: [[F:%[0-9]+]]:_(f16) = G_FCONSTANT half 0xH3C00
+; CHECK: [[F:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
; CHECK: [[M:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UNDEF]](f16), [[UNDEF]](f16), [[UNDEF]](f16), [[F]](f16)
; CHECK: $d0 = COPY [[M]](<4 x f16>)
define <4 x half> @test_constant_vector() {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
index d2f73675e9439..b2a25c05b467e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
@@ -39,7 +39,7 @@ name: test_combine_half_fabs_neg_constant
body: |
bb.1:
; CHECK-LABEL: name: test_combine_half_fabs_neg_constant
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4580
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.500000e+00
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = G_FCONSTANT half 0xHC580
%1:_(s16) = G_FABS %0
@@ -50,7 +50,7 @@ name: test_combine_half_fabs_pos_constant
body: |
bb.1:
; CHECK-LABEL: name: test_combine_half_fabs_pos_constant
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4580
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.500000e+00
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = G_FCONSTANT half 0xH4580
%1:_(s16) = G_FABS %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
index dfa131fc396d7..f4cf7e5345358 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
@@ -6,7 +6,7 @@ name: test_combine_half_flog2_constant
body: |
bb.1:
; CHECK-LABEL: name: test_combine_half_flog2_constant
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = G_FCONSTANT half 4.000000e+00
%1:_(s16) = G_FLOG2 %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
index 6e675c00d846b..20dc0594fe266 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
@@ -7,7 +7,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_rhs_fminimum_half
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7C01
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half +snan(0x1)
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = COPY $h0
%1:_(s16) = G_FCONSTANT half 0xH7C01
@@ -20,7 +20,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_rhs_fminimum_float
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; CHECK-NEXT: $w0 = COPY [[C]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_FCONSTANT float 0x7FF8000000000000
@@ -33,7 +33,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_rhs_fminimum_double
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x7FF8000000000000
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double +qnan
; CHECK-NEXT: $x0 = COPY [[C]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_FCONSTANT double 0x7FF8000000000000
@@ -46,7 +46,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_lhs_fminimum_half
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7C01
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half +snan(0x1)
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = COPY $h0
%1:_(s16) = G_FCONSTANT half 0xH7C01
@@ -59,7 +59,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_lhs_fminimum_float
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; CHECK-NEXT: $w0 = COPY [[C]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_FCONSTANT float 0x7FF8000000000000
@@ -72,7 +72,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_lhs_fminimum_double
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x7FF8000000000000
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double +qnan
; CHECK-NEXT: $x0 = COPY [[C]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_FCONSTANT double 0x7FF8000000000000
@@ -85,7 +85,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_rhs_fmaximum_half
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7C01
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half +snan(0x1)
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = COPY $h0
%1:_(s16) = G_FCONSTANT half 0xH7C01
@@ -98,7 +98,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_rhs_fmaximum_float
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; CHECK-NEXT: $w0 = COPY [[C]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_FCONSTANT float 0x7FF8000000000000
@@ -111,7 +111,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_rhs_fmaximum_double
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x7FF8000000000000
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double +qnan
; CHECK-NEXT: $x0 = COPY [[C]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_FCONSTANT double 0x7FF8000000000000
@@ -124,7 +124,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_lhs_fmaximum_half
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7C01
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half +snan(0x1)
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = COPY $h0
%1:_(s16) = G_FCONSTANT half 0xH7C01
@@ -137,7 +137,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_lhs_fmaximum_float
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; CHECK-NEXT: $w0 = COPY [[C]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_FCONSTANT float 0x7FF8000000000000
@@ -150,7 +150,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_nan_lhs_fmaximum_double
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x7FF8000000000000
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double +qnan
; CHECK-NEXT: $x0 = COPY [[C]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_FCONSTANT double 0x7FF8000000000000
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
index db3ab3d451d4c..ca763fb8aabc8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
@@ -35,7 +35,7 @@ name: test_combine_half_fneg_neg_constant
body: |
bb.1:
; CHECK-LABEL: name: test_combine_half_fneg_neg_constant
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4580
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.500000e+00
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = G_FCONSTANT half 0xHC580
%1:_(s16) = G_FNEG %0
@@ -46,7 +46,7 @@ name: test_combine_half_fneg_pos_constant
body: |
bb.1:
; CHECK-LABEL: name: test_combine_half_fneg_pos_constant
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHC580
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half -5.500000e+00
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = G_FCONSTANT half 0xH4580
%1:_(s16) = G_FNEG %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
index ab4c62e313703..9a8dd7d18b7e0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
@@ -6,7 +6,7 @@ name: test_combine_float_to_half_fptrunc_constant
body: |
bb.1:
; CHECK-LABEL: name: test_combine_float_to_half_fptrunc_constant
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4580
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.500000e+00
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s32) = G_FCONSTANT float 5.500000e+00
%1:_(s16) = G_FPTRUNC %0(s32)
@@ -17,7 +17,7 @@ name: test_combine_double_to_half_fptrunc_constant
body: |
bb.1:
; CHECK-LABEL: name: test_combine_double_to_half_fptrunc_constant
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4433
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 4.199220e+00
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s64) = G_FCONSTANT double 4.200000e+00
%1:_(s16) = G_FPTRUNC %0(s64)
@@ -28,7 +28,7 @@ name: test_combine_double_to_foat_fptrunc_constant
body: |
bb.1:
; CHECK-LABEL: name: test_combine_double_to_foat_fptrunc_constant
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4010CCCCC0000000
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.200000e+00
; CHECK-NEXT: $w0 = COPY [[C]](s32)
%0:_(s64) = G_FCONSTANT double 4.200000e+00
%1:_(s32) = G_FPTRUNC %0(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
index 4fe05c616eb3c..c938ce0dd70b8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
@@ -7,7 +7,7 @@ body: |
bb.1:
liveins:
; CHECK-LABEL: name: test_combine_half_fsqrt_constant
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: $h0 = COPY [[C]](s16)
%0:_(s16) = G_FCONSTANT half 4.000000e+00
%1:_(s16) = G_FSQRT %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir b/llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir
index c05ddf98640f8..8fcf1936ba5ed 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0, debug-location !11
; CHECK-NEXT: DBG_VALUE [[COPY]](p0), $noreg, !9, !DIExpression(), debug-location !11
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FA99999A0000000, debug-location !DILocation(line: 2, column: 1, scope: !5)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-02, debug-location !DILocation(line: 2, column: 1, scope: !5)
; CHECK-NEXT: DBG_VALUE [[C]](s32), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 524, debug-location !DILocation(line: 3, column: 1, scope: !5)
; CHECK-NEXT: DBG_VALUE [[C1]](s64), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 3, column: 1, scope: !5)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
index ab9ab56e9697b..87b6741a92456 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
@@ -48,7 +48,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
; CHECK-NEXT: $x0 = COPY [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C2]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
%0:_(s32) = G_FCONSTANT float 1.0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir
index c6df3456a8445..ed73efea8ea24 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir
@@ -8,12 +8,12 @@ tracksRegLiveness: true
body: |
bb.0:
; NO-FP16-LABEL: name: fp16
- ; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH0000
+ ; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0.000000e+00
; NO-FP16-NEXT: $h0 = COPY %cst(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
; FP16-LABEL: name: fp16
- ; FP16: %cst:_(s16) = G_FCONSTANT half 0xH0000
+ ; FP16: %cst:_(s16) = G_FCONSTANT half 0.000000e+00
; FP16-NEXT: $h0 = COPY %cst(s16)
; FP16-NEXT: RET_ReallyLR implicit $h0
%cst:_(s16) = G_FCONSTANT half 0.0
@@ -26,12 +26,12 @@ tracksRegLiveness: true
body: |
bb.0:
; NO-FP16-LABEL: name: fp16_non_zero
- ; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH4000
+ ; NO-FP16: %cst:_(s16) = G_FCONSTANT half 2.000000e+00
; NO-FP16-NEXT: $h0 = COPY %cst(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
; FP16-LABEL: name: fp16_non_zero
- ; FP16: %cst:_(s16) = G_FCONSTANT half 0xH4000
+ ; FP16: %cst:_(s16) = G_FCONSTANT half 2.000000e+00
; FP16-NEXT: $h0 = COPY %cst(s16)
; FP16-NEXT: RET_ReallyLR implicit $h0
%cst:_(s16) = G_FCONSTANT half 2.0
@@ -44,13 +44,13 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; NO-FP16-LABEL: name: nan
- ; NO-FP16: %cst:_(s16) = G_FCONSTANT half 0xH7C01
+ ; NO-FP16: %cst:_(s16) = G_FCONSTANT half +snan(0x1)
; NO-FP16-NEXT: %ext:_(s32) = G_FPEXT %cst(s16)
; NO-FP16-NEXT: $w0 = COPY %ext(s32)
; NO-FP16-NEXT: RET_ReallyLR implicit $w0
;
; FP16-LABEL: name: nan
- ; FP16: %cst:_(s16) = G_FCONSTANT half 0xH7C01
+ ; FP16: %cst:_(s16) = G_FCONSTANT half +snan(0x1)
; FP16-NEXT: %ext:_(s32) = G_FPEXT %cst(s16)
; FP16-NEXT: $w0 = COPY %ext(s32)
; FP16-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
index 03e507f5eaa7f..f9ae94805842c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
@@ -10,7 +10,7 @@ body: |
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s16) = G_FMAXIMUM [[COPY]], [[C]]
; CHECK-NEXT: $h0 = COPY [[FMAXIMUM]](s16)
; CHECK-NEXT: RET_ReallyLR implicit $h0
@@ -98,7 +98,7 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<8 x s16>) = G_FMAXIMUM [[COPY]], [[BUILD_VECTOR]]
; CHECK-NEXT: $q0 = COPY [[FMAXIMUM]](<8 x s16>)
diff --git a/llvm/test/CodeGen/AArch64/convertphitype.ll b/llvm/test/CodeGen/AArch64/convertphitype.ll
index e690653237a2d..e4ece7c0f42c0 100644
--- a/llvm/test/CodeGen/AArch64/convertphitype.ll
+++ b/llvm/test/CodeGen/AArch64/convertphitype.ll
@@ -939,7 +939,7 @@ define float @convphi2_ten(ptr %s, ptr %d, i32 %n) {
; CHECK-NEXT: [[LS_BC:%.*]] = bitcast i32 [[LS]] to float
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[PHI_TC:%.*]] = phi float [ [[LS_BC]], [[THEN]] ], [ 0x36D4000000000000, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[PHI_TC:%.*]] = phi float [ [[LS_BC]], [[THEN]] ], [ 1.401300e-44, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret float [[PHI_TC]]
;
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
index 00050157e9799..a4497326480e7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
@@ -11,7 +11,7 @@ body: |
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 3.000000e+00
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; GCN-NEXT: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[COPY]], [[BUILD_VECTOR]]
; GCN-NEXT: $vgpr0 = COPY [[SUB]](<2 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
index 020761352148f..2d835a5d3ae01 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
@@ -243,14 +243,14 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: %two:_(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: %two:_(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: %two_s32:_(s32) = G_ANYEXT %two(s16)
; CHECK-NEXT: %two_splat:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %two_s32(s32), %two_s32(s32)
- ; CHECK-NEXT: %zero:_(s16) = G_FCONSTANT half 0xH0000
+ ; CHECK-NEXT: %zero:_(s16) = G_FCONSTANT half 0.000000e+00
; CHECK-NEXT: %zero_s32:_(s32) = G_ANYEXT %zero(s16)
; CHECK-NEXT: %undef:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: %zero_undef:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %zero_s32(s32), %undef(s32)
- ; CHECK-NEXT: %one:_(s16) = G_FCONSTANT half 0xH3C00
+ ; CHECK-NEXT: %one:_(s16) = G_FCONSTANT half 1.000000e+00
; CHECK-NEXT: %one_s32:_(s32) = G_ANYEXT %one(s16)
; CHECK-NEXT: %one_undef:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %one_s32(s32), %undef(s32)
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<2 x s16>) = G_FMUL [[COPY]], %two_splat
@@ -293,14 +293,14 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: %two:_(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: %two:_(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: %two_s32:_(s32) = G_ANYEXT %two(s16)
; CHECK-NEXT: %two_splat:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %two_s32(s32), %two_s32(s32)
- ; CHECK-NEXT: %snan:_(s16) = G_FCONSTANT half 0xH7C01
+ ; CHECK-NEXT: %snan:_(s16) = G_FCONSTANT half +snan(0x1)
; CHECK-NEXT: %snan_s32:_(s32) = G_ANYEXT %snan(s16)
; CHECK-NEXT: %undef:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: %snan_undef:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %snan_s32(s32), %undef(s32)
- ; CHECK-NEXT: %qnan:_(s16) = G_FCONSTANT half 0xH7E01
+ ; CHECK-NEXT: %qnan:_(s16) = G_FCONSTANT half +nan(0x1)
; CHECK-NEXT: %qnan_s32:_(s32) = G_ANYEXT %qnan(s16)
; CHECK-NEXT: %qnan_undef:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %qnan_s32(s32), %undef(s32)
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<2 x s16>) = G_FMUL [[COPY]], %two_splat
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
index 6c5339e36c77f..5afdf5b7cfb3b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
@@ -39,7 +39,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = G_FSQRT %x
- ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 0xH3C00
+ ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 1.000000e+00
; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
@@ -66,7 +66,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = contract G_FSQRT %x
- ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 0xH3C00
+ ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 1.000000e+00
; GCN-NEXT: %rsq:_(s16) = G_FDIV %one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
@@ -119,7 +119,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = G_FSQRT %x
- ; GCN-NEXT: %neg_one:_(s16) = G_FCONSTANT half 0xHBC00
+ ; GCN-NEXT: %neg_one:_(s16) = G_FCONSTANT half -1.000000e+00
; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %neg_one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
@@ -146,7 +146,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = contract G_FSQRT %x
- ; GCN-NEXT: %neg_one:_(s16) = G_FCONSTANT half 0xHBC00
+ ; GCN-NEXT: %neg_one:_(s16) = G_FCONSTANT half -1.000000e+00
; GCN-NEXT: %rsq:_(s16) = G_FDIV %neg_one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
@@ -173,7 +173,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = contract G_FSQRT %x
- ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 0xH3C00
+ ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 1.000000e+00
; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
@@ -202,7 +202,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = G_FSQRT %x
- ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 0xH3C00
+ ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 1.000000e+00
; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
@@ -231,7 +231,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = contract G_FSQRT %x
- ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 0xH3C00
+ ; GCN-NEXT: %one:_(s16) = G_FCONSTANT half 1.000000e+00
; GCN-NEXT: %rsq:_(s16) = G_FDIV %one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
@@ -486,7 +486,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
- ; GCN-NEXT: %fract:_(s16) = G_FCONSTANT half 0xH3800
+ ; GCN-NEXT: %fract:_(s16) = G_FCONSTANT half 5.000000e-01
; GCN-NEXT: [[INT:%[0-9]+]]:_(s16) = contract G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %x(s16)
; GCN-NEXT: %rsq:_(s16) = contract G_FMUL [[INT]], %fract
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
@@ -513,7 +513,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
- ; GCN-NEXT: %neg_fract:_(s16) = G_FCONSTANT half 0xHB800
+ ; GCN-NEXT: %neg_fract:_(s16) = G_FCONSTANT half -5.000000e-01
; GCN-NEXT: [[INT:%[0-9]+]]:_(s16) = contract G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %x(s16)
; GCN-NEXT: %rsq:_(s16) = contract G_FMUL [[INT]], %neg_fract
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
@@ -541,7 +541,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
- ; GCN-NEXT: %ten:_(s16) = G_FCONSTANT half 0xH4900
+ ; GCN-NEXT: %ten:_(s16) = G_FCONSTANT half 1.000000e+01
; GCN-NEXT: [[INT:%[0-9]+]]:_(s16) = contract G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %x(s16)
; GCN-NEXT: %rsq:_(s16) = contract G_FMUL [[INT]], %ten
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
@@ -568,7 +568,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: %x:_(s16) = G_TRUNC [[COPY]](s32)
- ; GCN-NEXT: %neg_ten:_(s16) = G_FCONSTANT half 0xHC900
+ ; GCN-NEXT: %neg_ten:_(s16) = G_FCONSTANT half -1.000000e+01
; GCN-NEXT: [[INT:%[0-9]+]]:_(s16) = contract G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %x(s16)
; GCN-NEXT: %rsq:_(s16) = contract G_FMUL [[INT]], %neg_ten
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
index 99170d3276cc2..54379273b27f4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
@@ -709,7 +709,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s16) = G_FMINNUM [[TRUNC]], [[C]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FMINNUM]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FNEG]](s16)
@@ -732,7 +732,7 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]]
; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
@@ -752,7 +752,7 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C882
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C882
; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s64) = G_FMINNUM [[COPY]], [[C]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[FMINNUM]]
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
index 7bd51b87fbea4..c7fd9b846bc64 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
@@ -37,7 +37,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: %input:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: %cst:_(s16) = G_FCONSTANT half 0xH0000
+ ; CHECK-NEXT: %cst:_(s16) = G_FCONSTANT half 0.000000e+00
; CHECK-NEXT: %sub:_(s16) = G_FSUB %cst, %input
; CHECK-NEXT: %res:_(s32) = G_ANYEXT %sub(s16)
; CHECK-NEXT: $vgpr0 = COPY %res(s32)
@@ -225,7 +225,7 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %input:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: %cst:_(s16) = G_FCONSTANT half 0xH0000
+ ; CHECK-NEXT: %cst:_(s16) = G_FCONSTANT half 0.000000e+00
; CHECK-NEXT: %veccst:_(<4 x s16>) = G_BUILD_VECTOR %cst(s16), %cst(s16), %cst(s16), %cst(s16)
; CHECK-NEXT: %sub:_(<4 x s16>) = G_FSUB %veccst, %input
; CHECK-NEXT: $vgpr0_vgpr1 = COPY %sub(<4 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
index a0ba67f6df0a1..9180968abfab7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
@@ -122,7 +122,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = G_FSQRT [[TRUNC]]
- ; GCN-NEXT: %one:_(s16) = contract G_FCONSTANT half 0xH3C00
+ ; GCN-NEXT: %one:_(s16) = contract G_FCONSTANT half 1.000000e+00
; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
@@ -150,7 +150,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GCN-NEXT: %sqrt:_(s16) = G_FSQRT [[TRUNC]]
- ; GCN-NEXT: %one:_(s16) = contract G_FCONSTANT half 0xHBC00
+ ; GCN-NEXT: %one:_(s16) = contract G_FCONSTANT half -1.000000e+00
; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %one, %sqrt
; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
; GCN-NEXT: $vgpr0 = COPY %ext(s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
index 0213bb35cc3a2..f7a796c62412f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
@@ -13,7 +13,7 @@ define <3 x bfloat> @v3bf16(<3 x bfloat> %arg0) {
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0xR0000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0.000000e+00
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16)
; GFX9-NEXT: [[SHUF:%[0-9]+]]:_(<3 x s16>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<3 x s16>), [[BUILD_VECTOR1]], shufflemask(3, 1, 2)
; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[SHUF]](<3 x s16>)
@@ -35,7 +35,7 @@ define <4 x bfloat> @v4bf16(<4 x bfloat> %arg0) {
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0xR0000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0.000000e+00
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; GFX9-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s16>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<4 x s16>), [[BUILD_VECTOR]], shufflemask(3, 1, 2, 0)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[SHUF]](<4 x s16>)
@@ -57,7 +57,7 @@ define <5 x bfloat> @v5bf16(<5 x bfloat> %arg0) {
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[UV3]](s16), [[UV4]](s16)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0xR0000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0.000000e+00
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<5 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; GFX9-NEXT: [[SHUF:%[0-9]+]]:_(<5 x s16>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<5 x s16>), [[BUILD_VECTOR1]], shufflemask(3, 1, 2, 0, 4)
; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[SHUF]](<5 x s16>)
@@ -81,7 +81,7 @@ define <6 x bfloat> @v6bf16(<6 x bfloat> %arg0) {
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0xR0000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0.000000e+00
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; GFX9-NEXT: [[SHUF:%[0-9]+]]:_(<6 x s16>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<6 x s16>), [[BUILD_VECTOR]], shufflemask(3, 1, 2, 0, 4, 5)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[SHUF]](<6 x s16>)
@@ -105,7 +105,7 @@ define <7 x bfloat> @v7bf16(<7 x bfloat> %arg0) {
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s16>)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[UV3]](s16), [[UV4]](s16), [[UV5]](s16), [[UV6]](s16)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0xR0000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0.000000e+00
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<7 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; GFX9-NEXT: [[SHUF:%[0-9]+]]:_(<7 x s16>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<7 x s16>), [[BUILD_VECTOR1]], shufflemask(3, 1, 2, 0, 4, 5, 6)
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16), [[UV14:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[SHUF]](<7 x s16>)
@@ -131,7 +131,7 @@ define <8 x bfloat> @v8bf16(<8 x bfloat> %arg0) {
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0xR0000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT bfloat 0.000000e+00
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; GFX9-NEXT: [[SHUF:%[0-9]+]]:_(<8 x s16>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x s16>), [[BUILD_VECTOR]], shufflemask(3, 1, 2, 0, 4, 5, 6, 7)
; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[SHUF]](<8 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
index a439226fbc5fb..55b7c745b471c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
@@ -55,7 +55,7 @@ define <2 x half> @test_atomicrmw_fadd_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; CHECK-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:_(<2 x s16>) = G_ATOMICRMW_FADD [[COPY]](p3), [[BUILD_VECTOR]] :: (load store seq_cst (<2 x s16>) on %ir.addr, addrspace 3)
; CHECK-NEXT: $vgpr0 = COPY [[ATOMICRMW_FADD]](<2 x s16>)
@@ -71,7 +71,7 @@ define <2 x half> @test_atomicrmw_fsub_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)
@@ -109,7 +109,7 @@ define <2 x half> @test_atomicrmw_fmin_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)
@@ -147,7 +147,7 @@ define <2 x half> @test_atomicrmw_fmax_vector(ptr addrspace(3) %addr) {
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
index 2c1fd5800899a..6d4b1606452c2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
@@ -1611,7 +1611,7 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4400
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 4.000000e+00
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_f16
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
index 091d5fee1545d..dd29c9efe4839 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
@@ -115,7 +115,7 @@ body: |
; CHECK-NEXT: bb.3:
; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[PHI]], [[COPY1]]
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[PHI]](s32), [[COPY1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C2]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
index 93b605948165e..b54fb5cf2ad64 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
@@ -24,9 +24,9 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE0000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x7F7FFFFF
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM_IEEE [[INT]], [[C]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE0000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xFF7FFFFF
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[C1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
%0:_(s32) = COPY $vgpr0
@@ -56,9 +56,9 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE0000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x7F7FFFFF
; VI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM [[INT]], [[C]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE0000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xFF7FFFFF
; VI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
%0:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
index f75fa857448d7..9cd430178e6be 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
@@ -23,7 +23,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -84,7 +84,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
index 6906ff9f5b349..623e6edec05fd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
@@ -31,7 +31,7 @@ body: |
bb.0:
; GCN-LABEL: name: test_fconstant_s16
- ; GCN: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; GCN: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
; GCN-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
; GCN-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s16) = G_FCONSTANT half 1.0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
index 51a16b6c23a5b..50ed63de85f24 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
@@ -15,7 +15,7 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -25,7 +25,7 @@ body: |
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -35,7 +35,7 @@ body: |
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
@@ -54,7 +54,7 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
@@ -64,7 +64,7 @@ body: |
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
@@ -74,7 +74,7 @@ body: |
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s64)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
@@ -94,7 +94,7 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -107,7 +107,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
@@ -119,7 +119,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
@@ -142,7 +142,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -157,7 +157,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -172,7 +172,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
@@ -195,7 +195,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -213,7 +213,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -231,7 +231,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
@@ -256,7 +256,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
@@ -271,7 +271,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
@@ -286,7 +286,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s64)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[C]]
@@ -314,7 +314,7 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C1]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -340,7 +340,7 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
@@ -363,7 +363,7 @@ body: |
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
@@ -383,7 +383,7 @@ body: |
; SI-LABEL: name: test_fcos_v3s16
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -406,7 +406,7 @@ body: |
;
; VI-LABEL: name: test_fcos_v3s16
; VI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
@@ -424,7 +424,7 @@ body: |
;
; GFX9-LABEL: name: test_fcos_v3s16
; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
@@ -463,7 +463,7 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C1]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -510,7 +510,7 @@ body: |
; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
@@ -550,7 +550,7 @@ body: |
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
@@ -578,7 +578,7 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -588,7 +588,7 @@ body: |
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
@@ -598,7 +598,7 @@ body: |
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
index 30b716ad77311..3ace984c6e98a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
@@ -2734,7 +2734,7 @@ body: |
; SI-LABEL: name: test_fdiv_s16_constant_one_rcp
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
@@ -2808,7 +2808,7 @@ body: |
; SI-LABEL: name: test_fdiv_s16_constant_negative_one_rcp
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half -1.000000e+00
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
index 1b675a83307e8..12ca6d17d0849 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
@@ -15,11 +15,11 @@ body: |
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
; GFX6-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[C]], [[FNEG]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E54AE0BE0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[C1]], [[FMA]]
; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
@@ -27,13 +27,13 @@ body: |
; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C2]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C4]]
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[COPY1]](s32)
@@ -44,9 +44,9 @@ body: |
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4096
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[AND]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7140000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8A000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3F347652A0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x39A3B295
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C2]]
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[FMUL1]]
@@ -58,13 +58,13 @@ body: |
; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C3]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C5]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[COPY1]](s32)
@@ -72,11 +72,11 @@ body: |
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[C]], [[FNEG]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E54AE0BE0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[C1]], [[FMA]]
; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
@@ -84,13 +84,13 @@ body: |
; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C2]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C4]]
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32)
@@ -109,11 +109,11 @@ body: |
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL]]
; GFX6-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[COPY]], [[C]], [[FNEG]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E54AE0BE0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[COPY]], [[C1]], [[FMA]]
; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = nnan G_INTRINSIC_ROUNDEVEN [[FMUL]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
@@ -121,13 +121,13 @@ body: |
; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C2]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C4]]
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[COPY1]](s32)
@@ -138,9 +138,9 @@ body: |
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4096
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[COPY]], [[AND]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7140000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8A000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[AND]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3F347652A0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x39A3B295
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[FSUB]], [[C2]]
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = nnan G_FMUL [[FSUB]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL2]], [[FMUL1]]
@@ -152,13 +152,13 @@ body: |
; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C3]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C5]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[COPY1]](s32)
@@ -166,11 +166,11 @@ body: |
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL]]
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[COPY]], [[C]], [[FNEG]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E54AE0BE0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[COPY]], [[C1]], [[FMA]]
; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = nnan G_INTRINSIC_ROUNDEVEN [[FMUL]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
@@ -178,13 +178,13 @@ body: |
; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C2]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C4]]
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32)
@@ -204,11 +204,11 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
; GFX6-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C]], [[FNEG]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E54AE0BE0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C1]], [[FMA]]
; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
@@ -216,13 +216,13 @@ body: |
; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C2]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C4]]
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
@@ -250,9 +250,9 @@ body: |
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4096
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[AND]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7140000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8A000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3F347652A0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x39A3B295
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C2]]
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[FMUL1]]
@@ -264,13 +264,13 @@ body: |
; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C3]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C5]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
@@ -299,11 +299,11 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C]], [[FNEG]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E54AE0BE0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C1]], [[FMA]]
; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
@@ -311,13 +311,13 @@ body: |
; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C2]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C4]]
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
@@ -353,11 +353,11 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
; GFX6-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C]], [[FNEG]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E54AE0BE0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C1]], [[FMA]]
; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
@@ -365,13 +365,13 @@ body: |
; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C2]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C4]]
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
@@ -414,9 +414,9 @@ body: |
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4096
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[AND]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7140000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8A000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3F347652A0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x39A3B295
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C2]]
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[FMUL1]]
@@ -428,13 +428,13 @@ body: |
; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C3]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C5]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
@@ -482,11 +482,11 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C]], [[FNEG]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E54AE0BE0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C1]], [[FMA]]
; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
@@ -494,13 +494,13 @@ body: |
; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC059D1DA00000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C2]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40562E4300000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C4]]
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
@@ -552,7 +552,7 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](s32)
; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32)
@@ -564,7 +564,7 @@ body: |
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](s32)
; GFX8-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32)
@@ -576,7 +576,7 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](s32)
; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32)
@@ -600,7 +600,7 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %4(s16)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](s32)
; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32)
@@ -620,7 +620,7 @@ body: |
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX8-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %4(s16)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](s32)
; GFX8-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32)
@@ -640,7 +640,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %4(s16)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FF7154760000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](s32)
; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
index c59b42603f153..a6a008e0cfc0c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
@@ -22,7 +22,7 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[SELECT]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
@@ -38,7 +38,7 @@ body: |
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[SELECT]]
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
@@ -54,7 +54,7 @@ body: |
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[SELECT]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
@@ -82,7 +82,7 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[SELECT]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
@@ -106,7 +106,7 @@ body: |
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[SELECT]]
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
@@ -130,7 +130,7 @@ body: |
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[SELECT]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
@@ -165,7 +165,7 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[SELECT]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
@@ -195,7 +195,7 @@ body: |
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[SELECT]]
; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
@@ -225,7 +225,7 @@ body: |
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[SELECT]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
index 9999c181fb6c1..1c2431adb0fe3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
@@ -47,7 +47,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[COPY]](s64)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT]], [[C]]
; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FMINNUM_IEEE]]
@@ -85,7 +85,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[COPY]](s64)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT]], [[C]]
; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan G_FADD [[COPY]], [[FNEG]]
@@ -121,7 +121,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[COPY]](s64)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nsz G_FMINNUM_IEEE [[INT]], [[C]]
; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ord), [[COPY]](s64), [[COPY]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = nsz G_SELECT [[FCMP]](s1), [[COPY]], [[FMINNUM_IEEE]]
@@ -284,7 +284,7 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[UV]](s64)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT]], [[C]]
; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[UV]](s64), [[UV]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FMINNUM_IEEE]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
index 06fbbefd2c58e..b9241a9ca1320 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
@@ -11,26 +11,26 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E42E0000000
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E6EFA39E0000000
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317217
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3377D1CF
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40362E4300000000
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x41B17218
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
@@ -49,26 +49,26 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E42E0000000
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E6EFA39E0000000
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317217
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3377D1CF
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40362E4300000000
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x41B17218
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
@@ -88,26 +88,26 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E42E0000000
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E6EFA39E0000000
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317217
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3377D1CF
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40362E4300000000
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x41B17218
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
@@ -142,26 +142,26 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E42E0000000
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E6EFA39E0000000
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317217
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3377D1CF
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x40362E4300000000
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x41B17218
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
@@ -212,7 +212,7 @@ body: |
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317218
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C]]
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
@@ -242,7 +242,7 @@ body: |
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FE62E4300000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317218
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C1]]
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
index 28cd783473978..89b1f307462a8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
@@ -11,26 +11,26 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441340000000
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E509F79E0000000
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E9A209A
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3284FBCF
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4023441360000000
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.632960e+00
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
@@ -49,26 +49,26 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441340000000
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E509F79E0000000
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E9A209A
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3284FBCF
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4023441360000000
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.632960e+00
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
@@ -88,26 +88,26 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441340000000
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E509F79E0000000
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E9A209A
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3284FBCF
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4023441360000000
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.632960e+00
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
@@ -142,26 +142,26 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441340000000
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3E509F79E0000000
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E9A209A
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3284FBCF
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF0000000000000
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4023441360000000
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.632960e+00
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
@@ -212,7 +212,7 @@ body: |
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.010300e-01
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C]]
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
@@ -242,7 +242,7 @@ body: |
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FD3441360000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.010300e-01
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C1]]
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
index 42135d4bca4a0..b5a08a063a305 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
@@ -11,9 +11,9 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
@@ -39,9 +39,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
@@ -74,9 +74,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
index 4b214e66ea994..dd5718b1e32ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
@@ -17,7 +17,7 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[TRUNC]], [[TRUNC1]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7E00
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[SELECT]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
@@ -57,7 +57,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
@@ -90,7 +90,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s64) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x7FF8000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
@@ -133,7 +133,7 @@ body: |
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC2]]
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC1]](s16), [[TRUNC3]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7E00
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half +qnan
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[FMAXNUM_IEEE]](<2 x s16>)
; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
@@ -174,7 +174,7 @@ body: |
; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY2]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY2]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY1]], [[COPY3]]
@@ -222,7 +222,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMAXNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
index ed6e554948611..da03c0c78a776 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
@@ -996,7 +996,7 @@ body: |
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -1021,7 +1021,7 @@ body: |
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -1044,7 +1044,7 @@ body: |
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY]]
; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[BUILD_VECTOR]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
index 8ba0794be3069..bf9685621454c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
@@ -17,7 +17,7 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[TRUNC]], [[TRUNC1]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7E00
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[SELECT]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
@@ -57,7 +57,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
@@ -90,7 +90,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x7FF8000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
@@ -133,7 +133,7 @@ body: |
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC2]]
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[TRUNC1]](s16), [[TRUNC3]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH7E00
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half +qnan
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[FMINNUM_IEEE]](<2 x s16>)
; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
@@ -174,7 +174,7 @@ body: |
; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY2]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY2]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY1]], [[COPY3]]
@@ -222,7 +222,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x7FF8000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMINNUM_IEEE]], [[C]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
index f511df1976d0e..1e25b6dec47a1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
@@ -996,7 +996,7 @@ body: |
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -1021,7 +1021,7 @@ body: |
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -1044,7 +1044,7 @@ body: |
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY]]
; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[BUILD_VECTOR]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
index affa9c330cab2..b6e5e0ac8330d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
@@ -15,9 +15,9 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
@@ -33,7 +33,7 @@ body: |
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INT1]], [[SELECT2]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
; GFX6-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
@@ -42,9 +42,9 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[SELECT]]
@@ -60,7 +60,7 @@ body: |
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INT1]], [[SELECT2]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
; GFX9-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
@@ -83,9 +83,9 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
@@ -101,7 +101,7 @@ body: |
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INT1]], [[SELECT2]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
@@ -126,9 +126,9 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
@@ -144,7 +144,7 @@ body: |
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INT1]], [[SELECT2]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
@@ -181,9 +181,9 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; GFX6-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
@@ -199,7 +199,7 @@ body: |
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INT1]], [[SELECT2]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
@@ -237,9 +237,9 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; GFX9-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[SELECT]]
@@ -255,7 +255,7 @@ body: |
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INT1]], [[SELECT2]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
@@ -303,9 +303,9 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[COPY]], [[SELECT]]
@@ -321,7 +321,7 @@ body: |
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan nsz G_FADD [[INT1]], [[SELECT2]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[INT2]], [[SELECT3]]
; GFX6-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
@@ -330,9 +330,9 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[COPY]], [[SELECT]]
@@ -348,7 +348,7 @@ body: |
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan nsz G_FADD [[INT1]], [[SELECT2]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[INT2]], [[SELECT3]]
; GFX9-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
@@ -382,7 +382,7 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INT1]], [[SELECT]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT1]]
@@ -444,7 +444,7 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INT1]], [[SELECT]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[C5]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT1]]
@@ -531,7 +531,7 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan nsz G_FADD [[INT1]], [[SELECT]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = nnan nsz G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan nsz G_SELECT [[FCMP]](s1), [[C4]], [[C5]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan nsz G_FMUL [[INT2]], [[SELECT1]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
index 3e7f4e8843f4f..3b0b2cf363d9e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
@@ -27,7 +27,7 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[INT1]], [[SELECT]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[INT2]], [[SELECT1]]
@@ -69,9 +69,9 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
@@ -87,7 +87,7 @@ body: |
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[INT1]], [[SELECT2]]
; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[INT2]], [[SELECT3]]
; GFX6-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
@@ -97,9 +97,9 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY1]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3810000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x00800000
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[SELECT]]
@@ -115,7 +115,7 @@ body: |
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[INT1]], [[SELECT2]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3BF0000000000000
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[INT2]], [[SELECT3]]
; GFX9-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
index 3094d19471611..653d38cd389eb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
@@ -213,11 +213,11 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
- ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[SELECT1]], [[C8]]
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[FMUL]](s64), [[FMUL]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
@@ -233,8 +233,8 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -277,11 +277,11 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
- ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[SELECT1]], [[C8]]
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]]
; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan G_FADD [[FMUL]], [[FNEG]]
@@ -295,8 +295,8 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = nnan G_INTRINSIC_TRUNC [[COPY]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -340,11 +340,11 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
- ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[SELECT1]], [[C8]]
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[FMUL]](s64), [[FMUL]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
@@ -385,8 +385,8 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -421,8 +421,8 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
; SI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C2]], [[FABS]]
@@ -444,8 +444,8 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
; VI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C2]], [[FABS]]
@@ -479,8 +479,8 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV]], [[C]](s32)
; SI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C2]], [[FABS]]
@@ -519,8 +519,8 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV]], [[C]](s32)
; VI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C2]], [[FABS]]
@@ -722,8 +722,8 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
; SI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C2]], [[FABS]]
@@ -745,8 +745,8 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
; VI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C2]], [[FABS]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
index 2eab791f2ba12..f57148cb0aff3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
@@ -213,11 +213,11 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
- ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[SELECT1]], [[C8]]
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[FMUL]](s64), [[FMUL]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
@@ -233,8 +233,8 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -277,11 +277,11 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
- ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[SELECT1]], [[C8]]
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]]
; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan G_FADD [[FMUL]], [[FNEG]]
@@ -295,8 +295,8 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = nnan G_INTRINSIC_TRUNC [[COPY]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -340,11 +340,11 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
- ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; SI-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; SI-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[SELECT1]], [[C8]]
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
+ ; SI-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FEFFFFFFFFFFFFF
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[FMUL]](s64), [[FMUL]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
@@ -385,8 +385,8 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3DF0000000000000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0xC1F0000000000000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -418,8 +418,8 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -432,8 +432,8 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -458,8 +458,8 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -481,8 +481,8 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -667,8 +667,8 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
@@ -681,8 +681,8 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
index 4dfc9edeeed9b..840061ef6b48c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
@@ -533,7 +533,7 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; SI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
; SI-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -574,7 +574,7 @@ body: |
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; VI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
; VI-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -615,7 +615,7 @@ body: |
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
index 243ad1f4e642d..7fa148e1cf566 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
@@ -492,7 +492,7 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; SI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
; SI-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -532,7 +532,7 @@ body: |
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; VI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
; VI-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -572,7 +572,7 @@ body: |
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
index 9e5f6b6002035..c8e2fcd67c79b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
@@ -15,7 +15,7 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -25,7 +25,7 @@ body: |
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -35,7 +35,7 @@ body: |
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
@@ -54,7 +54,7 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
@@ -64,7 +64,7 @@ body: |
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
@@ -74,7 +74,7 @@ body: |
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s64)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
@@ -94,7 +94,7 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -107,7 +107,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s16)
@@ -119,7 +119,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
@@ -142,7 +142,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -157,7 +157,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -172,7 +172,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
@@ -195,7 +195,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -213,7 +213,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -231,7 +231,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
@@ -256,7 +256,7 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
@@ -271,7 +271,7 @@ body: |
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
@@ -286,7 +286,7 @@ body: |
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s64)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[C]]
@@ -314,7 +314,7 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C1]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -340,7 +340,7 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s16)
@@ -363,7 +363,7 @@ body: |
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s16)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
@@ -383,7 +383,7 @@ body: |
; SI-LABEL: name: test_fsin_v3s16
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -406,7 +406,7 @@ body: |
;
; VI-LABEL: name: test_fsin_v3s16
; VI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s16)
@@ -424,7 +424,7 @@ body: |
;
; GFX9-LABEL: name: test_fsin_v3s16
; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s16)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
@@ -463,7 +463,7 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C1]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -510,7 +510,7 @@ body: |
; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s16)
@@ -550,7 +550,7 @@ body: |
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s16)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
@@ -578,7 +578,7 @@ body: |
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -588,7 +588,7 @@ body: |
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
@@ -598,7 +598,7 @@ body: |
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
index f0df589660467..fe051245a502c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
@@ -15,9 +15,9 @@ body: |
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x39F0000000000000
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x0F800000
; GCN-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[C]](s32), [[COPY]]
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GCN-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMUL]], [[COPY]]
; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[SELECT]](s32)
@@ -34,7 +34,7 @@ body: |
; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[ADD]], [[INT]]
; GCN-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FMA1]](s32), [[C4]]
; GCN-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[ADD1]], [[SELECT1]]
- ; GCN-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3EF0000000000000
+ ; GCN-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x37800000
; GCN-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[SELECT2]], [[C5]]
; GCN-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMUL1]], [[SELECT2]]
; GCN-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[SELECT]](s32), 608
@@ -55,7 +55,7 @@ body: |
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x1000000000000000
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x1000000000000000
; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GCN-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s64), [[C]]
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
@@ -97,7 +97,7 @@ body: |
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x1000000000000000
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x1000000000000000
; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GCN-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s64), [[C]]
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
@@ -181,9 +181,9 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x39F0000000000000
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x0F800000
; GCN-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[C]](s32), [[UV]]
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GCN-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMUL]], [[UV]]
; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[SELECT]](s32)
@@ -200,7 +200,7 @@ body: |
; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[ADD]], [[INT]]
; GCN-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FMA1]](s32), [[C4]]
; GCN-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[ADD1]], [[SELECT1]]
- ; GCN-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3EF0000000000000
+ ; GCN-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x37800000
; GCN-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[SELECT2]], [[C5]]
; GCN-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMUL1]], [[SELECT2]]
; GCN-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[SELECT]](s32), 608
@@ -241,9 +241,9 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x39F0000000000000
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x0F800000
; GCN-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[C]](s32), [[UV]]
- ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GCN-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMUL]], [[UV]]
; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[SELECT]](s32)
@@ -260,7 +260,7 @@ body: |
; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[ADD]], [[INT]]
; GCN-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FMA1]](s32), [[C4]]
; GCN-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[ADD1]], [[SELECT1]]
- ; GCN-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3EF0000000000000
+ ; GCN-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x37800000
; GCN-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[SELECT2]], [[C5]]
; GCN-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[FMUL1]], [[SELECT2]]
; GCN-NEXT: [[IS_FPCLASS:%[0-9]+]]:_(s1) = G_IS_FPCLASS [[SELECT]](s32), 608
@@ -319,7 +319,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GCN-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x1000000000000000
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x1000000000000000
; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GCN-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s64), [[C]]
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
index 98336560ad5e6..4c889e1f5212b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
@@ -13,8 +13,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY1]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x45F0000000000000
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x6F800000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
@@ -41,8 +41,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[COPY1]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x45F0000000000000
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x6F800000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
index 4ebf8838ec4a7..20264d2cd701a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
@@ -499,12 +499,12 @@ body: |
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -526,10 +526,10 @@ body: |
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -548,10 +548,10 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -592,12 +592,12 @@ body: |
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -647,10 +647,10 @@ body: |
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -686,10 +686,10 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -739,12 +739,12 @@ body: |
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -825,10 +825,10 @@ body: |
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -884,10 +884,10 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -956,12 +956,12 @@ body: |
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -1062,10 +1062,10 @@ body: |
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
@@ -1130,10 +1130,10 @@ body: |
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C2]], [[C3]]
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
index 19fb0c7bbab85..800473bb2b9e4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
@@ -23,7 +23,7 @@ body: |
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -61,7 +61,7 @@ body: |
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -210,7 +210,7 @@ body: |
; GFX-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; GFX-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
; GFX-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
index b10acd0155ca2..e269111f04205 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
@@ -25,7 +25,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -63,7 +63,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -101,7 +101,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -139,7 +139,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -191,7 +191,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -260,7 +260,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -329,7 +329,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -398,7 +398,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -486,16 +486,16 @@ body: |
; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -658,16 +658,16 @@ body: |
; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -830,16 +830,16 @@ body: |
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1002,16 +1002,16 @@ body: |
; GFX10-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1188,16 +1188,16 @@ body: |
; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV12]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV13]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1521,16 +1521,16 @@ body: |
; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV12]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV13]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1854,16 +1854,16 @@ body: |
; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV12]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV13]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -2187,16 +2187,16 @@ body: |
; GFX10-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV12]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV13]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -2523,7 +2523,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2563,7 +2563,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2603,7 +2603,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2643,7 +2643,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2703,7 +2703,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2784,7 +2784,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2865,7 +2865,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2943,7 +2943,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3028,7 +3028,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3068,7 +3068,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3108,7 +3108,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3148,7 +3148,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3203,7 +3203,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3243,7 +3243,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3283,7 +3283,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3323,7 +3323,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3387,16 +3387,16 @@ body: |
; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3561,16 +3561,16 @@ body: |
; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3735,16 +3735,16 @@ body: |
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3909,16 +3909,16 @@ body: |
; GFX10-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
index 4cbdea64f1c00..238b7f6c09f1b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
@@ -367,8 +367,8 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half -1.000000e+00
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -377,8 +377,8 @@ body: |
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half -1.000000e+00
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
index b77758dfa6bfd..5db43a1f7e1ec 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
@@ -25,7 +25,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -59,7 +59,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -93,7 +93,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -127,7 +127,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -175,7 +175,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -237,7 +237,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -299,7 +299,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -361,7 +361,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -442,16 +442,16 @@ body: |
; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -609,16 +609,16 @@ body: |
; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -776,16 +776,16 @@ body: |
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -943,16 +943,16 @@ body: |
; GFX10-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1124,16 +1124,16 @@ body: |
; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV12]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV13]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1448,16 +1448,16 @@ body: |
; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV12]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV13]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1772,16 +1772,16 @@ body: |
; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV12]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV13]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -2096,16 +2096,16 @@ body: |
; GFX10-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV12]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV13]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -2423,7 +2423,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2461,7 +2461,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2499,7 +2499,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2537,7 +2537,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2595,7 +2595,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2669,7 +2669,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2743,7 +2743,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2814,7 +2814,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2892,7 +2892,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2928,7 +2928,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2964,7 +2964,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3000,7 +3000,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3051,7 +3051,7 @@ body: |
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3087,7 +3087,7 @@ body: |
; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3123,7 +3123,7 @@ body: |
; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3159,7 +3159,7 @@ body: |
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[ASHR1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -3219,16 +3219,16 @@ body: |
; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3388,16 +3388,16 @@ body: |
; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3557,16 +3557,16 @@ body: |
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3726,16 +3726,16 @@ body: |
; GFX10-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV8]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV9]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
index 9fd42c2586605..8cc4dafebe96c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
@@ -18,7 +18,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -47,7 +47,7 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -76,7 +76,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -105,7 +105,7 @@ body: |
; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -147,7 +147,7 @@ body: |
; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV2]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -198,7 +198,7 @@ body: |
; GFX8-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV2]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -249,7 +249,7 @@ body: |
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV2]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -300,7 +300,7 @@ body: |
; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV2]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -361,16 +361,16 @@ body: |
; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -512,16 +512,16 @@ body: |
; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -663,16 +663,16 @@ body: |
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -814,16 +814,16 @@ body: |
; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -978,16 +978,16 @@ body: |
; GFX6-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV4]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV5]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1269,16 +1269,16 @@ body: |
; GFX8-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV4]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV5]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1560,16 +1560,16 @@ body: |
; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV4]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV5]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1851,16 +1851,16 @@ body: |
; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV4]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV5]](s32)
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -2153,7 +2153,7 @@ body: |
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2186,7 +2186,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2219,7 +2219,7 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2252,7 +2252,7 @@ body: |
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2304,7 +2304,7 @@ body: |
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2365,7 +2365,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2426,7 +2426,7 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2485,7 +2485,7 @@ body: |
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2550,7 +2550,7 @@ body: |
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2582,7 +2582,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2614,7 +2614,7 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2646,7 +2646,7 @@ body: |
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2692,7 +2692,7 @@ body: |
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2724,7 +2724,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2756,7 +2756,7 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2788,7 +2788,7 @@ body: |
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2835,16 +2835,16 @@ body: |
; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -2989,16 +2989,16 @@ body: |
; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3143,16 +3143,16 @@ body: |
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3297,16 +3297,16 @@ body: |
; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
index 65826d7658f2c..e75495f53e410 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
@@ -339,8 +339,8 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -349,8 +349,8 @@ body: |
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
index d585c76650c4e..d4a4c7d335066 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
@@ -18,7 +18,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -44,7 +44,7 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -70,7 +70,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -96,7 +96,7 @@ body: |
; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -135,7 +135,7 @@ body: |
; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV2]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -181,7 +181,7 @@ body: |
; GFX8-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV2]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -227,7 +227,7 @@ body: |
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV2]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -273,7 +273,7 @@ body: |
; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV2]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -329,16 +329,16 @@ body: |
; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -476,16 +476,16 @@ body: |
; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -623,16 +623,16 @@ body: |
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -770,16 +770,16 @@ body: |
; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -930,16 +930,16 @@ body: |
; GFX6-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV4]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV5]](s32)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1214,16 +1214,16 @@ body: |
; GFX8-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV4]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV5]](s32)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1498,16 +1498,16 @@ body: |
; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV4]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV5]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -1782,16 +1782,16 @@ body: |
; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV4]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV5]](s32)
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C2]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C3]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -2077,7 +2077,7 @@ body: |
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2107,7 +2107,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2137,7 +2137,7 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2167,7 +2167,7 @@ body: |
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2216,7 +2216,7 @@ body: |
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2272,7 +2272,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2328,7 +2328,7 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2382,7 +2382,7 @@ body: |
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2442,7 +2442,7 @@ body: |
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2471,7 +2471,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2500,7 +2500,7 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2529,7 +2529,7 @@ body: |
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2572,7 +2572,7 @@ body: |
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2601,7 +2601,7 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2630,7 +2630,7 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2659,7 +2659,7 @@ body: |
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F7FFFFE
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -2703,16 +2703,16 @@ body: |
; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -2853,16 +2853,16 @@ body: |
; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3003,16 +3003,16 @@ body: |
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
@@ -3153,16 +3153,16 @@ body: |
; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
+ ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F800000
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP1]], [[C1]]
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UITOFP]]
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FADD]](s32)
- ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x43EFFFFF80000000
+ ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x5F7FFFFC
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
- ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF0000000000000
+ ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x2F800000
; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL1]], [[C3]]
; GFX10-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FMUL2]]
- ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC1F0000000000000
+ ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xCF800000
; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INTRINSIC_TRUNC]], [[C4]]
; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMUL1]]
; GFX10-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FADD1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
index a97d905f2a978..8463e45e7c7d5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
@@ -63,7 +63,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]
; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]
@@ -75,7 +75,7 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]
; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
index c3eed50092056..012e5e8f32916 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
@@ -89,7 +89,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]
; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s16) = G_FCANONICALIZE [[FMUL]]
@@ -129,7 +129,7 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
@@ -172,7 +172,7 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
@@ -286,7 +286,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]
; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]
@@ -324,7 +324,7 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
index a53e97af0d028..6a91f158d0664 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
@@ -82,10 +82,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s16) = G_FCANONICALIZE [[TRUNC]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 4.000000e+00
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)
; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = G_AMDGPU_FMED3 [[FCANONICALIZE]], [[COPY1]], [[COPY2]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)
@@ -121,9 +121,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 4.000000e+00
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)
; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY1]], [[COPY2]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)
@@ -221,9 +221,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 4.000000e+00
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)
; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY2]], [[COPY1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)
@@ -257,9 +257,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 4.000000e+00
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16)
; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY2]], [[COPY1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16)
@@ -426,10 +426,10 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 2.000000e+00
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 4.000000e+00
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C1]](s16)
; CHECK-NEXT: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT1]](s32), [[ANYEXT1]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
index 0a2a2e60cf5a0..cf7d82a2ced6f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
@@ -27,7 +27,7 @@ legalized: true
body: |
bb.0:
; CHECK-LABEL: name: test_fconstant_f16_1
- ; CHECK: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH3C00
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 1.000000e+00
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
%0:_(s16) = G_FCONSTANT half 1.0
%1:_(s32) = G_ANYEXT %0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
index fa1ba6ceff58b..2a30bc13fa9b9 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
@@ -469,7 +469,7 @@ define double @rsq_f64_input_known_not_zero(double nofpclass(zero) %x) {
; CHECK-LABEL: define double @rsq_f64_input_known_not_zero(
; CHECK-SAME: double nofpclass(zero) [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp contract oeq double [[X]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp contract oeq double [[X]], +inf
; CHECK-NEXT: [[TMP3:%.*]] = select contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul contract double [[TMP3]], [[TMP4]]
@@ -580,7 +580,7 @@ define double @rsq_f64_dynamic_denormal(double %x) #0 {
; CHECK-SAME: double [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[X]])
; CHECK-NEXT: [[TMP2:%.*]] = fcmp contract oeq double [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp contract oeq double [[X]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP3:%.*]] = fcmp contract oeq double [[X]], +inf
; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = select contract i1 [[TMP4]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP6:%.*]] = fneg contract double [[TMP1]]
@@ -619,7 +619,7 @@ define double @rsq_f64_dynamic_denormal_no_zero_no_denorm(double nofpclass(zero
; CHECK-LABEL: define double @rsq_f64_dynamic_denormal_no_zero_no_denorm(
; CHECK-SAME: double nofpclass(zero sub) [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp contract oeq double [[X]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp contract oeq double [[X]], +inf
; CHECK-NEXT: [[TMP3:%.*]] = select contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul contract double [[TMP3]], [[TMP4]]
@@ -750,7 +750,7 @@ define double @rsq_f64_assume_nonzero(double %x) {
; CHECK-NEXT: [[NONZERO:%.*]] = fcmp one double [[X]], 0.000000e+00
; CHECK-NEXT: call void @llvm.assume(i1 [[NONZERO]])
; CHECK-NEXT: [[TMP1:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp contract oeq double [[X]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp contract oeq double [[X]], +inf
; CHECK-NEXT: [[TMP3:%.*]] = select contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul contract double [[TMP3]], [[TMP4]]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
index cc0d279fe4ec8..ddeb4c2bdf778 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
@@ -880,7 +880,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub(ptr addrspace(1) %out, floa
; IEEE-GOODFREXP-LABEL: define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub(
; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
; IEEE-GOODFREXP-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IEEE-GOODFREXP-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], f0x00800000
; IEEE-GOODFREXP-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[X]])
; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0
@@ -894,7 +894,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub(ptr addrspace(1) %out, floa
; IEEE-BADFREXP-LABEL: define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub(
; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
; IEEE-BADFREXP-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IEEE-BADFREXP-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], f0x00800000
; IEEE-BADFREXP-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[X]])
; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0
@@ -908,7 +908,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub(ptr addrspace(1) %out, floa
; DAZ-LABEL: define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub(
; DAZ-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
; DAZ-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; DAZ-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
+; DAZ-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], f0x00800000
; DAZ-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
; DAZ-NEXT: [[MD_1ULP_NO_SUB:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[X]])
; DAZ-NEXT: store volatile float [[MD_1ULP_NO_SUB]], ptr addrspace(1) [[OUT]], align 4
@@ -927,7 +927,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub_assume_result_nosub(ptr add
; IEEE-GOODFREXP-LABEL: define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub_assume_result_nosub(
; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
; IEEE-GOODFREXP-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IEEE-GOODFREXP-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], f0x00800000
; IEEE-GOODFREXP-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[X]])
; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0
@@ -936,7 +936,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub_assume_result_nosub(ptr add
; IEEE-GOODFREXP-NEXT: [[TMP5:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP2]])
; IEEE-GOODFREXP-NEXT: [[MD_1ULP_NO_SUB:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP5]], i32 [[TMP4]])
; IEEE-GOODFREXP-NEXT: [[FABS_RESULT:%.*]] = call float @llvm.fabs.f32(float [[MD_1ULP_NO_SUB]])
-; IEEE-GOODFREXP-NEXT: [[RESULT_IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_RESULT]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[RESULT_IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_RESULT]], f0x00800000
; IEEE-GOODFREXP-NEXT: call void @llvm.assume(i1 [[RESULT_IS_NOT_SUBNORMAL]])
; IEEE-GOODFREXP-NEXT: store volatile float [[MD_1ULP_NO_SUB]], ptr addrspace(1) [[OUT]], align 4
; IEEE-GOODFREXP-NEXT: ret void
@@ -944,7 +944,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub_assume_result_nosub(ptr add
; IEEE-BADFREXP-LABEL: define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub_assume_result_nosub(
; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
; IEEE-BADFREXP-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IEEE-BADFREXP-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], f0x00800000
; IEEE-BADFREXP-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[X]])
; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0
@@ -953,7 +953,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub_assume_result_nosub(ptr add
; IEEE-BADFREXP-NEXT: [[TMP5:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP2]])
; IEEE-BADFREXP-NEXT: [[MD_1ULP_NO_SUB:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP5]], i32 [[TMP4]])
; IEEE-BADFREXP-NEXT: [[FABS_RESULT:%.*]] = call float @llvm.fabs.f32(float [[MD_1ULP_NO_SUB]])
-; IEEE-BADFREXP-NEXT: [[RESULT_IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_RESULT]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[RESULT_IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_RESULT]], f0x00800000
; IEEE-BADFREXP-NEXT: call void @llvm.assume(i1 [[RESULT_IS_NOT_SUBNORMAL]])
; IEEE-BADFREXP-NEXT: store volatile float [[MD_1ULP_NO_SUB]], ptr addrspace(1) [[OUT]], align 4
; IEEE-BADFREXP-NEXT: ret void
@@ -961,11 +961,11 @@ define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub_assume_result_nosub(ptr add
; DAZ-LABEL: define amdgpu_kernel void @rcp_fdiv_f32_assume_nosub_assume_result_nosub(
; DAZ-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
; DAZ-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; DAZ-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
+; DAZ-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], f0x00800000
; DAZ-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
; DAZ-NEXT: [[MD_1ULP_NO_SUB:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[X]])
; DAZ-NEXT: [[FABS_RESULT:%.*]] = call float @llvm.fabs.f32(float [[MD_1ULP_NO_SUB]])
-; DAZ-NEXT: [[RESULT_IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_RESULT]], 0x3810000000000000
+; DAZ-NEXT: [[RESULT_IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_RESULT]], f0x00800000
; DAZ-NEXT: call void @llvm.assume(i1 [[RESULT_IS_NOT_SUBNORMAL]])
; DAZ-NEXT: store volatile float [[MD_1ULP_NO_SUB]], ptr addrspace(1) [[OUT]], align 4
; DAZ-NEXT: ret void
@@ -1513,8 +1513,8 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
; IEEE-GOODFREXP-NEXT: [[SQRT_X_NO_MD:%.*]] = call contract float @llvm.sqrt.f32(float [[X]])
; IEEE-GOODFREXP-NEXT: [[NO_MD:%.*]] = fdiv contract float 1.000000e+00, [[SQRT_X_NO_MD]]
; IEEE-GOODFREXP-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = fmul contract float [[X]], [[TMP2]]
; IEEE-GOODFREXP-NEXT: [[TMP4:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
; IEEE-GOODFREXP-NEXT: [[TMP5:%.*]] = select contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
@@ -1529,8 +1529,8 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP7]])
; IEEE-GOODFREXP-NEXT: [[MD_1ULP_MULTI_USE:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP10]], i32 [[TMP9]])
; IEEE-GOODFREXP-NEXT: store volatile float [[MD_1ULP_MULTI_USE]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP13:%.*]] = fmul contract float [[X]], [[TMP12]]
; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP13]])
; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = select contract i1 [[TMP11]], float 4.096000e+03, float 1.000000e+00
@@ -1549,22 +1549,22 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
; IEEE-GOODFREXP-NEXT: store volatile float [[FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 4
; IEEE-GOODFREXP-NEXT: [[FAST_25ULP:%.*]] = call fast float @llvm.amdgcn.rsq.f32(float [[X]])
; IEEE-GOODFREXP-NEXT: store volatile float [[FAST_25ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = select contract i1 [[TMP16]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = select contract i1 [[TMP16]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = fmul contract float [[X]], [[TMP17]]
; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP18]])
; IEEE-GOODFREXP-NEXT: [[TMP20:%.*]] = select contract i1 [[TMP16]], float 4.096000e+03, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[FDIV_OPENCL:%.*]] = fmul contract float [[TMP19]], [[TMP20]]
; IEEE-GOODFREXP-NEXT: store volatile float [[FDIV_OPENCL]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-GOODFREXP-NEXT: [[TMP21:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP22:%.*]] = select contract i1 [[TMP21]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP21:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP22:%.*]] = select contract i1 [[TMP21]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP23:%.*]] = fmul contract float [[X]], [[TMP22]]
; IEEE-GOODFREXP-NEXT: [[TMP24:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP23]])
; IEEE-GOODFREXP-NEXT: [[TMP25:%.*]] = select contract i1 [[TMP21]], float -4.096000e+03, float -1.000000e+00
; IEEE-GOODFREXP-NEXT: [[NEG_FDIV_OPENCL:%.*]] = fmul contract float [[TMP24]], [[TMP25]]
; IEEE-GOODFREXP-NEXT: store volatile float [[NEG_FDIV_OPENCL]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-GOODFREXP-NEXT: [[TMP26:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP27:%.*]] = select contract i1 [[TMP26]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP26:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP27:%.*]] = select contract i1 [[TMP26]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP28:%.*]] = fmul contract float [[X]], [[TMP27]]
; IEEE-GOODFREXP-NEXT: [[TMP29:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP28]])
; IEEE-GOODFREXP-NEXT: [[TMP30:%.*]] = select contract i1 [[TMP26]], float 4.096000e+03, float 1.000000e+00
@@ -1578,7 +1578,7 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
; IEEE-GOODFREXP-NEXT: [[TMP35:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP32]])
; IEEE-GOODFREXP-NEXT: [[FDIV_SQRT_MISMATCH_MD1:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP35]], i32 [[TMP34]])
; IEEE-GOODFREXP-NEXT: store volatile float [[FDIV_SQRT_MISMATCH_MD1]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-GOODFREXP-NEXT: [[TMP36:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[TMP36:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-GOODFREXP-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 32, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP38:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP37]])
; IEEE-GOODFREXP-NEXT: [[TMP39:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP38]])
@@ -1593,8 +1593,8 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
; IEEE-BADFREXP-NEXT: [[SQRT_X_NO_MD:%.*]] = call contract float @llvm.sqrt.f32(float [[X]])
; IEEE-BADFREXP-NEXT: [[NO_MD:%.*]] = fdiv contract float 1.000000e+00, [[SQRT_X_NO_MD]]
; IEEE-BADFREXP-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = fmul contract float [[X]], [[TMP2]]
; IEEE-BADFREXP-NEXT: [[TMP4:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
; IEEE-BADFREXP-NEXT: [[TMP5:%.*]] = select contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
@@ -1609,8 +1609,8 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP7]])
; IEEE-BADFREXP-NEXT: [[MD_1ULP_MULTI_USE:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP10]], i32 [[TMP9]])
; IEEE-BADFREXP-NEXT: store volatile float [[MD_1ULP_MULTI_USE]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP13:%.*]] = fmul contract float [[X]], [[TMP12]]
; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP13]])
; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = select contract i1 [[TMP11]], float 4.096000e+03, float 1.000000e+00
@@ -1629,22 +1629,22 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
; IEEE-BADFREXP-NEXT: store volatile float [[FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 4
; IEEE-BADFREXP-NEXT: [[FAST_25ULP:%.*]] = call fast float @llvm.amdgcn.rsq.f32(float [[X]])
; IEEE-BADFREXP-NEXT: store volatile float [[FAST_25ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = select contract i1 [[TMP16]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = select contract i1 [[TMP16]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = fmul contract float [[X]], [[TMP17]]
; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP18]])
; IEEE-BADFREXP-NEXT: [[TMP20:%.*]] = select contract i1 [[TMP16]], float 4.096000e+03, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[FDIV_OPENCL:%.*]] = fmul contract float [[TMP19]], [[TMP20]]
; IEEE-BADFREXP-NEXT: store volatile float [[FDIV_OPENCL]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-BADFREXP-NEXT: [[TMP21:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP22:%.*]] = select contract i1 [[TMP21]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP21:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP22:%.*]] = select contract i1 [[TMP21]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP23:%.*]] = fmul contract float [[X]], [[TMP22]]
; IEEE-BADFREXP-NEXT: [[TMP24:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP23]])
; IEEE-BADFREXP-NEXT: [[TMP25:%.*]] = select contract i1 [[TMP21]], float -4.096000e+03, float -1.000000e+00
; IEEE-BADFREXP-NEXT: [[NEG_FDIV_OPENCL:%.*]] = fmul contract float [[TMP24]], [[TMP25]]
; IEEE-BADFREXP-NEXT: store volatile float [[NEG_FDIV_OPENCL]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-BADFREXP-NEXT: [[TMP26:%.*]] = fcmp contract olt float [[X]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP27:%.*]] = select contract i1 [[TMP26]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP26:%.*]] = fcmp contract olt float [[X]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP27:%.*]] = select contract i1 [[TMP26]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP28:%.*]] = fmul contract float [[X]], [[TMP27]]
; IEEE-BADFREXP-NEXT: [[TMP29:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP28]])
; IEEE-BADFREXP-NEXT: [[TMP30:%.*]] = select contract i1 [[TMP26]], float 4.096000e+03, float 1.000000e+00
@@ -1658,7 +1658,7 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
; IEEE-BADFREXP-NEXT: [[TMP35:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP32]])
; IEEE-BADFREXP-NEXT: [[FDIV_SQRT_MISMATCH_MD1:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP35]], i32 [[TMP34]])
; IEEE-BADFREXP-NEXT: store volatile float [[FDIV_SQRT_MISMATCH_MD1]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-BADFREXP-NEXT: [[TMP36:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[TMP36:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-BADFREXP-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 32, i32 0
; IEEE-BADFREXP-NEXT: [[TMP38:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP37]])
; IEEE-BADFREXP-NEXT: [[TMP39:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP38]])
@@ -1780,43 +1780,43 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) {
define amdgpu_kernel void @rsq_f32_fpmath_flags(ptr addrspace(1) %out, float %x) {
; IEEE-LABEL: define amdgpu_kernel void @rsq_f32_fpmath_flags(
; IEEE-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp nnan ninf contract olt float [[X]], 0x3810000000000000
-; IEEE-NEXT: [[TMP2:%.*]] = select nnan ninf contract i1 [[TMP1]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp nnan ninf contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP2:%.*]] = select nnan ninf contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP3:%.*]] = fmul nnan ninf contract float [[X]], [[TMP2]]
; IEEE-NEXT: [[TMP4:%.*]] = call nnan ninf contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select nnan ninf contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NINF_NNAN:%.*]] = fmul nnan ninf contract float [[TMP4]], [[TMP5]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NINF_NNAN]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP6:%.*]] = fcmp ninf contract olt float [[X]], 0x3810000000000000
-; IEEE-NEXT: [[TMP7:%.*]] = select ninf contract i1 [[TMP6]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP6:%.*]] = fcmp ninf contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP7:%.*]] = select ninf contract i1 [[TMP6]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP8:%.*]] = fmul ninf contract float [[X]], [[TMP7]]
; IEEE-NEXT: [[TMP9:%.*]] = call ninf contract float @llvm.amdgcn.rsq.f32(float [[TMP8]])
; IEEE-NEXT: [[TMP10:%.*]] = select ninf contract i1 [[TMP6]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NINF:%.*]] = fmul ninf contract float [[TMP9]], [[TMP10]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NINF]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP11:%.*]] = fcmp nnan contract olt float [[X]], 0x3810000000000000
-; IEEE-NEXT: [[TMP12:%.*]] = select nnan contract i1 [[TMP11]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP11:%.*]] = fcmp nnan contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP12:%.*]] = select nnan contract i1 [[TMP11]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP13:%.*]] = fmul nnan contract float [[X]], [[TMP12]]
; IEEE-NEXT: [[TMP14:%.*]] = call nnan contract float @llvm.amdgcn.rsq.f32(float [[TMP13]])
; IEEE-NEXT: [[TMP15:%.*]] = select nnan contract i1 [[TMP11]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NNAN:%.*]] = fmul nnan contract float [[TMP14]], [[TMP15]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NNAN]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP16:%.*]] = fcmp nsz contract olt float [[X]], 0x3810000000000000
-; IEEE-NEXT: [[TMP17:%.*]] = select nsz contract i1 [[TMP16]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP16:%.*]] = fcmp nsz contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP17:%.*]] = select nsz contract i1 [[TMP16]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP18:%.*]] = fmul nsz contract float [[X]], [[TMP17]]
; IEEE-NEXT: [[TMP19:%.*]] = call nsz contract float @llvm.amdgcn.rsq.f32(float [[TMP18]])
; IEEE-NEXT: [[TMP20:%.*]] = select nsz contract i1 [[TMP16]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NSZ:%.*]] = fmul nsz contract float [[TMP19]], [[TMP20]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NSZ]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP21:%.*]] = fcmp nnan ninf contract olt float [[X]], 0x3810000000000000
-; IEEE-NEXT: [[TMP22:%.*]] = select nnan ninf contract i1 [[TMP21]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP21:%.*]] = fcmp nnan ninf contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP22:%.*]] = select nnan ninf contract i1 [[TMP21]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP23:%.*]] = fmul nnan ninf contract float [[X]], [[TMP22]]
; IEEE-NEXT: [[TMP24:%.*]] = call nnan ninf contract float @llvm.amdgcn.rsq.f32(float [[TMP23]])
; IEEE-NEXT: [[TMP25:%.*]] = select nnan ninf contract i1 [[TMP21]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NNAN_MIX0:%.*]] = fmul nnan ninf contract float [[TMP24]], [[TMP25]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NNAN_MIX0]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP26:%.*]] = fcmp nnan ninf contract olt float [[X]], 0x3810000000000000
-; IEEE-NEXT: [[TMP27:%.*]] = select nnan ninf contract i1 [[TMP26]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP26:%.*]] = fcmp nnan ninf contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP27:%.*]] = select nnan ninf contract i1 [[TMP26]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP28:%.*]] = fmul nnan ninf contract float [[X]], [[TMP27]]
; IEEE-NEXT: [[TMP29:%.*]] = call nnan ninf contract float @llvm.amdgcn.rsq.f32(float [[TMP28]])
; IEEE-NEXT: [[TMP30:%.*]] = select nnan ninf contract i1 [[TMP26]], float 4.096000e+03, float 1.000000e+00
@@ -1938,8 +1938,8 @@ define float @rsq_f32_missing_contract1(float %x) {
define float @rsq_f32_flag_merge(float %x) {
; IEEE-LABEL: define float @rsq_f32_flag_merge(
; IEEE-SAME: float [[X:%.*]]) #[[ATTR1]] {
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp ninf nsz contract olt float [[X]], 0x3810000000000000
-; IEEE-NEXT: [[TMP2:%.*]] = select ninf nsz contract i1 [[TMP1]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp ninf nsz contract olt float [[X]], f0x00800000
+; IEEE-NEXT: [[TMP2:%.*]] = select ninf nsz contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP3:%.*]] = fmul ninf nsz contract float [[X]], [[TMP2]]
; IEEE-NEXT: [[TMP4:%.*]] = call ninf nsz contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select ninf nsz contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
@@ -1959,22 +1959,22 @@ define float @rsq_f32_flag_merge(float %x) {
define amdgpu_kernel void @rsq_f32_knownfinite(ptr addrspace(1) %out, float nofpclass(nan) %no.nan,
; IEEE-LABEL: define amdgpu_kernel void @rsq_f32_knownfinite(
; IEEE-SAME: ptr addrspace(1) [[OUT:%.*]], float nofpclass(nan) [[NO_NAN:%.*]], float nofpclass(nan) [[NO_INF:%.*]], float nofpclass(nan inf) [[NO_INF_NAN:%.*]]) #[[ATTR1]] {
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[NO_NAN]], 0x3810000000000000
-; IEEE-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[NO_NAN]], f0x00800000
+; IEEE-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP3:%.*]] = fmul contract float [[NO_NAN]], [[TMP2]]
; IEEE-NEXT: [[TMP4:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NO_NAN:%.*]] = fmul contract float [[TMP4]], [[TMP5]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NO_NAN]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP6:%.*]] = fcmp contract olt float [[NO_INF]], 0x3810000000000000
-; IEEE-NEXT: [[TMP7:%.*]] = select contract i1 [[TMP6]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP6:%.*]] = fcmp contract olt float [[NO_INF]], f0x00800000
+; IEEE-NEXT: [[TMP7:%.*]] = select contract i1 [[TMP6]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP8:%.*]] = fmul contract float [[NO_INF]], [[TMP7]]
; IEEE-NEXT: [[TMP9:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP8]])
; IEEE-NEXT: [[TMP10:%.*]] = select contract i1 [[TMP6]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NO_INF:%.*]] = fmul contract float [[TMP9]], [[TMP10]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NO_INF]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[NO_INF_NAN]], 0x3810000000000000
-; IEEE-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[NO_INF_NAN]], f0x00800000
+; IEEE-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP13:%.*]] = fmul contract float [[NO_INF_NAN]], [[TMP12]]
; IEEE-NEXT: [[TMP14:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP13]])
; IEEE-NEXT: [[TMP15:%.*]] = select contract i1 [[TMP11]], float 4.096000e+03, float 1.000000e+00
@@ -2012,8 +2012,8 @@ define amdgpu_kernel void @rsq_f32_knownfinite(ptr addrspace(1) %out, float nofp
define amdgpu_kernel void @rsq_f32_known_nozero(ptr addrspace(1) %out, float nofpclass(zero) %no.zero, float nofpclass(zero sub) %no.zero.sub) {
; IEEE-LABEL: define amdgpu_kernel void @rsq_f32_known_nozero(
; IEEE-SAME: ptr addrspace(1) [[OUT:%.*]], float nofpclass(zero) [[NO_ZERO:%.*]], float nofpclass(zero sub) [[NO_ZERO_SUB:%.*]]) #[[ATTR1]] {
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[NO_ZERO]], 0x3810000000000000
-; IEEE-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[NO_ZERO]], f0x00800000
+; IEEE-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP3:%.*]] = fmul contract float [[NO_ZERO]], [[TMP2]]
; IEEE-NEXT: [[TMP4:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
@@ -2047,15 +2047,15 @@ define amdgpu_kernel void @rsq_f32_known_nosub(ptr addrspace(1) %out, float nofp
; IEEE-SAME: ptr addrspace(1) [[OUT:%.*]], float nofpclass(sub) [[NO_SUB:%.*]], float nofpclass(psub) [[NO_PSUB:%.*]], float nofpclass(nsub) [[NO_NSUB:%.*]]) #[[ATTR1]] {
; IEEE-NEXT: [[FDIV_OPENCL_NO_SUB:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[NO_SUB]])
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NO_SUB]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[NO_PSUB]], 0x3810000000000000
-; IEEE-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp contract olt float [[NO_PSUB]], f0x00800000
+; IEEE-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP3:%.*]] = fmul contract float [[NO_PSUB]], [[TMP2]]
; IEEE-NEXT: [[TMP4:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00
; IEEE-NEXT: [[FDIV_OPENCL_NO_PSUB:%.*]] = fmul contract float [[TMP4]], [[TMP5]]
; IEEE-NEXT: store volatile float [[FDIV_OPENCL_NO_PSUB]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP6:%.*]] = fcmp contract olt float [[NO_NSUB]], 0x3810000000000000
-; IEEE-NEXT: [[TMP7:%.*]] = select contract i1 [[TMP6]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-NEXT: [[TMP6:%.*]] = fcmp contract olt float [[NO_NSUB]], f0x00800000
+; IEEE-NEXT: [[TMP7:%.*]] = select contract i1 [[TMP6]], float f0x4B800000, float 1.000000e+00
; IEEE-NEXT: [[TMP8:%.*]] = fmul contract float [[NO_NSUB]], [[TMP7]]
; IEEE-NEXT: [[TMP9:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP8]])
; IEEE-NEXT: [[TMP10:%.*]] = select contract i1 [[TMP6]], float 4.096000e+03, float 1.000000e+00
@@ -2092,7 +2092,7 @@ define amdgpu_kernel void @rsq_f32_assume_nosub(ptr addrspace(1) %out, float %x)
; CHECK-LABEL: define amdgpu_kernel void @rsq_f32_assume_nosub(
; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
+; CHECK-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
; CHECK-NEXT: [[FDIV_OPENCL_NO_SUB:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[X]])
; CHECK-NEXT: store volatile float [[FDIV_OPENCL_NO_SUB]], ptr addrspace(1) [[OUT]], align 4
@@ -2118,14 +2118,14 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo
; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP]], i64 1
; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-GOODFREXP-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-GOODFREXP-NEXT: [[TMP5:%.*]] = fcmp contract olt float [[TMP3]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP5:%.*]] = fcmp contract olt float [[TMP3]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP7:%.*]] = fmul contract float [[TMP3]], [[TMP6]]
; IEEE-GOODFREXP-NEXT: [[TMP8:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP7]])
; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = select contract i1 [[TMP5]], float 4.096000e+03, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = fmul contract float [[TMP8]], [[TMP9]]
-; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[TMP4]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[TMP4]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP13:%.*]] = fmul contract float [[TMP4]], [[TMP12]]
; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP13]])
; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = select contract i1 [[TMP11]], float 4.096000e+03, float 1.000000e+00
@@ -2138,8 +2138,8 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo
; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP_UNDEF]], i64 1
; IEEE-GOODFREXP-NEXT: [[TMP20:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-GOODFREXP-NEXT: [[TMP21:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-GOODFREXP-NEXT: [[TMP22:%.*]] = fcmp contract olt float [[TMP20]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP23:%.*]] = select contract i1 [[TMP22]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP22:%.*]] = fcmp contract olt float [[TMP20]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP23:%.*]] = select contract i1 [[TMP22]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP24:%.*]] = fmul contract float [[TMP20]], [[TMP23]]
; IEEE-GOODFREXP-NEXT: [[TMP25:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP24]])
; IEEE-GOODFREXP-NEXT: [[TMP26:%.*]] = select contract i1 [[TMP22]], float 4.096000e+03, float 1.000000e+00
@@ -2159,13 +2159,13 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo
; IEEE-GOODFREXP-NEXT: store volatile <2 x float> [[MD_1ULP_UNDEF]], ptr addrspace(1) [[OUT]], align 4
; IEEE-GOODFREXP-NEXT: [[TMP56:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-GOODFREXP-NEXT: [[TMP57:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-GOODFREXP-NEXT: [[TMP58:%.*]] = fcmp olt float [[TMP56]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[TMP58:%.*]] = fcmp olt float [[TMP56]], f0x00800000
; IEEE-GOODFREXP-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i32 32, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP60:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP56]], i32 [[TMP59]])
; IEEE-GOODFREXP-NEXT: [[TMP61:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP60]])
; IEEE-GOODFREXP-NEXT: [[TMP62:%.*]] = select i1 [[TMP58]], i32 -16, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP63:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP61]], i32 [[TMP62]])
-; IEEE-GOODFREXP-NEXT: [[TMP64:%.*]] = fcmp olt float [[TMP57]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[TMP64:%.*]] = fcmp olt float [[TMP57]], f0x00800000
; IEEE-GOODFREXP-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i32 32, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP66:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP57]], i32 [[TMP65]])
; IEEE-GOODFREXP-NEXT: [[TMP67:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP66]])
@@ -2177,14 +2177,14 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo
; IEEE-GOODFREXP-NEXT: [[TMP40:%.*]] = extractelement <2 x float> [[SQRT_X_3ULP]], i64 1
; IEEE-GOODFREXP-NEXT: [[TMP41:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-GOODFREXP-NEXT: [[TMP42:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-GOODFREXP-NEXT: [[TMP43:%.*]] = fcmp contract olt float [[TMP41]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP44:%.*]] = select contract i1 [[TMP43]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP43:%.*]] = fcmp contract olt float [[TMP41]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP44:%.*]] = select contract i1 [[TMP43]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP45:%.*]] = fmul contract float [[TMP41]], [[TMP44]]
; IEEE-GOODFREXP-NEXT: [[TMP46:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP45]])
; IEEE-GOODFREXP-NEXT: [[TMP47:%.*]] = select contract i1 [[TMP43]], float 4.096000e+03, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP48:%.*]] = fmul contract float [[TMP46]], [[TMP47]]
-; IEEE-GOODFREXP-NEXT: [[TMP49:%.*]] = fcmp contract olt float [[TMP42]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP50:%.*]] = select contract i1 [[TMP49]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP49:%.*]] = fcmp contract olt float [[TMP42]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP50:%.*]] = select contract i1 [[TMP49]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP51:%.*]] = fmul contract float [[TMP42]], [[TMP50]]
; IEEE-GOODFREXP-NEXT: [[TMP52:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP51]])
; IEEE-GOODFREXP-NEXT: [[TMP53:%.*]] = select contract i1 [[TMP49]], float 4.096000e+03, float 1.000000e+00
@@ -2204,14 +2204,14 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo
; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP]], i64 1
; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-BADFREXP-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-BADFREXP-NEXT: [[TMP5:%.*]] = fcmp contract olt float [[TMP3]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP5:%.*]] = fcmp contract olt float [[TMP3]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP6:%.*]] = select contract i1 [[TMP5]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP7:%.*]] = fmul contract float [[TMP3]], [[TMP6]]
; IEEE-BADFREXP-NEXT: [[TMP8:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP7]])
; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = select contract i1 [[TMP5]], float 4.096000e+03, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = fmul contract float [[TMP8]], [[TMP9]]
-; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[TMP4]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fcmp contract olt float [[TMP4]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = select contract i1 [[TMP11]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP13:%.*]] = fmul contract float [[TMP4]], [[TMP12]]
; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP13]])
; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = select contract i1 [[TMP11]], float 4.096000e+03, float 1.000000e+00
@@ -2224,8 +2224,8 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo
; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP_UNDEF]], i64 1
; IEEE-BADFREXP-NEXT: [[TMP20:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-BADFREXP-NEXT: [[TMP21:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-BADFREXP-NEXT: [[TMP22:%.*]] = fcmp contract olt float [[TMP20]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP23:%.*]] = select contract i1 [[TMP22]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP22:%.*]] = fcmp contract olt float [[TMP20]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP23:%.*]] = select contract i1 [[TMP22]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP24:%.*]] = fmul contract float [[TMP20]], [[TMP23]]
; IEEE-BADFREXP-NEXT: [[TMP25:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP24]])
; IEEE-BADFREXP-NEXT: [[TMP26:%.*]] = select contract i1 [[TMP22]], float 4.096000e+03, float 1.000000e+00
@@ -2245,13 +2245,13 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo
; IEEE-BADFREXP-NEXT: store volatile <2 x float> [[MD_1ULP_UNDEF]], ptr addrspace(1) [[OUT]], align 4
; IEEE-BADFREXP-NEXT: [[TMP56:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-BADFREXP-NEXT: [[TMP57:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-BADFREXP-NEXT: [[TMP58:%.*]] = fcmp olt float [[TMP56]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[TMP58:%.*]] = fcmp olt float [[TMP56]], f0x00800000
; IEEE-BADFREXP-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i32 32, i32 0
; IEEE-BADFREXP-NEXT: [[TMP60:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP56]], i32 [[TMP59]])
; IEEE-BADFREXP-NEXT: [[TMP61:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP60]])
; IEEE-BADFREXP-NEXT: [[TMP62:%.*]] = select i1 [[TMP58]], i32 -16, i32 0
; IEEE-BADFREXP-NEXT: [[TMP63:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP61]], i32 [[TMP62]])
-; IEEE-BADFREXP-NEXT: [[TMP64:%.*]] = fcmp olt float [[TMP57]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[TMP64:%.*]] = fcmp olt float [[TMP57]], f0x00800000
; IEEE-BADFREXP-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i32 32, i32 0
; IEEE-BADFREXP-NEXT: [[TMP66:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP57]], i32 [[TMP65]])
; IEEE-BADFREXP-NEXT: [[TMP67:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP66]])
@@ -2263,14 +2263,14 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo
; IEEE-BADFREXP-NEXT: [[TMP40:%.*]] = extractelement <2 x float> [[SQRT_X_3ULP]], i64 1
; IEEE-BADFREXP-NEXT: [[TMP41:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-BADFREXP-NEXT: [[TMP42:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-BADFREXP-NEXT: [[TMP43:%.*]] = fcmp contract olt float [[TMP41]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP44:%.*]] = select contract i1 [[TMP43]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP43:%.*]] = fcmp contract olt float [[TMP41]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP44:%.*]] = select contract i1 [[TMP43]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP45:%.*]] = fmul contract float [[TMP41]], [[TMP44]]
; IEEE-BADFREXP-NEXT: [[TMP46:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP45]])
; IEEE-BADFREXP-NEXT: [[TMP47:%.*]] = select contract i1 [[TMP43]], float 4.096000e+03, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP48:%.*]] = fmul contract float [[TMP46]], [[TMP47]]
-; IEEE-BADFREXP-NEXT: [[TMP49:%.*]] = fcmp contract olt float [[TMP42]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP50:%.*]] = select contract i1 [[TMP49]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP49:%.*]] = fcmp contract olt float [[TMP42]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP50:%.*]] = select contract i1 [[TMP49]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP51:%.*]] = fmul contract float [[TMP42]], [[TMP50]]
; IEEE-BADFREXP-NEXT: [[TMP52:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP51]])
; IEEE-BADFREXP-NEXT: [[TMP53:%.*]] = select contract i1 [[TMP49]], float 4.096000e+03, float 1.000000e+00
@@ -2795,7 +2795,7 @@ define amdgpu_kernel void @multiple_arcp_fdiv_denom_1ulp_vector(ptr addrspace(1)
define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp(ptr addrspace(1) %out, float %x, float %y, float %sqr.denom) {
; IEEE-GOODFREXP-LABEL: define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp(
; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]], float [[Y:%.*]], float [[SQR_DENOM:%.*]]) #[[ATTR1]] {
-; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = fcmp olt float [[SQR_DENOM]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = fcmp olt float [[SQR_DENOM]], f0x00800000
; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[SQR_DENOM]], i32 [[TMP2]])
; IEEE-GOODFREXP-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
@@ -2821,7 +2821,7 @@ define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp(ptr addrspace(1)
;
; IEEE-BADFREXP-LABEL: define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp(
; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]], float [[Y:%.*]], float [[SQR_DENOM:%.*]]) #[[ATTR1]] {
-; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = fcmp olt float [[SQR_DENOM]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = fcmp olt float [[SQR_DENOM]], f0x00800000
; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[SQR_DENOM]], i32 [[TMP2]])
; IEEE-BADFREXP-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
@@ -2869,13 +2869,13 @@ define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_vector_25ulp(ptr addrsp
; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], <2 x float> [[X:%.*]], <2 x float> [[Y:%.*]], <2 x float> [[SQR_DENOM:%.*]]) #[[ATTR1]] {
; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[SQR_DENOM]], i64 0
; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[SQR_DENOM]], i64 1
-; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = fcmp olt float [[TMP1]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = fcmp olt float [[TMP1]], f0x00800000
; IEEE-GOODFREXP-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 32, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP5:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP1]], i32 [[TMP4]])
; IEEE-GOODFREXP-NEXT: [[TMP6:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP5]])
; IEEE-GOODFREXP-NEXT: [[TMP7:%.*]] = select i1 [[TMP3]], i32 -16, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP6]], i32 [[TMP7]])
-; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp olt float [[TMP2]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp olt float [[TMP2]], f0x00800000
; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 32, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP2]], i32 [[TMP10]])
; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP11]])
@@ -2931,13 +2931,13 @@ define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_vector_25ulp(ptr addrsp
; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], <2 x float> [[X:%.*]], <2 x float> [[Y:%.*]], <2 x float> [[SQR_DENOM:%.*]]) #[[ATTR1]] {
; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[SQR_DENOM]], i64 0
; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[SQR_DENOM]], i64 1
-; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = fcmp olt float [[TMP1]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = fcmp olt float [[TMP1]], f0x00800000
; IEEE-BADFREXP-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 32, i32 0
; IEEE-BADFREXP-NEXT: [[TMP5:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP1]], i32 [[TMP4]])
; IEEE-BADFREXP-NEXT: [[TMP6:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP5]])
; IEEE-BADFREXP-NEXT: [[TMP7:%.*]] = select i1 [[TMP3]], i32 -16, i32 0
; IEEE-BADFREXP-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP6]], i32 [[TMP7]])
-; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp olt float [[TMP2]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp olt float [[TMP2]], f0x00800000
; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 32, i32 0
; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP2]], i32 [[TMP10]])
; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP11]])
@@ -3032,7 +3032,7 @@ define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_vector_25ulp(ptr addrsp
define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp_x3(ptr addrspace(1) %out, float %x, float %y, float %z, float %sqr.denom) {
; IEEE-GOODFREXP-LABEL: define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp_x3(
; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]], float [[Y:%.*]], float [[Z:%.*]], float [[SQR_DENOM:%.*]]) #[[ATTR1]] {
-; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = fcmp olt float [[SQR_DENOM]], 0x3810000000000000
+; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = fcmp olt float [[SQR_DENOM]], f0x00800000
; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[SQR_DENOM]], i32 [[TMP2]])
; IEEE-GOODFREXP-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
@@ -3066,7 +3066,7 @@ define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp_x3(ptr addrspace(
;
; IEEE-BADFREXP-LABEL: define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp_x3(
; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]], float [[Y:%.*]], float [[Z:%.*]], float [[SQR_DENOM:%.*]]) #[[ATTR1]] {
-; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = fcmp olt float [[SQR_DENOM]], 0x3810000000000000
+; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = fcmp olt float [[SQR_DENOM]], f0x00800000
; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[SQR_DENOM]], i32 [[TMP2]])
; IEEE-BADFREXP-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
@@ -3134,14 +3134,14 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator(<4 x float> %arg) {
; IEEE-GOODFREXP-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[ARG]], i64 1
; IEEE-GOODFREXP-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[ARG]], i64 2
; IEEE-GOODFREXP-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[ARG]], i64 3
-; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp contract olt float [[TMP5]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = select contract i1 [[TMP9]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp contract olt float [[TMP5]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = select contract i1 [[TMP9]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fmul contract float [[TMP5]], [[TMP10]]
; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP11]])
; IEEE-GOODFREXP-NEXT: [[TMP13:%.*]] = select contract i1 [[TMP9]], float 4.096000e+03, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = fmul contract float [[TMP12]], [[TMP13]]
-; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = fcmp contract olt float [[TMP6]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = fcmp contract olt float [[TMP6]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = fmul contract float [[TMP6]], [[TMP16]]
; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP17]])
; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = select contract i1 [[TMP15]], float -4.096000e+03, float -1.000000e+00
@@ -3183,14 +3183,14 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator(<4 x float> %arg) {
; IEEE-BADFREXP-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[ARG]], i64 1
; IEEE-BADFREXP-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[ARG]], i64 2
; IEEE-BADFREXP-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[ARG]], i64 3
-; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp contract olt float [[TMP5]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = select contract i1 [[TMP9]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp contract olt float [[TMP5]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = select contract i1 [[TMP9]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fmul contract float [[TMP5]], [[TMP10]]
; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP11]])
; IEEE-BADFREXP-NEXT: [[TMP13:%.*]] = select contract i1 [[TMP9]], float 4.096000e+03, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = fmul contract float [[TMP12]], [[TMP13]]
-; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = fcmp contract olt float [[TMP6]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = fcmp contract olt float [[TMP6]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = fmul contract float [[TMP6]], [[TMP16]]
; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP17]])
; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = select contract i1 [[TMP15]], float -4.096000e+03, float -1.000000e+00
@@ -3289,14 +3289,14 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_afn_sqrt(<4 x float>
; IEEE-GOODFREXP-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[ARG]], i64 1
; IEEE-GOODFREXP-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[ARG]], i64 2
; IEEE-GOODFREXP-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[ARG]], i64 3
-; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp contract afn olt float [[TMP5]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = select contract afn i1 [[TMP9]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp contract afn olt float [[TMP5]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = select contract afn i1 [[TMP9]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fmul contract afn float [[TMP5]], [[TMP10]]
; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = call contract afn float @llvm.amdgcn.rsq.f32(float [[TMP11]])
; IEEE-GOODFREXP-NEXT: [[TMP13:%.*]] = select contract afn i1 [[TMP9]], float 4.096000e+03, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = fmul contract afn float [[TMP12]], [[TMP13]]
-; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = fcmp contract afn olt float [[TMP6]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = select contract afn i1 [[TMP15]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = fcmp contract afn olt float [[TMP6]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = select contract afn i1 [[TMP15]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = fmul contract afn float [[TMP6]], [[TMP16]]
; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = call contract afn float @llvm.amdgcn.rsq.f32(float [[TMP17]])
; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = select contract afn i1 [[TMP15]], float -4.096000e+03, float -1.000000e+00
@@ -3338,14 +3338,14 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_afn_sqrt(<4 x float>
; IEEE-BADFREXP-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[ARG]], i64 1
; IEEE-BADFREXP-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[ARG]], i64 2
; IEEE-BADFREXP-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[ARG]], i64 3
-; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp contract afn olt float [[TMP5]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = select contract afn i1 [[TMP9]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp contract afn olt float [[TMP5]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = select contract afn i1 [[TMP9]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fmul contract afn float [[TMP5]], [[TMP10]]
; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = call contract afn float @llvm.amdgcn.rsq.f32(float [[TMP11]])
; IEEE-BADFREXP-NEXT: [[TMP13:%.*]] = select contract afn i1 [[TMP9]], float 4.096000e+03, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = fmul contract afn float [[TMP12]], [[TMP13]]
-; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = fcmp contract afn olt float [[TMP6]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = select contract afn i1 [[TMP15]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = fcmp contract afn olt float [[TMP6]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = select contract afn i1 [[TMP15]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = fmul contract afn float [[TMP6]], [[TMP16]]
; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = call contract afn float @llvm.amdgcn.rsq.f32(float [[TMP17]])
; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = select contract afn i1 [[TMP15]], float -4.096000e+03, float -1.000000e+00
@@ -3491,14 +3491,14 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_correct_sqrt(<4 x fl
; IEEE-GOODFREXP-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[ARG]], i64 1
; IEEE-GOODFREXP-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[ARG]], i64 2
; IEEE-GOODFREXP-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[ARG]], i64 3
-; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp contract olt float [[TMP5]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = select contract i1 [[TMP9]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp contract olt float [[TMP5]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = select contract i1 [[TMP9]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fmul contract float [[TMP5]], [[TMP14]]
; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP11]])
; IEEE-GOODFREXP-NEXT: [[TMP13:%.*]] = select contract i1 [[TMP9]], float 4.096000e+03, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = fmul contract float [[TMP12]], [[TMP13]]
-; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = fcmp contract olt float [[TMP6]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = fcmp contract olt float [[TMP6]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP41:%.*]] = fmul contract float [[TMP6]], [[TMP16]]
; IEEE-GOODFREXP-NEXT: [[TMP42:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP41]])
; IEEE-GOODFREXP-NEXT: [[TMP43:%.*]] = select contract i1 [[TMP15]], float -4.096000e+03, float -1.000000e+00
@@ -3540,14 +3540,14 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_correct_sqrt(<4 x fl
; IEEE-BADFREXP-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[ARG]], i64 1
; IEEE-BADFREXP-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[ARG]], i64 2
; IEEE-BADFREXP-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[ARG]], i64 3
-; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp contract olt float [[TMP5]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = select contract i1 [[TMP9]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp contract olt float [[TMP5]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = select contract i1 [[TMP9]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fmul contract float [[TMP5]], [[TMP14]]
; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP11]])
; IEEE-BADFREXP-NEXT: [[TMP13:%.*]] = select contract i1 [[TMP9]], float 4.096000e+03, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = fmul contract float [[TMP12]], [[TMP13]]
-; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = fcmp contract olt float [[TMP6]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = fcmp contract olt float [[TMP6]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP41:%.*]] = fmul contract float [[TMP6]], [[TMP16]]
; IEEE-BADFREXP-NEXT: [[TMP42:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[TMP41]])
; IEEE-BADFREXP-NEXT: [[TMP43:%.*]] = select contract i1 [[TMP15]], float -4.096000e+03, float -1.000000e+00
@@ -3635,14 +3635,14 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp(<4 x float> %ar
; IEEE-GOODFREXP-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[ARG]], i64 1
; IEEE-GOODFREXP-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[ARG]], i64 2
; IEEE-GOODFREXP-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[ARG]], i64 3
-; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp arcp contract olt float [[TMP5]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = select arcp contract i1 [[TMP9]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP9:%.*]] = fcmp arcp contract olt float [[TMP5]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = select arcp contract i1 [[TMP9]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fmul arcp contract float [[TMP5]], [[TMP10]]
; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = call arcp contract float @llvm.amdgcn.rsq.f32(float [[TMP11]])
; IEEE-GOODFREXP-NEXT: [[TMP13:%.*]] = select arcp contract i1 [[TMP9]], float 4.096000e+03, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP14:%.*]] = fmul arcp contract float [[TMP12]], [[TMP13]]
-; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = fcmp arcp contract olt float [[TMP6]], 0x3810000000000000
-; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = select arcp contract i1 [[TMP15]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = fcmp arcp contract olt float [[TMP6]], f0x00800000
+; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = select arcp contract i1 [[TMP15]], float f0x4B800000, float 1.000000e+00
; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = fmul arcp contract float [[TMP6]], [[TMP16]]
; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = call arcp contract float @llvm.amdgcn.rsq.f32(float [[TMP17]])
; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = select arcp contract i1 [[TMP15]], float -4.096000e+03, float -1.000000e+00
@@ -3678,14 +3678,14 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp(<4 x float> %ar
; IEEE-BADFREXP-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[ARG]], i64 1
; IEEE-BADFREXP-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[ARG]], i64 2
; IEEE-BADFREXP-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[ARG]], i64 3
-; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp arcp contract olt float [[TMP5]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = select arcp contract i1 [[TMP9]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP9:%.*]] = fcmp arcp contract olt float [[TMP5]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = select arcp contract i1 [[TMP9]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fmul arcp contract float [[TMP5]], [[TMP10]]
; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = call arcp contract float @llvm.amdgcn.rsq.f32(float [[TMP11]])
; IEEE-BADFREXP-NEXT: [[TMP13:%.*]] = select arcp contract i1 [[TMP9]], float 4.096000e+03, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP14:%.*]] = fmul arcp contract float [[TMP12]], [[TMP13]]
-; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = fcmp arcp contract olt float [[TMP6]], 0x3810000000000000
-; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = select arcp contract i1 [[TMP15]], float 0x4170000000000000, float 1.000000e+00
+; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = fcmp arcp contract olt float [[TMP6]], f0x00800000
+; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = select arcp contract i1 [[TMP15]], float f0x4B800000, float 1.000000e+00
; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = fmul arcp contract float [[TMP6]], [[TMP16]]
; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = call arcp contract float @llvm.amdgcn.rsq.f32(float [[TMP17]])
; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = select arcp contract i1 [[TMP15]], float -4.096000e+03, float -1.000000e+00
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
index e34aaf205cb95..62059cd989ba2 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
@@ -93,7 +93,7 @@ define i32 @select_sdiv_lhs_opaque_const0_i32(i1 %cond) {
; IR-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]
; IR-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
; IR-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]])
-; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41EFFFFFC0000000
+; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], f0x4F7FFFFE
; IR-NEXT: [[TMP8:%.*]] = fptoui float [[TMP7]] to i32
; IR-NEXT: [[TMP9:%.*]] = sub i32 0, [[TMP4]]
; IR-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP8]]
@@ -175,7 +175,7 @@ define i32 @select_sdiv_lhs_opaque_const1_i32(i1 %cond) {
; IR-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]
; IR-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
; IR-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]])
-; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41EFFFFFC0000000
+; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], f0x4F7FFFFE
; IR-NEXT: [[TMP8:%.*]] = fptoui float [[TMP7]] to i32
; IR-NEXT: [[TMP9:%.*]] = sub i32 0, [[TMP4]]
; IR-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP8]]
@@ -486,7 +486,7 @@ define i32 @select_add_bitcast_select(i1 %cond) {
; multiple uses.
define <2 x half> @multi_use_cast_regression(i1 %cond) {
; IR-LABEL: @multi_use_cast_regression(
-; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], half 0xH3C00, half 0xH0000
+; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], half 1.000000e+00, half 0.000000e+00
; IR-NEXT: [[FPEXT:%.*]] = fpext half [[SELECT]] to float
; IR-NEXT: [[FSUB:%.*]] = fsub nsz float 1.000000e+00, [[FPEXT]]
; IR-NEXT: [[CALL:%.*]] = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[FPEXT]], float [[FSUB]])
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index df77e7de43bf6..018eb779fc815 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -7,7 +7,7 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; CHECK-LABEL: @udiv_i32(
; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = sub i32 0, [[Y]]
; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
@@ -106,7 +106,7 @@ define amdgpu_kernel void @urem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; CHECK-LABEL: @urem_i32(
; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = sub i32 0, [[Y]]
; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
@@ -205,7 +205,7 @@ define amdgpu_kernel void @sdiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float
; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]])
-; CHECK-NEXT: [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP10:%.*]] = fmul fast float [[TMP9]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP11:%.*]] = fptoui float [[TMP10]] to i32
; CHECK-NEXT: [[TMP12:%.*]] = sub i32 0, [[TMP7]]
; CHECK-NEXT: [[TMP13:%.*]] = mul i32 [[TMP12]], [[TMP11]]
@@ -324,7 +324,7 @@ define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]]
; CHECK-NEXT: [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float
; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP8]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP9]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = sub i32 0, [[TMP6]]
; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP10]]
@@ -1046,7 +1046,7 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = sub i32 0, [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
@@ -1078,7 +1078,7 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i32> [[Y]], i64 1
; CHECK-NEXT: [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float
; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
-; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP36]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP38:%.*]] = fptoui float [[TMP37]] to i32
; CHECK-NEXT: [[TMP39:%.*]] = sub i32 0, [[TMP34]]
; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]
@@ -1110,7 +1110,7 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP66:%.*]] = extractelement <4 x i32> [[Y]], i64 2
; CHECK-NEXT: [[TMP67:%.*]] = uitofp i32 [[TMP66]] to float
; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP67]])
-; CHECK-NEXT: [[TMP69:%.*]] = fmul fast float [[TMP68]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP69:%.*]] = fmul fast float [[TMP68]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP70:%.*]] = fptoui float [[TMP69]] to i32
; CHECK-NEXT: [[TMP71:%.*]] = sub i32 0, [[TMP66]]
; CHECK-NEXT: [[TMP72:%.*]] = mul i32 [[TMP71]], [[TMP70]]
@@ -1142,7 +1142,7 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP98:%.*]] = extractelement <4 x i32> [[Y]], i64 3
; CHECK-NEXT: [[TMP99:%.*]] = uitofp i32 [[TMP98]] to float
; CHECK-NEXT: [[TMP100:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP99]])
-; CHECK-NEXT: [[TMP101:%.*]] = fmul fast float [[TMP100]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP101:%.*]] = fmul fast float [[TMP100]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP102:%.*]] = fptoui float [[TMP101]] to i32
; CHECK-NEXT: [[TMP103:%.*]] = sub i32 0, [[TMP98]]
; CHECK-NEXT: [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP102]]
@@ -1374,7 +1374,7 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = sub i32 0, [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
@@ -1404,7 +1404,7 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[Y]], i64 1
; CHECK-NEXT: [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float
; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
-; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP34]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP36:%.*]] = fptoui float [[TMP35]] to i32
; CHECK-NEXT: [[TMP37:%.*]] = sub i32 0, [[TMP32]]
; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]
@@ -1434,7 +1434,7 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP62:%.*]] = extractelement <4 x i32> [[Y]], i64 2
; CHECK-NEXT: [[TMP63:%.*]] = uitofp i32 [[TMP62]] to float
; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP63]])
-; CHECK-NEXT: [[TMP65:%.*]] = fmul fast float [[TMP64]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP65:%.*]] = fmul fast float [[TMP64]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP66:%.*]] = fptoui float [[TMP65]] to i32
; CHECK-NEXT: [[TMP67:%.*]] = sub i32 0, [[TMP62]]
; CHECK-NEXT: [[TMP68:%.*]] = mul i32 [[TMP67]], [[TMP66]]
@@ -1464,7 +1464,7 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP92:%.*]] = extractelement <4 x i32> [[Y]], i64 3
; CHECK-NEXT: [[TMP93:%.*]] = uitofp i32 [[TMP92]] to float
; CHECK-NEXT: [[TMP94:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP93]])
-; CHECK-NEXT: [[TMP95:%.*]] = fmul fast float [[TMP94]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP95:%.*]] = fmul fast float [[TMP94]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP96:%.*]] = fptoui float [[TMP95]] to i32
; CHECK-NEXT: [[TMP97:%.*]] = sub i32 0, [[TMP92]]
; CHECK-NEXT: [[TMP98:%.*]] = mul i32 [[TMP97]], [[TMP96]]
@@ -1682,7 +1682,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]
; CHECK-NEXT: [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float
; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])
-; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP13:%.*]] = fptoui float [[TMP12]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = sub i32 0, [[TMP9]]
; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]
@@ -1723,7 +1723,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]
; CHECK-NEXT: [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float
; CHECK-NEXT: [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])
-; CHECK-NEXT: [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP53:%.*]] = fmul fast float [[TMP52]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP54:%.*]] = fptoui float [[TMP53]] to i32
; CHECK-NEXT: [[TMP55:%.*]] = sub i32 0, [[TMP50]]
; CHECK-NEXT: [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]
@@ -1764,7 +1764,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP91:%.*]] = xor i32 [[TMP89]], [[TMP86]]
; CHECK-NEXT: [[TMP92:%.*]] = uitofp i32 [[TMP91]] to float
; CHECK-NEXT: [[TMP93:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP92]])
-; CHECK-NEXT: [[TMP94:%.*]] = fmul fast float [[TMP93]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP94:%.*]] = fmul fast float [[TMP93]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP95:%.*]] = fptoui float [[TMP94]] to i32
; CHECK-NEXT: [[TMP96:%.*]] = sub i32 0, [[TMP91]]
; CHECK-NEXT: [[TMP97:%.*]] = mul i32 [[TMP96]], [[TMP95]]
@@ -1805,7 +1805,7 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP132:%.*]] = xor i32 [[TMP130]], [[TMP127]]
; CHECK-NEXT: [[TMP133:%.*]] = uitofp i32 [[TMP132]] to float
; CHECK-NEXT: [[TMP134:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP133]])
-; CHECK-NEXT: [[TMP135:%.*]] = fmul fast float [[TMP134]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP135:%.*]] = fmul fast float [[TMP134]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP136:%.*]] = fptoui float [[TMP135]] to i32
; CHECK-NEXT: [[TMP137:%.*]] = sub i32 0, [[TMP132]]
; CHECK-NEXT: [[TMP138:%.*]] = mul i32 [[TMP137]], [[TMP136]]
@@ -2094,7 +2094,7 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]
; CHECK-NEXT: [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float
; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP10]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP11]] to i32
; CHECK-NEXT: [[TMP13:%.*]] = sub i32 0, [[TMP8]]
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]
@@ -2132,7 +2132,7 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]
; CHECK-NEXT: [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float
; CHECK-NEXT: [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])
-; CHECK-NEXT: [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP49:%.*]] = fmul fast float [[TMP48]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP50:%.*]] = fptoui float [[TMP49]] to i32
; CHECK-NEXT: [[TMP51:%.*]] = sub i32 0, [[TMP46]]
; CHECK-NEXT: [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]
@@ -2170,7 +2170,7 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP84:%.*]] = xor i32 [[TMP82]], [[TMP80]]
; CHECK-NEXT: [[TMP85:%.*]] = uitofp i32 [[TMP84]] to float
; CHECK-NEXT: [[TMP86:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP85]])
-; CHECK-NEXT: [[TMP87:%.*]] = fmul fast float [[TMP86]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP87:%.*]] = fmul fast float [[TMP86]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP88:%.*]] = fptoui float [[TMP87]] to i32
; CHECK-NEXT: [[TMP89:%.*]] = sub i32 0, [[TMP84]]
; CHECK-NEXT: [[TMP90:%.*]] = mul i32 [[TMP89]], [[TMP88]]
@@ -2208,7 +2208,7 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; CHECK-NEXT: [[TMP122:%.*]] = xor i32 [[TMP120]], [[TMP118]]
; CHECK-NEXT: [[TMP123:%.*]] = uitofp i32 [[TMP122]] to float
; CHECK-NEXT: [[TMP124:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP123]])
-; CHECK-NEXT: [[TMP125:%.*]] = fmul fast float [[TMP124]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP125:%.*]] = fmul fast float [[TMP124]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP126:%.*]] = fptoui float [[TMP125]] to i32
; CHECK-NEXT: [[TMP127:%.*]] = sub i32 0, [[TMP122]]
; CHECK-NEXT: [[TMP128:%.*]] = mul i32 [[TMP127]], [[TMP126]]
@@ -5581,7 +5581,7 @@ define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = sub i32 0, [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
@@ -5613,7 +5613,7 @@ define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; CHECK-NEXT: [[TMP34:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
; CHECK-NEXT: [[TMP35:%.*]] = uitofp i32 [[TMP34]] to float
; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]])
-; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP36]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP36]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP38:%.*]] = fptoui float [[TMP37]] to i32
; CHECK-NEXT: [[TMP39:%.*]] = sub i32 0, [[TMP34]]
; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP38]]
@@ -5924,7 +5924,7 @@ define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = sub i32 0, [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], [[TMP6]]
@@ -5954,7 +5954,7 @@ define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; CHECK-NEXT: [[TMP32:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1
; CHECK-NEXT: [[TMP33:%.*]] = uitofp i32 [[TMP32]] to float
; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]])
-; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP34]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP34]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP36:%.*]] = fptoui float [[TMP35]] to i32
; CHECK-NEXT: [[TMP37:%.*]] = sub i32 0, [[TMP32]]
; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP36]]
@@ -6377,7 +6377,7 @@ define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]]
; CHECK-NEXT: [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float
; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]])
-; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP13:%.*]] = fptoui float [[TMP12]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = sub i32 0, [[TMP9]]
; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP13]]
@@ -6418,7 +6418,7 @@ define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; CHECK-NEXT: [[TMP50:%.*]] = xor i32 [[TMP48]], [[TMP45]]
; CHECK-NEXT: [[TMP51:%.*]] = uitofp i32 [[TMP50]] to float
; CHECK-NEXT: [[TMP52:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP51]])
-; CHECK-NEXT: [[TMP53:%.*]] = fmul fast float [[TMP52]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP53:%.*]] = fmul fast float [[TMP52]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP54:%.*]] = fptoui float [[TMP53]] to i32
; CHECK-NEXT: [[TMP55:%.*]] = sub i32 0, [[TMP50]]
; CHECK-NEXT: [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP54]]
@@ -6828,7 +6828,7 @@ define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]]
; CHECK-NEXT: [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float
; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP10]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP11]] to i32
; CHECK-NEXT: [[TMP13:%.*]] = sub i32 0, [[TMP8]]
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP12]]
@@ -6866,7 +6866,7 @@ define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; CHECK-NEXT: [[TMP46:%.*]] = xor i32 [[TMP44]], [[TMP42]]
; CHECK-NEXT: [[TMP47:%.*]] = uitofp i32 [[TMP46]] to float
; CHECK-NEXT: [[TMP48:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP47]])
-; CHECK-NEXT: [[TMP49:%.*]] = fmul fast float [[TMP48]], 0x41EFFFFFC0000000
+; CHECK-NEXT: [[TMP49:%.*]] = fmul fast float [[TMP48]], f0x4F7FFFFE
; CHECK-NEXT: [[TMP50:%.*]] = fptoui float [[TMP49]] to i32
; CHECK-NEXT: [[TMP51:%.*]] = sub i32 0, [[TMP46]]
; CHECK-NEXT: [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP50]]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-log.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-log.ll
index e50f2b63646ae..6bda2f8a6967c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-log.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-log.ll
@@ -34,7 +34,7 @@ define half @log_f16_ulp180(half %x) {
; GFX8-LABEL: define half @log_f16_ulp180(
; GFX8-SAME: half [[X:%.*]]) #[[ATTR0]] {
; GFX8-NEXT: [[TMP1:%.*]] = call half @llvm.log2.f16(half [[X]])
-; GFX8-NEXT: [[RESULT:%.*]] = fmul half [[TMP1]], 0xH398C
+; GFX8-NEXT: [[RESULT:%.*]] = fmul half [[TMP1]], 6.933590e-01
; GFX8-NEXT: ret half [[RESULT]]
;
%result = call half @llvm.log.f16(half %x), !fpmath !{float 0x3FFCCCCCC0000000}
@@ -67,7 +67,7 @@ define half @log_f16_ulp2(half %x) {
; GFX8-LABEL: define half @log_f16_ulp2(
; GFX8-SAME: half [[X:%.*]]) #[[ATTR0]] {
; GFX8-NEXT: [[TMP1:%.*]] = call half @llvm.log2.f16(half [[X]])
-; GFX8-NEXT: [[RESULT:%.*]] = fmul half [[TMP1]], 0xH398C
+; GFX8-NEXT: [[RESULT:%.*]] = fmul half [[TMP1]], 6.933590e-01
; GFX8-NEXT: ret half [[RESULT]]
;
%result = call half @llvm.log.f16(half %x), !fpmath !0
@@ -84,7 +84,7 @@ define half @log10_f16_ulp2(half %x) {
; GFX8-LABEL: define half @log10_f16_ulp2(
; GFX8-SAME: half [[X:%.*]]) #[[ATTR0]] {
; GFX8-NEXT: [[TMP1:%.*]] = call half @llvm.log2.f16(half [[X]])
-; GFX8-NEXT: [[RESULT:%.*]] = fmul half [[TMP1]], 0xH34D1
+; GFX8-NEXT: [[RESULT:%.*]] = fmul half [[TMP1]], 3.010250e-01
; GFX8-NEXT: ret half [[RESULT]]
;
%result = call half @llvm.log10.f16(half %x), !fpmath !0
@@ -133,7 +133,7 @@ define <2 x half> @log_v2f16_ulp2(<2 x half> %x) {
; GFX8-LABEL: define <2 x half> @log_v2f16_ulp2(
; GFX8-SAME: <2 x half> [[X:%.*]]) #[[ATTR0]] {
; GFX8-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.log2.v2f16(<2 x half> [[X]])
-; GFX8-NEXT: [[RESULT:%.*]] = fmul <2 x half> [[TMP1]], splat (half 0xH398C)
+; GFX8-NEXT: [[RESULT:%.*]] = fmul <2 x half> [[TMP1]], splat (half 6.933590e-01)
; GFX8-NEXT: ret <2 x half> [[RESULT]]
;
%result = call <2 x half> @llvm.log.v2f16(<2 x half> %x), !fpmath !0
@@ -150,7 +150,7 @@ define <3 x half> @log_v3f16_ulp2(<3 x half> %x) {
; GFX8-LABEL: define <3 x half> @log_v3f16_ulp2(
; GFX8-SAME: <3 x half> [[X:%.*]]) #[[ATTR0]] {
; GFX8-NEXT: [[TMP1:%.*]] = call <3 x half> @llvm.log2.v3f16(<3 x half> [[X]])
-; GFX8-NEXT: [[RESULT:%.*]] = fmul <3 x half> [[TMP1]], splat (half 0xH398C)
+; GFX8-NEXT: [[RESULT:%.*]] = fmul <3 x half> [[TMP1]], splat (half 6.933590e-01)
; GFX8-NEXT: ret <3 x half> [[RESULT]]
;
%result = call <3 x half> @llvm.log.v3f16(<3 x half> %x), !fpmath !0
@@ -177,10 +177,10 @@ define bfloat @log_bf16_ulp2(bfloat %x) {
;.
-; GFX7: [[META0]] = !{float 0x3FFCCCCCC0000000}
-; GFX7: [[META1]] = !{float 0x3FFCCCCCA0000000}
+; GFX7: [[META0]] = !{float 1.800000e+00}
+; GFX7: [[META1]] = !{float f0x3FE66665}
; GFX7: [[META2]] = !{float 2.000000e+00}
;.
-; GFX8: [[META0]] = !{float 0x3FFCCCCCA0000000}
+; GFX8: [[META0]] = !{float f0x3FE66665}
; GFX8: [[META1]] = !{float 2.000000e+00}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-sqrt.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-sqrt.ll
index 03c84d1193609..b90afb7ae9b7f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-sqrt.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-sqrt.ll
@@ -24,21 +24,21 @@ define amdgpu_kernel void @sqrt_fpmath_f32(ptr addrspace(1) %out, float %x) {
; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])
; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0
; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])
; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0
; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])
; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])
; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0
; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])
; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0
; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])
; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])
@@ -94,13 +94,13 @@ define amdgpu_kernel void @sqrt_fpmath_v2f32(ptr addrspace(1) %out, <2 x float>
; IEEE-NEXT: store volatile <2 x float> [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-NEXT: [[TMP3:%.*]] = fcmp olt float [[TMP1]], 0x3810000000000000
+; IEEE-NEXT: [[TMP3:%.*]] = fcmp olt float [[TMP1]], f0x00800000
; IEEE-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 32, i32 0
; IEEE-NEXT: [[TMP5:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP1]], i32 [[TMP4]])
; IEEE-NEXT: [[TMP6:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP5]])
; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP3]], i32 -16, i32 0
; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP6]], i32 [[TMP7]])
-; IEEE-NEXT: [[TMP9:%.*]] = fcmp olt float [[TMP2]], 0x3810000000000000
+; IEEE-NEXT: [[TMP9:%.*]] = fcmp olt float [[TMP2]], f0x00800000
; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 32, i32 0
; IEEE-NEXT: [[TMP11:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP2]], i32 [[TMP10]])
; IEEE-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP11]])
@@ -111,13 +111,13 @@ define amdgpu_kernel void @sqrt_fpmath_v2f32(ptr addrspace(1) %out, <2 x float>
; IEEE-NEXT: store volatile <2 x float> [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-NEXT: [[TMP17:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-NEXT: [[TMP18:%.*]] = fcmp olt float [[TMP16]], 0x3810000000000000
+; IEEE-NEXT: [[TMP18:%.*]] = fcmp olt float [[TMP16]], f0x00800000
; IEEE-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 32, i32 0
; IEEE-NEXT: [[TMP20:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP16]], i32 [[TMP19]])
; IEEE-NEXT: [[TMP21:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP20]])
; IEEE-NEXT: [[TMP22:%.*]] = select i1 [[TMP18]], i32 -16, i32 0
; IEEE-NEXT: [[TMP23:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP21]], i32 [[TMP22]])
-; IEEE-NEXT: [[TMP24:%.*]] = fcmp olt float [[TMP17]], 0x3810000000000000
+; IEEE-NEXT: [[TMP24:%.*]] = fcmp olt float [[TMP17]], f0x00800000
; IEEE-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i32 32, i32 0
; IEEE-NEXT: [[TMP26:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP17]], i32 [[TMP25]])
; IEEE-NEXT: [[TMP27:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP26]])
@@ -128,13 +128,13 @@ define amdgpu_kernel void @sqrt_fpmath_v2f32(ptr addrspace(1) %out, <2 x float>
; IEEE-NEXT: store volatile <2 x float> [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[TMP31:%.*]] = extractelement <2 x float> [[X]], i64 0
; IEEE-NEXT: [[TMP32:%.*]] = extractelement <2 x float> [[X]], i64 1
-; IEEE-NEXT: [[TMP33:%.*]] = fcmp olt float [[TMP31]], 0x3810000000000000
+; IEEE-NEXT: [[TMP33:%.*]] = fcmp olt float [[TMP31]], f0x00800000
; IEEE-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 32, i32 0
; IEEE-NEXT: [[TMP35:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP31]], i32 [[TMP34]])
; IEEE-NEXT: [[TMP36:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP35]])
; IEEE-NEXT: [[TMP37:%.*]] = select i1 [[TMP33]], i32 -16, i32 0
; IEEE-NEXT: [[TMP38:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP36]], i32 [[TMP37]])
-; IEEE-NEXT: [[TMP39:%.*]] = fcmp olt float [[TMP32]], 0x3810000000000000
+; IEEE-NEXT: [[TMP39:%.*]] = fcmp olt float [[TMP32]], f0x00800000
; IEEE-NEXT: [[TMP40:%.*]] = select i1 [[TMP39]], i32 32, i32 0
; IEEE-NEXT: [[TMP41:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP32]], i32 [[TMP40]])
; IEEE-NEXT: [[TMP42:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP41]])
@@ -247,21 +247,21 @@ define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero(ptr addrspace(1) %out,
; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])
; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0
; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])
; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0
; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])
; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])
; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0
; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])
; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0
; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])
; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])
@@ -315,21 +315,21 @@ define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub(ptr addrspace(1)
; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])
; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0
; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])
; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0
; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])
; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])
; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0
; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])
; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0
; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])
; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])
@@ -383,21 +383,21 @@ define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub_noinf(ptr addrsp
; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])
; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0
; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])
; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0
; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])
; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])
; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0
; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])
; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0
; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])
; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])
@@ -451,21 +451,21 @@ define amdgpu_kernel void @sqrt_fpmath_f32_known_nopsub(ptr addrspace(1) %out, f
; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
; IEEE-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP1:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 32, i32 0
; IEEE-NEXT: [[TMP3:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP2]])
; IEEE-NEXT: [[TMP4:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP3]])
; IEEE-NEXT: [[TMP5:%.*]] = select i1 [[TMP1]], i32 -16, i32 0
; IEEE-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP4]], i32 [[TMP5]])
; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP6:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 32, i32 0
; IEEE-NEXT: [[TMP8:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP7]])
; IEEE-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP8]])
; IEEE-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i32 -16, i32 0
; IEEE-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP9]], i32 [[TMP10]])
; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
-; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], 0x3810000000000000
+; IEEE-NEXT: [[TMP11:%.*]] = fcmp olt float [[X]], f0x00800000
; IEEE-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 32, i32 0
; IEEE-NEXT: [[TMP13:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[TMP12]])
; IEEE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[TMP13]])
@@ -551,7 +551,7 @@ define amdgpu_kernel void @sqrt_fpmath_f32_assume_nosub(ptr addrspace(1) %out, f
; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_assume_nosub
; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
+; CHECK-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])
; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
index b2d5bb2faeca7..a553bb10ff29d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
@@ -57,11 +57,11 @@ define float @test_pow_fast_f32(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp fast une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp fast olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select fast i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select fast i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp fast oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp fast olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], [[TMP23]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = select fast i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select fast i1 [[TMP24]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP26:%.*]] = select fast i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP27:%.*]] = call fast float @llvm.copysign.f32(float [[TMP25]], float [[TMP26]])
; NOPRELINK-NEXT: [[TMP28:%.*]] = select fast i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
@@ -99,11 +99,11 @@ define <2 x float> @test_pow_fast_v2f32(<2 x float> %x, <2 x float> %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp fast une <2 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp fast olt <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select fast <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select fast <2 x i1> [[TMP20]], <2 x float> splat (float +qnan), <2 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp fast oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp fast olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[TMP22]], [[TMP23]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = select fast <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select fast <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP26:%.*]] = select fast <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP27:%.*]] = call fast <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP25]], <2 x float> [[TMP26]])
; NOPRELINK-NEXT: [[TMP28:%.*]] = select fast <2 x i1> [[TMP22]], <2 x float> [[TMP27]], <2 x float> [[TMP21]]
@@ -141,9 +141,9 @@ define float @test_pow_afn_f32_nnan(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
@@ -154,12 +154,12 @@ define float @test_pow_afn_f32_nnan(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
@@ -197,11 +197,11 @@ define float @test_pow_afn_f32_nnan_ninf(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan ninf afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan ninf afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan ninf afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan ninf afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], [[TMP23]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = select nnan ninf afn i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select nnan ninf afn i1 [[TMP24]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan ninf afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP27:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP25]], float [[TMP26]])
; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan ninf afn i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
@@ -239,9 +239,9 @@ define <2 x float> @test_pow_afn_v2f32_nnan(<2 x float> %x, <2 x float> %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une <2 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn <2 x i1> [[TMP20]], <2 x float> splat (float +qnan), <2 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP22]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une <2 x float> [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
@@ -252,12 +252,12 @@ define <2 x float> @test_pow_afn_v2f32_nnan(<2 x float> %x, <2 x float> %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn <2 x i1> [[TMP27]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn <2 x i1> [[TMP23]], <2 x float> [[TMP31]], <2 x float> [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP33]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP36:%.*]] = or <2 x i1> [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <2 x i1> [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn <2 x i1> [[TMP38]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn <2 x i1> [[TMP38]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP39]], <2 x float> [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn <2 x i1> [[TMP36]], <2 x float> [[TMP41]], <2 x float> [[TMP32]]
@@ -295,11 +295,11 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf(<2 x float> %x, <2 x float> %y)
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan ninf afn olt <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> splat (float +qnan), <2 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan ninf afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[TMP22]], [[TMP23]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = select nnan ninf afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select nnan ninf afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan ninf afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP27:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP25]], <2 x float> [[TMP26]])
; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan ninf afn <2 x i1> [[TMP22]], <2 x float> [[TMP27]], <2 x float> [[TMP21]]
@@ -337,9 +337,9 @@ define float @test_pow_afn_f32(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
@@ -350,17 +350,17 @@ define float @test_pow_afn_f32(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float +qnan, float [[TMP42]]
; NOPRELINK-NEXT: ret float [[TMP44]]
;
%pow = tail call afn float @_Z3powff(float %x, float %y)
@@ -395,9 +395,9 @@ define <2 x float> @test_pow_afn_v2f32(<2 x float> %x, <2 x float> %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float +qnan), <2 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <2 x float> [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
@@ -408,17 +408,17 @@ define <2 x float> @test_pow_afn_v2f32(<2 x float> %x, <2 x float> %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP27]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP31]], <2 x float> [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <2 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <2 x float> [[TMP33]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP36:%.*]] = or <2 x i1> [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <2 x i1> [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <2 x i1> [[TMP38]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <2 x i1> [[TMP38]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP39]], <2 x float> [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <2 x i1> [[TMP36]], <2 x float> [[TMP41]], <2 x float> [[TMP32]]
; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <2 x float> [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <2 x i1> [[TMP43]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP42]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <2 x i1> [[TMP43]], <2 x float> splat (float +qnan), <2 x float> [[TMP42]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP44]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
@@ -453,9 +453,9 @@ define <3 x float> @test_pow_afn_v3f32(<3 x float> %x, <3 x float> %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <3 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <3 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <3 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <3 x i1> [[TMP20]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <3 x i1> [[TMP20]], <3 x float> splat (float +qnan), <3 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <3 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <3 x float> [[TMP22]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <3 x float> [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP4]])
@@ -466,17 +466,17 @@ define <3 x float> @test_pow_afn_v3f32(<3 x float> %x, <3 x float> %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <3 x i1> [[TMP27]], <3 x float> splat (float 1.000000e+00), <3 x float> [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <3 x i1> [[TMP23]], <3 x float> [[TMP31]], <3 x float> [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <3 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <3 x float> [[TMP33]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <3 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP36:%.*]] = or <3 x i1> [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <3 x i1> [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <3 x i1> [[TMP38]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <3 x i1> [[TMP38]], <3 x float> zeroinitializer, <3 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <3 x i1> [[TMP14]], <3 x float> [[TMP4]], <3 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP39]], <3 x float> [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <3 x i1> [[TMP36]], <3 x float> [[TMP41]], <3 x float> [[TMP32]]
; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <3 x float> [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <3 x i1> [[TMP43]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP42]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <3 x i1> [[TMP43]], <3 x float> splat (float +qnan), <3 x float> [[TMP42]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP44]]
;
%pow = tail call afn <3 x float> @_Z3powDv3_fS_(<3 x float> %x, <3 x float> %y)
@@ -511,9 +511,9 @@ define <4 x float> @test_pow_afn_v4f32(<4 x float> %x, <4 x float> %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <4 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <4 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <4 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <4 x i1> [[TMP20]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <4 x i1> [[TMP20]], <4 x float> splat (float +qnan), <4 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <4 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <4 x float> [[TMP22]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <4 x float> [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
@@ -524,17 +524,17 @@ define <4 x float> @test_pow_afn_v4f32(<4 x float> %x, <4 x float> %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <4 x i1> [[TMP27]], <4 x float> splat (float 1.000000e+00), <4 x float> [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <4 x i1> [[TMP23]], <4 x float> [[TMP31]], <4 x float> [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <4 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <4 x float> [[TMP33]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <4 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP36:%.*]] = or <4 x i1> [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <4 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <4 x i1> [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <4 x i1> [[TMP38]], <4 x float> zeroinitializer, <4 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <4 x i1> [[TMP38]], <4 x float> zeroinitializer, <4 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <4 x i1> [[TMP14]], <4 x float> [[TMP4]], <4 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP39]], <4 x float> [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <4 x i1> [[TMP36]], <4 x float> [[TMP41]], <4 x float> [[TMP32]]
; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <4 x float> [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <4 x i1> [[TMP43]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP42]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <4 x i1> [[TMP43]], <4 x float> splat (float +qnan), <4 x float> [[TMP42]]
; NOPRELINK-NEXT: ret <4 x float> [[TMP44]]
;
%pow = tail call afn <4 x float> @_Z3powDv4_fS_(<4 x float> %x, <4 x float> %y)
@@ -569,9 +569,9 @@ define <8 x float> @test_pow_afn_v8f32(<8 x float> %x, <8 x float> %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <8 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <8 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <8 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <8 x i1> [[TMP20]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <8 x i1> [[TMP20]], <8 x float> splat (float +qnan), <8 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <8 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <8 x float> [[TMP22]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <8 x float> [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP4]])
@@ -582,17 +582,17 @@ define <8 x float> @test_pow_afn_v8f32(<8 x float> %x, <8 x float> %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <8 x i1> [[TMP27]], <8 x float> splat (float 1.000000e+00), <8 x float> [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <8 x i1> [[TMP23]], <8 x float> [[TMP31]], <8 x float> [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <8 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <8 x float> [[TMP33]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <8 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP36:%.*]] = or <8 x i1> [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <8 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <8 x i1> [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <8 x i1> [[TMP38]], <8 x float> zeroinitializer, <8 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <8 x i1> [[TMP38]], <8 x float> zeroinitializer, <8 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <8 x i1> [[TMP14]], <8 x float> [[TMP4]], <8 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP39]], <8 x float> [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <8 x i1> [[TMP36]], <8 x float> [[TMP41]], <8 x float> [[TMP32]]
; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <8 x float> [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <8 x i1> [[TMP43]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP42]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <8 x i1> [[TMP43]], <8 x float> splat (float +qnan), <8 x float> [[TMP42]]
; NOPRELINK-NEXT: ret <8 x float> [[TMP44]]
;
%pow = tail call afn <8 x float> @_Z3powDv8_fS_(<8 x float> %x, <8 x float> %y)
@@ -627,9 +627,9 @@ define <16 x float> @test_pow_afn_v16f32(<16 x float> %x, <16 x float> %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <16 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <16 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <16 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <16 x i1> [[TMP20]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <16 x i1> [[TMP20]], <16 x float> splat (float +qnan), <16 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <16 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <16 x float> [[TMP22]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <16 x float> [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP4]])
@@ -640,17 +640,17 @@ define <16 x float> @test_pow_afn_v16f32(<16 x float> %x, <16 x float> %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <16 x i1> [[TMP27]], <16 x float> splat (float 1.000000e+00), <16 x float> [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <16 x i1> [[TMP23]], <16 x float> [[TMP31]], <16 x float> [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <16 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <16 x float> [[TMP33]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <16 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP36:%.*]] = or <16 x i1> [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <16 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <16 x i1> [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <16 x i1> [[TMP38]], <16 x float> zeroinitializer, <16 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <16 x i1> [[TMP38]], <16 x float> zeroinitializer, <16 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <16 x i1> [[TMP14]], <16 x float> [[TMP4]], <16 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <16 x float> @llvm.copysign.v16f32(<16 x float> [[TMP39]], <16 x float> [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <16 x i1> [[TMP36]], <16 x float> [[TMP41]], <16 x float> [[TMP32]]
; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <16 x float> [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <16 x i1> [[TMP43]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP42]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <16 x i1> [[TMP43]], <16 x float> splat (float +qnan), <16 x float> [[TMP42]]
; NOPRELINK-NEXT: ret <16 x float> [[TMP44]]
;
%pow = tail call afn <16 x float> @_Z3powDv16_fS_(<16 x float> %x, <16 x float> %y)
@@ -995,9 +995,9 @@ define float @test_pow_afn_f32_minsize(float %x, float %y) #0 {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
@@ -1008,17 +1008,17 @@ define float @test_pow_afn_f32_minsize(float %x, float %y) #0 {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float +qnan, float [[TMP42]]
; NOPRELINK-NEXT: ret float [[TMP44]]
;
%pow = tail call afn float @_Z3powff(float %x, float %y)
@@ -1053,9 +1053,9 @@ define float @test_pow_afn_f32_nnan_minsize(float %x, float %y) #0 {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
@@ -1066,12 +1066,12 @@ define float @test_pow_afn_f32_nnan_minsize(float %x, float %y) #0 {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
@@ -1109,9 +1109,9 @@ define float @test_pow_afn_f32_noinline(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
@@ -1122,17 +1122,17 @@ define float @test_pow_afn_f32_noinline(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float +qnan, float [[TMP42]]
; NOPRELINK-NEXT: ret float [[TMP44]]
;
%pow = tail call afn float @_Z3powff(float %x, float %y) #1
@@ -1167,9 +1167,9 @@ define float @test_pow_afn_f32_nnan_noinline(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
@@ -1180,12 +1180,12 @@ define float @test_pow_afn_f32_nnan_noinline(float %x, float %y) {
; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
@@ -1225,9 +1225,9 @@ define float @test_pow_afn_f32_strictfp(float %x, float %y) #2 {
; NOPRELINK-NEXT: [[TMP20:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR3]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = xor i1 [[TMP19]], true
; NOPRELINK-NEXT: [[TMP22:%.*]] = and i1 [[TMP20]], [[TMP21]]
-; NOPRELINK-NEXT: [[TMP23:%.*]] = select nnan nsz afn i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP17]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select nnan nsz afn i1 [[TMP22]], float +qnan, float [[TMP17]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP2]]) #[[ATTR3]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP24]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP24]], float +inf, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP2]]) #[[ATTR3]]
; NOPRELINK-NEXT: [[TMP27:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP2]], float [[TMP26]], metadata !"une", metadata !"fpexcept.strict") #[[ATTR3]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP4]]) #[[ATTR3]]
@@ -1238,17 +1238,17 @@ define float @test_pow_afn_f32_strictfp(float %x, float %y) #2 {
; NOPRELINK-NEXT: [[TMP33:%.*]] = select nnan nsz afn i1 [[TMP29]], float [[TMP28]], float [[TMP32]]
; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan nsz afn i1 [[TMP25]], float [[TMP33]], float [[TMP23]]
; NOPRELINK-NEXT: [[TMP35:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP4]]) #[[ATTR3]]
-; NOPRELINK-NEXT: [[TMP36:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP35]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP36:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP35]], float +inf, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
; NOPRELINK-NEXT: [[TMP38:%.*]] = or i1 [[TMP36]], [[TMP37]]
; NOPRELINK-NEXT: [[TMP39:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP2]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR3]]
; NOPRELINK-NEXT: [[TMP40:%.*]] = xor i1 [[TMP37]], [[TMP39]]
-; NOPRELINK-NEXT: [[TMP41:%.*]] = select nnan nsz afn i1 [[TMP40]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP41:%.*]] = select nnan nsz afn i1 [[TMP40]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan nsz afn i1 [[TMP15]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP43:%.*]] = call nnan nsz afn float @llvm.copysign.f32(float [[TMP41]], float [[TMP42]]) #[[ATTR3]]
; NOPRELINK-NEXT: [[TMP44:%.*]] = select nnan nsz afn i1 [[TMP38]], float [[TMP43]], float [[TMP34]]
; NOPRELINK-NEXT: [[TMP45:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float [[TMP2]], metadata !"uno", metadata !"fpexcept.strict") #[[ATTR3]]
-; NOPRELINK-NEXT: [[TMP46:%.*]] = select nnan nsz afn i1 [[TMP45]], float 0x7FF8000000000000, float [[TMP44]]
+; NOPRELINK-NEXT: [[TMP46:%.*]] = select nnan nsz afn i1 [[TMP45]], float +qnan, float [[TMP44]]
; NOPRELINK-NEXT: ret float [[TMP46]]
;
%pow = tail call afn nsz nnan float @_Z3powff(float %x, float %y) #2
@@ -1333,17 +1333,17 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_0.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float +qnan), <2 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = or <2 x i1> [[TMP23]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> [[TMP28]], <2 x float> [[TMP21]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[TMP4]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0.0, float -0.0>)
@@ -1394,17 +1394,17 @@ define float @test_pow_afn_f32_0.5(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 0.5)
@@ -1437,19 +1437,19 @@ define float @test_pow_afn_f32_neg0.5(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -0.5)
@@ -1482,17 +1482,17 @@ define <2 x float> @test_pow_afn_v2f32_0.5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float 0.5>)
@@ -1525,19 +1525,19 @@ define <2 x float> @test_pow_afn_v2f32_neg0.5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -0.5, float -0.5>)
@@ -1570,19 +1570,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_0.5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float -0.5>)
@@ -1615,17 +1615,17 @@ define <3 x float> @test_pow_afn_v3f32_0.5_splat_undef(<3 x float> %x, <3 x floa
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <3 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <3 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <3 x i1> [[TMP18]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <3 x i1> [[TMP18]], <3 x float> splat (float +qnan), <3 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <3 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <3 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <3 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <3 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <3 x i1> [[TMP22]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <3 x i1> [[TMP22]], <3 x float> zeroinitializer, <3 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[X]], <3 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP24]], <3 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <3 x i1> [[TMP23]], <3 x float> [[TMP26]], <3 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <3 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <3 x i1> [[TMP28]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <3 x i1> [[TMP28]], <3 x float> splat (float +qnan), <3 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP29]]
;
%pow = tail call afn <3 x float> @_Z3powDv3_fS_(<3 x float> %x, <3 x float> <float 0.5, float poison, float 0.5>)
@@ -1658,19 +1658,19 @@ define <3 x float> @test_pow_afn_v3f32_neg0.5_splat_undef(<3 x float> %x, <3 x f
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <3 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <3 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <3 x i1> [[TMP18]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <3 x i1> [[TMP18]], <3 x float> splat (float +qnan), <3 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <3 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <3 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <3 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <3 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <3 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <3 x i1> [[TMP25]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <3 x i1> [[TMP25]], <3 x float> zeroinitializer, <3 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[X]], <3 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP26]], <3 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <3 x i1> [[TMP23]], <3 x float> [[TMP28]], <3 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <3 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <3 x i1> [[TMP30]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <3 x i1> [[TMP30]], <3 x float> splat (float +qnan), <3 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP31]]
;
%pow = tail call afn <3 x float> @_Z3powDv3_fS_(<3 x float> %x, <3 x float> <float -0.5, float poison, float -0.5>)
@@ -1741,19 +1741,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_1.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 1.0, float -1.0>)
@@ -1815,19 +1815,19 @@ define float @test_pow_afn_f32_neg2.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -2.0)
@@ -1870,19 +1870,19 @@ define <2 x float> @test_pow_afn_v2f32_neg2.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -2.0, float -2.0>)
@@ -1915,19 +1915,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_2.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 2.0, float -2.0>)
@@ -1960,17 +1960,17 @@ define float @test_pow_afn_f32_3.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 3.0)
@@ -2003,19 +2003,19 @@ define float @test_pow_afn_f32_neg3.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -3.0)
@@ -2048,17 +2048,17 @@ define <2 x float> @test_pow_afn_v2f32_3.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float 3.0>)
@@ -2091,19 +2091,19 @@ define <2 x float> @test_pow_afn_v2f32_neg3.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -3.0, float -3.0>)
@@ -2136,19 +2136,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_3.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float -3.0>)
@@ -2158,13 +2158,13 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_3.0(<2 x float> %x) {
define float @test_pow_afn_f32_3.99(float %x) {
; PRELINK-LABEL: define float @test_pow_afn_f32_3.99
; PRELINK-SAME: (float [[X:%.*]]) {
-; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float 0x400FEB8520000000)
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float 3.990000e+00)
; PRELINK-NEXT: ret float [[POW]]
;
; NOPRELINK-LABEL: define float @test_pow_afn_f32_3.99
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 0x400FEB8520000000
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 3.990000e+00
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
@@ -2181,17 +2181,17 @@ define float @test_pow_afn_f32_3.99(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 0x400FEB8520000000)
@@ -2201,13 +2201,13 @@ define float @test_pow_afn_f32_3.99(float %x) {
define float @test_pow_afn_f32_neg3.99(float %x) {
; PRELINK-LABEL: define float @test_pow_afn_f32_neg3.99
; PRELINK-SAME: (float [[X:%.*]]) {
-; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float 0xC00FEB8520000000)
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float -3.990000e+00)
; PRELINK-NEXT: ret float [[POW]]
;
; NOPRELINK-LABEL: define float @test_pow_afn_f32_neg3.99
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 0xC00FEB8520000000
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float -3.990000e+00
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
@@ -2224,19 +2224,19 @@ define float @test_pow_afn_f32_neg3.99(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float 0xC00FEB8520000000)
@@ -2246,13 +2246,13 @@ define float @test_pow_afn_f32_neg3.99(float %x) {
define <2 x float> @test_pow_afn_v2f32_3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
-; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0x400FEB8520000000))
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 3.990000e+00))
; PRELINK-NEXT: ret <2 x float> [[POW]]
;
; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 0x400FEB8520000000)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 3.990000e+00)
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
@@ -2269,17 +2269,17 @@ define <2 x float> @test_pow_afn_v2f32_3.99(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0x400FEB8520000000>)
@@ -2289,13 +2289,13 @@ define <2 x float> @test_pow_afn_v2f32_3.99(<2 x float> %x) {
define <2 x float> @test_pow_afn_v2f32_neg3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
-; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0xC00FEB8520000000))
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -3.990000e+00))
; PRELINK-NEXT: ret <2 x float> [[POW]]
;
; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 0xC00FEB8520000000)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float -3.990000e+00)
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
@@ -2312,19 +2312,19 @@ define <2 x float> @test_pow_afn_v2f32_neg3.99(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0xC00FEB8520000000, float 0xC00FEB8520000000>)
@@ -2334,13 +2334,13 @@ define <2 x float> @test_pow_afn_v2f32_neg3.99(<2 x float> %x) {
define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
-; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 3.990000e+00, float -3.990000e+00>)
; PRELINK-NEXT: ret <2 x float> [[POW]]
;
; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 3.990000e+00, float -3.990000e+00>
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
@@ -2357,19 +2357,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
@@ -2402,17 +2402,17 @@ define float @test_pow_afn_f32_8.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 8.0)
@@ -2445,19 +2445,19 @@ define float @test_pow_afn_f32_neg8.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -8.0)
@@ -2490,17 +2490,17 @@ define <2 x float> @test_pow_afn_v2f32_8.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float 8.0>)
@@ -2533,19 +2533,19 @@ define <2 x float> @test_pow_afn_v2f32_neg8.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -8.0, float -8.0>)
@@ -2578,19 +2578,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_8.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float -8.0>)
@@ -2623,17 +2623,17 @@ define float @test_pow_afn_f32_12.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 12.0)
@@ -2666,19 +2666,19 @@ define float @test_pow_afn_f32_neg12.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -12.0)
@@ -2711,17 +2711,17 @@ define <2 x float> @test_pow_afn_v2f32_12.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float 12.0>)
@@ -2754,19 +2754,19 @@ define <2 x float> @test_pow_afn_v2f32_neg12.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -12.0, float -12.0>)
@@ -2799,19 +2799,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_12.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float -12.0>)
@@ -2844,17 +2844,17 @@ define float @test_pow_afn_f32_13.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 13.0)
@@ -2887,19 +2887,19 @@ define float @test_pow_afn_f32_neg13.0(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -13.0)
@@ -2932,17 +2932,17 @@ define <2 x float> @test_pow_afn_v2f32_13.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 13.0>)
@@ -2975,19 +2975,19 @@ define <2 x float> @test_pow_afn_v2f32_neg13.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -13.0, float -13.0>)
@@ -3020,17 +3020,17 @@ define <2 x float> @test_pow_afn_v2f32_13.0_15.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 15.0>)
@@ -3063,17 +3063,17 @@ define <2 x float> @test_pow_afn_v2f32_13.0_14.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 14.0>)
@@ -3106,17 +3106,17 @@ define <2 x float> @test_pow_afn_v2f32_14.0_16.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float +qnan), <2 x float> [[TMP27]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 14.0, float 16.0>)
@@ -3149,19 +3149,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float -13.0>)
@@ -3194,19 +3194,19 @@ define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0_minus_14.0(<2 x float> %x
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -13.0, float -14.0>)
@@ -3238,7 +3238,7 @@ define float @test_pow_afn_f32_nnan_x_known_positive(float nofpclass(ninf nnorm
; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn oeq float [[TMP17]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn oeq float [[TMP17]], +inf
; NOPRELINK-NEXT: [[TMP19:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP19]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
@@ -3249,12 +3249,12 @@ define float @test_pow_afn_f32_nnan_x_known_positive(float nofpclass(ninf nnorm
; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan afn i1 [[TMP22]], float 1.000000e+00, float [[TMP25]]
; NOPRELINK-NEXT: [[TMP27:%.*]] = select nnan afn i1 [[TMP18]], float [[TMP26]], float [[TMP16]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp nnan afn oeq float [[TMP28]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp nnan afn oeq float [[TMP28]], +inf
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP31:%.*]] = or i1 [[TMP29]], [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP33:%.*]] = xor i1 [[TMP30]], [[TMP32]]
-; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan afn i1 [[TMP33]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan afn i1 [[TMP33]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP34]], float [[TMP35]])
; NOPRELINK-NEXT: [[TMP37:%.*]] = select nnan afn i1 [[TMP31]], float [[TMP36]], float [[TMP27]]
@@ -3292,7 +3292,7 @@ define float @test_pow_afn_f32_nnan_ninf_x_known_positive(float nofpclass(ninf n
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = xor i1 [[TMP16]], [[TMP17]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn i1 [[TMP18]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn i1 [[TMP18]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn i1 [[TMP13]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP19]], float [[TMP20]])
; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn i1 [[TMP16]], float [[TMP21]], float [[TMP15]]
@@ -3327,7 +3327,7 @@ define <2 x float> @test_pow_afn_v2f32_nnan_x_known_positive(<2 x float> nofpcla
; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP17]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP17]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP19:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn une <2 x float> [[TMP2]], [[TMP19]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
@@ -3338,12 +3338,12 @@ define <2 x float> @test_pow_afn_v2f32_nnan_x_known_positive(<2 x float> nofpcla
; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan afn <2 x i1> [[TMP22]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP25]]
; NOPRELINK-NEXT: [[TMP27:%.*]] = select nnan afn <2 x i1> [[TMP18]], <2 x float> [[TMP26]], <2 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP28]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP28]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP31:%.*]] = or <2 x i1> [[TMP29]], [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp nnan afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP33:%.*]] = xor <2 x i1> [[TMP30]], [[TMP32]]
-; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan afn <2 x i1> [[TMP33]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan afn <2 x i1> [[TMP33]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP35:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP36:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP34]], <2 x float> [[TMP35]])
; NOPRELINK-NEXT: [[TMP37:%.*]] = select nnan afn <2 x i1> [[TMP31]], <2 x float> [[TMP36]], <2 x float> [[TMP27]]
@@ -3381,7 +3381,7 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf_x_known_positive(<2 x float> no
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = xor <2 x i1> [[TMP16]], [[TMP17]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn <2 x i1> [[TMP13]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP19]], <2 x float> [[TMP20]])
; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP16]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
@@ -3431,7 +3431,7 @@ define float @test_pow_afn_f32_x_known_positive(float nofpclass(ninf nnorm nsub)
; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq float [[TMP17]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq float [[TMP17]], +inf
; NOPRELINK-NEXT: [[TMP19:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une float [[TMP2]], [[TMP19]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
@@ -3442,17 +3442,17 @@ define float @test_pow_afn_f32_x_known_positive(float nofpclass(ninf nnorm nsub)
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP22]], float 1.000000e+00, float [[TMP25]]
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP18]], float [[TMP26]], float [[TMP16]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp afn oeq float [[TMP28]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp afn oeq float [[TMP28]], +inf
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP31:%.*]] = or i1 [[TMP29]], [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP33:%.*]] = xor i1 [[TMP30]], [[TMP32]]
-; NOPRELINK-NEXT: [[TMP34:%.*]] = select afn i1 [[TMP33]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select afn i1 [[TMP33]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = call afn float @llvm.copysign.f32(float [[TMP34]], float [[TMP35]])
; NOPRELINK-NEXT: [[TMP37:%.*]] = select afn i1 [[TMP31]], float [[TMP36]], float [[TMP27]]
; NOPRELINK-NEXT: [[TMP38:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0x7FF8000000000000, float [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float +qnan, float [[TMP37]]
; NOPRELINK-NEXT: ret float [[TMP39]]
;
%pow = tail call afn float @_Z3powff(float %x, float %y)
@@ -3499,7 +3499,7 @@ define <2 x float> @test_pow_afn_v2f32_x_known_positive(<2 x float> nofpclass(ni
; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq <2 x float> [[TMP17]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq <2 x float> [[TMP17]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP19:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <2 x float> [[TMP2]], [[TMP19]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
@@ -3510,17 +3510,17 @@ define <2 x float> @test_pow_afn_v2f32_x_known_positive(<2 x float> nofpclass(ni
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP25]]
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> [[TMP26]], <2 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp afn oeq <2 x float> [[TMP28]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp afn oeq <2 x float> [[TMP28]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP31:%.*]] = or <2 x i1> [[TMP29]], [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP33:%.*]] = xor <2 x i1> [[TMP30]], [[TMP32]]
-; NOPRELINK-NEXT: [[TMP34:%.*]] = select afn <2 x i1> [[TMP33]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select afn <2 x i1> [[TMP33]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP35:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP36:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP34]], <2 x float> [[TMP35]])
; NOPRELINK-NEXT: [[TMP37:%.*]] = select afn <2 x i1> [[TMP31]], <2 x float> [[TMP36]], <2 x float> [[TMP27]]
; NOPRELINK-NEXT: [[TMP38:%.*]] = fcmp afn uno <2 x float> [[TMP4]], [[TMP2]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <2 x i1> [[TMP38]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <2 x i1> [[TMP38]], <2 x float> splat (float +qnan), <2 x float> [[TMP37]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP39]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
@@ -4224,14 +4224,14 @@ define float @test_pow_afn_f32__y_poison(float %x) {
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.copysign.f32(float [[TMP3]], float [[X]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], +inf
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.copysign.f32(float [[TMP9]], float [[X]])
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP8]], float [[TMP10]], float [[TMP4]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float 0x7FF8000000000000, float [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float +qnan, float [[TMP11]]
; NOPRELINK-NEXT: ret float [[TMP13]]
;
%pow = tail call afn float @_Z3powff(float %x, float poison)
@@ -4264,17 +4264,17 @@ define float @test_pow_afn_f32__y_3(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 3.0)
@@ -4318,17 +4318,17 @@ define float @test_pow_afn_f32__y_4(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 4.0)
@@ -4372,9 +4372,9 @@ define float @test_pow_afn_f32_nnan_ninf__y_4_5(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP21]], float [[TMP22]])
; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn i1 [[TMP20]], float [[TMP23]], float [[TMP19]]
@@ -4410,17 +4410,17 @@ define float @test_pow_afn_f32__y_5(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float +qnan, float [[TMP27]]
; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 5.0)
@@ -4465,19 +4465,19 @@ define float @test_pow_afn_f32__y_neg5(float %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], +inf
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -5.0)
@@ -4567,9 +4567,9 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
@@ -4605,9 +4605,9 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5_undef(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP15]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
@@ -4836,7 +4836,7 @@ define half @test_pow_afn_f16__y_3(half %x) {
;
; NOPRELINK-LABEL: define half @test_pow_afn_f16__y_3
; NOPRELINK-SAME: (half [[X:%.*]]) {
-; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 0xH4200)
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 3.000000e+00)
; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half 3.0)
@@ -4862,7 +4862,7 @@ define half @test_pow_afn_f16__y_4(half %x) {
;
; NOPRELINK-LABEL: define half @test_pow_afn_f16__y_4
; NOPRELINK-SAME: (half [[X:%.*]]) {
-; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 0xH4400)
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 4.000000e+00)
; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half 4.0)
@@ -4883,7 +4883,7 @@ define half @test_pow_afn_f16_nnan_ninf__y_4(half %x) {
define half @test_pow_afn_f16_nnan_ninf__y_4_5(half %x) {
; CHECK-LABEL: define half @test_pow_afn_f16_nnan_ninf__y_4_5
; CHECK-SAME: (half [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan ninf afn half @_Z3powDhDh(half [[X]], half 0xH4480)
+; CHECK-NEXT: [[POW:%.*]] = tail call nnan ninf afn half @_Z3powDhDh(half [[X]], half 4.500000e+00)
; CHECK-NEXT: ret half [[POW]]
;
%pow = tail call afn nnan ninf half @_Z3powDhDh(half %x, half 4.5)
@@ -4898,7 +4898,7 @@ define half @test_pow_afn_f16__y_5(half %x) {
;
; NOPRELINK-LABEL: define half @test_pow_afn_f16__y_5
; NOPRELINK-SAME: (half [[X:%.*]]) {
-; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 0xH4500)
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 5.000000e+00)
; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half 5.0)
@@ -4925,7 +4925,7 @@ define half @test_pow_afn_f16__y_neg5(half %x) {
;
; NOPRELINK-LABEL: define half @test_pow_afn_f16__y_neg5
; NOPRELINK-SAME: (half [[X:%.*]]) {
-; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 0xHC500)
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half -5.000000e+00)
; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half -5.0)
@@ -4938,7 +4938,7 @@ define half @test_pow_afn_f16_nnan_ninf__y_neg5(half %x) {
; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn half [[X]], [[X]]
; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn half [[__POWX2]], [[__POWX2]]
; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn half [[X]], [[__POWX21]]
-; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn half 0xH3C00, [[__POWPROD]]
+; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn half 1.000000e+00, [[__POWPROD]]
; CHECK-NEXT: ret half [[__1POWPROD]]
;
%pow = tail call afn nnan ninf half @_Z3powDhDh(half %x, half -5.0)
@@ -4983,7 +4983,7 @@ define <2 x half> @test_pow_afn_v2f16_nnan_ninf__y_4(<2 x half> %x) {
define <2 x half> @test_pow_afn_v2f16_nnan_ninf__y_4_5(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_pow_afn_v2f16_nnan_ninf__y_4_5
; CHECK-SAME: (<2 x half> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan ninf afn <2 x half> @_Z3powDv2_DhS_(<2 x half> [[X]], <2 x half> splat (half 0xH4480))
+; CHECK-NEXT: [[POW:%.*]] = tail call nnan ninf afn <2 x half> @_Z3powDv2_DhS_(<2 x half> [[X]], <2 x half> splat (half 4.500000e+00))
; CHECK-NEXT: ret <2 x half> [[POW]]
;
%pow = tail call afn nnan ninf <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> <half 4.5, half 4.5>)
@@ -5052,19 +5052,19 @@ define float @test_pow_afn_f32_known_integral_sitofp(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP27:%.*]] = xor i1 [[TMP24]], [[TMP26]]
-; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP30:%.*]] = call afn float @llvm.copysign.f32(float [[TMP28]], float [[TMP29]])
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP25]], float [[TMP30]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp afn uno float [[TMP4]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP33:%.*]] = select afn i1 [[TMP32]], float 0x7FF8000000000000, float [[TMP31]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = select afn i1 [[TMP32]], float +qnan, float [[TMP31]]
; NOPRELINK-NEXT: ret float [[TMP33]]
;
%y.cast = sitofp i32 %y to float
@@ -5140,14 +5140,14 @@ define float @test_pow_afn_nnan_f32_known_integral_sitofp(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP27:%.*]] = xor i1 [[TMP24]], [[TMP26]]
-; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan afn i1 [[TMP27]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan afn i1 [[TMP27]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP29:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP30:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP28]], float [[TMP29]])
; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP25]], float [[TMP30]], float [[TMP21]]
@@ -5189,16 +5189,16 @@ define float @test_pow_afn_ninf_f32_known_integral_sitofp(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp ninf afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp ninf afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select ninf afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select ninf afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp ninf afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp ninf afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], [[TMP23]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = select ninf afn i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select ninf afn i1 [[TMP24]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP26:%.*]] = select ninf afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP27:%.*]] = call ninf afn float @llvm.copysign.f32(float [[TMP25]], float [[TMP26]])
; NOPRELINK-NEXT: [[TMP28:%.*]] = select ninf afn i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp ninf afn uno float [[TMP4]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP30:%.*]] = select ninf afn i1 [[TMP29]], float 0x7FF8000000000000, float [[TMP28]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select ninf afn i1 [[TMP29]], float +qnan, float [[TMP28]]
; NOPRELINK-NEXT: ret float [[TMP30]]
;
%y.cast = sitofp i32 %y to float
@@ -5275,17 +5275,17 @@ define float @test_pow_afn_f32_known_integral_uitofp(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP24]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP25]], float [[TMP28]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[TMP4]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float +qnan, float [[TMP29]]
; NOPRELINK-NEXT: ret float [[TMP31]]
;
%y.cast = uitofp i32 %y to float
@@ -5361,19 +5361,19 @@ define float @test_pow_afn_nnan_f32_known_integral_uitofp_i256(float %x, i256 %y
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float +qnan, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp nnan afn oeq float [[TMP23]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn olt float [[TMP23]], 1.000000e+00
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan afn i1 [[TMP25]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP27:%.*]] = select nnan afn i1 [[TMP24]], float 1.000000e+00, float [[TMP26]]
; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan afn i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP29:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp nnan afn oeq float [[TMP29]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp nnan afn oeq float [[TMP29]], +inf
; NOPRELINK-NEXT: [[TMP31:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP32:%.*]] = or i1 [[TMP30]], [[TMP31]]
-; NOPRELINK-NEXT: [[TMP33:%.*]] = select nnan afn i1 [[TMP31]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP33:%.*]] = select nnan afn i1 [[TMP31]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP35:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP33]], float [[TMP34]])
; NOPRELINK-NEXT: [[TMP36:%.*]] = select nnan afn i1 [[TMP32]], float [[TMP35]], float [[TMP28]]
@@ -5415,9 +5415,9 @@ define float @test_pow_afn_nnan_f32_known_integral_sitofp_i256(float %x, i256 %y
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
@@ -5428,12 +5428,12 @@ define float @test_pow_afn_nnan_f32_known_integral_sitofp_i256(float %x, i256 %y
; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], +inf
; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
@@ -5605,17 +5605,17 @@ define <2 x float> @test_pow_afn_v2f32_known_integral_uitofp(<2 x float> %x, <2
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float +qnan), <2 x float> [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
; NOPRELINK-NEXT: [[TMP25:%.*]] = or <2 x i1> [[TMP23]], [[TMP24]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> [[TMP28]], <2 x float> [[TMP21]]
; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[TMP4]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float +qnan), <2 x float> [[TMP29]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
@@ -5727,17 +5727,17 @@ define float @test_pow_afn_f32_known_positive_x__known_integral_sitofp(float nof
; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq float [[TMP17]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq float [[TMP17]], +inf
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = or i1 [[TMP18]], [[TMP19]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP22:%.*]] = xor i1 [[TMP19]], [[TMP21]]
-; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = call afn float @llvm.copysign.f32(float [[TMP23]], float [[TMP24]])
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP20]], float [[TMP25]], float [[TMP16]]
; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn uno float [[TMP4]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float 0x7FF8000000000000, float [[TMP26]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float +qnan, float [[TMP26]]
; NOPRELINK-NEXT: ret float [[TMP28]]
;
%y.cast = sitofp i32 %y to float
@@ -5891,19 +5891,19 @@ define float @test_pow_afn_f32__y_known_integral_trunc(float %x, float nofpclass
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float +qnan, float [[TMP16]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], +inf
; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP27:%.*]] = xor i1 [[TMP24]], [[TMP26]]
-; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
; NOPRELINK-NEXT: [[TMP30:%.*]] = call afn float @llvm.copysign.f32(float [[TMP28]], float [[TMP29]])
; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP25]], float [[TMP30]], float [[TMP21]]
; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp afn uno float [[TMP4]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP33:%.*]] = select afn i1 [[TMP32]], float 0x7FF8000000000000, float [[TMP31]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = select afn i1 [[TMP32]], float +qnan, float [[TMP31]]
; NOPRELINK-NEXT: ret float [[TMP33]]
;
%y = call float @llvm.trunc.f32(float %y.arg)
@@ -6011,7 +6011,7 @@ define float @test_pow_f32__y_known_integral_nearbyint_assume(float %x, float %y
; PRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
; PRELINK-NEXT: [[Y_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y]])
-; PRELINK-NEXT: [[Y_IS_FINITE:%.*]] = fcmp one float [[Y_FABS]], 0x7FF0000000000000
+; PRELINK-NEXT: [[Y_IS_FINITE:%.*]] = fcmp one float [[Y_FABS]], +inf
; PRELINK-NEXT: call void @llvm.assume(i1 [[Y_IS_FINITE]])
; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
@@ -6021,7 +6021,7 @@ define float @test_pow_f32__y_known_integral_nearbyint_assume(float %x, float %y
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
; NOPRELINK-NEXT: [[Y_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y]])
-; NOPRELINK-NEXT: [[Y_IS_FINITE:%.*]] = fcmp one float [[Y_FABS]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[Y_IS_FINITE:%.*]] = fcmp one float [[Y_FABS]], +inf
; NOPRELINK-NEXT: call void @llvm.assume(i1 [[Y_IS_FINITE]])
; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
; NOPRELINK-NEXT: ret float [[POW]]
@@ -6038,7 +6038,7 @@ define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input(float %x
; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input
; PRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
; PRELINK-NEXT: [[Y_ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y_ARG]])
-; PRELINK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[Y_ARG_FABS]], 0x7FF0000000000000
+; PRELINK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[Y_ARG_FABS]], +inf
; PRELINK-NEXT: call void @llvm.assume(i1 [[IS_FINITE]])
; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
@@ -6048,7 +6048,7 @@ define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input(float %x
; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
; NOPRELINK-NEXT: [[Y_ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y_ARG]])
-; NOPRELINK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[Y_ARG_FABS]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[Y_ARG_FABS]], +inf
; NOPRELINK-NEXT: call void @llvm.assume(i1 [[IS_FINITE]])
; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll
index 70b3f48728b13..162a9de2f10aa 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll
@@ -495,10 +495,10 @@ define float @test__pown_fast_afn_f32__neg2(float %x) #0 {
; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], +inf
; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float 0.000000e+00, float [[TMP4]]
-; CHECK-NEXT: [[CALL:%.*]] = select i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP8]]
+; CHECK-NEXT: [[CALL:%.*]] = select i1 [[TMP7]], float +inf, float [[TMP8]]
; CHECK-NEXT: ret float [[CALL]]
;
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
index b4182ccbf77a4..8fb5df464b7e8 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
@@ -616,12 +616,12 @@ define float @test_pown_afn_f32(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[TMP1]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP8]])
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], +inf
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP15:%.*]] = xor i1 [[TMP12]], [[TMP14]]
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[TMP1]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.copysign.f32(float [[TMP16]], float [[TMP17]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP13]], float [[TMP18]], float [[TMP9]]
@@ -654,12 +654,12 @@ define <2 x float> @test_pown_afn_v2f32(<2 x float> %x, <2 x i32> %y) {
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP1]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP8]])
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP10]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP10]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[TMP1]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = or <2 x i1> [[TMP11]], [[TMP12]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP15:%.*]] = xor <2 x i1> [[TMP12]], [[TMP14]]
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[TMP1]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP16]], <2 x float> [[TMP17]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> [[TMP18]], <2 x float> [[TMP9]]
@@ -1133,12 +1133,12 @@ define float @test_pown_afn_f32__x_known_positive(float nofpclass(ninf nsub nnor
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[TMP1]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP8]])
; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], +inf
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP15:%.*]] = xor i1 [[TMP12]], [[TMP14]]
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[TMP1]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.copysign.f32(float [[TMP16]], float [[TMP17]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP13]], float [[TMP18]], float [[TMP9]]
@@ -1185,9 +1185,9 @@ define float @test_pown_afn_f32__x_known_positive__y_4(float nofpclass(ninf nsub
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], +inf
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float 0x7FF0000000000000, float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float +inf, float [[TMP4]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP7]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: ret float [[TMP9]]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
index d65fcdcc4d3fe..53ed5e311208f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
@@ -54,31 +54,31 @@ define float @test_powr_afn_f32(float %x, float %y) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt float [[Y]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[Y]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float +qnan, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.fabs.f32(float [[Y]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq float [[TMP18]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq float [[TMP18]], +inf
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une float [[TMP2]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt float [[TMP2]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float [[TMP8]], float [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP21]], float [[TMP23]], float [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno float [[TMP2]], [[Y]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0x7FF8000000000000, float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float +qnan, float [[TMP24]]
; NOPRELINK-NEXT: ret float [[TMP26]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y)
@@ -94,24 +94,24 @@ define float @test_powr_afn_f32_nnan(float %x, float %y) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul nnan afn float [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan afn olt float [[Y]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan afn i1 [[TMP7]], float +inf, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP7]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[Y]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float +qnan, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp nnan afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp nnan afn une float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select nnan afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call nnan afn float @llvm.fabs.f32(float [[Y]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn oeq float [[TMP18]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn oeq float [[TMP18]], +inf
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn une float [[TMP2]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan afn olt float [[TMP2]], 1.000000e+00
@@ -132,31 +132,31 @@ define <2 x float> @test_powr_afn_v2f32(<2 x float> %x, <2 x float> %y) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32
; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <2 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +inf), <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> splat (float +qnan), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP11]], <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <2 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <2 x i1> [[TMP16]], <2 x float> [[TMP9]], <2 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <2 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <2 x float> [[TMP18]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <2 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <2 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <2 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> [[TMP8]], <2 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP21]], <2 x float> [[TMP23]], <2 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <2 x float> [[TMP2]], [[Y]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> splat (float +qnan), <2 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP26]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
@@ -172,31 +172,31 @@ define <3 x float> @test_powr_afn_v3f32(<3 x float> %x, <3 x float> %y) {
; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32
; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float +qnan), <3 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <3 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> splat (float 0x7FF0000000000000), <3 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> splat (float +inf), <3 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> zeroinitializer, <3 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <3 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <3 x i1> [[TMP10]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <3 x i1> [[TMP10]], <3 x float> splat (float +qnan), <3 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[TMP11]], <3 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <3 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <3 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <3 x i1> [[TMP16]], <3 x float> [[TMP9]], <3 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[Y]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <3 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <3 x float> [[TMP18]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <3 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <3 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <3 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <3 x i1> [[TMP22]], <3 x float> [[TMP8]], <3 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <3 x i1> [[TMP21]], <3 x float> [[TMP23]], <3 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <3 x float> [[TMP2]], [[Y]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <3 x i1> [[TMP25]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <3 x i1> [[TMP25]], <3 x float> splat (float +qnan), <3 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP26]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> %y)
@@ -212,31 +212,31 @@ define <4 x float> @test_powr_afn_v4f32(<4 x float> %x, <4 x float> %y) {
; NOPRELINK-LABEL: define <4 x float> @test_powr_afn_v4f32
; NOPRELINK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <4 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <4 x i1> [[TMP1]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <4 x i1> [[TMP1]], <4 x float> splat (float +qnan), <4 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <4 x float> @llvm.log2.v4f32(<4 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <4 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <4 x float> @llvm.exp2.v4f32(<4 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <4 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> splat (float 0x7FF0000000000000), <4 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> zeroinitializer, <4 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> splat (float +inf), <4 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> zeroinitializer, <4 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <4 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <4 x i1> [[TMP10]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <4 x i1> [[TMP10]], <4 x float> splat (float +qnan), <4 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <4 x i1> [[TMP12]], <4 x float> [[TMP11]], <4 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <4 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <4 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <4 x i1> [[TMP16]], <4 x float> [[TMP9]], <4 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[Y]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <4 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <4 x float> [[TMP18]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <4 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <4 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <4 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <4 x i1> [[TMP22]], <4 x float> [[TMP8]], <4 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <4 x i1> [[TMP21]], <4 x float> [[TMP23]], <4 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <4 x float> [[TMP2]], [[Y]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <4 x i1> [[TMP25]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <4 x i1> [[TMP25]], <4 x float> splat (float +qnan), <4 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <4 x float> [[TMP26]]
;
%powr = tail call afn <4 x float> @_Z4powrDv4_fS_(<4 x float> %x, <4 x float> %y)
@@ -252,31 +252,31 @@ define <8 x float> @test_powr_afn_v8f32(<8 x float> %x, <8 x float> %y) {
; NOPRELINK-LABEL: define <8 x float> @test_powr_afn_v8f32
; NOPRELINK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <8 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <8 x i1> [[TMP1]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <8 x i1> [[TMP1]], <8 x float> splat (float +qnan), <8 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <8 x float> @llvm.log2.v8f32(<8 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <8 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <8 x float> @llvm.exp2.v8f32(<8 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <8 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> splat (float 0x7FF0000000000000), <8 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> zeroinitializer, <8 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> splat (float +inf), <8 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> zeroinitializer, <8 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <8 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <8 x i1> [[TMP10]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <8 x i1> [[TMP10]], <8 x float> splat (float +qnan), <8 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <8 x i1> [[TMP12]], <8 x float> [[TMP11]], <8 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <8 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <8 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <8 x i1> [[TMP16]], <8 x float> [[TMP9]], <8 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[Y]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <8 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <8 x float> [[TMP18]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <8 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <8 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <8 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <8 x i1> [[TMP22]], <8 x float> [[TMP8]], <8 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <8 x i1> [[TMP21]], <8 x float> [[TMP23]], <8 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <8 x float> [[TMP2]], [[Y]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <8 x i1> [[TMP25]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <8 x i1> [[TMP25]], <8 x float> splat (float +qnan), <8 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <8 x float> [[TMP26]]
;
%powr = tail call afn <8 x float> @_Z4powrDv8_fS_(<8 x float> %x, <8 x float> %y)
@@ -292,31 +292,31 @@ define <16 x float> @test_powr_afn_v16f32(<16 x float> %x, <16 x float> %y) {
; NOPRELINK-LABEL: define <16 x float> @test_powr_afn_v16f32
; NOPRELINK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <16 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <16 x i1> [[TMP1]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <16 x i1> [[TMP1]], <16 x float> splat (float +qnan), <16 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <16 x float> @llvm.log2.v16f32(<16 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <16 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <16 x float> @llvm.exp2.v16f32(<16 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <16 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> splat (float 0x7FF0000000000000), <16 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> zeroinitializer, <16 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> splat (float +inf), <16 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> zeroinitializer, <16 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <16 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <16 x i1> [[TMP10]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <16 x i1> [[TMP10]], <16 x float> splat (float +qnan), <16 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <16 x i1> [[TMP12]], <16 x float> [[TMP11]], <16 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <16 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <16 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <16 x i1> [[TMP16]], <16 x float> [[TMP9]], <16 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[Y]])
-; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <16 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <16 x float> [[TMP18]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <16 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <16 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <16 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <16 x i1> [[TMP22]], <16 x float> [[TMP8]], <16 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <16 x i1> [[TMP21]], <16 x float> [[TMP23]], <16 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <16 x float> [[TMP2]], [[Y]]
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <16 x i1> [[TMP25]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <16 x i1> [[TMP25]], <16 x float> splat (float +qnan), <16 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <16 x float> [[TMP26]]
;
%powr = tail call afn <16 x float> @_Z4powrDv16_fS_(<16 x float> %x, <16 x float> %y)
@@ -782,13 +782,13 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 0.000000e+00, float -0.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn ueq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +qnan), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP8]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.0, float -0.0>)
@@ -822,17 +822,17 @@ define float @test_powr_afn_f32_0.5(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_0.5
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 5.000000e-01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float +inf, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0.5)
@@ -848,17 +848,17 @@ define float @test_powr_afn_f32_neg0.5(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg0.5
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -5.000000e-01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -0.5)
@@ -874,17 +874,17 @@ define <2 x float> @test_powr_afn_v2f32_0.5(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_0.5
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 5.000000e-01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float +inf), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float 0.5>)
@@ -900,17 +900,17 @@ define <2 x float> @test_powr_afn_v2f32_neg0.5(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg0.5
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -5.000000e-01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +inf), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -0.5, float -0.5>)
@@ -926,17 +926,17 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 5.000000e-01, float -5.000000e-01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float +inf>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float +inf, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float -0.5>)
@@ -952,17 +952,17 @@ define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef(<3 x float> %x, <3 x flo
; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef
; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float +qnan), <3 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[TMP4]], <float 5.000000e-01, float poison, float 5.000000e-01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <3 x i1> [[TMP9]], <3 x float> <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>, <3 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <3 x i1> [[TMP9]], <3 x float> <float +inf, float poison, float +inf>, <3 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <3 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <3 x i1> [[TMP11]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <3 x i1> [[TMP11]], <3 x float> splat (float +qnan), <3 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP12]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float 0.5, float poison, float 0.5>)
@@ -978,17 +978,17 @@ define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef(<3 x float> %x, <3 x
; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef
; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float +qnan), <3 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[TMP4]], <float -5.000000e-01, float poison, float -5.000000e-01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>, <3 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> <float +inf, float poison, float +inf>, <3 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <3 x i1> [[TMP9]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <3 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <3 x i1> [[TMP11]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <3 x i1> [[TMP11]], <3 x float> splat (float +qnan), <3 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP12]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float -0.5, float poison, float -0.5>)
@@ -1042,17 +1042,17 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.000000e+00, float -1.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float +inf>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float +inf, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 1.0, float -1.0>)
@@ -1097,17 +1097,17 @@ define float @test_powr_afn_f32_neg2.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg2.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -2.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -2.0)
@@ -1133,17 +1133,17 @@ define <2 x float> @test_powr_afn_v2f32_neg2.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg2.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -2.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +inf), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -2.0, float -2.0>)
@@ -1159,17 +1159,17 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 2.000000e+00, float -2.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float +inf>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float +inf, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 2.0, float -2.0>)
@@ -1185,17 +1185,17 @@ define float @test_powr_afn_f32_3.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_3.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 3.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float +inf, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 3.0)
@@ -1211,17 +1211,17 @@ define float @test_powr_afn_f32_neg3.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg3.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -3.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -3.0)
@@ -1237,17 +1237,17 @@ define <2 x float> @test_powr_afn_v2f32_3.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 3.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float +inf), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float 3.0>)
@@ -1263,17 +1263,17 @@ define <2 x float> @test_powr_afn_v2f32_neg3.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -3.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +inf), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -3.0, float -3.0>)
@@ -1289,17 +1289,17 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 3.000000e+00, float -3.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float +inf>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float +inf, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float -3.0>)
@@ -1309,23 +1309,23 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0(<2 x float> %x) {
define float @test_powr_afn_f32_3.99(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_3.99
; PRELINK-SAME: (float [[X:%.*]]) {
-; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 0x400FEB8520000000)
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 3.990000e+00)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_3.99
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 0x400FEB8520000000
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 3.990000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float +inf, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0x400FEB8520000000)
@@ -1335,23 +1335,23 @@ define float @test_powr_afn_f32_3.99(float %x) {
define float @test_powr_afn_f32_neg3.99(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_neg3.99
; PRELINK-SAME: (float [[X:%.*]]) {
-; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 0xC00FEB8520000000)
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -3.990000e+00)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg3.99
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 0xC00FEB8520000000
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -3.990000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0xC00FEB8520000000)
@@ -1361,23 +1361,23 @@ define float @test_powr_afn_f32_neg3.99(float %x) {
define <2 x float> @test_powr_afn_v2f32_3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
-; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0x400FEB8520000000))
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 3.990000e+00))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 0x400FEB8520000000)
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 3.990000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float +inf), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0x400FEB8520000000>)
@@ -1387,23 +1387,23 @@ define <2 x float> @test_powr_afn_v2f32_3.99(<2 x float> %x) {
define <2 x float> @test_powr_afn_v2f32_neg3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
-; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0xC00FEB8520000000))
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -3.990000e+00))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 0xC00FEB8520000000)
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -3.990000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +inf), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0xC00FEB8520000000, float 0xC00FEB8520000000>)
@@ -1413,23 +1413,23 @@ define <2 x float> @test_powr_afn_v2f32_neg3.99(<2 x float> %x) {
define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
-; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 3.990000e+00, float -3.990000e+00>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 0x400FEB8520000000, float 0xC00FEB8520000000>
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 3.990000e+00, float -3.990000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float +inf>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float +inf, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
@@ -1445,17 +1445,17 @@ define float @test_powr_afn_f32_8.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_8.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 8.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float +inf, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 8.0)
@@ -1471,17 +1471,17 @@ define float @test_powr_afn_f32_neg8.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg8.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -8.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -8.0)
@@ -1497,17 +1497,17 @@ define <2 x float> @test_powr_afn_v2f32_8.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_8.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 8.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float +inf), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float 8.0>)
@@ -1523,17 +1523,17 @@ define <2 x float> @test_powr_afn_v2f32_neg8.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg8.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -8.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +inf), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -8.0, float -8.0>)
@@ -1549,17 +1549,17 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 8.000000e+00, float -8.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float +inf>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float +inf, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float -8.0>)
@@ -1575,17 +1575,17 @@ define float @test_powr_afn_f32_12.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_12.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 1.200000e+01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float +inf, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 12.0)
@@ -1601,17 +1601,17 @@ define float @test_powr_afn_f32_neg12.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg12.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -1.200000e+01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -12.0)
@@ -1627,17 +1627,17 @@ define <2 x float> @test_powr_afn_v2f32_12.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_12.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 1.200000e+01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float +inf), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float 12.0>)
@@ -1653,17 +1653,17 @@ define <2 x float> @test_powr_afn_v2f32_neg12.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg12.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -1.200000e+01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +inf), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -12.0, float -12.0>)
@@ -1679,17 +1679,17 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.200000e+01, float -1.200000e+01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float +inf>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float +inf, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float -12.0>)
@@ -1705,17 +1705,17 @@ define float @test_powr_afn_f32_13.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_13.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 1.300000e+01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float +inf, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 13.0)
@@ -1731,17 +1731,17 @@ define float @test_powr_afn_f32_neg13.0(float %x) {
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg13.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -1.300000e+01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -13.0)
@@ -1757,17 +1757,17 @@ define <2 x float> @test_powr_afn_v2f32_13.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_13.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 1.300000e+01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float +inf), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 13.0>)
@@ -1783,17 +1783,17 @@ define <2 x float> @test_powr_afn_v2f32_neg13.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg13.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -1.300000e+01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +inf), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -13.0, float -13.0>)
@@ -1809,17 +1809,17 @@ define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0(<2 x float> %x) {
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.300000e+01, float -1.300000e+01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float +inf>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float +inf, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float +qnan), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float -13.0>)
@@ -1839,18 +1839,18 @@ define float @test_powr_afn_f32_nnan_x_known_positive(float nofpclass(ninf nnorm
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan afn float [[Y]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan afn olt float [[Y]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan afn i1 [[TMP5]], float 0x7FF0000000000000, float 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan afn i1 [[TMP5]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan afn i1 [[TMP5]], float +inf, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan afn i1 [[TMP5]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan afn oeq float [[Y]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP8]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP8]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float [[TMP9]], float [[TMP4]]
-; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[X]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[X]], +inf
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP7]], float [[TMP11]]
; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.fabs.f32(float [[Y]])
-; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq float [[TMP16]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq float [[TMP16]], +inf
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[X]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP19:%.*]] = and i1 [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn olt float [[X]], 1.000000e+00
@@ -1887,18 +1887,18 @@ define <2 x float> @test_powr_afn_v2f32_nnan_x_known_positive(<2 x float> nofpcl
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan afn <2 x float> [[Y]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan afn olt <2 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> splat (float +inf), <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan afn oeq <2 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn <2 x i1> [[TMP8]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn <2 x i1> [[TMP8]], <2 x float> splat (float +qnan), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn <2 x i1> [[TMP10]], <2 x float> [[TMP9]], <2 x float> [[TMP4]]
-; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP12]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP7]], <2 x float> [[TMP11]]
; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
-; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP16]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP16]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une <2 x float> [[X]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP19:%.*]] = and <2 x i1> [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn olt <2 x float> [[X]], splat (float 1.000000e+00)
@@ -1945,25 +1945,25 @@ define float @test_powr_afn_f32_x_known_positive(float nofpclass(ninf nnorm nsub
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul afn float [[Y]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp afn olt float [[Y]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP6:%.*]] = select afn i1 [[TMP5]], float 0x7FF0000000000000, float 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[TMP5]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select afn i1 [[TMP5]], float +inf, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[TMP5]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[Y]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP8]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP8]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float [[TMP9]], float [[TMP4]]
-; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[X]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[X]], +inf
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP7]], float [[TMP11]]
; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.fabs.f32(float [[Y]])
-; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn oeq float [[TMP16]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn oeq float [[TMP16]], +inf
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[X]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP19:%.*]] = and i1 [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn olt float [[X]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float [[TMP6]], float [[TMP7]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = select afn i1 [[TMP19]], float [[TMP21]], float [[TMP15]]
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn uno float [[X]], [[Y]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP23]], float 0x7FF8000000000000, float [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP23]], float +qnan, float [[TMP22]]
; NOPRELINK-NEXT: ret float [[TMP24]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y)
@@ -1993,25 +1993,25 @@ define <2 x float> @test_powr_afn_v2f32_x_known_positive(<2 x float> nofpclass(n
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul afn <2 x float> [[Y]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp afn olt <2 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP6:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> splat (float +inf), <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP8]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP8]], <2 x float> splat (float +qnan), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> [[TMP9]], <2 x float> [[TMP4]]
-; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP12]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP7]], <2 x float> [[TMP11]]
; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
-; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn oeq <2 x float> [[TMP16]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn oeq <2 x float> [[TMP16]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[X]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP19:%.*]] = and <2 x i1> [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn olt <2 x float> [[X]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> [[TMP6]], <2 x float> [[TMP7]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = select afn <2 x i1> [[TMP19]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn uno <2 x float> [[X]], [[Y]]
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> splat (float +qnan), <2 x float> [[TMP22]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP24]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
@@ -2041,24 +2041,24 @@ define float @test_powr_afn_f32_known_integral_sitofp(float %x, i32 %y) {
; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[Y_CAST]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +inf, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[Y]], 0
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float +qnan, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP15:%.*]] = icmp ne i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP17]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float +qnan, float [[TMP17]]
; NOPRELINK-NEXT: ret float [[TMP19]]
;
%y.cast = sitofp i32 %y to float
@@ -2103,21 +2103,21 @@ define float @test_powr_afn_f32_known_integral_uitofp(float %x, i32 %y) {
; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float +qnan, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[Y_CAST]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[Y]], 0
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF8000000000000, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float +qnan, float 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float [[TMP8]], float [[TMP6]]
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP2]], +inf
; NOPRELINK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = select afn i1 [[TMP13]], float 0x7FF0000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select afn i1 [[TMP13]], float +inf, float [[TMP10]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: ret float [[TMP16]]
;
%y.cast = uitofp i32 %y to float
@@ -2176,21 +2176,21 @@ define <2 x float> @test_powr_afn_v2f32_known_integral_uitofp(<2 x float> %x, <2
; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float +qnan), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], [[Y_CAST]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float +qnan), <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> [[TMP8]], <2 x float> [[TMP6]]
-; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP12:%.*]] = icmp ne <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = and <2 x i1> [[TMP11]], [[TMP12]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> splat (float +inf), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP16]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
index 337ccb4a2d0e9..7aa35144627c2 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
@@ -296,7 +296,7 @@ define half @test_rootn_f16_3(half %x) {
define half @test_rootn_f16_neg1(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_neg1(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[__ROOTN2DIV:%.*]] = fdiv half 0xH3C00, [[X]]
+; CHECK-NEXT: [[__ROOTN2DIV:%.*]] = fdiv half 1.000000e+00, [[X]]
; CHECK-NEXT: ret half [[__ROOTN2DIV]]
;
%call = tail call half @_Z5rootnDhi(half %x, i32 -1)
@@ -307,7 +307,7 @@ define half @test_rootn_f16_neg2(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_neg2(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.sqrt.f16(half [[X]])
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract half 0xH3C00, [[TMP1]], !fpmath [[META1]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract half 1.000000e+00, [[TMP1]], !fpmath [[META1]]
; CHECK-NEXT: ret half [[__ROOTN2RSQRT]]
;
%call = tail call half @_Z5rootnDhi(half %x, i32 -2)
@@ -366,7 +366,7 @@ define <2 x half> @test_rootn_v2f16_2(<2 x half> %x) {
define <2 x half> @test_rootn_v2f16_neg1(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_neg1(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
-; CHECK-NEXT: [[__ROOTN2DIV:%.*]] = fdiv <2 x half> splat (half 0xH3C00), [[X]]
+; CHECK-NEXT: [[__ROOTN2DIV:%.*]] = fdiv <2 x half> splat (half 1.000000e+00), [[X]]
; CHECK-NEXT: ret <2 x half> [[__ROOTN2DIV]]
;
%call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 -1, i32 -1>)
@@ -377,7 +377,7 @@ define <2 x half> @test_rootn_v2f16_neg2(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_neg2(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> [[X]])
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract <2 x half> splat (half 0xH3C00), [[TMP1]], !fpmath [[META1]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = fdiv contract <2 x half> splat (half 1.000000e+00), [[TMP1]], !fpmath [[META1]]
; CHECK-NEXT: ret <2 x half> [[__ROOTN2RSQRT]]
;
%call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 -2, i32 -2>)
@@ -1020,12 +1020,12 @@ define float @test_rootn_afn_f32(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], +inf
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
-; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
@@ -1033,7 +1033,7 @@ define float @test_rootn_afn_f32(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[DOTNOT]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
-; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP18]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float +qnan, float [[TMP18]]
; NOPRELINK-NEXT: ret float [[TMP23]]
;
entry:
@@ -1062,12 +1062,12 @@ define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) {
; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP5]], <2 x float> [[TMP7]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], splat (float +inf)
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = or <2 x i1> [[TMP10]], [[TMP11]]
; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP14:%.*]] = xor <2 x i1> [[TMP11]], [[TMP13]]
-; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP15]], <2 x float> [[TMP16]])
; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP17]], <2 x float> [[TMP8]]
@@ -1075,7 +1075,7 @@ define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) {
; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[DOTNOT]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP22:%.*]] = or <2 x i1> [[TMP20]], [[TMP21]]
-; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP18]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> splat (float +qnan), <2 x float> [[TMP18]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP23]]
;
entry:
@@ -1154,7 +1154,7 @@ define float @test_rootn_afn_nnan_ninf_f32(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP11:%.*]] = xor i1 [[TMP9]], [[TMP10]]
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[TMP11]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[TMP11]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP12]], float [[TMP13]])
; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan ninf afn i1 [[TMP9]], float [[TMP14]], float [[TMP8]]
@@ -1162,7 +1162,7 @@ define float @test_rootn_afn_nnan_ninf_f32(float %x, i32 %y) {
; NOPRELINK-NEXT: [[TMP17:%.*]] = and i1 [[TMP16]], [[DOTNOT]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP19:%.*]] = or i1 [[TMP17]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn i1 [[TMP19]], float 0x7FF8000000000000, float [[TMP15]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn i1 [[TMP19]], float +qnan, float [[TMP15]]
; NOPRELINK-NEXT: ret float [[TMP20]]
;
entry:
@@ -1193,7 +1193,7 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y)
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = xor <2 x i1> [[TMP9]], [[TMP10]]
-; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn <2 x i1> [[TMP11]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn <2 x i1> [[TMP11]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan ninf afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP12]], <2 x float> [[TMP13]])
; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan ninf afn <2 x i1> [[TMP9]], <2 x float> [[TMP14]], <2 x float> [[TMP8]]
@@ -1201,7 +1201,7 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y)
; NOPRELINK-NEXT: [[TMP17:%.*]] = and <2 x i1> [[TMP16]], [[DOTNOT]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP19:%.*]] = or <2 x i1> [[TMP17]], [[TMP18]]
-; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn <2 x i1> [[TMP19]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP15]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn <2 x i1> [[TMP19]], <2 x float> splat (float +qnan), <2 x float> [[TMP15]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP20]]
;
entry:
@@ -1290,12 +1290,12 @@ define float @test_rootn_fast_f32_strictfp(float %x, i32 %y) #1 {
; NOPRELINK-NEXT: [[TMP7:%.*]] = select fast i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
; NOPRELINK-NEXT: [[TMP8:%.*]] = call fast float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]]) #[[ATTR0]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]
-; NOPRELINK-NEXT: [[TMP10:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP9]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP9]], float +inf, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
-; NOPRELINK-NEXT: [[TMP15:%.*]] = select fast i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select fast i1 [[TMP14]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP16:%.*]] = select fast i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = call fast float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]]) #[[ATTR0]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = select fast i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
@@ -1303,7 +1303,7 @@ define float @test_rootn_fast_f32_strictfp(float %x, i32 %y) #1 {
; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[DOTNOT]]
; NOPRELINK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
-; NOPRELINK-NEXT: [[TMP23:%.*]] = select fast i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP18]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select fast i1 [[TMP22]], float +qnan, float [[TMP18]]
; NOPRELINK-NEXT: ret float [[TMP23]]
;
entry:
@@ -1335,11 +1335,11 @@ define float @test_rootn_afn_nnan_ninf_f32__y_3(float %x) {
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0x3FD5555560000000
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], f0x3EAAAAAB
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT: ret float [[TMP9]]
@@ -1358,11 +1358,11 @@ define float @test_rootn_afn_nnan_ninf_f32__y_neg3(float %x) {
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFD5555560000000
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], f0xBEAAAAAB
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
; NOPRELINK-NEXT: ret float [[TMP9]]
@@ -1386,7 +1386,7 @@ define float @test_rootn_afn_nnan_ninf_f32__y_4(float %x) {
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float 0.000000e+00, float [[TMP4]]
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT: ret float [[TMP8]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 4)
@@ -1406,9 +1406,9 @@ define float @test_rootn_afn_nnan_ninf_f32__y_neg4(float %x) {
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -2.500000e-01
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float +inf
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT: ret float [[TMP8]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -4)
@@ -1425,11 +1425,11 @@ define float @test_rootn_afn_nnan_ninf_f32__y_5(float %x) {
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0x3FC99999A0000000
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 2.000000e-01
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT: ret float [[TMP9]]
@@ -1448,11 +1448,11 @@ define float @test_rootn_afn_nnan_ninf_f32__y_neg5(float %x) {
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFC99999A0000000
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -2.000000e-01
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
; NOPRELINK-NEXT: ret float [[TMP9]]
@@ -1471,11 +1471,11 @@ define float @test_rootn_afn_nnan_ninf_f32__y_7(float %x) {
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0x3FC24924A0000000
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], f0x3E124925
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT: ret float [[TMP9]]
@@ -1494,11 +1494,11 @@ define float @test_rootn_afn_nnan_ninf_f32__y_neg7(float %x) {
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFC24924A0000000
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], f0xBE124925
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
; NOPRELINK-NEXT: ret float [[TMP9]]
@@ -1522,7 +1522,7 @@ define float @test_rootn_afn_nnan_ninf_f32__y_8(float %x) {
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float 0.000000e+00, float [[TMP4]]
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT: ret float [[TMP8]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 8)
@@ -1542,9 +1542,9 @@ define float @test_rootn_afn_nnan_ninf_f32__y_neg8(float %x) {
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -1.250000e-01
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float +inf
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT: ret float [[TMP8]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -8)
@@ -1563,11 +1563,11 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(<2 x float> %x) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 0x3FD5555560000000)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float f0x3EAAAAAB)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP8]], <2 x float> [[TMP5]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP9]]
@@ -1594,7 +1594,7 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> [[TMP4]]
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float +qnan), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP8]]
;
entry:
@@ -1614,11 +1614,11 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(<2 x float> %x) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 0xBFD5555560000000)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float f0xBEAAAAAB)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP5]], <2 x float> [[TMP8]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP9]]
@@ -1643,9 +1643,9 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float -2.500000e-01)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> [[TMP4]], <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> [[TMP4]], <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float +qnan), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP8]]
;
entry:
@@ -1665,11 +1665,11 @@ define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(<2 x float> %x) {
; NOPRELINK-NEXT: entry:
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 0x3FC99999A0000000)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 2.000000e-01)
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP8]], <2 x float> [[TMP5]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP9]]
@@ -1712,17 +1712,17 @@ define float @test_rootn_afn_f32__x_known_positive(float nofpclass(ninf nsub nno
; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], +inf
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
-; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[Y]], 0
-; NOPRELINK-NEXT: [[TMP20:%.*]] = select afn i1 [[TMP19]], float 0x7FF8000000000000, float [[TMP18]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = select afn i1 [[TMP19]], float +qnan, float [[TMP18]]
; NOPRELINK-NEXT: ret float [[TMP20]]
;
entry:
@@ -1752,12 +1752,12 @@ define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(float nofpclass(nin
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP10:%.*]] = xor i1 [[TMP8]], [[TMP9]]
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan ninf afn i1 [[TMP10]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan ninf afn i1 [[TMP10]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT: [[TMP13:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP11]], float [[TMP12]])
; NOPRELINK-NEXT: [[TMP14:%.*]] = select nnan ninf afn i1 [[TMP8]], float [[TMP13]], float [[TMP7]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[Y]], 0
-; NOPRELINK-NEXT: [[TMP16:%.*]] = select nnan ninf afn i1 [[TMP15]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select nnan ninf afn i1 [[TMP15]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: ret float [[TMP16]]
;
entry:
@@ -1781,9 +1781,9 @@ define float @test_rootn_afn_f32__x_known_positive__y_4(float nofpclass(ninf nsu
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], +inf
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float 0x7FF0000000000000, float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float +inf, float [[TMP4]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP7]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: ret float [[TMP9]]
;
@@ -1838,12 +1838,12 @@ define float @test_fast_rootn_f32_y_known_even(float %x, i32 %y.arg) {
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP8:%.*]] = xor i1 [[TMP6]], [[TMP7]]
-; NOPRELINK-NEXT: [[TMP9:%.*]] = select fast i1 [[TMP8]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select fast i1 [[TMP8]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP10:%.*]] = select fast i1 [[TMP6]], float [[TMP9]], float [[TMP5]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp fast olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
-; NOPRELINK-NEXT: [[TMP14:%.*]] = select fast i1 [[TMP13]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select fast i1 [[TMP13]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP14]]
;
entry:
@@ -1872,10 +1872,10 @@ define float @test_fast_rootn_f32_known_positive_y_known_even(float nofpclass(ni
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP7:%.*]] = xor i1 [[TMP5]], [[TMP6]]
-; NOPRELINK-NEXT: [[TMP8:%.*]] = select fast i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select fast i1 [[TMP7]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT: [[TMP9:%.*]] = select fast i1 [[TMP5]], float [[TMP8]], float [[TMP4]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[Y]], 0
-; NOPRELINK-NEXT: [[TMP11:%.*]] = select fast i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP9]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select fast i1 [[TMP10]], float +qnan, float [[TMP9]]
; NOPRELINK-NEXT: ret float [[TMP11]]
;
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acos.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acos.ll
index 843602d8fcad9..49cd4006f6d79 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acos.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acos.ll
@@ -4,7 +4,7 @@
define float @test_tdo_scalar_f32_acos() {
; CHECK-LABEL: define float @test_tdo_scalar_f32_acos() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret float 0x3FF921FB60000000
+; CHECK-NEXT: ret float f0x3FC90FDB
;
entry:
%c = call float @_Z4acosf(float 0.000000e+00)
@@ -14,7 +14,7 @@ entry:
define <4 x float> @test_tdo_v2_f32_acos() {
; CHECK-LABEL: define <4 x float> @test_tdo_v2_f32_acos() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x float> <float 0x3FF921FB60000000, float 0x3FF921FB60000000, float 0.000000e+00, float 0x400921FB60000000>
+; CHECK-NEXT: ret <4 x float> <float f0x3FC90FDB, float f0x3FC90FDB, float 0.000000e+00, float f0x40490FDB>
;
entry:
%c = call <4 x float> @_Z4acosDv4_f(<4 x float> <float 0.000000e+00, float -0.000000e+00, float 1.000000e+00, float -1.000000e+00>)
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_acos() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_acos() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3E48
+; CHECK-NEXT: ret half 1.570310e+00
;
entry:
%c = call half @_Z4acosDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <4 x half> @test_tdo_v2_f16_acos() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_acos() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x half> <half 0xH3E48, half 0xH3E48, half 0xH0000, half 0xH4248>
+; CHECK-NEXT: ret <4 x half> <half 1.570310e+00, half 1.570310e+00, half 0.000000e+00, half 3.140630e+00>
;
entry:
%c = call <4 x half> @_Z4acosDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
@@ -44,7 +44,7 @@ entry:
define double @test_tdo_scalar_f64_acos() {
; CHECK-LABEL: define double @test_tdo_scalar_f64_acos() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret double 0x3FF921FB54442D18
+; CHECK-NEXT: ret double f0x3FF921FB54442D18
;
entry:
%c = call double @_Z4acosd(double 0.000000e+00)
@@ -54,7 +54,7 @@ entry:
define <4 x double> @test_tdo_v2_f64_acos() {
; CHECK-LABEL: define <4 x double> @test_tdo_v2_f64_acos() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x double> <double 0x3FF921FB54442D18, double 0x3FF921FB54442D18, double 0.000000e+00, double 0x400921FB54442D18>
+; CHECK-NEXT: ret <4 x double> <double f0x3FF921FB54442D18, double f0x3FF921FB54442D18, double 0.000000e+00, double f0x400921FB54442D18>
;
entry:
%c = call <4 x double> @_Z4acosDv4_d(<4 x double> <double 0.000000e+00, double -0.000000e+00, double 1.000000e+00, double -1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acosh.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acosh.ll
index 39f07af50dba0..5d3ace758b531 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acosh.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acosh.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_acosh() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_acosh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z5acoshDh(half 1.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acospi.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acospi.ll
index 23193b5b3c10e..8bcd964a2868e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acospi.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acospi.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_acospi() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_acospi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3800
+; CHECK-NEXT: ret half 5.000000e-01
;
entry:
%c = call half @_Z6acospiDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <4 x half> @test_tdo_v2_f16_acospi() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_acospi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x half> <half 0xH3800, half 0xH3800, half 0xH0000, half 0xH3C00>
+; CHECK-NEXT: ret <4 x half> <half 5.000000e-01, half 5.000000e-01, half 0.000000e+00, half 1.000000e+00>
;
entry:
%c = call <4 x half> @_Z6acospiDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asin.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asin.ll
index 56ab0ff089e4e..db42d582df33c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asin.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asin.ll
@@ -14,7 +14,7 @@ entry:
define <4 x float> @test_tdo_v2_f32_asin() {
; CHECK-LABEL: define <4 x float> @test_tdo_v2_f32_asin() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float -0.000000e+00, float 0x3FF921FB60000000, float 0xBFF921FB60000000>
+; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float -0.000000e+00, float f0x3FC90FDB, float f0xBFC90FDB>
;
entry:
%c = call <4 x float> @_Z4asinDv4_f(<4 x float> <float 0.000000e+00, float -0.000000e+00, float 1.000000e+00, float -1.000000e+00>)
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_asin() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_asin() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z4asinDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <4 x half> @test_tdo_v2_f16_asin() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_asin() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x half> <half 0xH0000, half 0xH8000, half 0xH3E48, half 0xHBE48>
+; CHECK-NEXT: ret <4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.570310e+00, half -1.570310e+00>
;
entry:
%c = call <4 x half> @_Z4asinDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
@@ -54,7 +54,7 @@ entry:
define <4 x double> @test_tdo_v2_f64_asin() {
; CHECK-LABEL: define <4 x double> @test_tdo_v2_f64_asin() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x double> <double 0.000000e+00, double -0.000000e+00, double 0x3FF921FB54442D18, double 0xBFF921FB54442D18>
+; CHECK-NEXT: ret <4 x double> <double 0.000000e+00, double -0.000000e+00, double f0x3FF921FB54442D18, double f0xBFF921FB54442D18>
;
entry:
%c = call <4 x double> @_Z4asinDv4_d(<4 x double> <double 0.000000e+00, double -0.000000e+00, double 1.000000e+00, double -1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinh.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinh.ll
index 161e108f258bb..1da72d9249c11 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinh.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinh.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_asinh() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_asinh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z5asinhDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_asinh() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_asinh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> <half 0xH0000, half 0xH8000>
+; CHECK-NEXT: ret <2 x half> <half 0.000000e+00, half -0.000000e+00>
;
entry:
%c = call <2 x half> @_Z5asinhDv2_Dh(<2 x half> <half 0.000000e+00, half -0.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinpi.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinpi.ll
index 349da1b4f1beb..88647b8f4176a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinpi.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinpi.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_asinpi() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_asinpi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z6asinpiDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <4 x half> @test_tdo_v2_f16_asinpi() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_asinpi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x half> <half 0xH0000, half 0xH8000, half 0xH3800, half 0xHB800>
+; CHECK-NEXT: ret <4 x half> <half 0.000000e+00, half -0.000000e+00, half 5.000000e-01, half -5.000000e-01>
;
entry:
%c = call <4 x half> @_Z6asinpiDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atan.ll
index a178c5ab24b3d..1a742bd3b6ba4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atan.ll
@@ -14,7 +14,7 @@ entry:
define <4 x float> @test_tdo_v2_f32_atan() {
; CHECK-LABEL: define <4 x float> @test_tdo_v2_f32_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float -0.000000e+00, float 0x3FE921FB60000000, float 0xBFE921FB60000000>
+; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float -0.000000e+00, float f0x3F490FDB, float f0xBF490FDB>
;
entry:
%c = call <4 x float> @_Z4atanDv4_f(<4 x float> <float 0.000000e+00, float -0.000000e+00, float 1.000000e+00, float -1.000000e+00>)
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_atan() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z4atanDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <4 x half> @test_tdo_v2_f16_atan() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x half> <half 0xH0000, half 0xH8000, half 0xH3A48, half 0xHBA48>
+; CHECK-NEXT: ret <4 x half> <half 0.000000e+00, half -0.000000e+00, half 7.851560e-01, half -7.851560e-01>
;
entry:
%c = call <4 x half> @_Z4atanDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
@@ -54,7 +54,7 @@ entry:
define <4 x double> @test_tdo_v2_f64_atan() {
; CHECK-LABEL: define <4 x double> @test_tdo_v2_f64_atan() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x double> <double 0.000000e+00, double -0.000000e+00, double 0x3FE921FB54442D18, double 0xBFE921FB54442D18>
+; CHECK-NEXT: ret <4 x double> <double 0.000000e+00, double -0.000000e+00, double f0x3FE921FB54442D18, double f0xBFE921FB54442D18>
;
entry:
%c = call <4 x double> @_Z4atanDv4_d(<4 x double> <double 0.000000e+00, double -0.000000e+00, double 1.000000e+00, double -1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanh.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanh.ll
index 3d93e335d1baa..6129ead8e2027 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanh.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanh.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_atanh() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_atanh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z5atanhDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_atanh() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_atanh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> <half 0xH0000, half 0xH8000>
+; CHECK-NEXT: ret <2 x half> <half 0.000000e+00, half -0.000000e+00>
;
entry:
%c = call <2 x half> @_Z5atanhDv2_Dh(<2 x half> <half 0.000000e+00, half -0.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanpi.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanpi.ll
index e5aef437f8245..93cfe6158074e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanpi.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanpi.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_atanpi() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_atanpi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z6atanpiDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <4 x half> @test_tdo_v2_f16_atanpi() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_atanpi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x half> <half 0xH0000, half 0xH8000, half 0xH3400, half 0xHB400>
+; CHECK-NEXT: ret <4 x half> <half 0.000000e+00, half -0.000000e+00, half 2.500000e-01, half -2.500000e-01>
;
entry:
%c = call <4 x half> @_Z6atanpiDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cbrt.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cbrt.ll
index 9b297ba8eae10..a09e0375612d4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cbrt.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cbrt.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_cbrt() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_cbrt() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z4cbrtDh(half 1.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <4 x half> @test_tdo_v2_f16_cbrt() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_cbrt() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x half> <half 0xH0000, half 0xH8000, half 0xH3C00, half 0xHBC00>
+; CHECK-NEXT: ret <4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>
;
entry:
%c = call <4 x half> @_Z4cbrtDv4_Dh(<4 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00, half -1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cos.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cos.ll
index 2d6b36b243a11..9b619ada4321d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cos.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cos.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_cos() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_cos() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z3cosDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_cos() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_cos() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> splat (half 0xH3C00)
+; CHECK-NEXT: ret <2 x half> splat (half 1.000000e+00)
;
entry:
%c = call <2 x half> @_Z3cosDv2_Dh(<2 x half> <half 0.000000e+00, half -0.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cosh.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cosh.ll
index 6f0b4c042387d..f17b55ebc7a55 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cosh.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cosh.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_cosh() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_cosh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z4coshDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_cosh() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_cosh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> splat (half 0xH3C00)
+; CHECK-NEXT: ret <2 x half> splat (half 1.000000e+00)
;
entry:
%c = call <2 x half> @_Z4coshDv2_Dh(<2 x half> <half 0.000000e+00, half -0.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cospi.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cospi.ll
index 886949b7b21e3..9f0bbcf96b443 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cospi.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cospi.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_cospi() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_cospi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z5cospiDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_cospi() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_cospi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> splat (half 0xH3C00)
+; CHECK-NEXT: ret <2 x half> splat (half 1.000000e+00)
;
entry:
%c = call <2 x half> @_Z5cospiDv2_Dh(<2 x half> <half 0.000000e+00, half -0.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erf.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erf.ll
index 3d1d6c9f644b2..b47ebf84f1e31 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erf.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erf.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_erf() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_erf() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z3erfDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_erf() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_erf() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> <half 0xH0000, half 0xH8000>
+; CHECK-NEXT: ret <2 x half> <half 0.000000e+00, half -0.000000e+00>
;
entry:
%c = call <2 x half> @_Z3erfDv2_Dh(<2 x half> <half 0.000000e+00, half -0.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erfc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erfc.ll
index 0e0bb9efab575..b4776c64b5b72 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erfc.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erfc.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_erfc() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_erfc() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z4erfcDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_erfc() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_erfc() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> splat (half 0xH3C00)
+; CHECK-NEXT: ret <2 x half> splat (half 1.000000e+00)
;
entry:
%c = call <2 x half> @_Z4erfcDv2_Dh(<2 x half> <half 0.000000e+00, half -0.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp.ll
index 6c49a84ef27e3..bd12a5e66782a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp.ll
@@ -14,7 +14,7 @@ entry:
define <3 x float> @test_tdo_v2_f32_exp() {
; CHECK-LABEL: define <3 x float> @test_tdo_v2_f32_exp() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <3 x float> <float 1.000000e+00, float 1.000000e+00, float 0x4005BF0A80000000>
+; CHECK-NEXT: ret <3 x float> <float 1.000000e+00, float 1.000000e+00, float f0x402DF854>
;
entry:
%c = call <3 x float> @_Z3expDv3_f(<3 x float> <float 0.000000e+00, float -0.000000e+00, float 1.000000e+00>)
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_exp() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_exp() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z3expDh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <3 x half> @test_tdo_v2_f16_exp() {
; CHECK-LABEL: define <3 x half> @test_tdo_v2_f16_exp() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <3 x half> <half 0xH3C00, half 0xH3C00, half 0xH4170>
+; CHECK-NEXT: ret <3 x half> <half 1.000000e+00, half 1.000000e+00, half 2.718750e+00>
;
entry:
%c = call <3 x half> @_Z3expDv3_Dh(<3 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00>)
@@ -54,7 +54,7 @@ entry:
define <3 x double> @test_tdo_v2_f64_exp() {
; CHECK-LABEL: define <3 x double> @test_tdo_v2_f64_exp() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <3 x double> <double 1.000000e+00, double 1.000000e+00, double 0x4005BF0A8B145769>
+; CHECK-NEXT: ret <3 x double> <double 1.000000e+00, double 1.000000e+00, double f0x4005BF0A8B145769>
;
entry:
%c = call <3 x double> @_Z3expDv3_d(<3 x double> <double 0.000000e+00, double -0.000000e+00, double 1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp10.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp10.ll
index 93c81f43ac93b..7c8e21206f9ae 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp10.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp10.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_exp10() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_exp10() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z5exp10Dh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <3 x half> @test_tdo_v2_f16_exp10() {
; CHECK-LABEL: define <3 x half> @test_tdo_v2_f16_exp10() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <3 x half> <half 0xH3C00, half 0xH3C00, half 0xH4900>
+; CHECK-NEXT: ret <3 x half> <half 1.000000e+00, half 1.000000e+00, half 1.000000e+01>
;
entry:
%c = call <3 x half> @_Z5exp10Dv3_Dh(<3 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp2.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp2.ll
index e1a645320cb7b..8776f9da13cb6 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp2.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_exp2() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_exp2() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z4exp2Dh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <3 x half> @test_tdo_v2_f16_exp2() {
; CHECK-LABEL: define <3 x half> @test_tdo_v2_f16_exp2() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <3 x half> <half 0xH3C00, half 0xH3C00, half 0xH4000>
+; CHECK-NEXT: ret <3 x half> <half 1.000000e+00, half 1.000000e+00, half 2.000000e+00>
;
entry:
%c = call <3 x half> @_Z4exp2Dv3_Dh(<3 x half> <half 0.000000e+00, half -0.000000e+00, half 1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-expm1.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-expm1.ll
index f20312a875d7b..bfe2d14793026 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-expm1.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-expm1.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_expm1() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_expm1() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z5expm1Dh(half 0.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_expm1() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_expm1() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> <half 0xH0000, half 0xH8000>
+; CHECK-NEXT: ret <2 x half> <half 0.000000e+00, half -0.000000e+00>
;
entry:
%c = call <2 x half> @_Z5expm1Dv2_Dh(<2 x half> <half 0.000000e+00, half -0.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log.ll
index f926e89e1b905..41a5ddd6fcfe8 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_log() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_log() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z3logDh(half 1.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log10.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log10.ll
index 77656a5242000..e210e8aba1648 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log10.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_log10() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_log10() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z5log10Dh(half 1.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log2.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log2.ll
index 317525c435f52..7d2d519573c15 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log2.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_log2() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_log2() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z4log2Dh(half 1.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-rsqrt.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-rsqrt.ll
index 9d794ce5f46b0..6b064cd6d3868 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-rsqrt.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-rsqrt.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_rsqrt() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_rsqrt() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z5rsqrtDh(half 1.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <2 x half> @test_tdo_v2_f16_rsqrt() {
; CHECK-LABEL: define <2 x half> @test_tdo_v2_f16_rsqrt() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <2 x half> splat (half 0xH3C00)
+; CHECK-NEXT: ret <2 x half> splat (half 1.000000e+00)
;
entry:
%c = call <2 x half> @_Z5rsqrtDv2_Dh(<2 x half> <half 1.000000e+00, half 1.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sin.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sin.ll
index c1c6f585ebd30..a7b0554eb583e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sin.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sin.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_sin() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_sin() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z3sinDh(half 0.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinh.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinh.ll
index f45474ddee859..aeedcca8befb0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinh.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinh.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_sinh() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_sinh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z4sinhDh(half 0.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinpi.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinpi.ll
index 250abaa28f51d..1ec380b070cae 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinpi.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinpi.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_sinpi() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_sinpi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z5sinpiDh(half 0.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sqrt.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sqrt.ll
index 04bdb0cabf004..8675f07249502 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sqrt.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sqrt.ll
@@ -14,7 +14,7 @@ entry:
define <3 x float> @test_tdo_v2_f32_sqrt() {
; CHECK-LABEL: define <3 x float> @test_tdo_v2_f32_sqrt() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <3 x float> <float 0.000000e+00, float 1.000000e+00, float 0x3FF6A09E60000000>
+; CHECK-NEXT: ret <3 x float> <float 0.000000e+00, float 1.000000e+00, float f0x3FB504F3>
;
entry:
%c = call <3 x float> @_Z4sqrtDv3_f(<3 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00>)
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_sqrt() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_sqrt() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z4sqrtDh(half 1.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <3 x half> @test_tdo_v2_f16_sqrt() {
; CHECK-LABEL: define <3 x half> @test_tdo_v2_f16_sqrt() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <3 x half> <half 0xH0000, half 0xH3C00, half 0xH3DA8>
+; CHECK-NEXT: ret <3 x half> <half 0.000000e+00, half 1.000000e+00, half 1.414060e+00>
;
entry:
%c = call <3 x half> @_Z4sqrtDv3_Dh(<3 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00>)
@@ -54,7 +54,7 @@ entry:
define <3 x double> @test_tdo_v2_f64_sqrt() {
; CHECK-LABEL: define <3 x double> @test_tdo_v2_f64_sqrt() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <3 x double> <double 0.000000e+00, double 1.000000e+00, double 0x3FF6A09E667F3BCD>
+; CHECK-NEXT: ret <3 x double> <double 0.000000e+00, double 1.000000e+00, double f0x3FF6A09E667F3BCD>
;
entry:
%c = call <3 x double> @_Z4sqrtDv3_d(<3 x double> <double 0.000000e+00, double 1.000000e+00, double 2.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tan.ll
index 2aa8ce4eae3f3..8e4152cbf73e2 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tan.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_tan() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_tan() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z3tanDh(half 0.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanh.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanh.ll
index ba20df929614a..5a11491f3929d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanh.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanh.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_tanh() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_tanh() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z4tanhDh(half 0.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanpi.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanpi.ll
index 72fbc1a82101a..05ca625bdae1e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanpi.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanpi.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_tanpi() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_tanpi() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
%c = call half @_Z5tanpiDh(half 0.000000e+00)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tgamma.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tgamma.ll
index a95aa6a5730c2..a365c840eb6c0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tgamma.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tgamma.ll
@@ -24,7 +24,7 @@ entry:
define half @test_tdo_scalar_f16_tgamma() {
; CHECK-LABEL: define half @test_tdo_scalar_f16_tgamma() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
entry:
%c = call half @_Z6tgammaDh(half 1.000000e+00)
@@ -34,7 +34,7 @@ entry:
define <4 x half> @test_tdo_v2_f16_tgamma() {
; CHECK-LABEL: define <4 x half> @test_tdo_v2_f16_tgamma() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x half> <half 0xH3C00, half 0xH3C00, half 0xH4000, half 0xH4600>
+; CHECK-NEXT: ret <4 x half> <half 1.000000e+00, half 1.000000e+00, half 2.000000e+00, half 6.000000e+00>
;
entry:
%c = call <4 x half> @_Z6tgammaDv4_Dh(<4 x half> <half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00>)
diff --git a/llvm/test/CodeGen/AMDGPU/fract-match.ll b/llvm/test/CodeGen/AMDGPU/fract-match.ll
index da538744fb8d2..17c93482564f8 100644
--- a/llvm/test/CodeGen/AMDGPU/fract-match.ll
+++ b/llvm/test/CodeGen/AMDGPU/fract-match.ll
@@ -28,11 +28,11 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[X]], float [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; GFX6-IR-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret float [[COND6]]
@@ -43,7 +43,7 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(
; IR-FRACT-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; IR-FRACT-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret float [[COND6]]
@@ -244,11 +244,11 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; GFX6-IR-SAME: <3 x float> [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) #[[ATTR0]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call <3 x float> @llvm.floor.v3f32(<3 x float> [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub <3 x float> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <3 x float> @llvm.minnum.v3f32(<3 x float> [[SUB]], <3 x float> <float 0x3FEFFFFFE0000000, float poison, float 0x3FEFFFFFE0000000>)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <3 x float> @llvm.minnum.v3f32(<3 x float> [[SUB]], <3 x float> <float f0x3F7FFFFF, float poison, float f0x3F7FFFFF>)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno <3 x float> [[X]], <float 0.000000e+00, float poison, float 0.000000e+00>
; GFX6-IR-NEXT: [[COND:%.*]] = select <3 x i1> [[UNO]], <3 x float> [[X]], <3 x float> [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <3 x float> [[FABS]], <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <3 x float> [[FABS]], <float +inf, float poison, float +inf>
; GFX6-IR-NEXT: [[COND6:%.*]] = select <3 x i1> [[CMPINF]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[COND]]
; GFX6-IR-NEXT: store <3 x float> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret <3 x float> [[COND6]]
@@ -265,7 +265,7 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; IR-FRACT-NEXT: [[TMP8:%.*]] = insertelement <3 x float> [[TMP7]], float [[TMP5]], i64 1
; IR-FRACT-NEXT: [[COND:%.*]] = insertelement <3 x float> [[TMP8]], float [[TMP6]], i64 2
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq <3 x float> [[FABS]], <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq <3 x float> [[FABS]], <float +inf, float poison, float +inf>
; IR-FRACT-NEXT: [[COND6:%.*]] = select <3 x i1> [[CMPINF]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[COND]]
; IR-FRACT-NEXT: store <3 x float> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret <3 x float> [[COND6]]
@@ -290,7 +290,7 @@ define <2 x float> @safe_math_fract_v2f32_const_splat_poison(<2 x float> %x, ptr
; IR-NEXT: [[UNO:%.*]] = fcmp uno <2 x float> [[X]], zeroinitializer
; IR-NEXT: [[COND:%.*]] = select <2 x i1> [[UNO]], <2 x float> [[X]], <2 x float> [[MIN]]
; IR-NEXT: [[FABS:%.*]] = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x float> [[FABS]], splat (float 0x7FF0000000000000)
+; IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x float> [[FABS]], splat (float +inf)
; IR-NEXT: [[COND6:%.*]] = select <2 x i1> [[CMPINF]], <2 x float> zeroinitializer, <2 x float> [[COND]]
; IR-NEXT: store <2 x float> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-NEXT: ret <2 x float> [[COND6]]
@@ -426,11 +426,11 @@ define float @safe_math_fract_f32_swap(float %x, ptr addrspace(1) writeonly capt
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[MIN]], float [[X]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; GFX6-IR-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret float [[COND6]]
@@ -441,7 +441,7 @@ define float @safe_math_fract_f32_swap(float %x, ptr addrspace(1) writeonly capt
; IR-FRACT-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; IR-FRACT-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret float [[COND6]]
@@ -538,7 +538,7 @@ define float @safe_math_fract_f32_noinf_check(float %x, ptr addrspace(1) writeon
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[X]], float [[MIN]]
; GFX6-IR-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
@@ -626,9 +626,9 @@ define float @no_nan_check_math_fract_f32(float %x, ptr addrspace(1) writeonly c
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[MIN]]
; IR-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-NEXT: ret float [[COND6]]
@@ -725,7 +725,7 @@ define float @basic_fract_f32_nonans(float nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @basic_fract_f32_nonans(
@@ -782,7 +782,7 @@ define float @basic_fract_f32_flags_minnum(float %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call nsz float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call nsz float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: basic_fract_f32_flags_minnum:
@@ -843,7 +843,7 @@ define float @basic_fract_f32_flags_fsub(float nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub nsz float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @basic_fract_f32_flags_fsub(
@@ -900,7 +900,7 @@ define <2 x float> @basic_fract_v2f32_nonans(<2 x float> nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call <2 x float> @llvm.floor.v2f32(<2 x float> [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub <2 x float> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x float> @llvm.minnum.v2f32(<2 x float> [[SUB]], <2 x float> splat (float 0x3FEFFFFFE0000000))
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x float> @llvm.minnum.v2f32(<2 x float> [[SUB]], <2 x float> splat (float f0x3F7FFFFF))
; GFX6-IR-NEXT: ret <2 x float> [[MIN]]
;
; IR-FRACT-LABEL: define <2 x float> @basic_fract_v2f32_nonans(
@@ -969,7 +969,7 @@ define float @basic_fract_f32_multi_use_fsub_nonans(float nofpclass(nan) %x, ptr
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: store float [[SUB]], ptr addrspace(1) [[PTR]], align 4
; GFX6-IR-NEXT: ret float [[MIN]]
;
@@ -1057,7 +1057,7 @@ define float @nnan_minnum_fract_f32(float %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nnan float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nnan float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @nnan_minnum_fract_f32(
@@ -1116,7 +1116,7 @@ define float @nnan_fsub_fract_f32(float %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub nnan float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: nnan_fsub_fract_f32:
@@ -1177,7 +1177,7 @@ define float @nnan_floor_fract_f32(float %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call nnan float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: nnan_floor_fract_f32:
@@ -1238,7 +1238,7 @@ define float @nnan_src_fract_f32(float nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @nnan_src_fract_f32(
@@ -1296,7 +1296,7 @@ define float @not_fract_f32_wrong_const(float nofpclass(nan) %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFC0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFE)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: not_fract_f32_wrong_const:
@@ -1358,7 +1358,7 @@ define float @not_fract_f32_swapped_fsub(float nofpclass(nan) %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[FLOOR]], [[X]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: not_fract_f32_swapped_fsub:
@@ -1420,7 +1420,7 @@ define float @not_fract_f32_not_floor(float nofpclass(nan) %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.trunc.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: not_fract_f32_not_floor:
@@ -1482,7 +1482,7 @@ define float @not_fract_f32_different_floor(float %x, float %y) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[Y]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: not_fract_f32_different_floor:
@@ -1544,7 +1544,7 @@ define float @not_fract_f32_maxnum(float nofpclass(nan) %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.maxnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.maxnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: not_fract_f32_maxnum:
@@ -1605,8 +1605,8 @@ define float @fcmp_uno_check_is_nan_f32(float %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
-; IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0x7FF8000000000000
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
+; IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], +qnan
; IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[X]], float [[MIN]]
; IR-NEXT: ret float [[COND]]
;
@@ -1639,7 +1639,7 @@ define float @select_nan_fract_f32(float %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[X]], float [[MIN]]
; GFX6-IR-NEXT: ret float [[COND]]
@@ -1702,7 +1702,7 @@ define float @commuted_select_nan_fract_f32(float %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[MIN]], float [[X]]
; GFX6-IR-NEXT: ret float [[COND]]
@@ -1765,7 +1765,7 @@ define float @wrong_commuted_nan_select_f32(float %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0.000000e+00
; IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[MIN]], float [[X]]
; IR-NEXT: ret float [[COND]]
@@ -1843,7 +1843,7 @@ define half @basic_fract_f16_nonan(half nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call half @llvm.floor.f16(half [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub half [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 0xH3BFF)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 9.995110e-01)
; GFX6-IR-NEXT: ret half [[MIN]]
;
; GFX7-IR-LABEL: define half @basic_fract_f16_nonan(
@@ -1851,7 +1851,7 @@ define half @basic_fract_f16_nonan(half nofpclass(nan) %x) {
; GFX7-IR-NEXT: [[ENTRY:.*:]]
; GFX7-IR-NEXT: [[FLOOR:%.*]] = tail call half @llvm.floor.f16(half [[X]])
; GFX7-IR-NEXT: [[SUB:%.*]] = fsub half [[X]], [[FLOOR]]
-; GFX7-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 0xH3BFF)
+; GFX7-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 9.995110e-01)
; GFX7-IR-NEXT: ret half [[MIN]]
;
; IR-LEGALF16-LABEL: define half @basic_fract_f16_nonan(
@@ -1938,7 +1938,7 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call <2 x half> @llvm.floor.v2f16(<2 x half> [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub <2 x half> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x half> @llvm.minnum.v2f16(<2 x half> [[SUB]], <2 x half> splat (half 0xH3BFF))
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x half> @llvm.minnum.v2f16(<2 x half> [[SUB]], <2 x half> splat (half 9.995110e-01))
; GFX6-IR-NEXT: ret <2 x half> [[MIN]]
;
; GFX7-IR-LABEL: define <2 x half> @basic_fract_v2f16_nonan(
@@ -1946,7 +1946,7 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) {
; GFX7-IR-NEXT: [[ENTRY:.*:]]
; GFX7-IR-NEXT: [[FLOOR:%.*]] = tail call <2 x half> @llvm.floor.v2f16(<2 x half> [[X]])
; GFX7-IR-NEXT: [[SUB:%.*]] = fsub <2 x half> [[X]], [[FLOOR]]
-; GFX7-IR-NEXT: [[MIN:%.*]] = tail call <2 x half> @llvm.minnum.v2f16(<2 x half> [[SUB]], <2 x half> splat (half 0xH3BFF))
+; GFX7-IR-NEXT: [[MIN:%.*]] = tail call <2 x half> @llvm.minnum.v2f16(<2 x half> [[SUB]], <2 x half> splat (half 9.995110e-01))
; GFX7-IR-NEXT: ret <2 x half> [[MIN]]
;
; IR-LEGALF16-LABEL: define <2 x half> @basic_fract_v2f16_nonan(
@@ -2074,7 +2074,7 @@ define double @basic_fract_f64_nanans(double nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call double @llvm.floor.f64(double [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub double [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call double @llvm.minnum.f64(double [[SUB]], double 0x3FEFFFFFFFFFFFFF)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call double @llvm.minnum.f64(double [[SUB]], double f0x3FEFFFFFFFFFFFFF)
; GFX6-IR-NEXT: ret double [[MIN]]
;
; IR-FRACT-LABEL: define double @basic_fract_f64_nanans(
@@ -2140,8 +2140,8 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call half @llvm.floor.f16(half [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub half [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 0xH3BFF)
-; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 9.995110e-01)
+; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], half [[X]], half [[MIN]]
; GFX6-IR-NEXT: store half [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret half [[COND]]
@@ -2151,8 +2151,8 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
; GFX7-IR-NEXT: [[ENTRY:.*:]]
; GFX7-IR-NEXT: [[FLOOR:%.*]] = tail call half @llvm.floor.f16(half [[X]])
; GFX7-IR-NEXT: [[SUB:%.*]] = fsub half [[X]], [[FLOOR]]
-; GFX7-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 0xH3BFF)
-; GFX7-IR-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; GFX7-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 9.995110e-01)
+; GFX7-IR-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; GFX7-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], half [[X]], half [[MIN]]
; GFX7-IR-NEXT: store half [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX7-IR-NEXT: ret half [[COND]]
@@ -2273,7 +2273,7 @@ define double @safe_math_fract_f64_noinf_check(double %x, ptr addrspace(1) write
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call double @llvm.floor.f64(double [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub double [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call double @llvm.minnum.f64(double [[SUB]], double 0x3FEFFFFFFFFFFFFF)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call double @llvm.minnum.f64(double [[SUB]], double f0x3FEFFFFFFFFFFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno double [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], double [[X]], double [[MIN]]
; GFX6-IR-NEXT: store double [[FLOOR]], ptr addrspace(1) [[IP]], align 4
@@ -2370,7 +2370,7 @@ define float @select_nan_fract_f32_flags_select(float %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select nsz i1 [[UNO]], float [[X]], float [[MIN]]
; GFX6-IR-NEXT: ret float [[COND]]
@@ -2433,7 +2433,7 @@ define float @select_nan_fract_f32_flags_minnum(float %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nsz float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nsz float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[X]], float [[MIN]]
; GFX6-IR-NEXT: ret float [[COND]]
@@ -2496,11 +2496,11 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call <2 x float> @llvm.floor.v2f32(<2 x float> [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub <2 x float> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x float> @llvm.minnum.v2f32(<2 x float> [[SUB]], <2 x float> splat (float 0x3FEFFFFFE0000000))
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x float> @llvm.minnum.v2f32(<2 x float> [[SUB]], <2 x float> splat (float f0x3F7FFFFF))
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno <2 x float> [[X]], zeroinitializer
; GFX6-IR-NEXT: [[COND:%.*]] = select <2 x i1> [[UNO]], <2 x float> [[X]], <2 x float> [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x float> [[FABS]], splat (float 0x7FF0000000000000)
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x float> [[FABS]], splat (float +inf)
; GFX6-IR-NEXT: [[COND6:%.*]] = select <2 x i1> [[CMPINF]], <2 x float> zeroinitializer, <2 x float> [[COND]]
; GFX6-IR-NEXT: store <2 x float> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret <2 x float> [[COND6]]
@@ -2516,7 +2516,7 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; IR-FRACT-NEXT: [[TMP4:%.*]] = insertelement <2 x float> poison, float [[TMP2]], i64 0
; IR-FRACT-NEXT: [[COND:%.*]] = insertelement <2 x float> [[TMP4]], float [[TMP3]], i64 1
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x float> [[FABS]], splat (float 0x7FF0000000000000)
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x float> [[FABS]], splat (float +inf)
; IR-FRACT-NEXT: [[COND6:%.*]] = select <2 x i1> [[CMPINF]], <2 x float> zeroinitializer, <2 x float> [[COND]]
; IR-FRACT-NEXT: store <2 x float> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret <2 x float> [[COND6]]
@@ -2636,11 +2636,11 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call double @llvm.floor.f64(double [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub double [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call double @llvm.minnum.f64(double [[SUB]], double 0x3FEFFFFFFFFFFFFF)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call double @llvm.minnum.f64(double [[SUB]], double f0x3FEFFFFFFFFFFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno double [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], double [[X]], double [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq double [[FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq double [[FABS]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], double 0.000000e+00, double [[COND]]
; GFX6-IR-NEXT: store double [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret double [[COND6]]
@@ -2651,7 +2651,7 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; IR-FRACT-NEXT: [[FLOOR:%.*]] = tail call double @llvm.floor.f64(double [[X]])
; IR-FRACT-NEXT: [[COND:%.*]] = call double @llvm.amdgcn.fract.f64(double [[X]])
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq double [[FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq double [[FABS]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], double 0.000000e+00, double [[COND]]
; IR-FRACT-NEXT: store double [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret double [[COND6]]
@@ -2764,12 +2764,12 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call half @llvm.floor.f16(half [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub half [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 0xH3BFF)
-; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 9.995110e-01)
+; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], half [[X]], half [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call half @llvm.fabs.f16(half [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], half 0xH0000, half [[COND]]
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], +inf
+; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], half 0.000000e+00, half [[COND]]
; GFX6-IR-NEXT: store half [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret half [[COND6]]
;
@@ -2778,12 +2778,12 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX7-IR-NEXT: [[ENTRY:.*:]]
; GFX7-IR-NEXT: [[FLOOR:%.*]] = tail call half @llvm.floor.f16(half [[X]])
; GFX7-IR-NEXT: [[SUB:%.*]] = fsub half [[X]], [[FLOOR]]
-; GFX7-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 0xH3BFF)
-; GFX7-IR-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; GFX7-IR-NEXT: [[MIN:%.*]] = tail call half @llvm.minnum.f16(half [[SUB]], half 9.995110e-01)
+; GFX7-IR-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; GFX7-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], half [[X]], half [[MIN]]
; GFX7-IR-NEXT: [[FABS:%.*]] = tail call half @llvm.fabs.f16(half [[X]])
-; GFX7-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; GFX7-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], half 0xH0000, half [[COND]]
+; GFX7-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], +inf
+; GFX7-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], half 0.000000e+00, half [[COND]]
; GFX7-IR-NEXT: store half [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX7-IR-NEXT: ret half [[COND6]]
;
@@ -2793,8 +2793,8 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; IR-LEGALF16-NEXT: [[FLOOR:%.*]] = tail call half @llvm.floor.f16(half [[X]])
; IR-LEGALF16-NEXT: [[COND:%.*]] = call half @llvm.amdgcn.fract.f16(half [[X]])
; IR-LEGALF16-NEXT: [[FABS:%.*]] = tail call half @llvm.fabs.f16(half [[X]])
-; IR-LEGALF16-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; IR-LEGALF16-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], half 0xH0000, half [[COND]]
+; IR-LEGALF16-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], +inf
+; IR-LEGALF16-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], half 0.000000e+00, half [[COND]]
; IR-LEGALF16-NEXT: store half [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-LEGALF16-NEXT: ret half [[COND6]]
;
@@ -2934,11 +2934,11 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call <2 x half> @llvm.floor.v2f16(<2 x half> [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub <2 x half> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x half> @llvm.minnum.v2f16(<2 x half> [[SUB]], <2 x half> splat (half 0xH3BFF))
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x half> @llvm.minnum.v2f16(<2 x half> [[SUB]], <2 x half> splat (half 9.995110e-01))
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno <2 x half> [[X]], zeroinitializer
; GFX6-IR-NEXT: [[COND:%.*]] = select <2 x i1> [[UNO]], <2 x half> [[X]], <2 x half> [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x half> [[FABS]], splat (half 0xH7C00)
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x half> [[FABS]], splat (half +inf)
; GFX6-IR-NEXT: [[COND6:%.*]] = select <2 x i1> [[CMPINF]], <2 x half> zeroinitializer, <2 x half> [[COND]]
; GFX6-IR-NEXT: store <2 x half> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret <2 x half> [[COND6]]
@@ -2948,11 +2948,11 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX7-IR-NEXT: [[ENTRY:.*:]]
; GFX7-IR-NEXT: [[FLOOR:%.*]] = tail call <2 x half> @llvm.floor.v2f16(<2 x half> [[X]])
; GFX7-IR-NEXT: [[SUB:%.*]] = fsub <2 x half> [[X]], [[FLOOR]]
-; GFX7-IR-NEXT: [[MIN:%.*]] = tail call <2 x half> @llvm.minnum.v2f16(<2 x half> [[SUB]], <2 x half> splat (half 0xH3BFF))
+; GFX7-IR-NEXT: [[MIN:%.*]] = tail call <2 x half> @llvm.minnum.v2f16(<2 x half> [[SUB]], <2 x half> splat (half 9.995110e-01))
; GFX7-IR-NEXT: [[UNO:%.*]] = fcmp uno <2 x half> [[X]], zeroinitializer
; GFX7-IR-NEXT: [[COND:%.*]] = select <2 x i1> [[UNO]], <2 x half> [[X]], <2 x half> [[MIN]]
; GFX7-IR-NEXT: [[FABS:%.*]] = tail call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X]])
-; GFX7-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x half> [[FABS]], splat (half 0xH7C00)
+; GFX7-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x half> [[FABS]], splat (half +inf)
; GFX7-IR-NEXT: [[COND6:%.*]] = select <2 x i1> [[CMPINF]], <2 x half> zeroinitializer, <2 x half> [[COND]]
; GFX7-IR-NEXT: store <2 x half> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX7-IR-NEXT: ret <2 x half> [[COND6]]
@@ -2968,7 +2968,7 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; IR-LEGALF16-NEXT: [[TMP4:%.*]] = insertelement <2 x half> poison, half [[TMP2]], i64 0
; IR-LEGALF16-NEXT: [[COND:%.*]] = insertelement <2 x half> [[TMP4]], half [[TMP3]], i64 1
; IR-LEGALF16-NEXT: [[FABS:%.*]] = tail call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X]])
-; IR-LEGALF16-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x half> [[FABS]], splat (half 0xH7C00)
+; IR-LEGALF16-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x half> [[FABS]], splat (half +inf)
; IR-LEGALF16-NEXT: [[COND6:%.*]] = select <2 x i1> [[CMPINF]], <2 x half> zeroinitializer, <2 x half> [[COND]]
; IR-LEGALF16-NEXT: store <2 x half> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-LEGALF16-NEXT: ret <2 x half> [[COND6]]
@@ -3179,11 +3179,11 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call <2 x double> @llvm.floor.v2f64(<2 x double> [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub <2 x double> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x double> @llvm.minnum.v2f64(<2 x double> [[SUB]], <2 x double> splat (double 0x3FEFFFFFFFFFFFFF))
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call <2 x double> @llvm.minnum.v2f64(<2 x double> [[SUB]], <2 x double> splat (double f0x3FEFFFFFFFFFFFFF))
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno <2 x double> [[X]], zeroinitializer
; GFX6-IR-NEXT: [[COND:%.*]] = select <2 x i1> [[UNO]], <2 x double> [[X]], <2 x double> [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x double> [[FABS]], splat (double 0x7FF0000000000000)
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x double> [[FABS]], splat (double +inf)
; GFX6-IR-NEXT: [[COND6:%.*]] = select <2 x i1> [[CMPINF]], <2 x double> zeroinitializer, <2 x double> [[COND]]
; GFX6-IR-NEXT: store <2 x double> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret <2 x double> [[COND6]]
@@ -3199,7 +3199,7 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; IR-FRACT-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i64 0
; IR-FRACT-NEXT: [[COND:%.*]] = insertelement <2 x double> [[TMP4]], double [[TMP3]], i64 1
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x double> [[FABS]], splat (double 0x7FF0000000000000)
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq <2 x double> [[FABS]], splat (double +inf)
; IR-FRACT-NEXT: [[COND6:%.*]] = select <2 x i1> [[CMPINF]], <2 x double> zeroinitializer, <2 x double> [[COND]]
; IR-FRACT-NEXT: store <2 x double> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret <2 x double> [[COND6]]
@@ -3343,11 +3343,11 @@ define float @safe_math_fract_f32_minimum(float %x, ptr addrspace(1) writeonly c
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[X]], float [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; GFX6-IR-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret float [[COND6]]
@@ -3358,7 +3358,7 @@ define float @safe_math_fract_f32_minimum(float %x, ptr addrspace(1) writeonly c
; IR-FRACT-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; IR-FRACT-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret float [[COND6]]
@@ -3458,11 +3458,11 @@ define float @safe_math_fract_f32_minimum_swap(float %x, ptr addrspace(1) writeo
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[MIN]], float [[X]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; GFX6-IR-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret float [[COND6]]
@@ -3473,7 +3473,7 @@ define float @safe_math_fract_f32_minimum_swap(float %x, ptr addrspace(1) writeo
; IR-FRACT-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; IR-FRACT-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret float [[COND6]]
@@ -3573,11 +3573,11 @@ define float @safe_math_fract_f32_minimumnum(float %x, ptr addrspace(1) writeonl
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimumnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimumnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp uno float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[X]], float [[MIN]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; GFX6-IR-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret float [[COND6]]
@@ -3588,7 +3588,7 @@ define float @safe_math_fract_f32_minimumnum(float %x, ptr addrspace(1) writeonl
; IR-FRACT-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; IR-FRACT-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret float [[COND6]]
@@ -3685,11 +3685,11 @@ define float @safe_math_fract_f32_minimumnum_swap(float %x, ptr addrspace(1) wri
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimumnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimumnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[UNO:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[UNO]], float [[MIN]], float [[X]]
; GFX6-IR-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; GFX6-IR-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret float [[COND6]]
@@ -3700,7 +3700,7 @@ define float @safe_math_fract_f32_minimumnum_swap(float %x, ptr addrspace(1) wri
; IR-FRACT-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[CMPINF:%.*]] = fcmp oeq float [[FABS]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[CMPINF]], float 0.000000e+00, float [[COND]]
; IR-FRACT-NEXT: store float [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret float [[COND6]]
@@ -3797,7 +3797,7 @@ define float @basic_fract_f32_nonans_minimumnum(float nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimumnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimumnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @basic_fract_f32_nonans_minimumnum(
@@ -3854,7 +3854,7 @@ define float @basic_fract_f32_nonans_minimum(float nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minimum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @basic_fract_f32_nonans_minimum(
@@ -3914,7 +3914,7 @@ define float @nnan_minimum_fract_f32(float %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nnan float @llvm.minimum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nnan float @llvm.minimum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @nnan_minimum_fract_f32(
@@ -3971,7 +3971,7 @@ define float @nnan_minimumnum_fract_f32(float %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nnan float @llvm.minimumnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nnan float @llvm.minimumnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @nnan_minimumnum_fract_f32(
@@ -4028,7 +4028,7 @@ define float @basic_fract_f32_flags_minimumnum(float %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call nsz float @llvm.minimumnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call nsz float @llvm.minimumnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: ret float [[MIN]]
;
; GFX6-LABEL: basic_fract_f32_flags_minimumnum:
@@ -4089,7 +4089,7 @@ define float @basic_fract_f32_flags_minimum(float %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nsz float @llvm.minimum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call nsz float @llvm.minimum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
;
; IR-FRACT-LABEL: define float @basic_fract_f32_flags_minimum(
@@ -4217,9 +4217,9 @@ define double @fract_match_f64_assume_not_nan(double %x) #0 {
; GFX6-IR-NEXT: tail call void @llvm.assume(i1 [[IS_ORD]])
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call double @llvm.floor.f64(double [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub double [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call double @llvm.minnum.f64(double [[SUB]], double 0x3FEFFFFFFFFFFFFF)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call double @llvm.minnum.f64(double [[SUB]], double f0x3FEFFFFFFFFFFFFF)
; GFX6-IR-NEXT: [[X_ABS:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-; GFX6-IR-NEXT: [[IS_INF:%.*]] = fcmp oeq double [[X_ABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[IS_INF:%.*]] = fcmp oeq double [[X_ABS]], +inf
; GFX6-IR-NEXT: [[RESULT:%.*]] = select i1 [[IS_INF]], double 0.000000e+00, double [[MIN]]
; GFX6-IR-NEXT: ret double [[RESULT]]
; IR-FRACT-LABEL: define double @fract_match_f64_assume_not_nan(
@@ -4229,7 +4229,7 @@ define double @fract_match_f64_assume_not_nan(double %x) #0 {
; IR-FRACT-NEXT: tail call void @llvm.assume(i1 [[IS_ORD]])
; IR-FRACT-NEXT: [[MIN:%.*]] = call nnan double @llvm.amdgcn.fract.f64(double [[X]])
; IR-FRACT-NEXT: [[X_ABS:%.*]] = tail call double @llvm.fabs.f64(double [[X]])
-; IR-FRACT-NEXT: [[IS_INF:%.*]] = fcmp oeq double [[X_ABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[IS_INF:%.*]] = fcmp oeq double [[X_ABS]], +inf
; IR-FRACT-NEXT: [[RESULT:%.*]] = select i1 [[IS_INF]], double 0.000000e+00, double [[MIN]]
; IR-FRACT-NEXT: ret double [[RESULT]]
entry:
@@ -4251,9 +4251,9 @@ define float @safe_math_fract_f32_swapped_edge_case(float %x) #0 {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
@@ -4264,7 +4264,7 @@ define float @safe_math_fract_f32_swapped_edge_case(float %x) #0 {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND8]]
;
@@ -4407,9 +4407,9 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select(float
; GFX6-IR-SAME: float [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: store float [[COND]], ptr addrspace(1) [[PTR]], align 4
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
@@ -4419,7 +4419,7 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select(float
; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: store float [[COND8]], ptr addrspace(1) [[PTR]], align 4
; IR-FRACT-NEXT: ret float [[COND8]]
@@ -4514,9 +4514,9 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp(
; GFX6-IR-SAME: float [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; GFX6-IR-NEXT: store i1 [[NOT_INF]], ptr addrspace(1) [[PTR]], align 1
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
@@ -4526,7 +4526,7 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp(
; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: store i1 [[NOT_INF]], ptr addrspace(1) [[PTR]], align 1
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND8]]
@@ -4621,10 +4621,10 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_fabs(float %x, ptr
; GFX6-IR-SAME: float [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
; GFX6-IR-NEXT: store float [[X_FABS]], ptr addrspace(1) [[PTR]], align 4
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
@@ -4634,7 +4634,7 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_fabs(float %x, ptr
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
; IR-FRACT-NEXT: store float [[X_FABS]], ptr addrspace(1) [[PTR]], align 4
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND8]]
%floor = call float @llvm.floor.f32(float %x) #3
@@ -4655,9 +4655,9 @@ define float @safe_math_fract_f32_swapped_edge_case_wrong_compared(float %x, flo
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: [[WRONG_FABS:%.*]] = call float @llvm.fabs.f32(float [[WRONG]])
-; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[WRONG_FABS]], 0x7FF0000000000000
+; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[WRONG_FABS]], +inf
; IR-NEXT: [[COND:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
@@ -4753,9 +4753,9 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_inf_check(float %x)
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[X_FABS]], 0x7FF0000000000000
+; IR-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[X_FABS]], +inf
; IR-NEXT: [[COND:%.*]] = select i1 [[IS_INF]], float 0.000000e+00, float [[MIN]]
; IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
@@ -4851,9 +4851,9 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_nan_check(float %x)
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-NEXT: [[COND:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; IR-NEXT: [[IS_NAN:%.*]] = fcmp uno float [[X]], 0.000000e+00
; IR-NEXT: [[COND8:%.*]] = select i1 [[IS_NAN]], float [[X]], float [[COND]]
@@ -4950,9 +4950,9 @@ define float @safe_math_fract_f32_swapped_edge_case_cmp_neg_inf(float %x) #0 {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0xFFF0000000000000
+; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], -inf
; IR-NEXT: [[COND:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
@@ -5013,9 +5013,9 @@ define float @basic_fract_f32_with_inf_check(float %x) {
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-NEXT: [[CLAMP_INF_TO_ZERO:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; IR-NEXT: ret float [[CLAMP_INF_TO_ZERO]]
;
@@ -5096,9 +5096,9 @@ define float @basic_fract_f32_nonans_with_inf_check(float nofpclass(nan) %x) {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = tail call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = tail call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; GFX6-IR-NEXT: [[CLAMP_INF_TO_ZERO:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: ret float [[CLAMP_INF_TO_ZERO]]
;
@@ -5107,7 +5107,7 @@ define float @basic_fract_f32_nonans_with_inf_check(float nofpclass(nan) %x) {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
; IR-FRACT-NEXT: [[MIN:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: [[CLAMP_INF_TO_ZERO:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[CLAMP_INF_TO_ZERO]]
;
@@ -5244,9 +5244,9 @@ define float @safe_math_fract_f32_swapped_edge_case_x_is_const() #0 {
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float bitcast (i32 ptrtoint (ptr @gv to i32) to float))
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float bitcast (i32 ptrtoint (ptr @gv to i32) to float), [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float bitcast (i32 ptrtoint (ptr @gv to i32) to float))
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float bitcast (i32 ptrtoint (ptr @gv to i32) to float), 0.000000e+00
; GFX6-IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float bitcast (i32 ptrtoint (ptr @gv to i32) to float)
@@ -5256,7 +5256,7 @@ define float @safe_math_fract_f32_swapped_edge_case_x_is_const() #0 {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float bitcast (i32 ptrtoint (ptr @gv to i32) to float))
; IR-FRACT-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float bitcast (i32 ptrtoint (ptr @gv to i32) to float))
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND8]]
entry:
@@ -5421,11 +5421,11 @@ define float @safe_math_fract_f32_swapped_edge_case_split_block(float %x, i1 %co
; GFX6-IR-SAME: float [[X:%.*]], i1 [[COND:%.*]]) #[[ATTR1]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
; GFX6-IR-NEXT: br i1 [[COND]], label %[[EDGE_CASES:.*]], label %[[RET:.*]]
; GFX6-IR: [[EDGE_CASES]]:
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; GFX6-IR-NEXT: [[CLAMP_INF:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[CLAMP_INF]], float [[X]]
@@ -5436,12 +5436,12 @@ define float @safe_math_fract_f32_swapped_edge_case_split_block(float %x, i1 %co
; IR-FRACT-SAME: float [[X:%.*]], i1 [[COND:%.*]]) #[[ATTR1]] {
; IR-FRACT-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; IR-FRACT-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-FRACT-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-FRACT-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-FRACT-NEXT: [[CLAMP_INF:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
; IR-FRACT-NEXT: br i1 [[COND]], label %[[EDGE_CASES:.*]], label %[[RET:.*]]
; IR-FRACT: [[EDGE_CASES]]:
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[CLAMP_INF]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND8]]
; IR-FRACT: [[RET]]:
@@ -5545,9 +5545,9 @@ define <3 x float> @safe_math_fract_f32_swapped_edge_case_vector(<3 x float> %x)
; GFX6-IR-NEXT: [[ENTRY:.*:]]
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call <3 x float> @llvm.floor.v3f32(<3 x float> [[X]])
; GFX6-IR-NEXT: [[SUB:%.*]] = fsub <3 x float> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call <3 x float> @llvm.minnum.v3f32(<3 x float> [[SUB]], <3 x float> <float 0x3FEFFFFFE0000000, float poison, float 0x3FEFFFFFE0000000>)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call <3 x float> @llvm.minnum.v3f32(<3 x float> [[SUB]], <3 x float> <float f0x3F7FFFFF, float poison, float f0x3F7FFFFF>)
; GFX6-IR-NEXT: [[X_FABS:%.*]] = call <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une <3 x float> [[X_FABS]], <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une <3 x float> [[X_FABS]], <float +inf, float poison, float +inf>
; GFX6-IR-NEXT: [[COND:%.*]] = select <3 x i1> [[NOT_INF]], <3 x float> [[MIN]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord <3 x float> [[X]], <float 0.000000e+00, float poison, float 0.000000e+00>
; GFX6-IR-NEXT: [[COND8:%.*]] = select <3 x i1> [[NOT_NAN]], <3 x float> [[COND]], <3 x float> [[X]]
@@ -5565,7 +5565,7 @@ define <3 x float> @safe_math_fract_f32_swapped_edge_case_vector(<3 x float> %x)
; IR-FRACT-NEXT: [[TMP7:%.*]] = insertelement <3 x float> [[TMP6]], float [[TMP4]], i64 1
; IR-FRACT-NEXT: [[COND:%.*]] = insertelement <3 x float> [[TMP7]], float [[TMP5]], i64 2
; IR-FRACT-NEXT: [[X_FABS:%.*]] = call <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une <3 x float> [[X_FABS]], <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une <3 x float> [[X_FABS]], <float +inf, float poison, float +inf>
; IR-FRACT-NEXT: [[COND8:%.*]] = select <3 x i1> [[NOT_INF]], <3 x float> [[COND]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>
; IR-FRACT-NEXT: ret <3 x float> [[COND8]]
entry:
@@ -5623,9 +5623,9 @@ define float @safe_math_fract_f32_swapped_edge_case_inf_check_wrong_compare(floa
; IR-NEXT: [[ENTRY:.*:]]
; IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; IR-NEXT: [[SUB:%.*]] = fsub float [[X]], [[FLOOR]]
-; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float 0x3FEFFFFFE0000000)
+; IR-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[SUB]], float f0x3F7FFFFF)
; IR-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-NEXT: [[NOT_NOT_INF:%.*]] = fcmp ule float [[X_FABS]], 0x7FF0000000000000
+; IR-NEXT: [[NOT_NOT_INF:%.*]] = fcmp ule float [[X_FABS]], +inf
; IR-NEXT: [[COND:%.*]] = select i1 [[NOT_NOT_INF]], float [[MIN]], float 0.000000e+00
; IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
@@ -5722,10 +5722,10 @@ define float @fract_pat_fcmp_oge_select(float %x, ptr addrspace(1) %iptr) #0 {
; GFX6-IR-NEXT: [[CALL:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: store float [[CALL]], ptr addrspace(1) [[IPTR]], align 4
; GFX6-IR-NEXT: [[SUB1:%.*]] = fsub float [[X]], [[CALL]]
-; GFX6-IR-NEXT: [[CMP:%.*]] = fcmp oge float [[SUB1]], 0x3FEFFFFFE0000000
-; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[CMP]], float 0x3FEFFFFFE0000000, float [[SUB1]]
+; GFX6-IR-NEXT: [[CMP:%.*]] = fcmp oge float [[SUB1]], f0x3F7FFFFF
+; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[CMP]], float f0x3F7FFFFF, float [[SUB1]]
; GFX6-IR-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; GFX6-IR-NEXT: ret float [[COND6]]
; IR-FRACT-LABEL: define float @fract_pat_fcmp_oge_select(
@@ -5735,7 +5735,7 @@ define float @fract_pat_fcmp_oge_select(float %x, ptr addrspace(1) %iptr) #0 {
; IR-FRACT-NEXT: store float [[CALL]], ptr addrspace(1) [[IPTR]], align 4
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND6]]
entry:
@@ -5828,10 +5828,10 @@ define float @fract_pat_fcmp_ogt_select(float %x, ptr addrspace(1) %iptr) #0 {
; GFX6-IR-NEXT: [[CALL:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: store float [[CALL]], ptr addrspace(1) [[IPTR]], align 4
; GFX6-IR-NEXT: [[SUB1:%.*]] = fsub float [[X]], [[CALL]]
-; GFX6-IR-NEXT: [[CMP:%.*]] = fcmp ogt float [[SUB1]], 0x3FEFFFFFE0000000
-; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[CMP]], float 0x3FEFFFFFE0000000, float [[SUB1]]
+; GFX6-IR-NEXT: [[CMP:%.*]] = fcmp ogt float [[SUB1]], f0x3F7FFFFF
+; GFX6-IR-NEXT: [[COND:%.*]] = select i1 [[CMP]], float f0x3F7FFFFF, float [[SUB1]]
; GFX6-IR-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; GFX6-IR-NEXT: ret float [[COND6]]
; IR-FRACT-LABEL: define float @fract_pat_fcmp_ogt_select(
@@ -5841,7 +5841,7 @@ define float @fract_pat_fcmp_ogt_select(float %x, ptr addrspace(1) %iptr) #0 {
; IR-FRACT-NEXT: store float [[CALL]], ptr addrspace(1) [[IPTR]], align 4
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND6]]
entry:
@@ -5939,10 +5939,10 @@ define float @negative_fract_pat_fcmp_olt(float %x, ptr addrspace(1) %iptr) #0 {
; IR-NEXT: [[CALL:%.*]] = call float @llvm.floor.f32(float noundef [[X]])
; IR-NEXT: store float [[CALL]], ptr addrspace(1) [[IPTR]], align 4
; IR-NEXT: [[SUB1:%.*]] = fsub float [[X]], [[CALL]]
-; IR-NEXT: [[CMP:%.*]] = fcmp olt float [[SUB1]], 0x3FEFFFFFE0000000
-; IR-NEXT: [[COND:%.*]] = select i1 [[CMP]], float [[SUB1]], float 0x3FEFFFFFE0000000
+; IR-NEXT: [[CMP:%.*]] = fcmp olt float [[SUB1]], f0x3F7FFFFF
+; IR-NEXT: [[COND:%.*]] = select i1 [[CMP]], float [[SUB1]], float f0x3F7FFFFF
; IR-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], 0x7FF0000000000000
+; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-NEXT: ret float [[COND6]]
entry:
@@ -6039,10 +6039,10 @@ define float @fract_pat_fcmp_olt_not_nan_src(float nofpclass(nan) %x, ptr addrsp
; IR-NEXT: [[CALL:%.*]] = call float @llvm.floor.f32(float noundef [[X]])
; IR-NEXT: store float [[CALL]], ptr addrspace(1) [[IPTR]], align 4
; IR-NEXT: [[SUB1:%.*]] = fsub float [[X]], [[CALL]]
-; IR-NEXT: [[CMP:%.*]] = fcmp olt float [[SUB1]], 0x3FEFFFFFE0000000
-; IR-NEXT: [[COND:%.*]] = select i1 [[CMP]], float [[SUB1]], float 0x3FEFFFFFE0000000
+; IR-NEXT: [[CMP:%.*]] = fcmp olt float [[SUB1]], f0x3F7FFFFF
+; IR-NEXT: [[COND:%.*]] = select i1 [[CMP]], float [[SUB1]], float f0x3F7FFFFF
; IR-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], 0x7FF0000000000000
+; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-NEXT: ret float [[COND6]]
entry:
@@ -6139,9 +6139,9 @@ define float @fract_pat_minimum(float %x, ptr addrspace(1) %iptr) #0 {
; GFX6-IR-NEXT: [[CALL:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: store float [[CALL]], ptr addrspace(1) [[IPTR]], align 4
; GFX6-IR-NEXT: [[SUB1:%.*]] = fsub float [[X]], [[CALL]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minimum.f32(float [[SUB1]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minimum.f32(float [[SUB1]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], 0x7FF0000000000000
+; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: ret float [[COND6]]
; IR-FRACT-LABEL: define float @fract_pat_minimum(
@@ -6151,7 +6151,7 @@ define float @fract_pat_minimum(float %x, ptr addrspace(1) %iptr) #0 {
; IR-FRACT-NEXT: store float [[CALL]], ptr addrspace(1) [[IPTR]], align 4
; IR-FRACT-NEXT: [[MIN:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], 0x7FF0000000000000
+; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND6]]
entry:
@@ -6205,8 +6205,8 @@ define float @core_fract_pat_fcmp_oge_select(float %x) #0 {
; GFX6-IR-SAME: float [[X:%.*]]) #[[ATTR1]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB_FLOOR:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[OGE_MIN_CONST:%.*]] = fcmp oge float [[SUB_FLOOR]], 0x3FEFFFFFE0000000
-; GFX6-IR-NEXT: [[SELECT:%.*]] = select i1 [[OGE_MIN_CONST]], float 0x3FEFFFFFE0000000, float [[SUB_FLOOR]]
+; GFX6-IR-NEXT: [[OGE_MIN_CONST:%.*]] = fcmp oge float [[SUB_FLOOR]], f0x3F7FFFFF
+; GFX6-IR-NEXT: [[SELECT:%.*]] = select i1 [[OGE_MIN_CONST]], float f0x3F7FFFFF, float [[SUB_FLOOR]]
; GFX6-IR-NEXT: ret float [[SELECT]]
; IR-FRACT-LABEL: define float @core_fract_pat_fcmp_oge_select(
; IR-FRACT-SAME: float [[X:%.*]]) #[[ATTR1]] {
@@ -6262,7 +6262,7 @@ define float @core_fract_pat_minimum(float %x) #0 {
; GFX6-IR-SAME: float [[X:%.*]]) #[[ATTR1]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
; GFX6-IR-NEXT: [[SUB_FLOOR:%.*]] = fsub float [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minimum.f32(float [[SUB_FLOOR]], float 0x3FEFFFFFE0000000)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minimum.f32(float [[SUB_FLOOR]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
; IR-FRACT-LABEL: define float @core_fract_pat_minimum(
; IR-FRACT-SAME: float [[X:%.*]]) #[[ATTR1]] {
@@ -6320,8 +6320,8 @@ define <2 x float> @core_fract_pat_fcmp_oge_select_v2f32(<2 x float> %x) #0 {
; GFX6-IR-SAME: <2 x float> [[X:%.*]]) #[[ATTR1]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[X]])
; GFX6-IR-NEXT: [[SUB_FLOOR:%.*]] = fsub <2 x float> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[OGE_MIN_CONST:%.*]] = fcmp oge <2 x float> [[SUB_FLOOR]], <float 0x3FEFFFFFE0000000, float poison>
-; GFX6-IR-NEXT: [[SELECT:%.*]] = select <2 x i1> [[OGE_MIN_CONST]], <2 x float> <float 0x3FEFFFFFE0000000, float poison>, <2 x float> [[SUB_FLOOR]]
+; GFX6-IR-NEXT: [[OGE_MIN_CONST:%.*]] = fcmp oge <2 x float> [[SUB_FLOOR]], <float f0x3F7FFFFF, float poison>
+; GFX6-IR-NEXT: [[SELECT:%.*]] = select <2 x i1> [[OGE_MIN_CONST]], <2 x float> <float f0x3F7FFFFF, float poison>, <2 x float> [[SUB_FLOOR]]
; GFX6-IR-NEXT: ret <2 x float> [[SELECT]]
; IR-FRACT-LABEL: define <2 x float> @core_fract_pat_fcmp_oge_select_v2f32(
; IR-FRACT-SAME: <2 x float> [[X:%.*]]) #[[ATTR1]] {
@@ -6387,7 +6387,7 @@ define <2 x float> @core_fract_pat_minimum_v2f32(<2 x float> %x) #0 {
; GFX6-IR-SAME: <2 x float> [[X:%.*]]) #[[ATTR1]] {
; GFX6-IR-NEXT: [[FLOOR:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[X]])
; GFX6-IR-NEXT: [[SUB_FLOOR:%.*]] = fsub <2 x float> [[X]], [[FLOOR]]
-; GFX6-IR-NEXT: [[MIN:%.*]] = call <2 x float> @llvm.minimum.v2f32(<2 x float> [[SUB_FLOOR]], <2 x float> <float 0x3FEFFFFFE0000000, float poison>)
+; GFX6-IR-NEXT: [[MIN:%.*]] = call <2 x float> @llvm.minimum.v2f32(<2 x float> [[SUB_FLOOR]], <2 x float> <float f0x3F7FFFFF, float poison>)
; GFX6-IR-NEXT: ret <2 x float> [[MIN]]
; IR-FRACT-LABEL: define <2 x float> @core_fract_pat_minimum_v2f32(
; IR-FRACT-SAME: <2 x float> [[X:%.*]]) #[[ATTR1]] {
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll b/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
index 8a61b8f5eeda5..23e5e8b454658 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
@@ -463,7 +463,7 @@ define amdgpu_ps float @global_atomic_fmin_uni_address_uni_value_agent_scope_uns
; IR-NEXT: [[TMP13:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP11]], [[TMP10]] ]
; IR-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.readfirstlane.f32(float [[TMP13]])
; IR-NEXT: [[TMP15:%.*]] = uitofp i32 [[TMP8]] to float
-; IR-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], float 0x7FF8000000000000, float [[VAL]]
+; IR-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], float +qnan, float [[VAL]]
; IR-NEXT: [[TMP17:%.*]] = call float @llvm.minnum.f32(float [[TMP14]], float [[TMP16]])
; IR-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], float [[TMP14]], float [[TMP17]]
; IR-NEXT: br label [[TMP19]]
@@ -501,7 +501,7 @@ define amdgpu_ps float @global_atomic_fmin_uni_address_div_value_agent_scope_uns
; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP16]], [[TMP12]] ]
; IR-ITERATIVE-NEXT: ret float [[TMP18]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP23]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ +qnan, [[TMP2]] ], [ [[TMP23]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP22]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP26:%.*]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
@@ -528,20 +528,20 @@ define amdgpu_ps float @global_atomic_fmin_uni_address_div_value_agent_scope_uns
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0)
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]])
-; IR-DPP-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.set.inactive.f32(float [[VAL:%.*]], float 0x7FF8000000000000)
-; IR-DPP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP9]], i32 273, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.set.inactive.f32(float [[VAL:%.*]], float +qnan)
+; IR-DPP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP9]], i32 273, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP11:%.*]] = call float @llvm.minnum.f32(float [[TMP9]], float [[TMP10]])
-; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP11]], i32 274, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP11]], i32 274, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP13:%.*]] = call float @llvm.minnum.f32(float [[TMP11]], float [[TMP12]])
-; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP13]], i32 276, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP13]], i32 276, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.minnum.f32(float [[TMP13]], float [[TMP14]])
-; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP15]], i32 280, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP15]], i32 280, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.minnum.f32(float [[TMP15]], float [[TMP16]])
-; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP17]], i32 322, i32 10, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP17]], i32 322, i32 10, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.minnum.f32(float [[TMP17]], float [[TMP18]])
-; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP19]], i32 323, i32 12, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP19]], i32 323, i32 12, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.minnum.f32(float [[TMP19]], float [[TMP20]])
-; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP21]], i32 312, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP21]], i32 312, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[TMP21]], i32 63)
; IR-DPP-NEXT: [[TMP24:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP23]])
; IR-DPP-NEXT: [[TMP25:%.*]] = icmp eq i32 [[TMP8]], 0
@@ -584,7 +584,7 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_uni_value_agent_scope_uns
; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP11]], [[TMP10]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.readfirstlane.f32(float [[TMP13]]) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], float 0x7FF8000000000000, float [[VAL]]
+; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], float +qnan, float [[VAL]]
; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP14]], float [[TMP16]], metadata !"fpexcept.strict") #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], float [[TMP14]], float [[TMP17]]
; IR-ITERATIVE-NEXT: br label [[TMP19]]
@@ -611,7 +611,7 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_uni_value_agent_scope_uns
; IR-DPP-NEXT: [[TMP13:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP11]], [[TMP10]] ]
; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.readfirstlane.f32(float [[TMP13]]) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], float 0x7FF8000000000000, float [[VAL]]
+; IR-DPP-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], float +qnan, float [[VAL]]
; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP14]], float [[TMP16]], metadata !"fpexcept.strict") #[[ATTR8]]
; IR-DPP-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], float [[TMP14]], float [[TMP17]]
; IR-DPP-NEXT: br label [[TMP19]]
@@ -649,7 +649,7 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_div_value_agent_scope_uns
; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP16]], [[TMP12]] ]
; IR-ITERATIVE-NEXT: ret float [[TMP18]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP23]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ +qnan, [[TMP2]] ], [ [[TMP23]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP22]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP26:%.*]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
@@ -676,20 +676,20 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_div_value_agent_scope_uns
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.set.inactive.f32(float [[VAL:%.*]], float 0x7FF8000000000000) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP9]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.set.inactive.f32(float [[VAL:%.*]], float +qnan) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP9]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP11:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP9]], float [[TMP10]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP11]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP11]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP13:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP11]], float [[TMP12]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP13]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP13]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP13]], float [[TMP14]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP15]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP15]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP15]], float [[TMP16]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP17]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP17]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP17]], float [[TMP18]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP19]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP19]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP19]], float [[TMP20]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP21]], i32 312, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP21]], i32 312, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[TMP21]], i32 63) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP24:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP23]]) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP25:%.*]] = icmp eq i32 [[TMP8]], 0
@@ -1433,7 +1433,7 @@ define amdgpu_ps double @global_atomic_fmin_double_uni_address_uni_value_agent_s
; IR-NEXT: [[TMP13:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP11]], [[TMP10]] ]
; IR-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.readfirstlane.f64(double [[TMP13]])
; IR-NEXT: [[TMP15:%.*]] = uitofp i32 [[TMP8]] to double
-; IR-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], double 0x7FF8000000000000, double [[VAL]]
+; IR-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], double +qnan, double [[VAL]]
; IR-NEXT: [[TMP17:%.*]] = call double @llvm.minnum.f64(double [[TMP14]], double [[TMP16]])
; IR-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], double [[TMP14]], double [[TMP17]]
; IR-NEXT: br label [[TMP19]]
@@ -1471,7 +1471,7 @@ define amdgpu_ps double @global_atomic_fmin_double_uni_address_div_value_agent_s
; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP16]], [[TMP12]] ]
; IR-ITERATIVE-NEXT: ret double [[TMP18]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi double [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP23]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi double [ +qnan, [[TMP2]] ], [ [[TMP23]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP22]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP26:%.*]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
@@ -1498,20 +1498,20 @@ define amdgpu_ps double @global_atomic_fmin_double_uni_address_div_value_agent_s
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0)
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]])
-; IR-DPP-NEXT: [[TMP9:%.*]] = call double @llvm.amdgcn.set.inactive.f64(double [[VAL:%.*]], double 0x7FF8000000000000)
-; IR-DPP-NEXT: [[TMP10:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP9]], i32 273, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP9:%.*]] = call double @llvm.amdgcn.set.inactive.f64(double [[VAL:%.*]], double +qnan)
+; IR-DPP-NEXT: [[TMP10:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP9]], i32 273, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP11:%.*]] = call double @llvm.minnum.f64(double [[TMP9]], double [[TMP10]])
-; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP11]], i32 274, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP11]], i32 274, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP13:%.*]] = call double @llvm.minnum.f64(double [[TMP11]], double [[TMP12]])
-; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP13]], i32 276, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP13]], i32 276, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP15:%.*]] = call double @llvm.minnum.f64(double [[TMP13]], double [[TMP14]])
-; IR-DPP-NEXT: [[TMP16:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP15]], i32 280, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP16:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP15]], i32 280, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP17:%.*]] = call double @llvm.minnum.f64(double [[TMP15]], double [[TMP16]])
-; IR-DPP-NEXT: [[TMP18:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP17]], i32 322, i32 10, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP18:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP17]], i32 322, i32 10, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP19:%.*]] = call double @llvm.minnum.f64(double [[TMP17]], double [[TMP18]])
-; IR-DPP-NEXT: [[TMP20:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP19]], i32 323, i32 12, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP20:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP19]], i32 323, i32 12, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP21:%.*]] = call double @llvm.minnum.f64(double [[TMP19]], double [[TMP20]])
-; IR-DPP-NEXT: [[TMP22:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP21]], i32 312, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP22:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP21]], i32 312, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP23:%.*]] = call double @llvm.amdgcn.readlane.f64(double [[TMP21]], i32 63)
; IR-DPP-NEXT: [[TMP24:%.*]] = call double @llvm.amdgcn.strict.wwm.f64(double [[TMP23]])
; IR-DPP-NEXT: [[TMP25:%.*]] = icmp eq i32 [[TMP8]], 0
@@ -1554,7 +1554,7 @@ define amdgpu_ps double @global_atomic__fmax_double_uni_address_uni_value_agent_
; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP11]], [[TMP10]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.readfirstlane.f64(double [[TMP13]]) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], double 0x7FF8000000000000, double [[VAL]]
+; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], double +qnan, double [[VAL]]
; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP14]], double [[TMP16]], metadata !"fpexcept.strict") #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], double [[TMP14]], double [[TMP17]]
; IR-ITERATIVE-NEXT: br label [[TMP19]]
@@ -1581,7 +1581,7 @@ define amdgpu_ps double @global_atomic__fmax_double_uni_address_uni_value_agent_
; IR-DPP-NEXT: [[TMP13:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP11]], [[TMP10]] ]
; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.readfirstlane.f64(double [[TMP13]]) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP15:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], double 0x7FF8000000000000, double [[VAL]]
+; IR-DPP-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], double +qnan, double [[VAL]]
; IR-DPP-NEXT: [[TMP17:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP14]], double [[TMP16]], metadata !"fpexcept.strict") #[[ATTR8]]
; IR-DPP-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], double [[TMP14]], double [[TMP17]]
; IR-DPP-NEXT: br label [[TMP19]]
@@ -1619,7 +1619,7 @@ define amdgpu_ps double @global_atomic__fmax_double_uni_address_div_value_agent_
; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP16]], [[TMP12]] ]
; IR-ITERATIVE-NEXT: ret double [[TMP18]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi double [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP23]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi double [ +qnan, [[TMP2]] ], [ [[TMP23]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP22]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP26:%.*]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
@@ -1646,20 +1646,20 @@ define amdgpu_ps double @global_atomic__fmax_double_uni_address_div_value_agent_
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP9:%.*]] = call double @llvm.amdgcn.set.inactive.f64(double [[VAL:%.*]], double 0x7FF8000000000000) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP10:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP9]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call double @llvm.amdgcn.set.inactive.f64(double [[VAL:%.*]], double +qnan) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP9]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP11:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP9]], double [[TMP10]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP11]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP11]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP13:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP11]], double [[TMP12]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP13]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP13]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP15:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP13]], double [[TMP14]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP15]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP16:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP15]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP17:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP15]], double [[TMP16]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP18:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP17]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP18:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP17]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP19:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP17]], double [[TMP18]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP20:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP19]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP20:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP19]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP21:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP19]], double [[TMP20]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP22:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP21]], i32 312, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP22:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP21]], i32 312, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP23:%.*]] = call double @llvm.amdgcn.readlane.f64(double [[TMP21]], i32 63) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP24:%.*]] = call double @llvm.amdgcn.strict.wwm.f64(double [[TMP23]]) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP25:%.*]] = icmp eq i32 [[TMP8]], 0
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
index 8587ab3fdb3af..bac9aed5ec40f 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
@@ -412,7 +412,7 @@ define amdgpu_ps void @global_atomic_fmin_uni_address_div_value_agent_scope_unsa
; IR-ITERATIVE: 13:
; IR-ITERATIVE-NEXT: ret void
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ +qnan, [[TMP2]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP20:%.*]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32
@@ -437,18 +437,18 @@ define amdgpu_ps void @global_atomic_fmin_uni_address_div_value_agent_scope_unsa
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0)
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]])
-; IR-DPP-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.set.inactive.f32(float [[VAL:%.*]], float 0x7FF8000000000000)
-; IR-DPP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP9]], i32 273, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.set.inactive.f32(float [[VAL:%.*]], float +qnan)
+; IR-DPP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP9]], i32 273, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP11:%.*]] = call float @llvm.minnum.f32(float [[TMP9]], float [[TMP10]])
-; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP11]], i32 274, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP11]], i32 274, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP13:%.*]] = call float @llvm.minnum.f32(float [[TMP11]], float [[TMP12]])
-; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP13]], i32 276, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP13]], i32 276, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.minnum.f32(float [[TMP13]], float [[TMP14]])
-; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP15]], i32 280, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP15]], i32 280, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.minnum.f32(float [[TMP15]], float [[TMP16]])
-; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP17]], i32 322, i32 10, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP17]], i32 322, i32 10, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.minnum.f32(float [[TMP17]], float [[TMP18]])
-; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP19]], i32 323, i32 12, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP19]], i32 323, i32 12, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.minnum.f32(float [[TMP19]], float [[TMP20]])
; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[TMP21]], i32 63)
; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP22]])
@@ -532,7 +532,7 @@ define amdgpu_ps void @global_atomic_fmax_uni_address_div_value_agent_scope_unsa
; IR-ITERATIVE: 13:
; IR-ITERATIVE-NEXT: ret void
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ +qnan, [[TMP2]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP20:%.*]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32
@@ -557,18 +557,18 @@ define amdgpu_ps void @global_atomic_fmax_uni_address_div_value_agent_scope_unsa
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.set.inactive.f32(float [[VAL:%.*]], float 0x7FF8000000000000) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP9]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call float @llvm.amdgcn.set.inactive.f32(float [[VAL:%.*]], float +qnan) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP9]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP11:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP9]], float [[TMP10]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP11]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP11]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP13:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP11]], float [[TMP12]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP13]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP13]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP13]], float [[TMP14]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP15]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP15]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP15]], float [[TMP16]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP17]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP17]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP17]], float [[TMP18]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float 0x7FF8000000000000, float [[TMP19]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float +qnan, float [[TMP19]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP19]], float [[TMP20]], metadata !"fpexcept.strict") #[[ATTR8]]
; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[TMP21]], i32 63) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP22]]) #[[ATTR8]]
@@ -1228,7 +1228,7 @@ define amdgpu_ps void @global_atomic_fmin_double_uni_address_div_value_agent_sco
; IR-ITERATIVE: 13:
; IR-ITERATIVE-NEXT: ret void
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi double [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi double [ +qnan, [[TMP2]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP20:%.*]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32
@@ -1253,18 +1253,18 @@ define amdgpu_ps void @global_atomic_fmin_double_uni_address_div_value_agent_sco
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0)
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]])
-; IR-DPP-NEXT: [[TMP9:%.*]] = call double @llvm.amdgcn.set.inactive.f64(double [[VAL:%.*]], double 0x7FF8000000000000)
-; IR-DPP-NEXT: [[TMP10:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP9]], i32 273, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP9:%.*]] = call double @llvm.amdgcn.set.inactive.f64(double [[VAL:%.*]], double +qnan)
+; IR-DPP-NEXT: [[TMP10:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP9]], i32 273, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP11:%.*]] = call double @llvm.minnum.f64(double [[TMP9]], double [[TMP10]])
-; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP11]], i32 274, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP11]], i32 274, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP13:%.*]] = call double @llvm.minnum.f64(double [[TMP11]], double [[TMP12]])
-; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP13]], i32 276, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP13]], i32 276, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP15:%.*]] = call double @llvm.minnum.f64(double [[TMP13]], double [[TMP14]])
-; IR-DPP-NEXT: [[TMP16:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP15]], i32 280, i32 15, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP16:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP15]], i32 280, i32 15, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP17:%.*]] = call double @llvm.minnum.f64(double [[TMP15]], double [[TMP16]])
-; IR-DPP-NEXT: [[TMP18:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP17]], i32 322, i32 10, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP18:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP17]], i32 322, i32 10, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP19:%.*]] = call double @llvm.minnum.f64(double [[TMP17]], double [[TMP18]])
-; IR-DPP-NEXT: [[TMP20:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP19]], i32 323, i32 12, i32 15, i1 false)
+; IR-DPP-NEXT: [[TMP20:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP19]], i32 323, i32 12, i32 15, i1 false)
; IR-DPP-NEXT: [[TMP21:%.*]] = call double @llvm.minnum.f64(double [[TMP19]], double [[TMP20]])
; IR-DPP-NEXT: [[TMP22:%.*]] = call double @llvm.amdgcn.readlane.f64(double [[TMP21]], i32 63)
; IR-DPP-NEXT: [[TMP23:%.*]] = call double @llvm.amdgcn.strict.wwm.f64(double [[TMP22]])
@@ -1348,7 +1348,7 @@ define amdgpu_ps void @global_atomic_fmax_double_uni_address_div_value_agent_sco
; IR-ITERATIVE: 13:
; IR-ITERATIVE-NEXT: ret void
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi double [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi double [ +qnan, [[TMP2]] ], [ [[TMP17]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP20:%.*]], [[COMPUTELOOP]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32
@@ -1373,18 +1373,18 @@ define amdgpu_ps void @global_atomic_fmax_double_uni_address_div_value_agent_sco
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP9:%.*]] = call double @llvm.amdgcn.set.inactive.f64(double [[VAL:%.*]], double 0x7FF8000000000000) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP10:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP9]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call double @llvm.amdgcn.set.inactive.f64(double [[VAL:%.*]], double +qnan) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP9]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP11:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP9]], double [[TMP10]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP11]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP11]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP13:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP11]], double [[TMP12]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP13]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP14:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP13]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP15:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP13]], double [[TMP14]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP15]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP16:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP15]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP17:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP15]], double [[TMP16]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP18:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP17]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP18:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP17]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP19:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP17]], double [[TMP18]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP20:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double 0x7FF8000000000000, double [[TMP19]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP20:%.*]] = call double @llvm.amdgcn.update.dpp.f64(double +qnan, double [[TMP19]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP21:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP19]], double [[TMP20]], metadata !"fpexcept.strict") #[[ATTR8]]
; IR-DPP-NEXT: [[TMP22:%.*]] = call double @llvm.amdgcn.readlane.f64(double [[TMP21]], i32 63) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP23:%.*]] = call double @llvm.amdgcn.strict.wwm.f64(double [[TMP22]]) #[[ATTR8]]
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds.ll
index a6c87d4e972f5..2f1cb6adf72a7 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds.ll
@@ -25,7 +25,7 @@
; Use in func rewritten to access struct at address zero
; CHECK-LABEL: @func()
-; CHECK: %dec = atomicrmw fsub ptr addrspace(3) @llvm.amdgcn.module.lds, float 1.0
+; CHECK: %dec = atomicrmw fsub ptr addrspace(3) @llvm.amdgcn.module.lds, float 1.000000e+00
; CHECK: %val0 = load i32, ptr addrspace(3) getelementptr inbounds (%llvm.amdgcn.module.lds.t, ptr addrspace(3) @llvm.amdgcn.module.lds, i32 0, i32 2), align 8
; CHECK: %val1 = add i32 %val0, 4
; CHECK: store i32 %val1, ptr addrspace(3) getelementptr inbounds (%llvm.amdgcn.module.lds.t, ptr addrspace(3) @llvm.amdgcn.module.lds, i32 0, i32 2), align 8
diff --git a/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll b/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
index d6cc833c8c73f..d250c5ab42559 100644
--- a/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
+++ b/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
@@ -727,7 +727,7 @@ bb5: ; preds = %bb3
; IR-NEXT: br i1 false, label %DummyReturnBlock, label %[[LOOP]]
; IR: [[EXP]]:
-; IR-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> <half 0xH3C00, half 0xH0000>, <2 x half> <half 0xH0000, half 0xH3C00>, i1 true, i1 true)
+; IR-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> <half 1.000000e+00, half 0.000000e+00>, <2 x half> <half 0.000000e+00, half 1.000000e+00>, i1 true, i1 true)
; IR-NEXT: ret void
; IR: DummyReturnBlock:
diff --git a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
index 5ce30cbc8c015..9e88a62925e50 100644
--- a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
+++ b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
@@ -254,8 +254,8 @@ define amdgpu_kernel void @nested_loop_conditions(ptr addrspace(1) captures(none
; IR-NEXT: [[MY_TMP23:%.*]] = lshr i32 [[MY_TMP22]], 16
; IR-NEXT: [[MY_TMP24:%.*]] = select i1 false, i32 0, i32 [[MY_TMP23]]
; IR-NEXT: [[MY_TMP25:%.*]] = uitofp i32 [[MY_TMP24]] to float
-; IR-NEXT: [[MY_TMP26:%.*]] = fmul float [[MY_TMP25]], 0x3EF0001000000000
-; IR-NEXT: [[MY_TMP27:%.*]] = fsub float [[MY_TMP26]], 0x7FF8000000000000
+; IR-NEXT: [[MY_TMP26:%.*]] = fmul float [[MY_TMP25]], f0x37800080
+; IR-NEXT: [[MY_TMP27:%.*]] = fsub float [[MY_TMP26]], +qnan
; IR-NEXT: [[MY_TMP28:%.*]] = fcmp olt float [[MY_TMP27]], 5.000000e-01
; IR-NEXT: [[MY_TMP29:%.*]] = select i1 [[MY_TMP28]], i64 1, i64 2
; IR-NEXT: [[MY_TMP30:%.*]] = extractelement <4 x i32> [[MY_TMP936]], i64 [[MY_TMP29]]
diff --git a/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll b/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
index 7a627733e12c2..5f733ca7fe1ab 100644
--- a/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
+++ b/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
@@ -130,7 +130,7 @@ define half @is_profitable_f16_preserve(ptr dereferenceable(8) %ptr_x, ptr deref
; GFX-SAME: ptr dereferenceable(8) [[PTR_X:%.*]], ptr dereferenceable(8) [[PTR_Y:%.*]], ptr dereferenceable(8) [[PTR_A:%.*]]) #[[ATTR0]] {
; GFX-NEXT: [[ENTRY:.*:]]
; GFX-NEXT: [[Y:%.*]] = load half, ptr [[PTR_Y]], align 8
-; GFX-NEXT: [[CMP:%.*]] = fcmp oeq half [[Y]], 0xH0000
+; GFX-NEXT: [[CMP:%.*]] = fcmp oeq half [[Y]], 0.000000e+00
; GFX-NEXT: [[X:%.*]] = load half, ptr [[PTR_X]], align 8
; GFX-NEXT: [[A_1:%.*]] = load half, ptr [[PTR_A]], align 8
; GFX-NEXT: [[MUL:%.*]] = fmul contract half [[X]], [[A_1]]
@@ -169,7 +169,7 @@ define half @is_profitable_f16_ieee(ptr dereferenceable(8) %ptr_x, ptr dereferen
; GFX-SAME: ptr dereferenceable(8) [[PTR_X:%.*]], ptr dereferenceable(8) [[PTR_Y:%.*]], ptr dereferenceable(8) [[PTR_A:%.*]]) #[[ATTR1:[0-9]+]] {
; GFX-NEXT: [[ENTRY:.*:]]
; GFX-NEXT: [[Y:%.*]] = load half, ptr [[PTR_Y]], align 8
-; GFX-NEXT: [[CMP:%.*]] = fcmp oeq half [[Y]], 0xH0000
+; GFX-NEXT: [[CMP:%.*]] = fcmp oeq half [[Y]], 0.000000e+00
; GFX-NEXT: [[X:%.*]] = load half, ptr [[PTR_X]], align 8
; GFX-NEXT: [[A_1:%.*]] = load half, ptr [[PTR_A]], align 8
; GFX-NEXT: [[MUL:%.*]] = fmul contract half [[X]], [[A_1]]
@@ -208,7 +208,7 @@ define bfloat @is_profitable_bfloat_preserve(ptr dereferenceable(8) %ptr_x, ptr
; GFX-SAME: ptr dereferenceable(8) [[PTR_X:%.*]], ptr dereferenceable(8) [[PTR_Y:%.*]], ptr dereferenceable(8) [[PTR_A:%.*]]) #[[ATTR0]] {
; GFX-NEXT: [[ENTRY:.*:]]
; GFX-NEXT: [[Y:%.*]] = load bfloat, ptr [[PTR_Y]], align 8
-; GFX-NEXT: [[CMP:%.*]] = fcmp oeq bfloat [[Y]], 0xR0000
+; GFX-NEXT: [[CMP:%.*]] = fcmp oeq bfloat [[Y]], 0.000000e+00
; GFX-NEXT: [[X:%.*]] = load bfloat, ptr [[PTR_X]], align 8
; GFX-NEXT: [[A_1:%.*]] = load bfloat, ptr [[PTR_A]], align 8
; GFX-NEXT: [[MUL:%.*]] = fmul contract bfloat [[X]], [[A_1]]
@@ -217,7 +217,7 @@ define bfloat @is_profitable_bfloat_preserve(ptr dereferenceable(8) %ptr_x, ptr
; GFX-NEXT: [[COMMON_RET_OP:%.*]] = phi bfloat [ [[MUL]], %[[IF_THEN]] ], [ [[SUB:%.*]], %[[IF_ELSE]] ]
; GFX-NEXT: ret bfloat [[COMMON_RET_OP]]
; GFX: [[IF_THEN]]:
-; GFX-NEXT: [[ADD:%.*]] = fadd contract bfloat 0xR3F80, [[MUL]]
+; GFX-NEXT: [[ADD:%.*]] = fadd contract bfloat 1.000000e+00, [[MUL]]
; GFX-NEXT: br label %[[COMMON_RET]]
; GFX: [[IF_ELSE]]:
; GFX-NEXT: [[SUB]] = fsub contract bfloat [[MUL]], [[Y]]
@@ -247,7 +247,7 @@ define bfloat @is_profitable_bfloat_ieee(ptr dereferenceable(8) %ptr_x, ptr dere
; GFX-SAME: ptr dereferenceable(8) [[PTR_X:%.*]], ptr dereferenceable(8) [[PTR_Y:%.*]], ptr dereferenceable(8) [[PTR_A:%.*]]) #[[ATTR1]] {
; GFX-NEXT: [[ENTRY:.*:]]
; GFX-NEXT: [[Y:%.*]] = load bfloat, ptr [[PTR_Y]], align 8
-; GFX-NEXT: [[CMP:%.*]] = fcmp oeq bfloat [[Y]], 0xR0000
+; GFX-NEXT: [[CMP:%.*]] = fcmp oeq bfloat [[Y]], 0.000000e+00
; GFX-NEXT: [[X:%.*]] = load bfloat, ptr [[PTR_X]], align 8
; GFX-NEXT: [[A_1:%.*]] = load bfloat, ptr [[PTR_A]], align 8
; GFX-NEXT: [[MUL:%.*]] = fmul contract bfloat [[X]], [[A_1]]
@@ -256,7 +256,7 @@ define bfloat @is_profitable_bfloat_ieee(ptr dereferenceable(8) %ptr_x, ptr dere
; GFX-NEXT: [[COMMON_RET_OP:%.*]] = phi bfloat [ [[MUL]], %[[IF_THEN]] ], [ [[SUB:%.*]], %[[IF_ELSE]] ]
; GFX-NEXT: ret bfloat [[COMMON_RET_OP]]
; GFX: [[IF_THEN]]:
-; GFX-NEXT: [[ADD:%.*]] = fadd contract bfloat 0xR3F80, [[MUL]]
+; GFX-NEXT: [[ADD:%.*]] = fadd contract bfloat 1.000000e+00, [[MUL]]
; GFX-NEXT: br label %[[COMMON_RET]]
; GFX: [[IF_ELSE]]:
; GFX-NEXT: [[SUB]] = fsub contract bfloat [[MUL]], [[Y]]
diff --git a/llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll b/llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
index 18e2d3d11265b..9d3a84216c586 100644
--- a/llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
@@ -453,7 +453,7 @@ define bfloat @atomicrmw_fadd_private_bf16(ptr addrspace(5) %ptr) {
; IR-LABEL: define bfloat @atomicrmw_fadd_private_bf16(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load bfloat, ptr addrspace(5) [[PTR]], align 2
-; IR-NEXT: [[NEW:%.*]] = fadd bfloat [[TMP1]], 0xR4000
+; IR-NEXT: [[NEW:%.*]] = fadd bfloat [[TMP1]], 2.000000e+00
; IR-NEXT: store bfloat [[NEW]], ptr addrspace(5) [[PTR]], align 2
; IR-NEXT: ret bfloat [[TMP1]]
;
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
index 62a04f3a6f86f..902eccf9e22d0 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
@@ -379,14 +379,14 @@ define void @store_2xi32_into_double(double %foo) {
; CHECK-LABEL: define void @store_2xi32_into_double
; CHECK-SAME: (double [[FOO:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <9 x double> poison
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <9 x double> [[ALLOCA]], double 0x5F0000005E, i32 0
-; CHECK-NEXT: [[DUMMYUSER0:%.*]] = freeze double 0x5F0000005E
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <9 x double> [[TMP1]], double 0x6700000066, i32 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <9 x double> [[TMP2]], double 0x6900000068, i32 5
-; CHECK-NEXT: [[DUMMYUSER1:%.*]] = freeze double 0x6700000066
-; CHECK-NEXT: [[DUMMYUSER2:%.*]] = freeze double 0x6900000068
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <9 x double> [[TMP3]], double 0x6F0000006E, i32 8
-; CHECK-NEXT: [[DUMMYUSER3:%.*]] = freeze double 0x6F0000006E
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <9 x double> [[ALLOCA]], double f0x0000005F0000005E, i32 0
+; CHECK-NEXT: [[DUMMYUSER0:%.*]] = freeze double f0x0000005F0000005E
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <9 x double> [[TMP1]], double f0x0000006700000066, i32 4
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <9 x double> [[TMP2]], double f0x0000006900000068, i32 5
+; CHECK-NEXT: [[DUMMYUSER1:%.*]] = freeze double f0x0000006700000066
+; CHECK-NEXT: [[DUMMYUSER2:%.*]] = freeze double f0x0000006900000068
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <9 x double> [[TMP3]], double f0x0000006F0000006E, i32 8
+; CHECK-NEXT: [[DUMMYUSER3:%.*]] = freeze double f0x0000006F0000006E
; CHECK-NEXT: ret void
;
%alloca = alloca [9 x double], align 8, addrspace(5)
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
index aaec725f85890..e815c41ae7ef4 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
@@ -71,7 +71,7 @@ entry:
; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c00
; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s[[[SL]]:[[SH]]]
-; OPT: %0 = extractelement <4 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400>, i32 %sel2
+; OPT: %0 = extractelement <4 x half> <half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00>, i32 %sel2
; OPT: store half %0, ptr addrspace(1) %out, align 2
define amdgpu_kernel void @half4_alloca_store4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {
@@ -97,7 +97,7 @@ entry:
; GCN: s_mov_b64 s[{{[0-9:]+}}], 0xffff
; OPT: %alloca = freeze <4 x half> poison
-; OPT: %0 = insertelement <4 x half> %alloca, half 0xH3C00, i32 %sel2
+; OPT: %0 = insertelement <4 x half> %alloca, half 1.000000e+00, i32 %sel2
; OPT: store <4 x half> %0, ptr addrspace(1) %out, align 2
define amdgpu_kernel void @half4_alloca_load4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {
diff --git a/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll b/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
index 5eb864310414c..a4d28c94daa89 100644
--- a/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
+++ b/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
@@ -436,7 +436,7 @@ declare <2 x half> @_Z3powDv2_DhS_(<2 x half>, <2 x half>)
; GCN-LABEL: define half @test_pow_fast_f16__y_13(half %x)
; GCN: %__fabs = tail call fast half @llvm.fabs.f16(half %x)
; GCN: %__log2 = tail call fast half @llvm.log2.f16(half %__fabs)
-; GCN: %__ylogx = fmul fast half %__log2, 0xH4A80
+; GCN: %__ylogx = fmul fast half %__log2, 1.300000e+01
; GCN: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) half @llvm.exp2.f16(half %__ylogx)
; GCN: %__pow_sign1 = tail call fast half @llvm.copysign.f16(half %__exp2, half %x)
define half @test_pow_fast_f16__y_13(half %x) {
@@ -447,7 +447,7 @@ define half @test_pow_fast_f16__y_13(half %x) {
; GCN-LABEL: define <2 x half> @test_pow_fast_v2f16__y_13(<2 x half> %x)
; GCN: %__fabs = tail call fast <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
; GCN: %__log2 = tail call fast <2 x half> @llvm.log2.v2f16(<2 x half> %__fabs)
-; GCN: %__ylogx = fmul fast <2 x half> %__log2, splat (half 0xH4A80)
+; GCN: %__ylogx = fmul fast <2 x half> %__log2, splat (half 1.300000e+01)
; GCN: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) <2 x half> @llvm.exp2.v2f16(<2 x half> %__ylogx)
; GCN: %__pow_sign1 = tail call fast <2 x half> @llvm.copysign.v2f16(<2 x half> %__exp2, <2 x half> %x)
define <2 x half> @test_pow_fast_v2f16__y_13(<2 x half> %x) {
diff --git a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
index 26d8a047e6541..ef110379efc2e 100644
--- a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
+++ b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
@@ -224,7 +224,7 @@ define hidden void @blam() {
; SI-OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]])
; SI-OPT-NEXT: br label [[BB1]]
; SI-OPT: bb10:
-; SI-OPT-NEXT: store float 0x7FF8000000000000, ptr addrspace(5) null, align 16
+; SI-OPT-NEXT: store float +qnan, ptr addrspace(5) null, align 16
; SI-OPT-NEXT: br label [[BB18:%.*]]
; SI-OPT: bb11:
; SI-OPT-NEXT: [[TMP12:%.*]] = call float @spam()
@@ -242,13 +242,13 @@ define hidden void @blam() {
; SI-OPT-NEXT: br i1 [[TMP10]], label [[BB17:%.*]], label [[BB16:%.*]]
; SI-OPT: bb16:
; SI-OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP11]])
-; SI-OPT-NEXT: store float 0x7FF8000000000000, ptr addrspace(5) null, align 16
+; SI-OPT-NEXT: store float +qnan, ptr addrspace(5) null, align 16
; SI-OPT-NEXT: br label [[BB17]]
; SI-OPT: bb17:
; SI-OPT-NEXT: store float [[TMP]], ptr addrspace(5) null, align 16
; SI-OPT-NEXT: br label [[BB18]]
; SI-OPT: bb18:
-; SI-OPT-NEXT: store float 0x7FF8000000000000, ptr addrspace(5) null, align 4
+; SI-OPT-NEXT: store float +qnan, ptr addrspace(5) null, align 4
; SI-OPT-NEXT: br label [[BB2]]
;
; GCN-LABEL: blam:
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index a35f82722adaf..70d8cdfb65153 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -632,7 +632,7 @@ body: |
bb.0:
liveins:
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.25
+ ; HARD: [[R:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.250000e+00
; SOFT-NOT: G_FCONSTANT
; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1080033280
; SOFT-NOT: G_FCONSTANT
@@ -663,7 +663,7 @@ body: |
; SOFT_POOL: id: 1
; SOFT_POOL: value: i32 858993459
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_FCONSTANT double -2.4
+ ; HARD: [[R:%[0-9]+]]:_(s64) = G_FCONSTANT double -2.400000e+00
; SOFT-NOT: G_FCONSTANT
; SOFT_CONST-DAG: [[HI:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1073532109
; SOFT_CONST-DAG: [[LO:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
diff --git a/llvm/test/CodeGen/ARM/vector-promotion.ll b/llvm/test/CodeGen/ARM/vector-promotion.ll
index 344014ad80449..41fff7823f765 100644
--- a/llvm/test/CodeGen/ARM/vector-promotion.ll
+++ b/llvm/test/CodeGen/ARM/vector-promotion.ll
@@ -201,7 +201,7 @@ define void @sremCase(ptr %addr1, ptr %dest) {
; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
-; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fdiv float [[EXTRACT]], 7.0
+; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fdiv float [[EXTRACT]], 7.000000e+00
; Vector version:
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = fdiv <2 x float> [[LOAD]], splat (float 7.000000e+00)
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
@@ -220,7 +220,7 @@ define void @fdivCase(ptr %addr1, ptr %dest) {
; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
-; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem float [[EXTRACT]], 7.0
+; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem float [[EXTRACT]], 7.000000e+00
; Vector version:
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = frem <2 x float> [[LOAD]], splat (float 7.000000e+00)
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
@@ -274,7 +274,7 @@ define void @undefRemCase(ptr %addr1, ptr %dest) {
; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
-; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem nnan float [[EXTRACT]], 7.0
+; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem nnan float [[EXTRACT]], 7.000000e+00
; Vector version:
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = frem nnan <2 x float> [[LOAD]], <float poison, float 7.000000e+00>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
@@ -317,7 +317,7 @@ define void @undefVectorFRemCaseWithFastMath(ptr %addr1, ptr %dest) {
; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
-; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fadd float [[EXTRACT]], 1.0
+; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fadd float [[EXTRACT]], 1.000000e+00
; Vector version:
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = fadd <2 x float> [[LOAD]], <float poison, float 1.000000e+00>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
diff --git a/llvm/test/CodeGen/DirectX/MemIntrinsics/memset.ll b/llvm/test/CodeGen/DirectX/MemIntrinsics/memset.ll
index fcb9899506167..2dea9f277ad6b 100644
--- a/llvm/test/CodeGen/DirectX/MemIntrinsics/memset.ll
+++ b/llvm/test/CodeGen/DirectX/MemIntrinsics/memset.ll
@@ -21,9 +21,9 @@ define void @replace_half_memset_test() #0 {
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [2 x half], align 4
; CHECK-NEXT: [[GEP:%.*]] = getelementptr [2 x half], ptr [[ACCUM_I_FLAT]], i32 0, i32 0
-; CHECK-NEXT: store half 0xH0000, ptr [[GEP]], align 2
+; CHECK-NEXT: store half 0.000000e+00, ptr [[GEP]], align 2
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr [2 x half], ptr [[ACCUM_I_FLAT]], i32 0, i32 1
-; CHECK-NEXT: store half 0xH0000, ptr [[GEP1]], align 2
+; CHECK-NEXT: store half 0.000000e+00, ptr [[GEP1]], align 2
; CHECK-NEXT: ret void
;
%accum.i.flat = alloca [2 x half], align 4
diff --git a/llvm/test/CodeGen/DirectX/all.ll b/llvm/test/CodeGen/DirectX/all.ll
index 1c0b6486dc935..444672705a410 100644
--- a/llvm/test/CodeGen/DirectX/all.ll
+++ b/llvm/test/CodeGen/DirectX/all.ll
@@ -51,7 +51,7 @@ entry:
}
; CHECK-LABEL: all_half
-; CHECK: fcmp une half %{{.*}}, 0xH0000
+; CHECK: fcmp une half %{{.*}}, 0.000000e+00
define noundef i1 @all_half(half noundef %p0) {
entry:
%dx.all = call i1 @llvm.dx.all.f16(half %p0)
diff --git a/llvm/test/CodeGen/DirectX/any.ll b/llvm/test/CodeGen/DirectX/any.ll
index e32aa389a81a5..c530a05992f36 100644
--- a/llvm/test/CodeGen/DirectX/any.ll
+++ b/llvm/test/CodeGen/DirectX/any.ll
@@ -71,7 +71,7 @@ entry:
}
; CHECK-LABEL: any_half
-; CHECK: fcmp une half %{{.*}}, 0xH0000
+; CHECK: fcmp une half %{{.*}}, 0.000000e+00
define noundef i1 @any_half(half noundef %p0) {
entry:
%p0.addr = alloca half, align 2
diff --git a/llvm/test/CodeGen/DirectX/atan2.ll b/llvm/test/CodeGen/DirectX/atan2.ll
index 8f51ab1b7a902..192189118a4da 100644
--- a/llvm/test/CodeGen/DirectX/atan2.ll
+++ b/llvm/test/CodeGen/DirectX/atan2.ll
@@ -8,8 +8,8 @@ entry:
; CHECK: [[DIV:%.+]] = fdiv float %y, %x
; EXPCHECK: [[ATAN:%.+]] = call float @llvm.atan.f32(float [[DIV]])
; DOPCHECK: [[ATAN:%.+]] = call float @dx.op.unary.f32(i32 17, float [[DIV]])
-; CHECK-DAG: [[ADD_PI:%.+]] = fadd float [[ATAN]], 0x400921FB60000000
-; CHECK-DAG: [[SUB_PI:%.+]] = fsub float [[ATAN]], 0x400921FB60000000
+; CHECK-DAG: [[ADD_PI:%.+]] = fadd float [[ATAN]], f0x40490FDB
+; CHECK-DAG: [[SUB_PI:%.+]] = fsub float [[ATAN]], f0x40490FDB
; CHECK-DAG: [[X_LT_0:%.+]] = fcmp olt float %x, 0.000000e+00
; CHECK-DAG: [[X_EQ_0:%.+]] = fcmp oeq float %x, 0.000000e+00
; CHECK-DAG: [[Y_GE_0:%.+]] = fcmp oge float %y, 0.000000e+00
@@ -19,9 +19,9 @@ entry:
; CHECK: [[XLT0_AND_YLT0:%.+]] = and i1 [[X_LT_0]], [[Y_LT_0]]
; CHECK: [[SELECT_SUB_PI:%.+]] = select i1 [[XLT0_AND_YLT0]], float [[SUB_PI]], float [[SELECT_ADD_PI]]
; CHECK: [[XEQ0_AND_YLT0:%.+]] = and i1 [[X_EQ_0]], [[Y_LT_0]]
-; CHECK: [[SELECT_NEGHPI:%.+]] = select i1 [[XEQ0_AND_YLT0]], float 0xBFF921FB60000000, float [[SELECT_SUB_PI]]
+; CHECK: [[SELECT_NEGHPI:%.+]] = select i1 [[XEQ0_AND_YLT0]], float f0xBFC90FDB, float [[SELECT_SUB_PI]]
; CHECK: [[XEQ0_AND_YGE0:%.+]] = and i1 [[X_EQ_0]], [[Y_GE_0]]
-; CHECK: [[SELECT_HPI:%.+]] = select i1 [[XEQ0_AND_YGE0]], float 0x3FF921FB60000000, float [[SELECT_NEGHPI]]
+; CHECK: [[SELECT_HPI:%.+]] = select i1 [[XEQ0_AND_YGE0]], float f0x3FC90FDB, float [[SELECT_NEGHPI]]
; CHECK: ret float [[SELECT_HPI]]
%elt.atan2 = call float @llvm.atan2.f32(float %y, float %x)
ret float %elt.atan2
@@ -32,20 +32,20 @@ entry:
; CHECK: [[DIV:%.+]] = fdiv half %y, %x
; EXPCHECK: [[ATAN:%.+]] = call half @llvm.atan.f16(half [[DIV]])
; DOPCHECK: [[ATAN:%.+]] = call half @dx.op.unary.f16(i32 17, half [[DIV]])
-; CHECK-DAG: [[ADD_PI:%.+]] = fadd half [[ATAN]], 0xH4248
-; CHECK-DAG: [[SUB_PI:%.+]] = fsub half [[ATAN]], 0xH4248
-; CHECK-DAG: [[X_LT_0:%.+]] = fcmp olt half %x, 0xH0000
-; CHECK-DAG: [[X_EQ_0:%.+]] = fcmp oeq half %x, 0xH0000
-; CHECK-DAG: [[Y_GE_0:%.+]] = fcmp oge half %y, 0xH0000
-; CHECK-DAG: [[Y_LT_0:%.+]] = fcmp olt half %y, 0xH0000
+; CHECK-DAG: [[ADD_PI:%.+]] = fadd half [[ATAN]], 3.140630e+00
+; CHECK-DAG: [[SUB_PI:%.+]] = fsub half [[ATAN]], 3.140630e+00
+; CHECK-DAG: [[X_LT_0:%.+]] = fcmp olt half %x, 0.000000e+00
+; CHECK-DAG: [[X_EQ_0:%.+]] = fcmp oeq half %x, 0.000000e+00
+; CHECK-DAG: [[Y_GE_0:%.+]] = fcmp oge half %y, 0.000000e+00
+; CHECK-DAG: [[Y_LT_0:%.+]] = fcmp olt half %y, 0.000000e+00
; CHECK: [[XLT0_AND_YGE0:%.+]] = and i1 [[X_LT_0]], [[Y_GE_0]]
; CHECK: [[SELECT_ADD_PI:%.+]] = select i1 [[XLT0_AND_YGE0]], half [[ADD_PI]], half [[ATAN]]
; CHECK: [[XLT0_AND_YLT0:%.+]] = and i1 [[X_LT_0]], [[Y_LT_0]]
; CHECK: [[SELECT_SUB_PI:%.+]] = select i1 [[XLT0_AND_YLT0]], half [[SUB_PI]], half [[SELECT_ADD_PI]]
; CHECK: [[XEQ0_AND_YLT0:%.+]] = and i1 [[X_EQ_0]], [[Y_LT_0]]
-; CHECK: [[SELECT_NEGHPI:%.+]] = select i1 [[XEQ0_AND_YLT0]], half 0xHBE48, half [[SELECT_SUB_PI]]
+; CHECK: [[SELECT_NEGHPI:%.+]] = select i1 [[XEQ0_AND_YLT0]], half -1.570310e+00, half [[SELECT_SUB_PI]]
; CHECK: [[XEQ0_AND_YGE0:%.+]] = and i1 [[X_EQ_0]], [[Y_GE_0]]
-; CHECK: [[SELECT_HPI:%.+]] = select i1 [[XEQ0_AND_YGE0]], half 0xH3E48, half [[SELECT_NEGHPI]]
+; CHECK: [[SELECT_HPI:%.+]] = select i1 [[XEQ0_AND_YGE0]], half 1.570310e+00, half [[SELECT_NEGHPI]]
; CHECK: ret half [[SELECT_HPI]]
%elt.atan2 = call half @llvm.atan2.f16(half %y, half %x)
ret half %elt.atan2
@@ -56,8 +56,8 @@ entry:
; Just Expansion, no scalarization or lowering:
; EXPCHECK: [[DIV:%.+]] = fdiv <4 x float> %y, %x
; EXPCHECK: [[ATAN:%.+]] = call <4 x float> @llvm.atan.v4f32(<4 x float> [[DIV]])
-; EXPCHECK-DAG: [[ADD_PI:%.+]] = fadd <4 x float> [[ATAN]], splat (float 0x400921FB60000000)
-; EXPCHECK-DAG: [[SUB_PI:%.+]] = fsub <4 x float> [[ATAN]], splat (float 0x400921FB60000000)
+; EXPCHECK-DAG: [[ADD_PI:%.+]] = fadd <4 x float> [[ATAN]], splat (float f0x40490FDB)
+; EXPCHECK-DAG: [[SUB_PI:%.+]] = fsub <4 x float> [[ATAN]], splat (float f0x40490FDB)
; EXPCHECK-DAG: [[X_LT_0:%.+]] = fcmp olt <4 x float> %x, zeroinitializer
; EXPCHECK-DAG: [[X_EQ_0:%.+]] = fcmp oeq <4 x float> %x, zeroinitializer
; EXPCHECK-DAG: [[Y_GE_0:%.+]] = fcmp oge <4 x float> %y, zeroinitializer
@@ -67,9 +67,9 @@ entry:
; EXPCHECK: [[XLT0_AND_YLT0:%.+]] = and <4 x i1> [[X_LT_0]], [[Y_LT_0]]
; EXPCHECK: [[SELECT_SUB_PI:%.+]] = select <4 x i1> [[XLT0_AND_YLT0]], <4 x float> [[SUB_PI]], <4 x float> [[SELECT_ADD_PI]]
; EXPCHECK: [[XEQ0_AND_YLT0:%.+]] = and <4 x i1> [[X_EQ_0]], [[Y_LT_0]]
-; EXPCHECK: [[SELECT_NEGHPI:%.+]] = select <4 x i1> [[XEQ0_AND_YLT0]], <4 x float> splat (float 0xBFF921FB60000000), <4 x float> [[SELECT_SUB_PI]]
+; EXPCHECK: [[SELECT_NEGHPI:%.+]] = select <4 x i1> [[XEQ0_AND_YLT0]], <4 x float> splat (float f0xBFC90FDB), <4 x float> [[SELECT_SUB_PI]]
; EXPCHECK: [[XEQ0_AND_YGE0:%.+]] = and <4 x i1> [[X_EQ_0]], [[Y_GE_0]]
-; EXPCHECK: [[SELECT_HPI:%.+]] = select <4 x i1> [[XEQ0_AND_YGE0]], <4 x float> splat (float 0x3FF921FB60000000), <4 x float> [[SELECT_NEGHPI]]
+; EXPCHECK: [[SELECT_HPI:%.+]] = select <4 x i1> [[XEQ0_AND_YGE0]], <4 x float> splat (float f0x3FC90FDB), <4 x float> [[SELECT_NEGHPI]]
; EXPCHECK: ret <4 x float> [[SELECT_HPI]]
; Scalarization occurs after expansion, so atan scalarization is tested separately.
diff --git a/llvm/test/CodeGen/DirectX/degrees.ll b/llvm/test/CodeGen/DirectX/degrees.ll
index b38ac13d5f24e..ebb5511afcc54 100644
--- a/llvm/test/CodeGen/DirectX/degrees.ll
+++ b/llvm/test/CodeGen/DirectX/degrees.ll
@@ -6,7 +6,7 @@ define noundef half @degrees_half(half noundef %a) {
; CHECK-LABEL: define noundef half @degrees_half(
; CHECK-SAME: half noundef [[A:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[DX_DEGREES1:%.*]] = fmul half [[A]], 0xH5329
+; CHECK-NEXT: [[DX_DEGREES1:%.*]] = fmul half [[A]], 5.728130e+01
; CHECK-NEXT: ret half [[DX_DEGREES1]]
;
entry:
@@ -18,7 +18,7 @@ define noundef float @degrees_float(float noundef %a) #0 {
; CHECK-LABEL: define noundef float @degrees_float(
; CHECK-SAME: float noundef [[A:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[DEGREES:%.*]] = fmul float [[A]], 0x404CA5DC20000000
+; CHECK-NEXT: [[DEGREES:%.*]] = fmul float [[A]], f0x42652EE1
; CHECK-NEXT: ret float [[DEGREES]]
;
entry:
@@ -31,13 +31,13 @@ define noundef <4 x float> @degrees_float4(<4 x float> noundef %a) #0 {
; CHECK-SAME: <4 x float> noundef [[A:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A]], i64 0
-; CHECK-NEXT: [[DEGREES_A0:%.*]] = fmul float [[A0]], 0x404CA5DC20000000
+; CHECK-NEXT: [[DEGREES_A0:%.*]] = fmul float [[A0]], f0x42652EE1
; CHECK-NEXT: [[A1:%.*]] = extractelement <4 x float> [[A]], i64 1
-; CHECK-NEXT: [[DEGREES_A1:%.*]] = fmul float [[A1]], 0x404CA5DC20000000
+; CHECK-NEXT: [[DEGREES_A1:%.*]] = fmul float [[A1]], f0x42652EE1
; CHECK-NEXT: [[A2:%.*]] = extractelement <4 x float> [[A]], i64 2
-; CHECK-NEXT: [[DEGREES_A2:%.*]] = fmul float [[A2]], 0x404CA5DC20000000
+; CHECK-NEXT: [[DEGREES_A2:%.*]] = fmul float [[A2]], f0x42652EE1
; CHECK-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i64 3
-; CHECK-NEXT: [[DEGREES_A3:%.*]] = fmul float [[A3]], 0x404CA5DC20000000
+; CHECK-NEXT: [[DEGREES_A3:%.*]] = fmul float [[A3]], f0x42652EE1
; CHECK-NEXT: [[INSERT_0:%.*]] = insertelement <4 x float> poison, float [[DEGREES_A0]], i64 0
; CHECK-NEXT: [[INSERT_1:%.*]] = insertelement <4 x float> [[INSERT_0]], float [[DEGREES_A1]], i64 1
; CHECK-NEXT: [[INSERT_2:%.*]] = insertelement <4 x float> [[INSERT_1]], float [[DEGREES_A2]], i64 2
diff --git a/llvm/test/CodeGen/DirectX/exp-vec.ll b/llvm/test/CodeGen/DirectX/exp-vec.ll
index a32af34aa133b..5385a23b67f5b 100644
--- a/llvm/test/CodeGen/DirectX/exp-vec.ll
+++ b/llvm/test/CodeGen/DirectX/exp-vec.ll
@@ -3,7 +3,7 @@
; Make sure dxil operation function calls for exp are generated for float and half.
; CHECK-LABEL: exp_float4
-; CHECK: fmul <4 x float> splat (float 0x3FF7154760000000), %{{.*}}
+; CHECK: fmul <4 x float> splat (float f0x3FB8AA3B), %{{.*}}
; CHECK: call <4 x float> @llvm.exp2.v4f32(<4 x float> %{{.*}})
define noundef <4 x float> @exp_float4(<4 x float> noundef %p0) {
entry:
diff --git a/llvm/test/CodeGen/DirectX/exp.ll b/llvm/test/CodeGen/DirectX/exp.ll
index 3719e05b9da37..4bd9f7d5f24c9 100644
--- a/llvm/test/CodeGen/DirectX/exp.ll
+++ b/llvm/test/CodeGen/DirectX/exp.ll
@@ -3,7 +3,7 @@
; Make sure dxil operation function calls for exp are generated for float and half.
; CHECK-LABEL: exp_float
-; CHECK: fmul float 0x3FF7154760000000, %{{.*}}
+; CHECK: fmul float f0x3FB8AA3B, %{{.*}}
; CHECK: call float @dx.op.unary.f32(i32 21, float %{{.*}})
define noundef float @exp_float(float noundef %a) {
entry:
@@ -15,7 +15,7 @@ entry:
}
; CHECK-LABEL: exp_half
-; CHECK: fmul half 0xH3DC5, %{{.*}}
+; CHECK: fmul half 1.442380e+00, %{{.*}}
; CHECK: call half @dx.op.unary.f16(i32 21, half %{{.*}})
; Function Attrs: noinline nounwind optnone
define noundef half @exp_half(half noundef %a) {
diff --git a/llvm/test/CodeGen/DirectX/log-vec.ll b/llvm/test/CodeGen/DirectX/log-vec.ll
index 8f9cd093b7308..65eff845cedc3 100644
--- a/llvm/test/CodeGen/DirectX/log-vec.ll
+++ b/llvm/test/CodeGen/DirectX/log-vec.ll
@@ -4,7 +4,7 @@
; CHECK-LABEL: log_float4
; CHECK: call <4 x float> @llvm.log2.v4f32(<4 x float> %{{.*}})
-; CHECK: fmul <4 x float> splat (float 0x3FE62E4300000000), %{{.*}}
+; CHECK: fmul <4 x float> splat (float f0x3F317218), %{{.*}}
define noundef <4 x float> @log_float4(<4 x float> noundef %p0) {
entry:
%p0.addr = alloca <4 x float>, align 16
@@ -16,7 +16,7 @@ entry:
; CHECK-LABEL: log10_float4
; CHECK: call <4 x float> @llvm.log2.v4f32(<4 x float> %{{.*}})
-; CHECK: fmul <4 x float> splat (float 0x3FD3441340000000), %{{.*}}
+; CHECK: fmul <4 x float> splat (float f0x3E9A209A), %{{.*}}
define noundef <4 x float> @log10_float4(<4 x float> noundef %p0) {
entry:
%p0.addr = alloca <4 x float>, align 16
diff --git a/llvm/test/CodeGen/DirectX/log.ll b/llvm/test/CodeGen/DirectX/log.ll
index 97f7d015e401d..2fa0504c21254 100644
--- a/llvm/test/CodeGen/DirectX/log.ll
+++ b/llvm/test/CodeGen/DirectX/log.ll
@@ -7,7 +7,7 @@ define noundef float @log_float(float noundef %a) #0 {
entry:
; DOPCHECK: call float @dx.op.unary.f32(i32 23, float %{{.*}})
; EXPCHECK: call float @llvm.log2.f32(float %a)
-; CHECK: fmul float 0x3FE62E4300000000, %{{.*}}
+; CHECK: fmul float f0x3F317218, %{{.*}}
%elt.log = call float @llvm.log.f32(float %a)
ret float %elt.log
}
@@ -16,7 +16,7 @@ define noundef half @log_half(half noundef %a) #0 {
entry:
; DOPCHECK: call half @dx.op.unary.f16(i32 23, half %{{.*}})
; EXPCHECK: call half @llvm.log2.f16(half %a)
-; CHECK: fmul half 0xH398C, %{{.*}}
+; CHECK: fmul half 6.933590e-01, %{{.*}}
%elt.log = call half @llvm.log.f16(half %a)
ret half %elt.log
}
diff --git a/llvm/test/CodeGen/DirectX/log10.ll b/llvm/test/CodeGen/DirectX/log10.ll
index bcef3a28cd73f..894cbc3e357eb 100644
--- a/llvm/test/CodeGen/DirectX/log10.ll
+++ b/llvm/test/CodeGen/DirectX/log10.ll
@@ -7,7 +7,7 @@ define noundef float @log10_float(float noundef %a) #0 {
entry:
; DOPCHECK: call float @dx.op.unary.f32(i32 23, float %{{.*}})
; EXPCHECK: call float @llvm.log2.f32(float %a)
-; CHECK: fmul float 0x3FD3441340000000, %{{.*}}
+; CHECK: fmul float f0x3E9A209A, %{{.*}}
%elt.log10 = call float @llvm.log10.f32(float %a)
ret float %elt.log10
}
@@ -16,7 +16,7 @@ define noundef half @log10_half(half noundef %a) #0 {
entry:
; DOPCHECK: call half @dx.op.unary.f16(i32 23, half %{{.*}})
; EXPCHECK: call half @llvm.log2.f16(half %a)
-; CHECK: fmul half 0xH34D1, %{{.*}}
+; CHECK: fmul half 3.010250e-01, %{{.*}}
%elt.log10 = call half @llvm.log10.f16(half %a)
ret half %elt.log10
}
diff --git a/llvm/test/CodeGen/DirectX/radians.ll b/llvm/test/CodeGen/DirectX/radians.ll
index f31585cead376..0e78b35ae3265 100644
--- a/llvm/test/CodeGen/DirectX/radians.ll
+++ b/llvm/test/CodeGen/DirectX/radians.ll
@@ -11,7 +11,7 @@ define noundef half @radians_half(half noundef %a) {
; CHECK-LABEL: define noundef half @radians_half(
; CHECK-SAME: half noundef [[A:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = fmul half [[A]], 0xH2478
+; CHECK-NEXT: [[TMP0:%.*]] = fmul half [[A]], 1.745610e-02
; CHECK-NEXT: ret half [[TMP0]]
;
entry:
@@ -23,7 +23,7 @@ define noundef float @radians_float(float noundef %a) {
; CHECK-LABEL: define noundef float @radians_float(
; CHECK-SAME: float noundef [[A:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = fmul float [[A]], 0x3F91DF46A0000000
+; CHECK-NEXT: [[TMP0:%.*]] = fmul float [[A]], f0x3C8EFA35
; CHECK-NEXT: ret float [[TMP0]]
;
entry:
@@ -36,13 +36,13 @@ define noundef <4 x half> @radians_half_vector(<4 x half> noundef %a) {
; CHECK-SAME: <4 x half> noundef [[A:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK: [[ee0:%.*]] = extractelement <4 x half> [[A]], i64 0
-; CHECK: [[ie0:%.*]] = fmul half [[ee0]], 0xH2478
+; CHECK: [[ie0:%.*]] = fmul half [[ee0]], 1.745610e-02
; CHECK: [[ee1:%.*]] = extractelement <4 x half> [[A]], i64 1
-; CHECK: [[ie1:%.*]] = fmul half [[ee1]], 0xH2478
+; CHECK: [[ie1:%.*]] = fmul half [[ee1]], 1.745610e-02
; CHECK: [[ee2:%.*]] = extractelement <4 x half> [[A]], i64 2
-; CHECK: [[ie2:%.*]] = fmul half [[ee2]], 0xH2478
+; CHECK: [[ie2:%.*]] = fmul half [[ee2]], 1.745610e-02
; CHECK: [[ee3:%.*]] = extractelement <4 x half> [[A]], i64 3
-; CHECK: [[ie3:%.*]] = fmul half [[ee3]], 0xH2478
+; CHECK: [[ie3:%.*]] = fmul half [[ee3]], 1.745610e-02
; CHECK: [[TMP0:%.*]] = insertelement <4 x half> poison, half [[ie0]], i64 0
; CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half [[ie1]], i64 1
; CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half [[ie2]], i64 2
@@ -59,13 +59,13 @@ define noundef <4 x float> @radians_float_vector(<4 x float> noundef %a) {
; CHECK-SAME: <4 x float> noundef [[A:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK: [[ee0:%.*]] = extractelement <4 x float> [[A]], i64 0
-; CHECK: [[ie0:%.*]] = fmul float [[ee0]], 0x3F91DF46A0000000
+; CHECK: [[ie0:%.*]] = fmul float [[ee0]], f0x3C8EFA35
; CHECK: [[ee1:%.*]] = extractelement <4 x float> [[A]], i64 1
-; CHECK: [[ie1:%.*]] = fmul float [[ee1]], 0x3F91DF46A0000000
+; CHECK: [[ie1:%.*]] = fmul float [[ee1]], f0x3C8EFA35
; CHECK: [[ee2:%.*]] = extractelement <4 x float> [[A]], i64 2
-; CHECK: [[ie2:%.*]] = fmul float [[ee2]], 0x3F91DF46A0000000
+; CHECK: [[ie2:%.*]] = fmul float [[ee2]], f0x3C8EFA35
; CHECK: [[ee3:%.*]] = extractelement <4 x float> [[A]], i64 3
-; CHECK: [[ie3:%.*]] = fmul float [[ee3]], 0x3F91DF46A0000000
+; CHECK: [[ie3:%.*]] = fmul float [[ee3]], f0x3C8EFA35
; CHECK: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[ie0]], i64 0
; CHECK: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[ie1]], i64 1
; CHECK: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[ie2]], i64 2
diff --git a/llvm/test/CodeGen/DirectX/sign.ll b/llvm/test/CodeGen/DirectX/sign.ll
index 47e51b28d2084..60b9b537271a4 100644
--- a/llvm/test/CodeGen/DirectX/sign.ll
+++ b/llvm/test/CodeGen/DirectX/sign.ll
@@ -6,8 +6,8 @@ define noundef i32 @sign_half(half noundef %a) {
; CHECK-LABEL: define noundef i32 @sign_half(
; CHECK-SAME: half noundef [[A:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt half 0xH0000, [[A]]
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt half [[A]], 0xH0000
+; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt half 0.000000e+00, [[A]]
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt half [[A]], 0.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP0]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]]
diff --git a/llvm/test/CodeGen/DirectX/step.ll b/llvm/test/CodeGen/DirectX/step.ll
index 1d2329e97073b..7dbd59d55e2b1 100644
--- a/llvm/test/CodeGen/DirectX/step.ll
+++ b/llvm/test/CodeGen/DirectX/step.ll
@@ -16,7 +16,7 @@ declare <4 x float> @llvm.dx.step.v4f32(<4 x float>, <4 x float>)
define noundef half @test_step_half(half noundef %p0, half noundef %p1) {
entry:
; CHECK: %0 = fcmp olt half %p1, %p0
- ; CHECK: %1 = select i1 %0, half 0xH0000, half 0xH3C00
+ ; CHECK: %1 = select i1 %0, half 0.000000e+00, half 1.000000e+00
%hlsl.step = call half @llvm.dx.step.f16(half %p0, half %p1)
ret half %hlsl.step
}
@@ -24,7 +24,7 @@ entry:
define noundef <2 x half> @test_step_half2(<2 x half> noundef %p0, <2 x half> noundef %p1) {
entry:
; CHECK: %0 = fcmp olt <2 x half> %p1, %p0
- ; CHECK: %1 = select <2 x i1> %0, <2 x half> zeroinitializer, <2 x half> splat (half 0xH3C00)
+ ; CHECK: %1 = select <2 x i1> %0, <2 x half> zeroinitializer, <2 x half> splat (half 1.000000e+00)
%hlsl.step = call <2 x half> @llvm.dx.step.v2f16(<2 x half> %p0, <2 x half> %p1)
ret <2 x half> %hlsl.step
}
@@ -32,7 +32,7 @@ entry:
define noundef <3 x half> @test_step_half3(<3 x half> noundef %p0, <3 x half> noundef %p1) {
entry:
; CHECK: %0 = fcmp olt <3 x half> %p1, %p0
- ; CHECK: %1 = select <3 x i1> %0, <3 x half> zeroinitializer, <3 x half> splat (half 0xH3C00)
+ ; CHECK: %1 = select <3 x i1> %0, <3 x half> zeroinitializer, <3 x half> splat (half 1.000000e+00)
%hlsl.step = call <3 x half> @llvm.dx.step.v3f16(<3 x half> %p0, <3 x half> %p1)
ret <3 x half> %hlsl.step
}
@@ -40,7 +40,7 @@ entry:
define noundef <4 x half> @test_step_half4(<4 x half> noundef %p0, <4 x half> noundef %p1) {
entry:
; CHECK: %0 = fcmp olt <4 x half> %p1, %p0
- ; CHECK: %1 = select <4 x i1> %0, <4 x half> zeroinitializer, <4 x half> splat (half 0xH3C00)
+ ; CHECK: %1 = select <4 x i1> %0, <4 x half> zeroinitializer, <4 x half> splat (half 1.000000e+00)
%hlsl.step = call <4 x half> @llvm.dx.step.v4f16(<4 x half> %p0, <4 x half> %p1)
ret <4 x half> %hlsl.step
}
diff --git a/llvm/test/CodeGen/DirectX/vector_reduce_add.ll b/llvm/test/CodeGen/DirectX/vector_reduce_add.ll
index d4ee16a24cb45..9aba036b6e946 100644
--- a/llvm/test/CodeGen/DirectX/vector_reduce_add.ll
+++ b/llvm/test/CodeGen/DirectX/vector_reduce_add.ll
@@ -22,7 +22,7 @@ define noundef half @test_length_half2_start1(<2 x half> noundef %p0) {
; CHECK-SAME: <2 x half> noundef [[P0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x half> [[P0]], i64 0
-; CHECK-NEXT: [[TMP1:%.*]] = fadd half [[TMP0]], 0xH0001
+; CHECK-NEXT: [[TMP1:%.*]] = fadd half [[TMP0]], 5.960460e-08
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x half> [[P0]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fadd half [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret half [[TMP3]]
diff --git a/llvm/test/CodeGen/MIR/Generic/bfloat-immediates.mir b/llvm/test/CodeGen/MIR/Generic/bfloat-immediates.mir
index c4e035a4f095c..13a16cdb0299f 100644
--- a/llvm/test/CodeGen/MIR/Generic/bfloat-immediates.mir
+++ b/llvm/test/CodeGen/MIR/Generic/bfloat-immediates.mir
@@ -5,8 +5,8 @@
name: bfloat_immediates
body: |
bb.0:
- ; CHECK: %0:_(s16) = G_FCONSTANT bfloat 0xR3E80
- ; CHECK: %1:_(s16) = G_FCONSTANT bfloat 0xR3E80
+ ; CHECK: %0:_(s16) = G_FCONSTANT bfloat 2.500000e-01
+ ; CHECK: %1:_(s16) = G_FCONSTANT bfloat 2.500000e-01
%0:_(s16) = G_FCONSTANT bfloat 0xR3E80
%1:_(s16) = G_FCONSTANT bfloat 0.25
...
diff --git a/llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
index 3158916a3195c..b057b51c99a00 100644
--- a/llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
+++ b/llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
@@ -69,11 +69,11 @@ body: |
%0 = LD_i32 0, 0, 4, 2, 32, -1, &test2_param_0, 0
%1 = CVT_f64_f32 %0, 0
%2 = LD_i32 0, 0, 4, 0, 32, -1, &test2_param_1, 0
- ; CHECK: %3:b64 = FADD_rnf64ri %1, double 0x7FF8000000000000
+ ; CHECK: %3:b64 = FADD_rnf64ri %1, double +qnan
%3 = FADD_rnf64ri %1, double 0x7FF8000000000000
%4 = CVT_f32_f64 %3, 5
%5 = CVT_f32_s32 %2, 5
- ; CHECK: %6:b32 = FADD_rnf32ri %5, float 0x7FF8000000000000
+ ; CHECK: %6:b32 = FADD_rnf32ri %5, float +qnan
%6 = FADD_rnf32ri %5, float 0x7FF8000000000000, 0
%7 = FMUL_rnf32rr %6, %4, 0
ST_i32 %7, 0, 0, 101, 32, &func_retval0, 0 :: (store (s32), addrspace 101)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir
index 923c41ecaafd0..3fbe8da170324 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir
@@ -15,11 +15,11 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_single_precision
- ; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4005BF0A80000000
+ ; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x402DF854
; FP32: $f0 = COPY [[C]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: e_single_precision
- ; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4005BF0A80000000
+ ; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x402DF854
; FP64: $f0 = COPY [[C]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = G_FCONSTANT float 0x4005BF0A80000000
@@ -34,11 +34,11 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_double_precision
- ; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4005BF0A8B145769
+ ; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4005BF0A8B145769
; FP32: $d0 = COPY [[C]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: e_double_precision
- ; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4005BF0A8B145769
+ ; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4005BF0A8B145769
; FP64: $d0 = COPY [[C]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = G_FCONSTANT double 0x4005BF0A8B145769
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
index 533cf5e132806..cac2dea3f5fd8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
@@ -365,7 +365,7 @@ body: |
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F000000
; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -380,7 +380,7 @@ body: |
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F000000
; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -408,7 +408,7 @@ body: |
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F000000
; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -425,7 +425,7 @@ body: |
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F000000
; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -456,7 +456,7 @@ body: |
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F000000
; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -473,7 +473,7 @@ body: |
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x4F000000
; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -547,7 +547,7 @@ body: |
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x41E0000000000000
; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -562,7 +562,7 @@ body: |
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x41E0000000000000
; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -590,7 +590,7 @@ body: |
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x41E0000000000000
; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -607,7 +607,7 @@ body: |
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x41E0000000000000
; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -638,7 +638,7 @@ body: |
; FP32-NEXT: {{ $}}
; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x41E0000000000000
; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -655,7 +655,7 @@ body: |
; FP64-NEXT: {{ $}}
; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x41E0000000000000
; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
index e81883473d88a..fcc5c63bb88b8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
@@ -338,7 +338,7 @@ body: |
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
- ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C1]]
; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP32: $f0 = COPY [[FPTRUNC]](s32)
@@ -348,7 +348,7 @@ body: |
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
- ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C1]]
; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP64: $f0 = COPY [[FPTRUNC]](s32)
@@ -374,7 +374,7 @@ body: |
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
- ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP32: $f0 = COPY [[FPTRUNC]](s32)
@@ -386,7 +386,7 @@ body: |
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
- ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP64: $f0 = COPY [[FPTRUNC]](s32)
@@ -413,7 +413,7 @@ body: |
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
- ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP32: $f0 = COPY [[FPTRUNC]](s32)
@@ -425,7 +425,7 @@ body: |
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
- ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
; FP64: $f0 = COPY [[FPTRUNC]](s32)
@@ -490,7 +490,7 @@ body: |
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
- ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C1]]
; FP32: $d0 = COPY [[FSUB]](s64)
; FP32: RetRA implicit $d0
@@ -499,7 +499,7 @@ body: |
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
- ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C1]]
; FP64: $d0 = COPY [[FSUB]](s64)
; FP64: RetRA implicit $d0
@@ -524,7 +524,7 @@ body: |
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
- ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP32: $d0 = COPY [[FSUB]](s64)
; FP32: RetRA implicit $d0
@@ -535,7 +535,7 @@ body: |
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
- ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP64: $d0 = COPY [[FSUB]](s64)
; FP64: RetRA implicit $d0
@@ -561,7 +561,7 @@ body: |
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
- ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP32: $d0 = COPY [[FSUB]](s64)
; FP32: RetRA implicit $d0
@@ -572,7 +572,7 @@ body: |
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
- ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[MV]], [[C2]]
; FP64: $d0 = COPY [[FSUB]](s64)
; FP64: RetRA implicit $d0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
index 4f0a688990d79..1eca0d3b96ac4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir
@@ -16,11 +16,11 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_single_precision
- ; FP32: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0x4005BF0A80000000
+ ; FP32: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float f0x402DF854
; FP32: $f0 = COPY [[C]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: e_single_precision
- ; FP64: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0x4005BF0A80000000
+ ; FP64: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float f0x402DF854
; FP64: $f0 = COPY [[C]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = G_FCONSTANT float 0x4005BF0A80000000
@@ -36,11 +36,11 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_double_precision
- ; FP32: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0x4005BF0A8B145769
+ ; FP32: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double f0x4005BF0A8B145769
; FP32: $d0 = COPY [[C]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: e_double_precision
- ; FP64: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0x4005BF0A8B145769
+ ; FP64: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double f0x4005BF0A8B145769
; FP64: $d0 = COPY [[C]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = G_FCONSTANT double 0x4005BF0A8B145769
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
index dd9b05487dca5..fa893a2332e02 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
@@ -76,7 +76,7 @@ body: |
; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; FP32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
- ; FP32: [[C1:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP32: [[C1:%[0-9]+]]:fprb(s64) = G_FCONSTANT double f0x4330000000000000
; FP32: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[MV]], [[C1]]
; FP32: $d0 = COPY [[FSUB]](s64)
; FP32: RetRA implicit $d0
@@ -85,7 +85,7 @@ body: |
; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; FP64: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
- ; FP64: [[C1:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0x4330000000000000
+ ; FP64: [[C1:%[0-9]+]]:fprb(s64) = G_FCONSTANT double f0x4330000000000000
; FP64: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[MV]], [[C1]]
; FP64: $d0 = COPY [[FSUB]](s64)
; FP64: RetRA implicit $d0
diff --git a/llvm/test/CodeGen/PowerPC/ppc_fp128-bcwriter.ll b/llvm/test/CodeGen/PowerPC/ppc_fp128-bcwriter.ll
index 3966f85cc8662..38ffbb2a12758 100644
--- a/llvm/test/CodeGen/PowerPC/ppc_fp128-bcwriter.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc_fp128-bcwriter.ll
@@ -1,7 +1,7 @@
; RUN: llvm-as < %s -o - | llvm-dis - | FileCheck %s
;CHECK-LABEL: main
-;CHECK: store ppc_fp128 0xM0000000000000000FFFFFFFFFFFFFFFF
+;CHECK: store ppc_fp128 f0xFFFFFFFFFFFFFFFF0000000000000000
define i32 @main() local_unnamed_addr {
_main_entry:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
index 51809d0069910..c3a8c7a9aff02 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll
@@ -865,8 +865,8 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; RV32I-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV32I-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 3.000000e+00
; RV32I-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2
; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
@@ -905,8 +905,8 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; RV32IF-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; RV32IF-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV32IF-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; RV32IF-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 3.000000e+00
; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
@@ -940,8 +940,8 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV32IZFH-NEXT: {{ $}}
; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
- ; RV32IZFH-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; RV32IZFH-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV32IZFH-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; RV32IZFH-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 3.000000e+00
; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
; RV32IZFH-NEXT: $f11_h = COPY [[C]](s16)
@@ -967,8 +967,8 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
- ; RV64I-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV64I-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 3.000000e+00
; RV64I-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $x2, implicit $x2
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s16)
@@ -1007,8 +1007,8 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; RV64IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
; RV64IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; RV64IF-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; RV64IF-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV64IF-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; RV64IF-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 3.000000e+00
; RV64IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
; RV64IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
@@ -1042,8 +1042,8 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
; RV64IZFH-NEXT: {{ $}}
; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
; RV64IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
- ; RV64IZFH-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; RV64IZFH-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; RV64IZFH-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
+ ; RV64IZFH-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 3.000000e+00
; RV64IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; RV64IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
; RV64IZFH-NEXT: $f11_h = COPY [[C]](s16)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
index 3225120219c0a..cc73e19f5b60b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
@@ -851,7 +851,7 @@ define i32 @caller_large_scalars() nounwind {
; ILP32-LABEL: name: caller_large_scalars
; ILP32: bb.1 (%ir-block.0):
; ILP32-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 1
- ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; ILP32-NEXT: G_STORE [[C]](s128), [[FRAME_INDEX]](p0) :: (store (s128) into %stack.0, align 8)
@@ -868,7 +868,7 @@ define i32 @caller_large_scalars() nounwind {
; ILP32F-LABEL: name: caller_large_scalars
; ILP32F: bb.1 (%ir-block.0):
; ILP32F-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 1
- ; ILP32F-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; ILP32F-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; ILP32F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; ILP32F-NEXT: G_STORE [[C]](s128), [[FRAME_INDEX]](p0) :: (store (s128) into %stack.0, align 8)
@@ -885,7 +885,7 @@ define i32 @caller_large_scalars() nounwind {
; ILP32D-LABEL: name: caller_large_scalars
; ILP32D: bb.1 (%ir-block.0):
; ILP32D-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 1
- ; ILP32D-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; ILP32D-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; ILP32D-NEXT: G_STORE [[C]](s128), [[FRAME_INDEX]](p0) :: (store (s128) into %stack.0, align 8)
@@ -947,7 +947,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; ILP32-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; ILP32-NEXT: [[C7:%[0-9]+]]:_(s128) = G_CONSTANT i128 8
; ILP32-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; ILP32-NEXT: [[C9:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; ILP32-NEXT: [[C9:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; ILP32-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $x2, implicit $x2
; ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; ILP32-NEXT: G_STORE [[C7]](s128), [[FRAME_INDEX]](p0) :: (store (s128) into %stack.0, align 8)
@@ -985,7 +985,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; ILP32F-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; ILP32F-NEXT: [[C7:%[0-9]+]]:_(s128) = G_CONSTANT i128 8
; ILP32F-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; ILP32F-NEXT: [[C9:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; ILP32F-NEXT: [[C9:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; ILP32F-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $x2, implicit $x2
; ILP32F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; ILP32F-NEXT: G_STORE [[C7]](s128), [[FRAME_INDEX]](p0) :: (store (s128) into %stack.0, align 8)
@@ -1023,7 +1023,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; ILP32D-NEXT: [[C7:%[0-9]+]]:_(s128) = G_CONSTANT i128 8
; ILP32D-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; ILP32D-NEXT: [[C9:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; ILP32D-NEXT: [[C9:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; ILP32D-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $x2, implicit $x2
; ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; ILP32D-NEXT: G_STORE [[C7]](s128), [[FRAME_INDEX]](p0) :: (store (s128) into %stack.0, align 8)
@@ -1246,7 +1246,7 @@ define fp128 @callee_large_scalar_ret() nounwind {
; RV32I-NEXT: liveins: $x10
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; RV32I-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; RV32I-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; RV32I-NEXT: G_STORE [[C]](s128), [[COPY]](p0) :: (store (s128))
; RV32I-NEXT: PseudoRET
ret fp128 0xL00000000000000007FFF000000000000
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
index a2973583ab6c5..6f40942b8fcb6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
@@ -108,7 +108,7 @@ define i64 @caller_i128_fp128_in_regs() nounwind {
; LP64-LABEL: name: caller_i128_fp128_in_regs
; LP64: bb.1 (%ir-block.0):
; LP64-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 1
- ; LP64-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; LP64-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; LP64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C]](s128)
; LP64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C1]](s128)
@@ -125,7 +125,7 @@ define i64 @caller_i128_fp128_in_regs() nounwind {
; LP64F-LABEL: name: caller_i128_fp128_in_regs
; LP64F: bb.1 (%ir-block.0):
; LP64F-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 1
- ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; LP64F-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C]](s128)
; LP64F-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C1]](s128)
@@ -142,7 +142,7 @@ define i64 @caller_i128_fp128_in_regs() nounwind {
; LP64D-LABEL: name: caller_i128_fp128_in_regs
; LP64D: bb.1 (%ir-block.0):
; LP64D-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 1
- ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; LP64D-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C]](s128)
; LP64D-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C1]](s128)
@@ -910,7 +910,7 @@ define i64 @caller_small_scalar_ret() nounwind {
define fp128 @callee_fp128_ret() nounwind {
; RV64I-LABEL: name: callee_fp128_ret
; RV64I: bb.1 (%ir-block.0):
- ; RV64I-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000007FFF000000000000
+ ; RV64I-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 +inf
; RV64I-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[C]](s128)
; RV64I-NEXT: $x10 = COPY [[UV]](s64)
; RV64I-NEXT: $x11 = COPY [[UV1]](s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll
index 6a1c3ca2b0b67..676d8a844ab81 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/splat_vector.ll
@@ -500,14 +500,14 @@ define <vscale x 8 x i64> @splat_zero_nxv8i64() {
define <vscale x 1 x half> @splat_zero_nxv1half() {
; RV32-LABEL: name: splat_zero_nxv1half
; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>)
; RV32-NEXT: PseudoRET implicit $v8
;
; RV64-LABEL: name: splat_zero_nxv1half
; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>)
; RV64-NEXT: PseudoRET implicit $v8
@@ -517,14 +517,14 @@ define <vscale x 1 x half> @splat_zero_nxv1half() {
define <vscale x 2 x half> @splat_zero_nxv2half() {
; RV32-LABEL: name: splat_zero_nxv2half
; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>)
; RV32-NEXT: PseudoRET implicit $v8
;
; RV64-LABEL: name: splat_zero_nxv2half
; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>)
; RV64-NEXT: PseudoRET implicit $v8
@@ -534,14 +534,14 @@ define <vscale x 2 x half> @splat_zero_nxv2half() {
define <vscale x 4 x half> @splat_zero_nxv4half() {
; RV32-LABEL: name: splat_zero_nxv4half
; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>)
; RV32-NEXT: PseudoRET implicit $v8
;
; RV64-LABEL: name: splat_zero_nxv4half
; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>)
; RV64-NEXT: PseudoRET implicit $v8
@@ -551,14 +551,14 @@ define <vscale x 4 x half> @splat_zero_nxv4half() {
define <vscale x 8 x half> @splat_zero_nxv8half() {
; RV32-LABEL: name: splat_zero_nxv8half
; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>)
; RV32-NEXT: PseudoRET implicit $v8m2
;
; RV64-LABEL: name: splat_zero_nxv8half
; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>)
; RV64-NEXT: PseudoRET implicit $v8m2
@@ -568,14 +568,14 @@ define <vscale x 8 x half> @splat_zero_nxv8half() {
define <vscale x 16 x half> @splat_zero_nxv16half() {
; RV32-LABEL: name: splat_zero_nxv16half
; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>)
; RV32-NEXT: PseudoRET implicit $v8m4
;
; RV64-LABEL: name: splat_zero_nxv16half
; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>)
; RV64-NEXT: PseudoRET implicit $v8m4
@@ -585,14 +585,14 @@ define <vscale x 16 x half> @splat_zero_nxv16half() {
define <vscale x 32 x half> @splat_zero_nxv32half() {
; RV32-LABEL: name: splat_zero_nxv32half
; RV32: bb.1 (%ir-block.0):
- ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s16>)
; RV32-NEXT: PseudoRET implicit $v8m8
;
; RV64-LABEL: name: splat_zero_nxv32half
; RV64: bb.1 (%ir-block.0):
- ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s16)
; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s16>)
; RV64-NEXT: PseudoRET implicit $v8m8
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
index 66d01a3773035..3586442d49464 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
@@ -189,7 +189,7 @@ body: |
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE float f0x00800000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
; CHECK-NEXT: tCBZ renamable $r1, %bb.4, debug-location !31
; CHECK-NEXT: {{ $}}
@@ -197,7 +197,7 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE float f0x00800000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
@@ -208,7 +208,7 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE float f0x00800000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34)
; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
@@ -221,7 +221,7 @@ body: |
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: liveins: $q0, $r2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE float f0x00800000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
; CHECK-NEXT: renamable $s4 = nnan ninf nsz VFP_VMAXNMS renamable $s2, renamable $s3, debug-location !31
; CHECK-NEXT: renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s1, implicit killed $q0, debug-location !31
@@ -232,7 +232,7 @@ body: |
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: liveins: $r2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE float f0x00800000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
@@ -241,7 +241,7 @@ body: |
; CHECK-NEXT: bb.5.while.end:
; CHECK-NEXT: liveins: $r2, $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE float f0x00800000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg, debug-location !45 :: (store (s32) into %ir.pResult, !tbaa !34)
; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, debug-location !46
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
index 02c72cf9f157d..42e616263dc12 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
@@ -39,7 +39,7 @@ define fp128 @test_ret_f128() {
; WASM32-NOMULTIVAL-NEXT: liveins: $arguments
; WASM32-NOMULTIVAL-NEXT: {{ $}}
; WASM32-NOMULTIVAL-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(p0) = ARGUMENT_i32 0, implicit $arguments
- ; WASM32-NOMULTIVAL-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000000000000000000000
+ ; WASM32-NOMULTIVAL-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0.000000e+00
; WASM32-NOMULTIVAL-NEXT: G_STORE [[C]](s128), [[ARGUMENT_i32_]](p0) :: (store (s128))
; WASM32-NOMULTIVAL-NEXT: RETURN implicit-def $arguments
;
@@ -48,7 +48,7 @@ define fp128 @test_ret_f128() {
; WASM64-NOMULTIVAL-NEXT: liveins: $arguments
; WASM64-NOMULTIVAL-NEXT: {{ $}}
; WASM64-NOMULTIVAL-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(p0) = ARGUMENT_i64 0, implicit $arguments
- ; WASM64-NOMULTIVAL-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000000000000000000000
+ ; WASM64-NOMULTIVAL-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0.000000e+00
; WASM64-NOMULTIVAL-NEXT: G_STORE [[C]](s128), [[ARGUMENT_i64_]](p0) :: (store (s128))
; WASM64-NOMULTIVAL-NEXT: RETURN implicit-def $arguments
;
@@ -56,7 +56,7 @@ define fp128 @test_ret_f128() {
; MULTIVAL: bb.1 (%ir-block.0):
; MULTIVAL-NEXT: liveins: $arguments
; MULTIVAL-NEXT: {{ $}}
- ; MULTIVAL-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0xL00000000000000000000000000000000
+ ; MULTIVAL-NEXT: [[C:%[0-9]+]]:_(s128) = G_FCONSTANT fp128 0.000000e+00
; MULTIVAL-NEXT: [[UV:%[0-9]+]]:i64(s64), [[UV1:%[0-9]+]]:i64(s64) = G_UNMERGE_VALUES [[C]](s128)
; MULTIVAL-NEXT: RETURN [[UV]](s64), [[UV1]](s64), implicit-def $arguments
ret fp128 zeroinitializer
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
index 5c7af1f28a874..515a09f848e0a 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
@@ -98,7 +98,7 @@ define half @test_ret_f16() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i32(s32) = G_ANYEXT [[C]](s16)
; CHECK-NEXT: RETURN [[ANYEXT]](s32), implicit-def $arguments
ret half 0.0
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
index 1c1462ff976f8..8b7ad8d4369f6 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
@@ -52,7 +52,7 @@ define <8 x half> @test_ret_v8f16() {
; NO-FP16-NEXT: liveins: $arguments
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(p0) = ARGUMENT_i32 0, implicit $arguments
- ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; NO-FP16-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; NO-FP16-NEXT: G_STORE [[BUILD_VECTOR]](<8 x s16>), [[ARGUMENT_i32_]](p0) :: (store (<8 x s16>))
; NO-FP16-NEXT: RETURN implicit-def $arguments
@@ -61,7 +61,7 @@ define <8 x half> @test_ret_v8f16() {
; FP16: bb.1 (%ir-block.0):
; FP16-NEXT: liveins: $arguments
; FP16-NEXT: {{ $}}
- ; FP16-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+ ; FP16-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
; FP16-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; FP16-NEXT: RETURN [[BUILD_VECTOR]](<8 x s16>), implicit-def $arguments
ret <8 x half> zeroinitializer
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
index 6c06d505e8231..449c6e365bb5c 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
@@ -7,7 +7,7 @@ define x86_fp80 @f0(x86_fp80 noundef %a) {
; X86: bb.1.entry:
; X86-NEXT: [[FRAME_INDEX:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
; X86-NEXT: [[LOAD:%[0-9]+]]:psr(s80) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s80) from %fixed-stack.0, align 4)
- ; X86-NEXT: [[C:%[0-9]+]]:psr(s80) = G_FCONSTANT x86_fp80 0xK400A8000000000000000
+ ; X86-NEXT: [[C:%[0-9]+]]:psr(s80) = G_FCONSTANT x86_fp80 2.048000e+03
; X86-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0.a.addr
; X86-NEXT: [[FRAME_INDEX2:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.1.x
; X86-NEXT: G_STORE [[LOAD]](s80), [[FRAME_INDEX1]](p0) :: (store (s80) into %ir.a.addr, align 16)
@@ -22,7 +22,7 @@ define x86_fp80 @f0(x86_fp80 noundef %a) {
; X64: bb.1.entry:
; X64-NEXT: [[FRAME_INDEX:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
; X64-NEXT: [[LOAD:%[0-9]+]]:psr(s80) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s80) from %fixed-stack.0, align 16)
- ; X64-NEXT: [[C:%[0-9]+]]:psr(s80) = G_FCONSTANT x86_fp80 0xK400A8000000000000000
+ ; X64-NEXT: [[C:%[0-9]+]]:psr(s80) = G_FCONSTANT x86_fp80 2.048000e+03
; X64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0.a.addr
; X64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.1.x
; X64-NEXT: G_STORE [[LOAD]](s80), [[FRAME_INDEX1]](p0) :: (store (s80) into %ir.a.addr, align 16)
diff --git a/llvm/test/DebugInfo/X86/float_const_loclist.ll b/llvm/test/DebugInfo/X86/float_const_loclist.ll
index 4483370c82859..152dea0cc0c50 100644
--- a/llvm/test/DebugInfo/X86/float_const_loclist.ll
+++ b/llvm/test/DebugInfo/X86/float_const_loclist.ll
@@ -14,8 +14,8 @@
; }
;
; SANITY: CALL{{.*}} @barrier
-; SANITY: DBG_VALUE float 0x40091EB860000000
-; SANITY: DBG_VALUE x86_fp80 0xK4000C8F5C28F5C28F800
+; SANITY: DBG_VALUE float 3.140000e+00
+; SANITY: DBG_VALUE x86_fp80 f0x4000C8F5C28F5C28F800
; SANITY: TAILJMP{{.*}} @barrier
;
; CHECK: .debug_info contents:
diff --git a/llvm/test/DebugInfo/X86/global-sra-fp80-array.ll b/llvm/test/DebugInfo/X86/global-sra-fp80-array.ll
index d3ab3bdcb1a42..6fd972baca26f 100644
--- a/llvm/test/DebugInfo/X86/global-sra-fp80-array.ll
+++ b/llvm/test/DebugInfo/X86/global-sra-fp80-array.ll
@@ -21,8 +21,8 @@ target triple = "x86_64-unknown-linux-gnu"
@array = internal global [2 x x86_fp80] zeroinitializer, align 16, !dbg !0
-; CHECK: @array.0 = internal unnamed_addr global x86_fp80 0xK00000000000000000000, align 16, !dbg ![[EL0:.*]]
-; CHECK: @array.1 = internal unnamed_addr global x86_fp80 0xK00000000000000000000, align 16, !dbg ![[EL1:.*]]
+; CHECK: @array.0 = internal unnamed_addr global x86_fp80 0.000000e+00, align 16, !dbg ![[EL0:.*]]
+; CHECK: @array.1 = internal unnamed_addr global x86_fp80 0.000000e+00, align 16, !dbg ![[EL1:.*]]
;
; CHECK: ![[EL0]] = !DIGlobalVariableExpression(var: ![[VAR:.*]], expr: !DIExpression(DW_OP_LLVM_fragment, 0, 128))
; CHECK: ![[VAR]] = distinct !DIGlobalVariable(name: "array"
diff --git a/llvm/test/DebugInfo/X86/global-sra-fp80-struct.ll b/llvm/test/DebugInfo/X86/global-sra-fp80-struct.ll
index 7adc40c5b844d..b2c00728dcea7 100644
--- a/llvm/test/DebugInfo/X86/global-sra-fp80-struct.ll
+++ b/llvm/test/DebugInfo/X86/global-sra-fp80-struct.ll
@@ -24,7 +24,7 @@ target triple = "x86_64-unknown-linux-gnu"
@static_struct = internal global %struct.mystruct zeroinitializer, align 16, !dbg !0
-; CHECK: @static_struct.0 = internal unnamed_addr global x86_fp80 0xK00000000000000000000, align 16, !dbg ![[EL0:.*]]
+; CHECK: @static_struct.0 = internal unnamed_addr global x86_fp80 0.000000e+00, align 16, !dbg ![[EL0:.*]]
; CHECK: @static_struct.1 = internal unnamed_addr global i32 0, align 16, !dbg ![[EL1:.*]]
; CHECK: ![[EL0]] = !DIGlobalVariableExpression(var: ![[VAR:.*]], expr: !DIExpression(DW_OP_LLVM_fragment, 0, 128))
diff --git a/llvm/test/Feature/vector-cast-constant-exprs.ll b/llvm/test/Feature/vector-cast-constant-exprs.ll
index 3a9d5525c43aa..3552a23a68eca 100644
--- a/llvm/test/Feature/vector-cast-constant-exprs.ll
+++ b/llvm/test/Feature/vector-cast-constant-exprs.ll
@@ -5,7 +5,7 @@
define <2 x float> @ga() {
; CHECK-LABEL: define <2 x float> @ga() {
-; CHECK-NEXT: ret <2 x float> <float 0x4011333340000000, float 0x40099999A0000000>
+; CHECK-NEXT: ret <2 x float> <float 4.300000e+00, float 3.200000e+00>
;
%fptrunc = fptrunc <2 x double> <double 4.3, double 3.2> to <2 x float>
ret <2 x float> %fptrunc
diff --git a/llvm/test/Instrumentation/HeapProfiler/basic.ll b/llvm/test/Instrumentation/HeapProfiler/basic.ll
index 5d918f20de842..129fcf2fc80fd 100644
--- a/llvm/test/Instrumentation/HeapProfiler/basic.ll
+++ b/llvm/test/Instrumentation/HeapProfiler/basic.ll
@@ -65,7 +65,7 @@ entry:
; CHECK-NEXT: store i64 %[[NEW_ST_SHADOW]]
; CHECK-NOT: store i64
; The actual store.
-; CHECK: store x86_fp80 0xK3FFF8000000000000000, ptr %a
+; CHECK: store x86_fp80 1.000000e+00, ptr %a
; CHECK: ret void
define void @i40test(ptr %a, ptr %b) nounwind uwtable {
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
index 30821c7a1f987..c7cc7ca7e8d62 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
@@ -71,9 +71,9 @@ define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bflo
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <8 x i16> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP3]], <8 x bfloat> splat (bfloat 0xR3F80), <8 x bfloat> zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP3]], <8 x bfloat> splat (bfloat 1.000000e+00), <8 x bfloat> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <8 x i16> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[TMP5]], <8 x bfloat> splat (bfloat 0xR3F80), <8 x bfloat> zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[TMP5]], <8 x bfloat> splat (bfloat 1.000000e+00), <8 x bfloat> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = call <4 x float> @llvm.aarch64.neon.bfmmla(<4 x float> zeroinitializer, <8 x bfloat> [[TMP4]], <8 x bfloat> [[TMP6]])
; CHECK-NEXT: [[TMP10:%.*]] = fcmp ult <4 x float> [[TMP7]], splat (float 3.500000e+00)
; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <4 x i32> [[TMP0]], zeroinitializer
diff --git a/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll b/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll
index a27e3318c59e8..572b6adf5e75c 100644
--- a/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll
+++ b/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll
@@ -71,8 +71,8 @@ define x86_fp80 @param_add_return_x86_fp80(x86_fp80 %a) sanitize_numerical_stabi
; CHECK-NEXT: [[TMP3:%.*]] = fpext x86_fp80 [[A:%.*]] to fp128
; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], fp128 [[TMP2]], fp128 [[TMP3]]
; CHECK-NEXT: store i64 0, ptr @__nsan_shadow_args_tag, align 8
-; CHECK-NEXT: [[B:%.*]] = fadd x86_fp80 [[A]], 0xK3FC9E69594BEC44DE000
-; CHECK-NEXT: [[TMP5:%.*]] = fadd fp128 [[TMP4]], 0xLC0000000000000003FC9CD2B297D889B
+; CHECK-NEXT: [[B:%.*]] = fadd x86_fp80 [[A]], f0x3FC9E69594BEC44DE000
+; CHECK-NEXT: [[TMP5:%.*]] = fadd fp128 [[TMP4]], f0x3FC9CD2B297D889BC000000000000000
; CHECK-NEXT: [[TMP6:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[B]], fp128 [[TMP5]], i32 1, i64 0)
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 1
; CHECK-NEXT: [[TMP8:%.*]] = fpext x86_fp80 [[B]] to fp128
@@ -96,7 +96,7 @@ define double @param_add_return_double(double %a) sanitize_numerical_stability {
; DQQ-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], fp128 [[TMP2]], fp128 [[TMP3]]
; DQQ-NEXT: store i64 0, ptr @__nsan_shadow_args_tag, align 8
; DQQ-NEXT: [[B:%.*]] = fadd double [[A]], 1.000000e+00
-; DQQ-NEXT: [[TMP5:%.*]] = fadd fp128 [[TMP4]], 0xL00000000000000003FFF000000000000
+; DQQ-NEXT: [[TMP5:%.*]] = fadd fp128 [[TMP4]], 1.000000e+00
; DQQ-NEXT: [[TMP6:%.*]] = call i32 @__nsan_internal_check_double_q(double [[B]], fp128 [[TMP5]], i32 1, i64 0)
; DQQ-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 1
; DQQ-NEXT: [[TMP8:%.*]] = fpext double [[B]] to fp128
@@ -114,7 +114,7 @@ define double @param_add_return_double(double %a) sanitize_numerical_stability {
; DLQ-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], x86_fp80 [[TMP2]], x86_fp80 [[TMP3]]
; DLQ-NEXT: store i64 0, ptr @__nsan_shadow_args_tag, align 8
; DLQ-NEXT: [[B:%.*]] = fadd double [[A]], 1.000000e+00
-; DLQ-NEXT: [[TMP5:%.*]] = fadd x86_fp80 [[TMP4]], 0xK3FFF8000000000000000
+; DLQ-NEXT: [[TMP5:%.*]] = fadd x86_fp80 [[TMP4]], 1.000000e+00
; DLQ-NEXT: [[TMP6:%.*]] = call i32 @__nsan_internal_check_double_l(double [[B]], x86_fp80 [[TMP5]], i32 1, i64 0)
; DLQ-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 1
; DLQ-NEXT: [[TMP8:%.*]] = fpext double [[B]] to x86_fp80
@@ -197,8 +197,8 @@ define void @constantload_add_store_x86_fp80(ptr %dst) sanitize_numerical_stabil
; CHECK-NEXT: entry:
; CHECK-NEXT: [[B:%.*]] = load x86_fp80, ptr @x86_fp80_const, align 16
; CHECK-NEXT: [[TMP0:%.*]] = fpext x86_fp80 [[B]] to fp128
-; CHECK-NEXT: [[C:%.*]] = fadd x86_fp80 [[B]], 0xK3FC9E69594BEC44DE000
-; CHECK-NEXT: [[TMP1:%.*]] = fadd fp128 [[TMP0]], 0xLC0000000000000003FC9CD2B297D889B
+; CHECK-NEXT: [[C:%.*]] = fadd x86_fp80 [[B]], f0x3FC9E69594BEC44DE000
+; CHECK-NEXT: [[TMP1:%.*]] = fadd fp128 [[TMP0]], f0x3FC9CD2B297D889BC000000000000000
; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__nsan_get_shadow_ptr_for_longdouble_store(ptr [[DST:%.*]], i64 1)
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[DST]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[C]], fp128 [[TMP1]], i32 4, i64 [[TMP3]])
@@ -222,7 +222,7 @@ define void @constantload_add_store_double(ptr %dst) sanitize_numerical_stabilit
; DQQ-NEXT: [[B:%.*]] = load double, ptr @double_const, align 8
; DQQ-NEXT: [[TMP0:%.*]] = fpext double [[B]] to fp128
; DQQ-NEXT: [[C:%.*]] = fadd double [[B]], 1.000000e+00
-; DQQ-NEXT: [[TMP1:%.*]] = fadd fp128 [[TMP0]], 0xL00000000000000003FFF000000000000
+; DQQ-NEXT: [[TMP1:%.*]] = fadd fp128 [[TMP0]], 1.000000e+00
; DQQ-NEXT: [[TMP2:%.*]] = call ptr @__nsan_get_shadow_ptr_for_double_store(ptr [[DST:%.*]], i64 1)
; DQQ-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[DST]] to i64
; DQQ-NEXT: [[TMP4:%.*]] = call i32 @__nsan_internal_check_double_q(double [[C]], fp128 [[TMP1]], i32 4, i64 [[TMP3]])
@@ -238,7 +238,7 @@ define void @constantload_add_store_double(ptr %dst) sanitize_numerical_stabilit
; DLQ-NEXT: [[B:%.*]] = load double, ptr @double_const, align 8
; DLQ-NEXT: [[TMP0:%.*]] = fpext double [[B]] to x86_fp80
; DLQ-NEXT: [[C:%.*]] = fadd double [[B]], 1.000000e+00
-; DLQ-NEXT: [[TMP1:%.*]] = fadd x86_fp80 [[TMP0]], 0xK3FFF8000000000000000
+; DLQ-NEXT: [[TMP1:%.*]] = fadd x86_fp80 [[TMP0]], 1.000000e+00
; DLQ-NEXT: [[TMP2:%.*]] = call ptr @__nsan_get_shadow_ptr_for_double_store(ptr [[DST:%.*]], i64 1)
; DLQ-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[DST]] to i64
; DLQ-NEXT: [[TMP4:%.*]] = call i32 @__nsan_internal_check_double_l(double [[C]], x86_fp80 [[TMP1]], i32 4, i64 [[TMP3]])
@@ -305,8 +305,8 @@ define void @load_add_store_x86_fp80(ptr %a) sanitize_numerical_stability {
; CHECK-NEXT: br label [[TMP6]]
; CHECK: 6:
; CHECK-NEXT: [[TMP7:%.*]] = phi fp128 [ [[TMP3]], [[TMP2]] ], [ [[TMP5]], [[TMP4]] ]
-; CHECK-NEXT: [[C:%.*]] = fadd x86_fp80 [[B]], 0xK3FC9E69594BEC44DE000
-; CHECK-NEXT: [[TMP8:%.*]] = fadd fp128 [[TMP7]], 0xLC0000000000000003FC9CD2B297D889B
+; CHECK-NEXT: [[C:%.*]] = fadd x86_fp80 [[B]], f0x3FC9E69594BEC44DE000
+; CHECK-NEXT: [[TMP8:%.*]] = fadd fp128 [[TMP7]], f0x3FC9CD2B297D889BC000000000000000
; CHECK-NEXT: [[TMP9:%.*]] = call ptr @__nsan_get_shadow_ptr_for_longdouble_store(ptr [[A]], i64 1)
; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i64
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[C]], fp128 [[TMP8]], i32 4, i64 [[TMP10]])
@@ -340,7 +340,7 @@ define void @load_add_store_double(ptr %a) sanitize_numerical_stability {
; DQQ: 6:
; DQQ-NEXT: [[TMP7:%.*]] = phi fp128 [ [[TMP3]], [[TMP2]] ], [ [[TMP5]], [[TMP4]] ]
; DQQ-NEXT: [[C:%.*]] = fadd double [[B]], 1.000000e+00
-; DQQ-NEXT: [[TMP8:%.*]] = fadd fp128 [[TMP7]], 0xL00000000000000003FFF000000000000
+; DQQ-NEXT: [[TMP8:%.*]] = fadd fp128 [[TMP7]], 1.000000e+00
; DQQ-NEXT: [[TMP9:%.*]] = call ptr @__nsan_get_shadow_ptr_for_double_store(ptr [[A]], i64 1)
; DQQ-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i64
; DQQ-NEXT: [[TMP11:%.*]] = call i32 @__nsan_internal_check_double_q(double [[C]], fp128 [[TMP8]], i32 4, i64 [[TMP10]])
@@ -366,7 +366,7 @@ define void @load_add_store_double(ptr %a) sanitize_numerical_stability {
; DLQ: 6:
; DLQ-NEXT: [[TMP7:%.*]] = phi x86_fp80 [ [[TMP3]], [[TMP2]] ], [ [[TMP5]], [[TMP4]] ]
; DLQ-NEXT: [[C:%.*]] = fadd double [[B]], 1.000000e+00
-; DLQ-NEXT: [[TMP8:%.*]] = fadd x86_fp80 [[TMP7]], 0xK3FFF8000000000000000
+; DLQ-NEXT: [[TMP8:%.*]] = fadd x86_fp80 [[TMP7]], 1.000000e+00
; DLQ-NEXT: [[TMP9:%.*]] = call ptr @__nsan_get_shadow_ptr_for_double_store(ptr [[A]], i64 1)
; DLQ-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i64
; DLQ-NEXT: [[TMP11:%.*]] = call i32 @__nsan_internal_check_double_l(double [[C]], x86_fp80 [[TMP8]], i32 4, i64 [[TMP10]])
@@ -484,18 +484,18 @@ define void @call_fn_taking_float() sanitize_numerical_stability {
; DQQ-NEXT: entry:
; DQQ-NEXT: store ptr @takes_floats, ptr @__nsan_shadow_args_tag, align 8
; DQQ-NEXT: store double 1.000000e+00, ptr @__nsan_shadow_args_ptr, align 1
-; DQQ-NEXT: store fp128 0xL00000000000000004000800000000000, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 8), align 1
-; DQQ-NEXT: store fp128 0xLC0000000000000003FC9CD2B297D889B, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 24), align 1
-; DQQ-NEXT: call void @takes_floats(float 1.000000e+00, i8 2, double 3.000000e+00, x86_fp80 0xK3FC9E69594BEC44DE000)
+; DQQ-NEXT: store fp128 3.000000e+00, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 8), align 1
+; DQQ-NEXT: store fp128 f0x3FC9CD2B297D889BC000000000000000, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 24), align 1
+; DQQ-NEXT: call void @takes_floats(float 1.000000e+00, i8 2, double 3.000000e+00, x86_fp80 f0x3FC9E69594BEC44DE000)
; DQQ-NEXT: ret void
;
; DLQ-LABEL: @call_fn_taking_float(
; DLQ-NEXT: entry:
; DLQ-NEXT: store ptr @takes_floats, ptr @__nsan_shadow_args_tag, align 8
; DLQ-NEXT: store double 1.000000e+00, ptr @__nsan_shadow_args_ptr, align 1
-; DLQ-NEXT: store x86_fp80 0xK4000C000000000000000, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 8), align 1
-; DLQ-NEXT: store fp128 0xLC0000000000000003FC9CD2B297D889B, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 18), align 1
-; DLQ-NEXT: call void @takes_floats(float 1.000000e+00, i8 2, double 3.000000e+00, x86_fp80 0xK3FC9E69594BEC44DE000)
+; DLQ-NEXT: store x86_fp80 3.000000e+00, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 8), align 1
+; DLQ-NEXT: store fp128 f0x3FC9CD2B297D889BC000000000000000, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 18), align 1
+; DLQ-NEXT: call void @takes_floats(float 1.000000e+00, i8 2, double 3.000000e+00, x86_fp80 f0x3FC9E69594BEC44DE000)
; DLQ-NEXT: ret void
;
entry:
diff --git a/llvm/test/Instrumentation/NumericalStabilitySanitizer/intrinsics.ll b/llvm/test/Instrumentation/NumericalStabilitySanitizer/intrinsics.ll
index 033a31ba12fbf..db2d9e66f5697 100644
--- a/llvm/test/Instrumentation/NumericalStabilitySanitizer/intrinsics.ll
+++ b/llvm/test/Instrumentation/NumericalStabilitySanitizer/intrinsics.ll
@@ -35,7 +35,7 @@ define double @call_sqrt_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_sqrt_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.sqrt.f64(double 4.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 0xK40018000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 4.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -48,7 +48,7 @@ define double @call_sqrt_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_sqrt_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.sqrt.f64(double 4.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 0xK40018000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 4.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -65,8 +65,8 @@ entry:
define x86_fp80 @call_sqrt_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_sqrt_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 0xK40018000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 0xK40018000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 4.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 4.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -142,8 +142,8 @@ entry:
define x86_fp80 @call_powi_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_powi_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.powi.f80.i32(x86_fp80 0xK40008000000000000000, i32 3)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.powi.f80.i32(x86_fp80 0xK40008000000000000000, i32 3)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.powi.f80.i32(x86_fp80 2.000000e+00, i32 3)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.powi.f80.i32(x86_fp80 2.000000e+00, i32 3)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -187,7 +187,7 @@ define double @call_sin_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_sin_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.sin.f64(double 1.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 0xK3FFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -200,7 +200,7 @@ define double @call_sin_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_sin_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.sin.f64(double 1.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 0xK3FFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -217,8 +217,8 @@ entry:
define x86_fp80 @call_sin_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_sin_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 0xK3FFF8000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 1.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -262,7 +262,7 @@ define double @call_cos_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_cos_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.cos.f64(double 1.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 0xK3FFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -275,7 +275,7 @@ define double @call_cos_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_cos_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.cos.f64(double 1.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 0xK3FFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -292,8 +292,8 @@ entry:
define x86_fp80 @call_cos_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_cos_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 0xK3FFF8000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 1.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -337,7 +337,7 @@ define double @call_pow_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_pow_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.pow.f64(double 2.000000e+00, double 3.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 0xK40008000000000000000, x86_fp80 0xK4000C000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 2.000000e+00, x86_fp80 3.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -350,7 +350,7 @@ define double @call_pow_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_pow_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.pow.f64(double 2.000000e+00, double 3.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 0xK40008000000000000000, x86_fp80 0xK4000C000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 2.000000e+00, x86_fp80 3.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -367,8 +367,8 @@ entry:
define x86_fp80 @call_pow_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_pow_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 0xK40008000000000000000, x86_fp80 0xK40018000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 0xK40008000000000000000, x86_fp80 0xK40018000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 2.000000e+00, x86_fp80 4.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 2.000000e+00, x86_fp80 4.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -412,7 +412,7 @@ define double @call_exp_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_exp_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.exp.f64(double 1.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 0xK3FFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -425,7 +425,7 @@ define double @call_exp_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_exp_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.exp.f64(double 1.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 0xK3FFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -442,8 +442,8 @@ entry:
define x86_fp80 @call_exp_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_exp_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 0xK3FFF8000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 1.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -487,7 +487,7 @@ define double @call_exp2_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_exp2_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.exp2.f64(double 1.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 0xK3FFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -500,7 +500,7 @@ define double @call_exp2_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_exp2_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.exp2.f64(double 1.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 0xK3FFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -517,8 +517,8 @@ entry:
define x86_fp80 @call_exp2_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_exp2_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 0xK3FFF8000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 1.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -562,7 +562,7 @@ define double @call_log_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_log_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.log.f64(double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -575,7 +575,7 @@ define double @call_log_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_log_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.log.f64(double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -592,8 +592,8 @@ entry:
define x86_fp80 @call_log_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_log_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -637,7 +637,7 @@ define double @call_log10_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_log10_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.log10.f64(double 1.000000e+02)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 0xK4005C800000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 1.000000e+02)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -650,7 +650,7 @@ define double @call_log10_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_log10_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.log10.f64(double 1.000000e+02)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 0xK4005C800000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 1.000000e+02)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -667,8 +667,8 @@ entry:
define x86_fp80 @call_log10_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_log10_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 0xK7FFF0000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 0xK7FFF0000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 +snan(0x0))
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 +snan(0x0))
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -712,7 +712,7 @@ define double @call_log2_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_log2_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.log2.f64(double 8.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 0xK40028000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 8.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -725,7 +725,7 @@ define double @call_log2_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_log2_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.log2.f64(double 8.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 0xK40028000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 8.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -742,8 +742,8 @@ entry:
define x86_fp80 @call_log2_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_log2_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 0xK40018000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 0xK40018000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 4.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 4.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -787,7 +787,7 @@ define double @call_fma_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_fma_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double 1.000000e+00, double 2.000000e+00, double 3.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fma.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000, x86_fp80 0xK4000C000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fma.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00, x86_fp80 3.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -800,7 +800,7 @@ define double @call_fma_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_fma_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double 1.000000e+00, double 2.000000e+00, double 3.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fma.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000, x86_fp80 0xK4000C000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fma.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00, x86_fp80 3.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -817,8 +817,8 @@ entry:
define x86_fp80 @call_fma_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_fma_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.fma.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000, x86_fp80 0xK40018000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fma.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000, x86_fp80 0xK40018000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.fma.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00, x86_fp80 4.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fma.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00, x86_fp80 4.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -862,7 +862,7 @@ define double @call_fmuladd_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_fmuladd_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double 1.000000e+00, double 2.000000e+00, double 3.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000, x86_fp80 0xK4000C000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00, x86_fp80 3.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -875,7 +875,7 @@ define double @call_fmuladd_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_fmuladd_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double 1.000000e+00, double 2.000000e+00, double 3.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000, x86_fp80 0xK4000C000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00, x86_fp80 3.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -892,8 +892,8 @@ entry:
define x86_fp80 @call_fmuladd_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_fmuladd_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000, x86_fp80 0xK40018000000000000000)
-; CHECK-NEXT: [[TMP6:%.*]] = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000, x86_fp80 0xK40018000000000000000)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00, x86_fp80 4.000000e+00)
+; CHECK-NEXT: [[TMP6:%.*]] = call x86_fp80 @llvm.fmuladd.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00, x86_fp80 4.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP6]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[TMP0]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -937,7 +937,7 @@ define double @call_fabs_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_fabs_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.fabs.f64(double -1.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 0xKBFFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 -1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -950,7 +950,7 @@ define double @call_fabs_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_fabs_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.fabs.f64(double -1.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 0xKBFFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 -1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -967,8 +967,8 @@ entry:
define x86_fp80 @call_fabs_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_fabs_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 0xKBFFF8000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 0xKBFFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 -1.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 -1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1012,7 +1012,7 @@ define double @call_minnum_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_minnum_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.minnum.f64(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1025,7 +1025,7 @@ define double @call_minnum_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_minnum_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.minnum.f64(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1042,8 +1042,8 @@ entry:
define x86_fp80 @call_minnum_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_minnum_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1087,7 +1087,7 @@ define double @call_maxnum_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_maxnum_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.maxnum.f64(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1100,7 +1100,7 @@ define double @call_maxnum_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_maxnum_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.maxnum.f64(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1117,8 +1117,8 @@ entry:
define x86_fp80 @call_maxnum_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_maxnum_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1162,7 +1162,7 @@ define double @call_minimum_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_minimum_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.minimum.f64(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1175,7 +1175,7 @@ define double @call_minimum_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_minimum_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.minimum.f64(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1192,8 +1192,8 @@ entry:
define x86_fp80 @call_minimum_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_minimum_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.minimum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.minimum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1237,7 +1237,7 @@ define double @call_maximum_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_maximum_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.maximum.f64(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1250,7 +1250,7 @@ define double @call_maximum_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_maximum_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.maximum.f64(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1267,8 +1267,8 @@ entry:
define x86_fp80 @call_maximum_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_maximum_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.maximum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.maximum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1312,7 +1312,7 @@ define double @call_minimumnum_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_minimumnum_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[TMP0:%.*]] = call double @llvm.minimumnum.f64(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP6:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP6:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP6]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[TMP0]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1325,7 +1325,7 @@ define double @call_minimumnum_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_minimumnum_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[TMP0:%.*]] = call double @llvm.minimumnum.f64(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP1:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP1:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_l(double [[TMP0]], x86_fp80 [[TMP1]], i32 1, i64 0)
; DLQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
; DLQ-NEXT: [[TMP4:%.*]] = fpext double [[TMP0]] to x86_fp80
@@ -1342,8 +1342,8 @@ entry:
define x86_fp80 @call_minimumnum_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_minimumnum_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1387,7 +1387,7 @@ define double @call_maximumnum_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_maximumnum_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[TMP0:%.*]] = call double @llvm.maximumnum.f64(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP6:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP6:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP6]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[TMP0]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1400,7 +1400,7 @@ define double @call_maximumnum_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_maximumnum_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[TMP0:%.*]] = call double @llvm.maximumnum.f64(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP1:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP1:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_l(double [[TMP0]], x86_fp80 [[TMP1]], i32 1, i64 0)
; DLQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
; DLQ-NEXT: [[TMP4:%.*]] = fpext double [[TMP0]] to x86_fp80
@@ -1417,8 +1417,8 @@ entry:
define x86_fp80 @call_maximumnum_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_maximumnum_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1462,7 +1462,7 @@ define double @call_copysign_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_copysign_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.copysign.f64(double 1.000000e+00, double -2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xKC0008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 1.000000e+00, x86_fp80 -2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1475,7 +1475,7 @@ define double @call_copysign_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_copysign_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.copysign.f64(double 1.000000e+00, double -2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xKC0008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 1.000000e+00, x86_fp80 -2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1492,8 +1492,8 @@ entry:
define x86_fp80 @call_copysign_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_copysign_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xKBFFF8000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xKBFFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 1.000000e+00, x86_fp80 -1.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 1.000000e+00, x86_fp80 -1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1537,7 +1537,7 @@ define double @call_floor_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_floor_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.floor.f64(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1550,7 +1550,7 @@ define double @call_floor_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_floor_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.floor.f64(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1567,8 +1567,8 @@ entry:
define x86_fp80 @call_floor_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_floor_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1612,7 +1612,7 @@ define double @call_ceil_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_ceil_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.ceil.f64(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1625,7 +1625,7 @@ define double @call_ceil_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_ceil_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.ceil.f64(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1642,8 +1642,8 @@ entry:
define x86_fp80 @call_ceil_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_ceil_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1687,7 +1687,7 @@ define double @call_trunc_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_trunc_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.trunc.f64(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1700,7 +1700,7 @@ define double @call_trunc_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_trunc_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.trunc.f64(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1717,8 +1717,8 @@ entry:
define x86_fp80 @call_trunc_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_trunc_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1762,7 +1762,7 @@ define double @call_rint_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_rint_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.rint.f64(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1775,7 +1775,7 @@ define double @call_rint_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_rint_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.rint.f64(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1792,8 +1792,8 @@ entry:
define x86_fp80 @call_rint_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_rint_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1837,7 +1837,7 @@ define double @call_nearbyint_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_nearbyint_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.nearbyint.f64(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1850,7 +1850,7 @@ define double @call_nearbyint_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_nearbyint_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.nearbyint.f64(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1867,8 +1867,8 @@ entry:
define x86_fp80 @call_nearbyint_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_nearbyint_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1912,7 +1912,7 @@ define double @call_round_f64() sanitize_numerical_stability {
; DQQ-LABEL: @call_round_f64(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @llvm.round.f64(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1925,7 +1925,7 @@ define double @call_round_f64() sanitize_numerical_stability {
; DLQ-LABEL: @call_round_f64(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @llvm.round.f64(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1942,8 +1942,8 @@ entry:
define x86_fp80 @call_round_f80() sanitize_numerical_stability {
; CHECK-LABEL: @call_round_f80(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
diff --git a/llvm/test/Instrumentation/NumericalStabilitySanitizer/libfuncs.ll b/llvm/test/Instrumentation/NumericalStabilitySanitizer/libfuncs.ll
index 6f474885cd89f..f73205a3f42c8 100644
--- a/llvm/test/Instrumentation/NumericalStabilitySanitizer/libfuncs.ll
+++ b/llvm/test/Instrumentation/NumericalStabilitySanitizer/libfuncs.ll
@@ -35,7 +35,7 @@ define double @call_sqrt() sanitize_numerical_stability {
; DQQ-LABEL: @call_sqrt(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @sqrt(double 4.000000e+00) #[[ATTR3]]
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 0xK40018000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 4.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -48,7 +48,7 @@ define double @call_sqrt() sanitize_numerical_stability {
; DLQ-LABEL: @call_sqrt(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @sqrt(double 4.000000e+00) #[[ATTR3]]
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 0xK40018000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 4.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -65,8 +65,8 @@ entry:
define x86_fp80 @call_sqrtl() sanitize_numerical_stability {
; CHECK-LABEL: @call_sqrtl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @sqrtl(x86_fp80 0xK40018000000000000000) #[[ATTR3]]
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 0xK40018000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @sqrtl(x86_fp80 4.000000e+00) #[[ATTR3]]
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sqrt.f80(x86_fp80 4.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -110,7 +110,7 @@ define double @call_sin() sanitize_numerical_stability {
; DQQ-LABEL: @call_sin(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @sin(double 1.000000e+00) #[[ATTR3]]
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 0xK3FFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -123,7 +123,7 @@ define double @call_sin() sanitize_numerical_stability {
; DLQ-LABEL: @call_sin(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @sin(double 1.000000e+00) #[[ATTR3]]
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 0xK3FFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -140,8 +140,8 @@ entry:
define x86_fp80 @call_sinl() sanitize_numerical_stability {
; CHECK-LABEL: @call_sinl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @sinl(x86_fp80 0xK3FFF8000000000000000) #[[ATTR3]]
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @sinl(x86_fp80 1.000000e+00) #[[ATTR3]]
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.sin.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -185,7 +185,7 @@ define double @call_cos() sanitize_numerical_stability {
; DQQ-LABEL: @call_cos(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @cos(double 1.000000e+00) #[[ATTR3]]
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 0xK3FFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -198,7 +198,7 @@ define double @call_cos() sanitize_numerical_stability {
; DLQ-LABEL: @call_cos(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @cos(double 1.000000e+00) #[[ATTR3]]
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 0xK3FFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -215,8 +215,8 @@ entry:
define x86_fp80 @call_cosl() sanitize_numerical_stability {
; CHECK-LABEL: @call_cosl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @cosl(x86_fp80 0xK3FFF8000000000000000) #[[ATTR3]]
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @cosl(x86_fp80 1.000000e+00) #[[ATTR3]]
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.cos.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -260,7 +260,7 @@ define double @call_pow() sanitize_numerical_stability {
; DQQ-LABEL: @call_pow(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @pow(double 2.000000e+00, double 3.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 0xK40008000000000000000, x86_fp80 0xK4000C000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 2.000000e+00, x86_fp80 3.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -273,7 +273,7 @@ define double @call_pow() sanitize_numerical_stability {
; DLQ-LABEL: @call_pow(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @pow(double 2.000000e+00, double 3.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 0xK40008000000000000000, x86_fp80 0xK4000C000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 2.000000e+00, x86_fp80 3.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -290,8 +290,8 @@ entry:
define x86_fp80 @call_powl() sanitize_numerical_stability {
; CHECK-LABEL: @call_powl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @powl(x86_fp80 0xK40008000000000000000, x86_fp80 0xK40018000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 0xK40008000000000000000, x86_fp80 0xK40018000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @powl(x86_fp80 2.000000e+00, x86_fp80 4.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.pow.f80(x86_fp80 2.000000e+00, x86_fp80 4.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -335,7 +335,7 @@ define double @call_exp() sanitize_numerical_stability {
; DQQ-LABEL: @call_exp(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @exp(double 1.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 0xK3FFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -348,7 +348,7 @@ define double @call_exp() sanitize_numerical_stability {
; DLQ-LABEL: @call_exp(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @exp(double 1.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 0xK3FFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -365,8 +365,8 @@ entry:
define x86_fp80 @call_expl() sanitize_numerical_stability {
; CHECK-LABEL: @call_expl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @expl(x86_fp80 0xK3FFF8000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @expl(x86_fp80 1.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -410,7 +410,7 @@ define double @call_exp2() sanitize_numerical_stability {
; DQQ-LABEL: @call_exp2(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @exp2(double 1.000000e+00) #[[ATTR3]]
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 0xK3FFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -423,7 +423,7 @@ define double @call_exp2() sanitize_numerical_stability {
; DLQ-LABEL: @call_exp2(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @exp2(double 1.000000e+00) #[[ATTR3]]
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 0xK3FFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -440,8 +440,8 @@ entry:
define x86_fp80 @call_exp2l() sanitize_numerical_stability {
; CHECK-LABEL: @call_exp2l(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @exp2l(x86_fp80 0xK3FFF8000000000000000) #[[ATTR3]]
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @exp2l(x86_fp80 1.000000e+00) #[[ATTR3]]
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.exp2.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -485,7 +485,7 @@ define double @call_log() sanitize_numerical_stability {
; DQQ-LABEL: @call_log(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @log(double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -498,7 +498,7 @@ define double @call_log() sanitize_numerical_stability {
; DLQ-LABEL: @call_log(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @log(double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -515,8 +515,8 @@ entry:
define x86_fp80 @call_logl() sanitize_numerical_stability {
; CHECK-LABEL: @call_logl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @logl(x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @logl(x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log.f80(x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -560,7 +560,7 @@ define double @call_log10() sanitize_numerical_stability {
; DQQ-LABEL: @call_log10(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @log10(double 1.000000e+02)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 0xK4005C800000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 1.000000e+02)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -573,7 +573,7 @@ define double @call_log10() sanitize_numerical_stability {
; DLQ-LABEL: @call_log10(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @log10(double 1.000000e+02)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 0xK4005C800000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 1.000000e+02)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -590,8 +590,8 @@ entry:
define x86_fp80 @call_log10l() sanitize_numerical_stability {
; CHECK-LABEL: @call_log10l(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @log10l(x86_fp80 0xK7FFF0000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 0xK7FFF0000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @log10l(x86_fp80 +snan(0x0))
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log10.f80(x86_fp80 +snan(0x0))
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -635,7 +635,7 @@ define double @call_log2() sanitize_numerical_stability {
; DQQ-LABEL: @call_log2(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @log2(double 8.000000e+00) #[[ATTR3]]
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 0xK40028000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 8.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -648,7 +648,7 @@ define double @call_log2() sanitize_numerical_stability {
; DLQ-LABEL: @call_log2(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @log2(double 8.000000e+00) #[[ATTR3]]
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 0xK40028000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 8.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -665,8 +665,8 @@ entry:
define x86_fp80 @call_log2l() sanitize_numerical_stability {
; CHECK-LABEL: @call_log2l(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @log2l(x86_fp80 0xK40018000000000000000) #[[ATTR3]]
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 0xK40018000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @log2l(x86_fp80 4.000000e+00) #[[ATTR3]]
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.log2.f80(x86_fp80 4.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -710,7 +710,7 @@ define double @call_fabs() sanitize_numerical_stability {
; DQQ-LABEL: @call_fabs(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @fabs(double -1.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 0xKBFFF8000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 -1.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -723,7 +723,7 @@ define double @call_fabs() sanitize_numerical_stability {
; DLQ-LABEL: @call_fabs(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @fabs(double -1.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 0xKBFFF8000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 -1.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -740,8 +740,8 @@ entry:
define x86_fp80 @call_fabsl() sanitize_numerical_stability {
; CHECK-LABEL: @call_fabsl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fabsl(x86_fp80 0xKBFFF8000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 0xKBFFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fabsl(x86_fp80 -1.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 -1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -785,7 +785,7 @@ define double @call_copysign() sanitize_numerical_stability {
; DQQ-LABEL: @call_copysign(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @copysign(double 1.000000e+00, double -2.000000e+00) #[[ATTR3]]
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xKC0008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 1.000000e+00, x86_fp80 -2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -798,7 +798,7 @@ define double @call_copysign() sanitize_numerical_stability {
; DLQ-LABEL: @call_copysign(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @copysign(double 1.000000e+00, double -2.000000e+00) #[[ATTR3]]
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xKC0008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 1.000000e+00, x86_fp80 -2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -815,8 +815,8 @@ entry:
define x86_fp80 @call_copysignl() sanitize_numerical_stability {
; CHECK-LABEL: @call_copysignl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @copysignl(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xKBFFF8000000000000000) #[[ATTR3]]
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xKBFFF8000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @copysignl(x86_fp80 1.000000e+00, x86_fp80 -1.000000e+00) #[[ATTR3]]
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.copysign.f80(x86_fp80 1.000000e+00, x86_fp80 -1.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -860,7 +860,7 @@ define double @call_floor() sanitize_numerical_stability {
; DQQ-LABEL: @call_floor(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @floor(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -873,7 +873,7 @@ define double @call_floor() sanitize_numerical_stability {
; DLQ-LABEL: @call_floor(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @floor(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -890,8 +890,8 @@ entry:
define x86_fp80 @call_floorl() sanitize_numerical_stability {
; CHECK-LABEL: @call_floorl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @floorl(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @floorl(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.floor.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -935,7 +935,7 @@ define double @call_fmax() sanitize_numerical_stability {
; DQQ-LABEL: @call_fmax(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @fmax(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -948,7 +948,7 @@ define double @call_fmax() sanitize_numerical_stability {
; DLQ-LABEL: @call_fmax(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @fmax(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -965,8 +965,8 @@ entry:
define x86_fp80 @call_fmaxl() sanitize_numerical_stability {
; CHECK-LABEL: @call_fmaxl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fmaxl(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fmaxl(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maxnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1010,7 +1010,7 @@ define double @call_fmin() sanitize_numerical_stability {
; DQQ-LABEL: @call_fmin(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @fmin(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1023,7 +1023,7 @@ define double @call_fmin() sanitize_numerical_stability {
; DLQ-LABEL: @call_fmin(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @fmin(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1040,8 +1040,8 @@ entry:
define x86_fp80 @call_fminl() sanitize_numerical_stability {
; CHECK-LABEL: @call_fminl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fminl(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fminl(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1085,7 +1085,7 @@ define double @call_fminimum_num() sanitize_numerical_stability {
; DQQ-LABEL: @call_fminimum_num(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @fminimum_num(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1098,7 +1098,7 @@ define double @call_fminimum_num() sanitize_numerical_stability {
; DLQ-LABEL: @call_fminimum_num(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @fminimum_num(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1115,8 +1115,8 @@ entry:
define x86_fp80 @call_fminimum_numl() sanitize_numerical_stability {
; CHECK-LABEL: @call_fminimum_numl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fminimum_numl(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fminimum_numl(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.minimumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1160,7 +1160,7 @@ define double @call_fmaximum_num() sanitize_numerical_stability {
; DQQ-LABEL: @call_fmaximum_num(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @fmaximum_num(double 1.000000e+00, double 2.000000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1173,7 +1173,7 @@ define double @call_fmaximum_num() sanitize_numerical_stability {
; DLQ-LABEL: @call_fmaximum_num(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @fmaximum_num(double 1.000000e+00, double 2.000000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1190,8 +1190,8 @@ entry:
define x86_fp80 @call_fmaximum_numl() sanitize_numerical_stability {
; CHECK-LABEL: @call_fmaximum_numl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fmaximum_numl(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK40008000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @fmaximum_numl(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.maximumnum.f80(x86_fp80 1.000000e+00, x86_fp80 2.000000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1235,7 +1235,7 @@ define double @call_ceil() sanitize_numerical_stability {
; DQQ-LABEL: @call_ceil(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @ceil(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1248,7 +1248,7 @@ define double @call_ceil() sanitize_numerical_stability {
; DLQ-LABEL: @call_ceil(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @ceil(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1265,8 +1265,8 @@ entry:
define x86_fp80 @call_ceill() sanitize_numerical_stability {
; CHECK-LABEL: @call_ceill(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @ceill(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @ceill(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.ceil.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1310,7 +1310,7 @@ define double @call_trunc() sanitize_numerical_stability {
; DQQ-LABEL: @call_trunc(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @trunc(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1323,7 +1323,7 @@ define double @call_trunc() sanitize_numerical_stability {
; DLQ-LABEL: @call_trunc(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @trunc(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1340,8 +1340,8 @@ entry:
define x86_fp80 @call_truncl() sanitize_numerical_stability {
; CHECK-LABEL: @call_truncl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @truncl(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @truncl(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.trunc.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1385,7 +1385,7 @@ define double @call_rint() sanitize_numerical_stability {
; DQQ-LABEL: @call_rint(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @rint(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1398,7 +1398,7 @@ define double @call_rint() sanitize_numerical_stability {
; DLQ-LABEL: @call_rint(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @rint(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1415,8 +1415,8 @@ entry:
define x86_fp80 @call_rintl() sanitize_numerical_stability {
; CHECK-LABEL: @call_rintl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @rintl(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @rintl(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.rint.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1460,7 +1460,7 @@ define double @call_nearbyint() sanitize_numerical_stability {
; DQQ-LABEL: @call_nearbyint(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @nearbyint(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1473,7 +1473,7 @@ define double @call_nearbyint() sanitize_numerical_stability {
; DLQ-LABEL: @call_nearbyint(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @nearbyint(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1490,8 +1490,8 @@ entry:
define x86_fp80 @call_nearbyintl() sanitize_numerical_stability {
; CHECK-LABEL: @call_nearbyintl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @nearbyintl(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @nearbyintl(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.nearbyint.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1535,7 +1535,7 @@ define double @call_round() sanitize_numerical_stability {
; DQQ-LABEL: @call_round(
; DQQ-NEXT: entry:
; DQQ-NEXT: [[R:%.*]] = call double @round(double 1.500000e+00)
-; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 0xK3FFFC000000000000000)
+; DQQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 1.500000e+00)
; DQQ-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; DQQ-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_double_q(double [[R]], fp128 [[TMP1]], i32 1, i64 0)
; DQQ-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
@@ -1548,7 +1548,7 @@ define double @call_round() sanitize_numerical_stability {
; DLQ-LABEL: @call_round(
; DLQ-NEXT: entry:
; DLQ-NEXT: [[R:%.*]] = call double @round(double 1.500000e+00)
-; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 0xK3FFFC000000000000000)
+; DLQ-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 1.500000e+00)
; DLQ-NEXT: [[TMP1:%.*]] = call i32 @__nsan_internal_check_double_l(double [[R]], x86_fp80 [[TMP0]], i32 1, i64 0)
; DLQ-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
; DLQ-NEXT: [[TMP3:%.*]] = fpext double [[R]] to x86_fp80
@@ -1565,8 +1565,8 @@ entry:
define x86_fp80 @call_roundl() sanitize_numerical_stability {
; CHECK-LABEL: @call_roundl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @roundl(x86_fp80 0xK3FFFC000000000000000)
-; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 0xK3FFFC000000000000000)
+; CHECK-NEXT: [[R:%.*]] = call x86_fp80 @roundl(x86_fp80 1.500000e+00)
+; CHECK-NEXT: [[TMP0:%.*]] = call x86_fp80 @llvm.round.f80(x86_fp80 1.500000e+00)
; CHECK-NEXT: [[TMP1:%.*]] = fpext x86_fp80 [[TMP0]] to fp128
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__nsan_internal_check_longdouble_q(x86_fp80 [[R]], fp128 [[TMP1]], i32 1, i64 0)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 1
diff --git a/llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll b/llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll
index 25341a52440f3..432c811c11524 100644
--- a/llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll
+++ b/llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll
@@ -9,7 +9,7 @@ define void @store_non_float(ptr %dst) sanitize_numerical_stability {
; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 42, ptr [[DST:%.*]], align 1
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @__nsan_get_shadow_ptr_for_float_store(ptr [[DST]], i64 1)
-; CHECK-NEXT: store double 0x36F5000000000000, ptr [[TMP0]], align 1
+; CHECK-NEXT: store double f0x36F5000000000000, ptr [[TMP0]], align 1
; CHECK-NEXT: ret void
;
entry:
@@ -22,7 +22,7 @@ define void @store_non_float_vector(ptr %dst) sanitize_numerical_stability {
; CHECK-NEXT: entry:
; CHECK-NEXT: store <4 x i32> splat (i32 42), ptr [[DST:%.*]], align 1
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @__nsan_get_shadow_ptr_for_float_store(ptr [[DST]], i64 4)
-; CHECK-NEXT: store <4 x double> splat (double 0x36F5000000000000), ptr [[TMP0]], align 1
+; CHECK-NEXT: store <4 x double> splat (double f0x36F5000000000000), ptr [[TMP0]], align 1
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-trig-preop.ll b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-trig-preop.ll
index 4cb217de2b1eb..292dc05756d2f 100644
--- a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-trig-preop.ll
+++ b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-trig-preop.ll
@@ -66,8 +66,8 @@ define double @trig_preop_propagate_nonan(double noundef nofpclass(inf nan) %x){
; CHECK-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[I2:%.*]] = tail call double @llvm.amdgcn.trig.preop.f64(double noundef nofpclass(nan inf) [[X]], i32 noundef 0) #[[ATTR2]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[X]], 0x7B00000000000000
-; CHECK-NEXT: [[I9:%.*]] = fmul double [[X]], 0x37F0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[X]], f0x7B00000000000000
+; CHECK-NEXT: [[I9:%.*]] = fmul double [[X]], f0x37F0000000000000
; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double [[I9]], double [[X]]
; CHECK-NEXT: [[MUL11:%.*]] = fmul double [[I2]], [[COND]]
; CHECK-NEXT: [[FNEG13:%.*]] = fneg double [[MUL11]]
@@ -96,8 +96,8 @@ define double @trig_preop_propagate_nonan_full(double noundef nofpclass(inf nan)
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[I2:%.*]] = tail call double @llvm.amdgcn.trig.preop.f64(double noundef nofpclass(nan inf) [[X]], i32 noundef 0) #[[ATTR2]]
; CHECK-NEXT: [[I4:%.*]] = tail call double @llvm.amdgcn.trig.preop.f64(double noundef nofpclass(nan inf) [[X]], i32 noundef 1) #[[ATTR2]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[X]], 0x7B00000000000000
-; CHECK-NEXT: [[I9:%.*]] = fmul double [[X]], 0x37F0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[X]], f0x7B00000000000000
+; CHECK-NEXT: [[I9:%.*]] = fmul double [[X]], f0x37F0000000000000
; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double [[I9]], double [[X]]
; CHECK-NEXT: [[MUL4:%.*]] = fmul double [[I4]], [[COND]]
; CHECK-NEXT: [[MUL11:%.*]] = fmul double [[I2]], [[COND]]
diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/fp-bc-icmp-const-fold.ll b/llvm/test/Transforms/Attributor/IPConstantProp/fp-bc-icmp-const-fold.ll
index c172eb2975c7d..715c6b50cf2b3 100644
--- a/llvm/test/Transforms/Attributor/IPConstantProp/fp-bc-icmp-const-fold.ll
+++ b/llvm/test/Transforms/Attributor/IPConstantProp/fp-bc-icmp-const-fold.ll
@@ -28,7 +28,7 @@ define void @test(i32 signext %n, i1 %arg) {
; CHECK: if.else14:
; CHECK-NEXT: br label [[DO_BODY:%.*]]
; CHECK: do.body:
-; CHECK-NEXT: [[SCALE_0:%.*]] = phi ppc_fp128 [ 0xM3FF00000000000000000000000000000, [[IF_ELSE14]] ], [ [[SCALE_0]], [[DO_BODY]] ]
+; CHECK-NEXT: [[SCALE_0:%.*]] = phi ppc_fp128 [ 1.000000e+00, [[IF_ELSE14]] ], [ [[SCALE_0]], [[DO_BODY]] ]
; CHECK-NEXT: br i1 [[ARG]], label [[DO_BODY]], label [[IF_THEN33:%.*]]
; CHECK: if.then33:
; CHECK-NEXT: br i1 [[ARG]], label [[_ZN5BOOST4MATH4SIGNIGEEIRKT__EXIT30:%.*]], label [[COND_FALSE_I28:%.*]]
diff --git a/llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll b/llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
index 443771da59ff9..3ff0505e868a6 100644
--- a/llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
@@ -106,7 +106,7 @@ define float @ret_canonicalize_ieee_denormal(float nofpclass(inf) %arg0) denorma
define float @ret_canonicalize_ieee_constant_pos_denormal() denormal_fpenv(ieee|ieee) {
; CHECK-LABEL: define noundef nofpclass(nan inf zero nsub norm) float @ret_canonicalize_ieee_constant_pos_denormal
; CHECK-SAME: () #[[ATTR9]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero nsub norm) float @llvm.canonicalize.f32(float noundef 0x36A0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero nsub norm) float @llvm.canonicalize.f32(float noundef 1.401300e-45) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x36A0000000000000)
@@ -116,7 +116,7 @@ define float @ret_canonicalize_ieee_constant_pos_denormal() denormal_fpenv(ieee|
define float @ret_canonicalize_ieee_constant_neg_denormal() denormal_fpenv(ieee|ieee) {
; CHECK-LABEL: define noundef nofpclass(nan inf zero psub norm) float @ret_canonicalize_ieee_constant_neg_denormal
; CHECK-SAME: () #[[ATTR9]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero psub norm) float @llvm.canonicalize.f32(float noundef 0xB6A0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero psub norm) float @llvm.canonicalize.f32(float noundef -1.401300e-45) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0xb6A0000000000000)
@@ -166,7 +166,7 @@ define float @ret_canonicalize_ieee_constant_neg_normal() denormal_fpenv(ieee|ie
define float @ret_canonicalize_ieee_constant_pos_inf() denormal_fpenv(ieee|ieee) {
; CHECK-LABEL: define noundef nofpclass(nan ninf zero sub norm) float @ret_canonicalize_ieee_constant_pos_inf
; CHECK-SAME: () #[[ATTR9]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf zero sub norm) float @llvm.canonicalize.f32(float noundef +inf) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF0000000000000)
@@ -176,7 +176,7 @@ define float @ret_canonicalize_ieee_constant_pos_inf() denormal_fpenv(ieee|ieee)
define float @ret_canonicalize_ieee_constant_neg_inf() denormal_fpenv(ieee|ieee) {
; CHECK-LABEL: define noundef nofpclass(nan pinf zero sub norm) float @ret_canonicalize_ieee_constant_neg_inf
; CHECK-SAME: () #[[ATTR9]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf zero sub norm) float @llvm.canonicalize.f32(float noundef 0xFFF0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf zero sub norm) float @llvm.canonicalize.f32(float noundef -inf) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0xFFF0000000000000)
@@ -186,7 +186,7 @@ define float @ret_canonicalize_ieee_constant_neg_inf() denormal_fpenv(ieee|ieee)
define float @ret_canonicalize_ieee_constant_qnan() denormal_fpenv(ieee|ieee) {
; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) float @ret_canonicalize_ieee_constant_qnan
; CHECK-SAME: () #[[ATTR9]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF8000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef +qnan) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF8000000000000)
@@ -196,7 +196,7 @@ define float @ret_canonicalize_ieee_constant_qnan() denormal_fpenv(ieee|ieee) {
define float @ret_canonicalize_ieee_constant_snan() denormal_fpenv(ieee|ieee) {
; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) float @ret_canonicalize_ieee_constant_snan
; CHECK-SAME: () #[[ATTR9]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF1000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef +snan(0x80000)) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF1000000000000)
@@ -206,7 +206,7 @@ define float @ret_canonicalize_ieee_constant_snan() denormal_fpenv(ieee|ieee) {
define float @ret_canonicalize_daz_constant_pos_denormal() denormal_fpenv(preservesign) {
; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_daz_constant_pos_denormal
; CHECK-SAME: () #[[ATTR10:[0-9]+]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x36A0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 1.401300e-45) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x36A0000000000000)
@@ -216,7 +216,7 @@ define float @ret_canonicalize_daz_constant_pos_denormal() denormal_fpenv(preser
define float @ret_canonicalize_daz_constant_neg_denormal() denormal_fpenv(preservesign) {
; CHECK-LABEL: define noundef nofpclass(nan inf pzero sub norm) float @ret_canonicalize_daz_constant_neg_denormal
; CHECK-SAME: () #[[ATTR10]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf pzero sub norm) float @llvm.canonicalize.f32(float noundef 0xB6A0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf pzero sub norm) float @llvm.canonicalize.f32(float noundef -1.401300e-45) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0xb6A0000000000000)
@@ -266,7 +266,7 @@ define float @ret_canonicalize_daz_constant_neg_normal() denormal_fpenv(preserve
define float @ret_canonicalize_daz_constant_pos_inf() denormal_fpenv(preservesign) {
; CHECK-LABEL: define noundef nofpclass(nan ninf zero sub norm) float @ret_canonicalize_daz_constant_pos_inf
; CHECK-SAME: () #[[ATTR10]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf zero sub norm) float @llvm.canonicalize.f32(float noundef +inf) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF0000000000000)
@@ -276,7 +276,7 @@ define float @ret_canonicalize_daz_constant_pos_inf() denormal_fpenv(preservesig
define float @ret_canonicalize_daz_constant_neg_inf() denormal_fpenv(preservesign) {
; CHECK-LABEL: define noundef nofpclass(nan pinf zero sub norm) float @ret_canonicalize_daz_constant_neg_inf
; CHECK-SAME: () #[[ATTR10]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf zero sub norm) float @llvm.canonicalize.f32(float noundef 0xFFF0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf zero sub norm) float @llvm.canonicalize.f32(float noundef -inf) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0xFFF0000000000000)
@@ -286,7 +286,7 @@ define float @ret_canonicalize_daz_constant_neg_inf() denormal_fpenv(preservesig
define float @ret_canonicalize_daz_constant_qnan() denormal_fpenv(preservesign) {
; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) float @ret_canonicalize_daz_constant_qnan
; CHECK-SAME: () #[[ATTR10]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF8000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef +qnan) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF8000000000000)
@@ -296,7 +296,7 @@ define float @ret_canonicalize_daz_constant_qnan() denormal_fpenv(preservesign)
define float @ret_canonicalize_daz_constant_snan() denormal_fpenv(preservesign) {
; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) float @ret_canonicalize_daz_constant_snan
; CHECK-SAME: () #[[ATTR10]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF1000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef +snan(0x80000)) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF1000000000000)
@@ -306,7 +306,7 @@ define float @ret_canonicalize_daz_constant_snan() denormal_fpenv(preservesign)
define float @ret_canonicalize_dapz_constant_pos_denormal() denormal_fpenv(positivezero|positivezero) {
; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_dapz_constant_pos_denormal
; CHECK-SAME: () #[[ATTR11:[0-9]+]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x36A0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 1.401300e-45) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x36A0000000000000)
@@ -316,7 +316,7 @@ define float @ret_canonicalize_dapz_constant_pos_denormal() denormal_fpenv(posit
define float @ret_canonicalize_dapz_constant_neg_denormal() denormal_fpenv(positivezero|positivezero) {
; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_dapz_constant_neg_denormal
; CHECK-SAME: () #[[ATTR11]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0xB6A0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef -1.401300e-45) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0xb6A0000000000000)
@@ -366,7 +366,7 @@ define float @ret_canonicalize_dapz_constant_neg_normal() denormal_fpenv(positiv
define float @ret_canonicalize_dapz_constant_pos_inf() denormal_fpenv(positivezero|positivezero) {
; CHECK-LABEL: define noundef nofpclass(nan ninf nzero sub norm) float @ret_canonicalize_dapz_constant_pos_inf
; CHECK-SAME: () #[[ATTR11]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf nzero sub norm) float @llvm.canonicalize.f32(float noundef +inf) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF0000000000000)
@@ -376,7 +376,7 @@ define float @ret_canonicalize_dapz_constant_pos_inf() denormal_fpenv(positiveze
define float @ret_canonicalize_dapz_constant_neg_inf() denormal_fpenv(positivezero|positivezero) {
; CHECK-LABEL: define noundef nofpclass(nan pinf nzero sub norm) float @ret_canonicalize_dapz_constant_neg_inf
; CHECK-SAME: () #[[ATTR11]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0xFFF0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf nzero sub norm) float @llvm.canonicalize.f32(float noundef -inf) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0xFFF0000000000000)
@@ -386,7 +386,7 @@ define float @ret_canonicalize_dapz_constant_neg_inf() denormal_fpenv(positiveze
define float @ret_canonicalize_dapz_constant_qnan() denormal_fpenv(positivezero|positivezero) {
; CHECK-LABEL: define noundef nofpclass(snan inf nzero sub norm) float @ret_canonicalize_dapz_constant_qnan
; CHECK-SAME: () #[[ATTR11]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF8000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef +qnan) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF8000000000000)
@@ -396,7 +396,7 @@ define float @ret_canonicalize_dapz_constant_qnan() denormal_fpenv(positivezero|
define float @ret_canonicalize_dapz_constant_snan() denormal_fpenv(positivezero|positivezero) {
; CHECK-LABEL: define noundef nofpclass(snan inf nzero sub norm) float @ret_canonicalize_dapz_constant_snan
; CHECK-SAME: () #[[ATTR11]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF1000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef +snan(0x80000)) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF1000000000000)
@@ -406,7 +406,7 @@ define float @ret_canonicalize_dapz_constant_snan() denormal_fpenv(positivezero|
define float @ret_canonicalize_dynamic_constant_pos_denormal() denormal_fpenv(dynamic) {
; CHECK-LABEL: define noundef nofpclass(nan inf nsub norm) float @ret_canonicalize_dynamic_constant_pos_denormal
; CHECK-SAME: () #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nsub norm) float @llvm.canonicalize.f32(float noundef 0x36A0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nsub norm) float @llvm.canonicalize.f32(float noundef 1.401300e-45) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x36A0000000000000)
@@ -416,7 +416,7 @@ define float @ret_canonicalize_dynamic_constant_pos_denormal() denormal_fpenv(dy
define float @ret_canonicalize_dynamic_constant_neg_denormal() denormal_fpenv(dynamic) {
; CHECK-LABEL: define noundef nofpclass(nan inf psub norm) float @ret_canonicalize_dynamic_constant_neg_denormal
; CHECK-SAME: () #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf psub norm) float @llvm.canonicalize.f32(float noundef 0xB6A0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf psub norm) float @llvm.canonicalize.f32(float noundef -1.401300e-45) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0xb6A0000000000000)
@@ -466,7 +466,7 @@ define float @ret_canonicalize_dynamic_constant_neg_normal() denormal_fpenv(dyna
define float @ret_canonicalize_dynamic_constant_pos_inf() denormal_fpenv(dynamic) {
; CHECK-LABEL: define noundef nofpclass(nan ninf sub norm) float @ret_canonicalize_dynamic_constant_pos_inf
; CHECK-SAME: () #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf sub norm) float @llvm.canonicalize.f32(float noundef +inf) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF0000000000000)
@@ -476,7 +476,7 @@ define float @ret_canonicalize_dynamic_constant_pos_inf() denormal_fpenv(dynamic
define float @ret_canonicalize_dynamic_constant_neg_inf() denormal_fpenv(dynamic) {
; CHECK-LABEL: define noundef nofpclass(nan pinf sub norm) float @ret_canonicalize_dynamic_constant_neg_inf
; CHECK-SAME: () #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf sub norm) float @llvm.canonicalize.f32(float noundef 0xFFF0000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf sub norm) float @llvm.canonicalize.f32(float noundef -inf) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0xFFF0000000000000)
@@ -486,7 +486,7 @@ define float @ret_canonicalize_dynamic_constant_neg_inf() denormal_fpenv(dynamic
define float @ret_canonicalize_dynamic_constant_qnan() denormal_fpenv(dynamic) {
; CHECK-LABEL: define noundef nofpclass(snan inf sub norm) float @ret_canonicalize_dynamic_constant_qnan
; CHECK-SAME: () #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF8000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf sub norm) float @llvm.canonicalize.f32(float noundef +qnan) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF8000000000000)
@@ -496,7 +496,7 @@ define float @ret_canonicalize_dynamic_constant_qnan() denormal_fpenv(dynamic) {
define float @ret_canonicalize_dynamic_constant_snan() denormal_fpenv(dynamic) {
; CHECK-LABEL: define noundef nofpclass(snan inf sub norm) float @ret_canonicalize_dynamic_constant_snan
; CHECK-SAME: () #[[ATTR2]] {
-; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF1000000000000) #[[ATTR12]]
+; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf sub norm) float @llvm.canonicalize.f32(float noundef +snan(0x80000)) #[[ATTR12]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @llvm.canonicalize.f32(float 0x7FF1000000000000)
diff --git a/llvm/test/Transforms/Attributor/nofpclass-fmul.ll b/llvm/test/Transforms/Attributor/nofpclass-fmul.ll
index 1b1cf60a33500..ba98a804afcb4 100644
--- a/llvm/test/Transforms/Attributor/nofpclass-fmul.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass-fmul.ll
@@ -37,7 +37,7 @@ define float @ret_fmul_square_f32_maybe_undef(float %arg) {
define float @ret_mul_exponent_f32_22(float %arg0) {
; CHECK-LABEL: define float @ret_mul_exponent_f32_22(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x4150000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x4A800000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x4150000000000000
@@ -77,7 +77,7 @@ define float @ret_fmul_square_f32_src_no_qnan(float noundef nofpclass(qnan) %arg
define float @ret_mul_exponent_f32_23(float %arg0) {
; CHECK-LABEL: define nofpclass(sub) float @ret_mul_exponent_f32_23(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x4160000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x4B000000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x4160000000000000
@@ -87,7 +87,7 @@ define float @ret_mul_exponent_f32_23(float %arg0) {
define float @ret_mul_exponent_f32_24(float %arg0) {
; CHECK-LABEL: define nofpclass(sub) float @ret_mul_exponent_f32_24(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x4170000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x4B800000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x4170000000000000
@@ -97,7 +97,7 @@ define float @ret_mul_exponent_f32_24(float %arg0) {
define float @ret_mul_exponent_f32_23_nnan(float nofpclass(nan) %arg0) {
; CHECK-LABEL: define nofpclass(nan sub) float @ret_mul_exponent_f32_23_nnan(
; CHECK-SAME: float nofpclass(nan) [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x4160000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x4B000000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x4160000000000000
@@ -107,7 +107,7 @@ define float @ret_mul_exponent_f32_23_nnan(float nofpclass(nan) %arg0) {
define double @ret_mul_exponent_f64_24(double %arg0) {
; CHECK-LABEL: define double @ret_mul_exponent_f64_24(
; CHECK-SAME: double [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul double [[ARG0]], 0x4170000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul double [[ARG0]], f0x4170000000000000
; CHECK-NEXT: ret double [[CALL]]
;
%call = fmul double %arg0, 0x4170000000000000
@@ -117,7 +117,7 @@ define double @ret_mul_exponent_f64_24(double %arg0) {
define double @ret_mul_exponent_f64_51(double %arg0) {
; CHECK-LABEL: define double @ret_mul_exponent_f64_51(
; CHECK-SAME: double [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul double [[ARG0]], 0x4320000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul double [[ARG0]], f0x4320000000000000
; CHECK-NEXT: ret double [[CALL]]
;
%call = fmul double %arg0, 0x4320000000000000
@@ -127,7 +127,7 @@ define double @ret_mul_exponent_f64_51(double %arg0) {
define double @ret_mul_exponent_f64_52(double %arg0) {
; CHECK-LABEL: define nofpclass(sub) double @ret_mul_exponent_f64_52(
; CHECK-SAME: double [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul double [[ARG0]], 0x4330000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul double [[ARG0]], f0x4330000000000000
; CHECK-NEXT: ret double [[CALL]]
;
%call = fmul double %arg0, 0x4330000000000000
@@ -137,7 +137,7 @@ define double @ret_mul_exponent_f64_52(double %arg0) {
define double @ret_mul_exponent_f64_53(double %arg0) {
; CHECK-LABEL: define nofpclass(sub) double @ret_mul_exponent_f64_53(
; CHECK-SAME: double [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul double [[ARG0]], 0x4340000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul double [[ARG0]], f0x4340000000000000
; CHECK-NEXT: ret double [[CALL]]
;
%call = fmul double %arg0, 0x4340000000000000
@@ -147,7 +147,7 @@ define double @ret_mul_exponent_f64_53(double %arg0) {
define half @ret_mul_exponent_f16_8(half %arg0) {
; CHECK-LABEL: define half @ret_mul_exponent_f16_8(
; CHECK-SAME: half [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul half [[ARG0]], 0xH5C00
+; CHECK-NEXT: [[CALL:%.*]] = fmul half [[ARG0]], 2.560000e+02
; CHECK-NEXT: ret half [[CALL]]
;
%call = fmul half %arg0, 0xH5C00
@@ -157,7 +157,7 @@ define half @ret_mul_exponent_f16_8(half %arg0) {
define half @ret_mul_exponent_f16_9(half %arg0) {
; CHECK-LABEL: define half @ret_mul_exponent_f16_9(
; CHECK-SAME: half [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul half [[ARG0]], 0xH6000
+; CHECK-NEXT: [[CALL:%.*]] = fmul half [[ARG0]], 5.120000e+02
; CHECK-NEXT: ret half [[CALL]]
;
%call = fmul half %arg0, 0xH6000
@@ -167,7 +167,7 @@ define half @ret_mul_exponent_f16_9(half %arg0) {
define half @ret_mul_exponent_f16_10(half %arg0) {
; CHECK-LABEL: define nofpclass(sub) half @ret_mul_exponent_f16_10(
; CHECK-SAME: half [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul half [[ARG0]], 0xH6400
+; CHECK-NEXT: [[CALL:%.*]] = fmul half [[ARG0]], 1.024000e+03
; CHECK-NEXT: ret half [[CALL]]
;
%call = fmul half %arg0, 0xH6400
@@ -177,7 +177,7 @@ define half @ret_mul_exponent_f16_10(half %arg0) {
define bfloat @ret_mul_exponent_bf16_6(bfloat %arg0) {
; CHECK-LABEL: define bfloat @ret_mul_exponent_bf16_6(
; CHECK-SAME: bfloat [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul bfloat [[ARG0]], 0xR4280
+; CHECK-NEXT: [[CALL:%.*]] = fmul bfloat [[ARG0]], 6.400000e+01
; CHECK-NEXT: ret bfloat [[CALL]]
;
%call = fmul bfloat %arg0, 0xR4280
@@ -187,7 +187,7 @@ define bfloat @ret_mul_exponent_bf16_6(bfloat %arg0) {
define bfloat @ret_mul_exponent_bf16_7(bfloat %arg0) {
; CHECK-LABEL: define nofpclass(sub) bfloat @ret_mul_exponent_bf16_7(
; CHECK-SAME: bfloat [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul bfloat [[ARG0]], 0xR4300
+; CHECK-NEXT: [[CALL:%.*]] = fmul bfloat [[ARG0]], 1.280000e+02
; CHECK-NEXT: ret bfloat [[CALL]]
;
%call = fmul bfloat %arg0, 0xR4300
@@ -197,7 +197,7 @@ define bfloat @ret_mul_exponent_bf16_7(bfloat %arg0) {
define bfloat @ret_mul_exponent_bf16_8(bfloat %arg0) {
; CHECK-LABEL: define nofpclass(sub) bfloat @ret_mul_exponent_bf16_8(
; CHECK-SAME: bfloat [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul bfloat [[ARG0]], 0xR4380
+; CHECK-NEXT: [[CALL:%.*]] = fmul bfloat [[ARG0]], 2.560000e+02
; CHECK-NEXT: ret bfloat [[CALL]]
;
%call = fmul bfloat %arg0, 0xR4380
@@ -207,7 +207,7 @@ define bfloat @ret_mul_exponent_bf16_8(bfloat %arg0) {
define float @ret_mul_exponent_f32_neg22(float %arg0) {
; CHECK-LABEL: define float @ret_mul_exponent_f32_neg22(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x3E90000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x34800000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x3E90000000000000
@@ -217,7 +217,7 @@ define float @ret_mul_exponent_f32_neg22(float %arg0) {
define float @ret_mul_exponent_f32_neg23(float %arg0) {
; CHECK-LABEL: define float @ret_mul_exponent_f32_neg23(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x3E80000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x34000000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x3E80000000000000
@@ -227,7 +227,7 @@ define float @ret_mul_exponent_f32_neg23(float %arg0) {
define float @ret_mul_exponent_f32_neg24(float %arg0) {
; CHECK-LABEL: define float @ret_mul_exponent_f32_neg24(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x3E70000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x33800000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x3E70000000000000
@@ -237,7 +237,7 @@ define float @ret_mul_exponent_f32_neg24(float %arg0) {
define float @ret_mul_exponent_f32_neg126(float %arg0) {
; CHECK-LABEL: define float @ret_mul_exponent_f32_neg126(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x3810000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x00800000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x3810000000000000
@@ -247,7 +247,7 @@ define float @ret_mul_exponent_f32_neg126(float %arg0) {
define float @ret_mul_exponent_f32_neg127(float %arg0) {
; CHECK-LABEL: define float @ret_mul_exponent_f32_neg127(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x3800000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], f0x00400000
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x3800000000000000
@@ -257,7 +257,7 @@ define float @ret_mul_exponent_f32_neg127(float %arg0) {
define <2 x float> @ret_mul_exponent_v2f32_splat_23(<2 x float> %arg0) {
; CHECK-LABEL: define nofpclass(sub) <2 x float> @ret_mul_exponent_v2f32_splat_23(
; CHECK-SAME: <2 x float> [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul <2 x float> [[ARG0]], splat (float 0x4160000000000000)
+; CHECK-NEXT: [[CALL:%.*]] = fmul <2 x float> [[ARG0]], splat (float f0x4B000000)
; CHECK-NEXT: ret <2 x float> [[CALL]]
;
%call = fmul <2 x float> %arg0, splat (float 0x4160000000000000)
@@ -267,7 +267,7 @@ define <2 x float> @ret_mul_exponent_v2f32_splat_23(<2 x float> %arg0) {
define <2 x float> @ret_mul_exponent_v2f32_splat_poison_23(<2 x float> %arg0) {
; CHECK-LABEL: define <2 x float> @ret_mul_exponent_v2f32_splat_poison_23(
; CHECK-SAME: <2 x float> [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul <2 x float> [[ARG0]], <float 0x4160000000000000, float poison>
+; CHECK-NEXT: [[CALL:%.*]] = fmul <2 x float> [[ARG0]], <float f0x4B000000, float poison>
; CHECK-NEXT: ret <2 x float> [[CALL]]
;
%call = fmul <2 x float> %arg0, <float 0x4160000000000000, float poison>
@@ -278,7 +278,7 @@ define <2 x float> @ret_mul_exponent_v2f32_splat_poison_23(<2 x float> %arg0) {
define <2 x float> @ret_mul_exponent_v2f32_nonsplat(<2 x float> %arg0) {
; CHECK-LABEL: define <2 x float> @ret_mul_exponent_v2f32_nonsplat(
; CHECK-SAME: <2 x float> [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul <2 x float> [[ARG0]], <float 0x4160000000000000, float 0x4170000000000000>
+; CHECK-NEXT: [[CALL:%.*]] = fmul <2 x float> [[ARG0]], <float f0x4B000000, float f0x4B800000>
; CHECK-NEXT: ret <2 x float> [[CALL]]
;
%call = fmul <2 x float> %arg0, <float 0x4160000000000000, float 0x4170000000000000>
@@ -289,7 +289,7 @@ define <2 x float> @ret_mul_exponent_v2f32_nonsplat(<2 x float> %arg0) {
define <2 x float> @ret_mul_partially_foldable_exponent_v2f32(<2 x float> %arg0) {
; CHECK-LABEL: define <2 x float> @ret_mul_partially_foldable_exponent_v2f32(
; CHECK-SAME: <2 x float> [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul <2 x float> [[ARG0]], <float 0x4160000000000000, float 0x4150000000000000>
+; CHECK-NEXT: [[CALL:%.*]] = fmul <2 x float> [[ARG0]], <float f0x4B000000, float f0x4A800000>
; CHECK-NEXT: ret <2 x float> [[CALL]]
;
%call = fmul <2 x float> %arg0, <float 0x4160000000000000, float 0x4150000000000000>
@@ -309,7 +309,7 @@ define float @ret_mul_f32_0(float %arg0) {
define float @ret_mul_f32_inf(float %arg0) {
; CHECK-LABEL: define nofpclass(zero sub norm) float @ret_mul_f32_inf(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x7FF0000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], +inf
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x7FF0000000000000
@@ -319,7 +319,7 @@ define float @ret_mul_f32_inf(float %arg0) {
define float @ret_mul_f32_nan(float %arg0) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_mul_f32_nan(
; CHECK-SAME: float [[ARG0:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], 0x7FF8000000000000
+; CHECK-NEXT: [[CALL:%.*]] = fmul float [[ARG0]], +qnan
; CHECK-NEXT: ret float [[CALL]]
;
%call = fmul float %arg0, 0x7FF8000000000000
@@ -882,7 +882,7 @@ define float @ret_fmul__not_inf__2(float nofpclass(inf) %x) {
define float @ret_fmul__not_inf__nextup_1(float nofpclass(inf) %x) {
; CHECK-LABEL: define float @ret_fmul__not_inf__nextup_1(
; CHECK-SAME: float nofpclass(inf) [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X]], 0x3FF0000020000000
+; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X]], f0x3F800001
; CHECK-NEXT: ret float [[MUL]]
;
%mul = fmul float %x, 0x3ff0000020000000
diff --git a/llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll b/llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll
index 48a66f7e75a90..3c57132847bd1 100644
--- a/llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll
@@ -642,7 +642,7 @@ define float @fcmp_fabs_one_1_neg2_else_arg(float noundef %arg) {
define float @clamp_olt_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(ninf nzero nsub nnorm) float @clamp_olt_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_OLT_LARGEST_DENORMAL:%.*]] = fcmp olt float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_OLT_LARGEST_DENORMAL:%.*]] = fcmp olt float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLT_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -654,7 +654,7 @@ define float @clamp_olt_largest_denormal_0.0(float noundef %arg) {
define float @clamp_ole_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(ninf nzero nsub nnorm) float @clamp_ole_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_OLE_LARGEST_DENORMAL:%.*]] = fcmp ole float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_OLE_LARGEST_DENORMAL:%.*]] = fcmp ole float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -666,7 +666,7 @@ define float @clamp_ole_largest_denormal_0.0(float noundef %arg) {
define float @clamp_ult_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan ninf nzero nsub nnorm) float @clamp_ult_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_ULT_LARGEST_DENORMAL:%.*]] = fcmp ult float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_ULT_LARGEST_DENORMAL:%.*]] = fcmp ult float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULT_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -678,7 +678,7 @@ define float @clamp_ult_largest_denormal_0.0(float noundef %arg) {
define float @clamp_ule_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan ninf nzero nsub nnorm) float @clamp_ule_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_ULE_LARGEST_DENORMAL:%.*]] = fcmp ule float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_ULE_LARGEST_DENORMAL:%.*]] = fcmp ule float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ULE_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -690,7 +690,7 @@ define float @clamp_ule_largest_denormal_0.0(float noundef %arg) {
define float @clamp_ogt_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan ninf nzero nsub nnorm) float @clamp_ogt_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_OGT_LARGEST_DENORMAL:%.*]] = fcmp ogt float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_OGT_LARGEST_DENORMAL:%.*]] = fcmp ogt float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -702,7 +702,7 @@ define float @clamp_ogt_largest_denormal_0.0(float noundef %arg) {
define float @clamp_oge_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan ninf nzero nsub nnorm) float @clamp_oge_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_OGE_LARGEST_DENORMAL:%.*]] = fcmp oge float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_OGE_LARGEST_DENORMAL:%.*]] = fcmp oge float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -714,7 +714,7 @@ define float @clamp_oge_largest_denormal_0.0(float noundef %arg) {
define float @clamp_ugt_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(ninf nzero nsub nnorm) float @clamp_ugt_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_UGT_LARGEST_DENORMAL:%.*]] = fcmp ugt float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_UGT_LARGEST_DENORMAL:%.*]] = fcmp ugt float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -726,7 +726,7 @@ define float @clamp_ugt_largest_denormal_0.0(float noundef %arg) {
define float @clamp_uge_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(ninf nzero nsub nnorm) float @clamp_uge_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_UGE_LARGEST_DENORMAL:%.*]] = fcmp uge float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_UGE_LARGEST_DENORMAL:%.*]] = fcmp uge float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGE_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -738,7 +738,7 @@ define float @clamp_uge_largest_denormal_0.0(float noundef %arg) {
define float @fcmp_oeq_largest_denormal_arg_else_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan inf nzero nsub norm) float @fcmp_oeq_largest_denormal_arg_else_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_OEQ_LARGEST_DENORMAL:%.*]] = fcmp oeq float [[ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_OEQ_LARGEST_DENORMAL:%.*]] = fcmp oeq float [[ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OEQ_LARGEST_DENORMAL]], float [[ARG]], float 0.000000e+00
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -751,7 +751,7 @@ define float @clamp_fabs_olt_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nzero) float @clamp_fabs_olt_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_FABS_OLT_LARGEST_DENORMAL:%.*]] = fcmp olt float [[FABS_ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_FABS_OLT_LARGEST_DENORMAL:%.*]] = fcmp olt float [[FABS_ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_FABS_OLT_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -765,7 +765,7 @@ define float @clamp_fabs_ole_largest_denormal_0.0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nzero) float @clamp_fabs_ole_largest_denormal_0.0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_FABS_OLE_LARGEST_DENORMAL:%.*]] = fcmp ole float [[FABS_ARG]], 0x380FFFFFC0000000
+; CHECK-NEXT: [[IS_FABS_OLE_LARGEST_DENORMAL:%.*]] = fcmp ole float [[FABS_ARG]], f0x007FFFFF
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_FABS_OLE_LARGEST_DENORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -923,8 +923,8 @@ define float @clamp_fabs_value_ule_1_to_1_copysign(float noundef %arg) {
define float @clamp_is_ogt_largest_normal_to_largest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(pinf) float @clamp_is_ogt_largest_normal_to_largest_normal(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_OGT_LARGEST_NORMAL:%.*]] = fcmp ogt float [[ARG]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]]
+; CHECK-NEXT: [[IS_OGT_LARGEST_NORMAL:%.*]] = fcmp ogt float [[ARG]], f0x7F7FFFFF
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_LARGEST_NORMAL]], float f0x7F7FFFFF, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%is.ogt.largest.normal = fcmp ogt float %arg, 0x47EFFFFFE0000000
@@ -936,8 +936,8 @@ define float @clamp_is_ogt_largest_normal_to_largest_normal(float noundef %arg)
define float @clamp_is_oge_largest_normal_to_largest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(pinf) float @clamp_is_oge_largest_normal_to_largest_normal(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_OGE_LARGEST_NORMAL:%.*]] = fcmp oge float [[ARG]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]]
+; CHECK-NEXT: [[IS_OGE_LARGEST_NORMAL:%.*]] = fcmp oge float [[ARG]], f0x7F7FFFFF
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_LARGEST_NORMAL]], float f0x7F7FFFFF, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%is.oge.largest.normal = fcmp oge float %arg, 0x47EFFFFFE0000000
@@ -949,8 +949,8 @@ define float @clamp_is_oge_largest_normal_to_largest_normal(float noundef %arg)
define float @clamp_is_ugt_largest_normal_to_largest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan pinf) float @clamp_is_ugt_largest_normal_to_largest_normal(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp ugt float [[ARG]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]]
+; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp ugt float [[ARG]], f0x7F7FFFFF
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float f0x7F7FFFFF, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%is.ugt.largest.normal = fcmp ugt float %arg, 0x47EFFFFFE0000000
@@ -962,8 +962,8 @@ define float @clamp_is_ugt_largest_normal_to_largest_normal(float noundef %arg)
define float @clamp_is_uge_largest_normal_to_largest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan pinf) float @clamp_is_uge_largest_normal_to_largest_normal(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[IS_UGE_LARGEST_NORMAL:%.*]] = fcmp uge float [[ARG]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGE_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]]
+; CHECK-NEXT: [[IS_UGE_LARGEST_NORMAL:%.*]] = fcmp uge float [[ARG]], f0x7F7FFFFF
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGE_LARGEST_NORMAL]], float f0x7F7FFFFF, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%is.uge.largest.normal = fcmp uge float %arg, 0x47EFFFFFE0000000
@@ -976,8 +976,8 @@ define float @clamp_fabs_is_ogt_largest_normal_to_largest_normal(float noundef %
; CHECK-LABEL: define noundef nofpclass(inf) float @clamp_fabs_is_ogt_largest_normal_to_largest_normal(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OGT_LARGEST_NORMAL:%.*]] = fcmp ogt float [[FABS_ARG]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]]
+; CHECK-NEXT: [[IS_OGT_LARGEST_NORMAL:%.*]] = fcmp ogt float [[FABS_ARG]], f0x7F7FFFFF
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_LARGEST_NORMAL]], float f0x7F7FFFFF, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%fabs.arg = call float @llvm.fabs.f32(float %arg)
@@ -991,8 +991,8 @@ define float @clamp_fabs_is_oge_largest_normal_to_largest_normal(float noundef %
; CHECK-LABEL: define noundef nofpclass(inf) float @clamp_fabs_is_oge_largest_normal_to_largest_normal(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OGE_LARGEST_NORMAL:%.*]] = fcmp oge float [[FABS_ARG]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]]
+; CHECK-NEXT: [[IS_OGE_LARGEST_NORMAL:%.*]] = fcmp oge float [[FABS_ARG]], f0x7F7FFFFF
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_LARGEST_NORMAL]], float f0x7F7FFFFF, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%fabs.arg = call float @llvm.fabs.f32(float %arg)
@@ -1006,8 +1006,8 @@ define float @clamp_fabs_is_ugt_largest_normal_to_largest_normal(float noundef %
; CHECK-LABEL: define noundef nofpclass(nan inf) float @clamp_fabs_is_ugt_largest_normal_to_largest_normal(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp ugt float [[FABS_ARG]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]]
+; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp ugt float [[FABS_ARG]], f0x7F7FFFFF
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float f0x7F7FFFFF, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%fabs.arg = call float @llvm.fabs.f32(float %arg)
@@ -1021,8 +1021,8 @@ define float @clamp_fabs_is_uge_largest_normal_to_largest_normal(float noundef %
; CHECK-LABEL: define noundef nofpclass(nan inf) float @clamp_fabs_is_uge_largest_normal_to_largest_normal(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp uge float [[FABS_ARG]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float 0x47EFFFFFE0000000, float [[ARG]]
+; CHECK-NEXT: [[IS_UGT_LARGEST_NORMAL:%.*]] = fcmp uge float [[FABS_ARG]], f0x7F7FFFFF
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UGT_LARGEST_NORMAL]], float f0x7F7FFFFF, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%fabs.arg = call float @llvm.fabs.f32(float %arg)
@@ -1040,7 +1040,7 @@ define float @clamp_fabs_ogt_smallest_normal_to_zero(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(inf) float @clamp_fabs_ogt_smallest_normal_to_zero(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OGT_SMALLEST_NORMAL:%.*]] = fcmp ogt float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OGT_SMALLEST_NORMAL:%.*]] = fcmp ogt float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGT_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1056,7 +1056,7 @@ define float @clamp_fabs_oge_smallest_normal_to_zero(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(inf norm) float @clamp_fabs_oge_smallest_normal_to_zero(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OGE_SMALLEST_NORMAL:%.*]] = fcmp oge float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OGE_SMALLEST_NORMAL:%.*]] = fcmp oge float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OGE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1071,7 +1071,7 @@ define float @clamp_fabs_olt_smallest_normal_to_zero(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nzero sub) float @clamp_fabs_olt_smallest_normal_to_zero(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OLT_SMALLEST_NORMAL:%.*]] = fcmp olt float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OLT_SMALLEST_NORMAL:%.*]] = fcmp olt float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLT_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1086,7 +1086,7 @@ define float @clamp_fabs_ole_smallest_normal_to_zero(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nzero sub) float @clamp_fabs_ole_smallest_normal_to_zero(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OLE_SMALLEST_NORMAL:%.*]] = fcmp ole float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OLE_SMALLEST_NORMAL:%.*]] = fcmp ole float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1100,7 +1100,7 @@ define float @clamp_fabs_is_is_olt_smallest_normal_to_0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nzero sub) float @clamp_fabs_is_is_olt_smallest_normal_to_0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OLT_SMALLEST_NORMAL:%.*]] = fcmp olt float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OLT_SMALLEST_NORMAL:%.*]] = fcmp olt float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLT_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1114,7 +1114,7 @@ define float @clamp_fabs_is_is_ole_smallest_normal_to_0(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nzero sub) float @clamp_fabs_is_is_ole_smallest_normal_to_0(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OLE_SMALLEST_NORMAL:%.*]] = fcmp ole float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OLE_SMALLEST_NORMAL:%.*]] = fcmp ole float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OLE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1128,7 +1128,7 @@ define float @clamp_fabs_oeq_smallest_normal_to_zero(float noundef %arg) {
; CHECK-LABEL: define noundef float @clamp_fabs_oeq_smallest_normal_to_zero(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_OEQ_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1142,7 +1142,7 @@ define float @clamp_fabs_one_smallest_normal_to_zero(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(inf nzero sub) float @clamp_fabs_one_smallest_normal_to_zero(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ONE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1156,7 +1156,7 @@ define float @clamp_fabs_ueq_smallest_normal_to_zero(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan) float @clamp_fabs_ueq_smallest_normal_to_zero(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UEQ_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -1170,7 +1170,7 @@ define float @clamp_fabs_une_smallest_normal_to_zero(float noundef %arg) {
; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub) float @clamp_fabs_une_smallest_normal_to_zero(
; CHECK-SAME: float noundef [[ARG:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_UNE_SMALLEST_NORMAL:%.*]] = fcmp une float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_UNE_SMALLEST_NORMAL:%.*]] = fcmp une float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_UNE_SMALLEST_NORMAL]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -2258,7 +2258,7 @@ define float @ret_assumed_uge_known_negative(float %arg, float %unknown) {
define float @assume_oeq_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_oeq_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_OEQ_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2270,7 +2270,7 @@ define float @assume_oeq_smallest_normal(float noundef %arg) {
define float @assume_one_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_one_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_ONE_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2282,7 +2282,7 @@ define float @assume_one_smallest_normal(float noundef %arg) {
define float @assume_ueq_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_ueq_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_UEQ_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2294,7 +2294,7 @@ define float @assume_ueq_smallest_normal(float noundef %arg) {
define float @assume_une_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_une_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[IS_UNE_SMALLEST_NORMAL:%.*]] = fcmp une float [[ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_UNE_SMALLEST_NORMAL:%.*]] = fcmp une float [[ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_UNE_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2306,7 +2306,7 @@ define float @assume_une_smallest_normal(float noundef %arg) {
define float @assume_ord_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_ord_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[IS_ORD_SMALLEST_NORMAL:%.*]] = fcmp ord float [[ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_ORD_SMALLEST_NORMAL:%.*]] = fcmp ord float [[ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_ORD_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2318,7 +2318,7 @@ define float @assume_ord_smallest_normal(float noundef %arg) {
define float @assume_uno_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_uno_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[IS_UNO_SMALLEST_NORMAL:%.*]] = fcmp uno float [[ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_UNO_SMALLEST_NORMAL:%.*]] = fcmp uno float [[ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_UNO_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2331,7 +2331,7 @@ define float @assume_fabs_oeq_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_fabs_oeq_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_OEQ_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2345,7 +2345,7 @@ define float @assume_fabs_one_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_fabs_one_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_ONE_SMALLEST_NORMAL:%.*]] = fcmp one float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_ONE_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2359,7 +2359,7 @@ define float @assume_fabs_ueq_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_fabs_ueq_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_UEQ_SMALLEST_NORMAL:%.*]] = fcmp ueq float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_UEQ_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2373,7 +2373,7 @@ define float @assume_fabs_une_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_fabs_une_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_UNE_SMALLEST_NORMAL:%.*]] = fcmp une float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_UNE_SMALLEST_NORMAL:%.*]] = fcmp une float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_UNE_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2387,7 +2387,7 @@ define float @assume_fabs_ord_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_fabs_ord_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_ORD_SMALLEST_NORMAL:%.*]] = fcmp ord float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_ORD_SMALLEST_NORMAL:%.*]] = fcmp ord float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_ORD_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2401,7 +2401,7 @@ define float @assume_fabs_uno_smallest_normal(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_fabs_uno_smallest_normal(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[IS_UNO_SMALLEST_NORMAL:%.*]] = fcmp uno float [[FABS_ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_UNO_SMALLEST_NORMAL:%.*]] = fcmp uno float [[FABS_ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_UNO_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2414,7 +2414,7 @@ define float @assume_fabs_uno_smallest_normal(float noundef %arg) {
define float @assume_oeq_smallest_normal_known_pos(float nofpclass(ninf nsub nnorm nzero) %arg) {
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @assume_oeq_smallest_normal_known_pos(
; CHECK-SAME: float returned nofpclass(ninf nzero nsub nnorm) [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[ARG]], 0x3810000000000000
+; CHECK-NEXT: [[IS_OEQ_SMALLEST_NORMAL:%.*]] = fcmp oeq float [[ARG]], f0x00800000
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_OEQ_SMALLEST_NORMAL]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2430,7 +2430,7 @@ define float @assume_oeq_smallest_normal_known_pos(float nofpclass(ninf nsub nno
define float @assume_ole_pinf(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_ole_pinf(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[FCMP:%.*]] = fcmp ole float [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[FCMP:%.*]] = fcmp ole float [[ARG]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[FCMP]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2442,7 +2442,7 @@ define float @assume_ole_pinf(float noundef %arg) {
define float @assume_ole_ninf(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_ole_ninf(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[FCMP:%.*]] = fcmp ole float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[FCMP:%.*]] = fcmp ole float [[ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[FCMP]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2454,7 +2454,7 @@ define float @assume_ole_ninf(float noundef %arg) {
define float @assume_ugt_pinf(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_ugt_pinf(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[FCMP:%.*]] = fcmp ugt float [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[FCMP:%.*]] = fcmp ugt float [[ARG]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[FCMP]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2466,7 +2466,7 @@ define float @assume_ugt_pinf(float noundef %arg) {
define float @assume_ugt_ninf(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_ugt_ninf(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[FCMP:%.*]] = fcmp ugt float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[FCMP:%.*]] = fcmp ugt float [[ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[FCMP]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2479,7 +2479,7 @@ define float @assume_fabs_ole_pinf(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_fabs_ole_pinf(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[FCMP:%.*]] = fcmp ole float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[FCMP:%.*]] = fcmp ole float [[FABS]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[FCMP]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
@@ -2505,7 +2505,7 @@ define float @assume_fabs_ugt_pinf(float noundef %arg) {
; CHECK-LABEL: define noundef float @assume_fabs_ugt_pinf(
; CHECK-SAME: float noundef returned [[ARG:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float noundef [[ARG]]) #[[ATTR4]]
-; CHECK-NEXT: [[FCMP:%.*]] = fcmp ugt float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[FCMP:%.*]] = fcmp ugt float [[FABS]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[FCMP]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[ARG]]
;
diff --git a/llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll b/llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll
index 6b09ba7223cae..24495293f6c09 100644
--- a/llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll
@@ -197,7 +197,7 @@ define float @ret_fmul_square_nnan_nzero(float noundef nofpclass(nan zero) %arg)
define float @ret_fmul_ieee_inf(float %arg) {
; CHECK-LABEL: define nofpclass(zero sub norm) float @ret_fmul_ieee_inf
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR4:[0-9]+]] {
-; CHECK-NEXT: [[FMUL:%.*]] = fmul float [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[FMUL:%.*]] = fmul float [[ARG]], +inf
; CHECK-NEXT: ret float [[FMUL]]
;
%fmul = fmul float %arg, 0x7FF0000000000000
diff --git a/llvm/test/Transforms/Attributor/nofpclass-select.ll b/llvm/test/Transforms/Attributor/nofpclass-select.ll
index ce8620ca24cef..59a006fd8431b 100644
--- a/llvm/test/Transforms/Attributor/nofpclass-select.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass-select.ll
@@ -92,7 +92,7 @@ define float @ret_select_clamp_onlynans(float %arg) {
; CHECK-LABEL: define float @ret_select_clamp_onlynans
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[ARG]], 0.000000e+00
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[NOT_NAN]], float 0x7FF8000000000000, float [[ARG]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[NOT_NAN]], float +qnan, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%not.nan = fcmp ord float %arg, 0.0
@@ -104,7 +104,7 @@ define float @clamp_nonfinite_to_normal_olt(float %arg) {
; CHECK-LABEL: define float @clamp_nonfinite_to_normal_olt
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp olt float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp olt float [[FABS]], +inf
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_FINITE]], float [[ARG]], float 1.024000e+03
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -118,7 +118,7 @@ define float @clamp_eq_inf_to_pnormal(float %arg) {
; CHECK-LABEL: define float @clamp_eq_inf_to_pnormal
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], +inf
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_INF]], float 1.024000e+03, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -131,7 +131,7 @@ define float @clamp_eq_inf_to_pnormal(float %arg) {
define float @clamp_eq_pinf_to_pnormal(float %arg) {
; CHECK-LABEL: define float @clamp_eq_pinf_to_pnormal
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[ARG]], +inf
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_INF]], float 1.024000e+03, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -143,7 +143,7 @@ define float @clamp_eq_pinf_to_pnormal(float %arg) {
define float @clamp_eq_ninf_to_negnormal(float %arg) {
; CHECK-LABEL: define float @clamp_eq_ninf_to_negnormal
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[ARG]], -inf
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_INF]], float -1.024000e+03, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -156,8 +156,8 @@ define float @clamp_eq_inf_to_nan(float %arg) {
; CHECK-LABEL: define float @clamp_eq_inf_to_nan
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_INF]], float 0x7FF8000000000000, float [[ARG]]
+; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], +inf
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_INF]], float +qnan, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -182,7 +182,7 @@ define float @isfinite_select_fabs_val_0(float %arg) {
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @isfinite_select_fabs_val_0
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call nofpclass(ninf nzero nsub nnorm) float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp olt float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp olt float [[FABS]], +inf
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_FINITE]], float [[FABS]], float 1.024000e+03
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -196,7 +196,7 @@ define float @isfinite_select_fabs_val_1(float %arg) {
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @isfinite_select_fabs_val_1
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call nofpclass(ninf nzero nsub nnorm) float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[NOT_IS_FINITE:%.*]] = fcmp uge float [[FABS]], 0x3810000000000000
+; CHECK-NEXT: [[NOT_IS_FINITE:%.*]] = fcmp uge float [[FABS]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[NOT_IS_FINITE]], float 1.024000e+03, float [[FABS]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -210,7 +210,7 @@ define float @clamp_denormal_to_poszero(float %arg) {
; CHECK-LABEL: define float @clamp_denormal_to_poszero
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_DENORM_OR_ZERO]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -224,7 +224,7 @@ define float @clamp_denormal_to_negzero(float %arg) {
; CHECK-LABEL: define float @clamp_denormal_to_negzero
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_DENORM_OR_ZERO]], float -0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -238,7 +238,7 @@ define float @clamp_denormal_to_zero_copysign(float %arg) {
; CHECK-LABEL: define float @clamp_denormal_to_zero_copysign
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], f0x00800000
; CHECK-NEXT: [[ZERO:%.*]] = call float @llvm.copysign.f32(float noundef 0.000000e+00, float [[ARG]]) #[[ATTR2]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_DENORM_OR_ZERO]], float [[ZERO]], float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -254,7 +254,7 @@ define float @clamp_only_denormal_or_zero(float %arg) {
; CHECK-LABEL: define float @clamp_only_denormal_or_zero
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], f0x00800000
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_DENORM_OR_ZERO]], float [[ARG]], float 0.000000e+00
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -268,7 +268,7 @@ define float @clamp_inf_to_fabs(float %arg) {
; CHECK-LABEL: define float @clamp_inf_to_fabs
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], +inf
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_INF]], float [[FABS]], float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -282,7 +282,7 @@ define float @not_clamp_inf_to_fabs(float %arg) {
; CHECK-LABEL: define float @not_clamp_inf_to_fabs
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call nofpclass(ninf nzero nsub nnorm) float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], +inf
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_INF]], float [[ARG]], float [[FABS]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -296,7 +296,7 @@ define float @clamp_zero_to_inf(float %arg) {
; CHECK-LABEL: define float @clamp_zero_to_inf
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[IS_ZERO:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ZERO]], float 0x7FF0000000000000, float [[ARG]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ZERO]], float +inf, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%is.zero = fcmp oeq float %arg, 0.0
@@ -308,7 +308,7 @@ define float @clamp_zero_to_only_inf(float %arg) {
; CHECK-LABEL: define float @clamp_zero_to_only_inf
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[IS_ZERO:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ZERO]], float [[ARG]], float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_ZERO]], float [[ARG]], float +inf
; CHECK-NEXT: ret float [[SELECT]]
;
%is.zero = fcmp oeq float %arg, 0.0
@@ -320,7 +320,7 @@ define float @clamp_is_class_subnormal_or_inf_to_nan(float %arg) {
; CHECK-LABEL: define float @clamp_is_class_subnormal_or_inf_to_nan
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[IS_SUBNORMAL_OR_INF:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 noundef 660) #[[ATTR2]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_SUBNORMAL_OR_INF]], float 0x7FF8000000000000, float [[ARG]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_SUBNORMAL_OR_INF]], float +qnan, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
%is.subnormal.or.inf = call i1 @llvm.is.fpclass.f32(float %arg, i32 660)
@@ -332,7 +332,7 @@ define float @clamp_is_class_subnormal_or_inf_to_nan_swap(float %arg) {
; CHECK-LABEL: define float @clamp_is_class_subnormal_or_inf_to_nan_swap
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[NOT_IS_SUBNORMAL_OR_INF:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 noundef 363) #[[ATTR2]]
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[NOT_IS_SUBNORMAL_OR_INF]], float [[ARG]], float 0x7FF8000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[NOT_IS_SUBNORMAL_OR_INF]], float [[ARG]], float +qnan
; CHECK-NEXT: ret float [[SELECT]]
;
%not.is.subnormal.or.inf = call i1 @llvm.is.fpclass.f32(float %arg, i32 363)
@@ -392,7 +392,7 @@ define float @clamp_is_denorm_or_zero_to_fneg(float %arg) {
; CHECK-LABEL: define float @clamp_is_denorm_or_zero_to_fneg
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], f0x00800000
; CHECK-NEXT: [[NEG_ARG:%.*]] = fneg float [[ARG]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_DENORM_OR_ZERO]], float [[NEG_ARG]], float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -408,7 +408,7 @@ define float @select_is_denorm_or_zero_to_fneg_or_fabs(float %arg) {
; CHECK-LABEL: define float @select_is_denorm_or_zero_to_fneg_or_fabs
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call nofpclass(ninf nzero nsub nnorm) float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], f0x00800000
; CHECK-NEXT: [[NEG_ARG:%.*]] = fneg float [[ARG]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_DENORM_OR_ZERO]], float [[NEG_ARG]], float [[FABS]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -424,7 +424,7 @@ define float @select_is_denorm_or_zero_to_fabs_or_fneg(float %arg) {
; CHECK-LABEL: define float @select_is_denorm_or_zero_to_fabs_or_fneg
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG]]) #[[ATTR2]]
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS]], f0x00800000
; CHECK-NEXT: [[NEG_ARG:%.*]] = fneg float [[ARG]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_DENORM_OR_ZERO]], float [[FABS]], float [[NEG_ARG]]
; CHECK-NEXT: ret float [[SELECT]]
diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll
index df1f4d11479ec..788558638a5d2 100644
--- a/llvm/test/Transforms/Attributor/nofpclass.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass.ll
@@ -72,7 +72,7 @@ define float @returned_freeze_poison() {
define double @returned_snan() {
; CHECK-LABEL: define noundef nofpclass(qnan inf zero sub norm) double @returned_snan() {
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: ret double 0x7FF0000000000001
+; CHECK-NEXT: ret double +snan(0x1)
;
call void @unknown()
ret double 0x7FF0000000000001
@@ -81,7 +81,7 @@ define double @returned_snan() {
define double @returned_qnan() {
; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) double @returned_qnan() {
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
call void @unknown()
ret double 0x7FF8000000000000
@@ -138,7 +138,7 @@ define <3 x double> @returned_poison_constant_vector_elt() {
define <2 x double> @returned_qnan_zero_vector() {
; CHECK-LABEL: define noundef nofpclass(snan inf nzero sub norm) <2 x double> @returned_qnan_zero_vector() {
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double 0.000000e+00>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double 0.000000e+00>
;
call void @unknown()
ret <2 x double> <double 0x7FF8000000000000, double 0.0>
@@ -517,7 +517,7 @@ define half @fcmp_assume_issubnormal_callsite_arg_return(half %arg) {
; CHECK-SAME: (half returned nofpclass(nan inf norm) [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[FABS:%.*]] = call nofpclass(ninf nzero nsub nnorm) half @llvm.fabs.f16(half nofpclass(nan inf norm) [[ARG]]) #[[ATTR24:[0-9]+]]
-; CHECK-NEXT: [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
+; CHECK-NEXT: [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 6.103520e-05
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_SUBNORMAL]]) #[[ATTR22]]
; CHECK-NEXT: call void @extern.use.f16(half nofpclass(nan inf norm) [[ARG]])
; CHECK-NEXT: ret half [[ARG]]
@@ -536,7 +536,7 @@ define half @fcmp_assume_not_inf_after_call(half %arg) {
; CHECK-SAME: (half returned [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: call void @extern.use.f16(half [[ARG]])
-; CHECK-NEXT: [[NOT_INF:%.*]] = fcmp oeq half [[ARG]], 0xH7C00
+; CHECK-NEXT: [[NOT_INF:%.*]] = fcmp oeq half [[ARG]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[NOT_INF]])
; CHECK-NEXT: ret half [[ARG]]
;
@@ -553,9 +553,9 @@ define half @fcmp_assume2_callsite_arg_return(half %arg) {
; CHECK-SAME: (half returned nofpclass(nan pinf zero sub) [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[FABS:%.*]] = call nofpclass(nan ninf nzero nsub nnorm) half @llvm.fabs.f16(half nofpclass(nan pinf zero sub) [[ARG]]) #[[ATTR24]]
-; CHECK-NEXT: [[NOT_SUBNORMAL_OR_ZERO:%.*]] = fcmp oge half [[FABS]], 0xH0400
+; CHECK-NEXT: [[NOT_SUBNORMAL_OR_ZERO:%.*]] = fcmp oge half [[FABS]], 6.103520e-05
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[NOT_SUBNORMAL_OR_ZERO]]) #[[ATTR22]]
-; CHECK-NEXT: [[NOT_INF:%.*]] = fcmp one half [[ARG]], 0xH7C00
+; CHECK-NEXT: [[NOT_INF:%.*]] = fcmp one half [[ARG]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[NOT_INF]]) #[[ATTR22]]
; CHECK-NEXT: call void @extern.use.f16(half nofpclass(nan pinf zero sub) [[ARG]])
; CHECK-NEXT: ret half [[ARG]]
@@ -595,9 +595,9 @@ define half @assume_fcmp_fabs_with_other_fabs_assume(half %arg) {
; CHECK-SAME: (half returned nofpclass(nan inf zero norm) [[ARG:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[FABS:%.*]] = call nofpclass(nan inf zero nsub norm) half @llvm.fabs.f16(half nofpclass(nan inf zero norm) [[ARG]]) #[[ATTR24]]
-; CHECK-NEXT: [[UNRELATED_FABS:%.*]] = fcmp one half [[FABS]], 0xH0000
+; CHECK-NEXT: [[UNRELATED_FABS:%.*]] = fcmp one half [[FABS]], 0.000000e+00
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UNRELATED_FABS]]) #[[ATTR22]]
-; CHECK-NEXT: [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
+; CHECK-NEXT: [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 6.103520e-05
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_SUBNORMAL]]) #[[ATTR22]]
; CHECK-NEXT: call void @extern.use.f16(half nofpclass(nan inf zero norm) [[ARG]])
; CHECK-NEXT: call void @extern.use.f16(half nofpclass(nan inf zero nsub norm) [[FABS]])
@@ -623,7 +623,7 @@ define half @assume_fcmp_fabs_with_other_fabs_assume_fallback(half %arg) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[FABS:%.*]] = call nofpclass(nan inf nzero sub norm) half @llvm.fabs.f16(half nofpclass(nan inf sub norm) [[ARG]]) #[[ATTR24]]
; CHECK-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR22]]
-; CHECK-NEXT: [[UNRELATED_FABS:%.*]] = fcmp oeq half [[FABS]], 0xH0000
+; CHECK-NEXT: [[UNRELATED_FABS:%.*]] = fcmp oeq half [[FABS]], 0.000000e+00
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[UNRELATED_FABS]]) #[[ATTR22]]
; CHECK-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR22]]
; CHECK-NEXT: call void @extern.use.f16(half nofpclass(nan inf sub norm) [[ARG]])
@@ -1528,7 +1528,7 @@ define <4 x float> @insertelement_constant_chain() {
; CHECK-NEXT: [[INS_0:%.*]] = insertelement <4 x float> poison, float 1.000000e+00, i32 0
; CHECK-NEXT: [[INS_1:%.*]] = insertelement <4 x float> [[INS_0]], float 0.000000e+00, i32 1
; CHECK-NEXT: [[INS_2:%.*]] = insertelement <4 x float> [[INS_1]], float -9.000000e+00, i32 2
-; CHECK-NEXT: [[INS_3:%.*]] = insertelement <4 x float> [[INS_2]], float 0x7FF0000000000000, i32 3
+; CHECK-NEXT: [[INS_3:%.*]] = insertelement <4 x float> [[INS_2]], float +inf, i32 3
; CHECK-NEXT: ret <4 x float> [[INS_3]]
;
%ins.0 = insertelement <4 x float> poison, float 1.0, i32 0
@@ -1564,7 +1564,7 @@ define <vscale x 4 x float> @insertelement_scalable_constant_chain() {
; CHECK-NEXT: [[INS_0:%.*]] = insertelement <vscale x 4 x float> poison, float 1.000000e+00, i32 0
; CHECK-NEXT: [[INS_1:%.*]] = insertelement <vscale x 4 x float> [[INS_0]], float 0.000000e+00, i32 1
; CHECK-NEXT: [[INS_2:%.*]] = insertelement <vscale x 4 x float> [[INS_1]], float -9.000000e+00, i32 2
-; CHECK-NEXT: [[INS_3:%.*]] = insertelement <vscale x 4 x float> [[INS_2]], float 0x7FF0000000000000, i32 3
+; CHECK-NEXT: [[INS_3:%.*]] = insertelement <vscale x 4 x float> [[INS_2]], float +inf, i32 3
; CHECK-NEXT: ret <vscale x 4 x float> [[INS_3]]
;
%ins.0 = insertelement <vscale x 4 x float> poison, float 1.0, i32 0
@@ -1628,7 +1628,7 @@ define <4 x float> @insertelement_index_oob_chain() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define nofpclass(nan ninf nzero sub norm) <4 x float> @insertelement_index_oob_chain
; CHECK-SAME: () #[[ATTR3]] {
-; CHECK-NEXT: [[INSERT:%.*]] = insertelement <4 x float> zeroinitializer, float 0x7FF0000000000000, i32 4
+; CHECK-NEXT: [[INSERT:%.*]] = insertelement <4 x float> zeroinitializer, float +inf, i32 4
; CHECK-NEXT: ret <4 x float> [[INSERT]]
;
%insert = insertelement <4 x float> zeroinitializer, float 0x7FF0000000000000, i32 4
@@ -1819,7 +1819,7 @@ define float @shufflevector_constantdatavector_demanded0() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @shufflevector_constantdatavector_demanded0
; CHECK-SAME: () #[[ATTR3]] {
-; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <3 x float> <float 1.000000e+00, float 0x7FF8000000000000, float 0.000000e+00>, <3 x float> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <3 x float> <float 1.000000e+00, float +qnan, float 0.000000e+00>, <3 x float> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x float> [[SHUFFLE]], i32 0
; CHECK-NEXT: ret float [[EXTRACT]]
;
@@ -1832,7 +1832,7 @@ define float @shufflevector_constantdatavector_demanded1() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) float @shufflevector_constantdatavector_demanded1
; CHECK-SAME: () #[[ATTR3]] {
-; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <3 x float> <float 1.000000e+00, float 0x7FF8000000000000, float 0.000000e+00>, <3 x float> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <3 x float> <float 1.000000e+00, float +qnan, float 0.000000e+00>, <3 x float> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x float> [[SHUFFLE]], i32 1
; CHECK-NEXT: ret float [[EXTRACT]]
;
@@ -3903,7 +3903,7 @@ define [2 x float] @constant_data_array_1() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) [2 x float] @constant_data_array_1
; CHECK-SAME: () #[[ATTR3]] {
-; CHECK-NEXT: ret [2 x float] [float 0x7FF8000000000000, float 0x7FF8000000000000]
+; CHECK-NEXT: ret [2 x float] [float +qnan, float +qnan]
;
ret [2 x float] [float 0x7FF8000000000000, float 0x7FF8000000000000]
}
@@ -3921,7 +3921,7 @@ define { float, float } @constant_data_struct_1() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) { float, float } @constant_data_struct_1
; CHECK-SAME: () #[[ATTR3]] {
-; CHECK-NEXT: ret { float, float } { float 0x7FF8000000000000, float 0x7FF8000000000000 }
+; CHECK-NEXT: ret { float, float } { float +qnan, float +qnan }
;
ret { float, float } { float 0x7FF8000000000000, float 0x7FF8000000000000 }
}
@@ -3930,7 +3930,7 @@ define { float, { float, float } } @constant_data_nested_struct() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define { float, { float, float } } @constant_data_nested_struct
; CHECK-SAME: () #[[ATTR3]] {
-; CHECK-NEXT: ret { float, { float, float } } { float 0x7FF8000000000000, { float, float } { float 0x7FF8000000000000, float 0x7FF8000000000000 } }
+; CHECK-NEXT: ret { float, { float, float } } { float +qnan, { float, float } { float +qnan, float +qnan } }
;
ret { float, { float, float } } { float 0x7FF8000000000000, { float, float } { float 0x7FF8000000000000, float 0x7FF8000000000000 } }
}
@@ -3939,7 +3939,7 @@ define { float, double } @constant_data_struct_heterogeneous() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define { float, double } @constant_data_struct_heterogeneous
; CHECK-SAME: () #[[ATTR3]] {
-; CHECK-NEXT: ret { float, double } { float 0x7FF8000000000000, double 0x7FF8000000000000 }
+; CHECK-NEXT: ret { float, double } { float +qnan, double +qnan }
;
ret { float, double } { float 0x7FF8000000000000, double 0x7FF8000000000000 }
}
@@ -3948,7 +3948,7 @@ define { float, [2 x float] } @constant_data_struct_array() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define { float, [2 x float] } @constant_data_struct_array
; CHECK-SAME: () #[[ATTR3]] {
-; CHECK-NEXT: ret { float, [2 x float] } { float 0x7FF8000000000000, [2 x float] [float 0x7FF8000000000000, float 0x7FF8000000000000] }
+; CHECK-NEXT: ret { float, [2 x float] } { float +qnan, [2 x float] [float +qnan, float +qnan] }
;
ret { float, [2 x float] } { float 0x7FF8000000000000, [2 x float] [float 0x7FF8000000000000, float 0x7FF8000000000000] }
}
diff --git a/llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll b/llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
index 3e07fe42261e9..858d288c64d41 100644
--- a/llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
+++ b/llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
@@ -126,11 +126,11 @@ define void @local_alloca_simplifiable_1(ptr noalias sret(%struct.S) align 4 %ag
; TUNIT-NEXT: [[I3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 2
; TUNIT-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(16) [[I3]], i32 noundef 3) #[[ATTR18]]
; TUNIT-NEXT: [[F12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[AGG_RESULT]], i64 0, i32 3
-; TUNIT-NEXT: store float 0x3FF19999A0000000, ptr [[F12]], align 4, !tbaa [[FLOAT_TBAA7:![0-9]+]]
+; TUNIT-NEXT: store float 1.100000e+00, ptr [[F12]], align 4, !tbaa [[FLOAT_TBAA7:![0-9]+]]
; TUNIT-NEXT: [[F24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[AGG_RESULT]], i64 0, i32 4
-; TUNIT-NEXT: store float 0x40119999A0000000, ptr [[F24]], align 4, !tbaa [[FLOAT_TBAA10:![0-9]+]]
+; TUNIT-NEXT: store float 4.400000e+00, ptr [[F24]], align 4, !tbaa [[FLOAT_TBAA10:![0-9]+]]
; TUNIT-NEXT: [[F37:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[AGG_RESULT]], i64 0, i32 5
-; TUNIT-NEXT: store float 0x40119999A0000000, ptr [[F37]], align 4, !tbaa [[FLOAT_TBAA11:![0-9]+]]
+; TUNIT-NEXT: store float 4.400000e+00, ptr [[F37]], align 4, !tbaa [[FLOAT_TBAA11:![0-9]+]]
; TUNIT-NEXT: store i32 1, ptr [[AGG_RESULT]], align 4, !tbaa [[INT_TBAA12:![0-9]+]]
; TUNIT-NEXT: [[I212:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[AGG_RESULT]], i64 0, i32 1
; TUNIT-NEXT: store i32 4, ptr [[I212]], align 4, !tbaa [[INT_TBAA13:![0-9]+]]
@@ -146,11 +146,11 @@ define void @local_alloca_simplifiable_1(ptr noalias sret(%struct.S) align 4 %ag
; CGSCC-NEXT: [[S:%.*]] = alloca [[STRUCT_S]], align 4
; CGSCC-NEXT: call void @llvm.lifetime.start.p0(ptr noalias nofree noundef nonnull align 4 captures(none) dereferenceable(24) [[S]]) #[[ATTR20:[0-9]+]]
; CGSCC-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 3
-; CGSCC-NEXT: store float 0x3FF19999A0000000, ptr [[F1]], align 4, !tbaa [[FLOAT_TBAA7:![0-9]+]]
+; CGSCC-NEXT: store float 1.100000e+00, ptr [[F1]], align 4, !tbaa [[FLOAT_TBAA7:![0-9]+]]
; CGSCC-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 4
-; CGSCC-NEXT: store float 0x40019999A0000000, ptr [[F2]], align 4, !tbaa [[FLOAT_TBAA10:![0-9]+]]
+; CGSCC-NEXT: store float 2.200000e+00, ptr [[F2]], align 4, !tbaa [[FLOAT_TBAA10:![0-9]+]]
; CGSCC-NEXT: [[F3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 5
-; CGSCC-NEXT: store float 0x400A666660000000, ptr [[F3]], align 4, !tbaa [[FLOAT_TBAA11:![0-9]+]]
+; CGSCC-NEXT: store float 3.300000e+00, ptr [[F3]], align 4, !tbaa [[FLOAT_TBAA11:![0-9]+]]
; CGSCC-NEXT: call void @write_arg(ptr noalias nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(24) [[S]], i32 noundef 1) #[[ATTR21:[0-9]+]]
; CGSCC-NEXT: [[I2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 1
; CGSCC-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(20) [[I2]], i32 noundef 2) #[[ATTR21]]
@@ -694,11 +694,11 @@ define void @static_global_simplifiable_1(ptr noalias sret(%struct.S) align 4 %a
; TUNIT-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(20) getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 1), i32 noundef 2) #[[ATTR18]]
; TUNIT-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(16) getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 2), i32 noundef 3) #[[ATTR18]]
; TUNIT-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[AGG_RESULT]], i64 0, i32 3
-; TUNIT-NEXT: store float 0x3FF19999A0000000, ptr [[F1]], align 4, !tbaa [[FLOAT_TBAA7]]
+; TUNIT-NEXT: store float 1.100000e+00, ptr [[F1]], align 4, !tbaa [[FLOAT_TBAA7]]
; TUNIT-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[AGG_RESULT]], i64 0, i32 4
-; TUNIT-NEXT: store float 0x40119999A0000000, ptr [[F2]], align 4, !tbaa [[FLOAT_TBAA10]]
+; TUNIT-NEXT: store float 4.400000e+00, ptr [[F2]], align 4, !tbaa [[FLOAT_TBAA10]]
; TUNIT-NEXT: [[F3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[AGG_RESULT]], i64 0, i32 5
-; TUNIT-NEXT: store float 0x40119999A0000000, ptr [[F3]], align 4, !tbaa [[FLOAT_TBAA11]]
+; TUNIT-NEXT: store float 4.400000e+00, ptr [[F3]], align 4, !tbaa [[FLOAT_TBAA11]]
; TUNIT-NEXT: store i32 1, ptr [[AGG_RESULT]], align 4, !tbaa [[INT_TBAA12]]
; TUNIT-NEXT: [[I2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[AGG_RESULT]], i64 0, i32 1
; TUNIT-NEXT: store i32 4, ptr [[I2]], align 4, !tbaa [[INT_TBAA13]]
@@ -710,9 +710,9 @@ define void @static_global_simplifiable_1(ptr noalias sret(%struct.S) align 4 %a
; CGSCC-LABEL: define void @static_global_simplifiable_1(
; CGSCC-SAME: ptr noalias nofree noundef nonnull writeonly sret([[STRUCT_S:%.*]]) align 4 captures(none) dereferenceable(24) [[AGG_RESULT:%.*]]) #[[ATTR3]] {
; CGSCC-NEXT: [[ENTRY:.*:]]
-; CGSCC-NEXT: store float 0x3FF19999A0000000, ptr getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 3), align 4, !tbaa [[FLOAT_TBAA7]]
-; CGSCC-NEXT: store float 0x40019999A0000000, ptr getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 4), align 4, !tbaa [[FLOAT_TBAA10]]
-; CGSCC-NEXT: store float 0x400A666660000000, ptr getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 5), align 4, !tbaa [[FLOAT_TBAA11]]
+; CGSCC-NEXT: store float 1.100000e+00, ptr getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 3), align 4, !tbaa [[FLOAT_TBAA7]]
+; CGSCC-NEXT: store float 2.200000e+00, ptr getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 4), align 4, !tbaa [[FLOAT_TBAA10]]
+; CGSCC-NEXT: store float 3.300000e+00, ptr getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 5), align 4, !tbaa [[FLOAT_TBAA11]]
; CGSCC-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(24) @Gs1, i32 noundef 1) #[[ATTR21]]
; CGSCC-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(20) getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 1), i32 noundef 2) #[[ATTR21]]
; CGSCC-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(16) getelementptr inbounds ([[STRUCT_S]], ptr @Gs1, i64 0, i32 2), i32 noundef 3) #[[ATTR21]]
@@ -1119,11 +1119,11 @@ define void @noalias_arg_simplifiable_1(ptr noalias sret(%struct.S) align 4 %agg
; TUNIT-SAME: ptr noalias nofree writeonly sret([[STRUCT_S:%.*]]) align 4 captures(none) dereferenceable_or_null(24) [[AGG_RESULT:%.*]], ptr noalias nofree nonnull byval([[STRUCT_S]]) align 8 captures(none) dereferenceable(24) [[S:%.*]]) #[[ATTR1]] {
; TUNIT-NEXT: [[ENTRY:.*:]]
; TUNIT-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 3
-; TUNIT-NEXT: store float 0x3FF19999A0000000, ptr [[F1]], align 4, !tbaa [[FLOAT_TBAA7]]
+; TUNIT-NEXT: store float 1.100000e+00, ptr [[F1]], align 4, !tbaa [[FLOAT_TBAA7]]
; TUNIT-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 4
-; TUNIT-NEXT: store float 0x40019999A0000000, ptr [[F2]], align 8, !tbaa [[FLOAT_TBAA10]]
+; TUNIT-NEXT: store float 2.200000e+00, ptr [[F2]], align 8, !tbaa [[FLOAT_TBAA10]]
; TUNIT-NEXT: [[F3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 5
-; TUNIT-NEXT: store float 0x400A666660000000, ptr [[F3]], align 4, !tbaa [[FLOAT_TBAA11]]
+; TUNIT-NEXT: store float 3.300000e+00, ptr [[F3]], align 4, !tbaa [[FLOAT_TBAA11]]
; TUNIT-NEXT: call void @write_arg(ptr noalias nofree noundef nonnull writeonly align 8 captures(none) dereferenceable(24) [[S]], i32 noundef 1) #[[ATTR18]]
; TUNIT-NEXT: [[I2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 1
; TUNIT-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(20) [[I2]], i32 noundef 2) #[[ATTR18]]
@@ -1165,11 +1165,11 @@ define void @noalias_arg_simplifiable_1(ptr noalias sret(%struct.S) align 4 %agg
; CGSCC-SAME: ptr noalias nofree noundef nonnull writeonly sret([[STRUCT_S:%.*]]) align 4 captures(none) dereferenceable(24) [[AGG_RESULT:%.*]], ptr noalias nofree noundef nonnull byval([[STRUCT_S]]) align 8 captures(none) dereferenceable(24) [[S:%.*]]) #[[ATTR1]] {
; CGSCC-NEXT: [[ENTRY:.*:]]
; CGSCC-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 3
-; CGSCC-NEXT: store float 0x3FF19999A0000000, ptr [[F1]], align 4, !tbaa [[FLOAT_TBAA7]]
+; CGSCC-NEXT: store float 1.100000e+00, ptr [[F1]], align 4, !tbaa [[FLOAT_TBAA7]]
; CGSCC-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 4
-; CGSCC-NEXT: store float 0x40019999A0000000, ptr [[F2]], align 8, !tbaa [[FLOAT_TBAA10]]
+; CGSCC-NEXT: store float 2.200000e+00, ptr [[F2]], align 8, !tbaa [[FLOAT_TBAA10]]
; CGSCC-NEXT: [[F3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 5
-; CGSCC-NEXT: store float 0x400A666660000000, ptr [[F3]], align 4, !tbaa [[FLOAT_TBAA11]]
+; CGSCC-NEXT: store float 3.300000e+00, ptr [[F3]], align 4, !tbaa [[FLOAT_TBAA11]]
; CGSCC-NEXT: call void @write_arg(ptr noalias nofree noundef nonnull writeonly align 8 captures(none) dereferenceable(24) [[S]], i32 noundef 1) #[[ATTR21]]
; CGSCC-NEXT: [[I2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S]], i64 0, i32 1
; CGSCC-NEXT: call void @write_arg(ptr nofree noundef nonnull writeonly align 4 captures(none) dereferenceable(20) [[I2]], i32 noundef 2) #[[ATTR21]]
diff --git a/llvm/test/Transforms/DCE/calls-errno.ll b/llvm/test/Transforms/DCE/calls-errno.ll
index 6b73c6ede1940..15a3f157ef5ed 100644
--- a/llvm/test/Transforms/DCE/calls-errno.ll
+++ b/llvm/test/Transforms/DCE/calls-errno.ll
@@ -49,9 +49,9 @@ define void @T() {
; CHECK-NEXT: [[LOG1:%.*]] = call double @log(double 0.000000e+00)
; CHECK-NEXT: [[LOG2:%.*]] = call double @log(double -1.000000e+00)
; CHECK-NEXT: [[EXP2:%.*]] = call double @exp(double 1.000000e+03)
-; CHECK-NEXT: [[COS2:%.*]] = call double @cos(double 0x7FF0000000000000)
+; CHECK-NEXT: [[COS2:%.*]] = call double @cos(double +inf)
; CHECK-NEXT: [[COS3:%.*]] = call double @cos(double 0.000000e+00) [[ATTR2:#.*]]
-; CHECK-NEXT: [[FMOD2:%.*]] = call double @fmod(double 0x7FF0000000000000, double 1.000000e+00)
+; CHECK-NEXT: [[FMOD2:%.*]] = call double @fmod(double +inf, double 1.000000e+00)
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/EarlyCSE/atan.ll b/llvm/test/Transforms/EarlyCSE/atan.ll
index 2b7206c0a6aab..66f9e65e60ff9 100644
--- a/llvm/test/Transforms/EarlyCSE/atan.ll
+++ b/llvm/test/Transforms/EarlyCSE/atan.ll
@@ -14,7 +14,7 @@ define float @callatan0() {
; TODO: constant should be folded
define float @callatanInf() {
; CHECK-LABEL: @callatanInf(
-; CHECK-NEXT: [[CALL:%.*]] = call float @atanf(float 0x7FF0000000000000)
+; CHECK-NEXT: [[CALL:%.*]] = call float @atanf(float +inf)
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @atanf(float 0x7FF0000000000000)
@@ -24,7 +24,7 @@ define float @callatanInf() {
; TODO: constant should be folded
define float @callatanNaN() {
; CHECK-LABEL: @callatanNaN(
-; CHECK-NEXT: [[CALL:%.*]] = call float @atanf(float 0x7FF8000000000000)
+; CHECK-NEXT: [[CALL:%.*]] = call float @atanf(float +qnan)
; CHECK-NEXT: ret float [[CALL]]
;
%call = call float @atanf(float 0x7FF8000000000000)
@@ -34,7 +34,7 @@ define float @callatanNaN() {
; POSIX: May fail with Range Error. We choose not to fail.
define float @callatanDenorm() {
; CHECK-LABEL: @callatanDenorm(
-; CHECK-NEXT: ret float 0x37A16C2000000000
+; CHECK-NEXT: ret float 9.999940e-41
;
%call = call float @atanf(float 0x37A16C2000000000)
ret float %call
@@ -43,7 +43,7 @@ define float @callatanDenorm() {
; TODO: long double calls currently not folded
define x86_fp80 @atanl_x86(x86_fp80 %x) {
; CHECK-LABEL: @atanl_x86(
-; CHECK-NEXT: [[CALL:%.*]] = call x86_fp80 @atanl(x86_fp80 noundef 0xK3FFF8CCCCCCCCCCCCCCD)
+; CHECK-NEXT: [[CALL:%.*]] = call x86_fp80 @atanl(x86_fp80 noundef 1.100000e+00)
; CHECK-NEXT: ret x86_fp80 [[CALL]]
;
%call = call x86_fp80 @atanl(x86_fp80 noundef 0xK3FFF8CCCCCCCCCCCCCCD)
@@ -96,7 +96,7 @@ define float @callatan2_n0n0() {
define float @callatan2_x0() {
; CHECK-LABEL: @callatan2_x0(
-; CHECK-NEXT: ret float 0x3FF921FB60000000
+; CHECK-NEXT: ret float f0x3FC90FDB
;
%call = call float @atan2f(float 1.0, float -0.000000e+00)
ret float %call
@@ -112,7 +112,7 @@ define float @callatan2_0x() {
define float @callatan2_xx() {
; CHECK-LABEL: @callatan2_xx(
-; CHECK-NEXT: ret float 0xBFE921FB60000000
+; CHECK-NEXT: ret float f0xBF490FDB
;
%call = call float @atan2f(float -1.0, float 1.0)
ret float %call
@@ -120,7 +120,7 @@ define float @callatan2_xx() {
define float @callatan2_denorm() {
; CHECK-LABEL: @callatan2_denorm(
-; CHECK-NEXT: ret float 0x37A16C2000000000
+; CHECK-NEXT: ret float 9.999940e-41
;
%call = call float @atan2f(float 0x39B4484C00000000, float 1.0e+10)
ret float %call
@@ -136,7 +136,7 @@ define float @callatan2_flush_to_zero() {
define float @callatan2_NaN() {
; CHECK-LABEL: @callatan2_NaN(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%call = call float @atan2f(float 0x7FF8000000000000, float 0x7FF8000000000000)
ret float %call
@@ -144,7 +144,7 @@ define float @callatan2_NaN() {
define float @callatan2_Inf() {
; CHECK-LABEL: @callatan2_Inf(
-; CHECK-NEXT: ret float 0x3FE921FB60000000
+; CHECK-NEXT: ret float f0x3F490FDB
;
%call = call float @atan2f(float 0x7FF0000000000000, float 0x7FF0000000000000)
ret float %call
diff --git a/llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem-inf.ll b/llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem-inf.ll
index a3e3e3d02eb07..89c05317e8c89 100644
--- a/llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem-inf.ll
+++ b/llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem-inf.ll
@@ -8,8 +8,8 @@
; CHECK-LABEL: define float @frem_x_maybe_inf(float %x, float %y)
; CHECK: 2:
; CHECK: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
-; CHECK: [[FCMP:%.*]] = fcmp ult float [[FABS]], 0x7FF0000000000000
-; CHECK-NEXT: %ret = select i1 [[FCMP]], float %{{.*}}, float 0x7FF8000000000000
+; CHECK: [[FCMP:%.*]] = fcmp ult float [[FABS]], +inf
+; CHECK-NEXT: %ret = select i1 [[FCMP]], float %{{.*}}, float +qnan
; CHECK-NEXT: ret float %ret
; CHECK-LABEL: }
define float @frem_x_maybe_inf(float %x, float %y) {
@@ -20,8 +20,8 @@ define float @frem_x_maybe_inf(float %x, float %y) {
; OPT1-LABEL: define float @frem_x_assumed_non_inf(float %x, float %y)
; OPT1: 2:
; OPT1-NOT: call float @llvm.fabs.f32(float %x)
-; OPT1-NOT: fcmp ult float [[FABS]], 0x7FF0000000000000
-; OPT1: %ret = select i1 true, float %{{.*}}, float 0x7FF8000000000000
+; OPT1-NOT: fcmp ult float [[FABS]], +inf
+; OPT1: %ret = select i1 true, float %{{.*}}, float +qnan
; OPT1-NEXT: ret float %ret
; OPT1-LABEL: }
; OPT0-LABEL: define float @frem_x_assumed_non_inf(float %x, float %y)
@@ -42,8 +42,8 @@ define float @frem_x_assumed_non_inf(float %x, float %y) {
; CHECK-LABEL: define float @frem_ninf(float %x, float %y)
; CHECK: 2:
; CHECK-NOT: call float @llvm.fabs.f32(float %x)
-; CHECK-NOT: fcmp ult float [[FABS]], 0x7FF0000000000000
-; CHECK: %ret = select ninf i1 true, float %{{.*}}, float 0x7FF8000000000000
+; CHECK-NOT: fcmp ult float [[FABS]], +inf
+; CHECK: %ret = select ninf i1 true, float %{{.*}}, float +qnan
; CHECK-NEXT: ret float %ret
; CHECK-LABEL: }
define float @frem_ninf(float %x, float %y) {
diff --git a/llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem.ll b/llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem.ll
index a9d237bbf799a..bdfc254687eaa 100644
--- a/llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem.ll
+++ b/llvm/test/Transforms/ExpandIRInsts/AMDGPU/frem.ll
@@ -15,11 +15,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CHECK-NEXT: br i1 [[TMP1]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]
; CHECK: [[BB2:.*]]:
; CHECK-NEXT: [[RET:%.*]] = phi half [ [[TMP25:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP16:%.*]], %[[FREM_ELSE]] ]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq half [[R1]], 0xH0000
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], half 0xH7E00, half [[RET]]
+; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq half [[R1]], 0.000000e+00
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], half +qnan, half [[RET]]
; CHECK-NEXT: [[TMP5:%.*]] = call half @llvm.fabs.f16(half [[R0]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult half [[TMP5]], 0xH7C00
-; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], half [[TMP4]], half 0xH7E00
+; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult half [[TMP5]], +inf
+; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], half [[TMP4]], half +qnan
; CHECK-NEXT: store half [[R2]], ptr addrspace(1) [[OUT]], align 4
; CHECK-NEXT: ret void
; CHECK: [[FREM_COMPUTE]]:
@@ -38,7 +38,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CHECK-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[NB]], 11
; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]
; CHECK: [[FREM_ELSE]]:
-; CHECK-NEXT: [[TMP14:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[R0]])
+; CHECK-NEXT: [[TMP14:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[R0]])
; CHECK-NEXT: [[TMP15:%.*]] = fcmp oeq float [[AX1]], [[AY2]]
; CHECK-NEXT: [[TMP16]] = select i1 [[TMP15]], half [[TMP14]], half [[R0]]
; CHECK-NEXT: br label %[[BB2]]
@@ -140,10 +140,10 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CHECK: [[BB2:.*]]:
; CHECK-NEXT: [[RET:%.*]] = phi float [ [[TMP24:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP16:%.*]], %[[FREM_ELSE]] ]
; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq float [[R1]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], float 0x7FF8000000000000, float [[RET]]
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], float +qnan, float [[RET]]
; CHECK-NEXT: [[TMP5:%.*]] = call float @llvm.fabs.f32(float [[R0]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult float [[TMP5]], 0x7FF0000000000000
-; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], float [[TMP4]], float 0x7FF8000000000000
+; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult float [[TMP5]], +inf
+; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], float [[TMP4]], float +qnan
; CHECK-NEXT: store float [[R2]], ptr addrspace(1) [[OUT]], align 4
; CHECK-NEXT: ret void
; CHECK: [[FREM_COMPUTE]]:
@@ -262,10 +262,10 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CHECK: [[BB2:.*]]:
; CHECK-NEXT: [[RET:%.*]] = phi double [ [[TMP24:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP16:%.*]], %[[FREM_ELSE]] ]
; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq double [[R1]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], double 0x7FF8000000000000, double [[RET]]
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], double +qnan, double [[RET]]
; CHECK-NEXT: [[TMP5:%.*]] = call double @llvm.fabs.f64(double [[R0]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult double [[TMP5]], 0x7FF0000000000000
-; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], double [[TMP4]], double 0x7FF8000000000000
+; CHECK-NEXT: [[TMP6:%.*]] = fcmp ult double [[TMP5]], +inf
+; CHECK-NEXT: [[R2:%.*]] = select i1 [[TMP6]], double [[TMP4]], double +qnan
; CHECK-NEXT: store double [[R2]], ptr addrspace(1) [[OUT]], align 8
; CHECK-NEXT: ret void
; CHECK: [[FREM_COMPUTE]]:
@@ -383,11 +383,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: br i1 [[TMP3]], label %[[FREM_COMPUTE19:.*]], label %[[FREM_ELSE20:.*]]
; CHECK: [[BB4:.*]]:
; CHECK-NEXT: [[RET:%.*]] = phi half [ [[TMP58:%.*]], %[[FREM_LOOP_EXIT28:.*]] ], [ [[TMP57:%.*]], %[[FREM_ELSE20]] ]
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq half [[TMP2]], 0xH0000
-; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], half 0xH7E00, half [[RET]]
+; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq half [[TMP2]], 0.000000e+00
+; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], half +qnan, half [[RET]]
; CHECK-NEXT: [[TMP7:%.*]] = call half @llvm.fabs.f16(half [[TMP1]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult half [[TMP7]], 0xH7C00
-; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], half [[TMP6]], half 0xH7E00
+; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult half [[TMP7]], +inf
+; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], half [[TMP6]], half +qnan
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x half> poison, half [[TMP9]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x half> [[R0]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x half> [[R1]], i64 1
@@ -399,11 +399,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]
; CHECK: [[BB14:.*]]:
; CHECK-NEXT: [[RET18:%.*]] = phi half [ [[TMP46:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP38:%.*]], %[[FREM_ELSE]] ]
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq half [[TMP12]], 0xH0000
-; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], half 0xH7E00, half [[RET18]]
+; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq half [[TMP12]], 0.000000e+00
+; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], half +qnan, half [[RET18]]
; CHECK-NEXT: [[TMP17:%.*]] = call half @llvm.fabs.f16(half [[TMP11]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult half [[TMP17]], 0xH7C00
-; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], half [[TMP16]], half 0xH7E00
+; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult half [[TMP17]], +inf
+; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], half [[TMP16]], half +qnan
; CHECK-NEXT: [[R2:%.*]] = insertelement <2 x half> [[TMP10]], half [[TMP19]], i64 1
; CHECK-NEXT: store <2 x half> [[R2]], ptr addrspace(1) [[OUT]], align 8
; CHECK-NEXT: ret void
@@ -423,7 +423,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i32 [[NB]], 11
; CHECK-NEXT: br i1 [[TMP26]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]
; CHECK: [[FREM_ELSE]]:
-; CHECK-NEXT: [[TMP28:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP11]])
+; CHECK-NEXT: [[TMP28:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[TMP11]])
; CHECK-NEXT: [[TMP29:%.*]] = fcmp oeq float [[AX16]], [[AY17]]
; CHECK-NEXT: [[TMP38]] = select i1 [[TMP29]], half [[TMP28]], half [[TMP11]]
; CHECK-NEXT: br label %[[BB14]]
@@ -474,7 +474,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: [[TMP45:%.*]] = icmp sgt i32 [[NB25]], 11
; CHECK-NEXT: br i1 [[TMP45]], label %[[FREM_LOOP_BODY27:.*]], label %[[FREM_LOOP_EXIT28]]
; CHECK: [[FREM_ELSE20]]:
-; CHECK-NEXT: [[TMP47:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP1]])
+; CHECK-NEXT: [[TMP47:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[TMP1]])
; CHECK-NEXT: [[TMP48:%.*]] = fcmp oeq float [[AX1]], [[AY2]]
; CHECK-NEXT: [[TMP57]] = select i1 [[TMP48]], half [[TMP47]], half [[TMP1]]
; CHECK-NEXT: br label %[[BB4]]
@@ -535,11 +535,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: br i1 [[TMP3]], label %[[FREM_COMPUTE85:.*]], label %[[FREM_ELSE86:.*]]
; CHECK: [[BB4:.*]]:
; CHECK-NEXT: [[RET:%.*]] = phi half [ [[TMP116:%.*]], %[[FREM_LOOP_EXIT94:.*]] ], [ [[TMP115:%.*]], %[[FREM_ELSE86]] ]
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq half [[TMP2]], 0xH0000
-; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], half 0xH7E00, half [[RET]]
+; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq half [[TMP2]], 0.000000e+00
+; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], half +qnan, half [[RET]]
; CHECK-NEXT: [[TMP7:%.*]] = call half @llvm.fabs.f16(half [[TMP1]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult half [[TMP7]], 0xH7C00
-; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], half [[TMP6]], half 0xH7E00
+; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult half [[TMP7]], +inf
+; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], half [[TMP6]], half +qnan
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x half> poison, half [[TMP9]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x half> [[R0]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x half> [[R1]], i64 1
@@ -551,11 +551,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: br i1 [[TMP13]], label %[[FREM_COMPUTE52:.*]], label %[[FREM_ELSE53:.*]]
; CHECK: [[BB14:.*]]:
; CHECK-NEXT: [[RET18:%.*]] = phi half [ [[TMP104:%.*]], %[[FREM_LOOP_EXIT61:.*]] ], [ [[TMP96:%.*]], %[[FREM_ELSE53]] ]
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq half [[TMP12]], 0xH0000
-; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], half 0xH7E00, half [[RET18]]
+; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq half [[TMP12]], 0.000000e+00
+; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], half +qnan, half [[RET18]]
; CHECK-NEXT: [[TMP17:%.*]] = call half @llvm.fabs.f16(half [[TMP11]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult half [[TMP17]], 0xH7C00
-; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], half [[TMP16]], half 0xH7E00
+; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult half [[TMP17]], +inf
+; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], half [[TMP16]], half +qnan
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x half> [[TMP10]], half [[TMP19]], i64 1
; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x half> [[R0]], i64 2
; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x half> [[R1]], i64 2
@@ -567,11 +567,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: br i1 [[TMP23]], label %[[FREM_COMPUTE19:.*]], label %[[FREM_ELSE20:.*]]
; CHECK: [[BB24:.*]]:
; CHECK-NEXT: [[RET51:%.*]] = phi half [ [[TMP85:%.*]], %[[FREM_LOOP_EXIT28:.*]] ], [ [[TMP77:%.*]], %[[FREM_ELSE20]] ]
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp ueq half [[TMP22]], 0xH0000
-; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP25]], half 0xH7E00, half [[RET51]]
+; CHECK-NEXT: [[TMP25:%.*]] = fcmp ueq half [[TMP22]], 0.000000e+00
+; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP25]], half +qnan, half [[RET51]]
; CHECK-NEXT: [[TMP27:%.*]] = call half @llvm.fabs.f16(half [[TMP21]])
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp ult half [[TMP27]], 0xH7C00
-; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], half [[TMP26]], half 0xH7E00
+; CHECK-NEXT: [[TMP28:%.*]] = fcmp ult half [[TMP27]], +inf
+; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], half [[TMP26]], half +qnan
; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x half> [[TMP20]], half [[TMP29]], i64 2
; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x half> [[R0]], i64 3
; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x half> [[R1]], i64 3
@@ -583,11 +583,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: br i1 [[TMP33]], label %[[FREM_COMPUTE:.*]], label %[[FREM_ELSE:.*]]
; CHECK: [[BB34:.*]]:
; CHECK-NEXT: [[RET84:%.*]] = phi half [ [[TMP66:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP58:%.*]], %[[FREM_ELSE]] ]
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp ueq half [[TMP32]], 0xH0000
-; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], half 0xH7E00, half [[RET84]]
+; CHECK-NEXT: [[TMP35:%.*]] = fcmp ueq half [[TMP32]], 0.000000e+00
+; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], half +qnan, half [[RET84]]
; CHECK-NEXT: [[TMP37:%.*]] = call half @llvm.fabs.f16(half [[TMP31]])
-; CHECK-NEXT: [[TMP38:%.*]] = fcmp ult half [[TMP37]], 0xH7C00
-; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], half [[TMP36]], half 0xH7E00
+; CHECK-NEXT: [[TMP38:%.*]] = fcmp ult half [[TMP37]], +inf
+; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], half [[TMP36]], half +qnan
; CHECK-NEXT: [[R2:%.*]] = insertelement <4 x half> [[TMP30]], half [[TMP39]], i64 3
; CHECK-NEXT: store <4 x half> [[R2]], ptr addrspace(1) [[OUT]], align 16
; CHECK-NEXT: ret void
@@ -607,7 +607,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: [[TMP46:%.*]] = icmp sgt i32 [[NB]], 11
; CHECK-NEXT: br i1 [[TMP46]], label %[[FREM_LOOP_BODY:.*]], label %[[FREM_LOOP_EXIT]]
; CHECK: [[FREM_ELSE]]:
-; CHECK-NEXT: [[TMP48:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP31]])
+; CHECK-NEXT: [[TMP48:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[TMP31]])
; CHECK-NEXT: [[TMP49:%.*]] = fcmp oeq float [[AX82]], [[AY83]]
; CHECK-NEXT: [[TMP58]] = select i1 [[TMP49]], half [[TMP48]], half [[TMP31]]
; CHECK-NEXT: br label %[[BB34]]
@@ -658,7 +658,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: [[TMP65:%.*]] = icmp sgt i32 [[NB25]], 11
; CHECK-NEXT: br i1 [[TMP65]], label %[[FREM_LOOP_BODY27:.*]], label %[[FREM_LOOP_EXIT28]]
; CHECK: [[FREM_ELSE20]]:
-; CHECK-NEXT: [[TMP67:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP21]])
+; CHECK-NEXT: [[TMP67:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[TMP21]])
; CHECK-NEXT: [[TMP68:%.*]] = fcmp oeq float [[AX49]], [[AY50]]
; CHECK-NEXT: [[TMP77]] = select i1 [[TMP68]], half [[TMP67]], half [[TMP21]]
; CHECK-NEXT: br label %[[BB24]]
@@ -709,7 +709,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: [[TMP84:%.*]] = icmp sgt i32 [[NB58]], 11
; CHECK-NEXT: br i1 [[TMP84]], label %[[FREM_LOOP_BODY60:.*]], label %[[FREM_LOOP_EXIT61]]
; CHECK: [[FREM_ELSE53]]:
-; CHECK-NEXT: [[TMP86:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP11]])
+; CHECK-NEXT: [[TMP86:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[TMP11]])
; CHECK-NEXT: [[TMP87:%.*]] = fcmp oeq float [[AX16]], [[AY17]]
; CHECK-NEXT: [[TMP96]] = select i1 [[TMP87]], half [[TMP86]], half [[TMP11]]
; CHECK-NEXT: br label %[[BB14]]
@@ -760,7 +760,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK-NEXT: [[TMP103:%.*]] = icmp sgt i32 [[NB91]], 11
; CHECK-NEXT: br i1 [[TMP103]], label %[[FREM_LOOP_BODY93:.*]], label %[[FREM_LOOP_EXIT94]]
; CHECK: [[FREM_ELSE86]]:
-; CHECK-NEXT: [[TMP105:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[TMP1]])
+; CHECK-NEXT: [[TMP105:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[TMP1]])
; CHECK-NEXT: [[TMP106:%.*]] = fcmp oeq float [[AX1]], [[AY2]]
; CHECK-NEXT: [[TMP115]] = select i1 [[TMP106]], half [[TMP105]], half [[TMP1]]
; CHECK-NEXT: br label %[[BB4]]
@@ -820,10 +820,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK: [[BB4:.*]]:
; CHECK-NEXT: [[RET:%.*]] = phi float [ [[TMP56:%.*]], %[[FREM_LOOP_EXIT24:.*]] ], [ [[TMP55:%.*]], %[[FREM_ELSE16]] ]
; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float 0x7FF8000000000000, float [[RET]]
+; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float +qnan, float [[RET]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.fabs.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult float [[TMP7]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP6]], float 0x7FF8000000000000
+; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult float [[TMP7]], +inf
+; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP6]], float +qnan
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x float> poison, float [[TMP9]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x float> [[R0]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x float> [[R1]], i64 1
@@ -834,10 +834,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK: [[BB14:.*]]:
; CHECK-NEXT: [[RET14:%.*]] = phi float [ [[TMP45:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP37:%.*]], %[[FREM_ELSE]] ]
; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq float [[TMP12]], 0.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], float 0x7FF8000000000000, float [[RET14]]
+; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], float +qnan, float [[RET14]]
; CHECK-NEXT: [[TMP17:%.*]] = call float @llvm.fabs.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult float [[TMP17]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], float [[TMP16]], float 0x7FF8000000000000
+; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult float [[TMP17]], +inf
+; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], float [[TMP16]], float +qnan
; CHECK-NEXT: [[R2:%.*]] = insertelement <2 x float> [[TMP10]], float [[TMP19]], i64 1
; CHECK-NEXT: store <2 x float> [[R2]], ptr addrspace(1) [[OUT]], align 8
; CHECK-NEXT: ret void
@@ -966,10 +966,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK: [[BB4:.*]]:
; CHECK-NEXT: [[RET:%.*]] = phi float [ [[TMP112:%.*]], %[[FREM_LOOP_EXIT86:.*]] ], [ [[TMP111:%.*]], %[[FREM_ELSE78]] ]
; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float 0x7FF8000000000000, float [[RET]]
+; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float +qnan, float [[RET]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.fabs.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult float [[TMP7]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP6]], float 0x7FF8000000000000
+; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult float [[TMP7]], +inf
+; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP6]], float +qnan
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[TMP9]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x float> [[R0]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[R1]], i64 1
@@ -980,10 +980,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK: [[BB14:.*]]:
; CHECK-NEXT: [[RET14:%.*]] = phi float [ [[TMP101:%.*]], %[[FREM_LOOP_EXIT55:.*]] ], [ [[TMP93:%.*]], %[[FREM_ELSE47]] ]
; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq float [[TMP12]], 0.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], float 0x7FF8000000000000, float [[RET14]]
+; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], float +qnan, float [[RET14]]
; CHECK-NEXT: [[TMP17:%.*]] = call float @llvm.fabs.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult float [[TMP17]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], float [[TMP16]], float 0x7FF8000000000000
+; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult float [[TMP17]], +inf
+; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], float [[TMP16]], float +qnan
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP19]], i64 1
; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x float> [[R0]], i64 2
; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x float> [[R1]], i64 2
@@ -994,10 +994,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK: [[BB24:.*]]:
; CHECK-NEXT: [[RET45:%.*]] = phi float [ [[TMP83:%.*]], %[[FREM_LOOP_EXIT24:.*]] ], [ [[TMP75:%.*]], %[[FREM_ELSE16]] ]
; CHECK-NEXT: [[TMP25:%.*]] = fcmp ueq float [[TMP22]], 0.000000e+00
-; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP25]], float 0x7FF8000000000000, float [[RET45]]
+; CHECK-NEXT: [[TMP26:%.*]] = select i1 [[TMP25]], float +qnan, float [[RET45]]
; CHECK-NEXT: [[TMP27:%.*]] = call float @llvm.fabs.f32(float [[TMP21]])
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp ult float [[TMP27]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], float [[TMP26]], float 0x7FF8000000000000
+; CHECK-NEXT: [[TMP28:%.*]] = fcmp ult float [[TMP27]], +inf
+; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], float [[TMP26]], float +qnan
; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x float> [[TMP20]], float [[TMP29]], i64 2
; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x float> [[R0]], i64 3
; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x float> [[R1]], i64 3
@@ -1008,10 +1008,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK: [[BB34:.*]]:
; CHECK-NEXT: [[RET76:%.*]] = phi float [ [[TMP65:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP57:%.*]], %[[FREM_ELSE]] ]
; CHECK-NEXT: [[TMP35:%.*]] = fcmp ueq float [[TMP32]], 0.000000e+00
-; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], float 0x7FF8000000000000, float [[RET76]]
+; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], float +qnan, float [[RET76]]
; CHECK-NEXT: [[TMP37:%.*]] = call float @llvm.fabs.f32(float [[TMP31]])
-; CHECK-NEXT: [[TMP38:%.*]] = fcmp ult float [[TMP37]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], float [[TMP36]], float 0x7FF8000000000000
+; CHECK-NEXT: [[TMP38:%.*]] = fcmp ult float [[TMP37]], +inf
+; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], float [[TMP36]], float +qnan
; CHECK-NEXT: [[R2:%.*]] = insertelement <4 x float> [[TMP30]], float [[TMP39]], i64 3
; CHECK-NEXT: store <4 x float> [[R2]], ptr addrspace(1) [[OUT]], align 16
; CHECK-NEXT: ret void
@@ -1240,10 +1240,10 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK: [[BB4:.*]]:
; CHECK-NEXT: [[RET:%.*]] = phi double [ [[TMP56:%.*]], %[[FREM_LOOP_EXIT24:.*]] ], [ [[TMP55:%.*]], %[[FREM_ELSE16]] ]
; CHECK-NEXT: [[TMP5:%.*]] = fcmp ueq double [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double 0x7FF8000000000000, double [[RET]]
+; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], double +qnan, double [[RET]]
; CHECK-NEXT: [[TMP7:%.*]] = call double @llvm.fabs.f64(double [[TMP1]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult double [[TMP7]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], double [[TMP6]], double 0x7FF8000000000000
+; CHECK-NEXT: [[TMP8:%.*]] = fcmp ult double [[TMP7]], +inf
+; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], double [[TMP6]], double +qnan
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> poison, double [[TMP9]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[R0]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x double> [[R1]], i64 1
@@ -1254,10 +1254,10 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CHECK: [[BB14:.*]]:
; CHECK-NEXT: [[RET14:%.*]] = phi double [ [[TMP45:%.*]], %[[FREM_LOOP_EXIT:.*]] ], [ [[TMP37:%.*]], %[[FREM_ELSE]] ]
; CHECK-NEXT: [[TMP15:%.*]] = fcmp ueq double [[TMP12]], 0.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], double 0x7FF8000000000000, double [[RET14]]
+; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], double +qnan, double [[RET14]]
; CHECK-NEXT: [[TMP17:%.*]] = call double @llvm.fabs.f64(double [[TMP11]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult double [[TMP17]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], double [[TMP16]], double 0x7FF8000000000000
+; CHECK-NEXT: [[TMP18:%.*]] = fcmp ult double [[TMP17]], +inf
+; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], double [[TMP16]], double +qnan
; CHECK-NEXT: [[R2:%.*]] = insertelement <2 x double> [[TMP10]], double [[TMP19]], i64 1
; CHECK-NEXT: store <2 x double> [[R2]], ptr addrspace(1) [[OUT]], align 16
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll
index 8077f5af1d8df..79b36fc8826f9 100644
--- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll
+++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll
@@ -70,7 +70,7 @@ define half @uitofp_i32_f16(i32 %x) {
; CHECK-NEXT: [[TMP39:%.*]] = fptrunc float [[TMP38]] to half
; CHECK-NEXT: br label %[[ITOFP_RETURN]]
; CHECK: [[ITOFP_RETURN]]:
-; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ]
+; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0.000000e+00, %[[ITOFP_ENTRY]] ]
; CHECK-NEXT: ret half [[TMP40]]
;
%res = uitofp i32 %x to half
@@ -143,7 +143,7 @@ define half @uitofp_i32_f16_noundef(i32 noundef %x) {
; CHECK-NEXT: [[TMP39:%.*]] = fptrunc float [[TMP38]] to half
; CHECK-NEXT: br label %[[ITOFP_RETURN]]
; CHECK: [[ITOFP_RETURN]]:
-; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ]
+; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0.000000e+00, %[[ITOFP_ENTRY]] ]
; CHECK-NEXT: ret half [[TMP40]]
;
%res = uitofp i32 %x to half
@@ -218,7 +218,7 @@ define half @uitofp_i16_f16(i16 %x) {
; CHECK-NEXT: [[TMP40:%.*]] = fptrunc float [[TMP39]] to half
; CHECK-NEXT: br label %[[ITOFP_RETURN]]
; CHECK: [[ITOFP_RETURN]]:
-; CHECK-NEXT: [[TMP41:%.*]] = phi half [ [[TMP40]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ]
+; CHECK-NEXT: [[TMP41:%.*]] = phi half [ [[TMP40]], %[[ITOFP_IF_END26]] ], [ 0.000000e+00, %[[ITOFP_ENTRY]] ]
; CHECK-NEXT: ret half [[TMP41]]
;
%res = uitofp i16 %x to half
@@ -292,7 +292,7 @@ define half @sitofp_i32_f16(i32 %x) {
; CHECK-NEXT: [[TMP39:%.*]] = fptrunc float [[TMP38]] to half
; CHECK-NEXT: br label %[[ITOFP_RETURN]]
; CHECK: [[ITOFP_RETURN]]:
-; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ]
+; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0.000000e+00, %[[ITOFP_ENTRY]] ]
; CHECK-NEXT: ret half [[TMP40]]
;
%res = sitofp i32 %x to half
@@ -367,7 +367,7 @@ define half @sitofp_i16_f16(i16 %x) {
; CHECK-NEXT: [[TMP39:%.*]] = fptrunc float [[TMP38]] to half
; CHECK-NEXT: br label %[[ITOFP_RETURN]]
; CHECK: [[ITOFP_RETURN]]:
-; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ]
+; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0.000000e+00, %[[ITOFP_ENTRY]] ]
; CHECK-NEXT: ret half [[TMP40]]
;
%res = sitofp i16 %x to half
diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll
index a3677bafb4449..8ba4147ae252f 100644
--- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll
+++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll
@@ -81,7 +81,7 @@ define half @si129tohalf(i129 %a) {
; CHECK-NEXT: [[TMP52:%.*]] = fptrunc float [[TMP51]] to half
; CHECK-NEXT: br label [[ITOFP_RETURN]]
; CHECK: itofp-return:
-; CHECK-NEXT: [[TMP53:%.*]] = phi half [ [[TMP52]], [[ITOFP_IF_END26]] ], [ 0xH0000, [[ITOFP_ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = phi half [ [[TMP52]], [[ITOFP_IF_END26]] ], [ 0.000000e+00, [[ITOFP_ENTRY:%.*]] ]
; CHECK-NEXT: ret half [[TMP53]]
;
%conv = sitofp i129 %a to half
@@ -341,7 +341,7 @@ define x86_fp80 @si129tox86_fp80(i129 %a) {
; CHECK-NEXT: [[TMP50:%.*]] = fptrunc fp128 [[TMP49]] to x86_fp80
; CHECK-NEXT: br label [[ITOFP_RETURN]]
; CHECK: itofp-return:
-; CHECK-NEXT: [[TMP51:%.*]] = phi x86_fp80 [ [[TMP50]], [[ITOFP_IF_END26]] ], [ 0xK00000000000000000000, [[ITOFP_ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP51:%.*]] = phi x86_fp80 [ [[TMP50]], [[ITOFP_IF_END26]] ], [ 0.000000e+00, [[ITOFP_ENTRY:%.*]] ]
; CHECK-NEXT: ret x86_fp80 [[TMP51]]
;
%conv = sitofp i129 %a to x86_fp80
@@ -425,7 +425,7 @@ define fp128 @si129tofp128(i129 %a) {
; CHECK-NEXT: [[TMP49:%.*]] = bitcast i128 [[TMP48]] to fp128
; CHECK-NEXT: br label [[ITOFP_RETURN]]
; CHECK: itofp-return:
-; CHECK-NEXT: [[TMP50:%.*]] = phi fp128 [ [[TMP49]], [[ITOFP_IF_END26]] ], [ 0xL00000000000000000000000000000000, [[ITOFP_ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP50:%.*]] = phi fp128 [ [[TMP49]], [[ITOFP_IF_END26]] ], [ 0.000000e+00, [[ITOFP_ENTRY:%.*]] ]
; CHECK-NEXT: ret fp128 [[TMP50]]
;
%conv = sitofp i129 %a to fp128
diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll
index eed61b7c53989..c2febf7ae98ac 100644
--- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll
+++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll
@@ -81,7 +81,7 @@ define half @ui129tohalf(i129 %a) {
; CHECK-NEXT: [[TMP52:%.*]] = fptrunc float [[TMP51]] to half
; CHECK-NEXT: br label [[ITOFP_RETURN]]
; CHECK: itofp-return:
-; CHECK-NEXT: [[TMP53:%.*]] = phi half [ [[TMP52]], [[ITOFP_IF_END26]] ], [ 0xH0000, [[ITOFP_ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP53:%.*]] = phi half [ [[TMP52]], [[ITOFP_IF_END26]] ], [ 0.000000e+00, [[ITOFP_ENTRY:%.*]] ]
; CHECK-NEXT: ret half [[TMP53]]
;
%conv = uitofp i129 %a to half
@@ -341,7 +341,7 @@ define x86_fp80 @ui129tox86_fp80(i129 %a) {
; CHECK-NEXT: [[TMP50:%.*]] = fptrunc fp128 [[TMP49]] to x86_fp80
; CHECK-NEXT: br label [[ITOFP_RETURN]]
; CHECK: itofp-return:
-; CHECK-NEXT: [[TMP51:%.*]] = phi x86_fp80 [ [[TMP50]], [[ITOFP_IF_END26]] ], [ 0xK00000000000000000000, [[ITOFP_ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP51:%.*]] = phi x86_fp80 [ [[TMP50]], [[ITOFP_IF_END26]] ], [ 0.000000e+00, [[ITOFP_ENTRY:%.*]] ]
; CHECK-NEXT: ret x86_fp80 [[TMP51]]
;
%conv = uitofp i129 %a to x86_fp80
@@ -425,7 +425,7 @@ define fp128 @ui129tofp128(i129 %a) {
; CHECK-NEXT: [[TMP49:%.*]] = bitcast i128 [[TMP48]] to fp128
; CHECK-NEXT: br label [[ITOFP_RETURN]]
; CHECK: itofp-return:
-; CHECK-NEXT: [[TMP50:%.*]] = phi fp128 [ [[TMP49]], [[ITOFP_IF_END26]] ], [ 0xL00000000000000000000000000000000, [[ITOFP_ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP50:%.*]] = phi fp128 [ [[TMP49]], [[ITOFP_IF_END26]] ], [ 0.000000e+00, [[ITOFP_ENTRY:%.*]] ]
; CHECK-NEXT: ret fp128 [[TMP50]]
;
%conv = uitofp i129 %a to fp128
diff --git a/llvm/test/Transforms/Float2Int/float2int-optnone.ll b/llvm/test/Transforms/Float2Int/float2int-optnone.ll
index 64ba838c9c437..d315285af1842 100644
--- a/llvm/test/Transforms/Float2Int/float2int-optnone.ll
+++ b/llvm/test/Transforms/Float2Int/float2int-optnone.ll
@@ -5,7 +5,7 @@
define i16 @simple1(i8 %a) #0 {
; CHECK-LABEL: @simple1
; CHECK: %1 = uitofp i8 %a to float
-; CHECK-NEXT: %2 = fadd float %1, 1.0
+; CHECK-NEXT: %2 = fadd float %1, 1.000000e+00
; CHECK-NEXT: %3 = fptoui float %2 to i16
; CHECK-NEXT: ret i16 %3
%1 = uitofp i8 %a to float
diff --git a/llvm/test/Transforms/Float2Int/pr167627.ll b/llvm/test/Transforms/Float2Int/pr167627.ll
index a170c21af7a2a..773072cfa3cb8 100644
--- a/llvm/test/Transforms/Float2Int/pr167627.ll
+++ b/llvm/test/Transforms/Float2Int/pr167627.ll
@@ -7,7 +7,7 @@
define i1 @pr167627() {
; CHECK-LABEL: define i1 @pr167627() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[FADD:%.*]] = fadd float 0xC5AAD8ABE0000000, 0xC57E819700000000
+; CHECK-NEXT: [[FADD:%.*]] = fadd float f0xED56C55F, f0xEBF40CB8
; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[FADD]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
diff --git a/llvm/test/Transforms/FunctionAttrs/nofpclass.ll b/llvm/test/Transforms/FunctionAttrs/nofpclass.ll
index 9ee58df18c598..c8a9dfd56a62a 100644
--- a/llvm/test/Transforms/FunctionAttrs/nofpclass.ll
+++ b/llvm/test/Transforms/FunctionAttrs/nofpclass.ll
@@ -202,7 +202,7 @@ define internal void @infer_arg_from_constants(float %a, <2 x half> %b, float %c
define void @call_infer_arg_from_constants() {
; CHECK-LABEL: define void @call_infer_arg_from_constants(
; CHECK-SAME: ) #[[ATTR2]] {
-; CHECK-NEXT: call void @infer_arg_from_constants(float 0.000000e+00, <2 x half> <half 0xH3C00, half 0xHBC00>, float poison, float 0x7FF8000000000000)
+; CHECK-NEXT: call void @infer_arg_from_constants(float 0.000000e+00, <2 x half> <half 1.000000e+00, half -1.000000e+00>, float poison, float +qnan)
; CHECK-NEXT: ret void
;
call void @infer_arg_from_constants(float 0.0, <2 x half> <half 1.0, half -1.0>, float poison, float 0x7FF8000000000000)
diff --git a/llvm/test/Transforms/FunctionAttrs/noundef.ll b/llvm/test/Transforms/FunctionAttrs/noundef.ll
index 75e5655f2a93e..d02c3eabcf2b8 100644
--- a/llvm/test/Transforms/FunctionAttrs/noundef.ll
+++ b/llvm/test/Transforms/FunctionAttrs/noundef.ll
@@ -226,7 +226,7 @@ define nofpclass(nan) float @maybe_nofpclass(float noundef %x) {
define nofpclass(nan) float @compute_not_nofpclass(float noundef nofpclass(nan) %x) {
; CHECK-LABEL: define nofpclass(nan) float @compute_not_nofpclass(
; CHECK-SAME: float noundef nofpclass(nan) [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[Y:%.*]] = fmul float [[X]], 0x7FF8000000000000
+; CHECK-NEXT: [[Y:%.*]] = fmul float [[X]], +qnan
; CHECK-NEXT: ret float [[Y]]
;
%y = fmul float %x, 0x7FF8000000000000
diff --git a/llvm/test/Transforms/GVN/edge.ll b/llvm/test/Transforms/GVN/edge.ll
index 83c4c336f6474..69d8eab897f58 100644
--- a/llvm/test/Transforms/GVN/edge.ll
+++ b/llvm/test/Transforms/GVN/edge.ll
@@ -230,7 +230,7 @@ define float @fcmp_oeq_denormal(float %x, float %y) {
; CHECK-LABEL: define float @fcmp_oeq_denormal(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[Y]], 0x3800000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[Y]], f0x00400000
; CHECK-NEXT: br i1 [[CMP]], label %[[IF:.*]], label %[[RETURN:.*]]
; CHECK: [[IF]]:
; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[X]], [[Y]]
diff --git a/llvm/test/Transforms/GVN/no-mem-dep-info.ll b/llvm/test/Transforms/GVN/no-mem-dep-info.ll
index 5f67902d791eb..837f85d78e50f 100644
--- a/llvm/test/Transforms/GVN/no-mem-dep-info.ll
+++ b/llvm/test/Transforms/GVN/no-mem-dep-info.ll
@@ -17,9 +17,9 @@ define <8 x float> @foo1(ptr noalias readonly %arr.ptr, ptr noalias readonly %vi
; CHECK-NEXT: [[ALLOCAS:.*:]]
; CHECK-NEXT: [[VIX:%.*]] = load <8 x i32>, ptr [[VIX_PTR]], align 4
; CHECK-NEXT: [[T1_PTR:%.*]] = getelementptr i8, ptr [[ARR_PTR]], i8 4
-; CHECK-NEXT: [[V1:%.*]] = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr [[ARR_PTR]], <8 x i32> [[VIX]], <8 x float> splat (float 0xFFFFFFFFE0000000), i8 1)
+; CHECK-NEXT: [[V1:%.*]] = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr [[ARR_PTR]], <8 x i32> [[VIX]], <8 x float> splat (float -nan(0x3FFFFF)), i8 1)
; CHECK-NEXT: store i8 1, ptr [[T1_PTR]], align 4
-; CHECK-NEXT: [[V2:%.*]] = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr [[ARR_PTR]], <8 x i32> [[VIX]], <8 x float> splat (float 0xFFFFFFFFE0000000), i8 1)
+; CHECK-NEXT: [[V2:%.*]] = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr [[ARR_PTR]], <8 x i32> [[VIX]], <8 x float> splat (float -nan(0x3FFFFF)), i8 1)
; CHECK-NEXT: [[RES:%.*]] = fadd <8 x float> [[V1]], [[V2]]
; CHECK-NEXT: ret <8 x float> [[RES]]
;
diff --git a/llvm/test/Transforms/GVNHoist/hoist-call.ll b/llvm/test/Transforms/GVNHoist/hoist-call.ll
index 01e6029c90b00..930e4162556dd 100644
--- a/llvm/test/Transforms/GVNHoist/hoist-call.ll
+++ b/llvm/test/Transforms/GVNHoist/hoist-call.ll
@@ -8,7 +8,7 @@ define void @fun(float %__b, i1 %arg) minsize {
; CHECK-NEXT: br label [[IF_THEN:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[TMP0:%.*]] = call float @llvm.fabs.f32(float [[__B:%.*]])
-; CHECK-NEXT: [[CMPINF7:%.*]] = fcmp oeq float [[TMP0]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMPINF7:%.*]] = fcmp oeq float [[TMP0]], +inf
; CHECK-NEXT: br i1 %arg, label [[IF_THEN8:%.*]], label [[LOR_LHS_FALSE:%.*]]
; CHECK: lor.lhs.false:
; CHECK-NEXT: unreachable
diff --git a/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll b/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
index a01c032460632..d45785b7818cf 100644
--- a/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
+++ b/llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
@@ -507,7 +507,7 @@ define void @test_fp_to_int_irrealizable_exitval_pow_2_24() {
; CHECK-NEXT: [[IV:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: call void @opaque()
; CHECK-NEXT: [[IV_NEXT]] = fadd float [[IV]], 1.000000e+00
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[IV_NEXT]], 0x4170000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[IV_NEXT]], f0x4B800000
; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -534,7 +534,7 @@ define void @test_fp_to_int_irrealizable_exitval_int64_min() {
; CHECK-NEXT: [[IV:%.*]] = phi double [ 2.500000e+01, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: call void @opaque()
; CHECK-NEXT: [[IV_NEXT]] = fadd double [[IV]], 1.700000e+01
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ult double [[IV_NEXT]], 0xC3E0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ult double [[IV_NEXT]], f0xC3E0000000000000
; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/Inline/simplify-fp128.ll b/llvm/test/Transforms/Inline/simplify-fp128.ll
index 73e63702cefcb..8b049113fcff5 100644
--- a/llvm/test/Transforms/Inline/simplify-fp128.ll
+++ b/llvm/test/Transforms/Inline/simplify-fp128.ll
@@ -4,7 +4,7 @@
define void @fli() {
; CHECK-LABEL: define void @fli() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = call fp128 @llvm.floor.f128(fp128 0xL999999999999999A4001199999999999)
+; CHECK-NEXT: [[TMP0:%.*]] = call fp128 @llvm.floor.f128(fp128 4.400000e+00)
; CHECK-NEXT: ret void
;
entry:
@@ -15,7 +15,7 @@ entry:
define void @sc() {
; CHECK-LABEL: define void @sc() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = tail call fp128 @llvm.floor.f128(fp128 0xL999999999999999A4001199999999999)
+; CHECK-NEXT: [[TMP0:%.*]] = tail call fp128 @llvm.floor.f128(fp128 4.400000e+00)
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/Inline/simplify-instruction-computeKnownFPClass-context.ll b/llvm/test/Transforms/Inline/simplify-instruction-computeKnownFPClass-context.ll
index fcb4f3f7b20ed..bcb93e83c92ea 100644
--- a/llvm/test/Transforms/Inline/simplify-instruction-computeKnownFPClass-context.ll
+++ b/llvm/test/Transforms/Inline/simplify-instruction-computeKnownFPClass-context.ll
@@ -168,7 +168,7 @@ define i1 @simplify_fcmp_ord_ldexp_caller(double nofpclass(zero inf) %i0) {
; CHECK-LABEL: define i1 @simplify_fcmp_ord_ldexp_caller
; CHECK-SAME: (double nofpclass(inf zero) [[I0:%.*]]) {
; CHECK-NEXT: [[LDEXP_I:%.*]] = call double @llvm.ldexp.f64.i32(double [[I0]], i32 42)
-; CHECK-NEXT: [[CMP_I:%.*]] = fcmp one double [[LDEXP_I]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP_I:%.*]] = fcmp one double [[LDEXP_I]], +inf
; CHECK-NEXT: ret i1 [[CMP_I]]
;
%call = call i1 @simplify_fcmp_ord_ldexp_callee(double %i0)
@@ -188,7 +188,7 @@ define i1 @simplify_fcmp_ord_frexp_caller(double nofpclass(zero inf) %i0) {
; CHECK-SAME: (double nofpclass(inf zero) [[I0:%.*]]) {
; CHECK-NEXT: [[FREXP_I:%.*]] = call { double, i32 } @llvm.frexp.f64.i32(double [[I0]])
; CHECK-NEXT: [[FREXP_0_I:%.*]] = extractvalue { double, i32 } [[FREXP_I]], 0
-; CHECK-NEXT: [[CMP_I:%.*]] = fcmp one double [[FREXP_0_I]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP_I:%.*]] = fcmp one double [[FREXP_0_I]], +inf
; CHECK-NEXT: ret i1 [[CMP_I]]
;
%call = call i1 @simplify_fcmp_ord_frexp_callee(double %i0)
diff --git a/llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll b/llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
index b8d570637963d..d228874a32a09 100644
--- a/llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
+++ b/llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
@@ -9,7 +9,7 @@ define i32 @main() {
; CHECK-LABEL: @main(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[U:%.*]] = alloca [[STRUCT__1ANON:%.*]], align 8
-; CHECK-NEXT: store double 0x7FF0000000000000, ptr [[U]], align 8
+; CHECK-NEXT: store double +inf, ptr [[U]], align 8
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[U]], i64 4
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[TMP6]], 2146435072
diff --git a/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll b/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll
index f151605627a68..46a28dc5ad19d 100644
--- a/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll
+++ b/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll
@@ -6,7 +6,7 @@
define float @test(float %x, x86_fp80 %y) nounwind readonly {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0xK00000000000000000000
+; CHECK-NEXT: [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP71:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[BOTHCOND:%.*]] = or i1 [[TMP67]], [[TMP71]]
; CHECK-NEXT: br i1 [[BOTHCOND]], label [[BB74:%.*]], label [[BB80:%.*]]
@@ -31,7 +31,7 @@ bb80: ; preds = %entry
define float @test_logical(float %x, x86_fp80 %y) nounwind readonly {
; CHECK-LABEL: @test_logical(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0xK00000000000000000000
+; CHECK-NEXT: [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP71:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[BOTHCOND:%.*]] = select i1 [[TMP67]], i1 true, i1 [[TMP71]]
; CHECK-NEXT: br i1 [[BOTHCOND]], label [[BB74:%.*]], label [[BB80:%.*]]
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
index a8c9b2c90912e..8138c42036a9b 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
@@ -207,7 +207,7 @@ define <vscale x 4 x float> @constant_fdiv(<vscale x 4 x i1> %pg) #0 {
define <vscale x 4 x float> @constant_fdiv_u(<vscale x 4 x i1> %pg) #0 {
; CHECK-LABEL: define <vscale x 4 x float> @constant_fdiv_u(
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: ret <vscale x 4 x float> splat (float 0x3FF2AAAAA0000000)
+; CHECK-NEXT: ret <vscale x 4 x float> splat (float f0x3F955555)
;
%r = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
ret <vscale x 4 x float> %r
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
index c1621069abf71..87164cff4276e 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
@@ -18,7 +18,7 @@ define float @test_constant_fold_rcp_f32_poison() nounwind {
define float @test_constant_fold_rcp_f32_undef() nounwind {
; CHECK-LABEL: @test_constant_fold_rcp_f32_undef(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.rcp.f32(float undef) nounwind readnone
ret float %val
@@ -58,7 +58,7 @@ define double @test_constant_fold_rcp_f64_half() nounwind {
define float @test_constant_fold_rcp_f32_43() nounwind {
; CHECK-LABEL: @test_constant_fold_rcp_f32_43(
-; CHECK-NEXT: ret float 0x3F97D05F40000000
+; CHECK-NEXT: ret float f0x3CBE82FA
;
%val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) nounwind readnone
ret float %val
@@ -66,7 +66,7 @@ define float @test_constant_fold_rcp_f32_43() nounwind {
define double @test_constant_fold_rcp_f64_43() nounwind {
; CHECK-LABEL: @test_constant_fold_rcp_f64_43(
-; CHECK-NEXT: ret double 0x3F97D05F417D05F4
+; CHECK-NEXT: ret double f0x3F97D05F417D05F4
;
%val = call double @llvm.amdgcn.rcp.f64(double 4.300000e+01) nounwind readnone
ret double %val
@@ -99,7 +99,7 @@ define half @test_constant_fold_sqrt_f16_poison() nounwind {
define half @test_constant_fold_sqrt_f16_undef() nounwind {
; CHECK-LABEL: @test_constant_fold_sqrt_f16_undef(
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%val = call half @llvm.amdgcn.sqrt.f16(half undef) nounwind readnone
ret half %val
@@ -115,7 +115,7 @@ define float @test_constant_fold_sqrt_f32_poison() nounwind {
define float @test_constant_fold_sqrt_f32_undef() nounwind {
; CHECK-LABEL: @test_constant_fold_sqrt_f32_undef(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.sqrt.f32(float undef) nounwind readnone
ret float %val
@@ -123,7 +123,7 @@ define float @test_constant_fold_sqrt_f32_undef() nounwind {
define double @test_constant_fold_sqrt_f64_undef() nounwind {
; CHECK-LABEL: @test_constant_fold_sqrt_f64_undef(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%val = call double @llvm.amdgcn.sqrt.f64(double undef) nounwind readnone
ret double %val
@@ -131,7 +131,7 @@ define double @test_constant_fold_sqrt_f64_undef() nounwind {
define half @test_constant_fold_sqrt_f16_0() nounwind {
; CHECK-LABEL: @test_constant_fold_sqrt_f16_0(
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%val = call half @llvm.amdgcn.sqrt.f16(half 0.0) nounwind readnone
ret half %val
@@ -157,7 +157,7 @@ define double @test_constant_fold_sqrt_f64_0() nounwind {
define half @test_constant_fold_sqrt_f16_neg0() nounwind {
; CHECK-LABEL: @test_constant_fold_sqrt_f16_neg0(
-; CHECK-NEXT: ret half 0xH8000
+; CHECK-NEXT: ret half -0.000000e+00
;
%val = call half @llvm.amdgcn.sqrt.f16(half -0.0) nounwind readnone
ret half %val
@@ -183,7 +183,7 @@ define double @test_constant_fold_sqrt_f64_neg0() nounwind {
define double @test_constant_fold_sqrt_snan_f64() nounwind {
; CHECK-LABEL: @test_constant_fold_sqrt_snan_f64(
-; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0x7FF0000000000001)
+; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double +snan(0x1))
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.sqrt.f64(double 0x7FF0000000000001)
@@ -192,7 +192,7 @@ define double @test_constant_fold_sqrt_snan_f64() nounwind {
define double @test_constant_fold_sqrt_qnan_f64() nounwind {
; CHECK-LABEL: @test_constant_fold_sqrt_qnan_f64(
-; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double +qnan)
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.sqrt.f64(double 0x7FF8000000000000)
@@ -260,7 +260,7 @@ define float @test_constant_fold_rsq_f32_poison() nounwind {
define float @test_constant_fold_rsq_f32_undef() nounwind {
; CHECK-LABEL: @test_constant_fold_rsq_f32_undef(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.rsq.f32(float undef) nounwind readnone
ret float %val
@@ -364,7 +364,7 @@ define double @test_constant_fold_frexp_mant_f64_n1() nounwind {
define float @test_constant_fold_frexp_mant_f32_nan() nounwind {
; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_nan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.frexp.mant.f32(float 0x7FF8000000000000)
ret float %val
@@ -372,7 +372,7 @@ define float @test_constant_fold_frexp_mant_f32_nan() nounwind {
define double @test_constant_fold_frexp_mant_f64_nan() nounwind {
; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%val = call double @llvm.amdgcn.frexp.mant.f64(double 0x7FF8000000000000)
ret double %val
@@ -380,7 +380,7 @@ define double @test_constant_fold_frexp_mant_f64_nan() nounwind {
define float @test_constant_fold_frexp_mant_f32_inf() nounwind {
; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_inf(
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%val = call float @llvm.amdgcn.frexp.mant.f32(float 0x7FF0000000000000)
ret float %val
@@ -388,7 +388,7 @@ define float @test_constant_fold_frexp_mant_f32_inf() nounwind {
define double @test_constant_fold_frexp_mant_f64_inf() nounwind {
; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_inf(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%val = call double @llvm.amdgcn.frexp.mant.f64(double 0x7FF0000000000000)
ret double %val
@@ -396,7 +396,7 @@ define double @test_constant_fold_frexp_mant_f64_inf() nounwind {
define float @test_constant_fold_frexp_mant_f32_ninf() nounwind {
; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_ninf(
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%val = call float @llvm.amdgcn.frexp.mant.f32(float 0xFFF0000000000000)
ret float %val
@@ -404,7 +404,7 @@ define float @test_constant_fold_frexp_mant_f32_ninf() nounwind {
define double @test_constant_fold_frexp_mant_f64_ninf() nounwind {
; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_ninf(
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%val = call double @llvm.amdgcn.frexp.mant.f64(double 0xFFF0000000000000)
ret double %val
@@ -412,7 +412,7 @@ define double @test_constant_fold_frexp_mant_f64_ninf() nounwind {
define float @test_constant_fold_frexp_mant_f32_max_num() nounwind {
; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_max_num(
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%val = call float @llvm.amdgcn.frexp.mant.f32(float 0x47EFFFFFE0000000)
ret float %val
@@ -420,7 +420,7 @@ define float @test_constant_fold_frexp_mant_f32_max_num() nounwind {
define double @test_constant_fold_frexp_mant_f64_max_num() nounwind {
; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_max_num(
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%val = call double @llvm.amdgcn.frexp.mant.f64(double 0x7FEFFFFFFFFFFFFF)
ret double %val
@@ -1194,7 +1194,7 @@ define <2 x half> @constant_splat0_cvt_pkrtz() {
define <2 x half> @constant_cvt_pkrtz() {
; CHECK-LABEL: @constant_cvt_pkrtz(
-; CHECK-NEXT: ret <2 x half> <half 0xH4000, half 0xH4400>
+; CHECK-NEXT: ret <2 x half> <half 2.000000e+00, half 4.000000e+00>
;
%cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 2.0, float 4.0)
ret <2 x half> %cvt
@@ -1203,7 +1203,7 @@ define <2 x half> @constant_cvt_pkrtz() {
; Test constant values where rtz changes result
define <2 x half> @constant_rtz_pkrtz() {
; CHECK-LABEL: @constant_rtz_pkrtz(
-; CHECK-NEXT: ret <2 x half> splat (half 0xH7BFF)
+; CHECK-NEXT: ret <2 x half> splat (half 6.550400e+04)
;
%cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 65535.0, float 65535.0)
ret <2 x half> %cvt
@@ -1211,7 +1211,7 @@ define <2 x half> @constant_rtz_pkrtz() {
define <2 x half> @fpext_const_cvt_pkrtz(half %x) {
; CHECK-LABEL: @fpext_const_cvt_pkrtz(
-; CHECK-NEXT: [[CVT:%.*]] = insertelement <2 x half> <half poison, half 0xH4200>, half [[X:%.*]], i64 0
+; CHECK-NEXT: [[CVT:%.*]] = insertelement <2 x half> <half poison, half 3.000000e+00>, half [[X:%.*]], i64 0
; CHECK-NEXT: ret <2 x half> [[CVT]]
;
%ext = fpext half %x to float
@@ -1221,7 +1221,7 @@ define <2 x half> @fpext_const_cvt_pkrtz(half %x) {
define <2 x half> @const_fpext_cvt_pkrtz(half %y) {
; CHECK-LABEL: @const_fpext_cvt_pkrtz(
-; CHECK-NEXT: [[CVT:%.*]] = insertelement <2 x half> <half 0xH4500, half poison>, half [[Y:%.*]], i64 1
+; CHECK-NEXT: [[CVT:%.*]] = insertelement <2 x half> <half 5.000000e+00, half poison>, half [[Y:%.*]], i64 1
; CHECK-NEXT: ret <2 x half> [[CVT]]
;
%ext = fpext half %y to float
@@ -1231,8 +1231,8 @@ define <2 x half> @const_fpext_cvt_pkrtz(half %y) {
define <2 x half> @const_fpext_multi_cvt_pkrtz(half %y) {
; CHECK-LABEL: @const_fpext_multi_cvt_pkrtz(
-; CHECK-NEXT: [[CVT1:%.*]] = insertelement <2 x half> <half 0xH4500, half poison>, half [[Y:%.*]], i64 1
-; CHECK-NEXT: [[CVT2:%.*]] = insertelement <2 x half> <half 0xH4200, half poison>, half [[Y]], i64 1
+; CHECK-NEXT: [[CVT1:%.*]] = insertelement <2 x half> <half 5.000000e+00, half poison>, half [[Y:%.*]], i64 1
+; CHECK-NEXT: [[CVT2:%.*]] = insertelement <2 x half> <half 3.000000e+00, half poison>, half [[Y]], i64 1
; CHECK-NEXT: [[ADD:%.*]] = fadd <2 x half> [[CVT1]], [[CVT2]]
; CHECK-NEXT: ret <2 x half> [[ADD]]
;
@@ -1825,9 +1825,9 @@ declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2
define void @exp_compr_disabled_inputs_to_undef(<2 x half> %xy, <2 x half> %zw) {
; CHECK-LABEL: @exp_compr_disabled_inputs_to_undef(
; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> poison, <2 x half> poison, i1 true, i1 false)
-; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 1, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> poison, i1 true, i1 false)
-; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> poison, i1 true, i1 false)
-; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 3, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> poison, i1 true, i1 false)
+; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 1, <2 x half> <half 1.000000e+00, half 2.000000e+00>, <2 x half> poison, i1 true, i1 false)
+; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> <half 1.000000e+00, half 2.000000e+00>, <2 x half> poison, i1 true, i1 false)
+; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 3, <2 x half> <half 1.000000e+00, half 2.000000e+00>, <2 x half> poison, i1 true, i1 false)
; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> poison, <2 x half> poison, i1 true, i1 false)
; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 1, <2 x half> [[XY:%.*]], <2 x half> poison, i1 true, i1 false)
; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> [[XY]], <2 x half> poison, i1 true, i1 false)
@@ -3920,7 +3920,7 @@ define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_V2(ptr addrspace(1) %o
define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_const(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %slice) {
; CHECK-LABEL: @image_sample_a16_c_d_o_2darray_const(
-; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f16.v8i32.v4i32(i32 6, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half 0xH3400, half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f16.v8i32.v4i32(i32 6, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half 2.500000e-01, half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
; CHECK-NEXT: store <2 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
@@ -5655,7 +5655,7 @@ define double @trig_preop_constfold_variable_int(i32 %arg) {
define double @trig_preop_qnan(i32 %arg) {
; CHECK-LABEL: @trig_preop_qnan(
-; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF8000000000000, i32 [[ARG:%.*]])
+; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double +qnan, i32 [[ARG:%.*]])
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF8000000000000, i32 %arg)
@@ -5664,7 +5664,7 @@ define double @trig_preop_qnan(i32 %arg) {
define double @trig_preop_snan(i32 %arg) {
; CHECK-LABEL: @trig_preop_snan(
-; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000001, i32 [[ARG:%.*]])
+; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double +snan(0x1), i32 [[ARG:%.*]])
; CHECK-NEXT: ret double [[VAL]]
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000001, i32 %arg)
@@ -5673,7 +5673,7 @@ define double @trig_preop_snan(i32 %arg) {
define double @trig_preop_inf_0() {
; CHECK-LABEL: @trig_preop_inf_0(
-; CHECK-NEXT: ret double 0xB43DD63F5F2F8BD
+; CHECK-NEXT: ret double f0x0B43DD63F5F2F8BD
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000000, i32 0)
ret double %val
@@ -5681,7 +5681,7 @@ define double @trig_preop_inf_0() {
define double @trig_preop_ninf_0() {
; CHECK-LABEL: @trig_preop_ninf_0(
-; CHECK-NEXT: ret double 0xB43DD63F5F2F8BD
+; CHECK-NEXT: ret double f0x0B43DD63F5F2F8BD
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0xFFF0000000000000, i32 0)
ret double %val
@@ -5707,7 +5707,7 @@ define double @trig_preop_variable_args(double %arg0, i32 %arg1) {
define double @trig_preop_constfold() {
; CHECK-LABEL: @trig_preop_constfold(
-; CHECK-NEXT: ret double 0x394A6EE06DB14ACC
+; CHECK-NEXT: ret double f0x394A6EE06DB14ACC
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 2)
ret double %val
@@ -5734,7 +5734,7 @@ define double @trig_preop_constfold_neg1_segment() {
; Only use src1[4:0], so segment is actually 0 for -32.
define double @trig_preop_constfold_neg32_segment() {
; CHECK-LABEL: @trig_preop_constfold_neg32_segment(
-; CHECK-NEXT: ret double 0x3FE45F306DC9C882
+; CHECK-NEXT: ret double f0x3FE45F306DC9C882
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 -32)
ret double %val
@@ -5751,7 +5751,7 @@ define double @trig_preop_constfold_strictfp() strictfp {
define double @trig_preop_constfold_exponent0_mantissa0__segment0() {
; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa0__segment0(
-; CHECK-NEXT: ret double 0x3FE45F306DC9C882
+; CHECK-NEXT: ret double f0x3FE45F306DC9C882
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 0)
ret double %val
@@ -5759,7 +5759,7 @@ define double @trig_preop_constfold_exponent0_mantissa0__segment0() {
define double @trig_preop_constfold_exponent0_mantissa1__segment0() {
; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa1__segment0(
-; CHECK-NEXT: ret double 0x3FE45F306DC9C882
+; CHECK-NEXT: ret double f0x3FE45F306DC9C882
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x000FFFFFFFFFFFFF, i32 0)
ret double %val
@@ -5767,7 +5767,7 @@ define double @trig_preop_constfold_exponent0_mantissa1__segment0() {
define double @trig_preop_constfold_exponent0_mantissaX__segment0() {
; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissaX__segment0(
-; CHECK-NEXT: ret double 0x3FE45F306DC9C882
+; CHECK-NEXT: ret double f0x3FE45F306DC9C882
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x0004A7F09D5F47D4, i32 0)
ret double %val
@@ -5775,7 +5775,7 @@ define double @trig_preop_constfold_exponent0_mantissaX__segment0() {
define double @trig_preop_constfold_exponent0_mantissa0__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa0__segment2(
-; CHECK-NEXT: ret double 0x394A6EE06DB14ACC
+; CHECK-NEXT: ret double f0x394A6EE06DB14ACC
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 2)
ret double %val
@@ -5783,7 +5783,7 @@ define double @trig_preop_constfold_exponent0_mantissa0__segment2() {
define double @trig_preop_constfold_exponent0_mantissa1__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa1__segment2(
-; CHECK-NEXT: ret double 0x394A6EE06DB14ACC
+; CHECK-NEXT: ret double f0x394A6EE06DB14ACC
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x000FFFFFFFFFFFFF, i32 2)
ret double %val
@@ -5791,7 +5791,7 @@ define double @trig_preop_constfold_exponent0_mantissa1__segment2() {
define double @trig_preop_constfold_exponent0_mantissaX__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissaX__segment2(
-; CHECK-NEXT: ret double 0x394A6EE06DB14ACC
+; CHECK-NEXT: ret double f0x394A6EE06DB14ACC
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x00094A6EE06DB14A, i32 2)
ret double %val
@@ -5827,7 +5827,7 @@ define double @trig_preop_constfold_exponent0_mantissaX__outbound_segment() {
; 1607 = 1077 + 10 * 53
define double @trig_preop_constfold_exponent1607_mantissa0__segment0() {
; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa0__segment0(
-; CHECK-NEXT: ret double 0x1EC8135A2FBF209C
+; CHECK-NEXT: ret double f0x1EC8135A2FBF209C
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x6470000000000000, i32 0)
ret double %val
@@ -5836,7 +5836,7 @@ define double @trig_preop_constfold_exponent1607_mantissa0__segment0() {
; 1607 = 1077 + 10 * 53
define double @trig_preop_constfold_exponent1607_mantissa1__segment1() {
; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa1__segment1(
-; CHECK-NEXT: ret double 0x1EC8135A2FBF209C
+; CHECK-NEXT: ret double f0x1EC8135A2FBF209C
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x647FFFFFFFFFFFFF, i32 0)
ret double %val
@@ -5845,7 +5845,7 @@ define double @trig_preop_constfold_exponent1607_mantissa1__segment1() {
; 1607 = 1077 + 10 * 53
define double @trig_preop_constfold_exponent1607_mantissaX__segment1() {
; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissaX__segment1(
-; CHECK-NEXT: ret double 0x1EC8135A2FBF209C
+; CHECK-NEXT: ret double f0x1EC8135A2FBF209C
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x6471B791D6398353, i32 0)
ret double %val
@@ -5854,7 +5854,7 @@ define double @trig_preop_constfold_exponent1607_mantissaX__segment1() {
; 1607 = 1077 + 10 * 53
define double @trig_preop_constfold_exponent1607_mantissa0__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa0__segment2(
-; CHECK-NEXT: ret double 0x181272117E2EF7E4
+; CHECK-NEXT: ret double f0x181272117E2EF7E4
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x6470000000000000, i32 2)
ret double %val
@@ -5863,7 +5863,7 @@ define double @trig_preop_constfold_exponent1607_mantissa0__segment2() {
; 1607 = 1077 + 10 * 53
define double @trig_preop_constfold_exponent1607_mantissa1__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa1__segment2(
-; CHECK-NEXT: ret double 0x181272117E2EF7E4
+; CHECK-NEXT: ret double f0x181272117E2EF7E4
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x647FFFFFFFFFFFFF, i32 2)
ret double %val
@@ -5872,7 +5872,7 @@ define double @trig_preop_constfold_exponent1607_mantissa1__segment2() {
; 1607 = 1077 + 10 * 53
define double @trig_preop_constfold_exponent1607_mantissaX__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissaX__segment2(
-; CHECK-NEXT: ret double 0x181272117E2EF7E4
+; CHECK-NEXT: ret double f0x181272117E2EF7E4
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x647272117E2EF7E4, i32 2)
ret double %val
@@ -5907,7 +5907,7 @@ define double @trig_preop_constfold_exponent1607_mantissaX__outbound_segment() {
define double @trig_preop_constfold_exponent1968_mantissa0__segment0() {
; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa0__segment0(
-; CHECK-NEXT: ret double 0x10374F463F669E5F
+; CHECK-NEXT: ret double f0x10374F463F669E5F
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B00000000000000, i32 0)
ret double %val
@@ -5915,7 +5915,7 @@ define double @trig_preop_constfold_exponent1968_mantissa0__segment0() {
define double @trig_preop_constfold_exponent1968_mantissa1__segment0() {
; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa1__segment0(
-; CHECK-NEXT: ret double 0x10374F463F669E5F
+; CHECK-NEXT: ret double f0x10374F463F669E5F
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B0FFFFFFFFFFFFF, i32 0)
ret double %val
@@ -5923,7 +5923,7 @@ define double @trig_preop_constfold_exponent1968_mantissa1__segment0() {
define double @trig_preop_constfold_exponent1968_mantissax__segment0() {
; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissax__segment0(
-; CHECK-NEXT: ret double 0x10374F463F669E5F
+; CHECK-NEXT: ret double f0x10374F463F669E5F
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B074F463F669E5F, i32 0)
ret double %val
@@ -5931,7 +5931,7 @@ define double @trig_preop_constfold_exponent1968_mantissax__segment0() {
define double @trig_preop_constfold_exponent1968_mantissa0__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa0__segment2(
-; CHECK-NEXT: ret double 0x98F2F8BD9E839CE
+; CHECK-NEXT: ret double f0x098F2F8BD9E839CE
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B00000000000000, i32 2)
ret double %val
@@ -5939,7 +5939,7 @@ define double @trig_preop_constfold_exponent1968_mantissa0__segment2() {
define double @trig_preop_constfold_exponent1968_mantissa1__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa1__segment2(
-; CHECK-NEXT: ret double 0x98F2F8BD9E839CE
+; CHECK-NEXT: ret double f0x098F2F8BD9E839CE
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B0FFFFFFFFFFFFF, i32 2)
ret double %val
@@ -5947,7 +5947,7 @@ define double @trig_preop_constfold_exponent1968_mantissa1__segment2() {
define double @trig_preop_constfold_exponent1968_mantissaX__segment2() {
; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissaX__segment2(
-; CHECK-NEXT: ret double 0x98F2F8BD9E839CE
+; CHECK-NEXT: ret double f0x098F2F8BD9E839CE
;
%val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B0A2F8BD9E839CE, i32 2)
ret double %val
@@ -6053,7 +6053,7 @@ declare half @llvm.amdgcn.log.f16(half) nounwind readnone
define float @test_constant_fold_log_f32_undef() {
; CHECK-LABEL: @test_constant_fold_log_f32_undef(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.log.f32(float undef)
ret float %val
@@ -6069,7 +6069,7 @@ define float @test_constant_fold_log_f32_poison() {
define float @test_constant_fold_log_f32_p0() {
; CHECK-LABEL: @test_constant_fold_log_f32_p0(
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%val = call float @llvm.amdgcn.log.f32(float 0.0)
ret float %val
@@ -6077,7 +6077,7 @@ define float @test_constant_fold_log_f32_p0() {
define float @test_constant_fold_log_f32_n0() {
; CHECK-LABEL: @test_constant_fold_log_f32_n0(
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%val = call float @llvm.amdgcn.log.f32(float -0.0)
ret float %val
@@ -6085,7 +6085,7 @@ define float @test_constant_fold_log_f32_n0() {
define float @test_constant_fold_log_f32_subnormal() {
; CHECK-LABEL: @test_constant_fold_log_f32_subnormal(
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%val = call float @llvm.amdgcn.log.f32(float 0x380FFFFFC0000000)
ret float %val
@@ -6093,7 +6093,7 @@ define float @test_constant_fold_log_f32_subnormal() {
define float @test_constant_fold_log_f32_negsubnormal() {
; CHECK-LABEL: @test_constant_fold_log_f32_negsubnormal(
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%val = call float @llvm.amdgcn.log.f32(float 0xB80FFFFFC0000000)
ret float %val
@@ -6101,7 +6101,7 @@ define float @test_constant_fold_log_f32_negsubnormal() {
define float @test_constant_fold_log_f32_pinf() {
; CHECK-LABEL: @test_constant_fold_log_f32_pinf(
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%val = call float @llvm.amdgcn.log.f32(float 0x7FF0000000000000)
ret float %val
@@ -6109,7 +6109,7 @@ define float @test_constant_fold_log_f32_pinf() {
define float @test_constant_fold_log_f32_ninf() {
; CHECK-LABEL: @test_constant_fold_log_f32_ninf(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000)
ret float %val
@@ -6135,7 +6135,7 @@ define float @test_constant_fold_log_f32_p10() {
define float @test_constant_fold_log_f32_neg10() {
; CHECK-LABEL: @test_constant_fold_log_f32_neg10(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.log.f32(float -10.0)
ret float %val
@@ -6143,7 +6143,7 @@ define float @test_constant_fold_log_f32_neg10() {
define float @test_constant_fold_log_f32_qnan() {
; CHECK-LABEL: @test_constant_fold_log_f32_qnan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000)
ret float %val
@@ -6151,7 +6151,7 @@ define float @test_constant_fold_log_f32_qnan() {
define float @test_constant_fold_log_f32_snan() {
; CHECK-LABEL: @test_constant_fold_log_f32_snan(
-; CHECK-NEXT: ret float 0x7FF8000020000000
+; CHECK-NEXT: ret float +nan(0x1)
;
%val = call float @llvm.amdgcn.log.f32(float 0x7FF0000020000000)
ret float %val
@@ -6159,7 +6159,7 @@ define float @test_constant_fold_log_f32_snan() {
define half @test_constant_fold_log_f16_p0() {
; CHECK-LABEL: @test_constant_fold_log_f16_p0(
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%val = call half @llvm.amdgcn.log.f16(half 0.0)
ret half %val
@@ -6167,7 +6167,7 @@ define half @test_constant_fold_log_f16_p0() {
define half @test_constant_fold_log_f16_neg10() {
; CHECK-LABEL: @test_constant_fold_log_f16_neg10(
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%val = call half @llvm.amdgcn.log.f16(half -10.0)
ret half %val
@@ -6175,7 +6175,7 @@ define half @test_constant_fold_log_f16_neg10() {
define float @test_constant_fold_log_f32_qnan_strictfp() strictfp {
; CHECK-LABEL: @test_constant_fold_log_f32_qnan_strictfp(
-; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000) #[[ATTR20]]
+; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float +qnan) #[[ATTR20]]
; CHECK-NEXT: ret float [[VAL]]
;
%val = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000) strictfp
@@ -6211,7 +6211,7 @@ define float @test_constant_fold_log_f32_neg_strictfp() strictfp {
define float @test_constant_fold_log_f32_pinf_strictfp() strictfp {
; CHECK-LABEL: @test_constant_fold_log_f32_pinf_strictfp(
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%val = call float @llvm.amdgcn.log.f32(float 0x7FF0000000000000) strictfp
ret float %val
@@ -6219,7 +6219,7 @@ define float @test_constant_fold_log_f32_pinf_strictfp() strictfp {
define float @test_constant_fold_log_f32_ninf_strictfp() strictfp {
; CHECK-LABEL: @test_constant_fold_log_f32_ninf_strictfp(
-; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000) #[[ATTR20]]
+; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float -inf) #[[ATTR20]]
; CHECK-NEXT: ret float [[VAL]]
;
%val = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000) strictfp
@@ -6228,7 +6228,7 @@ define float @test_constant_fold_log_f32_ninf_strictfp() strictfp {
define half @test_constant_fold_log_f16_denorm() {
; CHECK-LABEL: @test_constant_fold_log_f16_denorm(
-; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.log.f16(half 0xH03FF)
+; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.log.f16(half 6.097560e-05)
; CHECK-NEXT: ret half [[VAL]]
;
%val = call half @llvm.amdgcn.log.f16(half 0xH03ff)
@@ -6237,7 +6237,7 @@ define half @test_constant_fold_log_f16_denorm() {
define half @test_constant_fold_log_f16_neg_denorm() {
; CHECK-LABEL: @test_constant_fold_log_f16_neg_denorm(
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%val = call half @llvm.amdgcn.log.f16(half 0xH83ff)
ret half %val
@@ -6252,7 +6252,7 @@ declare half @llvm.amdgcn.exp2.f16(half) nounwind readnone
define float @test_constant_fold_exp2_f32_undef() {
; CHECK-LABEL: @test_constant_fold_exp2_f32_undef(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.exp2.f32(float undef)
ret float %val
@@ -6354,7 +6354,7 @@ define float @test_constant_fold_exp2_f32_negsubnormal() {
define float @test_constant_fold_exp2_f32_pinf() {
; CHECK-LABEL: @test_constant_fold_exp2_f32_pinf(
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%val = call float @llvm.amdgcn.exp2.f32(float 0x7FF0000000000000)
ret float %val
@@ -6388,7 +6388,7 @@ define float @test_constant_fold_exp2_f32_neg10() {
define float @test_constant_fold_exp2_f32_qnan() {
; CHECK-LABEL: @test_constant_fold_exp2_f32_qnan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%val = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000)
ret float %val
@@ -6396,7 +6396,7 @@ define float @test_constant_fold_exp2_f32_qnan() {
define float @test_constant_fold_exp2_f32_snan() {
; CHECK-LABEL: @test_constant_fold_exp2_f32_snan(
-; CHECK-NEXT: ret float 0x7FF8000020000000
+; CHECK-NEXT: ret float +nan(0x1)
;
%val = call float @llvm.amdgcn.exp2.f32(float 0x7FF0000020000000)
ret float %val
@@ -6404,7 +6404,7 @@ define float @test_constant_fold_exp2_f32_snan() {
define half @test_constant_fold_exp2_f16_p0() {
; CHECK-LABEL: @test_constant_fold_exp2_f16_p0(
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
%val = call half @llvm.amdgcn.exp2.f16(half 0.0)
ret half %val
@@ -6412,7 +6412,7 @@ define half @test_constant_fold_exp2_f16_p0() {
define half @test_constant_fold_exp2_f16_neg10() {
; CHECK-LABEL: @test_constant_fold_exp2_f16_neg10(
-; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half 0xHC900)
+; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half -1.000000e+01)
; CHECK-NEXT: ret half [[VAL]]
;
%val = call half @llvm.amdgcn.exp2.f16(half -10.0)
@@ -6421,7 +6421,7 @@ define half @test_constant_fold_exp2_f16_neg10() {
define float @test_constant_fold_exp2_f32_qnan_strictfp() strictfp {
; CHECK-LABEL: @test_constant_fold_exp2_f32_qnan_strictfp(
-; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000) #[[ATTR20]]
+; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float +qnan) #[[ATTR20]]
; CHECK-NEXT: ret float [[VAL]]
;
%val = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000) strictfp
@@ -6493,7 +6493,7 @@ define float @test_constant_fold_exp2_f32_neg_strictfp() strictfp {
define float @test_constant_fold_exp2_f32_pinf_strictfp() strictfp {
; CHECK-LABEL: @test_constant_fold_exp2_f32_pinf_strictfp(
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%val = call float @llvm.amdgcn.exp2.f32(float 0x7FF0000000000000) strictfp
ret float %val
@@ -6509,7 +6509,7 @@ define float @test_constant_fold_exp2_f32_ninf_strictfp() strictfp {
define half @test_constant_fold_exp2_f16_denorm() {
; CHECK-LABEL: @test_constant_fold_exp2_f16_denorm(
-; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half 0xH03FF)
+; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half 6.097560e-05)
; CHECK-NEXT: ret half [[VAL]]
;
%val = call half @llvm.amdgcn.exp2.f16(half 0xH03ff)
@@ -6518,7 +6518,7 @@ define half @test_constant_fold_exp2_f16_denorm() {
define half @test_constant_fold_exp2_f16_neg_denorm() {
; CHECK-LABEL: @test_constant_fold_exp2_f16_neg_denorm(
-; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half 0xH83FF)
+; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half -6.097560e-05)
; CHECK-NEXT: ret half [[VAL]]
;
%val = call half @llvm.amdgcn.exp2.f16(half 0xH83ff)
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/fma_legacy.ll b/llvm/test/Transforms/InstCombine/AMDGPU/fma_legacy.ll
index b2f851d6d56ed..3efd68b9c1444 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/fma_legacy.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/fma_legacy.ll
@@ -87,9 +87,9 @@ define float @test_finite(i32 %x, i32 %y, float %z) {
define float @test_finite_assumed(float %x, float %y, float %z) {
; CHECK-LABEL: @test_finite_assumed(
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[IS_FINITE_X:%.*]] = fcmp one float [[FABS_X]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE_X:%.*]] = fcmp one float [[FABS_X]], +inf
; CHECK-NEXT: [[FABS_Y:%.*]] = call float @llvm.fabs.f32(float [[Y:%.*]])
-; CHECK-NEXT: [[IS_FINITE_Y:%.*]] = fcmp one float [[FABS_Y]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE_Y:%.*]] = fcmp one float [[FABS_Y]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_FINITE_X]])
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_FINITE_Y]])
; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.fma.f32(float [[X]], float [[Y]], float [[Z:%.*]])
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/fmed3-fpext-fold.ll b/llvm/test/Transforms/InstCombine/AMDGPU/fmed3-fpext-fold.ll
index 66011ad1ac76f..1e3f8800d37e7 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/fmed3-fpext-fold.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/fmed3-fpext-fold.ll
@@ -67,7 +67,7 @@ define float @fmed3_f32_fpext_f16_k0(half %arg1, half %arg2) #1 {
;
; GFX9-LABEL: define float @fmed3_f32_fpext_f16_k0
; GFX9-SAME: (half [[ARG1:%.*]], half [[ARG2:%.*]]) #[[ATTR1]] {
-; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG1]], half [[ARG2]], half 0xH4000)
+; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG1]], half [[ARG2]], half 2.000000e+00)
; GFX9-NEXT: [[MED3:%.*]] = fpext half [[MED31]] to float
; GFX9-NEXT: ret float [[MED3]]
;
@@ -87,7 +87,7 @@ define float @fmed3_f32_fpext_f16_k1(half %arg0, half %arg2) #1 {
;
; GFX9-LABEL: define float @fmed3_f32_fpext_f16_k1
; GFX9-SAME: (half [[ARG0:%.*]], half [[ARG2:%.*]]) #[[ATTR1]] {
-; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG0]], half [[ARG2]], half 0xH4000)
+; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG0]], half [[ARG2]], half 2.000000e+00)
; GFX9-NEXT: [[MED3:%.*]] = fpext half [[MED31]] to float
; GFX9-NEXT: ret float [[MED3]]
;
@@ -107,7 +107,7 @@ define float @fmed3_f32_fpext_f16_k2(half %arg0, half %arg1) #1 {
;
; GFX9-LABEL: define float @fmed3_f32_fpext_f16_k2
; GFX9-SAME: (half [[ARG0:%.*]], half [[ARG1:%.*]]) #[[ATTR1]] {
-; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG0]], half [[ARG1]], half 0xH4000)
+; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG0]], half [[ARG1]], half 2.000000e+00)
; GFX9-NEXT: [[MED3:%.*]] = fpext half [[MED31]] to float
; GFX9-NEXT: ret float [[MED3]]
;
@@ -126,7 +126,7 @@ define float @fmed3_f32_fpext_f16_k0_k1(half %arg2) #1 {
;
; GFX9-LABEL: define float @fmed3_f32_fpext_f16_k0_k1
; GFX9-SAME: (half [[ARG2:%.*]]) #[[ATTR1]] {
-; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG2]], half 0xH0000, half 0xH4C00)
+; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG2]], half 0.000000e+00, half 1.600000e+01)
; GFX9-NEXT: [[MED3:%.*]] = fpext half [[MED31]] to float
; GFX9-NEXT: ret float [[MED3]]
;
@@ -144,7 +144,7 @@ define float @fmed3_f32_fpext_f16_k0_k2(half %arg1) #1 {
;
; GFX9-LABEL: define float @fmed3_f32_fpext_f16_k0_k2
; GFX9-SAME: (half [[ARG1:%.*]]) #[[ATTR1]] {
-; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG1]], half 0xH0000, half 0xH4000)
+; GFX9-NEXT: [[MED31:%.*]] = call half @llvm.amdgcn.fmed3.f16(half [[ARG1]], half 0.000000e+00, half 2.000000e+00)
; GFX9-NEXT: [[MED3:%.*]] = fpext half [[MED31]] to float
; GFX9-NEXT: ret float [[MED3]]
;
@@ -547,14 +547,14 @@ define float @fmed3_f32_fpext_f16_unrepresentable_k0(half %arg1, half %arg2) #1
; NO-FMED3F16-SAME: (half [[ARG1:%.*]], half [[ARG2:%.*]]) #[[ATTR1]] {
; NO-FMED3F16-NEXT: [[ARG1_EXT:%.*]] = fpext half [[ARG1]] to float
; NO-FMED3F16-NEXT: [[ARG2_EXT:%.*]] = fpext half [[ARG2]] to float
-; NO-FMED3F16-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG1_EXT]], float [[ARG2_EXT]], float 0x41F0000000000000)
+; NO-FMED3F16-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG1_EXT]], float [[ARG2_EXT]], float f0x4F800000)
; NO-FMED3F16-NEXT: ret float [[MED3]]
;
; GFX9-LABEL: define float @fmed3_f32_fpext_f16_unrepresentable_k0
; GFX9-SAME: (half [[ARG1:%.*]], half [[ARG2:%.*]]) #[[ATTR1]] {
; GFX9-NEXT: [[ARG1_EXT:%.*]] = fpext half [[ARG1]] to float
; GFX9-NEXT: [[ARG2_EXT:%.*]] = fpext half [[ARG2]] to float
-; GFX9-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG1_EXT]], float [[ARG2_EXT]], float 0x41F0000000000000)
+; GFX9-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG1_EXT]], float [[ARG2_EXT]], float f0x4F800000)
; GFX9-NEXT: ret float [[MED3]]
;
%arg1.ext = fpext half %arg1 to float
@@ -568,14 +568,14 @@ define float @fmed3_f32_fpext_f16_unrepresentable_k1(half %arg0, half %arg2) #1
; NO-FMED3F16-SAME: (half [[ARG0:%.*]], half [[ARG2:%.*]]) #[[ATTR1]] {
; NO-FMED3F16-NEXT: [[ARG0_EXT:%.*]] = fpext half [[ARG0]] to float
; NO-FMED3F16-NEXT: [[ARG2_EXT:%.*]] = fpext half [[ARG2]] to float
-; NO-FMED3F16-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG0_EXT]], float [[ARG2_EXT]], float 0x41F0000000000000)
+; NO-FMED3F16-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG0_EXT]], float [[ARG2_EXT]], float f0x4F800000)
; NO-FMED3F16-NEXT: ret float [[MED3]]
;
; GFX9-LABEL: define float @fmed3_f32_fpext_f16_unrepresentable_k1
; GFX9-SAME: (half [[ARG0:%.*]], half [[ARG2:%.*]]) #[[ATTR1]] {
; GFX9-NEXT: [[ARG0_EXT:%.*]] = fpext half [[ARG0]] to float
; GFX9-NEXT: [[ARG2_EXT:%.*]] = fpext half [[ARG2]] to float
-; GFX9-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG0_EXT]], float [[ARG2_EXT]], float 0x41F0000000000000)
+; GFX9-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG0_EXT]], float [[ARG2_EXT]], float f0x4F800000)
; GFX9-NEXT: ret float [[MED3]]
;
%arg0.ext = fpext half %arg0 to float
@@ -589,14 +589,14 @@ define float @fmed3_f32_fpext_f16_unrepresentable_k2(half %arg0, half %arg1) #1
; NO-FMED3F16-SAME: (half [[ARG0:%.*]], half [[ARG1:%.*]]) #[[ATTR1]] {
; NO-FMED3F16-NEXT: [[ARG0_EXT:%.*]] = fpext half [[ARG0]] to float
; NO-FMED3F16-NEXT: [[ARG1_EXT:%.*]] = fpext half [[ARG1]] to float
-; NO-FMED3F16-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG0_EXT]], float [[ARG1_EXT]], float 0x41F0000000000000)
+; NO-FMED3F16-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG0_EXT]], float [[ARG1_EXT]], float f0x4F800000)
; NO-FMED3F16-NEXT: ret float [[MED3]]
;
; GFX9-LABEL: define float @fmed3_f32_fpext_f16_unrepresentable_k2
; GFX9-SAME: (half [[ARG0:%.*]], half [[ARG1:%.*]]) #[[ATTR1]] {
; GFX9-NEXT: [[ARG0_EXT:%.*]] = fpext half [[ARG0]] to float
; GFX9-NEXT: [[ARG1_EXT:%.*]] = fpext half [[ARG1]] to float
-; GFX9-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG0_EXT]], float [[ARG1_EXT]], float 0x41F0000000000000)
+; GFX9-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ARG0_EXT]], float [[ARG1_EXT]], float f0x4F800000)
; GFX9-NEXT: ret float [[MED3]]
;
%arg0.ext = fpext half %arg0 to float
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/fmed3.ll b/llvm/test/Transforms/InstCombine/AMDGPU/fmed3.ll
index 378ca1fa44c17..252e78fd179f7 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/fmed3.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/fmed3.ll
@@ -208,7 +208,7 @@ define float @fmed3_qnan1_x_y_f32(float %x, float %y) #1 {
define float @fmed3_qnan0_qnan1_qnan2_f32(float %x, float %y) #1 {
; CHECK-LABEL: define float @fmed3_qnan0_qnan1_qnan2_f32(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: ret float 0x7FF8030000000000
+; CHECK-NEXT: ret float +nan(0x1800)
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float 0x7FF8000100000000, float 0x7FF8002000000000, float 0x7FF8030000000000)
ret float %med3
@@ -415,7 +415,7 @@ define float @fmed3_x_snan1_y_f32(float %x, float %y) #1 {
define float @fmed3_x_y_snan1_f32(float %x, float %y) #1 {
; IEEE1-LABEL: define float @fmed3_x_y_snan1_f32(
; IEEE1-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1]] {
-; IEEE1-NEXT: ret float 0x7FFC000000000000
+; IEEE1-NEXT: ret float +nan(0x200000)
;
; IEEE0-LABEL: define float @fmed3_x_y_snan1_f32(
; IEEE0-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1]] {
@@ -429,7 +429,7 @@ define float @fmed3_x_y_snan1_f32(float %x, float %y) #1 {
define float @fmed3_snan1_x_snan2_f32(float %x) #1 {
; IEEE1-LABEL: define float @fmed3_snan1_x_snan2_f32(
; IEEE1-SAME: float [[X:%.*]]) #[[ATTR1]] {
-; IEEE1-NEXT: ret float 0x7FF0000040000000
+; IEEE1-NEXT: ret float +snan(0x2)
;
; IEEE0-LABEL: define float @fmed3_snan1_x_snan2_f32(
; IEEE0-SAME: float [[X:%.*]]) #[[ATTR1]] {
@@ -442,7 +442,7 @@ define float @fmed3_snan1_x_snan2_f32(float %x) #1 {
define float @fmed3_x_snan1_snan2_f32(float %x) #1 {
; IEEE1-LABEL: define float @fmed3_x_snan1_snan2_f32(
; IEEE1-SAME: float [[X:%.*]]) #[[ATTR1]] {
-; IEEE1-NEXT: ret float 0x7FF0000040000000
+; IEEE1-NEXT: ret float +snan(0x2)
;
; IEEE0-LABEL: define float @fmed3_x_snan1_snan2_f32(
; IEEE0-SAME: float [[X:%.*]]) #[[ATTR1]] {
@@ -455,11 +455,11 @@ define float @fmed3_x_snan1_snan2_f32(float %x) #1 {
define float @fmed3_snan1_snan2_snan3_f32(float %x) #1 {
; IEEE1-LABEL: define float @fmed3_snan1_snan2_snan3_f32(
; IEEE1-SAME: float [[X:%.*]]) #[[ATTR1]] {
-; IEEE1-NEXT: ret float 0x7FF0000040000000
+; IEEE1-NEXT: ret float +snan(0x2)
;
; IEEE0-LABEL: define float @fmed3_snan1_snan2_snan3_f32(
; IEEE0-SAME: float [[X:%.*]]) #[[ATTR1]] {
-; IEEE0-NEXT: ret float 0x7FF8000040000000
+; IEEE0-NEXT: ret float +nan(0x2)
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float 0x7FF4000000000000, float 0x7FF0000020000000, float 0x7FF0000040000000)
ret float %med3
@@ -494,7 +494,7 @@ define float @fmed3_snan1_neg1_2_f32(float %x, float %y) #1 {
define float @fmed3_neg2_3_snan1_f32(float %x, float %y) #1 {
; IEEE1-LABEL: define float @fmed3_neg2_3_snan1_f32(
; IEEE1-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1]] {
-; IEEE1-NEXT: ret float 0x7FFC000000000000
+; IEEE1-NEXT: ret float +nan(0x200000)
;
; IEEE0-LABEL: define float @fmed3_neg2_3_snan1_f32(
; IEEE0-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1]] {
@@ -649,7 +649,7 @@ define amdgpu_ps float @amdgpu_ps_default_fmed3_x_y_snan1_f32(float %x, float %y
;
; NO-IEEE-BIT-LABEL: define amdgpu_ps float @amdgpu_ps_default_fmed3_x_y_snan1_f32(
; NO-IEEE-BIT-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR2]] {
-; NO-IEEE-BIT-NEXT: ret float 0x7FFC000000000000
+; NO-IEEE-BIT-NEXT: ret float +nan(0x200000)
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float 0x7FF4000000000000)
ret float %med3
@@ -689,7 +689,7 @@ define amdgpu_ps float @amdgpu_ps_attr_fmed3_x_snan1_y_f32(float %x, float %y) #
define amdgpu_ps float @amdgpu_ps_attr_fmed3_x_y_snan1_f32(float %x, float %y) #1 {
; IEEE1-LABEL: define amdgpu_ps float @amdgpu_ps_attr_fmed3_x_y_snan1_f32(
; IEEE1-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1]] {
-; IEEE1-NEXT: ret float 0x7FFC000000000000
+; IEEE1-NEXT: ret float +nan(0x200000)
;
; IEEE0-LABEL: define amdgpu_ps float @amdgpu_ps_attr_fmed3_x_y_snan1_f32(
; IEEE0-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1]] {
@@ -707,7 +707,7 @@ define amdgpu_ps float @amdgpu_ps_attr_fmed3_x_y_snan1_f32(float %x, float %y) #
define float @fmed3_qnan0_x_y_f32_strictfp(float %x, float %y) #2 {
; CHECK-LABEL: define float @fmed3_qnan0_x_y_f32_strictfp(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3:[0-9]+]] {
-; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float 0x7FF8000000000000, float [[X]], float [[Y]]) #[[ATTR5:[0-9]+]]
+; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float +qnan, float [[X]], float [[Y]]) #[[ATTR5:[0-9]+]]
; CHECK-NEXT: ret float [[MED3]]
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float 0x7FF8000000000000, float %x, float %y) strictfp
@@ -717,7 +717,7 @@ define float @fmed3_qnan0_x_y_f32_strictfp(float %x, float %y) #2 {
define float @fmed3_x_qnan0_y_f32_strictfp(float %x, float %y) #2 {
; CHECK-LABEL: define float @fmed3_x_qnan0_y_f32_strictfp(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float 0x7FF8000000000000, float [[Y]]) #[[ATTR5]]
+; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float +qnan, float [[Y]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[MED3]]
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float %x, float 0x7FF8000000000000, float %y) strictfp
@@ -727,7 +727,7 @@ define float @fmed3_x_qnan0_y_f32_strictfp(float %x, float %y) #2 {
define float @fmed3_x_y_qnan0_f32_strictfp(float %x, float %y) #2 {
; CHECK-LABEL: define float @fmed3_x_y_qnan0_f32_strictfp(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float [[Y]], float 0x7FF8000000000000) #[[ATTR5]]
+; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float [[Y]], float +qnan) #[[ATTR5]]
; CHECK-NEXT: ret float [[MED3]]
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float 0x7FF8000000000000) strictfp
@@ -737,7 +737,7 @@ define float @fmed3_x_y_qnan0_f32_strictfp(float %x, float %y) #2 {
define float @fmed3_snan1_x_y_f32_strictfp(float %x, float %y) #2 {
; CHECK-LABEL: define float @fmed3_snan1_x_y_f32_strictfp(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float 0x7FF4000000000000, float [[X]], float [[Y]]) #[[ATTR5]]
+; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float +snan(0x200000), float [[X]], float [[Y]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[MED3]]
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float 0x7FF4000000000000, float %x, float %y) strictfp
@@ -747,7 +747,7 @@ define float @fmed3_snan1_x_y_f32_strictfp(float %x, float %y) #2 {
define float @fmed3_x_snan1_y_f32_strictfp(float %x, float %y) #2 {
; CHECK-LABEL: define float @fmed3_x_snan1_y_f32_strictfp(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float 0x7FF4000000000000, float [[Y]]) #[[ATTR5]]
+; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float +snan(0x200000), float [[Y]]) #[[ATTR5]]
; CHECK-NEXT: ret float [[MED3]]
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float %x, float 0x7FF4000000000000, float %y) strictfp
@@ -757,7 +757,7 @@ define float @fmed3_x_snan1_y_f32_strictfp(float %x, float %y) #2 {
define float @fmed3_x_y_snan1_f32_strictfp(float %x, float %y) #2 {
; CHECK-LABEL: define float @fmed3_x_y_snan1_f32_strictfp(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float [[Y]], float 0x7FF4000000000000) #[[ATTR5]]
+; CHECK-NEXT: [[MED3:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[X]], float [[Y]], float +snan(0x200000)) #[[ATTR5]]
; CHECK-NEXT: ret float [[MED3]]
;
%med3 = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float 0x7FF4000000000000) strictfp
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll b/llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll
index a1872b25ff7f5..4600831b60b87 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll
@@ -57,9 +57,9 @@ define float @test_finite(i32 %x, i32 %y) {
define float @test_finite_assumed(float %x, float %y) {
; CHECK-LABEL: @test_finite_assumed(
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[IS_FINITE_X:%.*]] = fcmp one float [[FABS_X]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE_X:%.*]] = fcmp one float [[FABS_X]], +inf
; CHECK-NEXT: [[FABS_Y:%.*]] = call float @llvm.fabs.f32(float [[Y:%.*]])
-; CHECK-NEXT: [[IS_FINITE_Y:%.*]] = fcmp one float [[FABS_Y]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE_Y:%.*]] = fcmp one float [[FABS_Y]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_FINITE_X]])
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_FINITE_Y]])
; CHECK-NEXT: [[CALL:%.*]] = fmul nnan float [[X]], [[Y]]
diff --git a/llvm/test/Transforms/InstCombine/X86/2009-03-23-i80-fp80.ll b/llvm/test/Transforms/InstCombine/X86/2009-03-23-i80-fp80.ll
index 1e2396e952887..c32be05249fa9 100644
--- a/llvm/test/Transforms/InstCombine/X86/2009-03-23-i80-fp80.ll
+++ b/llvm/test/Transforms/InstCombine/X86/2009-03-23-i80-fp80.ll
@@ -13,7 +13,7 @@ define i80 @from() {
define x86_fp80 @to() {
; CHECK-LABEL: @to(
-; CHECK-NEXT: ret x86_fp80 0xK40018000000000000000
+; CHECK-NEXT: ret x86_fp80 4.000000e+00
;
%tmp = bitcast i80 302259125019767858003968 to x86_fp80
ret x86_fp80 %tmp
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-fp-minmax-negzero.ll b/llvm/test/Transforms/InstCombine/X86/x86-fp-minmax-negzero.ll
index 2ec4ed308ad25..852885e955846 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-fp-minmax-negzero.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-fp-minmax-negzero.ll
@@ -63,7 +63,7 @@ entry:
define <4 x float> @test_max_ss_allow_negzero_first() {
; CHECK-LABEL: define <4 x float> @test_max_ss_allow_negzero_first() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x float> <float 1.000000e+00, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>
+; CHECK-NEXT: ret <4 x float> <float 1.000000e+00, float +qnan, float +qnan, float +qnan>
;
entry:
%r = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> <float -0.0, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>, <4 x float> <float 1.0, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>)
@@ -73,7 +73,7 @@ entry:
define <4 x float> @test_max_ss_disallow_negzero_second() {
; CHECK-LABEL: define <4 x float> @test_max_ss_disallow_negzero_second() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[R:%.*]] = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> <float 1.000000e+00, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>, <4 x float> <float -0.000000e+00, float poison, float poison, float poison>)
+; CHECK-NEXT: [[R:%.*]] = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> <float 1.000000e+00, float +qnan, float +qnan, float +qnan>, <4 x float> <float -0.000000e+00, float poison, float poison, float poison>)
; CHECK-NEXT: ret <4 x float> [[R]]
;
entry:
@@ -84,7 +84,7 @@ entry:
define <4 x float> @test_min_ss_allow_negzero_second() {
; CHECK-LABEL: define <4 x float> @test_min_ss_allow_negzero_second() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x float> <float -0.000000e+00, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>
+; CHECK-NEXT: ret <4 x float> <float -0.000000e+00, float +qnan, float +qnan, float +qnan>
;
entry:
%r = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float 1.0, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>, <4 x float> <float -0.0, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>)
@@ -94,7 +94,7 @@ entry:
define <4 x float> @test_min_ss_disallow_negzero_first() {
; CHECK-LABEL: define <4 x float> @test_min_ss_disallow_negzero_first() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[R:%.*]] = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float -0.000000e+00, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>, <4 x float> <float 1.000000e+00, float poison, float poison, float poison>)
+; CHECK-NEXT: [[R:%.*]] = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float -0.000000e+00, float +qnan, float +qnan, float +qnan>, <4 x float> <float 1.000000e+00, float poison, float poison, float poison>)
; CHECK-NEXT: ret <4 x float> [[R]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-maxmin.ll b/llvm/test/Transforms/InstCombine/X86/x86-maxmin.ll
index dd87c9e8c1836..d147e33e2049e 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-maxmin.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-maxmin.ll
@@ -125,7 +125,7 @@ define <32 x half> @test_avx512fp16_max_ph(<32 x i16> %x, <32 x i16> %y) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[CVT:%.*]] = sitofp <32 x i16> [[X]] to <32 x half>
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <32 x i16> [[Y]], splat (i16 -1)
-; CHECK-NEXT: [[SEL:%.*]] = select <32 x i1> [[CMP]], <32 x half> splat (half 0xH3C00), <32 x half> splat (half 0xHBC00)
+; CHECK-NEXT: [[SEL:%.*]] = select <32 x i1> [[CMP]], <32 x half> splat (half 1.000000e+00), <32 x half> splat (half -1.000000e+00)
; CHECK-NEXT: [[MAX:%.*]] = call <32 x half> @llvm.maxnum.v32f16(<32 x half> [[CVT]], <32 x half> [[SEL]])
; CHECK-NEXT: ret <32 x half> [[MAX]]
;
@@ -143,7 +143,7 @@ define <32 x half> @test_avx512fp16_min_ph(<32 x i16> %x, <32 x i16> %y) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[CVT:%.*]] = sitofp <32 x i16> [[X]] to <32 x half>
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <32 x i16> [[Y]], splat (i16 -1)
-; CHECK-NEXT: [[SEL:%.*]] = select <32 x i1> [[CMP]], <32 x half> splat (half 0xH3C00), <32 x half> splat (half 0xHBC00)
+; CHECK-NEXT: [[SEL:%.*]] = select <32 x i1> [[CMP]], <32 x half> splat (half 1.000000e+00), <32 x half> splat (half -1.000000e+00)
; CHECK-NEXT: [[MAX:%.*]] = call <32 x half> @llvm.minnum.v32f16(<32 x half> [[CVT]], <32 x half> [[SEL]])
; CHECK-NEXT: ret <32 x half> [[MAX]]
;
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-scalar-max-min.ll b/llvm/test/Transforms/InstCombine/X86/x86-scalar-max-min.ll
index 0119a8ed3dd9b..4a5d388e7f128 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-scalar-max-min.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-scalar-max-min.ll
@@ -4,7 +4,7 @@
define <4 x float> @test_max_ss_nan(<4 x float> %a) {
; CHECK-LABEL: define <4 x float> @test_max_ss_nan(
; CHECK-SAME: <4 x float> [[A:%.*]]) {
-; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[A]], <4 x float> <float 0x7FF8000000000000, float poison, float poison, float poison>)
+; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[A]], <4 x float> <float +qnan, float poison, float poison, float poison>)
; CHECK-NEXT: ret <4 x float> [[RES]]
;
%res = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a, <4 x float> <float 0x7FF8000000000000, float 0.0, float 0.0, float 0.0>)
@@ -14,7 +14,7 @@ define <4 x float> @test_max_ss_nan(<4 x float> %a) {
define <4 x float> @test_min_ss_inf(<4 x float> %a) {
; CHECK-LABEL: define <4 x float> @test_min_ss_inf(
; CHECK-SAME: <4 x float> [[A:%.*]]) {
-; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[A]], <4 x float> <float 0x7FF0000000000000, float poison, float poison, float poison>)
+; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[A]], <4 x float> <float +inf, float poison, float poison, float poison>)
; CHECK-NEXT: ret <4 x float> [[RES]]
;
%res = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a, <4 x float> <float 0x7FF0000000000000, float 0.0, float 0.0, float 0.0>)
diff --git a/llvm/test/Transforms/InstCombine/and-fcmp.ll b/llvm/test/Transforms/InstCombine/and-fcmp.ll
index ec1b6ad2ea168..99adb49a579ec 100644
--- a/llvm/test/Transforms/InstCombine/and-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/and-fcmp.ll
@@ -4631,7 +4631,7 @@ define i1 @intersect_fmf_4(double %a, double %b) {
define i1 @clang_builtin_isnormal_inf_check(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4644,7 +4644,7 @@ define i1 @clang_builtin_isnormal_inf_check(half %x) {
define <2 x i1> @clang_builtin_isnormal_inf_check_vector(<2 x half> %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_vector(
; CHECK-NEXT: [[FABS_X:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq <2 x half> [[FABS_X]], splat (half 0xH7C00)
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq <2 x half> [[FABS_X]], splat (half +inf)
; CHECK-NEXT: ret <2 x i1> [[AND]]
;
%fabs.x = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
@@ -4657,7 +4657,7 @@ define <2 x i1> @clang_builtin_isnormal_inf_check_vector(<2 x half> %x) {
define i1 @clang_builtin_isnormal_inf_check_commute(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4670,7 +4670,7 @@ define i1 @clang_builtin_isnormal_inf_check_commute(half %x) {
define i1 @clang_builtin_isnormal_inf_check_commute_nsz_rhs(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute_nsz_rhs(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4683,7 +4683,7 @@ define i1 @clang_builtin_isnormal_inf_check_commute_nsz_rhs(half %x) {
define i1 @clang_builtin_isnormal_inf_check_commute_nsz_lhs(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute_nsz_lhs(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4695,7 +4695,7 @@ define i1 @clang_builtin_isnormal_inf_check_commute_nsz_lhs(half %x) {
define i1 @clang_builtin_isnormal_inf_check_commute_nofabs_ueq(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute_nofabs_ueq(
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%ord = fcmp ord half %x, 0.0
@@ -4707,7 +4707,7 @@ define i1 @clang_builtin_isnormal_inf_check_commute_nofabs_ueq(half %x) {
define i1 @clang_builtin_isnormal_inf_check_commute_nsz(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_commute_nsz(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp nsz oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp nsz oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4733,7 +4733,7 @@ define i1 @clang_builtin_isnormal_inf_check_ugt(half %x) {
define i1 @clang_builtin_isnormal_inf_check_ult(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ult(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4746,7 +4746,7 @@ define i1 @clang_builtin_isnormal_inf_check_ult(half %x) {
; ule -> ole
define i1 @clang_builtin_isnormal_inf_check_ule(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ule(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[ORD]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4760,7 +4760,7 @@ define i1 @clang_builtin_isnormal_inf_check_ule(half %x) {
define i1 @clang_builtin_isnormal_inf_check_ueq(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ueq(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4774,7 +4774,7 @@ define i1 @clang_builtin_isnormal_inf_check_ueq(half %x) {
define i1 @clang_builtin_isnormal_inf_check_une(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_une(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4799,7 +4799,7 @@ define i1 @clang_builtin_isnormal_inf_check_uno(half %x) {
; ord -> ord
define i1 @clang_builtin_isnormal_inf_check_ord(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ord(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4812,7 +4812,7 @@ define i1 @clang_builtin_isnormal_inf_check_ord(half %x) {
define i1 @clang_builtin_isnormal_inf_check_oge(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_oge(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4825,7 +4825,7 @@ define i1 @clang_builtin_isnormal_inf_check_oge(half %x) {
define i1 @clang_builtin_isnormal_inf_check_olt(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_olt(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4837,7 +4837,7 @@ define i1 @clang_builtin_isnormal_inf_check_olt(half %x) {
define i1 @clang_builtin_isnormal_inf_check_ole(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_ole(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4850,7 +4850,7 @@ define i1 @clang_builtin_isnormal_inf_check_ole(half %x) {
define i1 @clang_builtin_isnormal_inf_check_oeq(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_oeq(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4863,7 +4863,7 @@ define i1 @clang_builtin_isnormal_inf_check_oeq(half %x) {
define i1 @clang_builtin_isnormal_inf_check_unnececcary_fabs(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_unnececcary_fabs(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4876,7 +4876,7 @@ define i1 @clang_builtin_isnormal_inf_check_unnececcary_fabs(half %x) {
; Negative test
define i1 @clang_builtin_isnormal_inf_check_not_ord(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_not_ord(
-; CHECK-NEXT: [[AND:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[AND:%.*]] = fcmp uno half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4888,7 +4888,7 @@ define i1 @clang_builtin_isnormal_inf_check_not_ord(half %x) {
define i1 @clang_builtin_isnormal_inf_check_missing_fabs(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_missing_fabs(
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4900,7 +4900,7 @@ define i1 @clang_builtin_isnormal_inf_check_missing_fabs(half %x) {
define i1 @clang_builtin_isnormal_inf_check_neg_inf(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_neg_inf(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[ORD]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4914,8 +4914,8 @@ define i1 @clang_builtin_isnormal_inf_check_neg_inf(half %x) {
define i1 @clang_builtin_isnormal_inf_check_not_inf(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_not_inf(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT: [[UEQ:%.*]] = fcmp uge half [[FABS_X]], 0xH7BFF
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
+; CHECK-NEXT: [[UEQ:%.*]] = fcmp uge half [[FABS_X]], 6.550400e+04
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
;
@@ -4929,7 +4929,7 @@ define i1 @clang_builtin_isnormal_inf_check_not_inf(half %x) {
define i1 @clang_builtin_isnormal_inf_check_nsz_lhs(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_nsz_lhs(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4942,7 +4942,7 @@ define i1 @clang_builtin_isnormal_inf_check_nsz_lhs(half %x) {
define i1 @clang_builtin_isnormal_inf_check_nsz_rhs(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_nsz_rhs(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4955,7 +4955,7 @@ define i1 @clang_builtin_isnormal_inf_check_nsz_rhs(half %x) {
define i1 @clang_builtin_isnormal_inf_check_nsz(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_nsz(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp nsz oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp nsz oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -4967,7 +4967,7 @@ define i1 @clang_builtin_isnormal_inf_check_nsz(half %x) {
define i1 @clang_builtin_isnormal_inf_check_fneg(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_fneg(
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fneg.x = fneg half %x
@@ -4980,7 +4980,7 @@ define i1 @clang_builtin_isnormal_inf_check_fneg(half %x) {
define i1 @clang_builtin_isnormal_inf_check_copysign(half %x, half %y) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_copysign(
; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%copysign.x = call half @llvm.copysign.f16(half %x, half %y)
@@ -4993,8 +4993,8 @@ define i1 @clang_builtin_isnormal_inf_check_copysign(half %x, half %y) {
define i1 @clang_builtin_isnormal_inf_check_copysign_logical_select(half %x, half %y) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_copysign_logical_select(
; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[COPYSIGN_X]], 0xH7C00
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[COPYSIGN_X]], +inf
; CHECK-NEXT: [[AND:%.*]] = select i1 [[ORD]], i1 [[CMP]], i1 false
; CHECK-NEXT: ret i1 [[AND]]
;
@@ -5008,7 +5008,7 @@ define i1 @clang_builtin_isnormal_inf_check_copysign_logical_select(half %x, hal
define i1 @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(
; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%copysign.x = call nnan half @llvm.fabs.f16(half %x)
@@ -5021,7 +5021,7 @@ define i1 @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(half %x) {
define i1 @isnormal_logical_select_0(half %x) {
; CHECK-LABEL: @isnormal_logical_select_0(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -5034,7 +5034,7 @@ define i1 @isnormal_logical_select_0(half %x) {
define i1 @isnormal_logical_select_1(half %x) {
; CHECK-LABEL: @isnormal_logical_select_1(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -5047,7 +5047,7 @@ define i1 @isnormal_logical_select_1(half %x) {
define i1 @isnormal_logical_select_0_fmf0(half %x) {
; CHECK-LABEL: @isnormal_logical_select_0_fmf0(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp reassoc nsz arcp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp reassoc nsz arcp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
@@ -5060,7 +5060,7 @@ define i1 @isnormal_logical_select_0_fmf0(half %x) {
define i1 @isnormal_logical_select_0_fmf1(half %x) {
; CHECK-LABEL: @isnormal_logical_select_0_fmf1(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS_X]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs.x = call half @llvm.fabs.f16(half %x)
diff --git a/llvm/test/Transforms/InstCombine/atomicrmw.ll b/llvm/test/Transforms/InstCombine/atomicrmw.ll
index ca5ffd110ad61..b196b1932b7b0 100644
--- a/llvm/test/Transforms/InstCombine/atomicrmw.ll
+++ b/llvm/test/Transforms/InstCombine/atomicrmw.ll
@@ -255,7 +255,7 @@ define i8 @sat_max_smax_char(ptr %addr) {
define double @sat_fadd_nan(ptr %addr) {
; CHECK-LABEL: @sat_fadd_nan(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0x7FF00000FFFFFFFF release, align 8
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double +snan(0xFFFFFFFF) release, align 8
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fadd ptr %addr, double 0x7FF00000FFFFFFFF release
@@ -264,7 +264,7 @@ define double @sat_fadd_nan(ptr %addr) {
define double @sat_fsub_nan(ptr %addr) {
; CHECK-LABEL: @sat_fsub_nan(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0x7FF00000FFFFFFFF release, align 8
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double +snan(0xFFFFFFFF) release, align 8
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fsub ptr %addr, double 0x7FF00000FFFFFFFF release
@@ -273,7 +273,7 @@ define double @sat_fsub_nan(ptr %addr) {
define void @sat_fsub_nan_unused(ptr %addr) {
; CHECK-LABEL: @sat_fsub_nan_unused(
-; CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0x7FF00000FFFFFFFF monotonic, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double +snan(0xFFFFFFFF) monotonic, align 8
; CHECK-NEXT: ret void
;
atomicrmw fsub ptr %addr, double 0x7FF00000FFFFFFFF monotonic
@@ -363,7 +363,7 @@ define i32 @undef_operand_used(ptr %addr) {
define double @sat_fmax_inf(ptr %addr) {
; CHECK-LABEL: @sat_fmax_inf(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0x7FF0000000000000 monotonic, align 8
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double +inf monotonic, align 8
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fmax ptr %addr, double 0x7FF0000000000000 monotonic
@@ -381,7 +381,7 @@ define double @no_sat_fmax_inf(ptr %addr) {
define double @sat_fmin_inf(ptr %addr) {
; CHECK-LABEL: @sat_fmin_inf(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0xFFF0000000000000 monotonic, align 8
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double -inf monotonic, align 8
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fmin ptr %addr, double 0xFFF0000000000000 monotonic
@@ -399,7 +399,7 @@ define double @no_sat_fmin_inf(ptr %addr) {
define double @sat_fmaximum_inf(ptr %addr) {
; CHECK-LABEL: @sat_fmaximum_inf(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw fmaximum ptr [[ADDR:%.*]], double 0x7FF0000000000000 monotonic, align 8
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw fmaximum ptr [[ADDR:%.*]], double +inf monotonic, align 8
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fmaximum ptr %addr, double 0x7FF0000000000000 monotonic
@@ -417,7 +417,7 @@ define double @no_sat_fmaximum_inf(ptr %addr) {
define double @sat_fminimum_inf(ptr %addr) {
; CHECK-LABEL: @sat_fminimum_inf(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw fminimum ptr [[ADDR:%.*]], double 0xFFF0000000000000 monotonic, align 8
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw fminimum ptr [[ADDR:%.*]], double -inf monotonic, align 8
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fminimum ptr %addr, double 0xFFF0000000000000 monotonic
@@ -682,7 +682,7 @@ define i8 @sat_max_smax_char_preserve_md(ptr %addr) {
define double @sat_fadd_nan_preserve_md(ptr %addr) {
; CHECK-LABEL: @sat_fadd_nan_preserve_md(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0x7FF00000FFFFFFFF release, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double +snan(0xFFFFFFFF) release, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fadd ptr %addr, double 0x7FF00000FFFFFFFF release, !amdgpu.no.fine.grained.host.memory !0, !amdgpu.no.remote.memory.access !0, !mmra !1
@@ -691,7 +691,7 @@ define double @sat_fadd_nan_preserve_md(ptr %addr) {
define double @sat_fsub_nan_preserve_md(ptr %addr) {
; CHECK-LABEL: @sat_fsub_nan_preserve_md(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0x7FF00000FFFFFFFF release, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double +snan(0xFFFFFFFF) release, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fsub ptr %addr, double 0x7FF00000FFFFFFFF release, !amdgpu.no.fine.grained.host.memory !0, !amdgpu.no.remote.memory.access !0, !mmra !1
@@ -700,7 +700,7 @@ define double @sat_fsub_nan_preserve_md(ptr %addr) {
define void @sat_fsub_nan_unused_preserve_md(ptr %addr) {
; CHECK-LABEL: @sat_fsub_nan_unused_preserve_md(
-; CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0x7FF00000FFFFFFFF syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
+; CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double +snan(0xFFFFFFFF) syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
; CHECK-NEXT: ret void
;
atomicrmw fsub ptr %addr, double 0x7FF00000FFFFFFFF syncscope("agent") monotonic, !amdgpu.no.fine.grained.host.memory !0, !amdgpu.no.remote.memory.access !0, !mmra !1
@@ -790,7 +790,7 @@ define i32 @undef_operand_used_preserve_md(ptr %addr) {
define double @sat_fmax_inf_preserve_md(ptr %addr) {
; CHECK-LABEL: @sat_fmax_inf_preserve_md(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0x7FF0000000000000 syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double +inf syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fmax ptr %addr, double 0x7FF0000000000000 syncscope("agent") monotonic, !amdgpu.no.fine.grained.host.memory !0, !amdgpu.no.remote.memory.access !0, !mmra !1
@@ -808,7 +808,7 @@ define double @no_sat_fmax_inf_preserve_md(ptr %addr) {
define double @sat_fmin_inf_preserve_md(ptr %addr) {
; CHECK-LABEL: @sat_fmin_inf_preserve_md(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double 0xFFF0000000000000 syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw xchg ptr [[ADDR:%.*]], double -inf syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fmin ptr %addr, double 0xFFF0000000000000 syncscope("agent") monotonic, !amdgpu.no.fine.grained.host.memory !0, !amdgpu.no.remote.memory.access !0, !mmra !1
@@ -826,7 +826,7 @@ define double @no_sat_fmin_inf_preserve_md(ptr %addr) {
define double @sat_fmaximum_inf_preserve_md(ptr %addr) {
; CHECK-LABEL: @sat_fmaximum_inf_preserve_md(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw fmaximum ptr [[ADDR:%.*]], double 0x7FF0000000000000 syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw fmaximum ptr [[ADDR:%.*]], double +inf syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fmaximum ptr %addr, double 0x7FF0000000000000 syncscope("agent") monotonic, !amdgpu.no.fine.grained.host.memory !0, !amdgpu.no.remote.memory.access !0, !mmra !1
@@ -844,7 +844,7 @@ define double @no_sat_fmaximum_inf_preserve_md(ptr %addr) {
define double @sat_fminimum_inf_preserve_md(ptr %addr) {
; CHECK-LABEL: @sat_fminimum_inf_preserve_md(
-; CHECK-NEXT: [[RES:%.*]] = atomicrmw fminimum ptr [[ADDR:%.*]], double 0xFFF0000000000000 syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
+; CHECK-NEXT: [[RES:%.*]] = atomicrmw fminimum ptr [[ADDR:%.*]], double -inf syncscope("agent") monotonic, align 8, !mmra [[META0]], !amdgpu.no.fine.grained.host.memory [[META1]], !amdgpu.no.remote.memory.access [[META1]]
; CHECK-NEXT: ret double [[RES]]
;
%res = atomicrmw fminimum ptr %addr, double 0xFFF0000000000000 syncscope("agent") monotonic, !amdgpu.no.fine.grained.host.memory !0, !amdgpu.no.remote.memory.access !0, !mmra !1
diff --git a/llvm/test/Transforms/InstCombine/binop-itofp.ll b/llvm/test/Transforms/InstCombine/binop-itofp.ll
index 422fc42f65594..d4f57026174b6 100644
--- a/llvm/test/Transforms/InstCombine/binop-itofp.ll
+++ b/llvm/test/Transforms/InstCombine/binop-itofp.ll
@@ -50,7 +50,7 @@ define half @test_ui_ui_i8_add_C_fail_no_repr(i8 noundef %x_in) {
; CHECK-LABEL: @test_ui_ui_i8_add_C_fail_no_repr(
; CHECK-NEXT: [[X:%.*]] = and i8 [[X_IN:%.*]], 127
; CHECK-NEXT: [[XF:%.*]] = uitofp nneg i8 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 0xH57F8
+; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 1.275000e+02
; CHECK-NEXT: ret half [[R]]
;
%x = and i8 %x_in, 127
@@ -63,7 +63,7 @@ define half @test_ui_ui_i8_add_C_fail_overflow(i8 noundef %x_in) {
; CHECK-LABEL: @test_ui_ui_i8_add_C_fail_overflow(
; CHECK-NEXT: [[X:%.*]] = and i8 [[X_IN:%.*]], 127
; CHECK-NEXT: [[XF:%.*]] = uitofp nneg i8 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 0xH5808
+; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 1.290000e+02
; CHECK-NEXT: ret half [[R]]
;
%x = and i8 %x_in, 127
@@ -284,7 +284,7 @@ define half @test_ui_ui_i8_mul_C_fail_overlow(i8 noundef %x_in) {
; CHECK-LABEL: @test_ui_ui_i8_mul_C_fail_overlow(
; CHECK-NEXT: [[X:%.*]] = and i8 [[X_IN:%.*]], 14
; CHECK-NEXT: [[XF:%.*]] = uitofp nneg i8 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 0xH4CC0
+; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 1.900000e+01
; CHECK-NEXT: ret half [[R]]
;
%x = and i8 %x_in, 14
@@ -333,7 +333,7 @@ define half @test_si_si_i8_mul_C_fail_no_repr(i8 noundef %x_in) {
; CHECK-NEXT: [[XX:%.*]] = and i8 [[X_IN:%.*]], 6
; CHECK-NEXT: [[X:%.*]] = or disjoint i8 [[XX]], 1
; CHECK-NEXT: [[XF:%.*]] = uitofp nneg i8 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 0xHC780
+; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], -7.500000e+00
; CHECK-NEXT: ret half [[R]]
;
%xx = and i8 %x_in, 6
@@ -348,7 +348,7 @@ define half @test_si_si_i8_mul_C_fail_overflow(i8 noundef %x_in) {
; CHECK-NEXT: [[XX:%.*]] = and i8 [[X_IN:%.*]], 6
; CHECK-NEXT: [[X:%.*]] = or disjoint i8 [[XX]], 1
; CHECK-NEXT: [[XF:%.*]] = uitofp nneg i8 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 0xHCCC0
+; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], -1.900000e+01
; CHECK-NEXT: ret half [[R]]
;
%xx = and i8 %x_in, 6
@@ -464,7 +464,7 @@ define half @test_ui_ui_i16_add_C_fail_overflow(i16 noundef %x_in) {
; CHECK-LABEL: @test_ui_ui_i16_add_C_fail_overflow(
; CHECK-NEXT: [[X:%.*]] = and i16 [[X_IN:%.*]], 2047
; CHECK-NEXT: [[XF:%.*]] = uitofp nneg i16 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 0xH7BD0
+; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 6.400000e+04
; CHECK-NEXT: ret half [[R]]
;
%x = and i16 %x_in, 2047
@@ -512,7 +512,7 @@ define half @test_si_si_i16_add_C_overflow(i16 noundef %x_in) {
; CHECK-LABEL: @test_si_si_i16_add_C_overflow(
; CHECK-NEXT: [[X:%.*]] = or i16 [[X_IN:%.*]], -2048
; CHECK-NEXT: [[XF:%.*]] = sitofp i16 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 0xH7840
+; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 3.481600e+04
; CHECK-NEXT: ret half [[R]]
;
%x = or i16 %x_in, -2048
@@ -661,7 +661,7 @@ define half @test_si_si_i16_mul_C_fail_overflow(i16 noundef %x_in) {
; CHECK-LABEL: @test_si_si_i16_mul_C_fail_overflow(
; CHECK-NEXT: [[X:%.*]] = or i16 [[X_IN:%.*]], -129
; CHECK-NEXT: [[XF:%.*]] = sitofp i16 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 0xH5800
+; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 1.280000e+02
; CHECK-NEXT: ret half [[R]]
;
%x = or i16 %x_in, -129
@@ -674,7 +674,7 @@ define half @test_si_si_i16_mul_C_fail_no_promotion(i16 noundef %x_in) {
; CHECK-LABEL: @test_si_si_i16_mul_C_fail_no_promotion(
; CHECK-NEXT: [[X:%.*]] = or i16 [[X_IN:%.*]], -4097
; CHECK-NEXT: [[XF:%.*]] = sitofp i16 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 0xH4500
+; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 5.000000e+00
; CHECK-NEXT: ret half [[R]]
;
%x = or i16 %x_in, -4097
@@ -774,7 +774,7 @@ define half @test_si_si_i12_add_C_fail_overflow(i12 noundef %x_in) {
; CHECK-LABEL: @test_si_si_i12_add_C_fail_overflow(
; CHECK-NEXT: [[X:%.*]] = or i12 [[X_IN:%.*]], -2048
; CHECK-NEXT: [[XF:%.*]] = sitofp i12 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], 0xHBC00
+; CHECK-NEXT: [[R:%.*]] = fadd half [[XF]], -1.000000e+00
; CHECK-NEXT: ret half [[R]]
;
%x = or i12 %x_in, -2048
@@ -963,7 +963,7 @@ define half @test_si_si_i12_mul_C_fail_overflow(i12 noundef %x_in) {
; CHECK-LABEL: @test_si_si_i12_mul_C_fail_overflow(
; CHECK-NEXT: [[X:%.*]] = or i12 [[X_IN:%.*]], -64
; CHECK-NEXT: [[XF:%.*]] = sitofp i12 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], 0xHD400
+; CHECK-NEXT: [[R:%.*]] = fmul nnan half [[XF]], -6.400000e+01
; CHECK-NEXT: ret half [[R]]
;
%x = or i12 %x_in, -64
diff --git a/llvm/test/Transforms/InstCombine/binop-select.ll b/llvm/test/Transforms/InstCombine/binop-select.ll
index 8670a154a8bd3..3265ea54a831e 100644
--- a/llvm/test/Transforms/InstCombine/binop-select.ll
+++ b/llvm/test/Transforms/InstCombine/binop-select.ll
@@ -335,7 +335,7 @@ define i32 @sub_sel_op1_use(i1 %b) {
define float @fadd_sel_op0(i1 %b, float %x) {
; CHECK-LABEL: @fadd_sel_op0(
-; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], float 0xFFF0000000000000, float 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], float -inf, float +inf
; CHECK-NEXT: ret float [[R]]
;
%s = select i1 %b, float 0xFFF0000000000000, float 0x7FF0000000000000
@@ -345,7 +345,7 @@ define float @fadd_sel_op0(i1 %b, float %x) {
define float @fadd_sel_op0_use(i1 %b, float %x) {
; CHECK-LABEL: @fadd_sel_op0_use(
-; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], float 0xFFF0000000000000, float 0x7FF0000000000000
+; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], float -inf, float +inf
; CHECK-NEXT: call void @use_f32(float [[S]])
; CHECK-NEXT: [[R:%.*]] = fadd nnan float [[S]], [[X:%.*]]
; CHECK-NEXT: ret float [[R]]
@@ -368,7 +368,7 @@ define <2 x half> @fmul_sel_op1(i1 %b, <2 x half> %p) {
define <2 x half> @fmul_sel_op1_use(i1 %b, <2 x half> %p) {
; CHECK-LABEL: @fmul_sel_op1_use(
-; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], <2 x half> zeroinitializer, <2 x half> splat (half 0xHFFFF)
+; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], <2 x half> zeroinitializer, <2 x half> splat (half -nan(0x1FF))
; CHECK-NEXT: call void @use_v2f16(<2 x half> [[S]])
; CHECK-NEXT: ret <2 x half> zeroinitializer
;
diff --git a/llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll b/llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll
index 49e77009f3b1a..0c24d0ea962b7 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll
@@ -491,10 +491,10 @@ define void @constant_fold_vector_to_double() {
; CHECK-NEXT: store volatile double 1.000000e+00, ptr undef, align 8
; CHECK-NEXT: store volatile double 1.000000e+00, ptr undef, align 8
; CHECK-NEXT: store volatile double 1.000000e+00, ptr undef, align 8
-; CHECK-NEXT: store volatile double 0xFFFFFFFFFFFFFFFF, ptr undef, align 8
-; CHECK-NEXT: store volatile double 0x162E000004D2, ptr undef, align 8
+; CHECK-NEXT: store volatile double -nan(0x7FFFFFFFFFFFF), ptr undef, align 8
+; CHECK-NEXT: store volatile double f0x0000162E000004D2, ptr undef, align 8
; CHECK-NEXT: store volatile double bitcast (<2 x i32> <i32 1234, i32 ptrtoint (ptr @g to i32)> to double), ptr undef, align 8
-; CHECK-NEXT: store volatile double 0x400000003F800000, ptr undef, align 8
+; CHECK-NEXT: store volatile double f0x400000003F800000, ptr undef, align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr undef, align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr undef, align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr undef, align 8
@@ -541,8 +541,8 @@ define void @constant_fold_vector_to_float() {
define void @constant_fold_vector_to_half() {
; CHECK-LABEL: @constant_fold_vector_to_half(
-; CHECK-NEXT: store volatile half 0xH4000, ptr undef, align 2
-; CHECK-NEXT: store volatile half 0xH4000, ptr undef, align 2
+; CHECK-NEXT: store volatile half 2.000000e+00, ptr undef, align 2
+; CHECK-NEXT: store volatile half 2.000000e+00, ptr undef, align 2
; CHECK-NEXT: ret void
;
store volatile half bitcast (<2 x i8> <i8 0, i8 64> to half), ptr undef
diff --git a/llvm/test/Transforms/InstCombine/bitcast-select-const-vector.ll b/llvm/test/Transforms/InstCombine/bitcast-select-const-vector.ll
index 88dc5558a23f7..4d86575369033 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-select-const-vector.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-select-const-vector.ll
@@ -4,9 +4,9 @@
define double @bitcast_v2i32_select_to_double_const_rhs(double %i, <2 x i32> %i41) {
; CHECK-LABEL: define double @bitcast_v2i32_select_to_double_const_rhs(
; CHECK-SAME: double [[I:%.*]], <2 x i32> [[I41:%.*]]) {
-; CHECK-NEXT: [[I42:%.*]] = fcmp one double [[I]], 0x7FF0000000000000
+; CHECK-NEXT: [[I42:%.*]] = fcmp one double [[I]], +inf
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[I41]] to double
-; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[I42]], double [[TMP1]], double 0x7FF8000000000000
+; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[I42]], double [[TMP1]], double +qnan
; CHECK-NEXT: ret double [[ASTYPE13_I_I]]
;
%i42 = fcmp one double %i, 0x7FF0000000000000
@@ -18,9 +18,9 @@ define double @bitcast_v2i32_select_to_double_const_rhs(double %i, <2 x i32> %i4
define double @bitcast_v2i32_select_to_double_const_lhs(double %i, <2 x i32> %i41) {
; CHECK-LABEL: define double @bitcast_v2i32_select_to_double_const_lhs(
; CHECK-SAME: double [[I:%.*]], <2 x i32> [[I41:%.*]]) {
-; CHECK-NEXT: [[I42:%.*]] = fcmp one double [[I]], 0x7FF0000000000000
+; CHECK-NEXT: [[I42:%.*]] = fcmp one double [[I]], +inf
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[I41]] to double
-; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[I42]], double 0x7FF8000000000000, double [[TMP1]]
+; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[I42]], double +qnan, double [[TMP1]]
; CHECK-NEXT: ret double [[ASTYPE13_I_I]]
;
%i42 = fcmp one double %i, 0x7FF0000000000000
@@ -61,7 +61,7 @@ define <2 x i32> @bitcast_select_double_to_v2i32_const_lhs(i64 %i, double %i41)
define double @bitcast_v2i32_vselect_to_double_const_rhs(<2 x double> %cmp.vec, <2 x i32> %val) {
; CHECK-LABEL: define double @bitcast_v2i32_vselect_to_double_const_rhs(
; CHECK-SAME: <2 x double> [[CMP_VEC:%.*]], <2 x i32> [[VAL:%.*]]) {
-; CHECK-NEXT: [[VCMP:%.*]] = fcmp one <2 x double> [[CMP_VEC]], splat (double 0x7FF0000000000000)
+; CHECK-NEXT: [[VCMP:%.*]] = fcmp one <2 x double> [[CMP_VEC]], splat (double +inf)
; CHECK-NEXT: [[S_0_I_I:%.*]] = select <2 x i1> [[VCMP]], <2 x i32> [[VAL]], <2 x i32> <i32 0, i32 2146959360>
; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = bitcast <2 x i32> [[S_0_I_I]] to double
; CHECK-NEXT: ret double [[ASTYPE13_I_I]]
@@ -75,9 +75,9 @@ define double @bitcast_v2i32_vselect_to_double_const_rhs(<2 x double> %cmp.vec,
define <2 x float> @bitcast_v4i16_select_to_v2f32_const_lhs(double %arg, <4 x i16> %vec.v4i16) {
; CHECK-LABEL: define <2 x float> @bitcast_v4i16_select_to_v2f32_const_lhs(
; CHECK-SAME: double [[ARG:%.*]], <4 x i16> [[VEC_V4I16:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one double [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one double [[ARG]], +inf
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VEC_V4I16]] to <2 x float>
-; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[CMP]], <2 x float> <float 0x4372A00000000000, float 0xB8B744E1E0000000>, <2 x float> [[TMP1]]
+; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[CMP]], <2 x float> <float f0x5B950000, float f0x85BA270F>, <2 x float> [[TMP1]]
; CHECK-NEXT: ret <2 x float> [[ASTYPE13_I_I]]
;
%cmp = fcmp one double %arg, 0x7FF0000000000000
@@ -89,9 +89,9 @@ define <2 x float> @bitcast_v4i16_select_to_v2f32_const_lhs(double %arg, <4 x i1
define <2 x float> @bitcast_v4i16_select_to_v2f32_const_rhs(double %arg, <4 x i16> %vec.v4i16) {
; CHECK-LABEL: define <2 x float> @bitcast_v4i16_select_to_v2f32_const_rhs(
; CHECK-SAME: double [[ARG:%.*]], <4 x i16> [[VEC_V4I16:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one double [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one double [[ARG]], +inf
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VEC_V4I16]] to <2 x float>
-; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[CMP]], <2 x float> [[TMP1]], <2 x float> <float 0x4372A00000000000, float 0xB8B744E1E0000000>
+; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[CMP]], <2 x float> [[TMP1]], <2 x float> <float f0x5B950000, float f0x85BA270F>
; CHECK-NEXT: ret <2 x float> [[ASTYPE13_I_I]]
;
%cmp = fcmp one double %arg, 0x7FF0000000000000
@@ -103,9 +103,9 @@ define <2 x float> @bitcast_v4i16_select_to_v2f32_const_rhs(double %arg, <4 x i1
define <2 x float> @bitcast_v2i32_select_to_v2f32_const_rhs(double %arg, <2 x i32> %vec) {
; CHECK-LABEL: define <2 x float> @bitcast_v2i32_select_to_v2f32_const_rhs(
; CHECK-SAME: double [[ARG:%.*]], <2 x i32> [[VEC:%.*]]) {
-; CHECK-NEXT: [[I42:%.*]] = fcmp one double [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[I42:%.*]] = fcmp one double [[ARG]], +inf
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VEC]] to <2 x float>
-; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[I42]], <2 x float> [[TMP1]], <2 x float> <float 0.000000e+00, float 0x7FFF000000000000>
+; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[I42]], <2 x float> [[TMP1]], <2 x float> <float 0.000000e+00, float +nan(0x380000)>
; CHECK-NEXT: ret <2 x float> [[ASTYPE13_I_I]]
;
%cmp = fcmp one double %arg, 0x7FF0000000000000
@@ -117,9 +117,9 @@ define <2 x float> @bitcast_v2i32_select_to_v2f32_const_rhs(double %arg, <2 x i3
define <2 x float> @bitcast_v2i32_select_to_v2f32_const_lhs(double %arg, <2 x i32> %vec) {
; CHECK-LABEL: define <2 x float> @bitcast_v2i32_select_to_v2f32_const_lhs(
; CHECK-SAME: double [[ARG:%.*]], <2 x i32> [[VEC:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one double [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one double [[ARG]], +inf
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VEC]] to <2 x float>
-; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[CMP]], <2 x float> <float 0.000000e+00, float 0x7FFF000000000000>, <2 x float> [[TMP1]]
+; CHECK-NEXT: [[ASTYPE13_I_I:%.*]] = select i1 [[CMP]], <2 x float> <float 0.000000e+00, float +nan(0x380000)>, <2 x float> [[TMP1]]
; CHECK-NEXT: ret <2 x float> [[ASTYPE13_I_I]]
;
%cmp = fcmp one double %arg, 0x7FF0000000000000
diff --git a/llvm/test/Transforms/InstCombine/bitcast.ll b/llvm/test/Transforms/InstCombine/bitcast.ll
index 37d41de3e9991..d4c14c442190a 100644
--- a/llvm/test/Transforms/InstCombine/bitcast.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast.ll
@@ -618,10 +618,10 @@ define void @constant_fold_vector_to_double() {
; CHECK-NEXT: store volatile double 1.000000e+00, ptr undef, align 8
; CHECK-NEXT: store volatile double 1.000000e+00, ptr undef, align 8
; CHECK-NEXT: store volatile double 1.000000e+00, ptr undef, align 8
-; CHECK-NEXT: store volatile double 0xFFFFFFFFFFFFFFFF, ptr undef, align 8
-; CHECK-NEXT: store volatile double 0x162E000004D2, ptr undef, align 8
+; CHECK-NEXT: store volatile double -nan(0x7FFFFFFFFFFFF), ptr undef, align 8
+; CHECK-NEXT: store volatile double f0x0000162E000004D2, ptr undef, align 8
; CHECK-NEXT: store volatile double bitcast (<2 x i32> <i32 1234, i32 ptrtoint (ptr @g to i32)> to double), ptr undef, align 8
-; CHECK-NEXT: store volatile double 0x400000003F800000, ptr undef, align 8
+; CHECK-NEXT: store volatile double f0x400000003F800000, ptr undef, align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr undef, align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr undef, align 8
; CHECK-NEXT: store volatile double 0.000000e+00, ptr undef, align 8
@@ -668,8 +668,8 @@ define void @constant_fold_vector_to_float() {
define void @constant_fold_vector_to_half() {
; CHECK-LABEL: @constant_fold_vector_to_half(
-; CHECK-NEXT: store volatile half 0xH4000, ptr undef, align 2
-; CHECK-NEXT: store volatile half 0xH4000, ptr undef, align 2
+; CHECK-NEXT: store volatile half 2.000000e+00, ptr undef, align 2
+; CHECK-NEXT: store volatile half 2.000000e+00, ptr undef, align 2
; CHECK-NEXT: ret void
;
store volatile half bitcast (<2 x i8> <i8 0, i8 64> to half), ptr undef
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-const-to-bop.ll b/llvm/test/Transforms/InstCombine/canonicalize-const-to-bop.ll
index f0e40f4ede161..6c72147fb8bfe 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-const-to-bop.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-const-to-bop.ll
@@ -293,9 +293,9 @@ define i8 @multi_use_bop_negative(i8 %x) {
define half @float_negative(half %x) {
; CHECK-LABEL: define half @float_negative(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[ADD:%.*]] = fmul fast half [[X]], 0xH2E66
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt half [[X]], 0xH5640
-; CHECK-NEXT: [[S:%.*]] = select i1 [[CMP]], half 0xH4900, half [[ADD]]
+; CHECK-NEXT: [[ADD:%.*]] = fmul fast half [[X]], 9.997550e-02
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt half [[X]], 1.000000e+02
+; CHECK-NEXT: [[S:%.*]] = select i1 [[CMP]], half 1.000000e+01, half [[ADD]]
; CHECK-NEXT: ret half [[S]]
;
%add = fdiv fast half %x, 10.0
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-fcmp-inf.ll b/llvm/test/Transforms/InstCombine/canonicalize-fcmp-inf.ll
index a85d7932f9b7e..adfe17fd3f692 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-fcmp-inf.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-fcmp-inf.ll
@@ -4,7 +4,7 @@
define i1 @olt_pinf(half %x) {
; CHECK-LABEL: define i1 @olt_pinf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one half [[X]], 0xH7C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one half [[X]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp olt half %x, 0xH7c00
@@ -14,7 +14,7 @@ define i1 @olt_pinf(half %x) {
define i1 @ole_pinf(half %x) {
; CHECK-LABEL: define i1 @ole_pinf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ole half %x, 0xH7c00
@@ -33,7 +33,7 @@ define i1 @ogt_pinf(half %x) {
define i1 @oge_pinf(half %x) {
; CHECK-LABEL: define i1 @oge_pinf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X]], 0xH7C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp oge half %x, 0xH7c00
@@ -43,7 +43,7 @@ define i1 @oge_pinf(half %x) {
define i1 @ult_pinf(half %x) {
; CHECK-LABEL: define i1 @ult_pinf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une half [[X]], 0xH7C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une half [[X]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ult half %x, 0xH7c00
@@ -62,7 +62,7 @@ define i1 @ule_pinf(half %x) {
define i1 @ugt_pinf(half %x) {
; CHECK-LABEL: define i1 @ugt_pinf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ugt half %x, 0xH7c00
@@ -72,7 +72,7 @@ define i1 @ugt_pinf(half %x) {
define i1 @uge_pinf(half %x) {
; CHECK-LABEL: define i1 @uge_pinf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[X]], 0xH7C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[X]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp uge half %x, 0xH7c00
@@ -91,7 +91,7 @@ define i1 @olt_ninf(half %x) {
define i1 @ole_ninf(half %x) {
; CHECK-LABEL: define i1 @ole_ninf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X]], 0xHFC00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ole half %x, 0xHfc00
@@ -101,7 +101,7 @@ define i1 @ole_ninf(half %x) {
define i1 @ogt_ninf(half %x) {
; CHECK-LABEL: define i1 @ogt_ninf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one half [[X]], 0xHFC00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one half [[X]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ogt half %x, 0xHfc00
@@ -111,7 +111,7 @@ define i1 @ogt_ninf(half %x) {
define i1 @oge_ninf(half %x) {
; CHECK-LABEL: define i1 @oge_ninf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp oge half %x, 0xHfc00
@@ -121,7 +121,7 @@ define i1 @oge_ninf(half %x) {
define i1 @ult_ninf(half %x) {
; CHECK-LABEL: define i1 @ult_ninf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ult half %x, 0xHfc00
@@ -131,7 +131,7 @@ define i1 @ult_ninf(half %x) {
define i1 @ule_ninf(half %x) {
; CHECK-LABEL: define i1 @ule_ninf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[X]], 0xHFC00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[X]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ule half %x, 0xHfc00
@@ -141,7 +141,7 @@ define i1 @ule_ninf(half %x) {
define i1 @ugt_ninf(half %x) {
; CHECK-LABEL: define i1 @ugt_ninf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une half [[X]], 0xHFC00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une half [[X]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ugt half %x, 0xHfc00
@@ -160,7 +160,7 @@ define i1 @uge_ninf(half %x) {
define i1 @olt_pinf_fmf(half %x) {
; CHECK-LABEL: define i1 @olt_pinf_fmf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp nsz one half [[X]], 0xH7C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nsz one half [[X]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp nsz olt half %x, 0xH7c00
@@ -170,7 +170,7 @@ define i1 @olt_pinf_fmf(half %x) {
define i1 @oge_pinf_fmf(half %x) {
; CHECK-LABEL: define i1 @oge_pinf_fmf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq half [[X]], 0xH7C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq half [[X]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp nnan oge half %x, 0xH7c00
@@ -180,7 +180,7 @@ define i1 @oge_pinf_fmf(half %x) {
define <2 x i1> @olt_pinf_vec(<2 x half> %x) {
; CHECK-LABEL: define <2 x i1> @olt_pinf_vec(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one <2 x half> [[X]], splat (half 0xH7C00)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one <2 x half> [[X]], splat (half +inf)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%cmp = fcmp olt <2 x half> %x, <half 0xH7c00, half 0xH7c00>
@@ -202,7 +202,7 @@ define <2 x i1> @oge_ninf_vec(<2 x half> %x) {
define i1 @ord_pinf(half %x) {
; CHECK-LABEL: define i1 @ord_pinf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ord half %x, 0xH7c00
@@ -212,7 +212,7 @@ define i1 @ord_pinf(half %x) {
define i1 @uno_pinf(half %x) {
; CHECK-LABEL: define i1 @uno_pinf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp uno half %x, 0xH7c00
@@ -240,7 +240,7 @@ define i1 @false_pinf(half %x) {
define i1 @ord_ninf(half %x) {
; CHECK-LABEL: define i1 @ord_ninf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp ord half %x, 0xHfc00
@@ -250,7 +250,7 @@ define i1 @ord_ninf(half %x) {
define i1 @uno_ninf(half %x) {
; CHECK-LABEL: define i1 @uno_ninf(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp uno half %x, 0xHfc00
@@ -278,7 +278,7 @@ define i1 @false_ninf(half %x) {
define i1 @olt_one(half %x) {
; CHECK-LABEL: define i1 @olt_one(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt half [[X]], 0xH3C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt half [[X]], 1.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp olt half %x, 1.0
diff --git a/llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll b/llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll
index dfefa11b70a02..daf48a6949a42 100644
--- a/llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll
+++ b/llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll
@@ -274,7 +274,7 @@ define i1 @i64_cast_cmp_oeq_int_0_sitofp_half(i64 %i) {
define i1 @i32_cast_cmp_oeq_int_0_uitofp_ppcf128(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_0_uitofp_ppcf128(
; CHECK-NEXT: [[F:%.*]] = uitofp i32 [[I:%.*]] to ppc_fp128
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq ppc_fp128 [[F]], 0xM00000000000000000000000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq ppc_fp128 [[F]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i32 %i to ppc_fp128
@@ -314,7 +314,7 @@ define i1 @i32_cast_cmp_oeq_int_i24max_sitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i24maxp1_uitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i24maxp1_uitofp(
; CHECK-NEXT: [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], 0x4170000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4B800000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i32 %i to float
@@ -326,7 +326,7 @@ define i1 @i32_cast_cmp_oeq_int_i24maxp1_uitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i24maxp1_sitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i24maxp1_sitofp(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], 0x4170000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4B800000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %i to float
@@ -337,7 +337,7 @@ define i1 @i32_cast_cmp_oeq_int_i24maxp1_sitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i32umax_uitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32umax_uitofp(
; CHECK-NEXT: [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], 0x41F0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4F800000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i32 %i to float
@@ -368,7 +368,7 @@ define i1 @i32_cast_cmp_oeq_int_i32umax_sitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i32imin_sitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imin_sitofp(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], 0xC1E0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0xCF000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %i to float
@@ -379,7 +379,7 @@ define i1 @i32_cast_cmp_oeq_int_i32imin_sitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i32imax_uitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imax_uitofp(
; CHECK-NEXT: [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], 0x41E0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4F000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i32 %i to float
@@ -390,7 +390,7 @@ define i1 @i32_cast_cmp_oeq_int_i32imax_uitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i32imax_sitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imax_sitofp(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], 0x41E0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4F000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %i to float
@@ -502,7 +502,7 @@ define i1 @i32_cast_cmp_oeq_int_inf_sitofp(i32 %i) {
define i1 @i128_cast_cmp_oeq_int_inf_uitofp(i128 %i) {
; CHECK-LABEL: @i128_cast_cmp_oeq_int_inf_uitofp(
; CHECK-NEXT: [[F:%.*]] = uitofp i128 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i128 %i to float
@@ -533,7 +533,7 @@ define <2 x i1> @i32_vec_cast_cmp_oeq_vec_int_n0_sitofp(<2 x i32> %i) {
define <2 x i1> @i32_vec_cast_cmp_oeq_vec_int_i32imax_sitofp(<2 x i32> %i) {
; CHECK-LABEL: @i32_vec_cast_cmp_oeq_vec_int_i32imax_sitofp(
; CHECK-NEXT: [[F:%.*]] = sitofp <2 x i32> [[I:%.*]] to <2 x float>
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <2 x float> [[F]], splat (float 0x41E0000000000000)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <2 x float> [[F]], splat (float f0x4F000000)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%f = sitofp <2 x i32> %i to <2 x float>
diff --git a/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll b/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
index 9fb3f685a0b9c..5456b09513dd6 100644
--- a/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
@@ -36,7 +36,7 @@ define <2 x i1> @fcmp_oeq_inf_or_class_normal_vector(<2 x half> %x) {
define i1 @fcmp_oeq_inf_multi_use_or_class_normal(half %x, ptr %ptr) {
; CHECK-LABEL: @fcmp_oeq_inf_multi_use_or_class_normal(
-; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: store i1 [[OEQ_INF]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
@@ -51,7 +51,7 @@ define i1 @fcmp_oeq_inf_multi_use_or_class_normal(half %x, ptr %ptr) {
define i1 @fcmp_oeq_inf_or_class_normal_multi_use(half %x, ptr %ptr) {
; CHECK-LABEL: @fcmp_oeq_inf_or_class_normal_multi_use(
-; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
; CHECK-NEXT: store i1 [[CLASS]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
@@ -77,8 +77,8 @@ define i1 @fcmp_ord_or_class_isnan(half %x) {
define i1 @fcmp_ord_or_class_isnan_wrong_operand(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_or_class_isnan_wrong_operand(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp uno half [[Y:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp uno half [[Y:%.*]], 0.000000e+00
; CHECK-NEXT: [[OR:%.*]] = or i1 [[ORD]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -136,7 +136,7 @@ define i1 @fcmp_isfinite_and_class_subnormal(half %x) {
define i1 @fcmp_isfinite_or_class_subnormal(half %x) {
; CHECK-LABEL: @fcmp_isfinite_or_class_subnormal(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[SUBNORMAL_CLASS:%.*]] = fcmp one half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[SUBNORMAL_CLASS:%.*]] = fcmp one half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[SUBNORMAL_CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -150,7 +150,7 @@ define i1 @fcmp_isfinite_or_class_subnormal(half %x) {
define i1 @fcmp_issubnormal_or_class_finite(half %x) {
; CHECK-LABEL: @fcmp_issubnormal_or_class_finite(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp one half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[OR:%.*]] = fcmp one half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -164,7 +164,7 @@ define i1 @fcmp_issubnormal_or_class_finite(half %x) {
define i1 @class_finite_or_fcmp_issubnormal(half %x) {
; CHECK-LABEL: @class_finite_or_fcmp_issubnormal(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp one half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[OR:%.*]] = fcmp one half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -203,7 +203,7 @@ define i1 @class_inf_or_fcmp_issubnormal(half %x) {
define <2 x i1> @class_finite_or_fcmp_issubnormal_vector(<2 x half> %x) {
; CHECK-LABEL: @class_finite_or_fcmp_issubnormal_vector(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp one <2 x half> [[TMP1]], splat (half 0xH7C00)
+; CHECK-NEXT: [[OR:%.*]] = fcmp one <2 x half> [[TMP1]], splat (half +inf)
; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
@@ -226,7 +226,7 @@ define i1 @fcmp_oeq_zero_or_class_normal(half %x) {
define i1 @fcmp_oeq_zero_or_class_normal_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal_daz(
-; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
@@ -252,7 +252,7 @@ define <2 x i1> @fcmp_oeq_zero_or_class_normal_daz_v2f16(<2 x half> %x) #1 {
define i1 @fcmp_oeq_zero_or_class_normal_dynamic(half %x) #2 {
; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal_dynamic(
-; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
@@ -311,7 +311,7 @@ define i1 @class_normal_or_fcmp_ueq_zero(half %x) {
define i1 @fcmp_one_zero_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_one_zero_or_class_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%one.inf = fcmp one half %x, 0.0
@@ -322,7 +322,7 @@ define i1 @fcmp_one_zero_or_class_normal(half %x) {
define i1 @fcmp_one_zero_or_class_normal_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_one_zero_or_class_normal_daz(
-; CHECK-NEXT: [[ONE_INF:%.*]] = fcmp one half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ONE_INF:%.*]] = fcmp one half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[ONE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
@@ -335,7 +335,7 @@ define i1 @fcmp_one_zero_or_class_normal_daz(half %x) #1 {
define i1 @fcmp_one_zero_or_class_normal_dynamic(half %x) #2 {
; CHECK-LABEL: @fcmp_one_zero_or_class_normal_dynamic(
-; CHECK-NEXT: [[ONE_INF:%.*]] = fcmp one half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ONE_INF:%.*]] = fcmp one half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[ONE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
@@ -348,7 +348,7 @@ define i1 @fcmp_one_zero_or_class_normal_dynamic(half %x) #2 {
define i1 @class_normal_or_fcmp_one_zero(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_one_zero(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%one.inf = fcmp one half %x, 0.0
@@ -359,7 +359,7 @@ define i1 @class_normal_or_fcmp_one_zero(half %x) {
define i1 @fcmp_une_zero_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_une_zero_or_class_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%une.inf = fcmp une half %x, 0.0
@@ -370,7 +370,7 @@ define i1 @fcmp_une_zero_or_class_normal(half %x) {
define i1 @class_normal_or_fcmp_une_zero(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_une_zero(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%une.inf = fcmp une half %x, 0.0
@@ -381,7 +381,7 @@ define i1 @class_normal_or_fcmp_une_zero(half %x) {
define i1 @class_normal_or_fcmp_une_zero_daz(half %x) #1 {
; CHECK-LABEL: @class_normal_or_fcmp_une_zero_daz(
-; CHECK-NEXT: [[UNE_INF:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[UNE_INF:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[UNE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
@@ -394,7 +394,7 @@ define i1 @class_normal_or_fcmp_une_zero_daz(half %x) #1 {
define i1 @class_normal_or_fcmp_une_zero_dynamic(half %x) #2 {
; CHECK-LABEL: @class_normal_or_fcmp_une_zero_dynamic(
-; CHECK-NEXT: [[UNE_INF:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[UNE_INF:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[UNE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
diff --git a/llvm/test/Transforms/InstCombine/constant-fold-libfunc.ll b/llvm/test/Transforms/InstCombine/constant-fold-libfunc.ll
index 474d7b8849890..241cbb9287420 100644
--- a/llvm/test/Transforms/InstCombine/constant-fold-libfunc.ll
+++ b/llvm/test/Transforms/InstCombine/constant-fold-libfunc.ll
@@ -8,7 +8,7 @@ define double @test_simplify_acos() {
; CHECK-LABEL: @test_simplify_acos
%pi = call double @acos(double -1.000000e+00)
; CHECK-NOT: call double @acos
-; CHECK: ret double 0x400921FB54442D18
+; CHECK: ret double f0x400921FB54442D18
ret double %pi
}
diff --git a/llvm/test/Transforms/InstCombine/constant-fold-math.ll b/llvm/test/Transforms/InstCombine/constant-fold-math.ll
index fc3f1d59d6492..74ad1e496bd5e 100644
--- a/llvm/test/Transforms/InstCombine/constant-fold-math.ll
+++ b/llvm/test/Transforms/InstCombine/constant-fold-math.ll
@@ -48,7 +48,7 @@ define double @constant_fold_fmuladd_f64() #0 {
; PR32177
; CHECK-LABEL: @constant_fold_frem_f32
-; CHECK-NEXT: ret float 0x41A61B2000000000
+; CHECK-NEXT: ret float f0x4D30D900
define float @constant_fold_frem_f32() #0 {
%x = frem float 0x43cbfcd960000000, 0xc1e2b34a00000000
ret float %x
diff --git a/llvm/test/Transforms/InstCombine/constant-fold-nextafter.ll b/llvm/test/Transforms/InstCombine/constant-fold-nextafter.ll
index cab56c27deac3..5205856557c23 100644
--- a/llvm/test/Transforms/InstCombine/constant-fold-nextafter.ll
+++ b/llvm/test/Transforms/InstCombine/constant-fold-nextafter.ll
@@ -23,7 +23,7 @@
define double @nextafter_up_direction() {
; CHECK-LABEL: define double @nextafter_up_direction() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%next = call double @nextafter(double 1.0, double 2.0)
ret double %next
@@ -31,7 +31,7 @@ define double @nextafter_up_direction() {
define float @nextafterf_up_direction() {
; CHECK-LABEL: define float @nextafterf_up_direction() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%next = call float @nextafterf(float 1.0, float 2.0)
ret float %next
@@ -39,7 +39,7 @@ define float @nextafterf_up_direction() {
define double @nextafter_down_direction() {
; CHECK-LABEL: define double @nextafter_down_direction() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%next = call double @nextafter(double 1.0, double 0.0)
ret double %next
@@ -47,7 +47,7 @@ define double @nextafter_down_direction() {
define float @nextafterf_down_direction() {
; CHECK-LABEL: define float @nextafterf_down_direction() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%next = call float @nextafterf(float 1.0, float 0.0)
ret float %next
@@ -103,7 +103,7 @@ define float @nextafterf_neg_zero_pos_zero() {
define double @nextafter_nan_with_payload() {
; CHECK-LABEL: define double @nextafter_nan_with_payload() {
-; CHECK-NEXT: ret double 0x7FF8000000000001
+; CHECK-NEXT: ret double +nan(0x1)
;
%tmp1 = load i64, ptr @dbl_nan
%tmp2 = or i64 %tmp1, 1
@@ -114,7 +114,7 @@ define double @nextafter_nan_with_payload() {
define double @nextafter_nan_with_payload_2() {
; CHECK-LABEL: define double @nextafter_nan_with_payload_2() {
-; CHECK-NEXT: ret double 0x7FF8000000000001
+; CHECK-NEXT: ret double +nan(0x1)
;
%tmp1 = load i64, ptr @dbl_nan
%tmp2 = or i64 %tmp1, 1
@@ -125,7 +125,7 @@ define double @nextafter_nan_with_payload_2() {
define double @nextafter_snan() {
; CHECK-LABEL: define double @nextafter_snan() {
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%arg1 = load double, ptr @dbl_snan
%next = call double @nextafter(double %arg1, double 1.0)
@@ -134,7 +134,7 @@ define double @nextafter_snan() {
define double @nextafter_snan_2() {
; CHECK-LABEL: define double @nextafter_snan_2() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nextafter(double 1.000000e+00, double 0x7FF0000000000001)
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nextafter(double 1.000000e+00, double +snan(0x1))
; CHECK-NEXT: ret double [[NEXT]]
;
%arg2 = load double, ptr @dbl_snan
@@ -144,7 +144,7 @@ define double @nextafter_snan_2() {
define float @nextafterf_nan_with_payload() {
; CHECK-LABEL: define float @nextafterf_nan_with_payload() {
-; CHECK-NEXT: ret float 0x7FF8000020000000
+; CHECK-NEXT: ret float +nan(0x1)
;
%tmp1 = load i32, ptr @flt_nan
%tmp2 = or i32 %tmp1, 1
@@ -155,7 +155,7 @@ define float @nextafterf_nan_with_payload() {
define double @nextafter_pos_overflow () {
; CHECK-LABEL: define double @nextafter_pos_overflow() {
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%arg1 = load double, ptr @dbl_pos_max
%arg2 = load double, ptr @dbl_pos_infinity
@@ -165,7 +165,7 @@ define double @nextafter_pos_overflow () {
define float @nextafterf_pos_overflow() {
; CHECK-LABEL: define float @nextafterf_pos_overflow() {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%arg1 = load float, ptr @flt_pos_max
%arg2 = load float, ptr @flt_pos_infinity
@@ -175,7 +175,7 @@ define float @nextafterf_pos_overflow() {
define double @nextafter_neg_overflow() {
; CHECK-LABEL: define double @nextafter_neg_overflow() {
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%arg1 = load double, ptr @dbl_neg_max
%arg2 = load double, ptr @dbl_neg_infinity
@@ -185,7 +185,7 @@ define double @nextafter_neg_overflow() {
define float @nextafterf_neg_overflow() {
; CHECK-LABEL: define float @nextafterf_neg_overflow() {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%arg1 = load float, ptr @flt_neg_max
%arg2 = load float, ptr @flt_neg_infinity
@@ -205,7 +205,7 @@ define double @nextafter_zero_from_above() {
define float @nextafterf_zero_from_above() {
; CHECK-LABEL: define float @nextafterf_zero_from_above() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nextafterf(float 0x36A0000000000000, float 0.000000e+00)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nextafterf(float 1.401300e-45, float 0.000000e+00)
; CHECK-NEXT: ret float [[NEXT]]
;
%arg = load float, ptr @flt_pos_min_subnormal
@@ -225,7 +225,7 @@ define double @nextafter_zero_from_below() {
define float @nextafterf_zero_from_below() {
; CHECK-LABEL: define float @nextafterf_zero_from_below() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nextafterf(float 0xB6A0000000000000, float 0.000000e+00)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nextafterf(float -1.401300e-45, float 0.000000e+00)
; CHECK-NEXT: ret float [[NEXT]]
;
%arg = load float, ptr @flt_neg_min_subnormal
@@ -235,7 +235,7 @@ define float @nextafterf_zero_from_below() {
define double @nextafter_subnormal() {
; CHECK-LABEL: define double @nextafter_subnormal() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nextafter(double 4.940660e-324, double 0x7FF0000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nextafter(double 4.940660e-324, double +inf)
; CHECK-NEXT: ret double [[NEXT]]
;
%subnormal = load double, ptr @dbl_pos_min_subnormal
@@ -246,7 +246,7 @@ define double @nextafter_subnormal() {
define float @nextafterf_subnormal() {
; CHECK-LABEL: define float @nextafterf_subnormal() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nextafterf(float 0x36A0000000000000, float 0x7FF0000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nextafterf(float 1.401300e-45, float +inf)
; CHECK-NEXT: ret float [[NEXT]]
;
%subnormal = load float, ptr @flt_pos_min_subnormal
@@ -275,7 +275,7 @@ define double @nextafterf_poison() {
define double @nextafter_subnormal_readnone() {
; CHECK-LABEL: define double @nextafter_subnormal_readnone() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nextafter(double 4.940660e-324, double 0x7FF0000000000000) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nextafter(double 4.940660e-324, double +inf) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret double [[NEXT]]
;
%subnormal = load double, ptr @dbl_pos_min_subnormal
@@ -286,7 +286,7 @@ define double @nextafter_subnormal_readnone() {
define float @nextafterf_subnormal_readnone() {
; CHECK-LABEL: define float @nextafterf_subnormal_readnone() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nextafterf(float 0x36A0000000000000, float 0x7FF0000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nextafterf(float 1.401300e-45, float +inf) #[[ATTR1]]
; CHECK-NEXT: ret float [[NEXT]]
;
%subnormal = load float, ptr @flt_pos_min_subnormal
diff --git a/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-fp128.ll b/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-fp128.ll
index 8c2a042fcc317..8244960522322 100644
--- a/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-fp128.ll
+++ b/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-fp128.ll
@@ -22,7 +22,7 @@
define double @nexttoward_up_direction() {
; CHECK-LABEL: define double @nexttoward_up_direction() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%arg = fpext double 2.0 to fp128
%next = call double @nexttoward(double 1.0, fp128 %arg)
@@ -31,7 +31,7 @@ define double @nexttoward_up_direction() {
define float @nexttowardf_up_direction() {
; CHECK-LABEL: define float @nexttowardf_up_direction() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%arg = fpext float 2.0 to fp128
%next = call float @nexttowardf(float 1.0, fp128 %arg)
@@ -40,7 +40,7 @@ define float @nexttowardf_up_direction() {
define double @nexttoward_down_direction() {
; CHECK-LABEL: define double @nexttoward_down_direction() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%arg = fpext double 0.0 to fp128
%next = call double @nexttoward(double 1.0, fp128 %arg)
@@ -49,7 +49,7 @@ define double @nexttoward_down_direction() {
define float @nexttowardf_down_direction() {
; CHECK-LABEL: define float @nexttowardf_down_direction() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%arg = fpext float 0.0 to fp128
%next = call float @nexttowardf(float 1.0, fp128 %arg)
@@ -112,7 +112,7 @@ define float @nexttowardf_neg_zero_pos_zero() {
define double @nexttoward_nan_with_payload() {
; CHECK-LABEL: define double @nexttoward_nan_with_payload() {
-; CHECK-NEXT: ret double 0x7FF8000000000001
+; CHECK-NEXT: ret double +nan(0x1)
;
%tmp1 = load i64, ptr @dbl_nan
%tmp2 = or i64 %tmp1, 1
@@ -124,7 +124,7 @@ define double @nexttoward_nan_with_payload() {
define float @nexttowardf_nan_with_payload() {
; CHECK-LABEL: define float @nexttowardf_nan_with_payload() {
-; CHECK-NEXT: ret float 0x7FF8000020000000
+; CHECK-NEXT: ret float +nan(0x1)
;
%tmp1 = load i32, ptr @flt_nan
%tmp2 = or i32 %tmp1, 1
@@ -136,7 +136,7 @@ define float @nexttowardf_nan_with_payload() {
define double @nexttoward_pos_overflow() {
; CHECK-LABEL: define double @nexttoward_pos_overflow() {
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%pos_max = load double, ptr @dbl_pos_max
%pos_inf = load double, ptr @dbl_pos_infinity
@@ -147,7 +147,7 @@ define double @nexttoward_pos_overflow() {
define float @nexttowardf_pos_overflow () {
; CHECK-LABEL: define float @nexttowardf_pos_overflow() {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pos_max = load float, ptr @flt_pos_max
%pos_inf = load float, ptr @flt_pos_infinity
@@ -158,7 +158,7 @@ define float @nexttowardf_pos_overflow () {
define double @nexttoward_neg_overflow() {
; CHECK-LABEL: define double @nexttoward_neg_overflow() {
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%neg_max = load double, ptr @dbl_neg_max
%neg_inf = load double, ptr @dbl_neg_infinity
@@ -169,7 +169,7 @@ define double @nexttoward_neg_overflow() {
define float @nexttowardf_neg_overflow() {
; CHECK-LABEL: define float @nexttowardf_neg_overflow() {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%neg_max = load float, ptr @flt_neg_max
%neg_inf = load float, ptr @flt_neg_infinity
@@ -180,7 +180,7 @@ define float @nexttowardf_neg_overflow() {
define double @nexttoward_zero_from_above() {
; CHECK-LABEL: define double @nexttoward_zero_from_above() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, fp128 0xL00000000000000000000000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, fp128 0.000000e+00)
; CHECK-NEXT: ret double [[NEXT]]
;
%subnormal = load double, ptr @dbl_pos_min_subnormal
@@ -191,7 +191,7 @@ define double @nexttoward_zero_from_above() {
define float @nexttowardf_zero_from_above() {
; CHECK-LABEL: define float @nexttowardf_zero_from_above() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 0x36A0000000000000, fp128 0xL00000000000000000000000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 1.401300e-45, fp128 0.000000e+00)
; CHECK-NEXT: ret float [[NEXT]]
;
%min_subnormal = load float, ptr @flt_pos_min_subnormal
@@ -202,7 +202,7 @@ define float @nexttowardf_zero_from_above() {
define double @nexttoward_zero_from_below() {
; CHECK-LABEL: define double @nexttoward_zero_from_below() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double -4.940660e-324, fp128 0xL00000000000000000000000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double -4.940660e-324, fp128 0.000000e+00)
; CHECK-NEXT: ret double [[NEXT]]
;
%subnormal = load double, ptr @dbl_neg_min_subnormal
@@ -213,7 +213,7 @@ define double @nexttoward_zero_from_below() {
define float @nexttowardf_zero_from_below() {
; CHECK-LABEL: define float @nexttowardf_zero_from_below() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 0xB6A0000000000000, fp128 0xL00000000000000000000000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float -1.401300e-45, fp128 0.000000e+00)
; CHECK-NEXT: ret float [[NEXT]]
;
%min_subnormal = load float, ptr @flt_neg_min_subnormal
@@ -224,7 +224,7 @@ define float @nexttowardf_zero_from_below() {
define double @nexttoward_subnormal() {
; CHECK-LABEL: define double @nexttoward_subnormal() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, fp128 0xL00000000000000003FFF000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, fp128 1.000000e+00)
; CHECK-NEXT: ret double [[NEXT]]
;
%subnormal = load double, ptr @dbl_pos_min_subnormal
@@ -235,7 +235,7 @@ define double @nexttoward_subnormal() {
define float @nexttowardf_subnormal() {
; CHECK-LABEL: define float @nexttowardf_subnormal() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 0x36A0000000000000, fp128 0xL00000000000000003FFF000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 1.401300e-45, fp128 1.000000e+00)
; CHECK-NEXT: ret float [[NEXT]]
;
%subnormal = load float, ptr @flt_pos_min_subnormal
@@ -246,7 +246,7 @@ define float @nexttowardf_subnormal() {
define double @nexttoward_poison() {
; CHECK-LABEL: define double @nexttoward_poison() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double poison, fp128 0xL00000000000000003FFF000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double poison, fp128 1.000000e+00)
; CHECK-NEXT: ret double [[NEXT]]
;
%dummy_arg = fpext double 1.0 to fp128
@@ -256,7 +256,7 @@ define double @nexttoward_poison() {
define float @nexttowardf_poison() {
; CHECK-LABEL: define float @nexttowardf_poison() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float poison, fp128 0xL00000000000000003FFF000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float poison, fp128 1.000000e+00)
; CHECK-NEXT: ret float [[NEXT]]
;
%dummy_arg = fpext double 1.0 to fp128
@@ -266,7 +266,7 @@ define float @nexttowardf_poison() {
define double @nexttoward_subnormal_readnone() {
; CHECK-LABEL: define double @nexttoward_subnormal_readnone() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, fp128 0xL00000000000000003FFF000000000000) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, fp128 1.000000e+00) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret double [[NEXT]]
;
%subnormal = load double, ptr @dbl_pos_min_subnormal
@@ -277,7 +277,7 @@ define double @nexttoward_subnormal_readnone() {
define float @nexttowardf_subnormal_readnone() {
; CHECK-LABEL: define float @nexttowardf_subnormal_readnone() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 0x36A0000000000000, fp128 0xL00000000000000003FFF000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 1.401300e-45, fp128 1.000000e+00) #[[ATTR1]]
; CHECK-NEXT: ret float [[NEXT]]
;
%subnormal = load float, ptr @flt_pos_min_subnormal
diff --git a/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-ppc-fp128.ll b/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-ppc-fp128.ll
index d94afa0b814a9..e9a171c527a88 100644
--- a/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-ppc-fp128.ll
+++ b/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-ppc-fp128.ll
@@ -22,7 +22,7 @@
define double @nexttoward_up_direction() {
; CHECK-LABEL: define double @nexttoward_up_direction() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%arg = fpext double 2.0 to ppc_fp128
%next = call double @nexttoward(double 1.0, ppc_fp128 %arg)
@@ -31,7 +31,7 @@ define double @nexttoward_up_direction() {
define float @nexttowardf_up_direction() {
; CHECK-LABEL: define float @nexttowardf_up_direction() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%arg = fpext float 2.0 to ppc_fp128
%next = call float @nexttowardf(float 1.0, ppc_fp128 %arg)
@@ -40,7 +40,7 @@ define float @nexttowardf_up_direction() {
define double @nexttoward_down_direction() {
; CHECK-LABEL: define double @nexttoward_down_direction() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%arg = fpext double 0.0 to ppc_fp128
%next = call double @nexttoward(double 1.0, ppc_fp128 %arg)
@@ -49,7 +49,7 @@ define double @nexttoward_down_direction() {
define float @nexttowardf_down_direction() {
; CHECK-LABEL: define float @nexttowardf_down_direction() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%arg = fpext float 0.0 to ppc_fp128
%next = call float @nexttowardf(float 1.0, ppc_fp128 %arg)
@@ -58,7 +58,7 @@ define float @nexttowardf_down_direction() {
define double @nexttoward_pos_overflow() {
; CHECK-LABEL: define double @nexttoward_pos_overflow() {
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%pos_max = load double, ptr @dbl_pos_max
%pos_inf = load double, ptr @dbl_pos_infinity
@@ -69,7 +69,7 @@ define double @nexttoward_pos_overflow() {
define float @nexttowardf_pos_overflow () {
; CHECK-LABEL: define float @nexttowardf_pos_overflow() {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pos_max = load float, ptr @flt_pos_max
%pos_inf = load float, ptr @flt_pos_infinity
@@ -80,7 +80,7 @@ define float @nexttowardf_pos_overflow () {
define double @nexttoward_neg_overflow() {
; CHECK-LABEL: define double @nexttoward_neg_overflow() {
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%neg_max = load double, ptr @dbl_neg_max
%neg_inf = load double, ptr @dbl_neg_infinity
@@ -91,7 +91,7 @@ define double @nexttoward_neg_overflow() {
define float @nexttowardf_neg_overflow() {
; CHECK-LABEL: define float @nexttowardf_neg_overflow() {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%neg_max = load float, ptr @flt_neg_max
%neg_inf = load float, ptr @flt_neg_infinity
@@ -102,7 +102,7 @@ define float @nexttowardf_neg_overflow() {
define double @nexttoward_subnormal() {
; CHECK-LABEL: define double @nexttoward_subnormal() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, ppc_fp128 0xM3FF00000000000000000000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, ppc_fp128 1.000000e+00)
; CHECK-NEXT: ret double [[NEXT]]
;
%subnormal = load double, ptr @dbl_pos_min_subnormal
@@ -113,7 +113,7 @@ define double @nexttoward_subnormal() {
define float @nexttowardf_subnormal() {
; CHECK-LABEL: define float @nexttowardf_subnormal() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 0x36A0000000000000, ppc_fp128 0xM3FF00000000000000000000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 1.401300e-45, ppc_fp128 1.000000e+00)
; CHECK-NEXT: ret float [[NEXT]]
;
%subnormal = load float, ptr @flt_pos_min_subnormal
diff --git a/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-x86-fp80.ll b/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-x86-fp80.ll
index 08da8035172c4..779af3c632fdc 100644
--- a/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-x86-fp80.ll
+++ b/llvm/test/Transforms/InstCombine/constant-fold-nexttoward-x86-fp80.ll
@@ -22,7 +22,7 @@
define double @nexttoward_up_direction() {
; CHECK-LABEL: define double @nexttoward_up_direction() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%arg = fpext double 2.0 to x86_fp80
%next = call double @nexttoward(double 1.0, x86_fp80 %arg)
@@ -31,7 +31,7 @@ define double @nexttoward_up_direction() {
define float @nexttowardf_up_direction() {
; CHECK-LABEL: define float @nexttowardf_up_direction() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%arg = fpext float 2.0 to x86_fp80
%next = call float @nexttowardf(float 1.0, x86_fp80 %arg)
@@ -40,7 +40,7 @@ define float @nexttowardf_up_direction() {
define double @nexttoward_down_direction() {
; CHECK-LABEL: define double @nexttoward_down_direction() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%arg = fpext double 0.0 to x86_fp80
%next = call double @nexttoward(double 1.0, x86_fp80 %arg)
@@ -49,7 +49,7 @@ define double @nexttoward_down_direction() {
define float @nexttowardf_down_direction() {
; CHECK-LABEL: define float @nexttowardf_down_direction() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%arg = fpext float 0.0 to x86_fp80
%next = call float @nexttowardf(float 1.0, x86_fp80 %arg)
@@ -58,7 +58,7 @@ define float @nexttowardf_down_direction() {
define double @nexttoward_pos_overflow () {
; CHECK-LABEL: define double @nexttoward_pos_overflow() {
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%pos_max = load double, ptr @dbl_pos_max
%pos_inf = load double, ptr @dbl_pos_infinity
@@ -69,7 +69,7 @@ define double @nexttoward_pos_overflow () {
define float @nexttowardf_pos_overflow() {
; CHECK-LABEL: define float @nexttowardf_pos_overflow() {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pos_max = load float, ptr @flt_pos_max
%pos_inf = load float, ptr @flt_pos_infinity
@@ -80,7 +80,7 @@ define float @nexttowardf_pos_overflow() {
define double @nexttoward_neg_overflow() {
; CHECK-LABEL: define double @nexttoward_neg_overflow() {
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%neg_max = load double, ptr @dbl_neg_max
%neg_inf = load double, ptr @dbl_neg_infinity
@@ -91,7 +91,7 @@ define double @nexttoward_neg_overflow() {
define float @nexttowardf_neg_overflow() {
; CHECK-LABEL: define float @nexttowardf_neg_overflow() {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%neg_max = load float, ptr @flt_neg_max
%neg_inf = load float, ptr @flt_neg_infinity
@@ -102,7 +102,7 @@ define float @nexttowardf_neg_overflow() {
define double @nexttoward_subnormal() {
; CHECK-LABEL: define double @nexttoward_subnormal() {
-; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call double @nexttoward(double 4.940660e-324, x86_fp80 1.000000e+00)
; CHECK-NEXT: ret double [[NEXT]]
;
%subnormal = load double, ptr @dbl_pos_min_subnormal
@@ -113,7 +113,7 @@ define double @nexttoward_subnormal() {
define float @nexttowardf_subnormal() {
; CHECK-LABEL: define float @nexttowardf_subnormal() {
-; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 0x36A0000000000000, x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[NEXT:%.*]] = call float @nexttowardf(float 1.401300e-45, x86_fp80 1.000000e+00)
; CHECK-NEXT: ret float [[NEXT]]
;
%subnormal = load float, ptr @flt_pos_min_subnormal
diff --git a/llvm/test/Transforms/InstCombine/constrained.ll b/llvm/test/Transforms/InstCombine/constrained.ll
index 9b51c2856e9b5..01bb97ed1ae96 100644
--- a/llvm/test/Transforms/InstCombine/constrained.ll
+++ b/llvm/test/Transforms/InstCombine/constrained.ll
@@ -88,7 +88,7 @@ entry:
define float @f_eval_ignore() #0 {
; CHECK-LABEL: @f_eval_ignore(
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret float 0x3FD5555540000000
+; CHECK-NEXT: ret float f0x3EAAAAAA
;
entry:
%result = call float @llvm.experimental.constrained.fdiv.f32(float 1.0, float 3.0, metadata !"round.downward", metadata !"fpexcept.ignore") #0
@@ -111,7 +111,7 @@ entry:
define float @f_eval_maytrap() #0 {
; CHECK-LABEL: @f_eval_maytrap(
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret float 0x3FD5555560000000
+; CHECK-NEXT: ret float f0x3EAAAAAB
;
entry:
%result = call float @llvm.experimental.constrained.fdiv.f32(float 1.0, float 3.0, metadata !"round.tonearest", metadata !"fpexcept.maytrap") #0
diff --git a/llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll b/llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
index ce3355b6df039..8d11e375e179e 100644
--- a/llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
+++ b/llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
@@ -278,7 +278,7 @@ define half @fneg_fabs_copysign_multi_use_fabs(half %x, half %y, ptr %ptr) {
define half @copysign_pos(half %a) {
; CHECK-LABEL: @copysign_pos(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH3C00, half [[A:%.*]])
+; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 1.000000e+00, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
@@ -289,7 +289,7 @@ entry:
define half @copysign_neg(half %a) {
; CHECK-LABEL: @copysign_neg(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH3C00, half [[A:%.*]])
+; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 1.000000e+00, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
@@ -300,7 +300,7 @@ entry:
define half @copysign_negzero(half %a) {
; CHECK-LABEL: @copysign_negzero(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[A:%.*]])
+; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
@@ -311,7 +311,7 @@ entry:
define half @copysign_negnan(half %a) {
; CHECK-LABEL: @copysign_negnan(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH7E00, half [[A:%.*]])
+; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half +qnan, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
@@ -322,7 +322,7 @@ entry:
define half @copysign_neginf(half %a) {
; CHECK-LABEL: @copysign_neginf(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH7C00, half [[A:%.*]])
+; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half +inf, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
@@ -333,7 +333,7 @@ entry:
define <4 x half> @copysign_splat(<4 x half> %a) {
; CHECK-LABEL: @copysign_splat(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RET:%.*]] = call <4 x half> @llvm.copysign.v4f16(<4 x half> splat (half 0xH3C00), <4 x half> [[A:%.*]])
+; CHECK-NEXT: [[RET:%.*]] = call <4 x half> @llvm.copysign.v4f16(<4 x half> splat (half 1.000000e+00), <4 x half> [[A:%.*]])
; CHECK-NEXT: ret <4 x half> [[RET]]
;
entry:
@@ -346,7 +346,7 @@ entry:
define <4 x half> @copysign_vec4(<4 x half> %a) {
; CHECK-LABEL: @copysign_vec4(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RET:%.*]] = call <4 x half> @llvm.copysign.v4f16(<4 x half> <half 0xH3C00, half 0xHBC00, half undef, half poison>, <4 x half> [[A:%.*]])
+; CHECK-NEXT: [[RET:%.*]] = call <4 x half> @llvm.copysign.v4f16(<4 x half> <half 1.000000e+00, half -1.000000e+00, half undef, half poison>, <4 x half> [[A:%.*]])
; CHECK-NEXT: ret <4 x half> [[RET]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/copysign.ll b/llvm/test/Transforms/InstCombine/copysign.ll
index 59b13e6834961..4c7b4861b33c9 100644
--- a/llvm/test/Transforms/InstCombine/copysign.ll
+++ b/llvm/test/Transforms/InstCombine/copysign.ll
@@ -194,7 +194,7 @@ define i32 @issue178245(i32 %i.0.i.i) {
; CHECK-LABEL: @issue178245(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TOBOOL104_I_I_NOT:%.*]] = icmp eq i32 [[I_0_I_I:%.*]], -1177359834
-; CHECK-NEXT: [[CAST_SIGN:%.*]] = select i1 [[TOBOOL104_I_I_NOT]], float 0.000000e+00, float 0xFFFFFFFF60000000
+; CHECK-NEXT: [[CAST_SIGN:%.*]] = select i1 [[TOBOOL104_I_I_NOT]], float 0.000000e+00, float -nan(0x3FFFFB)
; CHECK-NEXT: [[FCMP:%.*]] = fcmp uno float [[CAST_SIGN]], 0.000000e+00
; CHECK-NEXT: [[COPYSIGN:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[CAST_SIGN]])
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[COPYSIGN]] to i32
diff --git a/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll b/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
index 3ac245cb0bec6..5a956581ffd85 100644
--- a/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
@@ -189,9 +189,9 @@ define i1 @not_isfinite_and_zero_f16(half %x) {
define i1 @not_isfinite_or_zero_f16_multi_use_cmp0(half %x, ptr %ptr) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_multi_use_cmp0(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], +inf
; CHECK-NEXT: store i1 [[CMPINF]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -207,8 +207,8 @@ define i1 @not_isfinite_or_zero_f16_multi_use_cmp0(half %x, ptr %ptr) {
define i1 @not_isfinite_or_zero_f16_multi_use_cmp1(half %x, ptr %ptr) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_multi_use_cmp1(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], +inf
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0.000000e+00
; CHECK-NEXT: store i1 [[CMPZERO]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
@@ -224,7 +224,7 @@ define i1 @not_isfinite_or_zero_f16_multi_use_cmp1(half %x, ptr %ptr) {
; Negative test
define i1 @not_isfinite_or_zero_f16_neg_inf(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_neg_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -251,7 +251,7 @@ define i1 @olt_0_or_fabs_ueq_inf(half %x) {
define i1 @oeq_0_or_fabs_ult_inf(half %x) {
; CHECK-LABEL: @oeq_0_or_fabs_ult_inf(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -265,8 +265,8 @@ define i1 @oeq_0_or_fabs_ult_inf(half %x) {
define i1 @not_isfinite_or_zero_f16_multi_not_0(half %x, ptr %ptr) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_multi_not_0(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH3C00
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], +inf
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 1.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -281,8 +281,8 @@ define i1 @not_isfinite_or_zero_f16_multi_not_0(half %x, ptr %ptr) {
define i1 @not_isfinite_or_zero_f16_fabs_wrong_val(half %x, half %y) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_fabs_wrong_val(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[Y:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], +inf
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -297,8 +297,8 @@ define i1 @not_isfinite_or_zero_f16_fabs_wrong_val(half %x, half %y) {
define i1 @not_isfinite_or_zero_f16_not_fabs(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_not_fabs(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.canonicalize.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], +inf
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -420,9 +420,9 @@ define i1 @negated_isfinite_or_zero_f16_swapped_constants(half %x) {
define i1 @negated_isfinite_or_zero_f16_multi_use_cmp0(half %x, ptr %ptr) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], +inf
; CHECK-NEXT: store i1 [[CMPINF]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0.000000e+00
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
;
@@ -438,8 +438,8 @@ define i1 @negated_isfinite_or_zero_f16_multi_use_cmp0(half %x, ptr %ptr) {
define i1 @negated_isfinite_or_zero_f16_multi_use_cmp1(half %x, ptr %ptr) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp1(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], +inf
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0.000000e+00
; CHECK-NEXT: store i1 [[CMPZERO]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
@@ -469,8 +469,8 @@ define i1 @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(half %x) {
define i1 @negated_isfinite_or_zero_f16_fabs_wrong_value(half %x, half %y) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_fabs_wrong_value(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[Y:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], +inf
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
;
@@ -581,8 +581,8 @@ define i1 @issubnormal_uge_or_inf(half %x) {
define i1 @issubnormal_or_inf_wrong_val(half %x) {
; CHECK-LABEL: @issubnormal_or_inf_wrong_val(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0401
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], +inf
+; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 6.109480e-05
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -596,7 +596,7 @@ define i1 @issubnormal_or_inf_wrong_val(half %x) {
define i1 @issubnormal_or_inf_neg_smallest_normal(half %x) {
; CHECK-LABEL: @issubnormal_or_inf_neg_smallest_normal(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], +inf
; CHECK-NEXT: ret i1 [[CMPINF]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -609,8 +609,8 @@ define i1 @issubnormal_or_inf_neg_smallest_normal(half %x) {
define i1 @fneg_fabs_olt_neg_smallest_normal_or_inf(half %x) {
; CHECK-LABEL: @fneg_fabs_olt_neg_smallest_normal_or_inf(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp ogt half [[FABS]], 0xH0400
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], +inf
+; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp ogt half [[FABS]], 6.103520e-05
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -625,7 +625,7 @@ define i1 @fneg_fabs_olt_neg_smallest_normal_or_inf(half %x) {
define i1 @issubnormal_or_finite_olt(half %x) {
; CHECK-LABEL: @issubnormal_or_finite_olt(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp one half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[OR:%.*]] = fcmp one half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -662,7 +662,7 @@ define i1 @issubnormal_and_finite_olt(half %x) {
define i1 @not_zero_and_subnormal(half %x) {
; CHECK-LABEL: @not_zero_and_subnormal(
-; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -691,7 +691,7 @@ define i1 @fcmp_fabs_uge_inf_or_fabs_uge_smallest_norm(half %x) {
define i1 @is_finite_and_ord(half %x) {
; CHECK-LABEL: @is_finite_and_ord(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[FABS]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -703,7 +703,7 @@ define i1 @is_finite_and_ord(half %x) {
define i1 @is_finite_and_uno(half %x) {
; CHECK-LABEL: @is_finite_and_uno(
-; CHECK-NEXT: [[AND:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[AND:%.*]] = fcmp uno half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -727,7 +727,7 @@ define i1 @is_finite_or_ord(half %x) {
define i1 @is_finite_or_uno(half %x) {
; CHECK-LABEL: @is_finite_or_uno(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp ueq half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[OR:%.*]] = fcmp ueq half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -740,7 +740,7 @@ define i1 @is_finite_or_uno(half %x) {
define i1 @oeq_isinf_or_uno(half %x) {
; CHECK-LABEL: @oeq_isinf_or_uno(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -752,7 +752,7 @@ define i1 @oeq_isinf_or_uno(half %x) {
define i1 @oeq_isinf_or_ord(half %x) {
; CHECK-LABEL: @oeq_isinf_or_ord(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -776,7 +776,7 @@ define i1 @oeq_isinf_and_uno(half %x) {
define i1 @oeq_isinf_and_ord(half %x) {
; CHECK-LABEL: @oeq_isinf_and_ord(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -829,7 +829,7 @@ entry:
; -> ord
define i1 @isnormalinf_or_ord(half %x) #0 {
; CHECK-LABEL: @isnormalinf_or_ord(
-; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -842,7 +842,7 @@ define i1 @isnormalinf_or_ord(half %x) #0 {
; -> ord
define i1 @ord_or_isnormalinf(half %x) #0 {
; CHECK-LABEL: @ord_or_isnormalinf(
-; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -856,7 +856,7 @@ define i1 @ord_or_isnormalinf(half %x) #0 {
; -> iszero
define i1 @une_or_oge_smallest_normal(half %x) #0 {
; CHECK-LABEL: @une_or_oge_smallest_normal(
-; CHECK-NEXT: [[OR:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[OR:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[OR]]
;
%is.normal.inf = fcmp oge half %x, 0xH0400
@@ -908,7 +908,7 @@ define i1 @isnormalinf_or_posinf(half %x) #0 {
define i1 @isnormalinf_and_inf(half %x) #0 {
; CHECK-LABEL: @isnormalinf_and_inf(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -921,7 +921,7 @@ define i1 @isnormalinf_and_inf(half %x) #0 {
; -> pinf
define i1 @posisnormalinf_and_posinf(half %x) #0 {
; CHECK-LABEL: @posisnormalinf_and_posinf(
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -934,7 +934,7 @@ define i1 @posisnormalinf_and_posinf(half %x) #0 {
; -> pinf
define i1 @isnormalinf_and_posinf(half %x) #0 {
; CHECK-LABEL: @isnormalinf_and_posinf(
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -977,7 +977,7 @@ define i1 @not_isnormalinf_and_ord(half %x) #0 {
define i1 @not_isnormalinf_or_inf(half %x) #0 {
; CHECK-LABEL: @not_isnormalinf_or_inf(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp une half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[OR:%.*]] = fcmp une half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -991,7 +991,7 @@ define i1 @not_isnormalinf_or_inf(half %x) #0 {
define i1 @not_isnormalinf_or_uno(half %x) #0 {
; CHECK-LABEL: @not_isnormalinf_or_uno(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp ult half [[FABS]], 0xH0400
+; CHECK-NEXT: [[OR:%.*]] = fcmp ult half [[FABS]], 6.103520e-05
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1005,7 +1005,7 @@ define i1 @not_isnormalinf_or_uno(half %x) #0 {
define i1 @not_isnormalinf_or_uno_nofabs(half %x) #0 {
; CHECK-LABEL: @not_isnormalinf_or_uno_nofabs(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp ult half [[FABS]], 0xH0400
+; CHECK-NEXT: [[OR:%.*]] = fcmp ult half [[FABS]], 6.103520e-05
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1056,7 +1056,7 @@ define i1 @not_isposnormalinf_and_isnormalinf(half %x) #0 {
; -> ord
define i1 @olt_smallest_normal_or_ord(half %x) #0 {
; CHECK-LABEL: @olt_smallest_normal_or_ord(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%ord = fcmp ord half %x, 0.0
@@ -1079,7 +1079,7 @@ define i1 @olt_smallest_normal_or_uno(half %x) #0 {
define i1 @olt_smallest_normal_or_finite(half %x) #0 {
; CHECK-LABEL: @olt_smallest_normal_or_finite(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1102,7 +1102,7 @@ define i1 @uge_smallest_normal_or_ord(half %x) #0 {
; -> nan | pnormal | pinf
define i1 @uge_smallest_normal_or_uno(half %x) #0 {
; CHECK-LABEL: @uge_smallest_normal_or_uno(
-; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[X:%.*]], 0xH0400
+; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[X:%.*]], 6.103520e-05
; CHECK-NEXT: ret i1 [[CMP_SMALLEST_NORMAL]]
;
%uno = fcmp uno half %x, 0.0
@@ -1114,7 +1114,7 @@ define i1 @uge_smallest_normal_or_uno(half %x) #0 {
; -> uno
define i1 @uge_smallest_normal_and_uno(half %x) #0 {
; CHECK-LABEL: @uge_smallest_normal_and_uno(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%uno = fcmp uno half %x, 0.0
@@ -1126,7 +1126,7 @@ define i1 @uge_smallest_normal_and_uno(half %x) #0 {
; -> true
define i1 @olt_infinity_or_finite(half %x) #0 {
; CHECK-LABEL: @olt_infinity_or_finite(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.infinity = fcmp olt half %x, 0xH7C00
@@ -1150,7 +1150,7 @@ define i1 @olt_infinity_and_finite(half %x) #0 { ; bustttedddd
; -> ord
define i1 @olt_infinity_or_ord(half %x) #0 {
; CHECK-LABEL: @olt_infinity_or_ord(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.infinity = fcmp olt half %x, 0xH7C00
@@ -1162,7 +1162,7 @@ define i1 @olt_infinity_or_ord(half %x) #0 {
; -> ~posinf
define i1 @olt_infinity_or_uno(half %x) #0 {
; CHECK-LABEL: @olt_infinity_or_uno(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.infinity = fcmp olt half %x, 0xH7C00
@@ -1173,7 +1173,7 @@ define i1 @olt_infinity_or_uno(half %x) #0 {
define i1 @olt_infinity_or_subnormal(half %x) #0 {
; CHECK-LABEL: @olt_infinity_or_subnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.infinity = fcmp olt half %x, 0xH7C00
@@ -1211,7 +1211,7 @@ define i1 @olt_infinity_and_not_subnormal(half %x) #0 {
; -> ninf
define i1 @olt_infinity_and_ueq_inf(half %x) #0 {
; CHECK-LABEL: @olt_infinity_and_ueq_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.infinity = fcmp olt half %x, 0xH7C00
@@ -1247,7 +1247,7 @@ define i1 @olt_smallest_normal_or_ueq_inf(half %x) #0 {
; -> ~pinf
define i1 @olt_smallest_normal_or_une_inf(half %x) #0 {
; CHECK-LABEL: @olt_smallest_normal_or_une_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.normal = fcmp olt half %x, 0xH0400
@@ -1297,7 +1297,7 @@ define i1 @olt_smallest_normal_and_une_inf_or_one_smallest_normal(half %x) #0 {
define i1 @oge_fabs_eq_inf_and_ord(half %x) #0 {
; CHECK-LABEL: @oge_fabs_eq_inf_and_ord(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1309,7 +1309,7 @@ define i1 @oge_fabs_eq_inf_and_ord(half %x) #0 {
define i1 @oge_eq_inf_and_ord(half %x) #0 {
; CHECK-LABEL: @oge_eq_inf_and_ord(
-; CHECK-NEXT: [[OGE_FABS_INF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[OGE_FABS_INF:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[OGE_FABS_INF]]
;
%oge.fabs.inf = fcmp oge half %x, 0xH7C00
@@ -1321,7 +1321,7 @@ define i1 @oge_eq_inf_and_ord(half %x) #0 {
define i1 @oge_fabs_eq_inf_or_uno(half %x) #0 {
; CHECK-LABEL: @oge_fabs_eq_inf_or_uno(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp ueq half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[OR:%.*]] = fcmp ueq half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1333,7 +1333,7 @@ define i1 @oge_fabs_eq_inf_or_uno(half %x) #0 {
define i1 @oge_eq_inf_or_uno(half %x) #0 {
; CHECK-LABEL: @oge_eq_inf_or_uno(
-; CHECK-NEXT: [[OR:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[OR:%.*]] = fcmp ueq half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[OR]]
;
%oge.fabs.inf = fcmp oge half %x, 0xH7C00
@@ -1345,7 +1345,7 @@ define i1 @oge_eq_inf_or_uno(half %x) #0 {
define i1 @ult_fabs_eq_inf_and_ord(half %x) #0 {
; CHECK-LABEL: @ult_fabs_eq_inf_and_ord(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[FABS]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[FABS]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1357,7 +1357,7 @@ define i1 @ult_fabs_eq_inf_and_ord(half %x) #0 {
define i1 @ult_eq_inf_and_ord(half %x) #0 {
; CHECK-LABEL: @ult_eq_inf_and_ord(
-; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[AND:%.*]] = fcmp one half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[AND]]
;
%ult.fabs.inf = fcmp ult half %x, 0xH7C00
@@ -1369,7 +1369,7 @@ define i1 @ult_eq_inf_and_ord(half %x) #0 {
define i1 @ult_fabs_eq_inf_or_uno(half %x) #0 {
; CHECK-LABEL: @ult_fabs_eq_inf_or_uno(
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[OR:%.*]] = fcmp une half [[TMP1]], 0xH7C00
+; CHECK-NEXT: [[OR:%.*]] = fcmp une half [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1381,7 +1381,7 @@ define i1 @ult_fabs_eq_inf_or_uno(half %x) #0 {
define i1 @ult_eq_inf_or_uno(half %x) #0 {
; CHECK-LABEL: @ult_eq_inf_or_uno(
-; CHECK-NEXT: [[ULT_FABS_INF:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[ULT_FABS_INF:%.*]] = fcmp une half [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[ULT_FABS_INF]]
;
%ult.fabs.inf = fcmp ult half %x, 0xH7C00
@@ -1394,8 +1394,8 @@ define i1 @ult_eq_inf_or_uno(half %x) #0 {
; Can't do anything with this
define i1 @oeq_neginfinity_or_oeq_smallest_normal(half %x) #0 {
; CHECK-LABEL: @oeq_neginfinity_or_oeq_smallest_normal(
-; CHECK-NEXT: [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
+; CHECK-NEXT: [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], -inf
+; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 6.103520e-05
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -1420,7 +1420,7 @@ define i1 @oeq_neginfinity_or_olt_smallest_normal(half %x) #0 {
; -> ninf
define i1 @oeq_neginfinity_and_olt_smallest_normal(half %x) #0 {
; CHECK-LABEL: @oeq_neginfinity_and_olt_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
@@ -1455,7 +1455,7 @@ define i1 @oeq_neginfinity_and_oge_smallest_normal(half %x) #0 {
; -> ord
define i1 @oeq_neginfinity_or_ord(half %x) #0 {
; CHECK-LABEL: @oeq_neginfinity_or_ord(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
@@ -1467,7 +1467,7 @@ define i1 @oeq_neginfinity_or_ord(half %x) #0 {
; -> ninf
define i1 @oeq_neginfinity_and_ord(half %x) #0 {
; CHECK-LABEL: @oeq_neginfinity_and_ord(
-; CHECK-NEXT: [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[OEQ_NEG_INFINITY]]
;
%oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
@@ -1479,8 +1479,8 @@ define i1 @oeq_neginfinity_and_ord(half %x) #0 {
; can't do anything with this
define i1 @une_neginfinity_or_oeq_smallest_normal(half %x) #0 {
; CHECK-LABEL: @une_neginfinity_or_oeq_smallest_normal(
-; CHECK-NEXT: [[UNE_NEG_INFINITY:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
+; CHECK-NEXT: [[UNE_NEG_INFINITY:%.*]] = fcmp une half [[X:%.*]], -inf
+; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 6.103520e-05
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[UNE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -1504,7 +1504,7 @@ define i1 @une_neginfinity_or_ord(half %x) #0 {
; -> ~(nan | ninf)
define i1 @une_neginfinity_and_ord(half %x) #0 {
; CHECK-LABEL: @une_neginfinity_and_ord(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp one half [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%une.neg.infinity = fcmp une half %x, 0xHFC00
@@ -1516,7 +1516,7 @@ define i1 @une_neginfinity_and_ord(half %x) #0 {
; -> ord
define i1 @one_neginfinity_or_olt_smallest_normal(half %x) #0 {
; CHECK-LABEL: @one_neginfinity_or_olt_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%one.neg.infinity = fcmp one half %x, 0xHFC00
@@ -1540,7 +1540,7 @@ define i1 @one_neginfinity_and_olt_smallest_normal(half %x) #0 {
; -> ~ninf
define i1 @one_neginfinity_or_uno(half %x) #0 {
; CHECK-LABEL: @one_neginfinity_or_uno(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp une half [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%one.neg.infinity = fcmp one half %x, 0xHFC00
@@ -1587,7 +1587,7 @@ define i1 @ueq_neginfinity_or_olt_smallest_normal(half %x) #0 {
; -> ninf
define i1 @ueq_neginfinity_and_olt_smallest_normal(half %x) #0 {
; CHECK-LABEL: @ueq_neginfinity_and_olt_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
@@ -1599,7 +1599,7 @@ define i1 @ueq_neginfinity_and_olt_smallest_normal(half %x) #0 {
; -> nan|ninf
define i1 @ueq_neginfinity_or_uno(half %x) #0 {
; CHECK-LABEL: @ueq_neginfinity_or_uno(
-; CHECK-NEXT: [[UEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[UEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[UEQ_NEG_INFINITY]]
;
%ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
@@ -1611,7 +1611,7 @@ define i1 @ueq_neginfinity_or_uno(half %x) #0 {
; -> nan|ninf
define i1 @ueq_neginfinity_and_ord(half %x) #0 {
; CHECK-LABEL: @ueq_neginfinity_and_ord(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
@@ -1623,7 +1623,7 @@ define i1 @ueq_neginfinity_and_ord(half %x) #0 {
; -> uno
define i1 @ueq_neginfinity_and_uge_smallest_normal(half %x) #0 {
; CHECK-LABEL: @ueq_neginfinity_and_uge_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
@@ -1635,7 +1635,7 @@ define i1 @ueq_neginfinity_and_uge_smallest_normal(half %x) #0 {
; -> ord
define i1 @fabs_oeq_neginfinity_or_ord(half %x) #0 {
; CHECK-LABEL: @fabs_oeq_neginfinity_or_ord(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[ORD]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1660,7 +1660,7 @@ define i1 @fabs_une_neginfinity_or_ord(half %x) #0 {
; -> une
define i1 @fabs_une_neginfinity_and_ord(half %x) #0 {
; CHECK-LABEL: @fabs_une_neginfinity_and_ord(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[ORD]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1685,7 +1685,7 @@ define i1 @fabs_oeq_neginfinity_and_uge_smallest_normal(half %x) #0 {
; -> false
define i1 @fabs_oeq_neginfinity_or_uge_smallest_normal(half %x) #0 {
; CHECK-LABEL: @fabs_oeq_neginfinity_or_uge_smallest_normal(
-; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X:%.*]], 0xH0400
+; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X:%.*]], 6.103520e-05
; CHECK-NEXT: ret i1 [[CMP_SMALLEST_NORMAL]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1735,7 +1735,7 @@ define i1 @fabs_one_neginfinity_and_uge_smallest_normal(half %x) #0 {
; -> ord
define i1 @fabs_one_neginfinity_or_olt_smallest_normal(half %x) #0 {
; CHECK-LABEL: @fabs_one_neginfinity_or_olt_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1766,8 +1766,8 @@ define i1 @fabs_ueq_neginfinity_or_fabs_uge_smallest_normal(half %x) #0 {
define i1 @not_isfinite_or_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @not_isfinite_or_zero_f16_daz(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], +inf
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -1781,7 +1781,7 @@ define i1 @not_isfinite_or_zero_f16_daz(half %x) #1 {
define <2 x i1> @not_isfinite_or_zero_v2f16_daz(<2 x half> %x) #1 {
; CHECK-LABEL: @not_isfinite_or_zero_v2f16_daz(
; CHECK-NEXT: [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], splat (half 0xH7C00)
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], splat (half +inf)
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
; CHECK-NEXT: [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
@@ -1797,8 +1797,8 @@ define <2 x i1> @not_isfinite_or_zero_v2f16_daz(<2 x half> %x) #1 {
define i1 @not_isfinite_or_zero_f16_dynamic(half %x) #2 {
; CHECK-LABEL: @not_isfinite_or_zero_f16_dynamic(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], +inf
+; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -1812,7 +1812,7 @@ define i1 @not_isfinite_or_zero_f16_dynamic(half %x) #2 {
define <2 x i1> @not_isfinite_or_zero_v2f16_dynamic(<2 x half> %x) #2 {
; CHECK-LABEL: @not_isfinite_or_zero_v2f16_dynamic(
; CHECK-NEXT: [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], splat (half 0xH7C00)
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], splat (half +inf)
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
; CHECK-NEXT: [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
@@ -1826,7 +1826,7 @@ define <2 x i1> @not_isfinite_or_zero_v2f16_dynamic(<2 x half> %x) #2 {
define i1 @not_zero_and_subnormal_daz(half %x) #1 {
; CHECK-LABEL: @not_zero_and_subnormal_daz(
-; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1839,8 +1839,8 @@ define i1 @not_zero_and_subnormal_daz(half %x) #1 {
define i1 @not_zero_and_subnormal_dynamic(half %x) #2 {
; CHECK-LABEL: @not_zero_and_subnormal_dynamic(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMP_ZERO:%.*]] = fcmp one half [[X]], 0xH0000
-; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
+; CHECK-NEXT: [[CMP_ZERO:%.*]] = fcmp one half [[X]], 0.000000e+00
+; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 6.103520e-05
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMP_ZERO]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -1866,7 +1866,7 @@ define i1 @subnormal_or_zero_ieee(half %x) #0 {
define i1 @subnormal_or_zero_daz(half %x) #1 {
; CHECK-LABEL: @subnormal_or_zero_daz(
-; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1879,8 +1879,8 @@ define i1 @subnormal_or_zero_daz(half %x) #1 {
define i1 @subnormal_or_zero_dynamic(half %x) #2 {
; CHECK-LABEL: @subnormal_or_zero_dynamic(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; CHECK-NEXT: [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
+; CHECK-NEXT: [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 6.103520e-05
+; CHECK-NEXT: [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0.000000e+00
; CHECK-NEXT: [[AND:%.*]] = or i1 [[IS_SUBNORMAL]], [[IS_ZERO]]
; CHECK-NEXT: ret i1 [[AND]]
;
@@ -1939,8 +1939,8 @@ define i1 @fcmp_oeq_neginf_or_oge_zero_f16(half %x) {
define i1 @fcmp_ueq_neginf_or_oge_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT: [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], -inf
+; CHECK-NEXT: [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -1952,8 +1952,8 @@ define i1 @fcmp_ueq_neginf_or_oge_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_neginf_or_oge_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT: [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], -inf
+; CHECK-NEXT: [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -1987,8 +1987,8 @@ define i1 @fcmp_ueq_neginf_or_ogt_zero_f16(half %x) {
define i1 @fcmp_ueq_neginf_or_ogt_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT: [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], -inf
+; CHECK-NEXT: [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2000,8 +2000,8 @@ define i1 @fcmp_ueq_neginf_or_ogt_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_neginf_or_ogt_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT: [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], -inf
+; CHECK-NEXT: [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2024,8 +2024,8 @@ define i1 @fcmp_oeq_neginf_or_ugt_zero_f16(half %x) {
define i1 @fcmp_ueq_neginf_or_ugt_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_ueq_neginf_or_ugt_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT: [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], -inf
+; CHECK-NEXT: [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2037,8 +2037,8 @@ define i1 @fcmp_ueq_neginf_or_ugt_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_neginf_or_ugt_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT: [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], -inf
+; CHECK-NEXT: [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2072,8 +2072,8 @@ define i1 @fcmp_oeq_posinf_or_ole_zero_f16(half %x) {
define i1 @fcmp_ueq_posinf_or_ole_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT: [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], +inf
+; CHECK-NEXT: [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2085,8 +2085,8 @@ define i1 @fcmp_ueq_posinf_or_ole_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_posinf_or_ole_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT: [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], +inf
+; CHECK-NEXT: [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2109,8 +2109,8 @@ define i1 @fcmp_oeq_posinf_or_olt_zero_f16(half %x) {
define i1 @fcmp_oeq_posinf_or_olt_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT: [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], +inf
+; CHECK-NEXT: [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2144,8 +2144,8 @@ define i1 @fcmp_oeq_posinf_or_ult_zero_f16(half %x) {
define i1 @fcmp_ueq_posinf_or_ult_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT: [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], +inf
+; CHECK-NEXT: [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2157,8 +2157,8 @@ define i1 @fcmp_ueq_posinf_or_ult_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_posinf_or_ult_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT: [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], +inf
+; CHECK-NEXT: [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2181,8 +2181,8 @@ define i1 @fcmp_ueq_posinf_or_ule_zero_f16(half %x) {
define i1 @fcmp_ueq_posinf_or_ule_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT: [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], +inf
+; CHECK-NEXT: [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -2194,8 +2194,8 @@ define i1 @fcmp_ueq_posinf_or_ule_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_posinf_or_ule_zero_f16_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_posinf_or_ule_zero_f16_daz(
-; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT: [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], +inf
+; CHECK-NEXT: [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0.000000e+00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
diff --git a/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll b/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
index f884d2bd1ab5b..d6faddf980f8d 100644
--- a/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
+++ b/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
@@ -509,7 +509,7 @@ define float @test_shrink_float_convertible_constant_intrin_trunc() {
define float @test_shrink_float_convertible_constant_intrin_fabs() {
; CHECK-LABEL: @test_shrink_float_convertible_constant_intrin_fabs(
-; CHECK-NEXT: ret float 0x4000CCCCC0000000
+; CHECK-NEXT: ret float 2.100000e+00
;
%E = call double @llvm.fabs.f64(double 2.1)
%F = fptrunc double %E to float
@@ -519,7 +519,7 @@ define float @test_shrink_float_convertible_constant_intrin_fabs() {
; Make sure fast math flags are preserved
define float @test_shrink_float_convertible_constant_intrin_fabs_fast() {
; CHECK-LABEL: @test_shrink_float_convertible_constant_intrin_fabs_fast(
-; CHECK-NEXT: ret float 0x4000CCCCC0000000
+; CHECK-NEXT: ret float 2.100000e+00
;
%E = call fast double @llvm.fabs.f64(double 2.1)
%F = fptrunc double %E to float
diff --git a/llvm/test/Transforms/InstCombine/erf.ll b/llvm/test/Transforms/InstCombine/erf.ll
index 13d6545acd5be..9f83acabb6fb7 100644
--- a/llvm/test/Transforms/InstCombine/erf.ll
+++ b/llvm/test/Transforms/InstCombine/erf.ll
@@ -4,7 +4,7 @@
define float @erff_const() {
; CHECK-LABEL: define float @erff_const() {
; CHECK-NEXT: [[R:%.*]] = call float @erff(float 5.000000e-01)
-; CHECK-NEXT: ret float 0x3FE0A7EF60000000
+; CHECK-NEXT: ret float f0x3F053F7B
;
%r = call float @erff(float 5.000000e-01)
ret float %r
@@ -13,7 +13,7 @@ define float @erff_const() {
define double @erf_const() {
; CHECK-LABEL: define double @erf_const() {
; CHECK-NEXT: [[R:%.*]] = call double @erf(double -5.000000e-01)
-; CHECK-NEXT: ret double 0xBFE0A7EF5C18EDD2
+; CHECK-NEXT: ret double f0xBFE0A7EF5C18EDD2
;
%r = call double @erf(double -5.000000e-01)
ret double %r
@@ -57,7 +57,7 @@ define double @erf_neg_zero() {
define float @erff_inf() {
; CHECK-LABEL: define float @erff_inf() {
-; CHECK-NEXT: [[R:%.*]] = call float @erff(float 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call float @erff(float +inf)
; CHECK-NEXT: ret float [[R]]
;
%r = call float @erff(float 0x7FF0000000000000)
@@ -66,7 +66,7 @@ define float @erff_inf() {
define double @erf_inf() {
; CHECK-LABEL: define double @erf_inf() {
-; CHECK-NEXT: [[R:%.*]] = call double @erf(double 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @erf(double +inf)
; CHECK-NEXT: ret double [[R]]
;
%r = call double @erf(double 0x7FF0000000000000)
@@ -75,7 +75,7 @@ define double @erf_inf() {
define float @erff_inf_memory_none() {
; CHECK-LABEL: define float @erff_inf_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call float @erff(float 0x7FF0000000000000) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[R:%.*]] = call float @erff(float +inf) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret float [[R]]
;
%r = call float @erff(float 0x7FF0000000000000) readnone
@@ -84,7 +84,7 @@ define float @erff_inf_memory_none() {
define double @erf_inf_memory_none() {
; CHECK-LABEL: define double @erf_inf_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call double @erf(double 0x7FF0000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call double @erf(double +inf) #[[ATTR1]]
; CHECK-NEXT: ret double [[R]]
;
%r = call double @erf(double 0x7FF0000000000000) readnone
@@ -93,7 +93,7 @@ define double @erf_inf_memory_none() {
define float @erff_neg_inf() {
; CHECK-LABEL: define float @erff_neg_inf() {
-; CHECK-NEXT: [[R:%.*]] = call float @erff(float 0xFFF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call float @erff(float -inf)
; CHECK-NEXT: ret float [[R]]
;
%r = call float @erff(float 0xFFF0000000000000)
@@ -102,7 +102,7 @@ define float @erff_neg_inf() {
define double @erf_neg_inf() {
; CHECK-LABEL: define double @erf_neg_inf() {
-; CHECK-NEXT: [[R:%.*]] = call double @erf(double 0xFFF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @erf(double -inf)
; CHECK-NEXT: ret double [[R]]
;
%r = call double @erf(double 0xFFF0000000000000)
@@ -111,7 +111,7 @@ define double @erf_neg_inf() {
define float @erff_neg_inf_memory_none() {
; CHECK-LABEL: define float @erff_neg_inf_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call float @erff(float 0xFFF0000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call float @erff(float -inf) #[[ATTR1]]
; CHECK-NEXT: ret float [[R]]
;
%r = call float @erff(float 0xFFF0000000000000) readnone
@@ -120,7 +120,7 @@ define float @erff_neg_inf_memory_none() {
define double @erf_neg_inf_memory_none() {
; CHECK-LABEL: define double @erf_neg_inf_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call double @erf(double 0xFFF0000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call double @erf(double -inf) #[[ATTR1]]
; CHECK-NEXT: ret double [[R]]
;
%r = call double @erf(double 0xFFF0000000000000) readnone
@@ -129,7 +129,7 @@ define double @erf_neg_inf_memory_none() {
define float @erff_nan() {
; CHECK-LABEL: define float @erff_nan() {
-; CHECK-NEXT: [[R:%.*]] = call float @erff(float 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call float @erff(float +qnan)
; CHECK-NEXT: ret float [[R]]
;
%r = call float @erff(float 0x7FF8000000000000)
@@ -138,7 +138,7 @@ define float @erff_nan() {
define double @erf_nan() {
; CHECK-LABEL: define double @erf_nan() {
-; CHECK-NEXT: [[R:%.*]] = call double @erf(double 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @erf(double +qnan)
; CHECK-NEXT: ret double [[R]]
;
%r = call double @erf(double 0x7FF8000000000000)
@@ -147,7 +147,7 @@ define double @erf_nan() {
define float @erff_nan_memory_none() {
; CHECK-LABEL: define float @erff_nan_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call float @erff(float 0x7FF8000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call float @erff(float +qnan) #[[ATTR1]]
; CHECK-NEXT: ret float [[R]]
;
%r = call float @erff(float 0x7FF8000000000000) readnone
@@ -156,7 +156,7 @@ define float @erff_nan_memory_none() {
define double @erf_nan_memory_none() {
; CHECK-LABEL: define double @erf_nan_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call double @erf(double 0x7FF8000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call double @erf(double +qnan) #[[ATTR1]]
; CHECK-NEXT: ret double [[R]]
;
%r = call double @erf(double 0x7FF8000000000000) readnone
@@ -201,7 +201,7 @@ define double @erf_const_strictfp() {
define float @erff_nan_strictfp() {
; CHECK-LABEL: define float @erff_nan_strictfp() {
-; CHECK-NEXT: [[R:%.*]] = call float @erff(float 0x7FF8000000000000) #[[ATTR2]]
+; CHECK-NEXT: [[R:%.*]] = call float @erff(float +qnan) #[[ATTR2]]
; CHECK-NEXT: ret float [[R]]
;
%r = call float @erff(float 0x7FF8000000000000) strictfp
@@ -210,7 +210,7 @@ define float @erff_nan_strictfp() {
define double @erf_nan_strictfp() {
; CHECK-LABEL: define double @erf_nan_strictfp() {
-; CHECK-NEXT: [[R:%.*]] = call double @erf(double 0x7FF8000000000000) #[[ATTR2]]
+; CHECK-NEXT: [[R:%.*]] = call double @erf(double +qnan) #[[ATTR2]]
; CHECK-NEXT: ret double [[R]]
;
%r = call double @erf(double 0x7FF8000000000000) strictfp
diff --git a/llvm/test/Transforms/InstCombine/exp2-1.ll b/llvm/test/Transforms/InstCombine/exp2-1.ll
index 0502540b7f7e9..6824d1babae7a 100644
--- a/llvm/test/Transforms/InstCombine/exp2-1.ll
+++ b/llvm/test/Transforms/InstCombine/exp2-1.ll
@@ -383,7 +383,7 @@ define float @test_readonly_exp2f_f32_of_sitofp(i32 %x) {
define fp128 @test_readonly_exp2l_fp128_of_sitofp(i32 %x) {
; LDEXP32-LABEL: @test_readonly_exp2l_fp128_of_sitofp(
-; LDEXP32-NEXT: [[LDEXPL:%.*]] = call fp128 @ldexpl(fp128 0xL00000000000000003FFF000000000000, i32 [[X:%.*]])
+; LDEXP32-NEXT: [[LDEXPL:%.*]] = call fp128 @ldexpl(fp128 1.000000e+00, i32 [[X:%.*]])
; LDEXP32-NEXT: ret fp128 [[LDEXPL]]
;
; LDEXP16-LABEL: @test_readonly_exp2l_fp128_of_sitofp(
diff --git a/llvm/test/Transforms/InstCombine/exp2-to-ldexp.ll b/llvm/test/Transforms/InstCombine/exp2-to-ldexp.ll
index 8a52f79f307ca..b47d2cc5d92a3 100644
--- a/llvm/test/Transforms/InstCombine/exp2-to-ldexp.ll
+++ b/llvm/test/Transforms/InstCombine/exp2-to-ldexp.ll
@@ -54,7 +54,7 @@ define half @exp2_f16_sitofp_i8(i8 %x) {
; CHECK-LABEL: define half @exp2_f16_sitofp_i8(
; CHECK-SAME: i8 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[X]] to i32
-; CHECK-NEXT: [[EXP2:%.*]] = call half @llvm.ldexp.f16.i32(half 0xH3C00, i32 [[TMP1]])
+; CHECK-NEXT: [[EXP2:%.*]] = call half @llvm.ldexp.f16.i32(half 1.000000e+00, i32 [[TMP1]])
; CHECK-NEXT: ret half [[EXP2]]
;
%itofp = sitofp i8 %x to half
@@ -78,7 +78,7 @@ define fp128 @exp2_fp128_sitofp_i8(i8 %x) {
; CHECK-LABEL: define fp128 @exp2_fp128_sitofp_i8(
; CHECK-SAME: i8 [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[X]] to i32
-; CHECK-NEXT: [[EXP2:%.*]] = call fp128 @llvm.ldexp.f128.i32(fp128 0xL00000000000000003FFF000000000000, i32 [[TMP1]])
+; CHECK-NEXT: [[EXP2:%.*]] = call fp128 @llvm.ldexp.f128.i32(fp128 1.000000e+00, i32 [[TMP1]])
; CHECK-NEXT: ret fp128 [[EXP2]]
;
%itofp = sitofp i8 %x to fp128
diff --git a/llvm/test/Transforms/InstCombine/fabs.ll b/llvm/test/Transforms/InstCombine/fabs.ll
index 0c3ed56a8347a..2425251207604 100644
--- a/llvm/test/Transforms/InstCombine/fabs.ll
+++ b/llvm/test/Transforms/InstCombine/fabs.ll
@@ -519,8 +519,8 @@ define half @select_fcmp_nnan_ugt_negzero(half %x) {
define half @select_fcmp_nnan_oge_negzero(half %x) {
; CHECK-LABEL: @select_fcmp_nnan_oge_negzero(
-; CHECK-NEXT: [[GTZERO:%.*]] = fcmp oge half [[X:%.*]], 0xH0000
-; CHECK-NEXT: [[NEGX:%.*]] = fsub nnan half 0xH0000, [[X]]
+; CHECK-NEXT: [[GTZERO:%.*]] = fcmp oge half [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[NEGX:%.*]] = fsub nnan half 0.000000e+00, [[X]]
; CHECK-NEXT: [[FABS:%.*]] = select i1 [[GTZERO]], half [[X]], half [[NEGX]]
; CHECK-NEXT: ret half [[FABS]]
;
@@ -922,7 +922,7 @@ define <2 x float> @select_fcmp_nnan_nsz_ugt_zero_unary_fneg(<2 x float> %x) {
define half @select_fcmp_nnan_nsz_ogt_negzero(half %x) {
; CHECK-LABEL: @select_fcmp_nnan_nsz_ogt_negzero(
-; CHECK-NEXT: [[GTZERO:%.*]] = fcmp ogt half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[GTZERO:%.*]] = fcmp ogt half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[NEGX:%.*]] = fneg fast half [[X]]
; CHECK-NEXT: [[FABS:%.*]] = select nnan i1 [[GTZERO]], half [[X]], half [[NEGX]]
; CHECK-NEXT: ret half [[FABS]]
@@ -937,7 +937,7 @@ define half @select_fcmp_nnan_nsz_ogt_negzero(half %x) {
define half @select_fcmp_nnan_nsz_ugt_negzero(half %x) {
; CHECK-LABEL: @select_fcmp_nnan_nsz_ugt_negzero(
-; CHECK-NEXT: [[GTZERO:%.*]] = fcmp ugt half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[GTZERO:%.*]] = fcmp ugt half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[NEGX:%.*]] = fneg fast half [[X]]
; CHECK-NEXT: [[FABS:%.*]] = select i1 [[GTZERO]], half [[X]], half [[NEGX]]
; CHECK-NEXT: ret half [[FABS]]
@@ -1010,7 +1010,7 @@ define <2 x double> @select_fcmp_nnan_nsz_uge_zero_unary_fneg(<2 x double> %x) {
define half @select_fcmp_nnan_nsz_oge_negzero(half %x) {
; CHECK-LABEL: @select_fcmp_nnan_nsz_oge_negzero(
-; CHECK-NEXT: [[GEZERO:%.*]] = fcmp oge half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[GEZERO:%.*]] = fcmp oge half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[NEGX:%.*]] = fneg nnan nsz half [[X]]
; CHECK-NEXT: [[FABS:%.*]] = select nnan i1 [[GEZERO]], half [[X]], half [[NEGX]]
; CHECK-NEXT: ret half [[FABS]]
@@ -1025,7 +1025,7 @@ define half @select_fcmp_nnan_nsz_oge_negzero(half %x) {
define half @select_fcmp_nnan_nsz_uge_negzero(half %x) {
; CHECK-LABEL: @select_fcmp_nnan_nsz_uge_negzero(
-; CHECK-NEXT: [[GEZERO:%.*]] = fcmp uge half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[GEZERO:%.*]] = fcmp uge half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[NEGX:%.*]] = fneg nnan nsz half [[X]]
; CHECK-NEXT: [[FABS:%.*]] = select i1 [[GEZERO]], half [[X]], half [[NEGX]]
; CHECK-NEXT: ret half [[FABS]]
@@ -1038,7 +1038,7 @@ define half @select_fcmp_nnan_nsz_uge_negzero(half %x) {
define half @select_fcmp_nnan_nsz_oge_negzero_unary_fneg(half %x) {
; CHECK-LABEL: @select_fcmp_nnan_nsz_oge_negzero_unary_fneg(
-; CHECK-NEXT: [[GEZERO:%.*]] = fcmp oge half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[GEZERO:%.*]] = fcmp oge half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[NEGX:%.*]] = fneg nnan nsz half [[X]]
; CHECK-NEXT: [[FABS:%.*]] = select nnan i1 [[GEZERO]], half [[X]], half [[NEGX]]
; CHECK-NEXT: ret half [[FABS]]
@@ -1053,7 +1053,7 @@ define half @select_fcmp_nnan_nsz_oge_negzero_unary_fneg(half %x) {
define half @select_fcmp_nnan_nsz_uge_negzero_unary_fneg(half %x) {
; CHECK-LABEL: @select_fcmp_nnan_nsz_uge_negzero_unary_fneg(
-; CHECK-NEXT: [[GEZERO:%.*]] = fcmp uge half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[GEZERO:%.*]] = fcmp uge half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[NEGX:%.*]] = fneg nnan nsz half [[X]]
; CHECK-NEXT: [[FABS:%.*]] = select i1 [[GEZERO]], half [[X]], half [[NEGX]]
; CHECK-NEXT: ret half [[FABS]]
diff --git a/llvm/test/Transforms/InstCombine/fadd-fsub-factor.ll b/llvm/test/Transforms/InstCombine/fadd-fsub-factor.ll
index 0be7f50cfddae..1c767f627049c 100644
--- a/llvm/test/Transforms/InstCombine/fadd-fsub-factor.ll
+++ b/llvm/test/Transforms/InstCombine/fadd-fsub-factor.ll
@@ -432,7 +432,7 @@ define float @fdiv_fsub_uses3(float %x, float %y, float %z) {
define float @fdiv_fadd_not_denorm(float %x) {
; CHECK-LABEL: @fdiv_fadd_not_denorm(
-; CHECK-NEXT: [[R:%.*]] = fdiv fast float 0x3818000000000000, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = fdiv fast float f0x00C00000, [[X:%.*]]
; CHECK-NEXT: ret float [[R]]
;
%t1 = fdiv fast float 0x3810000000000000, %x
@@ -445,8 +445,8 @@ define float @fdiv_fadd_not_denorm(float %x) {
define float @fdiv_fadd_denorm(float %x) {
; CHECK-LABEL: @fdiv_fadd_denorm(
-; CHECK-NEXT: [[T1:%.*]] = fdiv fast float 0xB810000000000000, [[X:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = fdiv fast float 0x3800000000000000, [[X]]
+; CHECK-NEXT: [[T1:%.*]] = fdiv fast float f0x80800000, [[X:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = fdiv fast float f0x00400000, [[X]]
; CHECK-NEXT: [[R:%.*]] = fadd fast float [[T1]], [[T2]]
; CHECK-NEXT: ret float [[R]]
;
@@ -460,8 +460,8 @@ define float @fdiv_fadd_denorm(float %x) {
define float @fdiv_fsub_denorm(float %x) {
; CHECK-LABEL: @fdiv_fsub_denorm(
-; CHECK-NEXT: [[T1:%.*]] = fdiv fast float 0x3810000000000000, [[X:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = fdiv fast float 0x3800000000000000, [[X]]
+; CHECK-NEXT: [[T1:%.*]] = fdiv fast float f0x00800000, [[X:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = fdiv fast float f0x00400000, [[X]]
; CHECK-NEXT: [[R:%.*]] = fsub fast float [[T1]], [[T2]]
; CHECK-NEXT: ret float [[R]]
;
diff --git a/llvm/test/Transforms/InstCombine/fadd.ll b/llvm/test/Transforms/InstCombine/fadd.ll
index d412e7fa75255..b6d9360e5def9 100644
--- a/llvm/test/Transforms/InstCombine/fadd.ll
+++ b/llvm/test/Transforms/InstCombine/fadd.ll
@@ -946,7 +946,7 @@ define float @fadd_reduce_sqr_sum_varA_invalid2(float %a, float %b) {
define float @fadd_reduce_sqr_sum_varA_invalid3(float %a, float %b) {
; CHECK-LABEL: @fadd_reduce_sqr_sum_varA_invalid3(
; CHECK-NEXT: [[A_SQ:%.*]] = fmul float [[A:%.*]], [[A]]
-; CHECK-NEXT: [[NOT_TWO_A:%.*]] = fmul float [[A]], 0x4000CCCCC0000000
+; CHECK-NEXT: [[NOT_TWO_A:%.*]] = fmul float [[A]], 2.100000e+00
; CHECK-NEXT: [[TWO_A_PLUS_B:%.*]] = fadd float [[NOT_TWO_A]], [[B:%.*]]
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[TWO_A_PLUS_B]], [[B]]
; CHECK-NEXT: [[ADD:%.*]] = fadd reassoc nsz float [[MUL]], [[A_SQ]]
@@ -1034,7 +1034,7 @@ define float @fadd_reduce_sqr_sum_varB_invalid2(float %a, float %b) {
define float @fadd_reduce_sqr_sum_varB_invalid3(float %a, float %b) {
; CHECK-LABEL: @fadd_reduce_sqr_sum_varB_invalid3(
; CHECK-NEXT: [[A_B:%.*]] = fmul float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[NOT_A_B_2:%.*]] = fmul float [[A_B]], 0x4000CCCCC0000000
+; CHECK-NEXT: [[NOT_A_B_2:%.*]] = fmul float [[A_B]], 2.100000e+00
; CHECK-NEXT: [[A_SQ:%.*]] = fmul float [[A]], [[A]]
; CHECK-NEXT: [[B_SQ:%.*]] = fmul float [[B]], [[B]]
; CHECK-NEXT: [[A_SQ_B_SQ:%.*]] = fadd float [[A_SQ]], [[B_SQ]]
@@ -1109,7 +1109,7 @@ define float @fadd_reduce_sqr_sum_varB2_invalid1(float %a, float %b) {
define float @fadd_reduce_sqr_sum_varB2_invalid2(float %a, float %b) {
; CHECK-LABEL: @fadd_reduce_sqr_sum_varB2_invalid2(
-; CHECK-NEXT: [[NOT_A_2:%.*]] = fmul float [[A:%.*]], 0x4000CCCCC0000000
+; CHECK-NEXT: [[NOT_A_2:%.*]] = fmul float [[A:%.*]], 2.100000e+00
; CHECK-NEXT: [[A_B_2:%.*]] = fmul float [[NOT_A_2]], [[B:%.*]]
; CHECK-NEXT: [[A_SQ:%.*]] = fmul float [[A]], [[A]]
; CHECK-NEXT: [[B_SQ:%.*]] = fmul float [[B]], [[B]]
diff --git a/llvm/test/Transforms/InstCombine/fast-math.ll b/llvm/test/Transforms/InstCombine/fast-math.ll
index 7b5f5cf477de9..722d3967974d6 100644
--- a/llvm/test/Transforms/InstCombine/fast-math.ll
+++ b/llvm/test/Transforms/InstCombine/fast-math.ll
@@ -5,7 +5,7 @@
; 1.2f and 2.3f is supposed to be fold.
define float @fold(float %a) {
; CHECK-LABEL: @fold(
-; CHECK-NEXT: [[MUL1:%.*]] = fmul fast float [[A:%.*]], 0x4006147AE0000000
+; CHECK-NEXT: [[MUL1:%.*]] = fmul fast float [[A:%.*]], 2.760000e+00
; CHECK-NEXT: ret float [[MUL1]]
;
%mul = fmul fast float %a, 0x3FF3333340000000
@@ -17,8 +17,8 @@ define float @fold(float %a) {
; fixed FP mode.
define float @notfold(float %a) {
; CHECK-LABEL: @notfold(
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[A:%.*]], 0x3FF3333340000000
-; CHECK-NEXT: [[MUL1:%.*]] = fmul nnan float [[MUL]], 0x4002666660000000
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[A:%.*]], 1.200000e+00
+; CHECK-NEXT: [[MUL1:%.*]] = fmul nnan float [[MUL]], 2.300000e+00
; CHECK-NEXT: ret float [[MUL1]]
;
%mul = fmul fast float %a, 0x3FF3333340000000
@@ -28,7 +28,7 @@ define float @notfold(float %a) {
define float @fold2(float %a) {
; CHECK-LABEL: @fold2(
-; CHECK-NEXT: [[MUL1:%.*]] = fmul fast float [[A:%.*]], 0x4006147AE0000000
+; CHECK-NEXT: [[MUL1:%.*]] = fmul fast float [[A:%.*]], 2.760000e+00
; CHECK-NEXT: ret float [[MUL1]]
;
%mul = fmul float %a, 0x3FF3333340000000
@@ -559,7 +559,7 @@ define <2 x float> @fneg2_vec_poison(<2 x float> %x) {
; X/C1 / C2 => X * (1/(C2*C1))
define float @fdiv1(float %x) {
; CHECK-LABEL: @fdiv1(
-; CHECK-NEXT: [[DIV1:%.*]] = fmul fast float [[X:%.*]], 0x3FD7303B60000000
+; CHECK-NEXT: [[DIV1:%.*]] = fmul fast float [[X:%.*]], f0x3EB981DB
; CHECK-NEXT: ret float [[DIV1]]
;
%div = fdiv fast float %x, 0x3FF3333340000000
@@ -573,7 +573,7 @@ define float @fdiv1(float %x) {
; X*C1 / C2 => X * (C1/C2)
define float @fdiv2(float %x) {
; CHECK-LABEL: @fdiv2(
-; CHECK-NEXT: [[DIV1:%.*]] = fmul fast float [[X:%.*]], 0x3FE0B21660000000
+; CHECK-NEXT: [[DIV1:%.*]] = fmul fast float [[X:%.*]], f0x3F0590B3
; CHECK-NEXT: ret float [[DIV1]]
;
%mul = fmul float %x, 0x3FF3333340000000
@@ -599,8 +599,8 @@ define <2 x float> @fdiv2_vec(<2 x float> %x) {
;
define float @fdiv3(float %x) {
; CHECK-LABEL: @fdiv3(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[X:%.*]], 0x3FDBD37A80000000
-; CHECK-NEXT: [[DIV1:%.*]] = fdiv fast float [[TMP1]], 0x47EFFFFFE0000000
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[X:%.*]], f0x3EDE9BD4
+; CHECK-NEXT: [[DIV1:%.*]] = fdiv fast float [[TMP1]], f0x7F7FFFFF
; CHECK-NEXT: ret float [[DIV1]]
;
%div = fdiv fast float %x, 0x47EFFFFFE0000000
@@ -611,8 +611,8 @@ define float @fdiv3(float %x) {
; "X*C1 / C2 => X * (C1/C2)" is disabled if C1/C2 is a denormal
define float @fdiv4(float %x) {
; CHECK-LABEL: @fdiv4(
-; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X:%.*]], 0x47EFFFFFE0000000
-; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[MUL]], 0x3FC99999A0000000
+; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X:%.*]], f0x7F7FFFFF
+; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[MUL]], 2.000000e-01
; CHECK-NEXT: ret float [[DIV]]
;
%mul = fmul float %x, 0x47EFFFFFE0000000
diff --git a/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll b/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll
index 7affd9215d0b7..670ed619fe04c 100644
--- a/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll
+++ b/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll
@@ -11,7 +11,7 @@ define void @denormal_input_preserve_sign_fcmp_olt_smallest_normalized(float %f3
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
; CHECK-NEXT: [[CMPF64:%.*]] = fcmp oeq double [[F64:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp oeq half [[F16:%.*]], 0xH0000
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp oeq half [[F16:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: [[CMPF32_FLAGS:%.*]] = fcmp oeq float [[F32]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF32_FLAGS]], ptr @var, align 1
@@ -44,7 +44,7 @@ define void @denormal_input_preserve_sign_fcmp_uge_smallest_normalized(float %f3
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
; CHECK-NEXT: [[CMPF64:%.*]] = fcmp une double [[F64:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp une half [[F16:%.*]], 0xH0000
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp une half [[F16:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: ret void
;
@@ -70,7 +70,7 @@ define void @denormal_input_preserve_sign_fcmp_oge_smallest_normalized(float %f3
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
; CHECK-NEXT: [[CMPF64:%.*]] = fcmp one double [[F64:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp one half [[F16:%.*]], 0xH0000
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp one half [[F16:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: ret void
;
@@ -96,7 +96,7 @@ define void @denormal_input_preserve_sign_fcmp_ult_smallest_normalized(float %f3
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
; CHECK-NEXT: [[CMPF64:%.*]] = fcmp ueq double [[F64:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp ueq half [[F16:%.*]], 0xH0000
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp ueq half [[F16:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: ret void
;
@@ -218,7 +218,7 @@ define void @denormal_input_positive_zero_fcmp_olt_smallest_normalized(float %f3
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
; CHECK-NEXT: [[CMPF64:%.*]] = fcmp oeq double [[F64:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp oeq half [[F16:%.*]], 0xH0000
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp oeq half [[F16:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: ret void
;
@@ -240,13 +240,13 @@ define void @denormal_input_positive_zero_fcmp_olt_smallest_normalized(float %f3
define void @denormal_input_ieee(float %f32, double %f64, half %f16) #2 {
; CHECK-LABEL: @denormal_input_ieee(
; CHECK-NEXT: [[F32_FABS:%.*]] = call float @llvm.fabs.f32(float [[F32:%.*]])
-; CHECK-NEXT: [[CMPF32:%.*]] = fcmp olt float [[F32_FABS]], 0x3810000000000000
+; CHECK-NEXT: [[CMPF32:%.*]] = fcmp olt float [[F32_FABS]], f0x00800000
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
; CHECK-NEXT: [[F64_FABS:%.*]] = call double @llvm.fabs.f64(double [[F64:%.*]])
-; CHECK-NEXT: [[CMPF64:%.*]] = fcmp olt double [[F64_FABS]], 0x10000000000000
+; CHECK-NEXT: [[CMPF64:%.*]] = fcmp olt double [[F64_FABS]], f0x0010000000000000
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
; CHECK-NEXT: [[F16_FABS:%.*]] = call half @llvm.fabs.f16(half [[F16:%.*]])
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp olt half [[F16_FABS]], 0xH0400
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp olt half [[F16_FABS]], 6.103520e-05
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: ret void
;
@@ -270,10 +270,10 @@ define void @denormal_input_preserve_sign_f32_only(float %f32, double %f64, half
; CHECK-NEXT: [[CMPF32:%.*]] = fcmp oeq float [[F32:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
; CHECK-NEXT: [[F64_FABS:%.*]] = call double @llvm.fabs.f64(double [[F64:%.*]])
-; CHECK-NEXT: [[CMPF64:%.*]] = fcmp olt double [[F64_FABS]], 0x10000000000000
+; CHECK-NEXT: [[CMPF64:%.*]] = fcmp olt double [[F64_FABS]], f0x0010000000000000
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
; CHECK-NEXT: [[F16_FABS:%.*]] = call half @llvm.fabs.f16(half [[F16:%.*]])
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp olt half [[F16_FABS]], 0xH0400
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp olt half [[F16_FABS]], 6.103520e-05
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: ret void
;
@@ -294,13 +294,13 @@ define void @denormal_input_preserve_sign_f32_only(float %f32, double %f64, half
define void @wrong_fcmp_type_ole(float %f32, double %f64, half %f16) #0 {
; CHECK-LABEL: @wrong_fcmp_type_ole(
; CHECK-NEXT: [[F32_FABS:%.*]] = call float @llvm.fabs.f32(float [[F32:%.*]])
-; CHECK-NEXT: [[CMPF32:%.*]] = fcmp ole float [[F32_FABS]], 0x3810000000000000
+; CHECK-NEXT: [[CMPF32:%.*]] = fcmp ole float [[F32_FABS]], f0x00800000
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
; CHECK-NEXT: [[F64_FABS:%.*]] = call double @llvm.fabs.f64(double [[F64:%.*]])
-; CHECK-NEXT: [[CMPF64:%.*]] = fcmp ole double [[F64_FABS]], 0x10000000000000
+; CHECK-NEXT: [[CMPF64:%.*]] = fcmp ole double [[F64_FABS]], f0x0010000000000000
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
; CHECK-NEXT: [[F16_FABS:%.*]] = call half @llvm.fabs.f16(half [[F16:%.*]])
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp ole half [[F16_FABS]], 0xH0400
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp ole half [[F16_FABS]], 6.103520e-05
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: ret void
;
@@ -320,11 +320,11 @@ define void @wrong_fcmp_type_ole(float %f32, double %f64, half %f16) #0 {
define void @missing_fabs(float %f32, double %f64, half %f16) #0 {
; CHECK-LABEL: @missing_fabs(
-; CHECK-NEXT: [[CMPF32:%.*]] = fcmp olt float [[F32:%.*]], 0x3810000000000000
+; CHECK-NEXT: [[CMPF32:%.*]] = fcmp olt float [[F32:%.*]], f0x00800000
; CHECK-NEXT: store volatile i1 [[CMPF32]], ptr @var, align 1
-; CHECK-NEXT: [[CMPF64:%.*]] = fcmp olt double [[F64:%.*]], 0x10000000000000
+; CHECK-NEXT: [[CMPF64:%.*]] = fcmp olt double [[F64:%.*]], f0x0010000000000000
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
-; CHECK-NEXT: [[CMPF16:%.*]] = fcmp olt half [[F16:%.*]], 0xH0400
+; CHECK-NEXT: [[CMPF16:%.*]] = fcmp olt half [[F16:%.*]], 6.103520e-05
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll b/llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
index 5a181ead4016c..27e7711dad7ce 100644
--- a/llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
+++ b/llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
@@ -7,7 +7,7 @@ define i1 @test_and_olt(float %x) {
; CHECK-LABEL: define i1 @test_and_olt(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp olt float %x, 0x3C00000000000000
@@ -20,7 +20,7 @@ define i1 @test_and_ole(float %x) {
; CHECK-LABEL: define i1 @test_and_ole(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp ole float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp ole float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp ole float %x, 0x3C00000000000000
@@ -33,7 +33,7 @@ define i1 @test_or_ogt(float %x) {
; CHECK-LABEL: define i1 @test_or_ogt(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp ogt float %x, 0x3C00000000000000
@@ -46,7 +46,7 @@ define i1 @test_or_oge(float %x) {
; CHECK-LABEL: define i1 @test_or_oge(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp oge float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp oge float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp oge float %x, 0x3C00000000000000
@@ -59,7 +59,7 @@ define i1 @test_and_ult(float %x) {
; CHECK-LABEL: define i1 @test_and_ult(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp ult float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp ult float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp ult float %x, 0x3C00000000000000
@@ -72,7 +72,7 @@ define i1 @test_and_ule(float %x) {
; CHECK-LABEL: define i1 @test_and_ule(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp ule float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp ule float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp ule float %x, 0x3C00000000000000
@@ -85,7 +85,7 @@ define i1 @test_or_ugt(float %x) {
; CHECK-LABEL: define i1 @test_or_ugt(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp ugt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp ugt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp ugt float %x, 0x3C00000000000000
@@ -98,7 +98,7 @@ define i1 @test_or_uge(float %x) {
; CHECK-LABEL: define i1 @test_or_uge(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp uge float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp uge float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp uge float %x, 0x3C00000000000000
@@ -111,7 +111,7 @@ define i1 @test_and_olt_commuted(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_commuted(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp olt float %x, 0x3C00000000000000
@@ -124,7 +124,7 @@ define i1 @test_and_olt_subnormal(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_subnormal(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x36A0000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 1.401300e-45
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp olt float %x, 0x36A0000000000000
@@ -137,7 +137,7 @@ define i1 @test_and_olt_infinity(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_infinity(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp one float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp one float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp olt float %x, 0x7FF0000000000000
@@ -173,7 +173,7 @@ define i1 @test_and_olt_logical(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_logical(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp olt float %x, 0x3C00000000000000
@@ -186,7 +186,7 @@ define <2 x i1> @test_and_olt_poison(<2 x float> %x) {
; CHECK-LABEL: define <2 x i1> @test_and_olt_poison(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp olt <2 x float> [[TMP1]], splat (float 0x3C00000000000000)
+; CHECK-NEXT: [[COND:%.*]] = fcmp olt <2 x float> [[TMP1]], splat (float f0x20000000)
; CHECK-NEXT: ret <2 x i1> [[COND]]
;
%cmp1 = fcmp olt <2 x float> %x, <float 0x3C00000000000000, float poison>
@@ -254,7 +254,7 @@ define i1 @test_or_olt(float %x) {
; CHECK-LABEL: define i1 @test_or_olt(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[TMP1]], 0xBC00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[TMP1]], f0xA0000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp olt float %x, 0x3C00000000000000
@@ -268,9 +268,9 @@ define i1 @test_or_olt(float %x) {
define i1 @test_and_olt_multiuse(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_multiuse(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0x3C00000000000000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], f0x20000000
; CHECK-NEXT: call void @use(i1 [[CMP1]])
-; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[X]], 0xBC00000000000000
+; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[X]], f0xA0000000
; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: ret i1 [[COND]]
;
@@ -284,8 +284,8 @@ define i1 @test_and_olt_multiuse(float %x) {
define i1 @test_and_olt_mismatched_lhs(float %x, float %y) {
; CHECK-LABEL: define i1 @test_and_olt_mismatched_lhs(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0x3C00000000000000
-; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[Y]], 0xBC00000000000000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], f0x20000000
+; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[Y]], f0xA0000000
; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: ret i1 [[COND]]
;
@@ -309,8 +309,8 @@ define i1 @test_and_olt_same_sign(float %x) {
define i1 @test_and_olt_mismatched_mag(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_mismatched_mag(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0x3C80000000000000
-; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[X]], 0xBC00000000000000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], f0x24000000
+; CHECK-NEXT: [[CMP2:%.*]] = fcmp ogt float [[X]], f0xA0000000
; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: ret i1 [[COND]]
;
@@ -323,8 +323,8 @@ define i1 @test_and_olt_mismatched_mag(float %x) {
define i1 @test_and_olt_wrong_pred2(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_wrong_pred2(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0x3C00000000000000
-; CHECK-NEXT: [[CMP2:%.*]] = fcmp oge float [[X]], 0xBC00000000000000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], f0x20000000
+; CHECK-NEXT: [[CMP2:%.*]] = fcmp oge float [[X]], f0xA0000000
; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: ret i1 [[COND]]
;
@@ -338,7 +338,7 @@ define i1 @test_and_olt_fmf_propagation(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_fmf_propagation(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp nnan ninf nsz olt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp nnan ninf nsz olt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp nsz nnan ninf olt float %x, 0x3C00000000000000
@@ -351,7 +351,7 @@ define i1 @test_and_olt_fmf_propagation_union(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_fmf_propagation_union(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp nnan ninf nsz olt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp nnan ninf nsz olt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp nnan ninf olt float %x, 0x3C00000000000000
@@ -364,7 +364,7 @@ define i1 @test_and_olt_fmf_propagation_union_logical_rhs_poison(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_fmf_propagation_union_logical_rhs_poison(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp ninf olt float %x, 0x3C00000000000000
@@ -377,7 +377,7 @@ define i1 @test_and_olt_fmf_propagation_union_logical_lhs_poison(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_fmf_propagation_union_logical_lhs_poison(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call ninf float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp ninf olt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp ninf olt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp olt float %x, 0x3C00000000000000
@@ -390,7 +390,7 @@ define i1 @test_and_olt_fmf_propagation_union_logical_both_poison(float %x) {
; CHECK-LABEL: define i1 @test_and_olt_fmf_propagation_union_logical_both_poison(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call ninf float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp ninf olt float [[TMP1]], 0x3C00000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp ninf olt float [[TMP1]], f0x20000000
; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = fcmp ninf olt float %x, 0x3C00000000000000
diff --git a/llvm/test/Transforms/InstCombine/fcmp-select.ll b/llvm/test/Transforms/InstCombine/fcmp-select.ll
index 268cd4675c6cc..1d1b38fed1916 100644
--- a/llvm/test/Transforms/InstCombine/fcmp-select.ll
+++ b/llvm/test/Transforms/InstCombine/fcmp-select.ll
@@ -163,8 +163,8 @@ define i1 @test_fcmp_select_const_const(double %x) {
define i1 @test_fcmp_select_var_const(double %x, double %y) {
; CHECK-LABEL: @test_fcmp_select_var_const(
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp ule double [[X:%.*]], 0x3E80000000000000
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt double [[Y:%.*]], 0x3E80000000000000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp ule double [[X:%.*]], f0x3E80000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt double [[Y:%.*]], f0x3E80000000000000
; CHECK-NEXT: [[CMP2:%.*]] = select i1 [[CMP1]], i1 true, i1 [[TMP1]]
; CHECK-NEXT: ret i1 [[CMP2]]
;
@@ -176,8 +176,8 @@ define i1 @test_fcmp_select_var_const(double %x, double %y) {
define i1 @test_fcmp_select_var_const_fmf(double %x, double %y) {
; CHECK-LABEL: @test_fcmp_select_var_const_fmf(
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp ule double [[X:%.*]], 0x3E80000000000000
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan olt double [[Y:%.*]], 0x3E80000000000000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp ule double [[X:%.*]], f0x3E80000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan olt double [[Y:%.*]], f0x3E80000000000000
; CHECK-NEXT: [[CMP2:%.*]] = select i1 [[CMP1]], i1 true, i1 [[TMP1]]
; CHECK-NEXT: ret i1 [[CMP2]]
;
@@ -233,7 +233,7 @@ define double @test_fcmp_select_maxnum(double %x) {
define i1 @test_fcmp_select_const_const_multiuse(double %x) {
; CHECK-LABEL: @test_fcmp_select_const_const_multiuse(
; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord double [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], double 0xFFFFFFFFFFFFFFFF, double 0.000000e+00
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], double -nan(0x7FFFFFFFFFFFF), double 0.000000e+00
; CHECK-NEXT: call void @usef64(double [[SEL]])
; CHECK-NEXT: [[CMP2:%.*]] = fcmp oeq double [[SEL]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP2]]
@@ -258,8 +258,8 @@ define i1 @test_fcmp_select_const_const_unordered(double %x) {
define i1 @test_fcmp_select_var_const_unordered(double %x, double %y) {
; CHECK-LABEL: @test_fcmp_select_var_const_unordered(
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp ult double [[X:%.*]], 0x3E80000000000000
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[Y:%.*]], 0x3E80000000000000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp ult double [[X:%.*]], f0x3E80000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[Y:%.*]], f0x3E80000000000000
; CHECK-NEXT: [[CMP2:%.*]] = select i1 [[CMP1]], i1 [[TMP1]], i1 false
; CHECK-NEXT: ret i1 [[CMP2]]
;
diff --git a/llvm/test/Transforms/InstCombine/fcmp-special.ll b/llvm/test/Transforms/InstCombine/fcmp-special.ll
index 64bc86f4266c7..2c3fced216538 100644
--- a/llvm/test/Transforms/InstCombine/fcmp-special.ll
+++ b/llvm/test/Transforms/InstCombine/fcmp-special.ll
@@ -137,7 +137,7 @@ define <2 x i1> @uno_self_vec(<2 x float> %x) {
define <2 x i1> @uno_vec_with_nan(<2 x double> %x) {
; CHECK-LABEL: @uno_vec_with_nan(
-; CHECK-NEXT: [[F:%.*]] = fcmp uno <2 x double> [[X:%.*]], <double 3.000000e+00, double 0x7FF00000FFFFFFFF>
+; CHECK-NEXT: [[F:%.*]] = fcmp uno <2 x double> [[X:%.*]], <double 3.000000e+00, double +snan(0xFFFFFFFF)>
; CHECK-NEXT: ret <2 x i1> [[F]]
;
%f = fcmp uno <2 x double> %x, <double 3.0, double 0x7FF00000FFFFFFFF>
@@ -208,7 +208,7 @@ define i1 @negative_zero_oge(double %x) {
define i1 @negative_zero_uge(half %x) {
; CHECK-LABEL: @negative_zero_uge(
-; CHECK-NEXT: [[R:%.*]] = fcmp fast uge half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[R:%.*]] = fcmp fast uge half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%r = fcmp fast uge half %x, -0.0
diff --git a/llvm/test/Transforms/InstCombine/fcmp.ll b/llvm/test/Transforms/InstCombine/fcmp.ll
index 76a3ce01cb746..6c3091afcacaa 100644
--- a/llvm/test/Transforms/InstCombine/fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/fcmp.ll
@@ -33,7 +33,7 @@ define i1 @fpext_constant(float %a) {
define <2 x i1> @fpext_constant_vec_splat(<2 x half> %a) {
; CHECK-LABEL: @fpext_constant_vec_splat(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ole <2 x half> [[A:%.*]], splat (half 0xH5140)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ole <2 x half> [[A:%.*]], splat (half 4.200000e+01)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%ext = fpext <2 x half> %a to <2 x double>
@@ -44,7 +44,7 @@ define <2 x i1> @fpext_constant_vec_splat(<2 x half> %a) {
define i1 @fpext_constant_lossy(float %a) {
; CHECK-LABEL: @fpext_constant_lossy(
; CHECK-NEXT: [[EXT:%.*]] = fpext float [[A:%.*]] to double
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[EXT]], 0x3FF0000000000001
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[EXT]], f0x3FF0000000000001
; CHECK-NEXT: ret i1 [[CMP]]
;
%ext = fpext float %a to double
@@ -55,7 +55,7 @@ define i1 @fpext_constant_lossy(float %a) {
define i1 @fpext_constant_denorm(float %a) {
; CHECK-LABEL: @fpext_constant_denorm(
; CHECK-NEXT: [[EXT:%.*]] = fpext float [[A:%.*]] to double
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[EXT]], 0x36A0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[EXT]], f0x36A0000000000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%ext = fpext float %a to double
@@ -381,7 +381,7 @@ define <2 x i1> @fabs_ult_nnan(<2 x float> %a) {
define i1 @fabs_une(half %a) {
; CHECK-LABEL: @fabs_une(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ninf une half [[A:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ninf une half [[A:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%call = call half @llvm.fabs.f16(half %a)
@@ -761,7 +761,7 @@ define i1 @lossy_one(float %x, ptr %p) {
define i1 @lossy_ueq(half %x) {
; CHECK-LABEL: @lossy_ueq(
-; CHECK-NEXT: [[R:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[R:%.*]] = fcmp uno half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%e = fpext half %x to double
@@ -872,7 +872,7 @@ define i1 @lossy_ule(half %x) {
define i1 @lossy_ord(half %x) {
; CHECK-LABEL: @lossy_ord(
-; CHECK-NEXT: [[R:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[R:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%e = fpext half %x to double
@@ -882,7 +882,7 @@ define i1 @lossy_ord(half %x) {
define i1 @lossy_uno(half %x) {
; CHECK-LABEL: @lossy_uno(
-; CHECK-NEXT: [[R:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[R:%.*]] = fcmp uno half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%e = fpext half %x to float
@@ -902,7 +902,7 @@ define i1 @fneg_oeq(float %a) {
define i1 @fneg_ogt(half %a) {
; CHECK-LABEL: @fneg_ogt(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp fast olt half [[A:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp fast olt half [[A:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%fneg = fneg half %a
@@ -975,7 +975,7 @@ define i1 @fneg_uno(float %a) {
define i1 @fneg_ueq(half %a) {
; CHECK-LABEL: @fneg_ueq(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp fast ueq half [[A:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp fast ueq half [[A:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%fneg = fneg half %a
@@ -1051,7 +1051,7 @@ define i1 @fneg_oeq_swap(float %p) {
define i1 @fneg_ogt_swap(half %p) {
; CHECK-LABEL: @fneg_ogt_swap(
; CHECK-NEXT: [[A:%.*]] = fadd half [[P:%.*]], [[P]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp fast ogt half [[A]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp fast ogt half [[A]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = fadd half %p, %p ; thwart complexity-based canonicalization
@@ -1138,7 +1138,7 @@ define i1 @fneg_uno_swap(float %p) {
define i1 @fneg_ueq_swap(half %p) {
; CHECK-LABEL: @fneg_ueq_swap(
; CHECK-NEXT: [[A:%.*]] = fadd half [[P:%.*]], [[P]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp fast ueq half [[A]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp fast ueq half [[A]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = fadd half %p, %p ; thwart complexity-based canonicalization
@@ -1851,8 +1851,8 @@ define i1 @same_const_sub_uitofp_olt(i32 %x) {
define i1 @same_const_sub_no_fold_large_c(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_large_c(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to float
-; CHECK-NEXT: [[S:%.*]] = fsub float 0x417FFFFFE0000000, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[S]], 0x417FFFFFE0000000
+; CHECK-NEXT: [[S:%.*]] = fsub float f0x4BFFFFFF, [[F]]
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[S]], f0x4BFFFFFF
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to float
@@ -1888,8 +1888,8 @@ define <2 x i1> @same_const_sub_uitofp_vec_olt(<2 x i32> %x) {
define i1 @same_const_sub_no_fold_subnormal_c(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_subnormal_c(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to float
-; CHECK-NEXT: [[S:%.*]] = fsub float 0x36A0000000000000, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[S]], 0x36A0000000000000
+; CHECK-NEXT: [[S:%.*]] = fsub float 1.401300e-45, [[F]]
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[S]], 1.401300e-45
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to float
@@ -1901,8 +1901,8 @@ define i1 @same_const_sub_no_fold_subnormal_c(i32 %x) {
define i1 @same_const_sub_no_fold_wrong_mantissa_width(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_wrong_mantissa_width(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to float
-; CHECK-NEXT: [[S:%.*]] = fsub float 0x4180000000000000, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[S]], 0x4180000000000000
+; CHECK-NEXT: [[S:%.*]] = fsub float f0x4C000000, [[F]]
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[S]], f0x4C000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to float
@@ -1925,8 +1925,8 @@ define i1 @same_const_sub_sitofp_x86_fp80_eq(i32 %x) {
define i1 @same_const_sub_no_fold_x86_fp80_large_c(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_x86_fp80_large_c(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to x86_fp80
-; CHECK-NEXT: [[S:%.*]] = fsub x86_fp80 0xK403F8000000000000000, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[S]], 0xK403F8000000000000000
+; CHECK-NEXT: [[S:%.*]] = fsub x86_fp80 f0x403F8000000000000000, [[F]]
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[S]], f0x403F8000000000000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to x86_fp80
@@ -1939,8 +1939,8 @@ define i1 @same_const_sub_no_fold_x86_fp80_large_c(i32 %x) {
define i1 @same_const_sub_no_fold_ppcfp128(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_ppcfp128(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to ppc_fp128
-; CHECK-NEXT: [[S:%.*]] = fsub ppc_fp128 0xM3FF00000000000000000000000000000, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq ppc_fp128 [[S]], 0xM3FF00000000000000000000000000000
+; CHECK-NEXT: [[S:%.*]] = fsub ppc_fp128 1.000000e+00, [[F]]
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq ppc_fp128 [[S]], 1.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to ppc_fp128
@@ -2358,7 +2358,7 @@ define i1 @fcmp_sqrt_zero_olt(half %x) {
define i1 @fcmp_sqrt_zero_ult(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ult(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2368,7 +2368,7 @@ define i1 @fcmp_sqrt_zero_ult(half %x) {
define i1 @fcmp_sqrt_zero_ult_fmf(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ult_fmf(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp nsz ult half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nsz ult half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2378,7 +2378,7 @@ define i1 @fcmp_sqrt_zero_ult_fmf(half %x) {
define i1 @fcmp_sqrt_zero_ult_fmf_sqrt_ninf(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ult_fmf_sqrt_ninf(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ninf nsz ult half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ninf nsz ult half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call ninf half @llvm.sqrt.f16(half %x)
@@ -2388,7 +2388,7 @@ define i1 @fcmp_sqrt_zero_ult_fmf_sqrt_ninf(half %x) {
define i1 @fcmp_sqrt_zero_ult_nzero(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ult_nzero(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2418,7 +2418,7 @@ define <2 x i1> @fcmp_sqrt_zero_ult_vec_mixed_zero(<2 x half> %x) {
define i1 @fcmp_sqrt_zero_ole(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ole(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2428,7 +2428,7 @@ define i1 @fcmp_sqrt_zero_ole(half %x) {
define i1 @fcmp_sqrt_zero_ule(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ule(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ule half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ule half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2438,7 +2438,7 @@ define i1 @fcmp_sqrt_zero_ule(half %x) {
define i1 @fcmp_sqrt_zero_ogt(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ogt(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2448,7 +2448,7 @@ define i1 @fcmp_sqrt_zero_ogt(half %x) {
define i1 @fcmp_sqrt_zero_ugt(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ugt(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2458,7 +2458,7 @@ define i1 @fcmp_sqrt_zero_ugt(half %x) {
define i1 @fcmp_sqrt_zero_oge(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_oge(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oge half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oge half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2477,7 +2477,7 @@ define i1 @fcmp_sqrt_zero_uge(half %x) {
define i1 @fcmp_sqrt_zero_oeq(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_oeq(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2487,7 +2487,7 @@ define i1 @fcmp_sqrt_zero_oeq(half %x) {
define i1 @fcmp_sqrt_zero_ueq(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ueq(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ule half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ule half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2497,7 +2497,7 @@ define i1 @fcmp_sqrt_zero_ueq(half %x) {
define i1 @fcmp_sqrt_zero_one(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_one(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2507,7 +2507,7 @@ define i1 @fcmp_sqrt_zero_one(half %x) {
define i1 @fcmp_sqrt_zero_une(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_une(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2517,7 +2517,7 @@ define i1 @fcmp_sqrt_zero_une(half %x) {
define i1 @fcmp_sqrt_zero_ord(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ord(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oge half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oge half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2527,7 +2527,7 @@ define i1 @fcmp_sqrt_zero_ord(half %x) {
define i1 @fcmp_sqrt_zero_uno(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_uno(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2538,7 +2538,7 @@ define i1 @fcmp_sqrt_zero_uno(half %x) {
; Make sure that ninf is cleared.
define i1 @fcmp_sqrt_zero_uno_fmf(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_uno_fmf(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2548,7 +2548,7 @@ define i1 @fcmp_sqrt_zero_uno_fmf(half %x) {
define i1 @fcmp_sqrt_zero_uno_fmf_sqrt_ninf(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_uno_fmf_sqrt_ninf(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ninf ult half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ninf ult half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call ninf half @llvm.sqrt.f16(half %x)
@@ -2572,7 +2572,7 @@ define i1 @fcmp_sqrt_zero_ult_var(half %x, half %y) {
define i1 @fcmp_sqrt_zero_ult_nonzero(half %x) {
; CHECK-LABEL: @fcmp_sqrt_zero_ult_nonzero(
; CHECK-NEXT: [[SQRT:%.*]] = call half @llvm.sqrt.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[SQRT]], 0xH3C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ult half [[SQRT]], 1.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%sqrt = call half @llvm.sqrt.f16(half %x)
@@ -2760,7 +2760,7 @@ define i1 @fabs_no_fold_i32_half(i32 %a, i32 %b) {
; CHECK-NEXT: [[FB:%.*]] = uitofp i32 [[B:%.*]] to half
; CHECK-NEXT: [[SUB:%.*]] = fsub half [[FA]], [[FB]]
; CHECK-NEXT: [[ABS:%.*]] = call half @llvm.fabs.f16(half [[SUB]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt half [[ABS]], 0xH3C00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt half [[ABS]], 1.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
@@ -2807,7 +2807,7 @@ define <2 x i1> @fabs_uitofp_sub_vec_half_no_fold(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: [[FY:%.*]] = uitofp <2 x i32> [[Y:%.*]] to <2 x half>
; CHECK-NEXT: [[SUB:%.*]] = fsub <2 x half> [[FX]], [[FY]]
; CHECK-NEXT: [[ABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[SUB]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <2 x half> [[ABS]], splat (half 0xH3C00)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <2 x half> [[ABS]], splat (half 1.000000e+00)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%fx = uitofp <2 x i32> %x to <2 x half>
@@ -2825,7 +2825,7 @@ define <2 x i1> @fabs_uitofp_sub_vec_bf16_no_fold(<2 x i16> %x, <2 x i16> %y) {
; CHECK-NEXT: [[FY:%.*]] = uitofp <2 x i16> [[Y:%.*]] to <2 x bfloat>
; CHECK-NEXT: [[SUB:%.*]] = fsub <2 x bfloat> [[FX]], [[FY]]
; CHECK-NEXT: [[ABS:%.*]] = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> [[SUB]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <2 x bfloat> [[ABS]], splat (bfloat 0xR3F80)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <2 x bfloat> [[ABS]], splat (bfloat 1.000000e+00)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%fx = uitofp <2 x i16> %x to <2 x bfloat>
diff --git a/llvm/test/Transforms/InstCombine/fdim.ll b/llvm/test/Transforms/InstCombine/fdim.ll
index 5329a8f5c8488..8e2f410106784 100644
--- a/llvm/test/Transforms/InstCombine/fdim.ll
+++ b/llvm/test/Transforms/InstCombine/fdim.ll
@@ -69,7 +69,7 @@ define double @fdim_undef1() {
define double @fdim_inf_ninf() {
; CHECK-LABEL: define double @fdim_inf_ninf() {
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%dim = call double @fdim(double 0x7FF0000000000000, double 0x8000000000000000 )
ret double %dim
@@ -77,7 +77,7 @@ define double @fdim_inf_ninf() {
define double @fdim_inf() {
; CHECK-LABEL: define double @fdim_inf() {
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%dim = call double @fdim(double 0x7FF0000000000000, double 0x7FF0000000000000)
ret double %dim
@@ -102,7 +102,7 @@ define double @fdim_strictfp() {
define double @fdim_nan1() {
; CHECK-LABEL: define double @fdim_nan1() {
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%dim = call double @fdim(double 10.0, double 0x7FF8000000000000)
ret double %dim
@@ -111,7 +111,7 @@ define double @fdim_nan1() {
define double @fdim_nan2() {
; CHECK-LABEL: define double @fdim_nan2() {
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%dim = call double @fdim(double 0x7FF8000000000000, double 1.4)
ret double %dim
@@ -119,7 +119,7 @@ define double @fdim_nan2() {
define double @fdim_snan1() {
; CHECK-LABEL: define double @fdim_snan1() {
-; CHECK-NEXT: ret double 0x7FFC000000000000
+; CHECK-NEXT: ret double +nan(0x4000000000000)
;
%dim = call double @fdim(double 0x7FF4000000000000, double 1.4)
ret double %dim
@@ -127,7 +127,7 @@ define double @fdim_snan1() {
define double @fdim_snan2() {
; CHECK-LABEL: define double @fdim_snan2() {
-; CHECK-NEXT: ret double 0x7FFC000000000000
+; CHECK-NEXT: ret double +nan(0x4000000000000)
;
%dim = call double @fdim(double 1.7, double 0x7FF4000000000000)
ret double %dim
diff --git a/llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll b/llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
index 6d945ede3b387..85c6f76de5335 100644
--- a/llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
+++ b/llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
@@ -106,7 +106,7 @@ define float @fdiv_cosf_sinf_reassoc(float %a) {
define fp128 @fdiv_cosfp128_sinfp128_reassoc(fp128 %a) {
; CHECK-LABEL: @fdiv_cosfp128_sinfp128_reassoc(
; CHECK-NEXT: [[TANL:%.*]] = call reassoc fp128 @tanl(fp128 [[A:%.*]]) #[[ATTR1]]
-; CHECK-NEXT: [[DIV:%.*]] = fdiv reassoc fp128 0xL00000000000000003FFF000000000000, [[TANL]]
+; CHECK-NEXT: [[DIV:%.*]] = fdiv reassoc fp128 1.000000e+00, [[TANL]]
; CHECK-NEXT: ret fp128 [[DIV]]
;
%1 = call reassoc fp128 @llvm.cos.fp128(fp128 %a)
diff --git a/llvm/test/Transforms/InstCombine/fdiv.ll b/llvm/test/Transforms/InstCombine/fdiv.ll
index 3465781e3af9d..256bafd70ec9a 100644
--- a/llvm/test/Transforms/InstCombine/fdiv.ll
+++ b/llvm/test/Transforms/InstCombine/fdiv.ll
@@ -25,7 +25,7 @@ define float @exact_inverse(float %x) {
define float @exact_inverse2(float %x) {
; CHECK-LABEL: @exact_inverse2(
-; CHECK-NEXT: [[DIV:%.*]] = fmul float [[X:%.*]], 0x47D0000000000000
+; CHECK-NEXT: [[DIV:%.*]] = fmul float [[X:%.*]], f0x7E800000
; CHECK-NEXT: ret float [[DIV]]
;
%div = fdiv float %x, 0x3810000000000000
@@ -36,7 +36,7 @@ define float @exact_inverse2(float %x) {
define float @exact_inverse_but_denorm(float %x) {
; CHECK-LABEL: @exact_inverse_but_denorm(
-; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[X:%.*]], 0x47E0000000000000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[X:%.*]], f0x7F000000
; CHECK-NEXT: ret float [[DIV]]
;
%div = fdiv float %x, 0x47E0000000000000
@@ -47,7 +47,7 @@ define float @exact_inverse_but_denorm(float %x) {
define float @not_exact_inverse2(float %x) {
; CHECK-LABEL: @not_exact_inverse2(
-; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[X:%.*]], 0x36A0000000000000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[X:%.*]], 1.401300e-45
; CHECK-NEXT: ret float [[DIV]]
;
%div = fdiv float %x, 0x36A0000000000000
@@ -58,7 +58,7 @@ define float @not_exact_inverse2(float %x) {
define float @not_exact_but_allow_recip(float %x) {
; CHECK-LABEL: @not_exact_but_allow_recip(
-; CHECK-NEXT: [[DIV:%.*]] = fmul arcp float [[X:%.*]], 0x3FD5555560000000
+; CHECK-NEXT: [[DIV:%.*]] = fmul arcp float [[X:%.*]], f0x3EAAAAAB
; CHECK-NEXT: ret float [[DIV]]
;
%div = fdiv arcp float %x, 3.0
@@ -70,7 +70,7 @@ define float @not_exact_but_allow_recip(float %x) {
define float @not_exact_but_allow_recip_but_denorm(float %x) {
; CHECK-LABEL: @not_exact_but_allow_recip_but_denorm(
-; CHECK-NEXT: [[DIV:%.*]] = fdiv arcp float [[X:%.*]], 0x47E0000100000000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv arcp float [[X:%.*]], f0x7F000008
; CHECK-NEXT: ret float [[DIV]]
;
%div = fdiv arcp float %x, 0x47E0000100000000
@@ -99,7 +99,7 @@ define <vscale x 2 x float> @exact_inverse_scalable_splat(<vscale x 2 x float> %
define <2 x float> @not_exact_but_allow_recip_splat(<2 x float> %x) {
; CHECK-LABEL: @not_exact_but_allow_recip_splat(
-; CHECK-NEXT: [[DIV:%.*]] = fmul arcp <2 x float> [[X:%.*]], splat (float 0x3FD5555560000000)
+; CHECK-NEXT: [[DIV:%.*]] = fmul arcp <2 x float> [[X:%.*]], splat (float f0x3EAAAAAB)
; CHECK-NEXT: ret <2 x float> [[DIV]]
;
%div = fdiv arcp <2 x float> %x, <float 3.0, float 3.0>
@@ -135,7 +135,7 @@ define <2 x float> @not_exact_inverse_vec(<2 x float> %x) {
define <2 x float> @not_exact_inverse_vec_arcp(<2 x float> %x) {
; CHECK-LABEL: @not_exact_inverse_vec_arcp(
-; CHECK-NEXT: [[DIV:%.*]] = fmul arcp <2 x float> [[X:%.*]], <float 2.500000e-01, float 0x3FD5555560000000>
+; CHECK-NEXT: [[DIV:%.*]] = fmul arcp <2 x float> [[X:%.*]], <float 2.500000e-01, float f0x3EAAAAAB>
; CHECK-NEXT: ret <2 x float> [[DIV]]
;
%div = fdiv arcp <2 x float> %x, <float 4.0, float 3.0>
@@ -950,7 +950,7 @@ define float @fdiv_zero_f32(float %x) {
; https://alive2.llvm.org/ce/z/gLBFKB
define float @fdiv_nnan_zero_f32(float %x) {
; CHECK-LABEL: @fdiv_nnan_zero_f32(
-; CHECK-NEXT: [[FDIV:%.*]] = call nnan float @llvm.copysign.f32(float 0x7FF0000000000000, float [[X:%.*]])
+; CHECK-NEXT: [[FDIV:%.*]] = call nnan float @llvm.copysign.f32(float +inf, float [[X:%.*]])
; CHECK-NEXT: ret float [[FDIV]]
;
%fdiv = fdiv nnan float %x, 0.0
@@ -959,7 +959,7 @@ define float @fdiv_nnan_zero_f32(float %x) {
define <2 x float> @fdiv_nnan_zero_v2f32(<2 x float> %x) {
; CHECK-LABEL: @fdiv_nnan_zero_v2f32(
-; CHECK-NEXT: [[FDIV:%.*]] = call nnan <2 x float> @llvm.copysign.v2f32(<2 x float> splat (float 0x7FF0000000000000), <2 x float> [[X:%.*]])
+; CHECK-NEXT: [[FDIV:%.*]] = call nnan <2 x float> @llvm.copysign.v2f32(<2 x float> splat (float +inf), <2 x float> [[X:%.*]])
; CHECK-NEXT: ret <2 x float> [[FDIV]]
;
%fdiv = fdiv nnan <2 x float> %x, zeroinitializer
@@ -968,7 +968,7 @@ define <2 x float> @fdiv_nnan_zero_v2f32(<2 x float> %x) {
define float @fdiv_nnan_zero_f32_fmf(float %x) {
; CHECK-LABEL: @fdiv_nnan_zero_f32_fmf(
-; CHECK-NEXT: [[FDIV:%.*]] = call nnan nsz float @llvm.copysign.f32(float 0x7FF0000000000000, float [[X:%.*]])
+; CHECK-NEXT: [[FDIV:%.*]] = call nnan nsz float @llvm.copysign.f32(float +inf, float [[X:%.*]])
; CHECK-NEXT: ret float [[FDIV]]
;
%fdiv = fdiv nnan nsz float %x, 0.0
@@ -977,7 +977,7 @@ define float @fdiv_nnan_zero_f32_fmf(float %x) {
define <2 x float> @fdiv_nnan_zero_v2f32_fmf(<2 x float> %x) {
; CHECK-LABEL: @fdiv_nnan_zero_v2f32_fmf(
-; CHECK-NEXT: [[FDIV:%.*]] = call nnan nsz <2 x float> @llvm.copysign.v2f32(<2 x float> splat (float 0x7FF0000000000000), <2 x float> [[X:%.*]])
+; CHECK-NEXT: [[FDIV:%.*]] = call nnan nsz <2 x float> @llvm.copysign.v2f32(<2 x float> splat (float +inf), <2 x float> [[X:%.*]])
; CHECK-NEXT: ret <2 x float> [[FDIV]]
;
%fdiv = fdiv nnan nsz <2 x float> %x, zeroinitializer
@@ -995,7 +995,7 @@ define float @fdiv_nnan_neg_zero_f32(float %x) {
define double @test_positive_zero_nsz(double %X) {
; CHECK-LABEL: @test_positive_zero_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz double @llvm.copysign.f64(double 0x7FF0000000000000, double [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz double @llvm.copysign.f64(double +inf, double [[X:%.*]])
; CHECK-NEXT: ret double [[TMP1]]
;
%1 = fdiv nnan nsz double %X, 0.0
@@ -1004,7 +1004,7 @@ define double @test_positive_zero_nsz(double %X) {
define double @test_negative_zero_nsz(double %X) {
; CHECK-LABEL: @test_negative_zero_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz double @llvm.copysign.f64(double 0x7FF0000000000000, double [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz double @llvm.copysign.f64(double +inf, double [[X:%.*]])
; CHECK-NEXT: ret double [[TMP1]]
;
%1 = fdiv nnan nsz double %X, -0.0
@@ -1013,7 +1013,7 @@ define double @test_negative_zero_nsz(double %X) {
define double @test_positive_zero(double %X) {
; CHECK-LABEL: @test_positive_zero(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan double @llvm.copysign.f64(double 0x7FF0000000000000, double [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan double @llvm.copysign.f64(double +inf, double [[X:%.*]])
; CHECK-NEXT: ret double [[TMP1]]
;
%1 = fdiv nnan double %X, 0.0
@@ -1031,7 +1031,7 @@ define double @test_negative_zero(double %X) {
define <2 x double> @test_positive_zero_vector_nsz(<2 x double> %X) {
; CHECK-LABEL: @test_positive_zero_vector_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz <2 x double> @llvm.copysign.v2f64(<2 x double> splat (double 0x7FF0000000000000), <2 x double> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz <2 x double> @llvm.copysign.v2f64(<2 x double> splat (double +inf), <2 x double> [[X:%.*]])
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = fdiv nnan nsz <2 x double> %X, <double 0.0, double 0.0>
@@ -1040,7 +1040,7 @@ define <2 x double> @test_positive_zero_vector_nsz(<2 x double> %X) {
define <2 x double> @test_negative_zero_vector_nsz(<2 x double> %X) {
; CHECK-LABEL: @test_negative_zero_vector_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz <2 x double> @llvm.copysign.v2f64(<2 x double> splat (double 0x7FF0000000000000), <2 x double> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz <2 x double> @llvm.copysign.v2f64(<2 x double> splat (double +inf), <2 x double> [[X:%.*]])
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = fdiv nnan nsz <2 x double> %X, <double -0.0, double 0.0>
@@ -1049,7 +1049,7 @@ define <2 x double> @test_negative_zero_vector_nsz(<2 x double> %X) {
define <2 x double> @test_positive_zero_vector(<2 x double> %X) {
; CHECK-LABEL: @test_positive_zero_vector(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan <2 x double> @llvm.copysign.v2f64(<2 x double> splat (double 0x7FF0000000000000), <2 x double> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan <2 x double> @llvm.copysign.v2f64(<2 x double> splat (double +inf), <2 x double> [[X:%.*]])
; CHECK-NEXT: ret <2 x double> [[TMP1]]
;
%1 = fdiv nnan <2 x double> %X, <double 0.0, double 0.0>
diff --git a/llvm/test/Transforms/InstCombine/fma.ll b/llvm/test/Transforms/InstCombine/fma.ll
index e3d3e722bcc23..7d22f9f808097 100644
--- a/llvm/test/Transforms/InstCombine/fma.ll
+++ b/llvm/test/Transforms/InstCombine/fma.ll
@@ -544,7 +544,7 @@ define <2 x double> @fma_sqrt(<2 x double> %a, <2 x double> %b) {
; We do not fold constant multiplies in FMAs, as they could require rounding, unless either constant is 0.0 or 1.0.
define <2 x double> @fma_const_fmul(<2 x double> %b) {
; CHECK-LABEL: @fma_const_fmul(
-; CHECK-NEXT: [[RES:%.*]] = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double 0x4131233302898702, double 0x40C387800000D6C0>, <2 x double> <double 1.291820e-08, double 9.123000e-06>, <2 x double> [[B:%.*]])
+; CHECK-NEXT: [[RES:%.*]] = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double f0x4131233302898702, double f0x40C387800000D6C0>, <2 x double> <double 1.291820e-08, double 9.123000e-06>, <2 x double> [[B:%.*]])
; CHECK-NEXT: ret <2 x double> [[RES]]
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double 1123123.0099110012314, double 9999.0000001>, <2 x double> <double 0.0000000129182, double 0.000009123>, <2 x double> %b)
@@ -569,7 +569,7 @@ define <2 x double> @fma_const_fmul_zero2(<2 x double> %b) {
define <2 x double> @fma_const_fmul_one(<2 x double> %b) {
; CHECK-LABEL: @fma_const_fmul_one(
-; CHECK-NEXT: [[RES:%.*]] = fadd nnan nsz <2 x double> [[B:%.*]], <double 0x4131233302898702, double 0x40C387800000D6C0>
+; CHECK-NEXT: [[RES:%.*]] = fadd nnan nsz <2 x double> [[B:%.*]], <double f0x4131233302898702, double f0x40C387800000D6C0>
; CHECK-NEXT: ret <2 x double> [[RES]]
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double 1.0, double 1.0>, <2 x double> <double 1123123.0099110012314, double 9999.0000001>, <2 x double> %b)
@@ -578,7 +578,7 @@ define <2 x double> @fma_const_fmul_one(<2 x double> %b) {
define <2 x double> @fma_const_fmul_one2(<2 x double> %b) {
; CHECK-LABEL: @fma_const_fmul_one2(
-; CHECK-NEXT: [[RES:%.*]] = fadd nnan nsz <2 x double> [[B:%.*]], <double 0x4131233302898702, double 0x40C387800000D6C0>
+; CHECK-NEXT: [[RES:%.*]] = fadd nnan nsz <2 x double> [[B:%.*]], <double f0x4131233302898702, double f0x40C387800000D6C0>
; CHECK-NEXT: ret <2 x double> [[RES]]
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double 1123123.0099110012314, double 9999.0000001>, <2 x double> <double 1.0, double 1.0>, <2 x double> %b)
@@ -587,7 +587,7 @@ define <2 x double> @fma_const_fmul_one2(<2 x double> %b) {
define <2 x double> @fma_nan_and_const_0(<2 x double> %b) {
; CHECK-LABEL: @fma_nan_and_const_0(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>, <2 x double> <double 0.0000000129182, double 0.000009123>, <2 x double> %b)
ret <2 x double> %res
@@ -595,7 +595,7 @@ define <2 x double> @fma_nan_and_const_0(<2 x double> %b) {
define <2 x double> @fma_nan_and_const_1(<2 x double> %b) {
; CHECK-LABEL: @fma_nan_and_const_1(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double 0.0000000129182, double 0.000009123>, <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>, <2 x double> %b)
ret <2 x double> %res
@@ -603,7 +603,7 @@ define <2 x double> @fma_nan_and_const_1(<2 x double> %b) {
define <2 x double> @fma_nan_and_const_2(<2 x double> %b) {
; CHECK-LABEL: @fma_nan_and_const_2(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double 0.0000000129182, double 0.000009123>, <2 x double> %b, <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>)
ret <2 x double> %res
@@ -611,7 +611,7 @@ define <2 x double> @fma_nan_and_const_2(<2 x double> %b) {
define <2 x double> @fma_undef_0(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_undef_0(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double undef, double undef>, <2 x double> %b, <2 x double> %c)
ret <2 x double> %res
@@ -619,7 +619,7 @@ define <2 x double> @fma_undef_0(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fma_undef_1(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_undef_1(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> <double undef, double undef>, <2 x double> %c)
ret <2 x double> %res
@@ -627,7 +627,7 @@ define <2 x double> @fma_undef_1(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fma_undef_2(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_undef_2(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> <double undef, double undef>)
ret <2 x double> %res
@@ -635,7 +635,7 @@ define <2 x double> @fma_undef_2(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fma_partial_undef_0(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_partial_undef_0(
-; CHECK-NEXT: [[RES:%.*]] = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> [[B:%.*]], <2 x double> <double undef, double 0x4068E00A137F38C5>, <2 x double> [[C:%.*]])
+; CHECK-NEXT: [[RES:%.*]] = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> [[B:%.*]], <2 x double> <double undef, double f0x4068E00A137F38C5>, <2 x double> [[C:%.*]])
; CHECK-NEXT: ret <2 x double> [[RES]]
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double undef, double 199.00123>, <2 x double> %b, <2 x double> %c)
@@ -644,7 +644,7 @@ define <2 x double> @fma_partial_undef_0(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fma_partial_undef_1(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_partial_undef_1(
-; CHECK-NEXT: [[RES:%.*]] = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> [[B:%.*]], <2 x double> <double 0x4068E00A137F38C5, double undef>, <2 x double> [[C:%.*]])
+; CHECK-NEXT: [[RES:%.*]] = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> [[B:%.*]], <2 x double> <double f0x4068E00A137F38C5, double undef>, <2 x double> [[C:%.*]])
; CHECK-NEXT: ret <2 x double> [[RES]]
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> <double 199.00123, double undef>, <2 x double> %c)
@@ -653,7 +653,7 @@ define <2 x double> @fma_partial_undef_1(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fma_partial_undef_2(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_partial_undef_2(
-; CHECK-NEXT: [[RES:%.*]] = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> [[B:%.*]], <2 x double> [[C:%.*]], <2 x double> <double 0x4068E00A137F38C5, double undef>)
+; CHECK-NEXT: [[RES:%.*]] = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> [[B:%.*]], <2 x double> [[C:%.*]], <2 x double> <double f0x4068E00A137F38C5, double undef>)
; CHECK-NEXT: ret <2 x double> [[RES]]
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> <double 199.00123, double undef>)
@@ -663,14 +663,14 @@ define <2 x double> @fma_partial_undef_2(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fma_nan_0(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_nan_0(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>, <2 x double> %b, <2 x double> %c)
ret <2 x double> %res
}
define <2 x double> @fma_nan_1(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_nan_1(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>, <2 x double> %c)
ret <2 x double> %res
@@ -678,7 +678,7 @@ define <2 x double> @fma_nan_1(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fma_nan_2(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fma_nan_2(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>)
ret <2 x double> %res
@@ -686,7 +686,7 @@ define <2 x double> @fma_nan_2(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fmuladd_const_fmul(<2 x double> %b) {
; CHECK-LABEL: @fmuladd_const_fmul(
-; CHECK-NEXT: [[RES:%.*]] = fadd nnan nsz <2 x double> [[B:%.*]], <double 0x3F8DB6C076AD949B, double 0x3FB75A405B6E6D69>
+; CHECK-NEXT: [[RES:%.*]] = fadd nnan nsz <2 x double> [[B:%.*]], <double f0x3F8DB6C076AD949B, double f0x3FB75A405B6E6D69>
; CHECK-NEXT: ret <2 x double> [[RES]]
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> <double 1123123.0099110012314, double 9999.0000001>, <2 x double> <double 0.0000000129182, double 0.000009123>, <2 x double> %b)
@@ -695,7 +695,7 @@ define <2 x double> @fmuladd_const_fmul(<2 x double> %b) {
define <2 x double> @fmuladd_nan_and_const_0(<2 x double> %b) {
; CHECK-LABEL: @fmuladd_nan_and_const_0(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>, <2 x double> <double 0.0000000129182, double 0.000009123>, <2 x double> %b)
ret <2 x double> %res
@@ -703,7 +703,7 @@ define <2 x double> @fmuladd_nan_and_const_0(<2 x double> %b) {
define <2 x double> @fmuladd_nan_and_const_1(<2 x double> %b) {
; CHECK-LABEL: @fmuladd_nan_and_const_1(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> <double 0.0000000129182, double 0.000009123>, <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>, <2 x double> %b)
ret <2 x double> %res
@@ -711,7 +711,7 @@ define <2 x double> @fmuladd_nan_and_const_1(<2 x double> %b) {
define <2 x double> @fmuladd_nan_and_const_2(<2 x double> %b) {
; CHECK-LABEL: @fmuladd_nan_and_const_2(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> <double 0.0000000129182, double 0.000009123>, <2 x double> %b, <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>)
ret <2 x double> %res
@@ -719,7 +719,7 @@ define <2 x double> @fmuladd_nan_and_const_2(<2 x double> %b) {
define <2 x double> @fmuladd_nan_0(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fmuladd_nan_0(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>, <2 x double> %b, <2 x double> %c)
ret <2 x double> %res
@@ -727,7 +727,7 @@ define <2 x double> @fmuladd_nan_0(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fmuladd_nan_1(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fmuladd_nan_1(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> %b, <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>, <2 x double> %c)
ret <2 x double> %res
@@ -735,7 +735,7 @@ define <2 x double> @fmuladd_nan_1(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fmuladd_undef_0(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fmuladd_undef_0(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> <double undef, double undef>, <2 x double> %b, <2 x double> %c)
ret <2 x double> %res
@@ -743,7 +743,7 @@ define <2 x double> @fmuladd_undef_0(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fmuladd_undef_1(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fmuladd_undef_1(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> %b, <2 x double> <double undef, double undef>, <2 x double> %c)
ret <2 x double> %res
@@ -751,7 +751,7 @@ define <2 x double> @fmuladd_undef_1(<2 x double> %b, <2 x double> %c) {
define <2 x double> @fmuladd_undef_2(<2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: @fmuladd_undef_2(
-; CHECK-NEXT: ret <2 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double +qnan)
;
%res = call nnan nsz <2 x double> @llvm.fmuladd.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>)
ret <2 x double> %res
@@ -965,7 +965,7 @@ define <2 x half> @fma_negone_vec(<2 x half> %x, <2 x half> %y) {
define <2 x half> @fma_negone_vec_partial_undef(<2 x half> %x, <2 x half> %y) {
; CHECK-LABEL: @fma_negone_vec_partial_undef(
-; CHECK-NEXT: [[SUB:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[X:%.*]], <2 x half> <half undef, half 0xHBC00>, <2 x half> [[Y:%.*]])
+; CHECK-NEXT: [[SUB:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[X:%.*]], <2 x half> <half undef, half -1.000000e+00>, <2 x half> [[Y:%.*]])
; CHECK-NEXT: ret <2 x half> [[SUB]]
;
%sub = call <2 x half> @llvm.fma.v2f16(<2 x half> %x, <2 x half> <half undef, half -1.0>, <2 x half> %y)
@@ -989,7 +989,7 @@ define <2 x float> @fmuladd_unary_shuffle_ops(<2 x float> %x, <2 x float> %y, <2
define half @fma_non_negone(half %x, half %y) {
; CHECK-LABEL: @fma_non_negone(
-; CHECK-NEXT: [[SUB:%.*]] = call half @llvm.fma.f16(half [[X:%.*]], half 0xHBE00, half [[Y:%.*]])
+; CHECK-NEXT: [[SUB:%.*]] = call half @llvm.fma.f16(half [[X:%.*]], half -1.500000e+00, half [[Y:%.*]])
; CHECK-NEXT: ret half [[SUB]]
;
%sub = call half @llvm.fma.f16(half %x, half -1.5, half %y)
diff --git a/llvm/test/Transforms/InstCombine/fmod.ll b/llvm/test/Transforms/InstCombine/fmod.ll
index 8e970c1b49532..804812abadbbb 100644
--- a/llvm/test/Transforms/InstCombine/fmod.ll
+++ b/llvm/test/Transforms/InstCombine/fmod.ll
@@ -6,7 +6,7 @@ define float @test_inf_const(float %f) {
; CHECK-SAME: float [[F:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ABS:%.*]] = tail call float @llvm.fabs.f32(float [[F]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq float [[ABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq float [[ABS]], +inf
; CHECK-NEXT: br i1 [[ISINF]], label [[RETURN:%.*]], label [[IF_END:%.*]]
; CHECK: if.end:
; CHECK-NEXT: [[CALL:%.*]] = frem nnan float [[F]], 2.000000e+00
diff --git a/llvm/test/Transforms/InstCombine/fmul.ll b/llvm/test/Transforms/InstCombine/fmul.ll
index c62ccfbbc6510..ef802e111ce1e 100644
--- a/llvm/test/Transforms/InstCombine/fmul.ll
+++ b/llvm/test/Transforms/InstCombine/fmul.ll
@@ -634,7 +634,7 @@ define float @log2half(float %x, float %y) {
define float @log2half_commute(float %x1, float %y) {
; CHECK-LABEL: @log2half_commute(
-; CHECK-NEXT: [[X:%.*]] = fmul fast float [[X1:%.*]], 0x3FC24924A0000000
+; CHECK-NEXT: [[X:%.*]] = fmul fast float [[X1:%.*]], f0x3E124925
; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.log2.f32(float [[Y:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = fmul fast float [[TMP1]], [[X]]
; CHECK-NEXT: [[MUL:%.*]] = fsub fast float [[TMP2]], [[X]]
@@ -756,7 +756,7 @@ define <4 x float> @fdiv_constant_denominator_fmul_vec_constexpr(<4 x float> %x)
define float @fmul_constant_reassociation(float %x) {
; CHECK-LABEL: @fmul_constant_reassociation(
-; CHECK-NEXT: [[R:%.*]] = fmul reassoc nsz float [[X:%.*]], 0x3800000000000000
+; CHECK-NEXT: [[R:%.*]] = fmul reassoc nsz float [[X:%.*]], f0x00400000
; CHECK-NEXT: ret float [[R]]
;
%mul_flt_min = fmul reassoc nsz float %x, 0x3810000000000000
@@ -770,7 +770,7 @@ define float @fmul_constant_reassociation(float %x) {
define float @fdiv_constant_denominator_fmul_denorm(float %x) {
; CHECK-LABEL: @fdiv_constant_denominator_fmul_denorm(
-; CHECK-NEXT: [[T3:%.*]] = fmul fast float [[X:%.*]], 0x3760620000000000
+; CHECK-NEXT: [[T3:%.*]] = fmul fast float [[X:%.*]], 5.877050e-42
; CHECK-NEXT: ret float [[T3]]
;
%t1 = fdiv fast float %x, 2.0e+3
@@ -784,7 +784,7 @@ define float @fdiv_constant_denominator_fmul_denorm(float %x) {
define float @fdiv_constant_denominator_fmul_denorm_try_harder(float %x) {
; CHECK-LABEL: @fdiv_constant_denominator_fmul_denorm_try_harder(
-; CHECK-NEXT: [[T3:%.*]] = fdiv reassoc float [[X:%.*]], 0x47E8000000000000
+; CHECK-NEXT: [[T3:%.*]] = fdiv reassoc float [[X:%.*]], f0x7F400000
; CHECK-NEXT: ret float [[T3]]
;
%t1 = fdiv reassoc float %x, 3.0
@@ -797,7 +797,7 @@ define float @fdiv_constant_denominator_fmul_denorm_try_harder(float %x) {
define float @fdiv_constant_denominator_fmul_denorm_try_harder_extra_use(float %x) {
; CHECK-LABEL: @fdiv_constant_denominator_fmul_denorm_try_harder_extra_use(
; CHECK-NEXT: [[T1:%.*]] = fdiv float [[X:%.*]], 3.000000e+00
-; CHECK-NEXT: [[T3:%.*]] = fmul fast float [[T1]], 0x3810000000000000
+; CHECK-NEXT: [[T3:%.*]] = fmul fast float [[T1]], f0x00800000
; CHECK-NEXT: [[R:%.*]] = fadd float [[T1]], [[T3]]
; CHECK-NEXT: ret float [[R]]
;
@@ -907,8 +907,8 @@ define float @fmul_fadd_distribute_extra_use(float %x) {
define double @fmul_fadd_fdiv_distribute2(double %x) {
; CHECK-LABEL: @fmul_fadd_fdiv_distribute2(
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc double [[X:%.*]], 0x7FE8000000000000
-; CHECK-NEXT: [[T3:%.*]] = fadd reassoc double [[TMP1]], 0x34000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc double [[X:%.*]], f0x7FE8000000000000
+; CHECK-NEXT: [[T3:%.*]] = fadd reassoc double [[TMP1]], f0x0034000000000000
; CHECK-NEXT: ret double [[T3]]
;
%t1 = fdiv reassoc double %x, 3.0
@@ -922,8 +922,8 @@ define double @fmul_fadd_fdiv_distribute2(double %x) {
define double @fmul_fadd_fdiv_distribute3(double %x) {
; CHECK-LABEL: @fmul_fadd_fdiv_distribute3(
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc double [[X:%.*]], 0x7FE8000000000000
-; CHECK-NEXT: [[T3:%.*]] = fadd reassoc double [[TMP1]], 0x34000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc double [[X:%.*]], f0x7FE8000000000000
+; CHECK-NEXT: [[T3:%.*]] = fadd reassoc double [[TMP1]], f0x0034000000000000
; CHECK-NEXT: ret double [[T3]]
;
%t1 = fdiv reassoc double %x, 3.0
@@ -1278,7 +1278,7 @@ define <vscale x 2 x float> @mul_scalable_splat_zero(<vscale x 2 x float> %z) {
define half @mul_zero_nnan(half %x) {
; CHECK-LABEL: @mul_zero_nnan(
-; CHECK-NEXT: [[R:%.*]] = call nnan half @llvm.copysign.f16(half 0xH0000, half [[X:%.*]])
+; CHECK-NEXT: [[R:%.*]] = call nnan half @llvm.copysign.f16(half 0.000000e+00, half [[X:%.*]])
; CHECK-NEXT: ret half [[R]]
;
%r = fmul nnan half %x, 0.0
@@ -1300,7 +1300,7 @@ define <2 x float> @mul_zero_nnan_vec_poison(<2 x float> %x) {
define half @mul_zero(half %x) {
; CHECK-LABEL: @mul_zero(
-; CHECK-NEXT: [[R:%.*]] = fmul ninf nsz half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[R:%.*]] = fmul ninf nsz half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: ret half [[R]]
;
%r = fmul ninf nsz half %x, 0.0
@@ -1310,7 +1310,7 @@ define half @mul_zero(half %x) {
define half @mul_negzero_nnan(half %x) {
; CHECK-LABEL: @mul_negzero_nnan(
; CHECK-NEXT: [[TMP1:%.*]] = fneg nnan half [[X:%.*]]
-; CHECK-NEXT: [[R:%.*]] = call nnan half @llvm.copysign.f16(half 0xH0000, half [[TMP1]])
+; CHECK-NEXT: [[R:%.*]] = call nnan half @llvm.copysign.f16(half 0.000000e+00, half [[TMP1]])
; CHECK-NEXT: ret half [[R]]
;
%r = fmul nnan half %x, -0.0
diff --git a/llvm/test/Transforms/InstCombine/fneg.ll b/llvm/test/Transforms/InstCombine/fneg.ll
index 36852c1d2a684..dfcd7e992a18d 100644
--- a/llvm/test/Transforms/InstCombine/fneg.ll
+++ b/llvm/test/Transforms/InstCombine/fneg.ll
@@ -92,7 +92,7 @@ define float @fmul_fneg_extra_use(float %x) {
define <4 x double> @fmul_fsub_vec(<4 x double> %x) {
; CHECK-LABEL: @fmul_fsub_vec(
-; CHECK-NEXT: [[R:%.*]] = fmul <4 x double> [[X:%.*]], <double -4.200000e+01, double 0xFFF8000000000000, double 0xFFF0000000000000, double poison>
+; CHECK-NEXT: [[R:%.*]] = fmul <4 x double> [[X:%.*]], <double -4.200000e+01, double -qnan, double -inf, double poison>
; CHECK-NEXT: ret <4 x double> [[R]]
;
%m = fmul <4 x double> %x, <double 42.0, double 0x7FF8000000000000, double 0x7FF0000000000000, double poison>
@@ -102,7 +102,7 @@ define <4 x double> @fmul_fsub_vec(<4 x double> %x) {
define <4 x double> @fmul_fneg_vec(<4 x double> %x) {
; CHECK-LABEL: @fmul_fneg_vec(
-; CHECK-NEXT: [[R:%.*]] = fmul <4 x double> [[X:%.*]], <double -4.200000e+01, double 0xFFF8000000000000, double 0xFFF0000000000000, double poison>
+; CHECK-NEXT: [[R:%.*]] = fmul <4 x double> [[X:%.*]], <double -4.200000e+01, double -qnan, double -inf, double poison>
; CHECK-NEXT: ret <4 x double> [[R]]
;
%m = fmul <4 x double> %x, <double 42.0, double 0x7FF8000000000000, double 0x7FF0000000000000, double poison>
@@ -171,7 +171,7 @@ define float @fdiv_op1_constant_fneg_fmf(float %x) {
define float @fdiv_op1_constant_fneg_ninf(float %x) {
; CHECK-LABEL: @fdiv_op1_constant_fneg_ninf(
-; CHECK-NEXT: [[R:%.*]] = fdiv float [[X:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fdiv float [[X:%.*]], -inf
; CHECK-NEXT: ret float [[R]]
;
%d = fdiv float %x, 0x7FF0000000000000
@@ -243,7 +243,7 @@ define float @fdiv_op1_constant_fneg_extra_use(float %x) {
define <4 x double> @fdiv_op1_constant_fsub_vec(<4 x double> %x) {
; CHECK-LABEL: @fdiv_op1_constant_fsub_vec(
-; CHECK-NEXT: [[R:%.*]] = fdiv <4 x double> [[X:%.*]], <double 4.200000e+01, double 0x7FF800000ABCD000, double 0x7FF0000000000000, double poison>
+; CHECK-NEXT: [[R:%.*]] = fdiv <4 x double> [[X:%.*]], <double 4.200000e+01, double +nan(0xABCD000), double +inf, double poison>
; CHECK-NEXT: ret <4 x double> [[R]]
;
%d = fdiv <4 x double> %x, <double -42.0, double 0xFFF800000ABCD000, double 0xFFF0000000000000, double poison>
@@ -253,7 +253,7 @@ define <4 x double> @fdiv_op1_constant_fsub_vec(<4 x double> %x) {
define <4 x double> @fdiv_op1_constant_fneg_vec(<4 x double> %x) {
; CHECK-LABEL: @fdiv_op1_constant_fneg_vec(
-; CHECK-NEXT: [[R:%.*]] = fdiv <4 x double> [[X:%.*]], <double 4.200000e+01, double 0x7FF800000ABCD000, double 0x7FF0000000000000, double poison>
+; CHECK-NEXT: [[R:%.*]] = fdiv <4 x double> [[X:%.*]], <double 4.200000e+01, double +nan(0xABCD000), double +inf, double poison>
; CHECK-NEXT: ret <4 x double> [[R]]
;
%d = fdiv <4 x double> %x, <double -42.0, double 0xFFF800000ABCD000, double 0xFFF0000000000000, double poison>
@@ -417,7 +417,7 @@ define float @fdiv_op0_constant_fneg_extra_use(float %x) {
define <4 x double> @fdiv_op0_constant_fsub_vec(<4 x double> %x) {
; CHECK-LABEL: @fdiv_op0_constant_fsub_vec(
-; CHECK-NEXT: [[R:%.*]] = fdiv <4 x double> <double 4.200000e+01, double 0xFFF8000000000000, double 0x7FF0000000000000, double poison>, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = fdiv <4 x double> <double 4.200000e+01, double -qnan, double +inf, double poison>, [[X:%.*]]
; CHECK-NEXT: ret <4 x double> [[R]]
;
%d = fdiv <4 x double> <double -42.0, double 0x7FF8000000000000, double 0xFFF0000000000000, double poison>, %x
@@ -427,7 +427,7 @@ define <4 x double> @fdiv_op0_constant_fsub_vec(<4 x double> %x) {
define <4 x double> @fdiv_op0_constant_fneg_vec(<4 x double> %x) {
; CHECK-LABEL: @fdiv_op0_constant_fneg_vec(
-; CHECK-NEXT: [[R:%.*]] = fdiv <4 x double> <double 4.200000e+01, double 0xFFF8000000000000, double 0x7FF0000000000000, double poison>, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = fdiv <4 x double> <double 4.200000e+01, double -qnan, double +inf, double poison>, [[X:%.*]]
; CHECK-NEXT: ret <4 x double> [[R]]
;
%d = fdiv <4 x double> <double -42.0, double 0x7FF8000000000000, double 0xFFF0000000000000, double poison>, %x
diff --git a/llvm/test/Transforms/InstCombine/fold-bin-operand.ll b/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
index 55b8b79f1485a..d502830d668f0 100644
--- a/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
+++ b/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
@@ -267,7 +267,7 @@ define <4 x float> @h1(i1 %A, <4 x i32> %B) {
; CHECK-LABEL: @h1(
; CHECK-NEXT: EntryBlock:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B:%.*]] to <4 x float>
-; CHECK-NEXT: [[BC:%.*]] = select i1 [[A:%.*]], <4 x float> splat (float 0x36A0000000000000), <4 x float> [[TMP0]]
+; CHECK-NEXT: [[BC:%.*]] = select i1 [[A:%.*]], <4 x float> splat (float 1.401300e-45), <4 x float> [[TMP0]]
; CHECK-NEXT: ret <4 x float> [[BC]]
;
EntryBlock:
diff --git a/llvm/test/Transforms/InstCombine/fold-calls.ll b/llvm/test/Transforms/InstCombine/fold-calls.ll
index 5817fa7450634..b59ffb42ec0b2 100644
--- a/llvm/test/Transforms/InstCombine/fold-calls.ll
+++ b/llvm/test/Transforms/InstCombine/fold-calls.ll
@@ -2,7 +2,7 @@
; This shouldn't fold, because sin(inf) is invalid.
; CHECK-LABEL: @foo(
-; CHECK: %t = call double @sin(double 0x7FF0000000000000)
+; CHECK: %t = call double @sin(double +inf)
define double @foo() {
%t = call double @sin(double 0x7FF0000000000000)
ret double %t
@@ -10,7 +10,7 @@ define double @foo() {
; This should fold.
; CHECK-LABEL: @bar(
-; CHECK: ret double 0.0
+; CHECK: ret double 0.000000e+00
define double @bar() {
%t = call double @sin(double 0.0)
ret double %t
diff --git a/llvm/test/Transforms/InstCombine/fold-fcmp-trunc.ll b/llvm/test/Transforms/InstCombine/fold-fcmp-trunc.ll
index d42ba952ace99..8b2d6daf56e25 100644
--- a/llvm/test/Transforms/InstCombine/fold-fcmp-trunc.ll
+++ b/llvm/test/Transforms/InstCombine/fold-fcmp-trunc.ll
@@ -5,7 +5,7 @@
define i1 @fcmp_trunc(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], 0x4058FFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], f0x4058FFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -16,7 +16,7 @@ define i1 @fcmp_trunc(double %0) {
define i1 @fcmp_trunc_ult(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_ult(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ult double [[TMP0]], 0x4068FFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ult double [[TMP0]], f0x4068FFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -27,7 +27,7 @@ define i1 @fcmp_trunc_ult(double %0) {
define i1 @fcmp_trunc_ole(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_ole(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole double [[TMP0]], 0x4072C00010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole double [[TMP0]], f0x4072C00010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -38,7 +38,7 @@ define i1 @fcmp_trunc_ole(double %0) {
define i1 @fcmp_trunc_ogt(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_ogt(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], 0x4079000010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], f0x4079000010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -49,7 +49,7 @@ define i1 @fcmp_trunc_ogt(double %0) {
define i1 @fcmp_trunc_zero(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_zero(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], 0xB690000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], f0xB690000000000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -106,7 +106,7 @@ define i1 @fcmp_trunc_pair_ord(double %x, double %y) {
define i1 @fcmp_trunc_with_nnan(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_with_nnan(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp nnan oge double [[TMP0]], 0x4058FFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp nnan oge double [[TMP0]], f0x4058FFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -117,7 +117,7 @@ define i1 @fcmp_trunc_with_nnan(double %0) {
define i1 @fcmp_trunc_with_ninf(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_with_ninf(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ninf oge double [[TMP0]], 0x4058FFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ninf oge double [[TMP0]], f0x4058FFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -128,7 +128,7 @@ define i1 @fcmp_trunc_with_ninf(double %0) {
define i1 @fcmp_trunc_with_nsz(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_with_nsz(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp nsz oge double [[TMP0]], 0x4058FFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp nsz oge double [[TMP0]], f0x4058FFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -139,7 +139,7 @@ define i1 @fcmp_trunc_with_nsz(double %0) {
define i1 @fcmp_trunc_with_reassoc(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_with_reassoc(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp reassoc oge double [[TMP0]], 0x4058FFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp reassoc oge double [[TMP0]], f0x4058FFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -150,7 +150,7 @@ define i1 @fcmp_trunc_with_reassoc(double %0) {
define i1 @fcmp_trunc_with_fast(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_with_fast(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast oge double [[TMP0]], 0x4058FFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast oge double [[TMP0]], f0x4058FFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -161,7 +161,7 @@ define i1 @fcmp_trunc_with_fast(double %0) {
define <4 x i1> @fcmp_vec_trunc(<4 x double> %0) {
; CHECK-LABEL: define <4 x i1> @fcmp_vec_trunc(
; CHECK-SAME: <4 x double> [[TMP0:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x double> [[TMP0]], splat (double 0x3FEFFFFFF0000000)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x double> [[TMP0]], splat (double f0x3FEFFFFFF0000000)
; CHECK-NEXT: ret <4 x i1> [[CMP]]
;
%vec = fptrunc <4 x double> %0 to <4 x float>
@@ -172,7 +172,7 @@ define <4 x i1> @fcmp_vec_trunc(<4 x double> %0) {
define <1 x i1> @fcmp_vec_trunc_scalar(<1 x double> %0) {
; CHECK-LABEL: define <1 x i1> @fcmp_vec_trunc_scalar(
; CHECK-SAME: <1 x double> [[TMP0:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp fast olt <1 x double> [[TMP0]], splat (double 0x3FEFFFFFF0000000)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp fast olt <1 x double> [[TMP0]], splat (double f0x3FEFFFFFF0000000)
; CHECK-NEXT: ret <1 x i1> [[CMP]]
;
%vec = fptrunc <1 x double> %0 to <1 x float>
@@ -183,7 +183,7 @@ define <1 x i1> @fcmp_vec_trunc_scalar(<1 x double> %0) {
define i1 @fcmp_trunc_fp128(fp128 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_fp128(
; CHECK-SAME: fp128 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast oge fp128 [[TMP0]], 0xL000000000000000040058FFFFF000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast oge fp128 [[TMP0]], f0x40058FFFFF0000000000000000000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc fp128 %0 to float
@@ -194,7 +194,7 @@ define i1 @fcmp_trunc_fp128(fp128 %0) {
define i1 @fcmp_trunc_x86_fp80(x86_fp80 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_x86_fp80(
; CHECK-SAME: x86_fp80 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast oge x86_fp80 [[TMP0]], 0xK4005C7FFFF8000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast oge x86_fp80 [[TMP0]], f0x4005C7FFFF8000000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc x86_fp80 %0 to float
@@ -205,7 +205,7 @@ define i1 @fcmp_trunc_x86_fp80(x86_fp80 %0) {
define i1 @fcmp_trunc_ppc_fp128(ppc_fp128 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_ppc_fp128(
; CHECK-SAME: ppc_fp128 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast oge ppc_fp128 [[TMP0]], 0xM4058FFFFF00000000000000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast oge ppc_fp128 [[TMP0]], f0x00000000000000004058FFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc ppc_fp128 %0 to float
@@ -227,7 +227,7 @@ define i1 @fcmp_trunc_nan(double %0) {
define i1 @fcmp_trunc_d1(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_d1(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], 0x3690000000000001
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], f0x3690000000000001
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -239,7 +239,7 @@ define i1 @fcmp_trunc_d1(double %0) {
define i1 @fcmp_trunc_d1_ole(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_d1_ole(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole double [[TMP0]], 0x36A7FFFFFFFFFFFF
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole double [[TMP0]], f0x36A7FFFFFFFFFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -251,7 +251,7 @@ define i1 @fcmp_trunc_d1_ole(double %0) {
define i1 @fcmp_trunc_d2(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_d2(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], 0x36A8000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], f0x36A8000000000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -263,7 +263,7 @@ define i1 @fcmp_trunc_d2(double %0) {
define i1 @fcmp_trunc_d3(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_d3(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], 0x380FFFFFDFFFFFFF
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], f0x380FFFFFDFFFFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -275,7 +275,7 @@ define i1 @fcmp_trunc_d3(double %0) {
define i1 @fcmp_trunc_d4(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_d4(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], 0xB690000000000001
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], f0xB690000000000001
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -287,7 +287,7 @@ define i1 @fcmp_trunc_d4(double %0) {
define i1 @fcmp_trunc_d5(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_d5(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt double [[TMP0]], 0xB80FFFFFDFFFFFFF
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt double [[TMP0]], f0xB80FFFFFDFFFFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -300,7 +300,7 @@ define i1 @fcmp_trunc_d5(double %0) {
define i1 @fcmp_trunc_p0(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_p0(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], 0xB690000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], f0xB690000000000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -313,7 +313,7 @@ define i1 @fcmp_trunc_p0(double %0) {
define i1 @fcmp_trunc_n0(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_n0(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], 0x3690000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], f0x3690000000000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -326,7 +326,7 @@ define i1 @fcmp_trunc_n0(double %0) {
define i1 @fcmp_trunc_mx(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_mx(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], 0x47EFFFFFEFFFFFFF
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], f0x47EFFFFFEFFFFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -338,7 +338,7 @@ define i1 @fcmp_trunc_mx(double %0) {
define i1 @fcmp_trunc_mn(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_mn(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt double [[TMP0]], 0xC7EFFFFFEFFFFFFF
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt double [[TMP0]], f0xC7EFFFFFEFFFFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -361,7 +361,7 @@ define i1 @fcmp_trunc_literal_positive_inf(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_literal_positive_inf(
; CHECK-SAME: double [[TMP0:%.*]]) {
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[TMP0]] to float
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oeq float [[TRUNC]], 0x7FF0000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oeq float [[TRUNC]], +inf
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -396,7 +396,7 @@ define i1 @fcmp_trunc_inf_uge(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_inf_uge(
; CHECK-SAME: double [[TMP0:%.*]]) {
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[TMP0]] to float
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ueq float [[TRUNC]], 0x7FF0000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ueq float [[TRUNC]], +inf
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -419,7 +419,7 @@ define i1 @fcmp_trunc_ninf_olt(double %0) {
define i1 @fcmp_trunc_uge(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_uge(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp uge double [[TMP0]], 0x405EBFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp uge double [[TMP0]], f0x405EBFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -431,7 +431,7 @@ define i1 @fcmp_trunc_uge(double %0) {
define i1 @fcmp_trunc_neg_uge(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_uge(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp uge double [[TMP0]], 0xC05EC00010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp uge double [[TMP0]], f0xC05EC00010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -443,7 +443,7 @@ define i1 @fcmp_trunc_neg_uge(double %0) {
define i1 @fcmp_trunc_oge(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_oge(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], 0x405EBFFFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], f0x405EBFFFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -455,7 +455,7 @@ define i1 @fcmp_trunc_oge(double %0) {
define i1 @fcmp_trunc_neg_oge(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_oge(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], 0xC05EC00010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge double [[TMP0]], f0xC05EC00010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -467,7 +467,7 @@ define i1 @fcmp_trunc_neg_oge(double %0) {
define i1 @fcmp_trunc_ugt(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_ugt(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ugt double [[TMP0]], 0x40FE0F3010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ugt double [[TMP0]], f0x40FE0F3010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -479,7 +479,7 @@ define i1 @fcmp_trunc_ugt(double %0) {
define i1 @fcmp_trunc_neg_ugt(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_ugt(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ugt double [[TMP0]], 0xC0FE1B8FF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ugt double [[TMP0]], f0xC0FE1B8FF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -491,7 +491,7 @@ define i1 @fcmp_trunc_neg_ugt(double %0) {
define i1 @fcmp_trunc_neg_ogt(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_ogt(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], 0xC0FE1B8FF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ogt double [[TMP0]], f0xC0FE1B8FF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -504,7 +504,7 @@ define i1 @fcmp_trunc_neg_ogt(double %0) {
define i1 @fcmp_trunc_ule(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_ule(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ule double [[TMP0]], 0x408ED80010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ule double [[TMP0]], f0x408ED80010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -517,7 +517,7 @@ define i1 @fcmp_trunc_ule(double %0) {
define i1 @fcmp_trunc_neg_ule(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_ule(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ule double [[TMP0]], 0xC088A7FFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ule double [[TMP0]], f0xC088A7FFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -530,7 +530,7 @@ define i1 @fcmp_trunc_neg_ule(double %0) {
define i1 @fcmp_trunc_neg_ole(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_ole(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole double [[TMP0]], 0xC088A7FFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole double [[TMP0]], f0xC088A7FFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -542,7 +542,7 @@ define i1 @fcmp_trunc_neg_ole(double %0) {
define i1 @fcmp_trunc_neg_ult(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_ult(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ult double [[TMP0]], 0xC088A80010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ult double [[TMP0]], f0xC088A80010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -555,7 +555,7 @@ define i1 @fcmp_trunc_neg_ult(double %0) {
define i1 @fcmp_trunc_olt(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_olt(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt double [[TMP0]], 0x408ED7FFF0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt double [[TMP0]], f0x408ED7FFF0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -568,7 +568,7 @@ define i1 @fcmp_trunc_olt(double %0) {
define i1 @fcmp_trunc_neg_olt(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_olt(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt double [[TMP0]], 0xC088A80010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt double [[TMP0]], f0xC088A80010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -580,7 +580,7 @@ define i1 @fcmp_trunc_neg_olt(double %0) {
define i1 @fcmp_trunc_neg_nsz_uge(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_nsz_uge(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp nsz uge double [[TMP0]], 0xC05EC00010000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp nsz uge double [[TMP0]], f0xC05EC00010000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -593,7 +593,7 @@ define i1 @fcmp_trunc_neg_nsz_uge(double %0) {
define i1 @fcmp_trunc_reassoc_ugt(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_reassoc_ugt(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp reassoc ugt double [[TMP0]], 0x40889F8210000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp reassoc ugt double [[TMP0]], f0x40889F8210000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -605,7 +605,7 @@ define i1 @fcmp_trunc_reassoc_ugt(double %0) {
define i1 @fcmp_trunc_neg_reassoc_ugt(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_reassoc_ugt(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp reassoc ugt double [[TMP0]], 0xC0889F81F0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp reassoc ugt double [[TMP0]], f0xC0889F81F0000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -618,7 +618,7 @@ define i1 @fcmp_trunc_neg_reassoc_ugt(double %0) {
define i1 @fcmp_trunc_fast_ult(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_fast_ult(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast uge double [[TMP0]], 0x40F8E8E010000001
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast uge double [[TMP0]], f0x40F8E8E010000001
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -630,7 +630,7 @@ define i1 @fcmp_trunc_fast_ult(double %0) {
define i1 @fcmp_trunc_neg_fast_ult(double %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_neg_fast_ult(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast uge double [[TMP0]], 0xC0F8E8E02FFFFFFF
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp fast uge double [[TMP0]], f0xC0F8E8E02FFFFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc double %0 to float
@@ -643,7 +643,7 @@ define i1 @fcmp_trunc_neg_fast_ult(double %0) {
define i1 @fcmp_trunc_mx_fp128(fp128 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_mx_fp128(
; CHECK-SAME: fp128 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole fp128 [[TMP0]], 0xLFFFFFFFFFFFFFFFF407EFFFFFEFFFFFF
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole fp128 [[TMP0]], f0x407EFFFFFEFFFFFFFFFFFFFFFFFFFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc fp128 %0 to float
@@ -656,7 +656,7 @@ define i1 @fcmp_trunc_mx_fp128(fp128 %0) {
define i1 @fcmp_trunc_mx_x86_fp80(x86_fp80 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_mx_x86_fp80(
; CHECK-SAME: x86_fp80 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ule x86_fp80 [[TMP0]], 0xK407EFFFFFF7FFFFFFFFF
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ule x86_fp80 [[TMP0]], f0x407EFFFFFF7FFFFFFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc x86_fp80 %0 to float
@@ -670,7 +670,7 @@ define i1 @fcmp_trunc_mx_ppc_fp128(ppc_fp128 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_mx_ppc_fp128(
; CHECK-SAME: ppc_fp128 [[TMP0:%.*]]) {
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc ppc_fp128 [[TMP0]] to float
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole float [[TRUNC]], 0x47EFFFFFE0000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp ole float [[TRUNC]], f0x7F7FFFFF
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc ppc_fp128 %0 to float
@@ -683,7 +683,7 @@ define i1 @fcmp_trunc_mx_ppc_fp128(ppc_fp128 %0) {
define i1 @fcmp_trunc_mn_fp128(fp128 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_mn_fp128(
; CHECK-SAME: fp128 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt fp128 [[TMP0]], 0xL0000000000000000C07EFFFFF1000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp olt fp128 [[TMP0]], f0xC07EFFFFF10000000000000000000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc fp128 %0 to float
@@ -696,7 +696,7 @@ define i1 @fcmp_trunc_mn_fp128(fp128 %0) {
define i1 @fcmp_trunc_mn_x86_fp80(x86_fp80 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_mn_x86_fp80(
; CHECK-SAME: x86_fp80 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge x86_fp80 [[TMP0]], 0xKC07EFFFFF88000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp oge x86_fp80 [[TMP0]], f0xC07EFFFFF88000000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc x86_fp80 %0 to float
@@ -709,7 +709,7 @@ define i1 @fcmp_trunc_mn_x86_fp80(x86_fp80 %0) {
define i1 @fcmp_trunc_mn_ppc_fp128(ppc_fp128 %0) {
; CHECK-LABEL: define i1 @fcmp_trunc_mn_ppc_fp128(
; CHECK-SAME: ppc_fp128 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = fcmp uge ppc_fp128 [[TMP0]], 0xMC7EFFFFF100000000000000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fcmp uge ppc_fp128 [[TMP0]], f0x0000000000000000C7EFFFFF10000000
; CHECK-NEXT: ret i1 [[RESULT]]
;
%trunc = fptrunc ppc_fp128 %0 to float
diff --git a/llvm/test/Transforms/InstCombine/fold-fops-into-selects.ll b/llvm/test/Transforms/InstCombine/fold-fops-into-selects.ll
index c986004f843ab..b147541d3d39b 100644
--- a/llvm/test/Transforms/InstCombine/fold-fops-into-selects.ll
+++ b/llvm/test/Transforms/InstCombine/fold-fops-into-selects.ll
@@ -66,7 +66,7 @@ EntryBlock:
ret float %op
; CHECK-LABEL: @test7(
; CHECK: [[OP:%.*]] = fdiv float %B, 3.000000e+00
-; CHECK: select i1 %A, float 0x3FD5555560000000, float [[OP]]
+; CHECK: select i1 %A, float f0x3EAAAAAB, float [[OP]]
}
define float @test8(i1 %A, float %B) {
diff --git a/llvm/test/Transforms/InstCombine/fold-select-fmul-if-zero.ll b/llvm/test/Transforms/InstCombine/fold-select-fmul-if-zero.ll
index 4495b0f26042b..50da75ba5abfa 100644
--- a/llvm/test/Transforms/InstCombine/fold-select-fmul-if-zero.ll
+++ b/llvm/test/Transforms/InstCombine/fold-select-fmul-if-zero.ll
@@ -371,7 +371,7 @@ define float @fmul_by_neg0_if_0_oeq_zero_f32(float %x) {
define float @fmul_by_neginf_if_0_oeq_zero_f32(float %x) {
; CHECK-LABEL: @fmul_by_neginf_if_0_oeq_zero_f32(
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[SCALED_X:%.*]] = fmul float [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[SCALED_X:%.*]] = fmul float [[X]], -inf
; CHECK-NEXT: [[SCALED_IF_DENORMAL:%.*]] = select i1 [[X_IS_ZERO]], float [[SCALED_X]], float [[X]]
; CHECK-NEXT: ret float [[SCALED_IF_DENORMAL]]
;
@@ -384,7 +384,7 @@ define float @fmul_by_neginf_if_0_oeq_zero_f32(float %x) {
define float @fmul_by_posinf_if_0_oeq_zero_f32(float %x) {
; CHECK-LABEL: @fmul_by_posinf_if_0_oeq_zero_f32(
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[SCALED_X:%.*]] = fmul float [[X]], 0x7FF0000000000000
+; CHECK-NEXT: [[SCALED_X:%.*]] = fmul float [[X]], +inf
; CHECK-NEXT: [[SCALED_IF_DENORMAL:%.*]] = select i1 [[X_IS_ZERO]], float [[SCALED_X]], float [[X]]
; CHECK-NEXT: ret float [[SCALED_IF_DENORMAL]]
;
@@ -397,7 +397,7 @@ define float @fmul_by_posinf_if_0_oeq_zero_f32(float %x) {
define float @fmul_by_qnan_if_0_oeq_zero_f32(float %x) {
; CHECK-LABEL: @fmul_by_qnan_if_0_oeq_zero_f32(
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[SCALED_IF_DENORMAL:%.*]] = select i1 [[X_IS_ZERO]], float 0x7FF8000000000000, float [[X]]
+; CHECK-NEXT: [[SCALED_IF_DENORMAL:%.*]] = select i1 [[X_IS_ZERO]], float +qnan, float [[X]]
; CHECK-NEXT: ret float [[SCALED_IF_DENORMAL]]
;
%x.is.zero = fcmp oeq float %x, 0.0
@@ -409,7 +409,7 @@ define float @fmul_by_qnan_if_0_oeq_zero_f32(float %x) {
define float @fmul_by_snan_if_0_oeq_zero_f32(float %x) {
; CHECK-LABEL: @fmul_by_snan_if_0_oeq_zero_f32(
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[SCALED_IF_DENORMAL:%.*]] = select i1 [[X_IS_ZERO]], float 0x7FF8800000000000, float [[X]]
+; CHECK-NEXT: [[SCALED_IF_DENORMAL:%.*]] = select i1 [[X_IS_ZERO]], float +nan(0x40000), float [[X]]
; CHECK-NEXT: ret float [[SCALED_IF_DENORMAL]]
;
%x.is.zero = fcmp oeq float %x, 0.0
@@ -653,7 +653,7 @@ define float @fmul_by_var_if_0_oeq_zero_f32_fmul_known_never_nan_inf_neg(float %
define float @fmul_by_var_if_0_oeq_zero_f32_assume_finite_fmul_nsz(float %x, float %y) {
; CHECK-LABEL: @fmul_by_var_if_0_oeq_zero_f32_assume_finite_fmul_nsz(
; CHECK-NEXT: [[FABS_Y:%.*]] = call float @llvm.fabs.f32(float [[Y:%.*]])
-; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[FABS_Y]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[FABS_Y]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_FINITE]])
; CHECK-NEXT: ret float [[X:%.*]]
;
@@ -670,7 +670,7 @@ define float @fmul_by_var_if_0_oeq_zero_f32_assume_finite_fmul_nsz(float %x, flo
define float @fmul_by_var_if_not_one_0_zero_f32_assume_finite_fmul_nsz(float %x, float %y) {
; CHECK-LABEL: @fmul_by_var_if_not_one_0_zero_f32_assume_finite_fmul_nsz(
; CHECK-NEXT: [[FABS_Y:%.*]] = call float @llvm.fabs.f32(float [[Y:%.*]])
-; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[FABS_Y]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[FABS_Y]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_FINITE]])
; CHECK-NEXT: ret float [[X:%.*]]
;
diff --git a/llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll b/llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
index 4695749cd7be8..0f714701b81e2 100644
--- a/llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
+++ b/llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
@@ -5,7 +5,7 @@ define i1 @f32_fcnan_fcinf(float %a) {
; CHECK-LABEL: define i1 @f32_fcnan_fcinf(
; CHECK-SAME: float [[A:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[A]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -30,7 +30,7 @@ define i1 @f32_not_fcnan_fcinf(float %a) {
; CHECK-LABEL: define i1 @f32_not_fcnan_fcinf(
; CHECK-SAME: float [[A:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[A]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -55,7 +55,7 @@ define i1 @f64_fcnan_fcinf(double %a) {
; CHECK-LABEL: define i1 @f64_fcnan_fcinf(
; CHECK-SAME: double [[A:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.fabs.f64(double [[A]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq double [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq double [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%i64 = bitcast double %a to i64
@@ -80,7 +80,7 @@ define i1 @f32_fcinf(float %a) {
; CHECK-LABEL: define i1 @f32_fcinf(
; CHECK-SAME: float [[A:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[A]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -104,7 +104,7 @@ define i1 @f32_fcinf_strictfp(float %a) strictfp {
define i1 @f32_fcposinf(float %a) {
; CHECK-LABEL: define i1 @f32_fcposinf(
; CHECK-SAME: float [[A:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[A]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[A]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -126,7 +126,7 @@ define i1 @f32_fcposinf_strictfp(float %a) strictfp {
define i1 @f32_fcneginf(float %a) {
; CHECK-LABEL: define i1 @f32_fcneginf(
; CHECK-SAME: float [[A:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[A]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[A]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -253,7 +253,7 @@ define <2 x i1> @f32_fcnan_fcinf_vec(<2 x float> %a) {
; CHECK-LABEL: define <2 x i1> @f32_fcnan_fcinf_vec(
; CHECK-SAME: <2 x float> [[A:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[A]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq <2 x float> [[TMP1]], splat (float 0x7FF0000000000000)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq <2 x float> [[TMP1]], splat (float +inf)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%i32 = bitcast <2 x float> %a to <2 x i32>
@@ -278,7 +278,7 @@ define <2 x i1> @f32_fcinf_vec(<2 x float> %a) {
; CHECK-LABEL: define <2 x i1> @f32_fcinf_vec(
; CHECK-SAME: <2 x float> [[A:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[A]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <2 x float> [[TMP1]], splat (float 0x7FF0000000000000)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <2 x float> [[TMP1]], splat (float +inf)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%i32 = bitcast <2 x float> %a to <2 x i32>
@@ -389,7 +389,7 @@ define i1 @f32_fcnan_fcinf_wrong_pred(float %a) {
; CHECK-LABEL: define i1 @f32_fcnan_fcinf_wrong_pred(
; CHECK-SAME: float [[A:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[A]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -884,7 +884,7 @@ define i1 @isnan_idiom_wrong_pred2(double %x) {
; CHECK-LABEL: define i1 @isnan_idiom_wrong_pred2(
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.fabs.f64(double [[X]])
-; CHECK-NEXT: [[RET:%.*]] = fcmp oeq double [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[RET:%.*]] = fcmp oeq double [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[RET]]
;
%bits = bitcast double %x to i64
diff --git a/llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll b/llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
index 02042b102d61e..610092901f5e9 100644
--- a/llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
+++ b/llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
@@ -29,7 +29,7 @@ define i1 @test2(double %x) {
; CHECK-LABEL: define i1 @test2(
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[X]], 0x3EB0C6F7A0000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[X]], f0x3EB0C6F7A0000000
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then:
; CHECK-NEXT: ret i1 false
@@ -50,7 +50,7 @@ define i1 @test2_or(double %x, i1 %cond) {
; CHECK-LABEL: define i1 @test2_or(
; CHECK-SAME: double [[X:%.*]], i1 [[COND:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[X]], 0x3EB0C6F7A0000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[X]], f0x3EB0C6F7A0000000
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[COND]]
; CHECK-NEXT: br i1 [[OR]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then:
@@ -78,7 +78,7 @@ define i1 @test3(float %x) {
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[X]], 3.000000e+00
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: [[RET:%.*]] = fcmp oeq float [[X]], 0x7FF0000000000000
+; CHECK-NEXT: [[RET:%.*]] = fcmp oeq float [[X]], +inf
; CHECK-NEXT: ret i1 [[RET]]
; CHECK: if.else:
; CHECK-NEXT: ret i1 false
@@ -98,7 +98,7 @@ define float @test4(float %x) {
; CHECK-LABEL: define float @test4(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[X]], 0x3EB0C6F7A0000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[X]], f0x358637BD
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then:
; CHECK-NEXT: ret float 1.000000e+00
@@ -159,7 +159,7 @@ define i1 @test6(double %x) {
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[X]], 0.000000e+00
; CHECK-NEXT: br i1 [[CMP]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
; CHECK: land.rhs:
-; CHECK-NEXT: [[CMP_I:%.*]] = fcmp oeq double [[X]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP_I:%.*]] = fcmp oeq double [[X]], +inf
; CHECK-NEXT: br label [[LAND_END]]
; CHECK: land.end:
; CHECK-NEXT: [[RET:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[CMP_I]], [[LAND_RHS]] ]
@@ -207,7 +207,7 @@ define i1 @test8(float %x) {
; CHECK-LABEL: define i1 @test8(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp oeq float [[ABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp oeq float [[ABS]], +inf
; CHECK-NEXT: br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.then:
; CHECK-NEXT: ret i1 true
@@ -459,7 +459,7 @@ define i1 @pr118257(half %v0, half %v1) {
; CHECK-LABEL: define i1 @pr118257(
; CHECK-SAME: half [[V0:%.*]], half [[V1:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp une half [[V1]], 0xH0000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp une half [[V1]], 0.000000e+00
; CHECK-NEXT: [[CAST0:%.*]] = bitcast half [[V0]] to i16
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i16 [[CAST0]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP1]], [[CMP2]]
@@ -491,7 +491,7 @@ define i1 @pr118257_is_fpclass(half %v0, half %v1) {
; CHECK-LABEL: define i1 @pr118257_is_fpclass(
; CHECK-SAME: half [[V0:%.*]], half [[V1:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP1:%.*]] = fcmp une half [[V1]], 0xH0000
+; CHECK-NEXT: [[CMP1:%.*]] = fcmp une half [[V1]], 0.000000e+00
; CHECK-NEXT: [[CMP2:%.*]] = call i1 @llvm.is.fpclass.f16(half [[V0]], i32 35)
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_END:%.*]], label [[IF_ELSE:%.*]]
diff --git a/llvm/test/Transforms/InstCombine/fpextend.ll b/llvm/test/Transforms/InstCombine/fpextend.ll
index a65b73b1ca75a..ffbdf3c033874 100644
--- a/llvm/test/Transforms/InstCombine/fpextend.ll
+++ b/llvm/test/Transforms/InstCombine/fpextend.ll
@@ -441,7 +441,7 @@ define half @bf16_to_f32_to_f16(bfloat %a) nounwind {
define bfloat @bf16_frem(bfloat %x) {
; CHECK-LABEL: @bf16_frem(
-; CHECK-NEXT: [[TMP1:%.*]] = frem bfloat [[X:%.*]], 0xR40C9
+; CHECK-NEXT: [[TMP1:%.*]] = frem bfloat [[X:%.*]], 6.281250e+00
; CHECK-NEXT: ret bfloat [[TMP1]]
;
%t1 = fpext bfloat %x to float
@@ -452,7 +452,7 @@ define bfloat @bf16_frem(bfloat %x) {
define <4 x bfloat> @v4bf16_frem_x_const(<4 x bfloat> %x) {
; CHECK-LABEL: @v4bf16_frem_x_const(
-; CHECK-NEXT: [[TMP1:%.*]] = frem <4 x bfloat> [[X:%.*]], splat (bfloat 0xR40C9)
+; CHECK-NEXT: [[TMP1:%.*]] = frem <4 x bfloat> [[X:%.*]], splat (bfloat 6.281250e+00)
; CHECK-NEXT: ret <4 x bfloat> [[TMP1]]
;
%t1 = fpext <4 x bfloat> %x to <4 x float>
@@ -463,7 +463,7 @@ define <4 x bfloat> @v4bf16_frem_x_const(<4 x bfloat> %x) {
define <4 x bfloat> @v4bf16_frem_const_x(<4 x bfloat> %x) {
; CHECK-LABEL: @v4bf16_frem_const_x(
-; CHECK-NEXT: [[TMP1:%.*]] = frem <4 x bfloat> splat (bfloat 0xR40C9), [[X:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = frem <4 x bfloat> splat (bfloat 6.281250e+00), [[X:%.*]]
; CHECK-NEXT: ret <4 x bfloat> [[TMP1]]
;
%t1 = fpext <4 x bfloat> %x to <4 x float>
diff --git a/llvm/test/Transforms/InstCombine/fptrunc.ll b/llvm/test/Transforms/InstCombine/fptrunc.ll
index 2ffb1690fa8cb..2601e3c60ee12 100644
--- a/llvm/test/Transforms/InstCombine/fptrunc.ll
+++ b/llvm/test/Transforms/InstCombine/fptrunc.ll
@@ -40,7 +40,7 @@ define <2 x float> @fdiv_constant_op0(<2 x double> %x) {
define <2 x half> @fmul_constant_op1(<2 x float> %x) {
; CHECK-LABEL: @fmul_constant_op1(
-; CHECK-NEXT: [[BO:%.*]] = fmul reassoc <2 x float> [[X:%.*]], <float 0x47EFFFFFE0000000, float 5.000000e-01>
+; CHECK-NEXT: [[BO:%.*]] = fmul reassoc <2 x float> [[X:%.*]], <float f0x7F7FFFFF, float 5.000000e-01>
; CHECK-NEXT: [[R:%.*]] = fptrunc <2 x float> [[BO]] to <2 x half>
; CHECK-NEXT: ret <2 x half> [[R]]
;
@@ -116,8 +116,8 @@ define half @fptrunc_select_true_val_extra_use(half %x, float %y, i1 %cond) {
define half @fptrunc_max(half %arg) {
; CHECK-LABEL: @fptrunc_max(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt half [[ARG:%.*]], 0xH0000
-; CHECK-NEXT: [[NARROW_SEL:%.*]] = select i1 [[CMP]], half 0xH0000, half [[ARG]]
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt half [[ARG:%.*]], 0.000000e+00
+; CHECK-NEXT: [[NARROW_SEL:%.*]] = select i1 [[CMP]], half 0.000000e+00, half [[ARG]]
; CHECK-NEXT: ret half [[NARROW_SEL]]
;
%ext = fpext half %arg to double
diff --git a/llvm/test/Transforms/InstCombine/frexp.ll b/llvm/test/Transforms/InstCombine/frexp.ll
index 6541f0d77a093..aa335c82469ad 100644
--- a/llvm/test/Transforms/InstCombine/frexp.ll
+++ b/llvm/test/Transforms/InstCombine/frexp.ll
@@ -183,7 +183,7 @@ define { float, i32 } @frexp_negtwo() {
define { float, i32 } @frexp_inf() {
; CHECK-LABEL: define { float, i32 } @frexp_inf() {
-; CHECK-NEXT: ret { float, i32 } { float 0x7FF0000000000000, i32 0 }
+; CHECK-NEXT: ret { float, i32 } { float +inf, i32 0 }
;
%ret = call { float, i32 } @llvm.frexp.f32.i32(float 0x7FF0000000000000)
ret { float, i32 } %ret
@@ -191,7 +191,7 @@ define { float, i32 } @frexp_inf() {
define { float, i32 } @frexp_neginf() {
; CHECK-LABEL: define { float, i32 } @frexp_neginf() {
-; CHECK-NEXT: ret { float, i32 } { float 0xFFF0000000000000, i32 0 }
+; CHECK-NEXT: ret { float, i32 } { float -inf, i32 0 }
;
%ret = call { float, i32 } @llvm.frexp.f32.i32(float 0xFFF0000000000000)
ret { float, i32 } %ret
@@ -199,7 +199,7 @@ define { float, i32 } @frexp_neginf() {
define { float, i32 } @frexp_qnan() {
; CHECK-LABEL: define { float, i32 } @frexp_qnan() {
-; CHECK-NEXT: ret { float, i32 } { float 0x7FF8000000000000, i32 0 }
+; CHECK-NEXT: ret { float, i32 } { float +qnan, i32 0 }
;
%ret = call { float, i32 } @llvm.frexp.f32.i32(float 0x7FF8000000000000)
ret { float, i32 } %ret
@@ -207,7 +207,7 @@ define { float, i32 } @frexp_qnan() {
define { float, i32 } @frexp_snan() {
; CHECK-LABEL: define { float, i32 } @frexp_snan() {
-; CHECK-NEXT: ret { float, i32 } { float 0x7FF8000020000000, i32 0 }
+; CHECK-NEXT: ret { float, i32 } { float +nan(0x1), i32 0 }
;
%ret = call { float, i32 } @llvm.frexp.f32.i32(float bitcast (i32 2139095041 to float))
ret { float, i32 } %ret
@@ -215,7 +215,7 @@ define { float, i32 } @frexp_snan() {
define { float, i32 } @frexp_pos_denorm() {
; CHECK-LABEL: define { float, i32 } @frexp_pos_denorm() {
-; CHECK-NEXT: ret { float, i32 } { float 0x3FEFFFFFC0000000, i32 -126 }
+; CHECK-NEXT: ret { float, i32 } { float f0x3F7FFFFE, i32 -126 }
;
%ret = call { float, i32 } @llvm.frexp.f32.i32(float bitcast (i32 8388607 to float))
ret { float, i32 } %ret
@@ -223,7 +223,7 @@ define { float, i32 } @frexp_pos_denorm() {
define { float, i32 } @frexp_neg_denorm() {
; CHECK-LABEL: define { float, i32 } @frexp_neg_denorm() {
-; CHECK-NEXT: ret { float, i32 } { float 0xBFEFFFFFC0000000, i32 -126 }
+; CHECK-NEXT: ret { float, i32 } { float f0xBF7FFFFE, i32 -126 }
;
%ret = call { float, i32 } @llvm.frexp.f32.i32(float bitcast (i32 -2139095041 to float))
ret { float, i32 } %ret
@@ -231,7 +231,7 @@ define { float, i32 } @frexp_neg_denorm() {
define { ppc_fp128, i32 } @frexp_one_ppcf128() {
; CHECK-LABEL: define { ppc_fp128, i32 } @frexp_one_ppcf128() {
-; CHECK-NEXT: ret { ppc_fp128, i32 } { ppc_fp128 0xM3FE00000000000000000000000000000, i32 1 }
+; CHECK-NEXT: ret { ppc_fp128, i32 } { ppc_fp128 5.000000e-01, i32 1 }
;
%ret = call { ppc_fp128, i32 } @llvm.frexp.ppcf128.i32(ppc_fp128 0xM3FF00000000000000000000000000000)
ret { ppc_fp128, i32 } %ret
@@ -239,7 +239,7 @@ define { ppc_fp128, i32 } @frexp_one_ppcf128() {
define { ppc_fp128, i32 } @frexp_negone_ppcf128() {
; CHECK-LABEL: define { ppc_fp128, i32 } @frexp_negone_ppcf128() {
-; CHECK-NEXT: ret { ppc_fp128, i32 } { ppc_fp128 0xMBFE00000000000000000000000000000, i32 1 }
+; CHECK-NEXT: ret { ppc_fp128, i32 } { ppc_fp128 -5.000000e-01, i32 1 }
;
%ret = call { ppc_fp128, i32 } @llvm.frexp.ppcf128.i32(ppc_fp128 0xMBFF00000000000000000000000000000)
ret { ppc_fp128, i32 } %ret
@@ -247,7 +247,7 @@ define { ppc_fp128, i32 } @frexp_negone_ppcf128() {
define { ppc_fp128, i32} @canonicalize_noncanonical_zero_1_ppcf128() {
; CHECK-LABEL: define { ppc_fp128, i32 } @canonicalize_noncanonical_zero_1_ppcf128() {
-; CHECK-NEXT: ret { ppc_fp128, i32 } { ppc_fp128 0xM00000000000000000000000000000001, i32 0 }
+; CHECK-NEXT: ret { ppc_fp128, i32 } { ppc_fp128 f0x00000000000000010000000000000000, i32 0 }
;
%ret = call { ppc_fp128, i32 } @llvm.frexp.ppcf128.i32(ppc_fp128 0xM00000000000000000000000000000001)
ret { ppc_fp128, i32 } %ret
@@ -263,7 +263,7 @@ define { <2 x float>, <2 x i32> } @frexp_splat_4() {
define { <2 x float>, <2 x i32> } @frexp_splat_qnan() {
; CHECK-LABEL: define { <2 x float>, <2 x i32> } @frexp_splat_qnan() {
-; CHECK-NEXT: ret { <2 x float>, <2 x i32> } { <2 x float> splat (float 0x7FF8000000000000), <2 x i32> zeroinitializer }
+; CHECK-NEXT: ret { <2 x float>, <2 x i32> } { <2 x float> splat (float +qnan), <2 x i32> zeroinitializer }
;
%ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>)
ret { <2 x float>, <2 x i32> } %ret
@@ -271,7 +271,7 @@ define { <2 x float>, <2 x i32> } @frexp_splat_qnan() {
define { <2 x float>, <2 x i32> } @frexp_splat_inf() {
; CHECK-LABEL: define { <2 x float>, <2 x i32> } @frexp_splat_inf() {
-; CHECK-NEXT: ret { <2 x float>, <2 x i32> } { <2 x float> splat (float 0x7FF0000000000000), <2 x i32> zeroinitializer }
+; CHECK-NEXT: ret { <2 x float>, <2 x i32> } { <2 x float> splat (float +inf), <2 x i32> zeroinitializer }
;
%ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>)
ret { <2 x float>, <2 x i32> } %ret
@@ -279,7 +279,7 @@ define { <2 x float>, <2 x i32> } @frexp_splat_inf() {
define { <2 x float>, <2 x i32> } @frexp_splat_neginf() {
; CHECK-LABEL: define { <2 x float>, <2 x i32> } @frexp_splat_neginf() {
-; CHECK-NEXT: ret { <2 x float>, <2 x i32> } { <2 x float> splat (float 0xFFF0000000000000), <2 x i32> zeroinitializer }
+; CHECK-NEXT: ret { <2 x float>, <2 x i32> } { <2 x float> splat (float -inf), <2 x i32> zeroinitializer }
;
%ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000>)
ret { <2 x float>, <2 x i32> } %ret
@@ -287,7 +287,7 @@ define { <2 x float>, <2 x i32> } @frexp_splat_neginf() {
define { <2 x float>, <2 x i32> } @frexp_splat_undef_inf() {
; CHECK-LABEL: define { <2 x float>, <2 x i32> } @frexp_splat_undef_inf() {
-; CHECK-NEXT: [[RET:%.*]] = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float undef, float 0x7FF0000000000000>)
+; CHECK-NEXT: [[RET:%.*]] = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float undef, float +inf>)
; CHECK-NEXT: ret { <2 x float>, <2 x i32> } [[RET]]
;
%ret = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> <float undef, float 0x7FF0000000000000>)
diff --git a/llvm/test/Transforms/InstCombine/fsub.ll b/llvm/test/Transforms/InstCombine/fsub.ll
index 28cee50d72c12..07f4f75f34923 100644
--- a/llvm/test/Transforms/InstCombine/fsub.ll
+++ b/llvm/test/Transforms/InstCombine/fsub.ll
@@ -920,7 +920,7 @@ define float @fmul_c1_use(float %x, float %y) {
define half @fdiv_c0(half %x, half %y) {
; CHECK-LABEL: @fdiv_c0(
-; CHECK-NEXT: [[M:%.*]] = fdiv half 0xH4700, [[X:%.*]]
+; CHECK-NEXT: [[M:%.*]] = fdiv half 7.000000e+00, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = fsub half [[Y:%.*]], [[M]]
; CHECK-NEXT: ret half [[R]]
;
diff --git a/llvm/test/Transforms/InstCombine/ilogb.ll b/llvm/test/Transforms/InstCombine/ilogb.ll
index e30791fe68e7b..20126278af7e7 100644
--- a/llvm/test/Transforms/InstCombine/ilogb.ll
+++ b/llvm/test/Transforms/InstCombine/ilogb.ll
@@ -75,7 +75,7 @@ define i32 @ilogb_neg_zero() {
define i32 @ilogbf_inf() {
; CHECK-LABEL: define i32 @ilogbf_inf() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float +inf)
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogbf(float 0x7FF0000000000000)
@@ -84,7 +84,7 @@ define i32 @ilogbf_inf() {
define i32 @ilogb_inf() {
; CHECK-LABEL: define i32 @ilogb_inf() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double +inf)
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogb(double 0x7FF0000000000000)
@@ -93,7 +93,7 @@ define i32 @ilogb_inf() {
define i32 @ilogbf_nan() {
; CHECK-LABEL: define i32 @ilogbf_nan() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float +qnan)
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogbf(float 0x7FF8000000000000)
@@ -102,7 +102,7 @@ define i32 @ilogbf_nan() {
define i32 @ilogb_nan() {
; CHECK-LABEL: define i32 @ilogb_nan() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double +qnan)
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogb(double 0x7FF8000000000000)
@@ -147,7 +147,7 @@ define i32 @ilogb_neg_zero_readnone() {
define i32 @ilogbf_inf_readnone() {
; CHECK-LABEL: define i32 @ilogbf_inf_readnone() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float 0x7FF0000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float +inf) #[[ATTR0]]
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogbf(float 0x7FF0000000000000) readnone
@@ -156,7 +156,7 @@ define i32 @ilogbf_inf_readnone() {
define i32 @ilogb_inf_readnone() {
; CHECK-LABEL: define i32 @ilogb_inf_readnone() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double 0x7FF0000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double +inf) #[[ATTR0]]
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogb(double 0x7FF0000000000000) readnone
@@ -165,7 +165,7 @@ define i32 @ilogb_inf_readnone() {
define i32 @ilogbf_nan_readnone() {
; CHECK-LABEL: define i32 @ilogbf_nan_readnone() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float 0x7FF8000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float +qnan) #[[ATTR0]]
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogbf(float 0x7FF8000000000000) readnone
@@ -174,7 +174,7 @@ define i32 @ilogbf_nan_readnone() {
define i32 @ilogb_nan_readnone() {
; CHECK-LABEL: define i32 @ilogb_nan_readnone() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double 0x7FF8000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double +qnan) #[[ATTR0]]
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogb(double 0x7FF8000000000000) readnone
diff --git a/llvm/test/Transforms/InstCombine/intrinsic-select.ll b/llvm/test/Transforms/InstCombine/intrinsic-select.ll
index 5678a964b6be8..e2de1971999da 100644
--- a/llvm/test/Transforms/InstCombine/intrinsic-select.ll
+++ b/llvm/test/Transforms/InstCombine/intrinsic-select.ll
@@ -284,7 +284,7 @@ entry:
define double @test_fabs_select1(double %a) {
; CHECK-LABEL: @test_fabs_select1(
; CHECK-NEXT: [[COND:%.*]] = fcmp uno double [[A:%.*]], 0.000000e+00
-; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND]], double 0x7FF8000000000000, double [[A]]
+; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND]], double +qnan, double [[A]]
; CHECK-NEXT: ret double [[SEL1]]
;
%cond = fcmp uno double %a, 0.000000e+00
@@ -297,7 +297,7 @@ define double @test_fabs_select1(double %a) {
define <2 x double> @test_fabs_select1_vec(<2 x double> %a) {
; CHECK-LABEL: @test_fabs_select1_vec(
; CHECK-NEXT: [[COND:%.*]] = fcmp uno <2 x double> [[A:%.*]], zeroinitializer
-; CHECK-NEXT: [[SEL2:%.*]] = select <2 x i1> [[COND]], <2 x double> splat (double 0x7FF8000000000000), <2 x double> [[A]]
+; CHECK-NEXT: [[SEL2:%.*]] = select <2 x i1> [[COND]], <2 x double> splat (double +qnan), <2 x double> [[A]]
; CHECK-NEXT: ret <2 x double> [[SEL2]]
;
%cond = fcmp uno <2 x double> %a, zeroinitializer
@@ -310,7 +310,7 @@ define <2 x double> @test_fabs_select1_vec(<2 x double> %a) {
define double @test_fabs_select2(double %a) {
; CHECK-LABEL: @test_fabs_select2(
; CHECK-NEXT: [[ABS1:%.*]] = call double @llvm.fabs.f64(double [[A:%.*]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq double [[ABS1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq double [[ABS1]], +inf
; CHECK-NEXT: [[ABS2:%.*]] = select i1 [[CMP]], double 0.000000e+00, double [[ABS1]]
; CHECK-NEXT: ret double [[ABS2]]
;
@@ -347,7 +347,7 @@ define double @test_fabs_select_fmf2(i1 %cond, double %a) {
define float @test_fabs_select_multiuse(i1 %cond, float %x) {
; CHECK-LABEL: @test_fabs_select_multiuse(
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], float [[X:%.*]], float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], float [[X:%.*]], float +inf
; CHECK-NEXT: call void @usef32(float [[SELECT]])
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
; CHECK-NEXT: ret float [[FABS]]
diff --git a/llvm/test/Transforms/InstCombine/is_fpclass.ll b/llvm/test/Transforms/InstCombine/is_fpclass.ll
index 70a7663e5768a..a4f7a43adf1e5 100644
--- a/llvm/test/Transforms/InstCombine/is_fpclass.ll
+++ b/llvm/test/Transforms/InstCombine/is_fpclass.ll
@@ -486,7 +486,7 @@ define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_dynamic(<2 x float> %x) den
define i1 @test_class_is_pinf_f32(float %x) {
; CHECK-LABEL: @test_class_is_pinf_f32(
-; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], 0x7FF0000000000000
+; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; fcPosInf
@@ -495,7 +495,7 @@ define i1 @test_class_is_pinf_f32(float %x) {
define i1 @test_class_is_pinf_or_nan_f32(float %x) {
; CHECK-LABEL: @test_class_is_pinf_or_nan_f32(
-; CHECK-NEXT: [[VAL:%.*]] = fcmp ueq float [[X:%.*]], 0x7FF0000000000000
+; CHECK-NEXT: [[VAL:%.*]] = fcmp ueq float [[X:%.*]], +inf
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 515) ; fcPosInf|fcNan
@@ -504,7 +504,7 @@ define i1 @test_class_is_pinf_or_nan_f32(float %x) {
define <2 x i1> @test_class_is_pinf_v2f32(<2 x float> %x) {
; CHECK-LABEL: @test_class_is_pinf_v2f32(
-; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq <2 x float> [[X:%.*]], splat (float 0x7FF0000000000000)
+; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq <2 x float> [[X:%.*]], splat (float +inf)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 512) ; fcPosInf
@@ -513,7 +513,7 @@ define <2 x i1> @test_class_is_pinf_v2f32(<2 x float> %x) {
define i1 @test_class_is_ninf_f32(float %x) {
; CHECK-LABEL: @test_class_is_ninf_f32(
-; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; fcNegInf
@@ -522,7 +522,7 @@ define i1 @test_class_is_ninf_f32(float %x) {
define i1 @test_class_is_ninf_or_nan_f32(float %x) {
; CHECK-LABEL: @test_class_is_ninf_or_nan_f32(
-; CHECK-NEXT: [[VAL:%.*]] = fcmp ueq float [[X:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[VAL:%.*]] = fcmp ueq float [[X:%.*]], -inf
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 7) ; fcNegInf|fcNan
@@ -531,7 +531,7 @@ define i1 @test_class_is_ninf_or_nan_f32(float %x) {
define <2 x i1> @test_class_is_ninf_v2f32(<2 x float> %x) {
; CHECK-LABEL: @test_class_is_ninf_v2f32(
-; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq <2 x float> [[X:%.*]], splat (float 0xFFF0000000000000)
+; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq <2 x float> [[X:%.*]], splat (float -inf)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 4) ; fcNegInf
@@ -541,7 +541,7 @@ define <2 x i1> @test_class_is_ninf_v2f32(<2 x float> %x) {
define i1 @test_class_is_inf_f32(float %x) {
; CHECK-LABEL: @test_class_is_inf_f32(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; fcInf
@@ -551,7 +551,7 @@ define i1 @test_class_is_inf_f32(float %x) {
define <2 x i1> @test_class_is_inf_v2f32(<2 x float> %x) {
; CHECK-LABEL: @test_class_is_inf_v2f32(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X:%.*]])
-; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq <2 x float> [[TMP1]], splat (float 0x7FF0000000000000)
+; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq <2 x float> [[TMP1]], splat (float +inf)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 516) ; fcInf
@@ -561,7 +561,7 @@ define <2 x i1> @test_class_is_inf_v2f32(<2 x float> %x) {
define i1 @test_class_is_inf_or_nan_f32(float %x) {
; CHECK-LABEL: @test_class_is_inf_or_nan_f32(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[VAL:%.*]] = fcmp ueq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[VAL:%.*]] = fcmp ueq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; fcInf|fcNan
@@ -953,7 +953,7 @@ define i1 @test_class_not_is_nan_multi_use(float %x, ptr %ptr) {
define i1 @test_class_not_is_inf_nan(float %x) {
; CHECK-LABEL: @test_class_not_is_inf_nan(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp one float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp one float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %x, i32 519)
@@ -1019,7 +1019,7 @@ define i1 @test_fold_or_class_f32_0(float %a) {
define i1 @test_fold_or3_class_f32_0(float %a) {
; CHECK-LABEL: @test_fold_or3_class_f32_0(
-; CHECK-NEXT: [[OR_1:%.*]] = fcmp ueq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[OR_1:%.*]] = fcmp ueq float [[A:%.*]], -inf
; CHECK-NEXT: ret i1 [[OR_1]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
@@ -1069,7 +1069,7 @@ define i1 @test_fold_or_class_f32_1(float %a) {
define i1 @test_no_fold_or_class_f32_multi_use0(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_or_class_f32_multi_use0(
-; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
; CHECK-NEXT: store i1 [[CLASS0]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CLASS0]], [[CLASS1]]
@@ -1084,7 +1084,7 @@ define i1 @test_no_fold_or_class_f32_multi_use0(float %a, ptr %ptr) {
define i1 @test_no_fold_or_class_f32_multi_use1(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_or_class_f32_multi_use1(
-; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
; CHECK-NEXT: store i1 [[CLASS1]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CLASS0]], [[CLASS1]]
@@ -1099,7 +1099,7 @@ define i1 @test_no_fold_or_class_f32_multi_use1(float %a, ptr %ptr) {
define i1 @test_fold_or_class_f32_2(float %a) {
; CHECK-LABEL: @test_fold_or_class_f32_2(
-; CHECK-NEXT: [[OR:%.*]] = fcmp ueq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[OR:%.*]] = fcmp ueq float [[A:%.*]], -inf
; CHECK-NEXT: ret i1 [[OR]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 7)
@@ -1110,7 +1110,7 @@ define i1 @test_fold_or_class_f32_2(float %a) {
define i1 @test_no_fold_or_class_f32_0(float %a, float %b) {
; CHECK-LABEL: @test_no_fold_or_class_f32_0(
-; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], i32 8)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[OR]]
@@ -1254,7 +1254,7 @@ define i1 @test_no_fold_and_class_f32_multi_use1(float %a, ptr %ptr) {
define i1 @test_fold_and_class_f32_2(float %a) {
; CHECK-LABEL: @test_fold_and_class_f32_2(
-; CHECK-NEXT: [[AND:%.*]] = fcmp ueq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[AND:%.*]] = fcmp ueq float [[A:%.*]], -inf
; CHECK-NEXT: ret i1 [[AND]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 7)
@@ -1287,7 +1287,7 @@ define i1 @test_fold_and_class_f32_4(float %a) {
define i1 @test_no_fold_and_class_f32_0(float %a, float %b) {
; CHECK-LABEL: @test_no_fold_and_class_f32_0(
-; CHECK-NEXT: [[CLASS0:%.*]] = fcmp ueq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS0:%.*]] = fcmp ueq float [[A:%.*]], -inf
; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], i32 15)
; CHECK-NEXT: [[AND:%.*]] = and i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -1300,7 +1300,7 @@ define i1 @test_no_fold_and_class_f32_0(float %a, float %b) {
define <2 x i1> @test_fold_and_class_v2f32(<2 x float> %a) {
; CHECK-LABEL: @test_fold_and_class_v2f32(
-; CHECK-NEXT: [[CLASS1:%.*]] = fcmp ueq <2 x float> [[A:%.*]], splat (float 0xFFF0000000000000)
+; CHECK-NEXT: [[CLASS1:%.*]] = fcmp ueq <2 x float> [[A:%.*]], splat (float -inf)
; CHECK-NEXT: ret <2 x i1> [[CLASS1]]
;
%class0 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %a, i32 7)
@@ -1326,7 +1326,7 @@ define i1 @test_fold_xor_class_f32_0(float %a) {
define i1 @test_fold_xor3_class_f32_0(float %a) {
; CHECK-LABEL: @test_fold_xor3_class_f32_0(
-; CHECK-NEXT: [[XOR_1:%.*]] = fcmp ueq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[XOR_1:%.*]] = fcmp ueq float [[A:%.*]], -inf
; CHECK-NEXT: ret i1 [[XOR_1]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
@@ -1376,7 +1376,7 @@ define i1 @test_fold_xor_class_f32_1(float %a) {
define i1 @test_no_fold_xor_class_f32_multi_use0(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_xor_class_f32_multi_use0(
-; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
; CHECK-NEXT: store i1 [[CLASS0]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[CLASS0]], [[CLASS1]]
@@ -1391,7 +1391,7 @@ define i1 @test_no_fold_xor_class_f32_multi_use0(float %a, ptr %ptr) {
define i1 @test_no_fold_xor_class_f32_multi_use1(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_xor_class_f32_multi_use1(
-; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
; CHECK-NEXT: store i1 [[CLASS1]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[CLASS0]], [[CLASS1]]
@@ -1416,7 +1416,7 @@ define i1 @test_fold_xor_class_f32_2(float %a) {
define i1 @test_no_fold_xor_class_f32_0(float %a, float %b) {
; CHECK-LABEL: @test_no_fold_xor_class_f32_0(
-; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], i32 8)
; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[XOR]]
@@ -1487,7 +1487,7 @@ define i1 @test_class_fneg_qnan(float %arg) {
; -> posinf
define i1 @test_class_fneg_neginf(float %arg) {
; CHECK-LABEL: @test_class_fneg_neginf(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[ARG:%.*]], 0x7FF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[ARG:%.*]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1564,7 +1564,7 @@ define i1 @test_class_fneg_posnormal(float %arg) {
; -> neginf
define i1 @test_class_fneg_posinf(float %arg) {
; CHECK-LABEL: @test_class_fneg_posinf(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[ARG:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[ARG:%.*]], -inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1898,7 +1898,7 @@ define i1 @test_class_fabs_posnormal(float %arg) {
define i1 @test_class_fabs_posinf(float %arg) {
; CHECK-LABEL: @test_class_fabs_posinf(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2156,7 +2156,7 @@ define i1 @test_class_fneg_fabs_qnan(float %arg) {
define i1 @test_class_fneg_fabs_neginf(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_neginf(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2530,7 +2530,7 @@ define i1 @test_class_is_normal_or_zero_nozero_src(float nofpclass(zero) %arg) {
define i1 @test_class_is_inf_or_nan_nozero_src(float nofpclass(zero) %arg) {
; CHECK-LABEL: @test_class_is_inf_or_nan_nozero_src(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 519)
@@ -2540,7 +2540,7 @@ define i1 @test_class_is_inf_or_nan_nozero_src(float nofpclass(zero) %arg) {
define i1 @test_class_is_inf_or_nan_noinf_src(float nofpclass(inf) %arg) {
; CHECK-LABEL: @test_class_is_inf_or_nan_noinf_src(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 519)
@@ -2550,7 +2550,7 @@ define i1 @test_class_is_inf_or_nan_noinf_src(float nofpclass(inf) %arg) {
define i1 @test_class_is_inf_or_nan_nonan_src(float nofpclass(nan) %arg) {
; CHECK-LABEL: @test_class_is_inf_or_nan_nonan_src(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq float [[TMP1]], 0x7FF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp ueq float [[TMP1]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 519)
@@ -2568,7 +2568,7 @@ define i1 @test_class_is_normal_or_subnormal_noinf_src(float nofpclass(inf) %arg
define i1 @test_class_is_neginf_or_nopinf_src(float nofpclass(pinf) %arg) {
; CHECK-LABEL: @test_class_is_neginf_or_nopinf_src(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[ARG:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[ARG:%.*]], -inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 4)
@@ -2593,7 +2593,7 @@ define i1 @test_class_is_neginf_noinf_src(float nofpclass(inf) %arg) {
define i1 @test_class_is_posinf_noninf_src(float nofpclass(ninf) %arg) {
; CHECK-LABEL: @test_class_is_posinf_noninf_src(
-; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[ARG:%.*]], 0x7FF0000000000000
+; CHECK-NEXT: [[CLASS:%.*]] = fcmp oeq float [[ARG:%.*]], +inf
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 512)
@@ -2740,7 +2740,7 @@ define i1 @test_class_is_nan_assume_uno(float %x) {
define i1 @test_class_is_nan_assume_not_eq_pinf(float %x) {
; CHECK-LABEL: @test_class_is_nan_assume_not_eq_pinf(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp oeq float [[X:%.*]], 0x7FF0000000000000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp oeq float [[X:%.*]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[ORD]])
; CHECK-NEXT: ret i1 false
;
diff --git a/llvm/test/Transforms/InstCombine/known-bits.ll b/llvm/test/Transforms/InstCombine/known-bits.ll
index da2123a5dfe74..acf09bc03c1eb 100644
--- a/llvm/test/Transforms/InstCombine/known-bits.ll
+++ b/llvm/test/Transforms/InstCombine/known-bits.ll
@@ -1600,7 +1600,7 @@ define i32 @test_inf_zero_only(float nofpclass(nan norm sub) %x) {
; Make sure that the signbit is cleared.
define i32 @test_ninf_only(double %x) {
; CHECK-LABEL: @test_ninf_only(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq double [[X:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq double [[X:%.*]], -inf
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.then:
; CHECK-NEXT: ret i32 0
@@ -1703,7 +1703,7 @@ if.else:
define i1 @test_simplify_icmp2(double %x) {
; CHECK-LABEL: @test_simplify_icmp2(
; CHECK-NEXT: [[ABS:%.*]] = tail call double @llvm.fabs.f64(double [[X:%.*]])
-; CHECK-NEXT: [[COND:%.*]] = fcmp oeq double [[ABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[COND:%.*]] = fcmp oeq double [[ABS]], +inf
; CHECK-NEXT: br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.then:
; CHECK-NEXT: ret i1 false
@@ -1787,7 +1787,7 @@ define i32 @test_none(float nofpclass(all) %x) {
; when the input is a negative value (except for -0).
define i1 @pr92217() {
; CHECK-LABEL: @pr92217(
-; CHECK-NEXT: [[X:%.*]] = call float @llvm.sqrt.f32(float 0xC6DEBE9E60000000)
+; CHECK-NEXT: [[X:%.*]] = call float @llvm.sqrt.f32(float f0xF6F5F4F3)
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[Y]], 0
; CHECK-NEXT: ret i1 [[CMP]]
diff --git a/llvm/test/Transforms/InstCombine/ldexp.ll b/llvm/test/Transforms/InstCombine/ldexp.ll
index 9586fffe9956c..e1fd5b45190ac 100644
--- a/llvm/test/Transforms/InstCombine/ldexp.ll
+++ b/llvm/test/Transforms/InstCombine/ldexp.ll
@@ -444,7 +444,7 @@ define float @ldexp_ldexp_different_exp_type(float %x, i32 %a, i64 %b) {
define float @ldexp_ldexp_constants(float %x) {
; CHECK-LABEL: define float @ldexp_ldexp_constants
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP1:%.*]] = fmul reassoc float [[X]], 0x41F0000000000000
+; CHECK-NEXT: [[LDEXP1:%.*]] = fmul reassoc float [[X]], f0x4F800000
; CHECK-NEXT: ret float [[LDEXP1]]
;
%ldexp0 = call reassoc float @llvm.ldexp.f32.i32(float %x, i32 8)
@@ -455,7 +455,7 @@ define float @ldexp_ldexp_constants(float %x) {
define float @ldexp_ldexp_constants_nsz(float %x) {
; CHECK-LABEL: define float @ldexp_ldexp_constants_nsz
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP1:%.*]] = fmul reassoc nsz float [[X]], 0x41F0000000000000
+; CHECK-NEXT: [[LDEXP1:%.*]] = fmul reassoc nsz float [[X]], f0x4F800000
; CHECK-NEXT: ret float [[LDEXP1]]
;
%ldexp0 = call reassoc nsz float @llvm.ldexp.f32.i32(float %x, i32 8)
@@ -466,7 +466,7 @@ define float @ldexp_ldexp_constants_nsz(float %x) {
define float @ldexp_ldexp_constants_nsz0(float %x) {
; CHECK-LABEL: define float @ldexp_ldexp_constants_nsz0
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP1:%.*]] = fmul reassoc float [[X]], 0x41F0000000000000
+; CHECK-NEXT: [[LDEXP1:%.*]] = fmul reassoc float [[X]], f0x4F800000
; CHECK-NEXT: ret float [[LDEXP1]]
;
%ldexp0 = call reassoc nsz float @llvm.ldexp.f32.i32(float %x, i32 8)
@@ -477,7 +477,7 @@ define float @ldexp_ldexp_constants_nsz0(float %x) {
define float @ldexp_ldexp_constants_nsz1(float %x) {
; CHECK-LABEL: define float @ldexp_ldexp_constants_nsz1
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP1:%.*]] = fmul reassoc nsz float [[X]], 0x41F0000000000000
+; CHECK-NEXT: [[LDEXP1:%.*]] = fmul reassoc nsz float [[X]], f0x4F800000
; CHECK-NEXT: ret float [[LDEXP1]]
;
%ldexp0 = call reassoc float @llvm.ldexp.f32.i32(float %x, i32 8)
@@ -651,7 +651,7 @@ define float @ldexp_neg150(float %x) {
define float @ldexp_neg149(float %x) {
; CHECK-LABEL: define float @ldexp_neg149
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x36A0000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 1.401300e-45
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 -149)
@@ -661,7 +661,7 @@ define float @ldexp_neg149(float %x) {
define float @ldexp_neg148(float %x) {
; CHECK-LABEL: define float @ldexp_neg148
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x36B0000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 2.802600e-45
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 -148)
@@ -671,7 +671,7 @@ define float @ldexp_neg148(float %x) {
define float @ldexp_neg127(float %x) {
; CHECK-LABEL: define float @ldexp_neg127
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x3800000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], f0x00400000
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 -127)
@@ -681,7 +681,7 @@ define float @ldexp_neg127(float %x) {
define float @ldexp_neg126(float %x) {
; CHECK-LABEL: define float @ldexp_neg126
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x3810000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], f0x00800000
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 -126)
@@ -691,7 +691,7 @@ define float @ldexp_neg126(float %x) {
define float @ldexp_neg125(float %x) {
; CHECK-LABEL: define float @ldexp_neg125
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x3820000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], f0x01000000
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 -125)
@@ -701,7 +701,7 @@ define float @ldexp_neg125(float %x) {
define float @ldexp_neg16(float %x) {
; CHECK-LABEL: define float @ldexp_neg16
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x3EF0000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], f0x37800000
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 -16)
@@ -800,7 +800,7 @@ define float @ldexp_10(float %x) {
define float @ldexp_125(float %x) {
; CHECK-LABEL: define float @ldexp_125
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x47C0000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], f0x7E000000
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 125)
@@ -810,7 +810,7 @@ define float @ldexp_125(float %x) {
define float @ldexp_126(float %x) {
; CHECK-LABEL: define float @ldexp_126
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x47D0000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], f0x7E800000
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 126)
@@ -820,7 +820,7 @@ define float @ldexp_126(float %x) {
define float @ldexp_127(float %x) {
; CHECK-LABEL: define float @ldexp_127
; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], 0x47E0000000000000
+; CHECK-NEXT: [[LDEXP:%.*]] = fmul float [[X]], f0x7F000000
; CHECK-NEXT: ret float [[LDEXP]]
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 127)
diff --git a/llvm/test/Transforms/InstCombine/load-store-forward.ll b/llvm/test/Transforms/InstCombine/load-store-forward.ll
index 72329f637d8b3..6c10c096143fa 100644
--- a/llvm/test/Transforms/InstCombine/load-store-forward.ll
+++ b/llvm/test/Transforms/InstCombine/load-store-forward.ll
@@ -334,7 +334,7 @@ define i32 @load_after_memset_1(ptr %a) {
define float @load_after_memset_1_float(ptr %a) {
; CHECK-LABEL: @load_after_memset_1_float(
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(16) [[A:%.*]], i8 1, i64 16, i1 false)
-; CHECK-NEXT: ret float 0x3820202020000000
+; CHECK-NEXT: ret float f0x01010101
;
call void @llvm.memset.p0.i64(ptr %a, i8 1, i64 16, i1 false)
%v = load float, ptr %a
diff --git a/llvm/test/Transforms/InstCombine/load.ll b/llvm/test/Transforms/InstCombine/load.ll
index 526faf3c4832e..67bc405a09ce9 100644
--- a/llvm/test/Transforms/InstCombine/load.ll
+++ b/llvm/test/Transforms/InstCombine/load.ll
@@ -21,7 +21,7 @@ define i32 @test1() {
define float @test2() {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: ret float 0x3FF3B2FEC0000000
+; CHECK-NEXT: ret float 1.231200e+00
;
%A = getelementptr [2 x { i32, float }], ptr @Y, i64 0, i64 1, i32 1 ; <ptr> [#uses=1]
%B = load float, ptr %A ; <float> [#uses=1]
diff --git a/llvm/test/Transforms/InstCombine/load3.ll b/llvm/test/Transforms/InstCombine/load3.ll
index a762ed838a739..fe2743125f0c2 100644
--- a/llvm/test/Transforms/InstCombine/load3.ll
+++ b/llvm/test/Transforms/InstCombine/load3.ll
@@ -23,7 +23,7 @@ define float @test2() {
ret float %tmp
; CHECK-LABEL: @test2(
-; CHECK: ret float 0x3806965600000000
+; CHECK: ret float f0x005A5958
}
@rslts32 = global [36 x i32] zeroinitializer, align 4
diff --git a/llvm/test/Transforms/InstCombine/log-pow.ll b/llvm/test/Transforms/InstCombine/log-pow.ll
index 374115953145d..3aeab9d8531d6 100644
--- a/llvm/test/Transforms/InstCombine/log-pow.ll
+++ b/llvm/test/Transforms/InstCombine/log-pow.ll
@@ -127,7 +127,7 @@ define float @function_pointer(ptr %fptr, float %p1) {
define double @log10_exp(double %x) {
; CHECK-LABEL: @log10_exp(
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], 0x3FDBCB7B1526E50E
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], f0x3FDBCB7B1526E50E
; CHECK-NEXT: ret double [[MUL]]
;
%exp = call fast double @exp(double %x)
@@ -137,7 +137,7 @@ define double @log10_exp(double %x) {
define <2 x float> @logv_exp2v(<2 x float> %x) {
; CHECK-LABEL: @logv_exp2v(
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast <2 x float> [[X:%.*]], splat (float 0x3FE62E4300000000)
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast <2 x float> [[X:%.*]], splat (float f0x3F317218)
; CHECK-NEXT: ret <2 x float> [[MUL]]
;
%exp = call fast <2 x float> @llvm.exp2.v2f32(<2 x float> %x)
@@ -147,7 +147,7 @@ define <2 x float> @logv_exp2v(<2 x float> %x) {
define float @log2f_exp10f(float %x) {
; CHECK-LABEL: @log2f_exp10f(
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[X:%.*]], 0x400A934F00000000
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[X:%.*]], f0x40549A78
; CHECK-NEXT: ret float [[MUL]]
;
%exp = call fast float @exp10f(float %x)
diff --git a/llvm/test/Transforms/InstCombine/log-to-intrinsic.ll b/llvm/test/Transforms/InstCombine/log-to-intrinsic.ll
index 527dc6e138440..e21526f84d156 100644
--- a/llvm/test/Transforms/InstCombine/log-to-intrinsic.ll
+++ b/llvm/test/Transforms/InstCombine/log-to-intrinsic.ll
@@ -53,13 +53,13 @@ define fp128 @test_logl_pos(fp128 %f) {
; CHECK-LABEL: define fp128 @test_logl_pos(
; CHECK-SAME: fp128 [[F:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp ugt fp128 [[F]], 0xL00000000000000000000000000000000
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp ugt fp128 [[F]], 0.000000e+00
; CHECK-NEXT: br i1 [[ISINF]], label %[[IF_END:.*]], label %[[RETURN:.*]]
; CHECK: [[IF_END]]:
; CHECK-NEXT: [[CALL:%.*]] = tail call fp128 @llvm.log.f128(fp128 [[F]])
; CHECK-NEXT: ret fp128 [[CALL]]
; CHECK: [[RETURN]]:
-; CHECK-NEXT: ret fp128 0xL00000000000000000000000000000000
+; CHECK-NEXT: ret fp128 0.000000e+00
;
entry:
%isinf = fcmp ole fp128 %f, 0xL00000000000000000000000000000000
@@ -125,13 +125,13 @@ define fp128 @test_log10l_pos(fp128 %f) {
; CHECK-LABEL: define fp128 @test_log10l_pos(
; CHECK-SAME: fp128 [[F:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp ugt fp128 [[F]], 0xL00000000000000000000000000000000
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp ugt fp128 [[F]], 0.000000e+00
; CHECK-NEXT: br i1 [[ISINF]], label %[[IF_END:.*]], label %[[RETURN:.*]]
; CHECK: [[IF_END]]:
; CHECK-NEXT: [[CALL:%.*]] = tail call fp128 @llvm.log10.f128(fp128 [[F]])
; CHECK-NEXT: ret fp128 [[CALL]]
; CHECK: [[RETURN]]:
-; CHECK-NEXT: ret fp128 0xL00000000000000000000000000000000
+; CHECK-NEXT: ret fp128 0.000000e+00
;
entry:
%isinf = fcmp ole fp128 %f, 0xL00000000000000000000000000000000
@@ -197,13 +197,13 @@ define fp128 @test_log2l_pos(fp128 %f) {
; CHECK-LABEL: define fp128 @test_log2l_pos(
; CHECK-SAME: fp128 [[F:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp ugt fp128 [[F]], 0xL00000000000000000000000000000000
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp ugt fp128 [[F]], 0.000000e+00
; CHECK-NEXT: br i1 [[ISINF]], label %[[IF_END:.*]], label %[[RETURN:.*]]
; CHECK: [[IF_END]]:
; CHECK-NEXT: [[CALL:%.*]] = tail call fp128 @llvm.log2.f128(fp128 [[F]])
; CHECK-NEXT: ret fp128 [[CALL]]
; CHECK: [[RETURN]]:
-; CHECK-NEXT: ret fp128 0xL00000000000000000000000000000000
+; CHECK-NEXT: ret fp128 0.000000e+00
;
entry:
%isinf = fcmp ole fp128 %f, 0xL00000000000000000000000000000000
diff --git a/llvm/test/Transforms/InstCombine/log1p.ll b/llvm/test/Transforms/InstCombine/log1p.ll
index 81d3cc8a4f7ac..c04e5423cc15d 100644
--- a/llvm/test/Transforms/InstCombine/log1p.ll
+++ b/llvm/test/Transforms/InstCombine/log1p.ll
@@ -4,7 +4,7 @@
define float @log1pf_const() {
; CHECK-LABEL: define float @log1pf_const() {
; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float 7.000000e+00)
-; CHECK-NEXT: ret float 0x4000A2B240000000
+; CHECK-NEXT: ret float f0x40051592
;
%r = call float @log1pf(float 7.000000e+00)
ret float %r
@@ -13,7 +13,7 @@ define float @log1pf_const() {
define double @log1p_const() {
; CHECK-LABEL: define double @log1p_const() {
; CHECK-NEXT: [[R:%.*]] = call double @log1p(double 7.000000e+00)
-; CHECK-NEXT: ret double 0x4000A2B23F3BAB73
+; CHECK-NEXT: ret double f0x4000A2B23F3BAB73
;
%r = call double @log1p(double 7.000000e+00)
ret double %r
@@ -130,7 +130,7 @@ define double @log1p_neg1_memory_none() {
define float @log1pf_neg2() {
; CHECK-LABEL: define float @log1pf_neg2() {
; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float -5.000000e-01)
-; CHECK-NEXT: ret float 0xBFE62E4300000000
+; CHECK-NEXT: ret float f0xBF317218
;
%r = call float @log1pf(float -5.000000e-01)
ret float %r
@@ -139,7 +139,7 @@ define float @log1pf_neg2() {
define double @log1p_neg2() {
; CHECK-LABEL: define double @log1p_neg2() {
; CHECK-NEXT: [[R:%.*]] = call double @log1p(double -5.000000e-01)
-; CHECK-NEXT: ret double 0xBFE62E42FEFA39EF
+; CHECK-NEXT: ret double f0xBFE62E42FEFA39EF
;
%r = call double @log1p(double -5.000000e-01)
ret double %r
@@ -147,7 +147,7 @@ define double @log1p_neg2() {
define float @log1pf_inf() {
; CHECK-LABEL: define float @log1pf_inf() {
-; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float +inf)
; CHECK-NEXT: ret float [[R]]
;
%r = call float @log1pf(float 0x7FF0000000000000)
@@ -156,7 +156,7 @@ define float @log1pf_inf() {
define double @log1p_inf() {
; CHECK-LABEL: define double @log1p_inf() {
-; CHECK-NEXT: [[R:%.*]] = call double @log1p(double 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @log1p(double +inf)
; CHECK-NEXT: ret double [[R]]
;
%r = call double @log1p(double 0x7FF0000000000000)
@@ -165,7 +165,7 @@ define double @log1p_inf() {
define float @log1pf_inf_memory_none() {
; CHECK-LABEL: define float @log1pf_inf_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float 0x7FF0000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float +inf) #[[ATTR0]]
; CHECK-NEXT: ret float [[R]]
;
%r = call float @log1pf(float 0x7FF0000000000000) readnone
@@ -174,7 +174,7 @@ define float @log1pf_inf_memory_none() {
define double @log1p_inf_memory_none() {
; CHECK-LABEL: define double @log1p_inf_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call double @log1p(double 0x7FF0000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call double @log1p(double +inf) #[[ATTR0]]
; CHECK-NEXT: ret double [[R]]
;
%r = call double @log1p(double 0x7FF0000000000000) readnone
@@ -183,7 +183,7 @@ define double @log1p_inf_memory_none() {
define float @log1pf_neg_inf() {
; CHECK-LABEL: define float @log1pf_neg_inf() {
-; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float 0xFFF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float -inf)
; CHECK-NEXT: ret float [[R]]
;
%r = call float @log1pf(float 0xFFF0000000000000)
@@ -192,7 +192,7 @@ define float @log1pf_neg_inf() {
define double @log1p_neg_inf() {
; CHECK-LABEL: define double @log1p_neg_inf() {
-; CHECK-NEXT: [[R:%.*]] = call double @log1p(double 0xFFF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @log1p(double -inf)
; CHECK-NEXT: ret double [[R]]
;
%r = call double @log1p(double 0xFFF0000000000000)
@@ -201,7 +201,7 @@ define double @log1p_neg_inf() {
define float @log1pf_neg_inf_memory_none() {
; CHECK-LABEL: define float @log1pf_neg_inf_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float 0xFFF0000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float -inf) #[[ATTR0]]
; CHECK-NEXT: ret float [[R]]
;
%r = call float @log1pf(float 0xFFF0000000000000) readnone
@@ -210,7 +210,7 @@ define float @log1pf_neg_inf_memory_none() {
define double @log1p_neg_inf_memory_none() {
; CHECK-LABEL: define double @log1p_neg_inf_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call double @log1p(double 0xFFF0000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call double @log1p(double -inf) #[[ATTR0]]
; CHECK-NEXT: ret double [[R]]
;
%r = call double @log1p(double 0xFFF0000000000000) readnone
@@ -219,7 +219,7 @@ define double @log1p_neg_inf_memory_none() {
define float @log1pf_nan() {
; CHECK-LABEL: define float @log1pf_nan() {
-; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float +qnan)
; CHECK-NEXT: ret float [[R]]
;
%r = call float @log1pf(float 0x7FF8000000000000)
@@ -228,7 +228,7 @@ define float @log1pf_nan() {
define double @log1p_nan() {
; CHECK-LABEL: define double @log1p_nan() {
-; CHECK-NEXT: [[R:%.*]] = call double @log1p(double 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @log1p(double +qnan)
; CHECK-NEXT: ret double [[R]]
;
%r = call double @log1p(double 0x7FF8000000000000)
@@ -237,7 +237,7 @@ define double @log1p_nan() {
define float @log1pf_nan_memory_none() {
; CHECK-LABEL: define float @log1pf_nan_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float 0x7FF8000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call float @log1pf(float +qnan) #[[ATTR0]]
; CHECK-NEXT: ret float [[R]]
;
%r = call float @log1pf(float 0x7FF8000000000000) readnone
@@ -246,7 +246,7 @@ define float @log1pf_nan_memory_none() {
define double @log1p_nan_memory_none() {
; CHECK-LABEL: define double @log1p_nan_memory_none() {
-; CHECK-NEXT: [[R:%.*]] = call double @log1p(double 0x7FF8000000000000) #[[ATTR0]]
+; CHECK-NEXT: [[R:%.*]] = call double @log1p(double +qnan) #[[ATTR0]]
; CHECK-NEXT: ret double [[R]]
;
%r = call double @log1p(double 0x7FF8000000000000) readnone
diff --git a/llvm/test/Transforms/InstCombine/logb.ll b/llvm/test/Transforms/InstCombine/logb.ll
index f2509e956d71c..18d07c5418555 100644
--- a/llvm/test/Transforms/InstCombine/logb.ll
+++ b/llvm/test/Transforms/InstCombine/logb.ll
@@ -57,7 +57,7 @@ define double @logb_neg_zero() {
define float @logbf_inf() {
; CHECK-LABEL: define float @logbf_inf() {
-; CHECK-NEXT: [[R:%.*]] = call float @logbf(float 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call float @logbf(float +inf)
; CHECK-NEXT: ret float [[R]]
;
%r = call float @logbf(float 0x7FF0000000000000)
@@ -66,7 +66,7 @@ define float @logbf_inf() {
define double @logb_inf() {
; CHECK-LABEL: define double @logb_inf() {
-; CHECK-NEXT: [[R:%.*]] = call double @logb(double 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @logb(double +inf)
; CHECK-NEXT: ret double [[R]]
;
%r = call double @logb(double 0x7FF0000000000000)
@@ -75,7 +75,7 @@ define double @logb_inf() {
define float @logbf_nan() {
; CHECK-LABEL: define float @logbf_nan() {
-; CHECK-NEXT: [[R:%.*]] = call float @logbf(float 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call float @logbf(float +qnan)
; CHECK-NEXT: ret float [[R]]
;
%r = call float @logbf(float 0x7FF8000000000000)
@@ -84,7 +84,7 @@ define float @logbf_nan() {
define double @logb_nan() {
; CHECK-LABEL: define double @logb_nan() {
-; CHECK-NEXT: [[R:%.*]] = call double @logb(double 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @logb(double +qnan)
; CHECK-NEXT: ret double [[R]]
;
%r = call double @logb(double 0x7FF8000000000000)
diff --git a/llvm/test/Transforms/InstCombine/maximum.ll b/llvm/test/Transforms/InstCombine/maximum.ll
index c79449472235b..bf826b0f165b3 100644
--- a/llvm/test/Transforms/InstCombine/maximum.ll
+++ b/llvm/test/Transforms/InstCombine/maximum.ll
@@ -26,7 +26,7 @@ define float @constant_fold_maximum_f32_inv() {
define float @constant_fold_maximum_f32_nan0() {
; CHECK-LABEL: @constant_fold_maximum_f32_nan0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x = call float @llvm.maximum.f32(float 0x7FF8000000000000, float 2.0)
ret float %x
@@ -34,7 +34,7 @@ define float @constant_fold_maximum_f32_nan0() {
define float @constant_fold_maximum_f32_nan1() {
; CHECK-LABEL: @constant_fold_maximum_f32_nan1(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x = call float @llvm.maximum.f32(float 2.0, float 0x7FF8000000000000)
ret float %x
@@ -42,7 +42,7 @@ define float @constant_fold_maximum_f32_nan1() {
define float @constant_fold_maximum_f32_nan_nan() {
; CHECK-LABEL: @constant_fold_maximum_f32_nan_nan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x = call float @llvm.maximum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
ret float %x
@@ -98,7 +98,7 @@ define double @constant_fold_maximum_f64() {
define double @constant_fold_maximum_f64_nan0() {
; CHECK-LABEL: @constant_fold_maximum_f64_nan0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%x = call double @llvm.maximum.f64(double 0x7FF8000000000000, double 2.0)
ret double %x
@@ -106,7 +106,7 @@ define double @constant_fold_maximum_f64_nan0() {
define double @constant_fold_maximum_f64_nan1() {
; CHECK-LABEL: @constant_fold_maximum_f64_nan1(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%x = call double @llvm.maximum.f64(double 2.0, double 0x7FF8000000000000)
ret double %x
@@ -114,7 +114,7 @@ define double @constant_fold_maximum_f64_nan1() {
define double @constant_fold_maximum_f64_nan_nan() {
; CHECK-LABEL: @constant_fold_maximum_f64_nan_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%x = call double @llvm.maximum.f64(double 0x7FF8000000000000, double 0x7FF8000000000000)
ret double %x
@@ -131,7 +131,7 @@ define float @canonicalize_constant_maximum_f32(float %x) {
define float @maximum_f32_nan_val(float %x) {
; CHECK-LABEL: @maximum_f32_nan_val(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%y = call float @llvm.maximum.f32(float 0x7FF8000000000000, float %x)
ret float %y
@@ -139,7 +139,7 @@ define float @maximum_f32_nan_val(float %x) {
define float @maximum_f32_val_nan(float %x) {
; CHECK-LABEL: @maximum_f32_val_nan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%y = call float @llvm.maximum.f32(float %x, float 0x7FF8000000000000)
ret float %y
diff --git a/llvm/test/Transforms/InstCombine/maxnum.ll b/llvm/test/Transforms/InstCombine/maxnum.ll
index 5e275627414cb..9a039fafe3c21 100644
--- a/llvm/test/Transforms/InstCombine/maxnum.ll
+++ b/llvm/test/Transforms/InstCombine/maxnum.ll
@@ -42,7 +42,7 @@ define float @constant_fold_maxnum_f32_nan1() {
define float @constant_fold_maxnum_f32_nan_nan() {
; CHECK-LABEL: @constant_fold_maxnum_f32_nan_nan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
ret float %x
@@ -114,7 +114,7 @@ define double @constant_fold_maxnum_f64_nan1() {
define double @constant_fold_maxnum_f64_nan_nan() {
; CHECK-LABEL: @constant_fold_maxnum_f64_nan_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%x = call double @llvm.maxnum.f64(double 0x7FF8000000000000, double 0x7FF8000000000000)
ret double %x
diff --git a/llvm/test/Transforms/InstCombine/minimum.ll b/llvm/test/Transforms/InstCombine/minimum.ll
index eb6eadf96e132..e874ec350c750 100644
--- a/llvm/test/Transforms/InstCombine/minimum.ll
+++ b/llvm/test/Transforms/InstCombine/minimum.ll
@@ -28,7 +28,7 @@ define float @constant_fold_minimum_f32_inv() {
define float @constant_fold_minimum_f32_nan0() {
; CHECK-LABEL: @constant_fold_minimum_f32_nan0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x = call float @llvm.minimum.f32(float 0x7FF8000000000000, float 2.0)
ret float %x
@@ -36,7 +36,7 @@ define float @constant_fold_minimum_f32_nan0() {
define float @constant_fold_minimum_f32_nan1() {
; CHECK-LABEL: @constant_fold_minimum_f32_nan1(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x = call float @llvm.minimum.f32(float 2.0, float 0x7FF8000000000000)
ret float %x
@@ -44,7 +44,7 @@ define float @constant_fold_minimum_f32_nan1() {
define float @constant_fold_minimum_f32_nan_nan() {
; CHECK-LABEL: @constant_fold_minimum_f32_nan_nan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x = call float @llvm.minimum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
ret float %x
@@ -100,7 +100,7 @@ define double @constant_fold_minimum_f64() {
define double @constant_fold_minimum_f64_nan0() {
; CHECK-LABEL: @constant_fold_minimum_f64_nan0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%x = call double @llvm.minimum.f64(double 0x7FF8000000000000, double 2.0)
ret double %x
@@ -108,7 +108,7 @@ define double @constant_fold_minimum_f64_nan0() {
define double @constant_fold_minimum_f64_nan1() {
; CHECK-LABEL: @constant_fold_minimum_f64_nan1(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%x = call double @llvm.minimum.f64(double 2.0, double 0x7FF8000000000000)
ret double %x
@@ -116,7 +116,7 @@ define double @constant_fold_minimum_f64_nan1() {
define double @constant_fold_minimum_f64_nan_nan() {
; CHECK-LABEL: @constant_fold_minimum_f64_nan_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%x = call double @llvm.minimum.f64(double 0x7FF8000000000000, double 0x7FF8000000000000)
ret double %x
@@ -133,7 +133,7 @@ define float @canonicalize_constant_minimum_f32(float %x) {
define float @minimum_f32_nan_val(float %x) {
; CHECK-LABEL: @minimum_f32_nan_val(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%y = call float @llvm.minimum.f32(float 0x7FF8000000000000, float %x)
ret float %y
@@ -141,7 +141,7 @@ define float @minimum_f32_nan_val(float %x) {
define float @minimum_f32_val_nan(float %x) {
; CHECK-LABEL: @minimum_f32_val_nan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%y = call float @llvm.minimum.f32(float %x, float 0x7FF8000000000000)
ret float %y
diff --git a/llvm/test/Transforms/InstCombine/minnum.ll b/llvm/test/Transforms/InstCombine/minnum.ll
index 7ac83bf91163e..1ff9b2d193b3e 100644
--- a/llvm/test/Transforms/InstCombine/minnum.ll
+++ b/llvm/test/Transforms/InstCombine/minnum.ll
@@ -44,7 +44,7 @@ define float @constant_fold_minnum_f32_nan1() {
define float @constant_fold_minnum_f32_nan_nan() {
; CHECK-LABEL: @constant_fold_minnum_f32_nan_nan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
ret float %x
@@ -116,7 +116,7 @@ define double @constant_fold_minnum_f64_nan1() {
define double @constant_fold_minnum_f64_nan_nan() {
; CHECK-LABEL: @constant_fold_minnum_f64_nan_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%x = call double @llvm.minnum.f64(double 0x7FF8000000000000, double 0x7FF8000000000000)
ret double %x
diff --git a/llvm/test/Transforms/InstCombine/nan.ll b/llvm/test/Transforms/InstCombine/nan.ll
index 09ebfc715babe..ff8e66fca07b2 100644
--- a/llvm/test/Transforms/InstCombine/nan.ll
+++ b/llvm/test/Transforms/InstCombine/nan.ll
@@ -7,7 +7,7 @@
define double @nan_empty() {
; CHECK-LABEL: define double @nan_empty() {
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%res = call double @nan(ptr @empty)
ret double %res
@@ -15,7 +15,7 @@ define double @nan_empty() {
define double @nan_dec() {
; CHECK-LABEL: define double @nan_dec() {
-; CHECK-NEXT: ret double 0x7FF8000000000001
+; CHECK-NEXT: ret double +nan(0x1)
;
%res = call double @nan(ptr @dec)
ret double %res
@@ -23,7 +23,7 @@ define double @nan_dec() {
define double @nan_hex() {
; CHECK-LABEL: define double @nan_hex() {
-; CHECK-NEXT: ret double 0x7FF800000000000F
+; CHECK-NEXT: ret double +nan(0xF)
;
%res = call double @nan(ptr @hex)
ret double %res
@@ -31,7 +31,7 @@ define double @nan_hex() {
define float @nanf_empty() {
; CHECK-LABEL: define float @nanf_empty() {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%res = call float @nanf(ptr @empty)
ret float %res
diff --git a/llvm/test/Transforms/InstCombine/nanl-fp128.ll b/llvm/test/Transforms/InstCombine/nanl-fp128.ll
index 21ba0fb14ca20..f88b84a0b0ad9 100644
--- a/llvm/test/Transforms/InstCombine/nanl-fp128.ll
+++ b/llvm/test/Transforms/InstCombine/nanl-fp128.ll
@@ -7,7 +7,7 @@
define fp128 @nanl_empty() {
; CHECK-LABEL: define fp128 @nanl_empty() {
-; CHECK-NEXT: ret fp128 0xL00000000000000007FFF800000000000
+; CHECK-NEXT: ret fp128 +qnan
;
%res = call fp128 @nanl(ptr @empty)
ret fp128 %res
@@ -15,7 +15,7 @@ define fp128 @nanl_empty() {
define fp128 @nanl_dec() {
; CHECK-LABEL: define fp128 @nanl_dec() {
-; CHECK-NEXT: ret fp128 0xL00000000000000017FFF800000000000
+; CHECK-NEXT: ret fp128 +nan(0x1)
;
%res = call fp128 @nanl(ptr @dec)
ret fp128 %res
@@ -23,7 +23,7 @@ define fp128 @nanl_dec() {
define fp128 @nanl_hex() {
; CHECK-LABEL: define fp128 @nanl_hex() {
-; CHECK-NEXT: ret fp128 0xL000000000000000F7FFF800000000000
+; CHECK-NEXT: ret fp128 +nan(0xF)
;
%res = call fp128 @nanl(ptr @hex)
ret fp128 %res
diff --git a/llvm/test/Transforms/InstCombine/nanl-fp80.ll b/llvm/test/Transforms/InstCombine/nanl-fp80.ll
index 7868af3696a56..e178288dc7d4a 100644
--- a/llvm/test/Transforms/InstCombine/nanl-fp80.ll
+++ b/llvm/test/Transforms/InstCombine/nanl-fp80.ll
@@ -7,7 +7,7 @@
define x86_fp80 @nanl_empty() {
; CHECK-LABEL: define x86_fp80 @nanl_empty() {
-; CHECK-NEXT: ret x86_fp80 0xK7FFFC000000000000000
+; CHECK-NEXT: ret x86_fp80 +qnan
;
%res = call x86_fp80 @nanl(ptr @empty)
ret x86_fp80 %res
@@ -15,7 +15,7 @@ define x86_fp80 @nanl_empty() {
define x86_fp80 @nanl_dec() {
; CHECK-LABEL: define x86_fp80 @nanl_dec() {
-; CHECK-NEXT: ret x86_fp80 0xK7FFFC000000000000001
+; CHECK-NEXT: ret x86_fp80 +nan(0x1)
;
%res = call x86_fp80 @nanl(ptr @dec)
ret x86_fp80 %res
@@ -23,7 +23,7 @@ define x86_fp80 @nanl_dec() {
define x86_fp80 @nanl_hex() {
; CHECK-LABEL: define x86_fp80 @nanl_hex() {
-; CHECK-NEXT: ret x86_fp80 0xK7FFFC00000000000000F
+; CHECK-NEXT: ret x86_fp80 +nan(0xF)
;
%res = call x86_fp80 @nanl(ptr @hex)
ret x86_fp80 %res
diff --git a/llvm/test/Transforms/InstCombine/nanl-ppc-fp128.ll b/llvm/test/Transforms/InstCombine/nanl-ppc-fp128.ll
index 7f60a379c4885..dfe8a81cee202 100644
--- a/llvm/test/Transforms/InstCombine/nanl-ppc-fp128.ll
+++ b/llvm/test/Transforms/InstCombine/nanl-ppc-fp128.ll
@@ -7,7 +7,7 @@
define ppc_fp128 @nanl_empty() {
; CHECK-LABEL: define ppc_fp128 @nanl_empty() {
-; CHECK-NEXT: ret ppc_fp128 0xM7FF80000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 +qnan
;
%res = call ppc_fp128 @nanl(ptr @empty)
ret ppc_fp128 %res
@@ -15,7 +15,7 @@ define ppc_fp128 @nanl_empty() {
define ppc_fp128 @nanl_dec() {
; CHECK-LABEL: define ppc_fp128 @nanl_dec() {
-; CHECK-NEXT: ret ppc_fp128 0xM7FF80000000000010000000000000000
+; CHECK-NEXT: ret ppc_fp128 +nan(0x1)
;
%res = call ppc_fp128 @nanl(ptr @dec)
ret ppc_fp128 %res
@@ -23,7 +23,7 @@ define ppc_fp128 @nanl_dec() {
define ppc_fp128 @nanl_hex() {
; CHECK-LABEL: define ppc_fp128 @nanl_hex() {
-; CHECK-NEXT: ret ppc_fp128 0xM7FF800000000000F0000000000000000
+; CHECK-NEXT: ret ppc_fp128 +nan(0xF)
;
%res = call ppc_fp128 @nanl(ptr @hex)
ret ppc_fp128 %res
diff --git a/llvm/test/Transforms/InstCombine/nanless-canonicalize-combine.ll b/llvm/test/Transforms/InstCombine/nanless-canonicalize-combine.ll
index 147347599e701..5e42064d81c87 100644
--- a/llvm/test/Transforms/InstCombine/nanless-canonicalize-combine.ll
+++ b/llvm/test/Transforms/InstCombine/nanless-canonicalize-combine.ll
@@ -421,7 +421,7 @@ define x86_fp80 @ignore_x86_fp80(x86_fp80 %x) #0 {
; CHECK-LABEL: define x86_fp80 @ignore_x86_fp80(
; CHECK-SAME: x86_fp80 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[HARD_CANONICAL:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 [[X]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord x86_fp80 [[X]], 0xK00000000000000000000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord x86_fp80 [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[ORD]], x86_fp80 [[HARD_CANONICAL]], x86_fp80 [[X]]
; CHECK-NEXT: ret x86_fp80 [[X_CANON]]
;
@@ -435,7 +435,7 @@ define ppc_fp128 @ignore_ppc_fp128(ppc_fp128 %x) #0 {
; CHECK-LABEL: define ppc_fp128 @ignore_ppc_fp128(
; CHECK-SAME: ppc_fp128 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[HARD_CANONICAL:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 [[X]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord ppc_fp128 [[X]], 0xM00000000000000000000000000000000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord ppc_fp128 [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[ORD]], ppc_fp128 [[HARD_CANONICAL]], ppc_fp128 [[X]]
; CHECK-NEXT: ret ppc_fp128 [[X_CANON]]
;
@@ -555,7 +555,7 @@ define float @canonicalize_missing_noop_only_daz(float %x) "denormal-fp-math"="i
define half @independent_hands_canonicalize_ieee_0(half noundef %x, half %y) #0 {
; CHECK-LABEL: define half @independent_hands_canonicalize_ieee_0(
; CHECK-SAME: half noundef [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[ORD]], half [[X]], half [[Y]]
; CHECK-NEXT: ret half [[X_CANON]]
;
@@ -568,7 +568,7 @@ define half @independent_hands_canonicalize_ieee_0(half noundef %x, half %y) #0
define half @independent_hands_canonicalize_ieee_1(half noundef %x, half %y) #0 {
; CHECK-LABEL: define half @independent_hands_canonicalize_ieee_1(
; CHECK-SAME: half noundef [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[UNO]], half [[Y]], half [[X]]
; CHECK-NEXT: ret half [[X_CANON]]
;
@@ -581,7 +581,7 @@ define half @independent_hands_canonicalize_ieee_1(half noundef %x, half %y) #0
define half @independent_hands_fdiv_ieee_0(half noundef %x, half %y) #0 {
; CHECK-LABEL: define half @independent_hands_fdiv_ieee_0(
; CHECK-SAME: half noundef [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[ORD]], half [[Y]], half [[X]]
; CHECK-NEXT: ret half [[SEL]]
;
@@ -594,7 +594,7 @@ define half @independent_hands_fdiv_ieee_0(half noundef %x, half %y) #0 {
define half @independent_hands_fdiv_ieee_1(half noundef %x, half %y) #0 {
; CHECK-LABEL: define half @independent_hands_fdiv_ieee_1(
; CHECK-SAME: half noundef [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[UNO]], half [[X]], half [[Y]]
; CHECK-NEXT: ret half [[SEL]]
;
@@ -608,7 +608,7 @@ define half @independent_hands_canonicalize_daz_0(half noundef %x, half %y) #1 {
; CHECK-LABEL: define half @independent_hands_canonicalize_daz_0(
; CHECK-SAME: half noundef [[X:%.*]], half [[Y:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[HARD_CANONICAL:%.*]] = call half @llvm.canonicalize.f16(half [[X]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[ORD]], half [[HARD_CANONICAL]], half [[Y]]
; CHECK-NEXT: ret half [[X_CANON]]
;
@@ -622,7 +622,7 @@ define half @independent_hands_canonicalize_daz_1(half noundef %x, half %y) #1 {
; CHECK-LABEL: define half @independent_hands_canonicalize_daz_1(
; CHECK-SAME: half noundef [[X:%.*]], half [[Y:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[HARD_CANONICAL:%.*]] = call half @llvm.canonicalize.f16(half [[X]])
-; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[UNO]], half [[Y]], half [[HARD_CANONICAL]]
; CHECK-NEXT: ret half [[X_CANON]]
;
@@ -635,8 +635,8 @@ define half @independent_hands_canonicalize_daz_1(half noundef %x, half %y) #1 {
define half @independent_hands_fdiv_daz_0(half noundef %x, half %y) #1 {
; CHECK-LABEL: define half @independent_hands_fdiv_daz_0(
; CHECK-SAME: half noundef [[X:%.*]], half [[Y:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[RCP:%.*]] = fdiv half 0xH3C00, [[X]]
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[RCP:%.*]] = fdiv half 1.000000e+00, [[X]]
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[ORD]], half [[Y]], half [[RCP]]
; CHECK-NEXT: ret half [[SEL]]
;
@@ -649,8 +649,8 @@ define half @independent_hands_fdiv_daz_0(half noundef %x, half %y) #1 {
define half @independent_hands_fdiv_daz_1(half noundef %x, half %y) #1 {
; CHECK-LABEL: define half @independent_hands_fdiv_daz_1(
; CHECK-SAME: half noundef [[X:%.*]], half [[Y:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[RCP:%.*]] = fdiv half 0xH3C00, [[X]]
-; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[RCP:%.*]] = fdiv half 1.000000e+00, [[X]]
+; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[UNO]], half [[RCP]], half [[Y]]
; CHECK-NEXT: ret half [[SEL]]
;
@@ -664,7 +664,7 @@ define x86_fp80 @independent_hands_canonicalize_ieee_0_x86_fp80(x86_fp80 noundef
; CHECK-LABEL: define x86_fp80 @independent_hands_canonicalize_ieee_0_x86_fp80(
; CHECK-SAME: x86_fp80 noundef [[X:%.*]], x86_fp80 [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[HARD_CANONICAL:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 [[X]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord x86_fp80 [[X]], 0xK00000000000000000000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord x86_fp80 [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[ORD]], x86_fp80 [[HARD_CANONICAL]], x86_fp80 [[Y]]
; CHECK-NEXT: ret x86_fp80 [[X_CANON]]
;
@@ -677,8 +677,8 @@ define x86_fp80 @independent_hands_canonicalize_ieee_0_x86_fp80(x86_fp80 noundef
define x86_fp80 @independent_hands_fdiv_ieee_0_x86_fp80(x86_fp80 noundef %x, x86_fp80 %y) #0 {
; CHECK-LABEL: define x86_fp80 @independent_hands_fdiv_ieee_0_x86_fp80(
; CHECK-SAME: x86_fp80 noundef [[X:%.*]], x86_fp80 [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[RCP:%.*]] = fdiv x86_fp80 0xK3FFF8000000000000000, [[X]]
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord x86_fp80 [[X]], 0xK00000000000000000000
+; CHECK-NEXT: [[RCP:%.*]] = fdiv x86_fp80 1.000000e+00, [[X]]
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord x86_fp80 [[X]], 0.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[ORD]], x86_fp80 [[Y]], x86_fp80 [[RCP]]
; CHECK-NEXT: ret x86_fp80 [[SEL]]
;
@@ -693,7 +693,7 @@ define x86_fp80 @independent_hands_fdiv_ieee_0_x86_fp80(x86_fp80 noundef %x, x86
define half @independent_hands_canonicalize_ieee_0_maybe_undef(half %x, half %y) #0 {
; CHECK-LABEL: define half @independent_hands_canonicalize_ieee_0_maybe_undef(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[ORD]], half [[X]], half [[Y]]
; CHECK-NEXT: ret half [[X_CANON]]
;
@@ -707,7 +707,7 @@ define half @independent_hands_canonicalize_ieee_0_maybe_undef(half %x, half %y)
define half @independent_hands_canonicalize_ieee_1_maybe_undef(half %x, half %y) #0 {
; CHECK-LABEL: define half @independent_hands_canonicalize_ieee_1_maybe_undef(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: [[X_CANON:%.*]] = select i1 [[UNO]], half [[Y]], half [[X]]
; CHECK-NEXT: ret half [[X_CANON]]
;
@@ -722,7 +722,7 @@ define half @independent_hands_fdiv_ieee_0_maybe_undef(half %x, half %y) #0 {
; CHECK-LABEL: define half @independent_hands_fdiv_ieee_0_maybe_undef(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[X_FR:%.*]] = freeze half [[X]]
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X_FR]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X_FR]], 0.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[ORD]], half [[Y]], half [[X_FR]]
; CHECK-NEXT: ret half [[SEL]]
;
@@ -737,7 +737,7 @@ define half @independent_hands_fdiv_ieee_1_maybe_undef(half %x, half %y) #0 {
; CHECK-LABEL: define half @independent_hands_fdiv_ieee_1_maybe_undef(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[X_FR:%.*]] = freeze half [[X]]
-; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X_FR]], 0xH0000
+; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X_FR]], 0.000000e+00
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[UNO]], half [[X_FR]], half [[Y]]
; CHECK-NEXT: ret half [[SEL]]
;
diff --git a/llvm/test/Transforms/InstCombine/opaque-ptr.ll b/llvm/test/Transforms/InstCombine/opaque-ptr.ll
index 9f3cd87924774..b25b87f77d7e2 100644
--- a/llvm/test/Transforms/InstCombine/opaque-ptr.ll
+++ b/llvm/test/Transforms/InstCombine/opaque-ptr.ll
@@ -858,7 +858,7 @@ declare float @fmodf(float, float)
define i32 @const_fold_call_with_func_type_mismatch() {
; CHECK-LABEL: @const_fold_call_with_func_type_mismatch(
-; CHECK-NEXT: [[V:%.*]] = call i32 @fmodf(float 0x40091EB860000000, float 2.000000e+00)
+; CHECK-NEXT: [[V:%.*]] = call i32 @fmodf(float 3.140000e+00, float 2.000000e+00)
; CHECK-NEXT: ret i32 [[V]]
;
%v = call i32 @fmodf(float 0x40091EB860000000, float 2.000000e+00)
diff --git a/llvm/test/Transforms/InstCombine/pow-1.ll b/llvm/test/Transforms/InstCombine/pow-1.ll
index dde2ac7ed32b9..4fd2d252e8c2a 100644
--- a/llvm/test/Transforms/InstCombine/pow-1.ll
+++ b/llvm/test/Transforms/InstCombine/pow-1.ll
@@ -699,7 +699,7 @@ define float @powf_libcall_half_assume_ninf_noerrno(float %x) {
; ANY-LABEL: define float @powf_libcall_half_assume_ninf_noerrno(
; ANY-SAME: float [[X:%.*]]) {
; ANY-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; ANY-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], 0x7FF0000000000000
+; ANY-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], +inf
; ANY-NEXT: call void @llvm.assume(i1 [[NOT_INF]])
; ANY-NEXT: [[SQRT:%.*]] = call float @llvm.sqrt.f32(float [[X]])
; ANY-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SQRT]])
@@ -708,7 +708,7 @@ define float @powf_libcall_half_assume_ninf_noerrno(float %x) {
; VC32-LABEL: define float @powf_libcall_half_assume_ninf_noerrno(
; VC32-SAME: float [[X:%.*]]) {
; VC32-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; VC32-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], 0x7FF0000000000000
+; VC32-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], +inf
; VC32-NEXT: call void @llvm.assume(i1 [[NOT_INF]])
; VC32-NEXT: [[RETVAL:%.*]] = call float @powf(float [[X]], float 5.000000e-01) #[[ATTR2]]
; VC32-NEXT: ret float [[RETVAL]]
@@ -716,7 +716,7 @@ define float @powf_libcall_half_assume_ninf_noerrno(float %x) {
; VC51-LABEL: define float @powf_libcall_half_assume_ninf_noerrno(
; VC51-SAME: float [[X:%.*]]) {
; VC51-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; VC51-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], 0x7FF0000000000000
+; VC51-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], +inf
; VC51-NEXT: call void @llvm.assume(i1 [[NOT_INF]])
; VC51-NEXT: [[RETVAL:%.*]] = call float @powf(float [[X]], float 5.000000e-01) #[[ATTR2]]
; VC51-NEXT: ret float [[RETVAL]]
@@ -724,7 +724,7 @@ define float @powf_libcall_half_assume_ninf_noerrno(float %x) {
; VC64-LABEL: define float @powf_libcall_half_assume_ninf_noerrno(
; VC64-SAME: float [[X:%.*]]) {
; VC64-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; VC64-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], 0x7FF0000000000000
+; VC64-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], +inf
; VC64-NEXT: call void @llvm.assume(i1 [[NOT_INF]])
; VC64-NEXT: [[SQRT:%.*]] = call float @llvm.sqrt.f32(float [[X]])
; VC64-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SQRT]])
@@ -733,7 +733,7 @@ define float @powf_libcall_half_assume_ninf_noerrno(float %x) {
; VC83-LABEL: define float @powf_libcall_half_assume_ninf_noerrno(
; VC83-SAME: float [[X:%.*]]) {
; VC83-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; VC83-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], 0x7FF0000000000000
+; VC83-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], +inf
; VC83-NEXT: call void @llvm.assume(i1 [[NOT_INF]])
; VC83-NEXT: [[SQRT:%.*]] = call float @llvm.sqrt.f32(float [[X]])
; VC83-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SQRT]])
@@ -742,7 +742,7 @@ define float @powf_libcall_half_assume_ninf_noerrno(float %x) {
; NOLIB-LABEL: define float @powf_libcall_half_assume_ninf_noerrno(
; NOLIB-SAME: float [[X:%.*]]) {
; NOLIB-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; NOLIB-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], 0x7FF0000000000000
+; NOLIB-NEXT: [[NOT_INF:%.*]] = fcmp one float [[FABS]], +inf
; NOLIB-NEXT: call void @llvm.assume(i1 [[NOT_INF]])
; NOLIB-NEXT: [[RETVAL:%.*]] = call float @powf(float [[X]], float 5.000000e-01) #[[ATTR2]]
; NOLIB-NEXT: ret float [[RETVAL]]
@@ -866,7 +866,7 @@ define double @pow_libcall_half_fromdomcondition(double %x) {
; LIB-LABEL: define double @pow_libcall_half_fromdomcondition(
; LIB-SAME: double [[X:%.*]]) {
; LIB-NEXT: [[A:%.*]] = call double @llvm.fabs.f64(double [[X]])
-; LIB-NEXT: [[C:%.*]] = fcmp oeq double [[A]], 0x7FF0000000000000
+; LIB-NEXT: [[C:%.*]] = fcmp oeq double [[A]], +inf
; LIB-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
; LIB: then:
; LIB-NEXT: ret double 0.000000e+00
@@ -878,7 +878,7 @@ define double @pow_libcall_half_fromdomcondition(double %x) {
; NOLIB-LABEL: define double @pow_libcall_half_fromdomcondition(
; NOLIB-SAME: double [[X:%.*]]) {
; NOLIB-NEXT: [[A:%.*]] = call double @llvm.fabs.f64(double [[X]])
-; NOLIB-NEXT: [[C:%.*]] = fcmp oeq double [[A]], 0x7FF0000000000000
+; NOLIB-NEXT: [[C:%.*]] = fcmp oeq double [[A]], +inf
; NOLIB-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
; NOLIB: then:
; NOLIB-NEXT: ret double 0.000000e+00
@@ -903,8 +903,8 @@ define double @pow_libcall_half_no_FMF_noerrno(double %x) {
; LIB-SAME: double [[X:%.*]]) {
; LIB-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X]])
; LIB-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
-; LIB-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
-; LIB-NEXT: [[RETVAL:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; LIB-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], -inf
+; LIB-NEXT: [[RETVAL:%.*]] = select i1 [[ISINF]], double +inf, double [[ABS]]
; LIB-NEXT: ret double [[RETVAL]]
;
; NOLIB-LABEL: define double @pow_libcall_half_no_FMF_noerrno(
@@ -921,7 +921,7 @@ define double @pow_libcall_half_no_FMF_noerrno(double %x) {
define float @test_simplify9(float %x) {
; CHECK-LABEL: define float @test_simplify9(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%retval = call float @llvm.pow.f32(float 0xFFF0000000000000, float 0.5)
ret float %retval
@@ -930,7 +930,7 @@ define float @test_simplify9(float %x) {
define double @test_simplify10(double %x) {
; CHECK-LABEL: define double @test_simplify10(
; CHECK-SAME: double [[X:%.*]]) {
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%retval = call double @llvm.pow.f64(double 0xFFF0000000000000, double 0.5)
ret double %retval
@@ -1339,8 +1339,8 @@ define double @pow_intrinsic_half_no_FMF(double %x) {
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X]])
; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
-; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], -inf
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[ISINF]], double +inf, double [[ABS]]
; CHECK-NEXT: ret double [[RETVAL]]
;
%retval = call double @llvm.pow.f64(double %x, double 0.5)
@@ -1442,7 +1442,7 @@ define double @test_libcall_pow_10_f64_noerrno(double %x) {
define half @test_pow_10_f16(half %x) {
; CHECK-LABEL: define half @test_pow_10_f16(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[RETVAL:%.*]] = call half @llvm.pow.f16(half 0xH4900, half [[X]])
+; CHECK-NEXT: [[RETVAL:%.*]] = call half @llvm.pow.f16(half 1.000000e+01, half [[X]])
; CHECK-NEXT: ret half [[RETVAL]]
;
%retval = call half @llvm.pow.f16(half 10.0, half %x)
@@ -1482,7 +1482,7 @@ define double @test_pow_10_f64(double %x) {
define fp128 @test_pow_10_fp128(fp128 %x) {
; CHECK-LABEL: define fp128 @test_pow_10_fp128(
; CHECK-SAME: fp128 [[X:%.*]]) {
-; CHECK-NEXT: [[RETVAL:%.*]] = call fp128 @llvm.pow.f128(fp128 0xL00000000000000004002400000000000, fp128 [[X]])
+; CHECK-NEXT: [[RETVAL:%.*]] = call fp128 @llvm.pow.f128(fp128 1.000000e+01, fp128 [[X]])
; CHECK-NEXT: ret fp128 [[RETVAL]]
;
%ten = fpext double 10.0 to fp128
@@ -1493,7 +1493,7 @@ define fp128 @test_pow_10_fp128(fp128 %x) {
define bfloat @test_pow_10_bf16(bfloat %x) {
; CHECK-LABEL: define bfloat @test_pow_10_bf16(
; CHECK-SAME: bfloat [[X:%.*]]) {
-; CHECK-NEXT: [[RETVAL:%.*]] = call bfloat @llvm.pow.bf16(bfloat 0xR4120, bfloat [[X]])
+; CHECK-NEXT: [[RETVAL:%.*]] = call bfloat @llvm.pow.bf16(bfloat 1.000000e+01, bfloat [[X]])
; CHECK-NEXT: ret bfloat [[RETVAL]]
;
%retval = call bfloat @llvm.pow.bf16(bfloat 10.0, bfloat %x)
@@ -1503,7 +1503,7 @@ define bfloat @test_pow_10_bf16(bfloat %x) {
define <2 x half> @test_pow_10_v2f16(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_pow_10_v2f16(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
-; CHECK-NEXT: [[RETVAL:%.*]] = call <2 x half> @llvm.pow.v2f16(<2 x half> splat (half 0xH4900), <2 x half> [[X]])
+; CHECK-NEXT: [[RETVAL:%.*]] = call <2 x half> @llvm.pow.v2f16(<2 x half> splat (half 1.000000e+01), <2 x half> [[X]])
; CHECK-NEXT: ret <2 x half> [[RETVAL]]
;
%retval = call <2 x half> @llvm.pow.v2f16(<2 x half> <half 10.0, half 10.0>, <2 x half> %x)
@@ -1533,7 +1533,7 @@ define <2 x double> @test_pow_10_v2f64(<2 x double> %x) {
define <2 x bfloat> @test_pow_10_v2bf16(<2 x bfloat> %x) {
; CHECK-LABEL: define <2 x bfloat> @test_pow_10_v2bf16(
; CHECK-SAME: <2 x bfloat> [[X:%.*]]) {
-; CHECK-NEXT: [[RETVAL:%.*]] = call <2 x bfloat> @llvm.pow.v2bf16(<2 x bfloat> splat (bfloat 0xR4120), <2 x bfloat> [[X]])
+; CHECK-NEXT: [[RETVAL:%.*]] = call <2 x bfloat> @llvm.pow.v2bf16(<2 x bfloat> splat (bfloat 1.000000e+01), <2 x bfloat> [[X]])
; CHECK-NEXT: ret <2 x bfloat> [[RETVAL]]
;
%retval = call <2 x bfloat> @llvm.pow.v2bf16(<2 x bfloat> <bfloat 10.0, bfloat 10.0>, <2 x bfloat> %x)
diff --git a/llvm/test/Transforms/InstCombine/pow-3.ll b/llvm/test/Transforms/InstCombine/pow-3.ll
index 20d8afbe755d7..1d5a39a8e2ed4 100644
--- a/llvm/test/Transforms/InstCombine/pow-3.ll
+++ b/llvm/test/Transforms/InstCombine/pow-3.ll
@@ -17,8 +17,8 @@ define double @sqrt_intrinsic(double %x) {
; CHECK-LABEL: @sqrt_intrinsic(
; CHECK-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
-; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], -inf
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[ISINF]], double +inf, double [[ABS]]
; CHECK-NEXT: ret double [[RETVAL]]
;
%retval = call double @llvm.pow.f64(double %x, double 0.5)
diff --git a/llvm/test/Transforms/InstCombine/pow-cbrt.ll b/llvm/test/Transforms/InstCombine/pow-cbrt.ll
index fd26ec843ee98..5241a7b63ea88 100644
--- a/llvm/test/Transforms/InstCombine/pow-cbrt.ll
+++ b/llvm/test/Transforms/InstCombine/pow-cbrt.ll
@@ -3,7 +3,7 @@
define double @pow_intrinsic_third_fast(double %x) {
; CHECK-LABEL: @pow_intrinsic_third_fast(
-; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double 0x3FD5555555555555)
+; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double f0x3FD5555555555555)
; CHECK-NEXT: ret double [[POW]]
;
%pow = call fast double @llvm.pow.f64(double %x, double 0x3fd5555555555555)
@@ -12,7 +12,7 @@ define double @pow_intrinsic_third_fast(double %x) {
define float @powf_intrinsic_third_fast(float %x) {
; CHECK-LABEL: @powf_intrinsic_third_fast(
-; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[X:%.*]], float 0x3FD5555560000000)
+; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[X:%.*]], float f0x3EAAAAAB)
; CHECK-NEXT: ret float [[POW]]
;
%pow = call fast float @llvm.pow.f32(float %x, float 0x3fd5555560000000)
@@ -21,7 +21,7 @@ define float @powf_intrinsic_third_fast(float %x) {
define double @pow_intrinsic_third_approx(double %x) {
; CHECK-LABEL: @pow_intrinsic_third_approx(
-; CHECK-NEXT: [[POW:%.*]] = call afn double @llvm.pow.f64(double [[X:%.*]], double 0x3FD5555555555555)
+; CHECK-NEXT: [[POW:%.*]] = call afn double @llvm.pow.f64(double [[X:%.*]], double f0x3FD5555555555555)
; CHECK-NEXT: ret double [[POW]]
;
%pow = call afn double @llvm.pow.f64(double %x, double 0x3fd5555555555555)
@@ -30,7 +30,7 @@ define double @pow_intrinsic_third_approx(double %x) {
define float @powf_intrinsic_third_approx(float %x) {
; CHECK-LABEL: @powf_intrinsic_third_approx(
-; CHECK-NEXT: [[POW:%.*]] = call afn float @llvm.pow.f32(float [[X:%.*]], float 0x3FD5555560000000)
+; CHECK-NEXT: [[POW:%.*]] = call afn float @llvm.pow.f32(float [[X:%.*]], float f0x3EAAAAAB)
; CHECK-NEXT: ret float [[POW]]
;
%pow = call afn float @llvm.pow.f32(float %x, float 0x3fd5555560000000)
@@ -39,7 +39,7 @@ define float @powf_intrinsic_third_approx(float %x) {
define double @pow_libcall_third_fast(double %x) {
; CHECK-LABEL: @pow_libcall_third_fast(
-; CHECK-NEXT: [[POW:%.*]] = call fast double @pow(double [[X:%.*]], double 0x3FD5555555555555)
+; CHECK-NEXT: [[POW:%.*]] = call fast double @pow(double [[X:%.*]], double f0x3FD5555555555555)
; CHECK-NEXT: ret double [[POW]]
;
%pow = call fast double @pow(double %x, double 0x3fd5555555555555)
@@ -48,7 +48,7 @@ define double @pow_libcall_third_fast(double %x) {
define float @powf_libcall_third_fast(float %x) {
; CHECK-LABEL: @powf_libcall_third_fast(
-; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float 0x3FD5555560000000)
+; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float f0x3EAAAAAB)
; CHECK-NEXT: ret float [[POW]]
;
%pow = call fast float @powf(float %x, float 0x3fd5555560000000)
@@ -57,7 +57,7 @@ define float @powf_libcall_third_fast(float %x) {
define double @pow_intrinsic_negthird_fast(double %x) {
; CHECK-LABEL: @pow_intrinsic_negthird_fast(
-; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double 0xBFD5555555555555)
+; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double f0xBFD5555555555555)
; CHECK-NEXT: ret double [[POW]]
;
%pow = call fast double @llvm.pow.f64(double %x, double 0xbfd5555555555555)
@@ -66,7 +66,7 @@ define double @pow_intrinsic_negthird_fast(double %x) {
define float @powf_intrinsic_negthird_fast(float %x) {
; CHECK-LABEL: @powf_intrinsic_negthird_fast(
-; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[X:%.*]], float 0xBFD5555560000000)
+; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[X:%.*]], float f0xBEAAAAAB)
; CHECK-NEXT: ret float [[POW]]
;
%pow = call fast float @llvm.pow.f32(float %x, float 0xbfd5555560000000)
@@ -75,7 +75,7 @@ define float @powf_intrinsic_negthird_fast(float %x) {
define double @pow_intrinsic_negthird_approx(double %x) {
; CHECK-LABEL: @pow_intrinsic_negthird_approx(
-; CHECK-NEXT: [[POW:%.*]] = call afn double @llvm.pow.f64(double [[X:%.*]], double 0xBFD5555555555555)
+; CHECK-NEXT: [[POW:%.*]] = call afn double @llvm.pow.f64(double [[X:%.*]], double f0xBFD5555555555555)
; CHECK-NEXT: ret double [[POW]]
;
%pow = call afn double @llvm.pow.f64(double %x, double 0xbfd5555555555555)
@@ -84,7 +84,7 @@ define double @pow_intrinsic_negthird_approx(double %x) {
define float @powf_intrinsic_negthird_approx(float %x) {
; CHECK-LABEL: @powf_intrinsic_negthird_approx(
-; CHECK-NEXT: [[POW:%.*]] = call afn float @llvm.pow.f32(float [[X:%.*]], float 0xBFD5555560000000)
+; CHECK-NEXT: [[POW:%.*]] = call afn float @llvm.pow.f32(float [[X:%.*]], float f0xBEAAAAAB)
; CHECK-NEXT: ret float [[POW]]
;
%pow = call afn float @llvm.pow.f32(float %x, float 0xbfd5555560000000)
@@ -93,7 +93,7 @@ define float @powf_intrinsic_negthird_approx(float %x) {
define double @pow_libcall_negthird_fast(double %x) {
; CHECK-LABEL: @pow_libcall_negthird_fast(
-; CHECK-NEXT: [[POW:%.*]] = call fast double @pow(double [[X:%.*]], double 0xBFD5555555555555)
+; CHECK-NEXT: [[POW:%.*]] = call fast double @pow(double [[X:%.*]], double f0xBFD5555555555555)
; CHECK-NEXT: ret double [[POW]]
;
%pow = call fast double @pow(double %x, double 0xbfd5555555555555)
@@ -102,7 +102,7 @@ define double @pow_libcall_negthird_fast(double %x) {
define float @powf_libcall_negthird_fast(float %x) {
; CHECK-LABEL: @powf_libcall_negthird_fast(
-; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float 0xBFD5555560000000)
+; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float f0xBEAAAAAB)
; CHECK-NEXT: ret float [[POW]]
;
%pow = call fast float @powf(float %x, float 0xbfd5555560000000)
diff --git a/llvm/test/Transforms/InstCombine/pow-sqrt.ll b/llvm/test/Transforms/InstCombine/pow-sqrt.ll
index 7eef670ccea3d..d6ce33e8577b0 100644
--- a/llvm/test/Transforms/InstCombine/pow-sqrt.ll
+++ b/llvm/test/Transforms/InstCombine/pow-sqrt.ll
@@ -20,8 +20,8 @@ define double @pow_intrinsic_half_no_FMF(double %x) {
; CHECK-LABEL: @pow_intrinsic_half_no_FMF(
; CHECK-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
-; CHECK-NEXT: [[POW:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], -inf
+; CHECK-NEXT: [[POW:%.*]] = select i1 [[ISINF]], double +inf, double [[ABS]]
; CHECK-NEXT: ret double [[POW]]
;
%pow = call double @llvm.pow.f64(double %x, double 5.0e-01)
@@ -51,8 +51,8 @@ define <2 x double> @pow_intrinsic_half_approx(<2 x double> %x) {
; CHECK-LABEL: @pow_intrinsic_half_approx(
; CHECK-NEXT: [[SQRT:%.*]] = call afn <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq <2 x double> [[X]], splat (double 0xFFF0000000000000)
-; CHECK-NEXT: [[POW:%.*]] = select afn <2 x i1> [[ISINF]], <2 x double> splat (double 0x7FF0000000000000), <2 x double> [[ABS]]
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq <2 x double> [[X]], splat (double -inf)
+; CHECK-NEXT: [[POW:%.*]] = select afn <2 x i1> [[ISINF]], <2 x double> splat (double +inf), <2 x double> [[ABS]]
; CHECK-NEXT: ret <2 x double> [[POW]]
;
%pow = call afn <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 5.0e-01, double 5.0e-01>)
@@ -116,8 +116,8 @@ define double @pow_libcall_half_nsz(double %x) {
define double @pow_intrinsic_half_nsz(double %x) {
; CHECK-LABEL: @pow_intrinsic_half_nsz(
; CHECK-NEXT: [[SQRT:%.*]] = call nsz double @llvm.sqrt.f64(double [[X:%.*]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz oeq double [[X]], 0xFFF0000000000000
-; CHECK-NEXT: [[POW:%.*]] = select nsz i1 [[ISINF]], double 0x7FF0000000000000, double [[SQRT]]
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz oeq double [[X]], -inf
+; CHECK-NEXT: [[POW:%.*]] = select nsz i1 [[ISINF]], double +inf, double [[SQRT]]
; CHECK-NEXT: ret double [[POW]]
;
%pow = call nsz double @llvm.pow.f64(double %x, double 5.0e-01)
@@ -221,7 +221,7 @@ define <2 x double> @pow_intrinsic_neghalf_reassoc(<2 x double> %x) {
; CHECK-LABEL: @pow_intrinsic_neghalf_reassoc(
; CHECK-NEXT: [[SQRT:%.*]] = call reassoc <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call reassoc <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp reassoc oeq <2 x double> [[X]], splat (double 0xFFF0000000000000)
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp reassoc oeq <2 x double> [[X]], splat (double -inf)
; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc <2 x double> splat (double 1.000000e+00), [[ABS]]
; CHECK-NEXT: [[RECIPROCAL:%.*]] = select <2 x i1> [[ISINF]], <2 x double> zeroinitializer, <2 x double> [[TMP1]]
; CHECK-NEXT: ret <2 x double> [[RECIPROCAL]]
@@ -238,7 +238,7 @@ define <2 x double> @pow_intrinsic_neghalf_afn(<2 x double> %x) {
; CHECK-LABEL: @pow_intrinsic_neghalf_afn(
; CHECK-NEXT: [[SQRT:%.*]] = call afn <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq <2 x double> [[X]], splat (double 0xFFF0000000000000)
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq <2 x double> [[X]], splat (double -inf)
; CHECK-NEXT: [[TMP1:%.*]] = fdiv afn <2 x double> splat (double 1.000000e+00), [[ABS]]
; CHECK-NEXT: [[RECIPROCAL:%.*]] = select <2 x i1> [[ISINF]], <2 x double> zeroinitializer, <2 x double> [[TMP1]]
; CHECK-NEXT: ret <2 x double> [[RECIPROCAL]]
@@ -285,7 +285,7 @@ define double @pow_libcall_neghalf_nsz(double %x) {
define double @pow_intrinsic_neghalf_nsz(double %x) {
; CHECK-LABEL: @pow_intrinsic_neghalf_nsz(
; CHECK-NEXT: [[SQRT:%.*]] = call nsz afn double @llvm.sqrt.f64(double [[X:%.*]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz afn oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz afn oeq double [[X]], -inf
; CHECK-NEXT: [[TMP1:%.*]] = fdiv nsz afn double 1.000000e+00, [[SQRT]]
; CHECK-NEXT: [[RECIPROCAL:%.*]] = select i1 [[ISINF]], double 0.000000e+00, double [[TMP1]]
; CHECK-NEXT: ret double [[RECIPROCAL]]
diff --git a/llvm/test/Transforms/InstCombine/pow-to-ldexp.ll b/llvm/test/Transforms/InstCombine/pow-to-ldexp.ll
index 727e2693e429d..d2b1f6e0a4337 100644
--- a/llvm/test/Transforms/InstCombine/pow-to-ldexp.ll
+++ b/llvm/test/Transforms/InstCombine/pow-to-ldexp.ll
@@ -116,7 +116,7 @@ define double @pow_sitofp_f64_const_base_2(i32 %x) {
define half @pow_sitofp_f16_const_base_2(i32 %x) {
; CHECK-LABEL: define half @pow_sitofp_f16_const_base_2(
; CHECK-SAME: i32 [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call half @llvm.ldexp.f16.i32(half 0xH3C00, i32 [[X]])
+; CHECK-NEXT: [[POW:%.*]] = tail call half @llvm.ldexp.f16.i32(half 1.000000e+00, i32 [[X]])
; CHECK-NEXT: ret half [[POW]]
;
%itofp = sitofp i32 %x to half
@@ -198,7 +198,7 @@ define <vscale x 4 x float> @pow_sitofp_nxv4f32_const_base_2(<vscale x 4 x i32>
define <2 x half> @pow_sitofp_v2f16_const_base_2(<2 x i32> %x) {
; CHECK-LABEL: define <2 x half> @pow_sitofp_v2f16_const_base_2(
; CHECK-SAME: <2 x i32> [[X:%.*]]) {
-; CHECK-NEXT: [[EXP2:%.*]] = tail call <2 x half> @llvm.ldexp.v2f16.v2i32(<2 x half> splat (half 0xH3C00), <2 x i32> [[X]])
+; CHECK-NEXT: [[EXP2:%.*]] = tail call <2 x half> @llvm.ldexp.v2f16.v2i32(<2 x half> splat (half 1.000000e+00), <2 x i32> [[X]])
; CHECK-NEXT: ret <2 x half> [[EXP2]]
;
%itofp = sitofp <2 x i32> %x to <2 x half>
@@ -228,20 +228,20 @@ define <2 x half> @pow_sitofp_v2f16_const_base_8(<2 x i32> %x) {
; LDEXP-EXP2-LABEL: define <2 x half> @pow_sitofp_v2f16_const_base_8(
; LDEXP-EXP2-SAME: <2 x i32> [[X:%.*]]) {
; LDEXP-EXP2-NEXT: [[ITOFP:%.*]] = sitofp <2 x i32> [[X]] to <2 x half>
-; LDEXP-EXP2-NEXT: [[MUL:%.*]] = fmul nnan <2 x half> [[ITOFP]], splat (half 0xH4200)
+; LDEXP-EXP2-NEXT: [[MUL:%.*]] = fmul nnan <2 x half> [[ITOFP]], splat (half 3.000000e+00)
; LDEXP-EXP2-NEXT: [[EXP2:%.*]] = tail call <2 x half> @llvm.exp2.v2f16(<2 x half> [[MUL]])
; LDEXP-EXP2-NEXT: ret <2 x half> [[EXP2]]
;
; LDEXP-NOEXP2-LABEL: define <2 x half> @pow_sitofp_v2f16_const_base_8(
; LDEXP-NOEXP2-SAME: <2 x i32> [[X:%.*]]) {
; LDEXP-NOEXP2-NEXT: [[ITOFP:%.*]] = sitofp <2 x i32> [[X]] to <2 x half>
-; LDEXP-NOEXP2-NEXT: [[POW:%.*]] = tail call <2 x half> @llvm.pow.v2f16(<2 x half> splat (half 0xH4800), <2 x half> [[ITOFP]])
+; LDEXP-NOEXP2-NEXT: [[POW:%.*]] = tail call <2 x half> @llvm.pow.v2f16(<2 x half> splat (half 8.000000e+00), <2 x half> [[ITOFP]])
; LDEXP-NOEXP2-NEXT: ret <2 x half> [[POW]]
;
; NOLDEXP-LABEL: define <2 x half> @pow_sitofp_v2f16_const_base_8(
; NOLDEXP-SAME: <2 x i32> [[X:%.*]]) {
; NOLDEXP-NEXT: [[ITOFP:%.*]] = sitofp <2 x i32> [[X]] to <2 x half>
-; NOLDEXP-NEXT: [[MUL:%.*]] = fmul nnan <2 x half> [[ITOFP]], splat (half 0xH4200)
+; NOLDEXP-NEXT: [[MUL:%.*]] = fmul nnan <2 x half> [[ITOFP]], splat (half 3.000000e+00)
; NOLDEXP-NEXT: [[EXP2:%.*]] = tail call <2 x half> @llvm.exp2.v2f16(<2 x half> [[MUL]])
; NOLDEXP-NEXT: ret <2 x half> [[EXP2]]
;
@@ -286,7 +286,7 @@ define <2 x double> @pow_sitofp_v2f64_const_base_8(<2 x i32> %x) {
define fp128 @pow_sitofp_fp128_const_base_2(i32 %x) {
; CHECK-LABEL: define fp128 @pow_sitofp_fp128_const_base_2(
; CHECK-SAME: i32 [[X:%.*]]) {
-; CHECK-NEXT: [[EXP2:%.*]] = tail call fp128 @llvm.ldexp.f128.i32(fp128 0xL00000000000000003FFF000000000000, i32 [[X]])
+; CHECK-NEXT: [[EXP2:%.*]] = tail call fp128 @llvm.ldexp.f128.i32(fp128 1.000000e+00, i32 [[X]])
; CHECK-NEXT: ret fp128 [[EXP2]]
;
%itofp = sitofp i32 %x to fp128
@@ -381,7 +381,7 @@ define double @readnone_libcall_pow_sitofp_f32_const_base_2(i32 %x) {
define fp128 @readnone_libcall_powl_sitofp_fp128_const_base_2(i32 %x) {
; CHECK-LABEL: define fp128 @readnone_libcall_powl_sitofp_fp128_const_base_2(
; CHECK-SAME: i32 [[X:%.*]]) {
-; CHECK-NEXT: [[EXP2:%.*]] = tail call fp128 @llvm.ldexp.f128.i32(fp128 0xL00000000000000003FFF000000000000, i32 [[X]])
+; CHECK-NEXT: [[EXP2:%.*]] = tail call fp128 @llvm.ldexp.f128.i32(fp128 1.000000e+00, i32 [[X]])
; CHECK-NEXT: ret fp128 [[EXP2]]
;
%itofp = sitofp i32 %x to fp128
diff --git a/llvm/test/Transforms/InstCombine/pow_fp_int.ll b/llvm/test/Transforms/InstCombine/pow_fp_int.ll
index f4f7895582268..169992b8755fe 100644
--- a/llvm/test/Transforms/InstCombine/pow_fp_int.ll
+++ b/llvm/test/Transforms/InstCombine/pow_fp_int.ll
@@ -245,7 +245,7 @@ define double @pow_uitofp_const_base_fast_i32(i32 %x) {
; CHECK-LABEL: define double @pow_uitofp_const_base_fast_i32(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[SUBFP:%.*]] = uitofp i32 [[X]] to float
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[SUBFP]], 0x4006757680000000
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[SUBFP]], f0x4033ABB4
; CHECK-NEXT: [[EXP2:%.*]] = tail call fast float @llvm.exp2.f32(float [[MUL]])
; CHECK-NEXT: [[RES:%.*]] = fpext float [[EXP2]] to double
; CHECK-NEXT: ret double [[RES]]
@@ -315,7 +315,7 @@ define double @pow_sitofp_const_base_fast_i64(i64 %x) {
; CHECK-LABEL: define double @pow_sitofp_const_base_fast_i64(
; CHECK-SAME: i64 [[X:%.*]]) {
; CHECK-NEXT: [[SUBFP:%.*]] = sitofp i64 [[X]] to float
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[SUBFP]], 0x4006757680000000
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[SUBFP]], f0x4033ABB4
; CHECK-NEXT: [[EXP2:%.*]] = tail call fast float @llvm.exp2.f32(float [[MUL]])
; CHECK-NEXT: [[RES:%.*]] = fpext float [[EXP2]] to double
; CHECK-NEXT: ret double [[RES]]
@@ -331,7 +331,7 @@ define double @pow_uitofp_const_base_fast_i64(i64 %x) {
; CHECK-LABEL: define double @pow_uitofp_const_base_fast_i64(
; CHECK-SAME: i64 [[X:%.*]]) {
; CHECK-NEXT: [[SUBFP:%.*]] = uitofp i64 [[X]] to float
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[SUBFP]], 0x4006757680000000
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[SUBFP]], f0x4033ABB4
; CHECK-NEXT: [[EXP2:%.*]] = tail call fast float @llvm.exp2.f32(float [[MUL]])
; CHECK-NEXT: [[RES:%.*]] = fpext float [[EXP2]] to double
; CHECK-NEXT: ret double [[RES]]
diff --git a/llvm/test/Transforms/InstCombine/remquo.ll b/llvm/test/Transforms/InstCombine/remquo.ll
index b2499ea13179e..eeeb50f1d0533 100644
--- a/llvm/test/Transforms/InstCombine/remquo.ll
+++ b/llvm/test/Transforms/InstCombine/remquo.ll
@@ -30,7 +30,7 @@ define float @remquo_f32_round(ptr %quo) {
; CHECK-SAME: ptr [[QUO:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: store i32 -6, ptr [[QUO]], align 4
-; CHECK-NEXT: ret float 0xBFC9999900000000
+; CHECK-NEXT: ret float f0xBE4CCCC8
;
entry:
%call = call float @remquof(float -5.000000e+00, float 0x3FE99999A0000000, ptr %quo)
@@ -55,7 +55,7 @@ define float @remquo_f32_inf_x(ptr %quo) {
; CHECK-LABEL: define float @remquo_f32_inf_x(
; CHECK-SAME: ptr [[QUO:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[CALL:%.*]] = call float @remquof(float 0x7FF0000000000000, float 1.000000e+00, ptr [[QUO]])
+; CHECK-NEXT: [[CALL:%.*]] = call float @remquof(float +inf, float 1.000000e+00, ptr [[QUO]])
; CHECK-NEXT: ret float [[CALL]]
;
entry:
@@ -91,7 +91,7 @@ define float @remquo_f32_nan_x(ptr %quo) {
; CHECK-LABEL: define float @remquo_f32_nan_x(
; CHECK-SAME: ptr [[QUO:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[CALL:%.*]] = call float @remquof(float 0x7FF8000000000000, float 1.000000e+00, ptr [[QUO]])
+; CHECK-NEXT: [[CALL:%.*]] = call float @remquof(float +qnan, float 1.000000e+00, ptr [[QUO]])
; CHECK-NEXT: ret float [[CALL]]
;
entry:
@@ -103,7 +103,7 @@ define float @remquo_f32_nan_y(ptr %quo) {
; CHECK-LABEL: define float @remquo_f32_nan_y(
; CHECK-SAME: ptr [[QUO:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[CALL:%.*]] = call float @remquof(float 1.000000e+00, float 0x7FF8000000000000, ptr [[QUO]])
+; CHECK-NEXT: [[CALL:%.*]] = call float @remquof(float 1.000000e+00, float +qnan, ptr [[QUO]])
; CHECK-NEXT: ret float [[CALL]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/remquol-fp128.ll b/llvm/test/Transforms/InstCombine/remquol-fp128.ll
index 38e0a6040a140..4a85371986118 100644
--- a/llvm/test/Transforms/InstCombine/remquol-fp128.ll
+++ b/llvm/test/Transforms/InstCombine/remquol-fp128.ll
@@ -6,7 +6,7 @@ define fp128 @remquo_fp128(ptr %quo) {
; CHECK-SAME: ptr [[QUO:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: store i32 -2, ptr [[QUO]], align 4
-; CHECK-NEXT: ret fp128 0xL00000000000000003FFF000000000000
+; CHECK-NEXT: ret fp128 1.000000e+00
;
entry:
%call = call fp128 @remquol(fp128 0xL0000000000000000C001400000000000, fp128 0xL00000000000000004000800000000000, ptr %quo)
diff --git a/llvm/test/Transforms/InstCombine/remquol-fp80.ll b/llvm/test/Transforms/InstCombine/remquol-fp80.ll
index fe65ee1acc902..01f96dcafdfca 100644
--- a/llvm/test/Transforms/InstCombine/remquol-fp80.ll
+++ b/llvm/test/Transforms/InstCombine/remquol-fp80.ll
@@ -6,7 +6,7 @@ define x86_fp80 @remquo_fp80(ptr %quo) {
; CHECK-SAME: ptr [[QUO:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: store i32 -2, ptr [[QUO]], align 4
-; CHECK-NEXT: ret x86_fp80 0xK3FFF8000000000000000
+; CHECK-NEXT: ret x86_fp80 1.000000e+00
;
entry:
%call = call x86_fp80 @remquol(x86_fp80 0xKC001A000000000000000, x86_fp80 0xK4000C000000000000000, ptr %quo)
diff --git a/llvm/test/Transforms/InstCombine/remquol-ppc-fp128.ll b/llvm/test/Transforms/InstCombine/remquol-ppc-fp128.ll
index 86dfd01f859ac..1293e1bcaf206 100644
--- a/llvm/test/Transforms/InstCombine/remquol-ppc-fp128.ll
+++ b/llvm/test/Transforms/InstCombine/remquol-ppc-fp128.ll
@@ -6,7 +6,7 @@ define ppc_fp128 @remquo_ppc_fp128(ptr %quo) {
; CHECK-SAME: ptr [[QUO:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: store i32 -2, ptr [[QUO]], align 4
-; CHECK-NEXT: ret ppc_fp128 0xM3FF00000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 1.000000e+00
;
entry:
%call = call ppc_fp128 @remquol(ppc_fp128 0xMC0140000000000000000000000000000, ppc_fp128 0xM40080000000000000000000000000000, ptr %quo)
diff --git a/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll b/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll
index 29c0ac415ce7c..b4f42ff822965 100644
--- a/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll
@@ -77,7 +77,7 @@ define void @scalarize_phi(ptr %n, ptr %inout) {
; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]]
; CHECK: for.body:
; CHECK-NEXT: store volatile float [[TMP0]], ptr [[INOUT]], align 4
-; CHECK-NEXT: [[TMP1]] = fmul float [[TMP0]], 0x4002A3D700000000
+; CHECK-NEXT: [[TMP1]] = fmul float [[TMP0]], 2.330000e+00
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end:
@@ -112,7 +112,7 @@ define float @extract_element_binop_splat_constant_index(<4 x float> %x) {
;
; CHECK-LABEL: @extract_element_binop_splat_constant_index(
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[X:%.*]], i64 2
-; CHECK-NEXT: [[R:%.*]] = fadd float [[TMP1]], 0x4002A3D700000000
+; CHECK-NEXT: [[R:%.*]] = fadd float [[TMP1]], 2.330000e+00
; CHECK-NEXT: ret float [[R]]
;
%b = fadd <4 x float> %x, <float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000>
diff --git a/llvm/test/Transforms/InstCombine/scalarization.ll b/llvm/test/Transforms/InstCombine/scalarization.ll
index c4adf756f7756..28c0d8dbf5064 100644
--- a/llvm/test/Transforms/InstCombine/scalarization.ll
+++ b/llvm/test/Transforms/InstCombine/scalarization.ll
@@ -77,7 +77,7 @@ define void @scalarize_phi(ptr %n, ptr %inout) {
; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]]
; CHECK: for.body:
; CHECK-NEXT: store volatile float [[TMP0]], ptr [[INOUT]], align 4
-; CHECK-NEXT: [[TMP1]] = fmul float [[TMP0]], 0x4002A3D700000000
+; CHECK-NEXT: [[TMP1]] = fmul float [[TMP0]], 2.330000e+00
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end:
@@ -156,7 +156,7 @@ define float @extract_element_binop_splat_constant_index(<4 x float> %x) {
;
; CHECK-LABEL: @extract_element_binop_splat_constant_index(
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[X:%.*]], i64 2
-; CHECK-NEXT: [[R:%.*]] = fadd float [[TMP1]], 0x4002A3D700000000
+; CHECK-NEXT: [[R:%.*]] = fadd float [[TMP1]], 2.330000e+00
; CHECK-NEXT: ret float [[R]]
;
%b = fadd <4 x float> %x, <float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000>
diff --git a/llvm/test/Transforms/InstCombine/select-fcmp-fmul-zero-absorbing-value.ll b/llvm/test/Transforms/InstCombine/select-fcmp-fmul-zero-absorbing-value.ll
index 48a01f73adac6..8b4163c39bfc2 100644
--- a/llvm/test/Transforms/InstCombine/select-fcmp-fmul-zero-absorbing-value.ll
+++ b/llvm/test/Transforms/InstCombine/select-fcmp-fmul-zero-absorbing-value.ll
@@ -50,7 +50,7 @@ define float @select_oeq_fmul_fneg_or_fneg_src(float %x) {
; CHECK-LABEL: define float @select_oeq_fmul_fneg_or_fneg_src(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FNEG_X:%.*]] = fneg float [[X]]
-; CHECK-NEXT: [[MUL_FNEG_X:%.*]] = fmul float [[X]], 0xC170000000000000
+; CHECK-NEXT: [[MUL_FNEG_X:%.*]] = fmul float [[X]], f0xCB800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_FNEG_X]], float [[FNEG_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -67,7 +67,7 @@ define float @select_oeq_fmul_fneg_fabs_or_fneg_fabs_src(float %x) {
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
; CHECK-NEXT: [[FNEG_FABS_X:%.*]] = fneg float [[FABS_X]]
-; CHECK-NEXT: [[MUL_FNEG_FABS_X:%.*]] = fmul float [[FABS_X]], 0xC170000000000000
+; CHECK-NEXT: [[MUL_FNEG_FABS_X:%.*]] = fmul float [[FABS_X]], f0xCB800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_FNEG_FABS_X]], float [[FNEG_FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -85,7 +85,7 @@ define float @select_oeq_fdiv_swapped_fabs_or_fabs_src(float %x) {
; CHECK-LABEL: define float @select_oeq_fdiv_swapped_fabs_or_fabs_src(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fdiv float 0x4170000000000000, [[FABS_X]]
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fdiv float f0x4B800000, [[FABS_X]]
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_FABS_X]], float [[FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -133,7 +133,7 @@ define float @select_oeq_fmul_fabs_or_fabs_src_wrong_order(float %x) {
; CHECK-LABEL: define float @select_oeq_fmul_fabs_or_fabs_src_wrong_order(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[FABS_X]], float [[MUL_FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -150,7 +150,7 @@ define float @select_olt_fmul_fabs_or_fabs_src(float %x) {
; CHECK-LABEL: define float @select_olt_fmul_fabs_or_fabs_src(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp olt float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_FABS_X]], float [[FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -182,7 +182,7 @@ define float @select_fmul_or_fabs_src(float %x) {
; CHECK-LABEL: define float @select_fmul_or_fabs_src(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[X]], f0x4B800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_FABS_X]], float [[FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -214,7 +214,7 @@ define float @select_fmul_nsz_or_fabs_src(float %x) {
; CHECK-LABEL: define float @select_fmul_nsz_or_fabs_src(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_X:%.*]] = fmul nsz float [[X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_X:%.*]] = fmul nsz float [[X]], f0x4B800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_X]], float [[FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -246,7 +246,7 @@ define float @select_ueq_fmul_fabs_or_fabs_src(float %x) {
; CHECK-LABEL: define float @select_ueq_fmul_fabs_or_fabs_src(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp ueq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_FABS_X]], float [[FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -263,7 +263,7 @@ define float @select_one_fmul_fabs_or_fabs_src(float %x) {
; CHECK-LABEL: define float @select_one_fmul_fabs_or_fabs_src(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_NOT_ZERO:%.*]] = fcmp one float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_NOT_ZERO]], float [[FABS_X]], float [[MUL_FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -320,7 +320,7 @@ define float @degenerate_fmul_nan(float %x) {
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float 0x7FF8000000000000, float [[FABS_X]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float +qnan, float [[FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
;
%fabs.x = call float @llvm.fabs.f32(float %x)
@@ -334,7 +334,7 @@ define float @degenerate_fmul_posinf(float %x) {
; CHECK-LABEL: define float @degenerate_fmul_posinf(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], 0x7FF0000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], +inf
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_FABS_X]], float [[FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -350,7 +350,7 @@ define float @degenerate_fmul_neginf(float %x) {
; CHECK-LABEL: define float @degenerate_fmul_neginf(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], 0xFFF0000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], -inf
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_FABS_X]], float [[FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -367,7 +367,7 @@ define float @cmp_one_nnan_fabs(float %x) {
; CHECK-LABEL: define float @cmp_one_nnan_fabs(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call nnan float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul nnan float [[FABS_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul nnan float [[FABS_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_NOT_ZERO:%.*]] = fcmp one float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_NOT_ZERO]], float [[FABS_X]], float [[MUL_FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -384,7 +384,7 @@ define float @cmp_one_nnan_fmul(float %x) {
; CHECK-LABEL: define float @cmp_one_nnan_fmul(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul nnan float [[FABS_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul nnan float [[FABS_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_NOT_ZERO:%.*]] = fcmp one float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_NOT_ZERO]], float [[FABS_X]], float [[MUL_FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -401,7 +401,7 @@ define float @cmp_one_nnan_fcmp(float %x) {
; CHECK-LABEL: define float @cmp_one_nnan_fcmp(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_NOT_ZERO:%.*]] = fcmp nnan one float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_NOT_ZERO]], float [[FABS_X]], float [[MUL_FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -418,7 +418,7 @@ define float @cmp_one_nnan_select(float %x) {
; CHECK-LABEL: define float @cmp_one_nnan_select(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_FABS_X:%.*]] = fmul float [[FABS_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_NOT_ZERO:%.*]] = fcmp one float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select nnan i1 [[X_IS_NOT_ZERO]], float [[FABS_X]], float [[MUL_FABS_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -515,7 +515,7 @@ define float @select_oeq_fmul_copysign_or_copysign_src(float %x, float %sign) {
; CHECK-LABEL: define float @select_oeq_fmul_copysign_or_copysign_src(
; CHECK-SAME: float [[X:%.*]], float [[SIGN:%.*]]) {
; CHECK-NEXT: [[SIGN_X:%.*]] = call float @llvm.copysign.f32(float [[X]], float [[SIGN]])
-; CHECK-NEXT: [[MUL_SIGN_X:%.*]] = fmul float [[SIGN_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_SIGN_X:%.*]] = fmul float [[SIGN_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_SIGN_X]], float [[SIGN_X]]
; CHECK-NEXT: ret float [[SELECT]]
@@ -531,7 +531,7 @@ define float @select_oeq_fmul_copysign_or_src(float %x, float %sign) {
; CHECK-LABEL: define float @select_oeq_fmul_copysign_or_src(
; CHECK-SAME: float [[X:%.*]], float [[SIGN:%.*]]) {
; CHECK-NEXT: [[SIGN_X:%.*]] = call float @llvm.copysign.f32(float [[X]], float [[SIGN]])
-; CHECK-NEXT: [[MUL_SIGN_X:%.*]] = fmul float [[SIGN_X]], 0x4170000000000000
+; CHECK-NEXT: [[MUL_SIGN_X:%.*]] = fmul float [[SIGN_X]], f0x4B800000
; CHECK-NEXT: [[X_IS_ZERO:%.*]] = fcmp oeq float [[X]], 0.000000e+00
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[X_IS_ZERO]], float [[MUL_SIGN_X]], float [[X]]
; CHECK-NEXT: ret float [[SELECT]]
diff --git a/llvm/test/Transforms/InstCombine/select-with-extreme-eq-cond.ll b/llvm/test/Transforms/InstCombine/select-with-extreme-eq-cond.ll
index 7f2cca44eab3b..20923ec4224a3 100644
--- a/llvm/test/Transforms/InstCombine/select-with-extreme-eq-cond.ll
+++ b/llvm/test/Transforms/InstCombine/select-with-extreme-eq-cond.ll
@@ -267,8 +267,8 @@ define i1 @compare_float_negative(half %x, half %y) {
; CHECK-LABEL: define i1 @compare_float_negative(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
; CHECK-NEXT: [[START:.*:]]
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq half [[X]], 0xH0000
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp one half [[Y]], 0xH0000
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq half [[X]], 0.000000e+00
+; CHECK-NEXT: [[TMP3:%.*]] = fcmp one half [[Y]], 0.000000e+00
; CHECK-NEXT: [[TMP4:%.*]] = fcmp ult half [[X]], [[Y]]
; CHECK-NEXT: [[RESULT:%.*]] = select i1 [[TMP2]], i1 [[TMP3]], i1 [[TMP4]]
; CHECK-NEXT: ret i1 [[RESULT]]
diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index feb889e6de99e..4110f6691a76b 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -1641,7 +1641,7 @@ define <4 x float> @PR33721(<4 x float> %w) {
; CHECK-SAME: <4 x float> [[W:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = fcmp ole <4 x float> [[W]], zeroinitializer
-; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[TMP0]], <4 x float> splat (float 0xFFFFFFFFE0000000), <4 x float> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[TMP0]], <4 x float> splat (float -nan(0x3FFFFF)), <4 x float> zeroinitializer
; CHECK-NEXT: ret <4 x float> [[TMP1]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/select_with_identical_phi.ll b/llvm/test/Transforms/InstCombine/select_with_identical_phi.ll
index db4965b2f03f0..4e9968f1d39f3 100644
--- a/llvm/test/Transforms/InstCombine/select_with_identical_phi.ll
+++ b/llvm/test/Transforms/InstCombine/select_with_identical_phi.ll
@@ -10,8 +10,8 @@ define void @select_with_identical_phi(ptr %m, ptr %n, i32 %count) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V0:%.*]] = phi float [ 0x4415AF1D80000000, [[ENTRY:%.*]] ], [ [[V0_1:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V0:%.*]] = phi float [ 1.000000e+20, [[ENTRY:%.*]] ], [ [[V0_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[Q:%.*]] = phi ptr [ [[M:%.*]], [[ENTRY]] ], [ [[Q_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[C:%.*]] = phi ptr [ [[N:%.*]], [[ENTRY]] ], [ [[C_NEXT:%.*]], [[FOR_BODY]] ]
@@ -69,7 +69,7 @@ define void @select_with_identical_phi_2(i1 %cmp1, i1 %cmp2, float %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2:%.*]], float [[X:%.*]], float [[V1]]
; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1
@@ -107,7 +107,7 @@ define void @select_with_identical_phi_3(i1 %cmp1, i1 %cmp2, float %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2:%.*]], float [[V1]], float [[X:%.*]]
; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1
@@ -145,7 +145,7 @@ define void @select_with_identical_phi_4(i1 %cmp1, i1 %cmp2, float %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2:%.*]], float [[X:%.*]], float [[V1]]
; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1
@@ -183,7 +183,7 @@ define void @select_with_identical_phi_5(i1 %cmp1, i1 %cmp2, float %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2:%.*]], float [[V1]], float [[X:%.*]]
; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1
@@ -221,7 +221,7 @@ define void @select_with_identical_phi_6(i1 %cmp1, i1 %cmp2, float %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2:%.*]], float [[X:%.*]], float [[V1]]
; CHECK-NEXT: [[INC_I]] = add nuw nsw i32 [[I]], 1
@@ -258,8 +258,8 @@ define void @select_with_identical_phi_negative_1(i1 %cmp1, i1 %cmp2, float %x)
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0x4415AF1D80000000, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[PHI_TO_REMOVE:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[PHI_TO_REMOVE_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ 1.000000e+20, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[PHI_TO_REMOVE:%.*]] = phi float [ -1.000000e+20, [[ENTRY]] ], [ [[PHI_TO_REMOVE_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SAME_AS_V1:%.*]] = select i1 [[CMP1:%.*]], float [[V1]], float [[PHI_TO_REMOVE]]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2:%.*]], float [[X:%.*]], float [[V1]]
@@ -298,8 +298,8 @@ define void @select_with_identical_phi_negative_2(i1 %cmp1, i1 %cmp2, float %x)
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[PHI_TO_REMOVE:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[PHI_TO_REMOVE_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[PHI_TO_REMOVE:%.*]] = phi float [ -1.000000e+20, [[ENTRY]] ], [ [[PHI_TO_REMOVE_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SAME_AS_V1:%.*]] = select i1 [[CMP1:%.*]], float [[V1]], float [[PHI_TO_REMOVE]]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2:%.*]], float [[V1]], float [[X:%.*]]
@@ -339,8 +339,8 @@ define void @select_with_identical_phi_negative_3(i1 %cmp1, i1 %cmp2, i1 %cmp3,
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[PHI_TO_REMOVE:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[PHI_TO_REMOVE_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY:%.*]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[PHI_TO_REMOVE:%.*]] = phi float [ -1.000000e+20, [[ENTRY]] ], [ [[PHI_TO_REMOVE_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SAME_AS_V1:%.*]] = select i1 [[CMP1:%.*]], float [[V1]], float [[PHI_TO_REMOVE]]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP3:%.*]], float [[V1]], float [[X:%.*]]
@@ -379,9 +379,9 @@ define void @select_with_identical_phi_negative_4(i1 %cmp1, i1 %cmp2, float %x)
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V0:%.*]] = phi float [ 0x4415AF1D80000000, [[ENTRY:%.*]] ], [ [[V0_1:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[V1:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[PHI_TO_REMOVE:%.*]] = phi float [ 0xC415AF1D80000000, [[ENTRY]] ], [ [[PHI_TO_REMOVE_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V0:%.*]] = phi float [ 1.000000e+20, [[ENTRY:%.*]] ], [ [[V0_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[V1:%.*]] = phi float [ -1.000000e+20, [[ENTRY]] ], [ [[V1_1:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[PHI_TO_REMOVE:%.*]] = phi float [ -1.000000e+20, [[ENTRY]] ], [ [[PHI_TO_REMOVE_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SAME_AS_V1:%.*]] = select i1 [[CMP1:%.*]], float [[V0]], float [[PHI_TO_REMOVE]]
; CHECK-NEXT: [[V1_1]] = select i1 [[CMP2:%.*]], float [[X:%.*]], float [[V1]]
diff --git a/llvm/test/Transforms/InstCombine/shufflevec-constant-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shufflevec-constant-inseltpoison.ll
index 967d370092d01..bf3189470ae9b 100644
--- a/llvm/test/Transforms/InstCombine/shufflevec-constant-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/shufflevec-constant-inseltpoison.ll
@@ -6,7 +6,7 @@ target triple = "i386-apple-darwin9"
define <4 x float> @__inff4() nounwind readnone {
; CHECK-LABEL: @__inff4(
-; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0x7FF0000000000000, float 0x7FF0000000000000>
+; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float +inf, float +inf>
;
%tmp14 = extractelement <1 x double> bitcast (<2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000> to <1 x double>), i32 0
%tmp4 = bitcast double %tmp14 to i64
diff --git a/llvm/test/Transforms/InstCombine/shufflevec-constant.ll b/llvm/test/Transforms/InstCombine/shufflevec-constant.ll
index 7d33473aecca5..bcad5d793e23f 100644
--- a/llvm/test/Transforms/InstCombine/shufflevec-constant.ll
+++ b/llvm/test/Transforms/InstCombine/shufflevec-constant.ll
@@ -6,7 +6,7 @@ target triple = "i386-apple-darwin9"
define <4 x float> @__inff4() nounwind readnone {
; CHECK-LABEL: @__inff4(
-; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0x7FF0000000000000, float 0x7FF0000000000000>
+; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float +inf, float +inf>
;
%tmp14 = extractelement <1 x double> bitcast (<2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000> to <1 x double>), i32 0
%tmp4 = bitcast double %tmp14 to i64
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
index 9bd87b545d5fc..f96cd2179b0ee 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
@@ -52,7 +52,7 @@ entry:
define nofpclass(pinf) { float } @ret_nofpclass_struct_ty_pinf__ninf() {
; CHECK-LABEL: define nofpclass(pinf) { float } @ret_nofpclass_struct_ty_pinf__ninf() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret { float } { float 0xFFF0000000000000 }
+; CHECK-NEXT: ret { float } { float -inf }
;
entry:
ret { float } { float 0xFFF0000000000000 }
@@ -61,7 +61,7 @@ entry:
define nofpclass(pinf) { float, float } @ret_nofpclass_multiple_elems_struct_ty_pinf__ninf() {
; CHECK-LABEL: define nofpclass(pinf) { float, float } @ret_nofpclass_multiple_elems_struct_ty_pinf__ninf() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret { float, float } { float 0xFFF0000000000000, float 0xFFF0000000000000 }
+; CHECK-NEXT: ret { float, float } { float -inf, float -inf }
;
entry:
ret { float, float } { float 0xFFF0000000000000, float 0xFFF0000000000000 }
@@ -70,7 +70,7 @@ entry:
define nofpclass(pinf) { <2 x float> } @ret_nofpclass_vector_elems_struct_ty_pinf__ninf() {
; CHECK-LABEL: define nofpclass(pinf) { <2 x float> } @ret_nofpclass_vector_elems_struct_ty_pinf__ninf() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret { <2 x float> } { <2 x float> splat (float 0xFFF0000000000000) }
+; CHECK-NEXT: ret { <2 x float> } { <2 x float> splat (float -inf) }
;
entry:
ret { <2 x float>} { <2 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000> }
@@ -81,7 +81,7 @@ entry:
define nofpclass(pinf) [ 1 x [ 1 x float ]] @ret_nofpclass_nested_array_ty_pinf__ninf() {
; CHECK-LABEL: @ret_nofpclass_nested_array_ty_pinf__ninf() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret {{.*}}float 0xFFF0000000000000
+; CHECK-NEXT: ret {{.*}}float -inf
;
entry:
ret [ 1 x [ 1 x float ]] [[ 1 x float ] [float 0xFFF0000000000000]]
@@ -100,7 +100,7 @@ entry:
define nofpclass(ninf) { float, float } @ret_nofpclass_multiple_elems_struct_ty_ninf__npinf() {
; CHECK-LABEL: define nofpclass(ninf) { float, float } @ret_nofpclass_multiple_elems_struct_ty_ninf__npinf() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret { float, float } { float 0x7FF0000000000000, float 0x7FF0000000000000 }
+; CHECK-NEXT: ret { float, float } { float +inf, float +inf }
;
entry:
ret { float, float } { float 0x7FF0000000000000, float 0x7FF0000000000000 }
@@ -183,7 +183,7 @@ define nofpclass(inf norm sub zero) float @simplify_demanded_extractvalue_only_n
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @simplify_demanded_extractvalue_only_nan(
; CHECK-SAME: i1 [[COND:%.*]], [2 x float] [[ARG0:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = extractvalue [2 x float] [[ARG0]], 0
-; CHECK-NEXT: [[EXTRACT:%.*]] = select i1 [[COND]], float [[TMP1]], float 0x7FF8000000000000
+; CHECK-NEXT: [[EXTRACT:%.*]] = select i1 [[COND]], float [[TMP1]], float +qnan
; CHECK-NEXT: ret float [[EXTRACT]]
;
%select = select i1 %cond, [2 x float] %arg0, [2 x float] [float 0x7FF8000000000000, float 0x7FF8000000000000]
@@ -238,7 +238,7 @@ define nofpclass(nan) [2 x float] @simplify_demanded_insertvalue_array_both(i1 %
define nofpclass(inf norm sub zero) [2 x float] @only_nan_simplify_demanded_insertvalue_array(i1 %cond, [2 x float] %array, float %unknown) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) [2 x float] @only_nan_simplify_demanded_insertvalue_array(
; CHECK-SAME: i1 [[COND:%.*]], [2 x float] [[ARRAY:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float 0x7FF8000000000000, float [[UNKNOWN]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float +qnan, float [[UNKNOWN]]
; CHECK-NEXT: [[INSERT:%.*]] = insertvalue [2 x float] [[ARRAY]], float [[SELECT]], 0
; CHECK-NEXT: ret [2 x float] [[INSERT]]
;
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
index ce5bdfb2a4973..8a380567b61ec 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
@@ -498,7 +498,7 @@ define nofpclass(nan) float @ret_nofpclass_nan__canonicalize_only_sub_dynamic()
define nofpclass(nan) float @ret_nofpclass_nan__canonicalize_only_ninf__dynamic(i1 %cond, float nofpclass(sub norm zero pinf) %must.be.ninf.or.nan) #1 {
; CHECK-LABEL: define nofpclass(nan) float @ret_nofpclass_nan__canonicalize_only_ninf__dynamic(
; CHECK-SAME: i1 [[COND:%.*]], float nofpclass(pinf zero sub norm) [[MUST_BE_NINF_OR_NAN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%canon = call float @llvm.canonicalize.f32(float %must.be.ninf.or.nan)
ret float %canon
@@ -507,7 +507,7 @@ define nofpclass(nan) float @ret_nofpclass_nan__canonicalize_only_ninf__dynamic(
define nofpclass(nan) float @ret_nofpclass_nan__canonicalize_only_pinf__dynamic(i1 %cond, float nofpclass(sub norm zero pinf) %must.be.pinf.or.nan) #1 {
; CHECK-LABEL: define nofpclass(nan) float @ret_nofpclass_nan__canonicalize_only_pinf__dynamic(
; CHECK-SAME: i1 [[COND:%.*]], float nofpclass(pinf zero sub norm) [[MUST_BE_PINF_OR_NAN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%canon = call float @llvm.canonicalize.f32(float %must.be.pinf.or.nan)
ret float %canon
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll
index 311c8ce7a1a26..56ca3a8134f8b 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll
@@ -155,7 +155,7 @@ define nofpclass(nan) float @handle_exp10(i1 %cond, float %maybe.nan, float nofp
define nofpclass(inf norm nan) float @ret_nofpclass_only_subzero__exp2_select_unknown_or_not_norm(i1 %cond, float %unknown, float nofpclass(norm) %not.norm) {
; CHECK-LABEL: define nofpclass(nan inf norm) float @ret_nofpclass_only_subzero__exp2_select_unknown_or_not_norm(
; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]], float nofpclass(norm) [[NOT_NORM:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[UNKNOWN]], float 0xFFF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[UNKNOWN]], float -inf
; CHECK-NEXT: [[EXP:%.*]] = call nnan float @llvm.exp2.f32(float [[SELECT]])
; CHECK-NEXT: ret float [[EXP]]
;
@@ -191,7 +191,7 @@ define nofpclass(inf norm nan sub) float @ret_nofpclass_only_zero__exp2_select_u
define nofpclass(ninf norm zero sub) float @pinf_result_implies_pnorm_source(float nofpclass(pinf nan) %maybe.pnorm) {
; CHECK-LABEL: define nofpclass(ninf zero sub norm) float @pinf_result_implies_pnorm_source(
; CHECK-SAME: float nofpclass(nan pinf) [[MAYBE_PNORM:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%exp = call float @llvm.exp2.f32(float %maybe.pnorm)
ret float %exp
@@ -372,7 +372,7 @@ define nofpclass(pzero) float @source_is_known_nzero(float nofpclass(nan inf nor
define nofpclass(nzero) float @source_is_known_inf(float nofpclass(nan norm sub zero) %must.be.inf) !prof !0 {
; CHECK-LABEL: define nofpclass(nzero) float @source_is_known_inf(
; CHECK-SAME: float nofpclass(nan zero sub norm) [[MUST_BE_INF:%.*]]) !prof [[PROF0:![0-9]+]] {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq float [[MUST_BE_INF]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq float [[MUST_BE_INF]], +inf
; CHECK-NEXT: [[EXP:%.*]] = select i1 [[TMP1]], float [[MUST_BE_INF]], float 0.000000e+00, !prof [[PROF1:![0-9]+]]
; CHECK-NEXT: ret float [[EXP]]
;
@@ -383,7 +383,7 @@ define nofpclass(nzero) float @source_is_known_inf(float nofpclass(nan norm sub
define nofpclass(nzero) <2 x float> @source_is_known_inf_vec(<2 x float> nofpclass(nan norm sub zero) %must.be.inf) {
; CHECK-LABEL: define nofpclass(nzero) <2 x float> @source_is_known_inf_vec(
; CHECK-SAME: <2 x float> nofpclass(nan zero sub norm) [[MUST_BE_INF:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq <2 x float> [[MUST_BE_INF]], splat (float 0x7FF0000000000000)
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq <2 x float> [[MUST_BE_INF]], splat (float +inf)
; CHECK-NEXT: [[EXP:%.*]] = select <2 x i1> [[TMP1]], <2 x float> [[MUST_BE_INF]], <2 x float> zeroinitializer
; CHECK-NEXT: ret <2 x float> [[EXP]]
;
@@ -394,7 +394,7 @@ define nofpclass(nzero) <2 x float> @source_is_known_inf_vec(<2 x float> nofpcla
define nofpclass(nzero) float @source_is_known_pinf(float nofpclass(ninf nan norm sub zero) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nzero) float @source_is_known_pinf(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%exp = call float @llvm.exp2.f32(float %must.be.pinf)
ret float %exp
@@ -430,7 +430,7 @@ define nofpclass(nzero) float @source_is_known_nan_preserve_flags(float nofpclas
define nofpclass(nzero) float @source_is_known_inf_or_nan(float nofpclass(norm sub zero) %must.be.inf.or.nan) {
; CHECK-LABEL: define nofpclass(nzero) float @source_is_known_inf_or_nan(
; CHECK-SAME: float nofpclass(zero sub norm) [[MUST_BE_INF_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq float [[MUST_BE_INF_OR_NAN]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq float [[MUST_BE_INF_OR_NAN]], +inf
; CHECK-NEXT: [[EXP:%.*]] = select i1 [[TMP1]], float [[MUST_BE_INF_OR_NAN]], float 0.000000e+00
; CHECK-NEXT: ret float [[EXP]]
;
@@ -441,7 +441,7 @@ define nofpclass(nzero) float @source_is_known_inf_or_nan(float nofpclass(norm s
define nofpclass(nzero) float @source_is_known_inf_or_nan_preserve_flags(float nofpclass(norm sub zero) %must.be.inf.or.nan) {
; CHECK-LABEL: define nofpclass(nzero) float @source_is_known_inf_or_nan_preserve_flags(
; CHECK-SAME: float nofpclass(zero sub norm) [[MUST_BE_INF_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nsz contract ueq float [[MUST_BE_INF_OR_NAN]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp nsz contract ueq float [[MUST_BE_INF_OR_NAN]], +inf
; CHECK-NEXT: [[TMP2:%.*]] = select nsz contract i1 [[TMP1]], float [[MUST_BE_INF_OR_NAN]], float 0.000000e+00
; CHECK-NEXT: ret float [[TMP2]]
;
@@ -452,7 +452,7 @@ define nofpclass(nzero) float @source_is_known_inf_or_nan_preserve_flags(float n
define nofpclass(nzero nan) float @source_is_known_inf_or_nan__nnan_result(float nofpclass(norm sub zero) %must.be.inf.or.nan) {
; CHECK-LABEL: define nofpclass(nan nzero) float @source_is_known_inf_or_nan__nnan_result(
; CHECK-SAME: float nofpclass(zero sub norm) [[MUST_BE_INF_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq float [[MUST_BE_INF_OR_NAN]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq float [[MUST_BE_INF_OR_NAN]], +inf
; CHECK-NEXT: [[EXP:%.*]] = select i1 [[TMP1]], float [[MUST_BE_INF_OR_NAN]], float 0.000000e+00
; CHECK-NEXT: ret float [[EXP]]
;
@@ -523,7 +523,7 @@ define nofpclass(nan inf nnorm sub zero) float @posnormal_result_demands_negnorm
define nofpclass(inf zero sub norm) float @ret_only_nan__exp2(float %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan__exp2(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%exp = call float @llvm.exp2.f32(float %x)
ret float %exp
@@ -541,7 +541,7 @@ define nofpclass(qnan inf zero sub norm) float @ret_only_snan__exp2(float %x) {
define nofpclass(snan inf zero sub norm) float @ret_only_qnan__exp2(float %x) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan__exp2(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%exp = call float @llvm.exp2.f32(float %x)
ret float %exp
@@ -550,7 +550,7 @@ define nofpclass(snan inf zero sub norm) float @ret_only_qnan__exp2(float %x) {
define nofpclass(inf zero sub norm) <2 x float> @ret_only_nan__exp2_vec(<2 x float> %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) <2 x float> @ret_only_nan__exp2_vec(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
-; CHECK-NEXT: ret <2 x float> splat (float 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x float> splat (float +qnan)
;
%exp = call <2 x float> @llvm.exp2.v2f32(<2 x float> %x)
ret <2 x float> %exp
@@ -559,7 +559,7 @@ define nofpclass(inf zero sub norm) <2 x float> @ret_only_nan__exp2_vec(<2 x flo
define nofpclass(inf zero sub norm) <2 x float> @ret_only_nan__exp2_vec_partially_defined(<2 x float> %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) <2 x float> @ret_only_nan__exp2_vec_partially_defined(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
-; CHECK-NEXT: ret <2 x float> splat (float 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x float> splat (float +qnan)
;
%exp = call <2 x float> @llvm.exp2.v2f32(<2 x float> <float 0x7ff8000000000000, float poison>)
ret <2 x float> %exp
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-extractelement.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-extractelement.ll
index e571774c72f2b..fbc24980c9b2f 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-extractelement.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-extractelement.ll
@@ -37,7 +37,7 @@ define nofpclass(qnan inf norm sub zero) half @ret_only_snan__extractelement_unk
define nofpclass(nan inf norm sub nzero) half @ret_only_pzero__extractelement_unknown(<4 x half> %vec, i32 %idx) {
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) half @ret_only_pzero__extractelement_unknown(
; CHECK-SAME: <4 x half> [[VEC:%.*]], i32 [[IDX:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%ext = extractelement <4 x half> %vec, i32 %idx
ret half %ext
@@ -46,7 +46,7 @@ define nofpclass(nan inf norm sub nzero) half @ret_only_pzero__extractelement_un
define nofpclass(nan inf norm sub pzero) half @ret_only_nzero__extractelement_unknown(<4 x half> %vec, i32 %idx) {
; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) half @ret_only_nzero__extractelement_unknown(
; CHECK-SAME: <4 x half> [[VEC:%.*]], i32 [[IDX:%.*]]) {
-; CHECK-NEXT: ret half 0xH8000
+; CHECK-NEXT: ret half -0.000000e+00
;
%ext = extractelement <4 x half> %vec, i32 %idx
ret half %ext
@@ -65,7 +65,7 @@ define nofpclass(nan inf norm sub) half @ret_only_zero__extractelement_unknown(<
define nofpclass(nan pinf norm sub zero) half @ret_only_ninf__extractelement_unknown(<4 x half> %vec, i32 %idx) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) half @ret_only_ninf__extractelement_unknown(
; CHECK-SAME: <4 x half> [[VEC:%.*]], i32 [[IDX:%.*]]) {
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%ext = extractelement <4 x half> %vec, i32 %idx
ret half %ext
@@ -74,7 +74,7 @@ define nofpclass(nan pinf norm sub zero) half @ret_only_ninf__extractelement_unk
define nofpclass(nan ninf norm sub zero) half @ret_only_pinf__extractelement_unknown(<4 x half> %vec, i32 %idx) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) half @ret_only_pinf__extractelement_unknown(
; CHECK-SAME: <4 x half> [[VEC:%.*]], i32 [[IDX:%.*]]) {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%ext = extractelement <4 x half> %vec, i32 %idx
ret half %ext
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll
index b7338f435531c..12bc61ef4ce39 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll
@@ -35,7 +35,7 @@ declare void @use(half)
define nofpclass(inf zero sub norm) half @ret_only_nan(half %x, half %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%add = fadd half %x, %y
ret half %add
@@ -44,7 +44,7 @@ define nofpclass(inf zero sub norm) half @ret_only_nan(half %x, half %y) {
define nofpclass(snan inf zero sub norm) half @ret_only_qnan(half %x, half %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) half @ret_only_qnan(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%add = fadd half %x, %y
ret half %add
@@ -73,7 +73,7 @@ define nofpclass(nan inf sub norm) half @ret_only_zero(half %x, half %y) {
define nofpclass(nan inf nzero sub norm) half @ret_only_pzero(half %x, half %y) {
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) half @ret_only_pzero(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%add = fadd half %x, %y
ret half %add
@@ -82,7 +82,7 @@ define nofpclass(nan inf nzero sub norm) half @ret_only_pzero(half %x, half %y)
define nofpclass(nan inf pzero sub norm) half @ret_only_nzero(half %x, half %y) {
; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) half @ret_only_nzero(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH8000
+; CHECK-NEXT: ret half -0.000000e+00
;
%add = fadd half %x, %y
ret half %add
@@ -101,7 +101,7 @@ define nofpclass(nan zero sub norm) half @ret_only_inf(half %x, half %y) {
define nofpclass(nan ninf zero sub norm) half @ret_only_pinf(half %x, half %y) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) half @ret_only_pinf(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%add = fadd half %x, %y
ret half %add
@@ -110,7 +110,7 @@ define nofpclass(nan ninf zero sub norm) half @ret_only_pinf(half %x, half %y) {
define nofpclass(nan pinf zero sub norm) half @ret_only_ninf(half %x, half %y) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) half @ret_only_ninf(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%add = fadd half %x, %y
ret half %add
@@ -119,7 +119,7 @@ define nofpclass(nan pinf zero sub norm) half @ret_only_ninf(half %x, half %y) {
define nofpclass(pinf) half @ret_nofpclass_pinf__fadd_select_unknown_or_pinf__unknown(i1 %cond, half %x, half %y) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fadd_select_unknown_or_pinf__unknown(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fadd half [[X_OR_PINF]], [[Y]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -131,7 +131,7 @@ define nofpclass(pinf) half @ret_nofpclass_pinf__fadd_select_unknown_or_pinf__un
define nofpclass(pinf) half @ret_nofpclass_pinf__fadd_unknown__select_unknown_or_pinf(i1 %cond, half %x, half %y) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fadd_unknown__select_unknown_or_pinf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fadd half [[X]], [[Y_OR_PINF]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -231,7 +231,7 @@ define nofpclass(inf sub norm) half @nan_result_demands_inf_input_lhs(i1 %cond,
; CHECK-LABEL: define nofpclass(inf sub norm) half @nan_result_demands_inf_input_lhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(nan inf zero) [[Y:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call half @returns_pinf()
-; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fadd half [[X_OR_INF]], [[Y]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -246,7 +246,7 @@ define nofpclass(inf sub norm) half @nan_result_demands_inf_input_rhs(i1 %cond,
; CHECK-LABEL: define nofpclass(inf sub norm) half @nan_result_demands_inf_input_rhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half [[Y:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call half @returns_pinf()
-; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fadd half [[X]], [[Y_OR_INF]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -291,7 +291,7 @@ define nofpclass(nan sub norm zero) half @inf_result_demands_pinf_input_lhs(i1 %
; CHECK-LABEL: define nofpclass(nan zero sub norm) half @inf_result_demands_pinf_input_lhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(zero) [[Y:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call half @returns_pinf()
-; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[X_OR_INF]], [[Y]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -306,7 +306,7 @@ define nofpclass(nan sub norm zero) half @inf_result_demands_pinf_input_rhs(i1 %
; CHECK-LABEL: define nofpclass(nan zero sub norm) half @inf_result_demands_pinf_input_rhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(zero) [[Y:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call half @returns_pinf()
-; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[X]], [[Y_OR_INF]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -321,7 +321,7 @@ define nofpclass(nan sub norm zero) half @inf_result_demands_ninf_input_lhs(i1 %
; CHECK-LABEL: define nofpclass(nan zero sub norm) half @inf_result_demands_ninf_input_lhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(zero) [[Y:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call half @returns_ninf()
-; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half 0xHFC00
+; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half -inf
; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[X_OR_INF]], [[Y]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -336,7 +336,7 @@ define nofpclass(nan sub norm zero) half @inf_result_demands_ninf_input_rhs(i1 %
; CHECK-LABEL: define nofpclass(nan zero sub norm) half @inf_result_demands_ninf_input_rhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(zero) [[Y:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call half @returns_ninf()
-; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half 0xHFC00
+; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half -inf
; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[X]], [[Y_OR_INF]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -681,7 +681,7 @@ define nofpclass(snan) half @unknown__fadd__pzero(half %unknown) {
; CHECK-LABEL: define nofpclass(snan) half @unknown__fadd__pzero(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fadd half [[UNKNOWN]], 0xH0000
+; CHECK-NEXT: [[ADD:%.*]] = fadd half [[UNKNOWN]], 0.000000e+00
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -693,7 +693,7 @@ define nofpclass(snan) half @pzero__fadd__unknown(half %unknown) {
; CHECK-LABEL: define nofpclass(snan) half @pzero__fadd__unknown(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fadd half [[UNKNOWN]], 0xH0000
+; CHECK-NEXT: [[ADD:%.*]] = fadd half [[UNKNOWN]], 0.000000e+00
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -705,7 +705,7 @@ define nofpclass(nan) half @ret_nonan__unknown__fadd__pzero(half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__unknown__fadd__pzero(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[UNKNOWN]], 0xH0000
+; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[UNKNOWN]], 0.000000e+00
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -717,7 +717,7 @@ define nofpclass(nan) half @ret_nonan__pzero__fadd__unknown(half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__pzero__fadd__unknown(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[UNKNOWN]], 0xH0000
+; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[UNKNOWN]], 0.000000e+00
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -1908,7 +1908,7 @@ define nofpclass(norm sub pzero) half @demand_nzero_select_nsub_source__fadd_sel
; CHECK-LABEL: define nofpclass(pzero sub norm) half @demand_nzero_select_nsub_source__fadd_self__ieee_dapz(
; CHECK-SAME: i1 [[COND:%.*]], half noundef [[UNKNOWN:%.*]]) #[[ATTR4]] {
; CHECK-NEXT: [[NSUB:%.*]] = call noundef half @returns_nsub()
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%nsub = call noundef half @returns_nsub()
%select = select i1 %cond, half %unknown, half %nsub
@@ -1973,7 +1973,7 @@ define nofpclass(norm sub pzero) half @demand_nzero_select_nsub_source__fadd_sel
; CHECK-LABEL: define nofpclass(pzero sub norm) half @demand_nzero_select_nsub_source__fadd_self__ftpz_ieee(
; CHECK-SAME: i1 [[COND:%.*]], half noundef [[UNKNOWN:%.*]]) #[[ATTR5]] {
; CHECK-NEXT: [[NSUB:%.*]] = call noundef half @returns_nsub()
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%nsub = call noundef half @returns_nsub()
%select = select i1 %cond, half %unknown, half %nsub
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
index bdde6b3a72dad..343e453b9f88a 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
@@ -17,8 +17,8 @@ declare void @use(half)
define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_unknown_or_pinf(i1 %cond, half %x, half %y) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_unknown_or_pinf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
-; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
+; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[TMP1:%.*]] = fdiv half [[X_OR_PINF]], [[Y_OR_PINF]]
; CHECK-NEXT: ret half [[TMP1]]
;
@@ -31,8 +31,8 @@ define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_unknown_or_pinf(i1 %cond,
define nofpclass(ninf) half @ret_nofpclass_pinf__fdiv_unknown_or_ninf(i1 %cond, half %x, half %y) {
; CHECK-LABEL: define nofpclass(ninf) half @ret_nofpclass_pinf__fdiv_unknown_or_ninf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_NINF:%.*]] = select i1 [[COND]], half [[X]], half 0xHFC00
-; CHECK-NEXT: [[Y_OR_NINF:%.*]] = select i1 [[COND]], half [[Y]], half 0xHFC00
+; CHECK-NEXT: [[X_OR_NINF:%.*]] = select i1 [[COND]], half [[X]], half -inf
+; CHECK-NEXT: [[Y_OR_NINF:%.*]] = select i1 [[COND]], half [[Y]], half -inf
; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[X_OR_NINF]], [[Y_OR_NINF]]
; CHECK-NEXT: ret half [[DIV]]
;
@@ -45,8 +45,8 @@ define nofpclass(ninf) half @ret_nofpclass_pinf__fdiv_unknown_or_ninf(i1 %cond,
define nofpclass(inf) half @ret_nofpclass_inf__fdiv_unknown_or_pinf(i1 %cond, half %x, half %y) {
; CHECK-LABEL: define nofpclass(inf) half @ret_nofpclass_inf__fdiv_unknown_or_pinf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
-; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
+; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[TMP1:%.*]] = fdiv half [[X_OR_PINF]], [[Y_OR_PINF]]
; CHECK-NEXT: ret half [[TMP1]]
;
@@ -60,7 +60,7 @@ define nofpclass(inf) half @ret_nofpclass_inf__fdiv_unknown_or_pinf(i1 %cond, ha
define nofpclass(pinf pnorm psub pzero) half @ret_only_negative_results_or_nan_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) half @ret_only_negative_results_or_nan_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -89,7 +89,7 @@ define nofpclass(pinf pnorm psub pzero nan) half @ret_only_negative_results_self
define nofpclass(inf norm sub) half @ret_only_zero_or_nan_results_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(inf sub norm) half @ret_only_zero_or_nan_results_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -107,7 +107,7 @@ define nofpclass(inf norm sub nan) half @ret_only_zero_results_self(half noundef
define nofpclass(inf norm sub zero) half @ret_only_nan_results_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan_results_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -116,7 +116,7 @@ define nofpclass(inf norm sub zero) half @ret_only_nan_results_self(half noundef
define nofpclass(inf norm sub zero snan) half @ret_only_qnan_results_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) half @ret_only_qnan_results_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -134,7 +134,7 @@ define nofpclass(inf norm sub zero qnan) half @ret_only_snan_results_self(half n
define nofpclass(norm sub zero) half @ret_only_inf_or_nan_results_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(zero sub norm) half @ret_only_inf_or_nan_results_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -152,7 +152,7 @@ define nofpclass(norm sub zero nan) half @ret_only_inf_results_self(half noundef
define nofpclass(ninf norm sub zero) half @ret_only_pinf_or_nan_results_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(ninf zero sub norm) half @ret_only_pinf_or_nan_results_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -180,7 +180,7 @@ define nofpclass(pinf norm sub zero nan) half @ret_only_ninf_results_self(half n
define nofpclass(inf) half @ret_src_must_be_zero_self(half noundef nofpclass(nan inf norm sub) %x) {
; CHECK-LABEL: define nofpclass(inf) half @ret_src_must_be_zero_self(
; CHECK-SAME: half noundef nofpclass(nan inf sub norm) [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -189,7 +189,7 @@ define nofpclass(inf) half @ret_src_must_be_zero_self(half noundef nofpclass(nan
define nofpclass(inf) half @ret_src_must_be_pzero(half noundef nofpclass(nan inf norm sub nzero) %x) {
; CHECK-LABEL: define nofpclass(inf) half @ret_src_must_be_pzero(
; CHECK-SAME: half noundef nofpclass(nan inf nzero sub norm) [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -198,7 +198,7 @@ define nofpclass(inf) half @ret_src_must_be_pzero(half noundef nofpclass(nan inf
define nofpclass(inf) half @ret_src_must_be_nzero(half noundef nofpclass(nan inf norm sub pzero) %x) {
; CHECK-LABEL: define nofpclass(inf) half @ret_src_must_be_nzero(
; CHECK-SAME: half noundef nofpclass(nan inf pzero sub norm) [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -207,7 +207,7 @@ define nofpclass(inf) half @ret_src_must_be_nzero(half noundef nofpclass(nan inf
define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self(half noundef nofpclass(inf norm sub) %x) {
; CHECK-LABEL: define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self(
; CHECK-SAME: half noundef nofpclass(inf sub norm) [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -216,7 +216,7 @@ define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self(half noundef nofpcl
define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self__preserve_flags(half noundef nofpclass(inf norm sub) %x) {
; CHECK-LABEL: define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self__preserve_flags(
; CHECK-SAME: half noundef nofpclass(inf sub norm) [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv contract half %x, %x
ret half %div
@@ -226,7 +226,7 @@ define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self_other_use_input0(ha
; CHECK-LABEL: define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self_other_use_input0(
; CHECK-SAME: half noundef nofpclass(inf sub norm) [[X:%.*]]) {
; CHECK-NEXT: call void @use(half [[X]])
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
call void @use(half %x)
%div = fdiv half %x, %x
@@ -237,7 +237,7 @@ define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self_other_use_input1(ha
; CHECK-LABEL: define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self_other_use_input1(
; CHECK-SAME: half noundef nofpclass(inf sub norm) [[X:%.*]]) {
; CHECK-NEXT: call void @use(half [[X]])
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
call void @use(half %x)
@@ -248,7 +248,7 @@ define nofpclass(snan) half @ret_src_nonan_self(half noundef nofpclass(nan) %x)
; CHECK-LABEL: define nofpclass(snan) half @ret_src_nonan_self(
; CHECK-SAME: half noundef nofpclass(nan) [[X:%.*]]) !prof [[PROF0:![0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 612)
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half 0xH7E00, half 0xH3C00, !prof [[PROF1:![0-9]+]]
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00, !prof [[PROF1:![0-9]+]]
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -258,7 +258,7 @@ define nofpclass(snan) half @ret_src_nonan_self(half noundef nofpclass(nan) %x)
define nofpclass(nan) half @ret_nonan_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
%div = fdiv half %x, %x
ret half %div
@@ -267,8 +267,8 @@ define nofpclass(nan) half @ret_nonan_self(half noundef %x) {
define nofpclass(snan) half @ret_src_noinf_self(half noundef nofpclass(inf) %x) {
; CHECK-LABEL: define nofpclass(snan) half @ret_src_noinf_self(
; CHECK-SAME: half noundef nofpclass(inf) [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq half [[X]], 0xH0000
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq half [[X]], 0.000000e+00
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -279,7 +279,7 @@ define nofpclass(inf) half @ret_noinf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(inf) half @ret_noinf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -289,8 +289,8 @@ define nofpclass(inf) half @ret_noinf_self(half noundef %x) {
define nofpclass(snan) half @ret_src_nonan_noinf_self(half noundef nofpclass(nan inf) %x) {
; CHECK-LABEL: define nofpclass(snan) half @ret_src_nonan_noinf_self(
; CHECK-SAME: half noundef nofpclass(nan inf) [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq half [[X]], 0xH0000
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq half [[X]], 0.000000e+00
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -301,8 +301,8 @@ define nofpclass(snan) half @ret_src_nozero_self(half noundef nofpclass(zero) %x
; CHECK-LABEL: define nofpclass(snan) half @ret_src_nozero_self(
; CHECK-SAME: half noundef nofpclass(zero) [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp ueq half [[TMP1]], 0xH7C00
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP2]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp ueq half [[TMP1]], +inf
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP2]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -312,11 +312,11 @@ define nofpclass(snan) half @ret_src_nozero_self(half noundef nofpclass(zero) %x
define nofpclass(snan) half @ret_src_nozero_self__daz(half noundef nofpclass(zero) %x) #2 {
; CHECK-LABEL: define nofpclass(snan) half @ret_src_nozero_self__daz(
; CHECK-SAME: half noundef nofpclass(zero) [[X:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq half [[X]], 0xH0000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq half [[X]], 0.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq half [[TMP2]], 0xH7C00
+; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq half [[TMP2]], +inf
; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP1]]
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP4]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP4]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -327,8 +327,8 @@ define nofpclass(snan) half @ret_src_nozero_nosub_self(half noundef nofpclass(su
; CHECK-LABEL: define nofpclass(snan) half @ret_src_nozero_nosub_self(
; CHECK-SAME: half noundef nofpclass(zero sub) [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp ueq half [[TMP1]], 0xH7C00
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP2]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp ueq half [[TMP1]], +inf
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP2]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -338,11 +338,11 @@ define nofpclass(snan) half @ret_src_nozero_nosub_self(half noundef nofpclass(su
define nofpclass(snan) half @ret_src_nozero_nosub_self__daz(half noundef nofpclass(sub zero) %x) #2 {
; CHECK-LABEL: define nofpclass(snan) half @ret_src_nozero_nosub_self__daz(
; CHECK-SAME: half noundef nofpclass(zero sub) [[X:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq half [[X]], 0xH0000
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq half [[X]], 0.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq half [[TMP2]], 0xH7C00
+; CHECK-NEXT: [[TMP3:%.*]] = fcmp ueq half [[TMP2]], +inf
; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP1]]
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP4]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP4]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -352,7 +352,7 @@ define nofpclass(snan) half @ret_src_nozero_nosub_self__daz(half noundef nofpcla
define nofpclass(snan) half @ret_fdiv_nnan_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(snan) half @ret_fdiv_nnan_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
%div = fdiv nnan half %x, %x
ret half %div
@@ -362,7 +362,7 @@ define nofpclass(snan) half @ret_fdiv_ninf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(snan) half @ret_fdiv_ninf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
-; CHECK-NEXT: [[DIV:%.*]] = select ninf i1 [[TMP1]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[DIV:%.*]] = select ninf i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv ninf half %x, %x
@@ -372,7 +372,7 @@ define nofpclass(snan) half @ret_fdiv_ninf_self(half noundef %x) {
define nofpclass(snan) half @ret_fdiv_nnan_ninf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(snan) half @ret_fdiv_nnan_ninf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
%div = fdiv nnan ninf half %x, %x
ret half %div
@@ -381,7 +381,7 @@ define nofpclass(snan) half @ret_fdiv_nnan_ninf_self(half noundef %x) {
define nofpclass(pnorm) half @ret_nopnorm_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(pnorm) half @ret_nopnorm_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -391,7 +391,7 @@ define nofpclass(ninf) half @ret_noninf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(ninf) half @ret_noninf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -402,7 +402,7 @@ define nofpclass(pinf) half @ret_nopinf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nopinf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -413,7 +413,7 @@ define nofpclass(zero) half @ret_nozero_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(zero) half @ret_nozero_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
-; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half 0xH7E00, half 0xH3C00
+; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, %x
@@ -437,7 +437,7 @@ define nofpclass(ninf norm sub zero) half @pinf_result_demands__self__pnorm_sour
define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf(i1 %cond, half %x) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[X_OR_PINF]], [[X_OR_PINF]]
; CHECK-NEXT: ret half [[DIV]]
;
@@ -449,7 +449,7 @@ define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf(i1 %c
define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf__other_use0(i1 %cond, half %x) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf__other_use0(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: call void @use(half [[X_OR_PINF]])
; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[X_OR_PINF]], [[X_OR_PINF]]
; CHECK-NEXT: ret half [[DIV]]
@@ -463,7 +463,7 @@ define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf__othe
define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf__other_use1(i1 %cond, half %x) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf__other_use1(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[X_OR_PINF]], [[X_OR_PINF]]
; CHECK-NEXT: call void @use(half [[X_OR_PINF]])
; CHECK-NEXT: ret half [[DIV]]
@@ -478,7 +478,7 @@ define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_self_unknown_or_pinf__othe
define nofpclass(nzero) half @ret_src_must_be_nan_self(half noundef nofpclass(inf norm sub zero) %x) {
; CHECK-LABEL: define nofpclass(nzero) half @ret_src_must_be_nan_self(
; CHECK-SAME: half noundef nofpclass(inf zero sub norm) [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %x
ret half %div
@@ -488,7 +488,7 @@ define nofpclass(nzero) half @ret_src_must_be_nan_self(half noundef nofpclass(in
define nofpclass(pinf pnorm psub pzero) half @ret_only_negative_results_or_nan_fabs_xy(half %x, half nofpclass(ninf nnorm nsub nzero) %y.pos.or.nan) {
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) half @ret_only_negative_results_or_nan_fabs_xy(
; CHECK-SAME: half [[X:%.*]], half nofpclass(ninf nzero nsub nnorm) [[Y_POS_OR_NAN:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%x.fabs = call half @llvm.fabs.f32(half %x)
%div = fdiv half %x.fabs, %y.pos.or.nan
@@ -509,7 +509,7 @@ define nofpclass(pinf pnorm psub pzero nan) half @ret_only_negative_results_fabs
define nofpclass(zero) half @ret_only_zero_results__rhs_non0_const(half %x) {
; CHECK-LABEL: define nofpclass(zero) half @ret_only_zero_results__rhs_non0_const(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fmul half [[X]], 0xH3800
+; CHECK-NEXT: [[DIV:%.*]] = fmul half [[X]], 5.000000e-01
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %x, 2.0
@@ -569,7 +569,7 @@ define nofpclass(zero) half @ret_only_zero_results__lhs_known_nonzero_daz(half n
define nofpclass(inf) half @ret_only_inf_results__lhs_known_non_inf(i1 %cond, half %x, half nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(inf) half @ret_only_inf_results__lhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[X_OR_PINF]], [[Y]]
; CHECK-NEXT: ret half [[DIV]]
;
@@ -581,7 +581,7 @@ define nofpclass(inf) half @ret_only_inf_results__lhs_known_non_inf(i1 %cond, ha
define nofpclass(inf) half @ret_no_inf_results__rhs_known_non_inf(i1 %cond, half %x, half nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(inf) half @ret_no_inf_results__rhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[X]], [[Y_OR_PINF]]
; CHECK-NEXT: ret half [[DIV]]
;
@@ -594,7 +594,7 @@ define nofpclass(inf) half @ret_no_inf_results__rhs_known_non_inf(i1 %cond, half
define nofpclass(ninf nan) half @ret_no_ninf_or_nan_results__lhs_known_non_inf(i1 %cond, half %x, half nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(nan ninf) half @ret_no_ninf_or_nan_results__lhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[X_OR_PINF]], [[Y]]
; CHECK-NEXT: ret half [[DIV]]
;
@@ -607,7 +607,7 @@ define nofpclass(ninf nan) half @ret_no_ninf_or_nan_results__lhs_known_non_inf(i
define nofpclass(pinf nan) half @ret_no_pinf_or_nan_results__lhs_known_non_inf(i1 %cond, half %x, half nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(nan pinf) half @ret_no_pinf_or_nan_results__lhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[X_OR_PINF]], [[Y]]
; CHECK-NEXT: ret half [[DIV]]
;
@@ -632,7 +632,7 @@ define nofpclass(inf nan) half @ret_no_inf_or_nan_results__lhs_known_non_inf(i1
define nofpclass(inf nan) half @ret_no_inf_or_nan_results__rhs_known_non_inf(i1 %cond, half %x, half nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(nan inf) half @ret_no_inf_or_nan_results__rhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[X]], [[Y_OR_PINF]]
; CHECK-NEXT: ret half [[DIV]]
;
@@ -645,7 +645,7 @@ define nofpclass(inf nan) half @ret_no_inf_or_nan_results__rhs_known_non_inf(i1
define nofpclass(ninf nnorm nsub nzero) half @ret_only_positive_results_or_nan_known_negative_fdiv(half nofpclass(ninf nnorm nsub nzero) %only.positive.or.nan, half nofpclass(pinf pnorm psub pzero) %only.negative.or.nan) {
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) half @ret_only_positive_results_or_nan_known_negative_fdiv(
; CHECK-SAME: half nofpclass(ninf nzero nsub nnorm) [[ONLY_POSITIVE_OR_NAN:%.*]], half nofpclass(pinf pzero psub pnorm) [[ONLY_NEGATIVE_OR_NAN:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %only.negative.or.nan, %only.positive.or.nan
ret half %div
@@ -819,7 +819,7 @@ define nofpclass(nsub) half @ret__known_negative_nonlogical0__fdiv__known_inf_or
define nofpclass(nan) half @ret_no_nan_result__known_pzero__fdiv__not_inf(half nofpclass(inf sub norm nzero) %pzero.or.nan, half nofpclass(inf nan) %not.inf.or.nan) {
; CHECK-LABEL: define nofpclass(nan) half @ret_no_nan_result__known_pzero__fdiv__not_inf(
; CHECK-SAME: half nofpclass(inf nzero sub norm) [[PZERO_OR_NAN:%.*]], half nofpclass(nan inf) [[NOT_INF_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[NOT_INF_OR_NAN]])
+; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[NOT_INF_OR_NAN]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %pzero.or.nan, %not.inf.or.nan
@@ -829,7 +829,7 @@ define nofpclass(nan) half @ret_no_nan_result__known_pzero__fdiv__not_inf(half n
define nofpclass(nan) half @ret_no_nan_result__known_pzero__fdiv__not_inf__insert_point(half nofpclass(inf sub norm nzero) %pzero.or.nan, half nofpclass(inf nan) %not.inf.or.nan) {
; CHECK-LABEL: define nofpclass(nan) half @ret_no_nan_result__known_pzero__fdiv__not_inf__insert_point(
; CHECK-SAME: half nofpclass(inf nzero sub norm) [[PZERO_OR_NAN:%.*]], half nofpclass(nan inf) [[NOT_INF_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[NOT_INF_OR_NAN]])
+; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[NOT_INF_OR_NAN]])
; CHECK-NEXT: [[BARRIER:%.*]] = call half @llvm.arithmetic.fence.f16(half [[DIV]])
; CHECK-NEXT: ret half [[BARRIER]]
;
@@ -842,7 +842,7 @@ define nofpclass(nan) half @ret_no_nan_result__known_pzero__fdiv__not_inf__inser
define nofpclass(nan) half @ret_no_nan_result__not_inf_or_nan__fdiv__known_pzero_or_nan(half nofpclass(inf) %not.inf.or.nan, half nofpclass(inf sub norm nzero) %pzero.or.nan) {
; CHECK-LABEL: define nofpclass(nan) half @ret_no_nan_result__not_inf_or_nan__fdiv__known_pzero_or_nan(
; CHECK-SAME: half nofpclass(inf) [[NOT_INF_OR_NAN:%.*]], half nofpclass(inf nzero sub norm) [[PZERO_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0xH7C00, half [[NOT_INF_OR_NAN]])
+; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half +inf, half [[NOT_INF_OR_NAN]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %not.inf.or.nan, %pzero.or.nan
@@ -852,7 +852,7 @@ define nofpclass(nan) half @ret_no_nan_result__not_inf_or_nan__fdiv__known_pzero
define nofpclass(nan) half @ret_no_nan_result__not_inf_or_nan__fdiv__known_pzero_or_nan__insert_pt(half nofpclass(inf) %not.inf.or.nan, half nofpclass(inf sub norm nzero) %pzero.or.nan) {
; CHECK-LABEL: define nofpclass(nan) half @ret_no_nan_result__not_inf_or_nan__fdiv__known_pzero_or_nan__insert_pt(
; CHECK-SAME: half nofpclass(inf) [[NOT_INF_OR_NAN:%.*]], half nofpclass(inf nzero sub norm) [[PZERO_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0xH7C00, half [[NOT_INF_OR_NAN]])
+; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half +inf, half [[NOT_INF_OR_NAN]])
; CHECK-NEXT: [[BARRIER:%.*]] = call half @llvm.arithmetic.fence.f16(half [[DIV]])
; CHECK-NEXT: ret half [[BARRIER]]
;
@@ -887,7 +887,7 @@ define nofpclass(nan) half @ret_no_nan_result__known_negative_non0__fdiv__known_
define nofpclass(inf nan) half @ret_noinf_nonan__known_pzero_or_nan__fdiv__not_inf_or_nan(half nofpclass(inf sub norm nzero) %pzero.or.nan, half %unknown) {
; CHECK-LABEL: define nofpclass(nan inf) half @ret_noinf_nonan__known_pzero_or_nan__fdiv__not_inf_or_nan(
; CHECK-SAME: half nofpclass(inf nzero sub norm) [[PZERO_OR_NAN:%.*]], half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[UNKNOWN]])
+; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[UNKNOWN]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %pzero.or.nan, %unknown
@@ -898,7 +898,7 @@ define nofpclass(inf nan) half @ret_noinf_nonan__known_pzero_or_nan__fdiv__not_i
define nofpclass(inf nan) half @ret_noinf_nonan__not_inf_or_nan__fdiv__known_pzero_or_nan(half nofpclass(inf sub norm nzero) %pzero.or.nan, half %unknown) {
; CHECK-LABEL: define nofpclass(nan inf) half @ret_noinf_nonan__not_inf_or_nan__fdiv__known_pzero_or_nan(
; CHECK-SAME: half nofpclass(inf nzero sub norm) [[PZERO_OR_NAN:%.*]], half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[UNKNOWN]])
+; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[UNKNOWN]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %pzero.or.nan, %unknown
@@ -1073,7 +1073,7 @@ define nofpclass(ninf) half @ret_noninf__not_nan_neg__fdiv__known_zero_or_pos_na
define nofpclass(inf norm sub zero) half @ret_only_nan_results_fdiv(half %x, half %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan_results_fdiv(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %y
ret half %div
@@ -1082,7 +1082,7 @@ define nofpclass(inf norm sub zero) half @ret_only_nan_results_fdiv(half %x, hal
define nofpclass(inf norm sub zero snan) half @ret_only_qnan_results_fdiv(half %x, half %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) half @ret_only_qnan_results_fdiv(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%div = fdiv half %x, %y
ret half %div
@@ -1111,7 +1111,7 @@ define nofpclass(nan inf) half @ret_no_nan_no_inf__fdiv_nonan_noinf__nonan_noinf
define nofpclass(nan inf) half @ret_no_nan_no_inf__fdiv_no_nan__normal_constant(half nofpclass(inf nan) %x) {
; CHECK-LABEL: define nofpclass(nan inf) half @ret_no_nan_no_inf__fdiv_no_nan__normal_constant(
; CHECK-SAME: half nofpclass(nan inf) [[X:%.*]]) {
-; CHECK-NEXT: [[FDIV:%.*]] = fmul nnan ninf half [[X]], 0xH3400
+; CHECK-NEXT: [[FDIV:%.*]] = fmul nnan ninf half [[X]], 2.500000e-01
; CHECK-NEXT: ret half [[FDIV]]
;
%fdiv = fdiv half %x, 4.0
@@ -1146,7 +1146,7 @@ define nofpclass(nan) half @ret_no_nan__fdiv_pzero__unknown(half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_no_nan__fdiv_pzero__unknown(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[FDIV:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[UNKNOWN]])
+; CHECK-NEXT: [[FDIV:%.*]] = call half @llvm.copysign.f16(half 0.000000e+00, half [[UNKNOWN]])
; CHECK-NEXT: ret half [[FDIV]]
;
%pzero = call half @returns_pzero()
@@ -1158,7 +1158,7 @@ define nofpclass(nan) half @ret_no_nan__fdiv_unknown__pzero(half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_no_nan__fdiv_unknown__pzero(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[FDIV:%.*]] = call half @llvm.copysign.f16(half 0xH7C00, half [[UNKNOWN]])
+; CHECK-NEXT: [[FDIV:%.*]] = call half @llvm.copysign.f16(half +inf, half [[UNKNOWN]])
; CHECK-NEXT: ret half [[FDIV]]
;
%pzero = call half @returns_pzero()
@@ -1170,7 +1170,7 @@ define nofpclass(nan) half @ret_no_nan__fdiv_nzero__unknown(half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_no_nan__fdiv_nzero__unknown(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NZERO:%.*]] = call half @returns_nzero()
-; CHECK-NEXT: [[FDIV:%.*]] = fdiv nnan half 0xH8000, [[UNKNOWN]]
+; CHECK-NEXT: [[FDIV:%.*]] = fdiv nnan half -0.000000e+00, [[UNKNOWN]]
; CHECK-NEXT: ret half [[FDIV]]
;
%nzero = call half @returns_nzero()
@@ -1182,7 +1182,7 @@ define nofpclass(nan) half @ret_no_nan__fdiv_unknown__nzero(half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_no_nan__fdiv_unknown__nzero(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NZERO:%.*]] = call half @returns_nzero()
-; CHECK-NEXT: [[FDIV:%.*]] = fdiv nnan half [[UNKNOWN]], 0xH8000
+; CHECK-NEXT: [[FDIV:%.*]] = fdiv nnan half [[UNKNOWN]], -0.000000e+00
; CHECK-NEXT: ret half [[FDIV]]
;
%nzero = call half @returns_nzero()
@@ -1206,7 +1206,7 @@ define nofpclass(ninf) half @ret_ninf__fdiv_nnan_unknown__zero(half %unknown) {
; CHECK-LABEL: define nofpclass(ninf) half @ret_ninf__fdiv_nnan_unknown__zero(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[ZERO:%.*]] = call half @returns_zero()
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%zero = call half @returns_zero()
%fdiv = fdiv nnan half %unknown, %zero
@@ -1305,7 +1305,7 @@ define nofpclass(inf) half @ret_noinf__not_inf_or_nan__fdiv__nzero_or_nan(half n
define nofpclass(nan) half @ret_nonan__nzero_or_nan__fdiv__not_inf_or_nan(half nofpclass(inf sub norm pzero) %nzero.or.nan, half nofpclass(nan) %not.nan) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__nzero_or_nan__fdiv__not_inf_or_nan(
; CHECK-SAME: half nofpclass(inf pzero sub norm) [[NZERO_OR_NAN:%.*]], half nofpclass(nan) [[NOT_NAN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half 0xH8000, [[NOT_NAN]]
+; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half -0.000000e+00, [[NOT_NAN]]
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %nzero.or.nan, %not.nan
@@ -1316,7 +1316,7 @@ define nofpclass(nan) half @ret_nonan__nzero_or_nan__fdiv__not_inf_or_nan(half n
define nofpclass(nan) half @ret_nonan__not_inf_or_nan__fdiv__nzero_or_nan(half nofpclass(nan) %not.nan, half nofpclass(inf sub norm pzero) %nzero.or.nan) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__not_inf_or_nan__fdiv__nzero_or_nan(
; CHECK-SAME: half nofpclass(nan) [[NOT_NAN:%.*]], half nofpclass(inf pzero sub norm) [[NZERO_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[NOT_NAN]], 0xH8000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[NOT_NAN]], -0.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %not.nan, %nzero.or.nan
@@ -1349,7 +1349,7 @@ define nofpclass(snan) half @ret_not_inf_or_nan__fdiv_ninf__nzero_or_nan(half no
define nofpclass(snan) half @ret__nzero_or_nan__fdiv_nnan__not_inf_or_nan(half nofpclass(inf sub norm pzero) %nzero.or.nan, half %unknown) {
; CHECK-LABEL: define nofpclass(snan) half @ret__nzero_or_nan__fdiv_nnan__not_inf_or_nan(
; CHECK-SAME: half nofpclass(inf pzero sub norm) [[NZERO_OR_NAN:%.*]], half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half 0xH8000, [[UNKNOWN]]
+; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half -0.000000e+00, [[UNKNOWN]]
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nnan half %nzero.or.nan, %unknown
@@ -1360,7 +1360,7 @@ define nofpclass(snan) half @ret__nzero_or_nan__fdiv_nnan__not_inf_or_nan(half n
define nofpclass(snan) half @not_inf_or_nan__fdiv_nnan__nzero_or_nan(half %unknown, half nofpclass(inf sub norm pzero) %nzero.or.nan) {
; CHECK-LABEL: define nofpclass(snan) half @not_inf_or_nan__fdiv_nnan__nzero_or_nan(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(inf pzero sub norm) [[NZERO_OR_NAN:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[UNKNOWN]], 0xH8000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[UNKNOWN]], -0.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nnan half %unknown, %nzero.or.nan
@@ -1970,7 +1970,7 @@ define nofpclass(nan) half @ret_nonan__known_zero_or_nan__fdiv__unknown(half nof
define nofpclass(nan) half @ret_nonan__zero_or_nan__fdiv_nsz__unknown(half nofpclass(inf sub norm) %zero.or.nan, half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__zero_or_nan__fdiv_nsz__unknown(
; CHECK-SAME: half nofpclass(inf sub norm) [[ZERO_OR_NAN:%.*]], half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%div = fdiv nsz contract half %zero.or.nan, %unknown
ret half %div
@@ -2061,7 +2061,7 @@ define nofpclass(snan) half @ret__unknown__fdiv_nsz__zero(half %unknown, half no
define nofpclass(snan) half @ret__unknown__fdiv__pzero(half %unknown, half nofpclass(inf nan sub norm nzero) %pzero) {
; CHECK-LABEL: define nofpclass(snan) half @ret__unknown__fdiv__pzero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf nzero sub norm) [[PZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[UNKNOWN]], 0xH0000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[UNKNOWN]], 0.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %unknown, %pzero
@@ -2071,7 +2071,7 @@ define nofpclass(snan) half @ret__unknown__fdiv__pzero(half %unknown, half nofpc
define nofpclass(snan) half @ret__unknown__fdiv_nsz__pzero(half %unknown, half nofpclass(nan inf sub norm nzero) %pzero) {
; CHECK-LABEL: define nofpclass(snan) half @ret__unknown__fdiv_nsz__pzero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf nzero sub norm) [[PZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv nsz contract half [[UNKNOWN]], 0xH0000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv nsz contract half [[UNKNOWN]], 0.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nsz contract half %unknown, %pzero
@@ -2081,7 +2081,7 @@ define nofpclass(snan) half @ret__unknown__fdiv_nsz__pzero(half %unknown, half n
define nofpclass(snan) half @ret__unknown__fdiv__nzero(half %unknown, half nofpclass(nan inf sub norm pzero) %nzero) {
; CHECK-LABEL: define nofpclass(snan) half @ret__unknown__fdiv__nzero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf pzero sub norm) [[NZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[UNKNOWN]], 0xH8000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv half [[UNKNOWN]], -0.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %unknown, %nzero
@@ -2091,7 +2091,7 @@ define nofpclass(snan) half @ret__unknown__fdiv__nzero(half %unknown, half nofpc
define nofpclass(snan) half @ret__unknown__fdiv_nsz__nzero(half %unknown, half nofpclass(nan inf sub norm pzero) %nzero) {
; CHECK-LABEL: define nofpclass(snan) half @ret__unknown__fdiv_nsz__nzero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf pzero sub norm) [[NZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv nsz contract half [[UNKNOWN]], 0xH8000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv nsz contract half [[UNKNOWN]], -0.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nsz contract half %unknown, %nzero
@@ -2111,7 +2111,7 @@ define nofpclass(nan) half @ret_nonan__unknown__fdiv__zero(half %unknown, half n
define nofpclass(nan) half @ret_nonan__unknown__fdiv_nsz__zero(half %unknown, half nofpclass(nan inf sub norm) %zero) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__unknown__fdiv_nsz__zero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf sub norm) [[ZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half 0xH7C00, half [[UNKNOWN]])
+; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half +inf, half [[UNKNOWN]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nsz contract half %unknown, %zero
@@ -2121,7 +2121,7 @@ define nofpclass(nan) half @ret_nonan__unknown__fdiv_nsz__zero(half %unknown, ha
define nofpclass(nan) half @ret_nonan__unknown__fdiv__pzero(half %unknown, half nofpclass(inf nan sub norm nzero) %pzero) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__unknown__fdiv__pzero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf nzero sub norm) [[PZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half 0xH7C00, half [[UNKNOWN]])
+; CHECK-NEXT: [[DIV:%.*]] = call half @llvm.copysign.f16(half +inf, half [[UNKNOWN]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %unknown, %pzero
@@ -2131,7 +2131,7 @@ define nofpclass(nan) half @ret_nonan__unknown__fdiv__pzero(half %unknown, half
define nofpclass(nan) half @ret_nonan__unknown__fdiv_nsz__pzero(half %unknown, half nofpclass(nan inf sub norm nzero) %pzero) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__unknown__fdiv_nsz__pzero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf nzero sub norm) [[PZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half 0xH7C00, half [[UNKNOWN]])
+; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half +inf, half [[UNKNOWN]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nsz contract half %unknown, %pzero
@@ -2141,7 +2141,7 @@ define nofpclass(nan) half @ret_nonan__unknown__fdiv_nsz__pzero(half %unknown, h
define nofpclass(nan) half @ret_nonan__unknown__fdiv__nzero(half %unknown, half nofpclass(nan inf sub norm pzero) %nzero) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__unknown__fdiv__nzero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf pzero sub norm) [[NZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[UNKNOWN]], 0xH8000
+; CHECK-NEXT: [[DIV:%.*]] = fdiv nnan half [[UNKNOWN]], -0.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv half %unknown, %nzero
@@ -2151,7 +2151,7 @@ define nofpclass(nan) half @ret_nonan__unknown__fdiv__nzero(half %unknown, half
define nofpclass(nan) half @ret_nonan__unknown__fdiv_nsz__nzero(half %unknown, half nofpclass(nan inf sub norm pzero) %nzero) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__unknown__fdiv_nsz__nzero(
; CHECK-SAME: half [[UNKNOWN:%.*]], half nofpclass(nan inf pzero sub norm) [[NZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half 0xH7C00, half [[UNKNOWN]])
+; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half +inf, half [[UNKNOWN]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nsz contract half %unknown, %nzero
@@ -2171,7 +2171,7 @@ define nofpclass(snan) half @ret__not_nan__fdiv_nsz__zero(half nofpclass(nan) %n
define nofpclass(snan) half @ret__not_nan_not_zero__fdiv_nsz__zero(half nofpclass(nan zero) %not.nan.or.zero, half nofpclass(nan inf sub norm) %zero) {
; CHECK-LABEL: define nofpclass(snan) half @ret__not_nan_not_zero__fdiv_nsz__zero(
; CHECK-SAME: half nofpclass(nan zero) [[NOT_NAN_OR_ZERO:%.*]], half nofpclass(nan inf sub norm) [[ZERO:%.*]]) {
-; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half 0xH7C00, half [[NOT_NAN_OR_ZERO]])
+; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half +inf, half [[NOT_NAN_OR_ZERO]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nsz contract half %not.nan.or.zero, %zero
@@ -2201,7 +2201,7 @@ define nofpclass(snan) half @ret__not_nan_not_zero__fdiv_nsz__zero__dynamic(half
define nofpclass(snan) half @ret__not_nan_not_zero_not_sub__fdiv_nsz__zero__daz(half nofpclass(nan zero sub) %not.nan.or.zero.or.sub, half nofpclass(nan inf sub norm) %zero) #2 {
; CHECK-LABEL: define nofpclass(snan) half @ret__not_nan_not_zero_not_sub__fdiv_nsz__zero__daz(
; CHECK-SAME: half nofpclass(nan zero sub) [[NOT_NAN_OR_ZERO_OR_SUB:%.*]], half nofpclass(nan inf sub norm) [[ZERO:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half 0xH7C00, half [[NOT_NAN_OR_ZERO_OR_SUB]])
+; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half +inf, half [[NOT_NAN_OR_ZERO_OR_SUB]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nsz contract half %not.nan.or.zero.or.sub, %zero
@@ -2211,7 +2211,7 @@ define nofpclass(snan) half @ret__not_nan_not_zero_not_sub__fdiv_nsz__zero__daz(
define nofpclass(snan) half @ret__not_nan_not_zero_not_sub__fdiv_nsz__zero__dynamic(half nofpclass(nan zero sub) %not.nan.or.zero.or.sub, half nofpclass(nan inf sub norm) %zero) #3 {
; CHECK-LABEL: define nofpclass(snan) half @ret__not_nan_not_zero_not_sub__fdiv_nsz__zero__dynamic(
; CHECK-SAME: half nofpclass(nan zero sub) [[NOT_NAN_OR_ZERO_OR_SUB:%.*]], half nofpclass(nan inf sub norm) [[ZERO:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half 0xH7C00, half [[NOT_NAN_OR_ZERO_OR_SUB]])
+; CHECK-NEXT: [[DIV:%.*]] = call nsz contract half @llvm.copysign.f16(half +inf, half [[NOT_NAN_OR_ZERO_OR_SUB]])
; CHECK-NEXT: ret half [[DIV]]
;
%div = fdiv nsz contract half %not.nan.or.zero.or.sub, %zero
@@ -2263,7 +2263,7 @@ define nofpclass(nan inf norm sub) half @zero_result_demands_subnorm_lhs__daz(i1
define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_lhs__ieee(i1 %cond, half nofpclass(nan inf zero norm) %only.sub, half %unknown0, half %unknown1) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @nan_result_demands_subnorm_lhs__ieee(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(nan inf zero norm) [[ONLY_SUB:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%select = select i1 %cond, half %unknown0, half %only.sub
%div = fdiv half %select, %unknown1
@@ -2273,7 +2273,7 @@ define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_lhs__ieee(i
define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_rhs__ieee(i1 %cond, half nofpclass(nan inf zero norm) %only.sub, half %unknown0, half %unknown1) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @nan_result_demands_subnorm_rhs__ieee(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(nan inf zero norm) [[ONLY_SUB:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%select = select i1 %cond, half %unknown0, half %only.sub
%div = fdiv half %unknown1, %select
@@ -2283,7 +2283,7 @@ define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_rhs__ieee(i
define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_lhs__daz(i1 %cond, half nofpclass(nan inf zero norm) %only.sub, half %unknown0, half %unknown1) #2 {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @nan_result_demands_subnorm_lhs__daz(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(nan inf zero norm) [[ONLY_SUB:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%select = select i1 %cond, half %unknown0, half %only.sub
%div = fdiv half %select, %unknown1
@@ -2293,7 +2293,7 @@ define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_lhs__daz(i1
define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_rhs__daz(i1 %cond, half nofpclass(nan inf zero norm) %only.sub, half %unknown0, half %unknown1) #2 {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @nan_result_demands_subnorm_rhs__daz(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(nan inf zero norm) [[ONLY_SUB:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%select = select i1 %cond, half %unknown0, half %only.sub
%div = fdiv half %unknown1, %select
@@ -2303,7 +2303,7 @@ define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_rhs__daz(i1
define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_lhs__dynamic(i1 %cond, half nofpclass(nan inf zero norm) %only.sub, half %unknown0, half %unknown1) #3 {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @nan_result_demands_subnorm_lhs__dynamic(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(nan inf zero norm) [[ONLY_SUB:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%select = select i1 %cond, half %unknown0, half %only.sub
%div = fdiv half %select, %unknown1
@@ -2313,7 +2313,7 @@ define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_lhs__dynami
define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_rhs__dynamic(i1 %cond, half nofpclass(nan inf zero norm) %only.sub, half %unknown0, half %unknown1) #3 {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @nan_result_demands_subnorm_rhs__dynamic(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(nan inf zero norm) [[ONLY_SUB:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) #[[ATTR3]] {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%select = select i1 %cond, half %unknown0, half %only.sub
%div = fdiv half %unknown1, %select
@@ -2355,7 +2355,7 @@ define float @fdiv_replacement_insert_point_regression(i1 %cmp, float %x, float
; CHECK-SAME: i1 [[CMP:%.*]], float [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[Y]], i32 615)
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], float 0x7FF8000000000000, float 1.000000e+00
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], float +qnan, float 1.000000e+00
; CHECK-NEXT: [[SCALE_0:%.*]] = select i1 [[CMP]], float [[TMP1]], float [[Y]]
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[SCALE_0]], [[X]]
; CHECK-NEXT: ret float [[MUL]]
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
index 6f914c98c16ec..86984e797f575 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
@@ -7,7 +7,7 @@ declare nofpclass(qnan inf norm sub zero) half @returns_snan()
define nofpclass(inf norm sub zero) half @ret_only_nan(half %x, half %y, half %z) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]], half [[Z:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%result = call half @llvm.fma.f16(half %x, half %y, half %z)
ret half %result
@@ -16,7 +16,7 @@ define nofpclass(inf norm sub zero) half @ret_only_nan(half %x, half %y, half %z
define nofpclass(inf norm sub zero) <2 x half> @ret_only_nan_vec(<2 x half> %x, <2 x half> %y, <2 x half> %z) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) <2 x half> @ret_only_nan_vec(
; CHECK-SAME: <2 x half> [[X:%.*]], <2 x half> [[Y:%.*]], <2 x half> [[Z:%.*]]) {
-; CHECK-NEXT: ret <2 x half> splat (half 0xH7E00)
+; CHECK-NEXT: ret <2 x half> splat (half +qnan)
;
%result = call <2 x half> @llvm.fma.v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z)
ret <2 x half> %result
@@ -35,7 +35,7 @@ define nofpclass(inf norm sub zero qnan) half @ret_only_snan(half %x, half %y, h
define nofpclass(inf norm sub zero snan) half @ret_only_qnan(half %x, half %y, half %z) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) half @ret_only_qnan(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]], half [[Z:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%result = call half @llvm.fma.f16(half %x, half %y, half %z)
ret half %result
@@ -54,7 +54,7 @@ define nofpclass(nan norm sub zero) half @ret_only_inf(half %x, half %y, half %z
define nofpclass(nan pinf norm sub zero) half @ret_only_ninf(half %x, half %y, half %z) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) half @ret_only_ninf(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]], half [[Z:%.*]]) {
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%result = call half @llvm.fma.f16(half %x, half %y, half %z)
ret half %result
@@ -63,7 +63,7 @@ define nofpclass(nan pinf norm sub zero) half @ret_only_ninf(half %x, half %y, h
define nofpclass(nan ninf norm sub zero) half @ret_only_pinf(half %x, half %y, half %z) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) half @ret_only_pinf(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]], half [[Z:%.*]]) {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%result = call half @llvm.fma.f16(half %x, half %y, half %z)
ret half %result
@@ -82,7 +82,7 @@ define nofpclass(inf nan norm sub) half @ret_only_zero(half %x, half %y, half %z
define nofpclass(inf nan norm sub nzero) half @ret_only_pzero(half %x, half %y, half %z) {
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) half @ret_only_pzero(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]], half [[Z:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%result = call half @llvm.fma.f16(half %x, half %y, half %z)
ret half %result
@@ -91,7 +91,7 @@ define nofpclass(inf nan norm sub nzero) half @ret_only_pzero(half %x, half %y,
define nofpclass(inf nan norm sub pzero) half @ret_only_nzero(half %x, half %y, half %z) {
; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) half @ret_only_nzero(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]], half [[Z:%.*]]) {
-; CHECK-NEXT: ret half 0xH8000
+; CHECK-NEXT: ret half -0.000000e+00
;
%result = call half @llvm.fma.f16(half %x, half %y, half %z)
ret half %result
@@ -130,7 +130,7 @@ define nofpclass(nan inf) half @ret_no_nans_no_infs(half %x, half %y, half %z) {
define nofpclass(inf norm sub zero) half @ret_only_nan__square(half noundef %x, half %z) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan__square(
; CHECK-SAME: half noundef [[X:%.*]], half [[Z:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%result = call half @llvm.fma.f16(half %x, half %x, half %z)
ret half %result
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
index 57ca1a9db2ddf..c24bfbecc3456 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
@@ -30,7 +30,7 @@ define nofpclass(ninf) float @ret_nofpclass_pinf__fmul_unknown_or_ninf(i1 %cond,
; CHECK-LABEL: define nofpclass(ninf) float @ret_nofpclass_pinf__fmul_unknown_or_ninf(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = fmul float [[X]], [[Y]]
-; CHECK-NEXT: [[MUL:%.*]] = select i1 [[COND]], float [[TMP1]], float 0x7FF0000000000000
+; CHECK-NEXT: [[MUL:%.*]] = select i1 [[COND]], float [[TMP1]], float +inf
; CHECK-NEXT: ret float [[MUL]]
;
%x.or.ninf = select i1 %cond, float %x, float 0xFFF0000000000000
@@ -55,7 +55,7 @@ define nofpclass(inf) float @ret_nofpclass_inf__fmul_unknown_or_pinf(i1 %cond, f
define nofpclass(pinf pnorm psub pzero) float @ret_only_negative_results_or_nan_square(float noundef %x) {
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_only_negative_results_or_nan_square(
; CHECK-SAME: float noundef [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%mul = fmul float %x, %x
ret float %mul
@@ -104,7 +104,7 @@ define nofpclass(inf norm sub nan) float @ret_only_zero_results_square(float nou
define nofpclass(inf norm sub zero) float @ret_only_nan_results_square(float noundef %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan_results_square(
; CHECK-SAME: float noundef [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%mul = fmul float %x, %x
ret float %mul
@@ -113,7 +113,7 @@ define nofpclass(inf norm sub zero) float @ret_only_nan_results_square(float nou
define nofpclass(inf norm sub zero snan) float @ret_only_qnan_results_square(float noundef %x) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan_results_square(
; CHECK-SAME: float noundef [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%mul = fmul float %x, %x
ret float %mul
@@ -142,7 +142,7 @@ define nofpclass(norm sub zero) float @ret_only_inf_or_nan_results_square(float
define nofpclass(norm sub zero nan) float @ret_only_inf_results_square(float noundef %x) {
; CHECK-LABEL: define nofpclass(nan zero sub norm) float @ret_only_inf_results_square(
; CHECK-SAME: float noundef [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%mul = fmul float %x, %x
ret float %mul
@@ -161,7 +161,7 @@ define nofpclass(ninf norm sub zero) float @ret_only_pinf_or_nan_results_square(
define nofpclass(ninf norm sub zero nan) float @ret_only_pinf_results_square(float noundef %x) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf_results_square(
; CHECK-SAME: float noundef [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%mul = fmul float %x, %x
ret float %mul
@@ -265,7 +265,7 @@ define nofpclass(ninf norm sub zero) float @pinf_result_demands__square__pnorm_s
define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X_OR_PINF]], [[X_OR_PINF]]
; CHECK-NEXT: ret float [[MUL]]
;
@@ -277,7 +277,7 @@ define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf(i1
define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf__other_use0(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf__other_use0(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: call void @use(float [[X_OR_PINF]])
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X_OR_PINF]], [[X_OR_PINF]]
; CHECK-NEXT: ret float [[MUL]]
@@ -291,7 +291,7 @@ define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf__o
define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf__other_use1(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf__other_use1(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X_OR_PINF]], [[X_OR_PINF]]
; CHECK-NEXT: call void @use(float [[X_OR_PINF]])
; CHECK-NEXT: ret float [[MUL]]
@@ -306,7 +306,7 @@ define nofpclass(pinf) float @ret_nofpclass_pinf__fmul_square_unknown_or_pinf__o
define nofpclass(nzero) float @ret_src_must_be_nan_square(float noundef nofpclass(inf norm sub zero) %x) {
; CHECK-LABEL: define nofpclass(nzero) float @ret_src_must_be_nan_square(
; CHECK-SAME: float noundef nofpclass(inf zero sub norm) [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%mul = fmul float %x, %x
ret float %mul
@@ -316,7 +316,7 @@ define nofpclass(nzero) float @ret_src_must_be_nan_square(float noundef nofpclas
define nofpclass(pinf pnorm psub pzero) float @ret_only_negative_results_or_nan_fabs_xy(float %x, float nofpclass(ninf nnorm nsub nzero) %y.pos.or.nan) {
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_only_negative_results_or_nan_fabs_xy(
; CHECK-SAME: float [[X:%.*]], float nofpclass(ninf nzero nsub nnorm) [[Y_POS_OR_NAN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%x.fabs = call float @llvm.fabs.f32(float %x)
%mul = fmul float %x.fabs, %y.pos.or.nan
@@ -397,7 +397,7 @@ define nofpclass(zero) float @ret_only_zero_results__lhs_known_nonzero_daz(float
define nofpclass(inf) float @ret_only_inf_results__lhs_known_non_inf(i1 %cond, float %x, float nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(inf) float @ret_only_inf_results__lhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]], float nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X_OR_PINF]], [[Y]]
; CHECK-NEXT: ret float [[MUL]]
;
@@ -409,7 +409,7 @@ define nofpclass(inf) float @ret_only_inf_results__lhs_known_non_inf(i1 %cond, f
define nofpclass(inf) float @ret_no_inf_results__rhs_known_non_inf(i1 %cond, float %x, float nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(inf) float @ret_no_inf_results__rhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]], float nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], float [[Y]], float 0x7FF0000000000000
+; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], float [[Y]], float +inf
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[X]], [[Y_OR_PINF]]
; CHECK-NEXT: ret float [[MUL]]
;
@@ -422,7 +422,7 @@ define nofpclass(inf) float @ret_no_inf_results__rhs_known_non_inf(i1 %cond, flo
define nofpclass(ninf nan) float @ret_no_ninf_or_nan_results__lhs_known_non_inf(i1 %cond, float %x, float nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(nan ninf) float @ret_no_ninf_or_nan_results__lhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]], float nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[MUL:%.*]] = fmul nnan float [[X_OR_PINF]], [[Y]]
; CHECK-NEXT: ret float [[MUL]]
;
@@ -435,7 +435,7 @@ define nofpclass(ninf nan) float @ret_no_ninf_or_nan_results__lhs_known_non_inf(
define nofpclass(pinf nan) float @ret_no_pinf_or_nan_results__lhs_known_non_inf(i1 %cond, float %x, float nofpclass(inf) %y) {
; CHECK-LABEL: define nofpclass(nan pinf) float @ret_no_pinf_or_nan_results__lhs_known_non_inf(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]], float nofpclass(inf) [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[MUL:%.*]] = fmul nnan float [[X_OR_PINF]], [[Y]]
; CHECK-NEXT: ret float [[MUL]]
;
@@ -472,7 +472,7 @@ define nofpclass(inf nan) float @ret_no_inf_or_nan_results__rhs_known_non_inf(i1
define nofpclass(ninf nnorm nsub nzero) float @ret_only_positive_results_or_nan_known_negative_fmul(float nofpclass(ninf nnorm nsub nzero) %only.positive.or.nan, float nofpclass(pinf pnorm psub pzero) %only.negative.or.nan) {
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_only_positive_results_or_nan_known_negative_fmul(
; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[ONLY_POSITIVE_OR_NAN:%.*]], float nofpclass(pinf pzero psub pnorm) [[ONLY_NEGATIVE_OR_NAN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%mul = fmul float %only.negative.or.nan, %only.positive.or.nan
ret float %mul
@@ -924,7 +924,7 @@ define nofpclass(ninf) float @ret_noninf__not_nan_neg__fmul__known_zero_or_pos_n
define nofpclass(inf norm sub zero) float @ret_only_nan_results_fmul(float %x, float %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan_results_fmul(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%mul = fmul float %x, %y
ret float %mul
@@ -933,7 +933,7 @@ define nofpclass(inf norm sub zero) float @ret_only_nan_results_fmul(float %x, f
define nofpclass(inf norm sub zero snan) float @ret_only_qnan_results_fmul(float %x, float %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan_results_fmul(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%mul = fmul float %x, %y
ret float %mul
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll
index 7ff6e6f179673..43226d280a5a1 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll
@@ -37,7 +37,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan__fpext(half %x) {
define nofpclass(inf norm sub zero snan) float @ret_only_qnan__fpext(half %x) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan__fpext(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = fpext half %x to float
ret float %result
@@ -46,7 +46,7 @@ define nofpclass(inf norm sub zero snan) float @ret_only_qnan__fpext(half %x) {
define nofpclass(inf norm sub zero) float @ret_only_nan__fpext(half %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan__fpext(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = fpext half %x to float
ret float %result
@@ -65,7 +65,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf__fpext(half %x) {
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf__fpext(half %x) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf__fpext(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = fpext half %x to float
ret float %result
@@ -74,7 +74,7 @@ define nofpclass(nan pinf norm sub zero) float @ret_only_ninf__fpext(half %x) {
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf__fpext(half %x) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf__fpext(
; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = fpext half %x to float
ret float %result
@@ -415,7 +415,7 @@ define nofpclass(inf nan norm pzero psub) float @ret_only_nsub_nzero__fpext(half
define nofpclass(ninf) float @ret_no_ninf__fpext__inf() {
; CHECK-LABEL: define nofpclass(ninf) float @ret_no_ninf__fpext__inf() {
; CHECK-NEXT: [[INF:%.*]] = call half @returns_inf_f16()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%inf = call half @returns_inf_f16()
%result = fpext half %inf to float
@@ -426,7 +426,7 @@ define nofpclass(ninf) float @ret_no_ninf__fpext__inf() {
define nofpclass(pinf) float @ret_no_pinf__fpext__inf() {
; CHECK-LABEL: define nofpclass(pinf) float @ret_no_pinf__fpext__inf() {
; CHECK-NEXT: [[INF:%.*]] = call half @returns_inf_f16()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%inf = call half @returns_inf_f16()
%result = fpext half %inf to float
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll
index d4f84348530e6..4c2c9b4c21892 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll
@@ -41,7 +41,7 @@ define nofpclass(inf norm sub zero qnan) half @ret_only_snan__fptrunc(float %x)
define nofpclass(inf norm sub zero snan) half @ret_only_qnan__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) half @ret_only_qnan__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%result = call half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.downward")
ret half %result
@@ -50,7 +50,7 @@ define nofpclass(inf norm sub zero snan) half @ret_only_qnan__fptrunc(float %x)
define nofpclass(inf norm sub zero) half @ret_only_nan__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%result = call half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.downward")
ret half %result
@@ -69,7 +69,7 @@ define nofpclass(nan norm sub zero) half @ret_only_inf__fptrunc(float %x) {
define nofpclass(nan pinf norm sub zero) half @ret_only_ninf__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) half @ret_only_ninf__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%result = call half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.downward")
ret half %result
@@ -78,7 +78,7 @@ define nofpclass(nan pinf norm sub zero) half @ret_only_ninf__fptrunc(float %x)
define nofpclass(nan ninf norm sub zero) half @ret_only_pinf__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) half @ret_only_pinf__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%result = call half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.downward")
ret half %result
@@ -97,7 +97,7 @@ define nofpclass(inf nan norm sub) half @ret_only_zero__fptrunc(float %x) {
define nofpclass(inf nan norm sub nzero) half @ret_only_pzero__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) half @ret_only_pzero__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%result = call half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.downward")
ret half %result
@@ -106,7 +106,7 @@ define nofpclass(inf nan norm sub nzero) half @ret_only_pzero__fptrunc(float %x)
define nofpclass(inf nan norm sub pzero) half @ret_only_nzero__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) half @ret_only_nzero__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH8000
+; CHECK-NEXT: ret half -0.000000e+00
;
%result = call half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.downward")
ret half %result
@@ -418,7 +418,7 @@ define nofpclass(inf nan norm pzero psub) half @ret_only_nsub_nzero__fptrunc(flo
define nofpclass(ninf) half @ret_no_ninf__fptrunc__inf() {
; CHECK-LABEL: define nofpclass(ninf) half @ret_no_ninf__fptrunc__inf() {
; CHECK-NEXT: [[INF:%.*]] = call float @returns_inf_f32()
-; CHECK-NEXT: [[RESULT:%.*]] = call nnan half @llvm.fptrunc.round.f16.f32(float 0x7FF0000000000000, metadata !"round.downward")
+; CHECK-NEXT: [[RESULT:%.*]] = call nnan half @llvm.fptrunc.round.f16.f32(float +inf, metadata !"round.downward")
; CHECK-NEXT: ret half [[RESULT]]
;
%inf = call float @returns_inf_f32()
@@ -430,7 +430,7 @@ define nofpclass(ninf) half @ret_no_ninf__fptrunc__inf() {
define nofpclass(pinf) half @ret_no_pinf__fptrunc__inf() {
; CHECK-LABEL: define nofpclass(pinf) half @ret_no_pinf__fptrunc__inf() {
; CHECK-NEXT: [[INF:%.*]] = call float @returns_inf_f32()
-; CHECK-NEXT: [[RESULT:%.*]] = call nnan half @llvm.fptrunc.round.f16.f32(float 0xFFF0000000000000, metadata !"round.downward")
+; CHECK-NEXT: [[RESULT:%.*]] = call nnan half @llvm.fptrunc.round.f16.f32(float -inf, metadata !"round.downward")
; CHECK-NEXT: ret half [[RESULT]]
;
%inf = call float @returns_inf_f32()
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll
index a291b3b06d6ed..f5e814bdf8e2f 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll
@@ -41,7 +41,7 @@ define nofpclass(inf norm sub zero qnan) half @ret_only_snan__fptrunc(float %x)
define nofpclass(inf norm sub zero snan) half @ret_only_qnan__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) half @ret_only_qnan__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%result = fptrunc float %x to half
ret half %result
@@ -50,7 +50,7 @@ define nofpclass(inf norm sub zero snan) half @ret_only_qnan__fptrunc(float %x)
define nofpclass(inf norm sub zero) half @ret_only_nan__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%result = fptrunc float %x to half
ret half %result
@@ -69,7 +69,7 @@ define nofpclass(nan norm sub zero) half @ret_only_inf__fptrunc(float %x) {
define nofpclass(nan pinf norm sub zero) half @ret_only_ninf__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) half @ret_only_ninf__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%result = fptrunc float %x to half
ret half %result
@@ -78,7 +78,7 @@ define nofpclass(nan pinf norm sub zero) half @ret_only_ninf__fptrunc(float %x)
define nofpclass(nan ninf norm sub zero) half @ret_only_pinf__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) half @ret_only_pinf__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%result = fptrunc float %x to half
ret half %result
@@ -97,7 +97,7 @@ define nofpclass(inf nan norm sub) half @ret_only_zero__fptrunc(float %x) {
define nofpclass(inf nan norm sub nzero) half @ret_only_pzero__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) half @ret_only_pzero__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%result = fptrunc float %x to half
ret half %result
@@ -106,7 +106,7 @@ define nofpclass(inf nan norm sub nzero) half @ret_only_pzero__fptrunc(float %x)
define nofpclass(inf nan norm sub pzero) half @ret_only_nzero__fptrunc(float %x) {
; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) half @ret_only_nzero__fptrunc(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret half 0xH8000
+; CHECK-NEXT: ret half -0.000000e+00
;
%result = fptrunc float %x to half
ret half %result
@@ -418,7 +418,7 @@ define nofpclass(inf nan norm pzero psub) half @ret_only_nsub_nzero__fptrunc(flo
define nofpclass(ninf) half @ret_no_ninf__fptrunc__inf() {
; CHECK-LABEL: define nofpclass(ninf) half @ret_no_ninf__fptrunc__inf() {
; CHECK-NEXT: [[INF:%.*]] = call float @returns_inf_f32()
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%inf = call float @returns_inf_f32()
%result = fptrunc float %inf to half
@@ -429,7 +429,7 @@ define nofpclass(ninf) half @ret_no_ninf__fptrunc__inf() {
define nofpclass(pinf) half @ret_no_pinf__fptrunc__inf() {
; CHECK-LABEL: define nofpclass(pinf) half @ret_no_pinf__fptrunc__inf() {
; CHECK-NEXT: [[INF:%.*]] = call float @returns_inf_f32()
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%inf = call float @returns_inf_f32()
%result = fptrunc float %inf to half
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-frexp.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-frexp.ll
index ee431d216b41f..51d0125565d3b 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-frexp.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-frexp.ll
@@ -65,7 +65,7 @@ define nofpclass(nan) half @extractvalue_not_frexp() {
define nofpclass(snan inf norm sub zero) half @ret_only_qnan__frexp(half %unknown) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) half @ret_only_qnan__frexp(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%frexp = call { half, i32 } @llvm.frexp.f16.i32(half %unknown)
%frexp.mant = extractvalue { half, i32 } %frexp, 0
@@ -85,7 +85,7 @@ define nofpclass(qnan inf norm sub zero) half @ret_only_snan__frexp(half %unknow
define nofpclass(inf norm sub zero) half @ret_only_nan__frexp(half %unknown) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan__frexp(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%frexp = call { half, i32 } @llvm.frexp.f16.i32(half %unknown)
%frexp.mant = extractvalue { half, i32 } %frexp, 0
@@ -95,7 +95,7 @@ define nofpclass(inf norm sub zero) half @ret_only_nan__frexp(half %unknown) {
define nofpclass(nan ninf norm sub zero) half @ret_only_pinf__frexp(half %unknown) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) half @ret_only_pinf__frexp(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%frexp = call { half, i32 } @llvm.frexp.f16.i32(half %unknown)
%frexp.mant = extractvalue { half, i32 } %frexp, 0
@@ -105,7 +105,7 @@ define nofpclass(nan ninf norm sub zero) half @ret_only_pinf__frexp(half %unknow
define nofpclass(nan pinf norm sub zero) half @ret_only_ninf__frexp(half %unknown) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) half @ret_only_ninf__frexp(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%frexp = call { half, i32 } @llvm.frexp.f16.i32(half %unknown)
%frexp.mant = extractvalue { half, i32 } %frexp, 0
@@ -125,7 +125,7 @@ define nofpclass(nan norm sub zero) half @ret_only_inf__frexp(half %unknown) {
define nofpclass(nan inf norm sub nzero) half @ret_only_pzero__frexp(half %unknown) {
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) half @ret_only_pzero__frexp(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%frexp = call { half, i32 } @llvm.frexp.f16.i32(half %unknown)
%frexp.mant = extractvalue { half, i32 } %frexp, 0
@@ -135,7 +135,7 @@ define nofpclass(nan inf norm sub nzero) half @ret_only_pzero__frexp(half %unkno
define nofpclass(nan inf norm sub nzero) half @ret_only_nzero__frexp(half %unknown) {
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) half @ret_only_nzero__frexp(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%frexp = call { half, i32 } @llvm.frexp.f16.i32(half %unknown)
%frexp.mant = extractvalue { half, i32 } %frexp, 0
@@ -533,7 +533,7 @@ define nofpclass(snan) half @src_only_inf__frexp() {
define nofpclass(snan) half @src_only_nan__frexp() {
; CHECK-LABEL: define nofpclass(snan) half @src_only_nan__frexp() {
; CHECK-NEXT: [[ONLY_NAN:%.*]] = call half @returns_nan()
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%only.nan = call half @returns_nan()
%frexp = call { half, i32 } @llvm.frexp.f16.i32(half %only.nan)
@@ -583,7 +583,7 @@ define nofpclass(nan) half @ret_no_nan_src_only_inf__frexp() {
define nofpclass(inf) half @ret_no_inf_src_only_nan__frexp() {
; CHECK-LABEL: define nofpclass(inf) half @ret_no_inf_src_only_nan__frexp() {
; CHECK-NEXT: [[NAN:%.*]] = call half @returns_nan()
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%nan = call half @returns_nan()
%frexp = call { half, i32 } @llvm.frexp.f16.i32(half %nan)
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll
index 88cbb7d86c1e7..7b0fae7c9263e 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll
@@ -35,7 +35,7 @@ declare void @use(half)
define nofpclass(inf zero sub norm) half @ret_only_nan(half %x, half %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%add = fsub half %x, %y
ret half %add
@@ -44,7 +44,7 @@ define nofpclass(inf zero sub norm) half @ret_only_nan(half %x, half %y) {
define nofpclass(snan inf zero sub norm) half @ret_only_qnan(half %x, half %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) half @ret_only_qnan(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH7E00
+; CHECK-NEXT: ret half +qnan
;
%add = fsub half %x, %y
ret half %add
@@ -73,7 +73,7 @@ define nofpclass(nan inf sub norm) half @ret_only_zero(half %x, half %y) {
define nofpclass(nan inf nzero sub norm) half @ret_only_pzero(half %x, half %y) {
; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) half @ret_only_pzero(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%add = fsub half %x, %y
ret half %add
@@ -82,7 +82,7 @@ define nofpclass(nan inf nzero sub norm) half @ret_only_pzero(half %x, half %y)
define nofpclass(nan inf pzero sub norm) half @ret_only_nzero(half %x, half %y) {
; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) half @ret_only_nzero(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH8000
+; CHECK-NEXT: ret half -0.000000e+00
;
%add = fsub half %x, %y
ret half %add
@@ -101,7 +101,7 @@ define nofpclass(nan zero sub norm) half @ret_only_inf(half %x, half %y) {
define nofpclass(nan ninf zero sub norm) half @ret_only_pinf(half %x, half %y) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) half @ret_only_pinf(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%add = fsub half %x, %y
ret half %add
@@ -110,7 +110,7 @@ define nofpclass(nan ninf zero sub norm) half @ret_only_pinf(half %x, half %y) {
define nofpclass(nan pinf zero sub norm) half @ret_only_ninf(half %x, half %y) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) half @ret_only_ninf(
; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%add = fsub half %x, %y
ret half %add
@@ -119,7 +119,7 @@ define nofpclass(nan pinf zero sub norm) half @ret_only_ninf(half %x, half %y) {
define nofpclass(pinf) half @ret_nofpclass_pinf__fsub_select_unknown_or_pinf__unknown(i1 %cond, half %x, half %y) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fsub_select_unknown_or_pinf__unknown(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_PINF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fsub half [[X_OR_PINF]], [[Y]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -131,7 +131,7 @@ define nofpclass(pinf) half @ret_nofpclass_pinf__fsub_select_unknown_or_pinf__un
define nofpclass(pinf) half @ret_nofpclass_pinf__fsub_unknown__select_unknown_or_pinf(i1 %cond, half %x, half %y) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fsub_unknown__select_unknown_or_pinf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[Y_OR_PINF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fsub half [[X]], [[Y_OR_PINF]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -172,7 +172,7 @@ define nofpclass(pinf) half @ret_nofpclass_pinf__fsub_select_unknown_or_pinf(i1
; CHECK-LABEL: define nofpclass(pinf) half @ret_nofpclass_pinf__fsub_select_unknown_or_pinf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = fsub half [[X]], [[Y]]
-; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], half [[TMP1]], half 0xH7E00
+; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], half [[TMP1]], half +qnan
; CHECK-NEXT: ret half [[ADD]]
;
%x.or.pinf = select i1 %cond, half %x, half 0xH7C00
@@ -185,7 +185,7 @@ define nofpclass(ninf) half @ret_nofpclass_ninf__fsub_select_unknown_or_ninf(i1
; CHECK-LABEL: define nofpclass(ninf) half @ret_nofpclass_ninf__fsub_select_unknown_or_ninf(
; CHECK-SAME: i1 [[COND:%.*]], half [[X:%.*]], half [[Y:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = fsub half [[X]], [[Y]]
-; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], half [[TMP1]], half 0xH7E00
+; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], half [[TMP1]], half +qnan
; CHECK-NEXT: ret half [[ADD]]
;
%x.or.ninf = select i1 %cond, half %x, half 0xHFC00
@@ -233,7 +233,7 @@ define nofpclass(inf sub norm) half @nan_result_demands_inf_input_lhs(i1 %cond,
; CHECK-LABEL: define nofpclass(inf sub norm) half @nan_result_demands_inf_input_lhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(nan inf zero) [[Y:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call half @returns_pinf()
-; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fsub half [[X_OR_INF]], [[Y]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -248,7 +248,7 @@ define nofpclass(inf sub norm) half @nan_result_demands_inf_input_rhs(i1 %cond,
; CHECK-LABEL: define nofpclass(inf sub norm) half @nan_result_demands_inf_input_rhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half [[Y:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call half @returns_pinf()
-; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fsub half [[X]], [[Y_OR_INF]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -293,7 +293,7 @@ define nofpclass(nan sub norm zero) half @inf_result_demands_pinf_input_lhs(i1 %
; CHECK-LABEL: define nofpclass(nan zero sub norm) half @inf_result_demands_pinf_input_lhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(zero) [[Y:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call half @returns_pinf()
-; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half 0xH7C00
+; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fsub nnan half [[X_OR_INF]], [[Y]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -308,7 +308,7 @@ define nofpclass(nan sub norm zero) half @inf_result_demands_pinf_input_rhs(i1 %
; CHECK-LABEL: define nofpclass(nan zero sub norm) half @inf_result_demands_pinf_input_rhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(zero) [[Y:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call half @returns_pinf()
-; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half 0xH7C00
+; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half +inf
; CHECK-NEXT: [[ADD:%.*]] = fsub nnan half [[X]], [[Y_OR_INF]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -323,7 +323,7 @@ define nofpclass(nan sub norm zero) half @inf_result_demands_ninf_input_lhs(i1 %
; CHECK-LABEL: define nofpclass(nan zero sub norm) half @inf_result_demands_ninf_input_lhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(zero) [[Y:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call half @returns_ninf()
-; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half 0xHFC00
+; CHECK-NEXT: [[X_OR_INF:%.*]] = select i1 [[COND]], half [[X]], half -inf
; CHECK-NEXT: [[ADD:%.*]] = fsub nnan half [[X_OR_INF]], [[Y]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -338,7 +338,7 @@ define nofpclass(nan sub norm zero) half @inf_result_demands_ninf_input_rhs(i1 %
; CHECK-LABEL: define nofpclass(nan zero sub norm) half @inf_result_demands_ninf_input_rhs(
; CHECK-SAME: i1 [[COND:%.*]], half nofpclass(zero) [[X:%.*]], half nofpclass(zero) [[Y:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call half @returns_ninf()
-; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half 0xHFC00
+; CHECK-NEXT: [[Y_OR_INF:%.*]] = select i1 [[COND]], half [[Y]], half -inf
; CHECK-NEXT: [[ADD:%.*]] = fsub nnan half [[X]], [[Y_OR_INF]]
; CHECK-NEXT: ret half [[ADD]]
;
@@ -529,7 +529,7 @@ define nofpclass(nan) half @ret_nonan_fabs_fsub_known_positive_sources() {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan_fabs_fsub_known_positive_sources() {
; CHECK-NEXT: [[POSITIVE0:%.*]] = call half @returns_positive()
; CHECK-NEXT: [[POSITIVE1:%.*]] = call half @returns_positive()
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%positive0 = call half @returns_positive()
%positive1 = call half @returns_positive()
@@ -695,7 +695,7 @@ define nofpclass(snan) half @pzero__fsub__unknown(half %unknown) {
; CHECK-LABEL: define nofpclass(snan) half @pzero__fsub__unknown(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fsub half 0xH0000, [[UNKNOWN]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub half 0.000000e+00, [[UNKNOWN]]
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -718,7 +718,7 @@ define nofpclass(nan) half @ret_nonan__pzero__fsub__unknown(half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__pzero__fsub__unknown(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fsub nnan half 0xH0000, [[UNKNOWN]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub nnan half 0.000000e+00, [[UNKNOWN]]
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -730,7 +730,7 @@ define nofpclass(snan) half @unknown__fsub__nzero(half %unknown) {
; CHECK-LABEL: define nofpclass(snan) half @unknown__fsub__nzero(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NZERO:%.*]] = call half @returns_nzero()
-; CHECK-NEXT: [[ADD:%.*]] = fadd half [[UNKNOWN]], 0xH0000
+; CHECK-NEXT: [[ADD:%.*]] = fadd half [[UNKNOWN]], 0.000000e+00
; CHECK-NEXT: ret half [[ADD]]
;
%nzero = call half @returns_nzero()
@@ -778,7 +778,7 @@ define nofpclass(nan) half @ret_nonan__unknown__fsub__nzero(half %unknown) {
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__unknown__fsub__nzero(
; CHECK-SAME: half [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NZERO:%.*]] = call half @returns_nzero()
-; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[UNKNOWN]], 0xH0000
+; CHECK-NEXT: [[ADD:%.*]] = fadd nnan half [[UNKNOWN]], 0.000000e+00
; CHECK-NEXT: ret half [[ADD]]
;
%nzero = call half @returns_nzero()
@@ -837,7 +837,7 @@ define nofpclass(snan) half @pzero__fsub__not_nzero(half nofpclass(nzero) %not.n
; CHECK-LABEL: define nofpclass(snan) half @pzero__fsub__not_nzero(
; CHECK-SAME: half nofpclass(nzero) [[NOT_NZERO:%.*]]) {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fsub half 0xH0000, [[NOT_NZERO]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub half 0.000000e+00, [[NOT_NZERO]]
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -1030,7 +1030,7 @@ define nofpclass(snan) half @pzero__fsub__not_nzero__daz(half nofpclass(nzero) %
; CHECK-LABEL: define nofpclass(snan) half @pzero__fsub__not_nzero__daz(
; CHECK-SAME: half nofpclass(nzero) [[NOT_NZERO:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fsub half 0xH0000, [[NOT_NZERO]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub half 0.000000e+00, [[NOT_NZERO]]
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -1053,7 +1053,7 @@ define nofpclass(snan) half @pzero__fsub__not_nzero__dynamic(half nofpclass(nzer
; CHECK-LABEL: define nofpclass(snan) half @pzero__fsub__not_nzero__dynamic(
; CHECK-SAME: half nofpclass(nzero) [[NOT_NZERO:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fsub half 0xH0000, [[NOT_NZERO]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub half 0.000000e+00, [[NOT_NZERO]]
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -1076,7 +1076,7 @@ define nofpclass(snan) half @pzero__fsub__not_nzero_nsub__daz(half nofpclass(nze
; CHECK-LABEL: define nofpclass(snan) half @pzero__fsub__not_nzero_nsub__daz(
; CHECK-SAME: half nofpclass(nzero nsub) [[NOT_NZERO_NSUB:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fsub half 0xH0000, [[NOT_NZERO_NSUB]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub half 0.000000e+00, [[NOT_NZERO_NSUB]]
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -1099,7 +1099,7 @@ define nofpclass(snan) half @pzero__fsub__not_nzero_nsub__dynamic(half nofpclass
; CHECK-LABEL: define nofpclass(snan) half @pzero__fsub__not_nzero_nsub__dynamic(
; CHECK-SAME: half nofpclass(nzero nsub) [[NOT_NZERO_NSUB:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[PZERO:%.*]] = call half @returns_pzero()
-; CHECK-NEXT: [[ADD:%.*]] = fsub half 0xH0000, [[NOT_NZERO_NSUB]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub half 0.000000e+00, [[NOT_NZERO_NSUB]]
; CHECK-NEXT: ret half [[ADD]]
;
%pzero = call half @returns_pzero()
@@ -1111,7 +1111,7 @@ define nofpclass(nan) half @ret_nonan__fsub_self__nonan(i1 %cond, half noundef %
; CHECK-LABEL: define nofpclass(nan) half @ret_nonan__fsub_self__nonan(
; CHECK-SAME: i1 [[COND:%.*]], half noundef [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NAN:%.*]] = call noundef half @returns_nan()
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%nan = call noundef half @returns_nan()
%select = select i1 %cond, half %nan, half %unknown
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-insertelement.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-insertelement.ll
index 36d8766d967aa..0631e9883d395 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-insertelement.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-insertelement.ll
@@ -49,7 +49,7 @@ define nofpclass(nan zero sub norm) <4 x half> @ret_only_inf__insert_unknown_unk
define nofpclass(nan ninf zero sub norm) <4 x half> @ret_only_pinf__insert_unknown_unknown(<4 x half> %vec, half %elt, i32 %idx) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) <4 x half> @ret_only_pinf__insert_unknown_unknown(
; CHECK-SAME: <4 x half> [[VEC:%.*]], half [[ELT:%.*]], i32 [[IDX:%.*]]) {
-; CHECK-NEXT: ret <4 x half> splat (half 0xH7C00)
+; CHECK-NEXT: ret <4 x half> splat (half +inf)
;
%insert = insertelement <4 x half> %vec, half %elt, i32 %idx
ret <4 x half> %insert
@@ -58,7 +58,7 @@ define nofpclass(nan ninf zero sub norm) <4 x half> @ret_only_pinf__insert_unkno
define nofpclass(nan pinf zero sub norm) <4 x half> @ret_only_ninf__insert_unknown_unknown(<4 x half> %vec, half %elt, i32 %idx) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) <4 x half> @ret_only_ninf__insert_unknown_unknown(
; CHECK-SAME: <4 x half> [[VEC:%.*]], half [[ELT:%.*]], i32 [[IDX:%.*]]) {
-; CHECK-NEXT: ret <4 x half> splat (half 0xHFC00)
+; CHECK-NEXT: ret <4 x half> splat (half -inf)
;
%insert = insertelement <4 x half> %vec, half %elt, i32 %idx
ret <4 x half> %insert
@@ -86,7 +86,7 @@ define nofpclass(nan inf nzero sub norm) <4 x half> @ret_only_pzero__insert_unkn
define nofpclass(nan inf pzero sub norm) <4 x half> @ret_only_nzero__insert_unknown_unknown(<4 x half> %vec, half %elt, i32 %idx) {
; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) <4 x half> @ret_only_nzero__insert_unknown_unknown(
; CHECK-SAME: <4 x half> [[VEC:%.*]], half [[ELT:%.*]], i32 [[IDX:%.*]]) {
-; CHECK-NEXT: ret <4 x half> splat (half 0xH8000)
+; CHECK-NEXT: ret <4 x half> splat (half -0.000000e+00)
;
%insert = insertelement <4 x half> %vec, half %elt, i32 %idx
ret <4 x half> %insert
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-ldexp.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-ldexp.ll
index b110f58f64c23..0ca11d09b56de 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-ldexp.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-ldexp.ll
@@ -34,7 +34,7 @@ define nofpclass(qnan inf norm sub zero) float @ret_only_snan__ldexp(float %x, i
define nofpclass(snan inf norm sub zero) float @ret_only_qnan__ldexp(float %x, i32 %exp) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan__ldexp(
; CHECK-SAME: float [[X:%.*]], i32 [[EXP:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 %exp)
ret float %ldexp
@@ -43,7 +43,7 @@ define nofpclass(snan inf norm sub zero) float @ret_only_qnan__ldexp(float %x, i
define nofpclass(inf norm sub zero) float @ret_only_nan__ldexp(float %x, i32 %exp) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan__ldexp(
; CHECK-SAME: float [[X:%.*]], i32 [[EXP:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 %exp)
ret float %ldexp
@@ -62,7 +62,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf__ldexp(float %x, i32 %ex
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf__ldexp(float %x, i32 %exp) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf__ldexp(
; CHECK-SAME: float [[X:%.*]], i32 [[EXP:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 %exp)
ret float %ldexp
@@ -71,7 +71,7 @@ define nofpclass(nan ninf norm sub zero) float @ret_only_pinf__ldexp(float %x, i
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf__ldexp(float %x, i32 %exp) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf__ldexp(
; CHECK-SAME: float [[X:%.*]], i32 [[EXP:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 %exp)
ret float %ldexp
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll
index 6f9f20f12a007..737b32b4e2651 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll
@@ -7,7 +7,7 @@ declare nofpclass(qnan inf norm sub zero) float @returns_snan()
define nofpclass(inf norm sub zero) float @ret_nofpclass_only_nan__log(float %unknown) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_nofpclass_only_nan__log(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.log.f32(float %unknown)
ret float %result
@@ -37,7 +37,7 @@ define nofpclass(nan inf norm sub nzero) float @ret_nofpclass_only_pzero__log(fl
define nofpclass(nan ninf norm sub zero) float @ret_nofpclass_only_pinf__log(float %unknown) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_nofpclass_only_pinf__log(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.log.f32(float %unknown)
ret float %result
@@ -47,7 +47,7 @@ define nofpclass(nan ninf norm sub zero) float @ret_nofpclass_only_pinf__log(flo
define nofpclass(nan pinf norm sub zero) float @ret_nofpclass_only_ninf__log(float %unknown) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_nofpclass_only_ninf__log(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.log.f32(float %unknown)
ret float %result
@@ -161,7 +161,7 @@ define nofpclass(ninf norm zero) float @ret_nofpclass_nan_or_sub__log_select__fi
define nofpclass(pinf nan norm zero) float @ret_ninf_or_sub__log_select__pinf_or_sub_orzero__else_not0__ieee(i1 %cond, float nofpclass(ninf norm nan) %must.be.pinf.or.sub.or.zero, float nofpclass(zero) %not.zero) {
; CHECK-LABEL: define nofpclass(nan pinf zero norm) float @ret_ninf_or_sub__log_select__pinf_or_sub_orzero__else_not0__ieee(
; CHECK-SAME: i1 [[COND:%.*]], float nofpclass(nan ninf norm) [[MUST_BE_PINF_OR_SUB_OR_ZERO:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%select = select i1 %cond, float %must.be.pinf.or.sub.or.zero, float %not.zero
%result = call float @llvm.log.f32(float %select)
@@ -171,7 +171,7 @@ define nofpclass(pinf nan norm zero) float @ret_ninf_or_sub__log_select__pinf_or
define nofpclass(pinf nan norm zero) float @ret_ninf_or_sub__log_select__pinf_or_sub_orzero__else_not0__daz(i1 %cond, float nofpclass(ninf norm nan) %must.be.pinf.or.sub.or.zero, float nofpclass(zero) %not.zero) #0 {
; CHECK-LABEL: define nofpclass(nan pinf zero norm) float @ret_ninf_or_sub__log_select__pinf_or_sub_orzero__else_not0__daz(
; CHECK-SAME: i1 [[COND:%.*]], float nofpclass(nan ninf norm) [[MUST_BE_PINF_OR_SUB_OR_ZERO:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%select = select i1 %cond, float %must.be.pinf.or.sub.or.zero, float %not.zero
%result = call float @llvm.log.f32(float %select)
@@ -181,7 +181,7 @@ define nofpclass(pinf nan norm zero) float @ret_ninf_or_sub__log_select__pinf_or
define nofpclass(pinf nan norm zero) float @ret_ninf_or_sub__log_select__pinf_or_sub_orzero__else_not0__dynamic(i1 %cond, float nofpclass(ninf norm nan) %must.be.pinf.or.sub.or.zero, float nofpclass(zero) %not.zero) #1 {
; CHECK-LABEL: define nofpclass(nan pinf zero norm) float @ret_ninf_or_sub__log_select__pinf_or_sub_orzero__else_not0__dynamic(
; CHECK-SAME: i1 [[COND:%.*]], float nofpclass(nan ninf norm) [[MUST_BE_PINF_OR_SUB_OR_ZERO:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%select = select i1 %cond, float %must.be.pinf.or.sub.or.zero, float %not.zero
%result = call float @llvm.log.f32(float %select)
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
index 420588bce238a..2386a5e8af85e 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
@@ -50,7 +50,7 @@ declare nofpclass(ninf nnorm nsub zero) float @returns_positive_nonzero_or_nan()
define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.maximum.f32(float %x, float %y)
ret float %result
@@ -69,7 +69,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y
define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.maximum.f32(float %x, float %y)
ret float %result
@@ -88,7 +88,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf(float %x, float %y) {
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.maximum.f32(float %x, float %y)
ret float %result
@@ -97,7 +97,7 @@ define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maximum.f32(float %x, float %y)
ret float %result
@@ -166,7 +166,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_known_positive_or_nan__maximu
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_known_positive_or_nan__maximum__negative_or_nan___negative_or_nan() {
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN0:%.*]] = call float @returns_negative_or_nan()
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN1:%.*]] = call float @returns_negative_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.negative.or.nan0 = call float @returns_negative_or_nan()
%must.be.negative.or.nan1 = call float @returns_negative_or_nan()
@@ -179,7 +179,7 @@ define nofpclass(pinf pnorm psub pzero) float @ret_known_negative_or_nan__maximu
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_known_negative_or_nan__maximum__positive_or_nan___positive_or_nan() {
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN0:%.*]] = call float @returns_positive_or_nan()
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN1:%.*]] = call float @returns_positive_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.positive.or.nan0 = call float @returns_positive_or_nan()
%must.be.positive.or.nan1 = call float @returns_positive_or_nan()
@@ -432,7 +432,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm
define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(nan ninf norm zero sub) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.maximum.f32(float %must.be.pinf, float %unknown)
@@ -442,7 +442,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.maximum.f32(float %unknown, float %must.be.pinf)
@@ -453,7 +453,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zer
define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan ninf norm zero sub) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maximum.f32(float %must.be.pinf, float %not.nan)
ret float %result
@@ -463,7 +463,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan)
define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float nofpclass(nan) %not.nan) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maximum.f32(float %not.nan, float %must.be.pinf)
ret float %result
@@ -1345,7 +1345,7 @@ define nofpclass(snan) float @pinf__maximum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @pinf__maximum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%pinf = call float @returns_pinf()
@@ -1357,7 +1357,7 @@ define nofpclass(snan) float @unknown__maximum__pinf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__maximum__pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%pinf = call float @returns_pinf()
@@ -1579,7 +1579,7 @@ define nofpclass(snan) float @pinf__maximum__not_nan(float nofpclass(nan) %not.n
; CHECK-LABEL: define nofpclass(snan) float @pinf__maximum__not_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf.or.nan = call float @returns_pinf()
%result = call float @llvm.maximum.f32(float %pinf.or.nan, float %not.nan)
@@ -1590,7 +1590,7 @@ define nofpclass(snan) float @not_nan__maximum__pinf(float nofpclass(nan) %not.n
; CHECK-LABEL: define nofpclass(snan) float @not_nan__maximum__pinf(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf.or.nan = call float @returns_pinf()
%result = call float @llvm.maximum.f32(float %not.nan, float %pinf.or.nan)
@@ -1996,7 +1996,7 @@ define nofpclass(snan) float @known_pinf__maximum__known_psub() {
; CHECK-LABEL: define nofpclass(snan) float @known_pinf__maximum__known_psub() {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf = call float @returns_pinf()
%psub = call float @returns_psub()
@@ -2008,7 +2008,7 @@ define nofpclass(snan) float @known_psub__maximum__known_pinf() {
; CHECK-LABEL: define nofpclass(snan) float @known_psub__maximum__known_pinf() {
; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub()
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%psub = call float @returns_psub()
%pinf = call float @returns_pinf()
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
index 7c36c3eb871a6..8a27076d75ed3 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
@@ -49,7 +49,7 @@ declare nofpclass(ninf nnorm nsub zero) float @returns_positive_nonzero_or_nan()
define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
@@ -68,7 +68,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y
define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
@@ -87,7 +87,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf(float %x, float %y) {
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
@@ -96,7 +96,7 @@ define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %result
@@ -165,7 +165,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_known_positive_or_nan__maximu
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_known_positive_or_nan__maximumnum__negative_or_nan___negative_or_nan() {
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN0:%.*]] = call float @returns_negative_or_nan()
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN1:%.*]] = call float @returns_negative_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.negative.or.nan0 = call float @returns_negative_or_nan()
%must.be.negative.or.nan1 = call float @returns_negative_or_nan()
@@ -178,7 +178,7 @@ define nofpclass(pinf pnorm psub pzero) float @ret_known_negative_or_nan__maximu
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_known_negative_or_nan__maximumnum__positive_or_nan___positive_or_nan() {
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN0:%.*]] = call float @returns_positive_or_nan()
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN1:%.*]] = call float @returns_positive_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.positive.or.nan0 = call float @returns_positive_or_nan()
%must.be.positive.or.nan1 = call float @returns_positive_or_nan()
@@ -433,7 +433,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm
define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(nan ninf norm zero sub) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maximumnum.f32(float %must.be.pinf, float %unknown)
ret float %result
@@ -442,7 +442,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maximumnum.f32(float %unknown, float %must.be.pinf)
ret float %result
@@ -452,7 +452,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zer
define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan ninf norm zero sub) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maximumnum.f32(float %must.be.pinf, float %not.nan)
ret float %result
@@ -462,7 +462,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan)
define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float nofpclass(nan) %not.nan) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maximumnum.f32(float %not.nan, float %must.be.pinf)
ret float %result
@@ -491,7 +491,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm
define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(nan pinf norm zero sub) %must.be.ninf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.maximumnum.f32(float %must.be.ninf, float %unknown)
@@ -501,7 +501,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.maximumnum.f32(float %unknown, float %must.be.ninf)
@@ -1353,7 +1353,7 @@ define nofpclass(snan) float @pinf__maximumnum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @pinf__maximumnum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf = call float @returns_pinf()
%result = call float @llvm.maximumnum.f32(float %pinf, float %unknown)
@@ -1364,7 +1364,7 @@ define nofpclass(snan) float @unknown__maximumnum__pinf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__maximumnum__pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf = call float @returns_pinf()
%result = call float @llvm.maximumnum.f32(float %unknown, float %pinf)
@@ -1399,7 +1399,7 @@ define nofpclass(snan) float @ninf__maximumnum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @ninf__maximumnum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%ninf = call float @returns_ninf()
@@ -1411,7 +1411,7 @@ define nofpclass(snan) float @unknown__maximumnum__ninf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__maximumnum__ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%ninf = call float @returns_ninf()
@@ -1587,7 +1587,7 @@ define nofpclass(snan) float @pinf__maximumnum__not_nan(float nofpclass(nan) %no
; CHECK-LABEL: define nofpclass(snan) float @pinf__maximumnum__not_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf.or.nan = call float @returns_pinf()
%result = call float @llvm.maximumnum.f32(float %pinf.or.nan, float %not.nan)
@@ -1598,7 +1598,7 @@ define nofpclass(snan) float @not_nan__maximumnum__pinf(float nofpclass(nan) %no
; CHECK-LABEL: define nofpclass(snan) float @not_nan__maximumnum__pinf(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf.or.nan = call float @returns_pinf()
%result = call float @llvm.maximumnum.f32(float %not.nan, float %pinf.or.nan)
@@ -2001,7 +2001,7 @@ define nofpclass(snan) float @known_pinf__maximumnum__known_psub() {
; CHECK-LABEL: define nofpclass(snan) float @known_pinf__maximumnum__known_psub() {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf = call float @returns_pinf()
%psub = call float @returns_psub()
@@ -2013,7 +2013,7 @@ define nofpclass(snan) float @known_psub__maximumnum__known_pinf() {
; CHECK-LABEL: define nofpclass(snan) float @known_psub__maximumnum__known_pinf() {
; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub()
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%psub = call float @returns_psub()
%pinf = call float @returns_pinf()
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
index ddd316baa1fd5..ae4aed7031d6a 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
@@ -50,7 +50,7 @@ declare nofpclass(ninf nnorm nsub zero) float @returns_positive_nonzero_or_nan()
define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.maxnum.f32(float %x, float %y)
ret float %result
@@ -69,7 +69,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y
define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.maxnum.f32(float %x, float %y)
ret float %result
@@ -88,7 +88,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf(float %x, float %y) {
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.maxnum.f32(float %x, float %y)
ret float %result
@@ -97,7 +97,7 @@ define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maxnum.f32(float %x, float %y)
ret float %result
@@ -166,7 +166,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_known_positive_or_nan__maxnum
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_known_positive_or_nan__maxnum__negative_or_nan___negative_or_nan() {
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN0:%.*]] = call float @returns_negative_or_nan()
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN1:%.*]] = call float @returns_negative_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.negative.or.nan0 = call float @returns_negative_or_nan()
%must.be.negative.or.nan1 = call float @returns_negative_or_nan()
@@ -179,7 +179,7 @@ define nofpclass(pinf pnorm psub pzero) float @ret_known_negative_or_nan__maxnum
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_known_negative_or_nan__maxnum__positive_or_nan___positive_or_nan() {
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN0:%.*]] = call float @returns_positive_or_nan()
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN1:%.*]] = call float @returns_positive_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.positive.or.nan0 = call float @returns_positive_or_nan()
%must.be.positive.or.nan1 = call float @returns_positive_or_nan()
@@ -434,7 +434,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm
define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(nan ninf norm zero sub) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maxnum.f32(float %must.be.pinf, float %unknown)
ret float %result
@@ -443,7 +443,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maxnum.f32(float %unknown, float %must.be.pinf)
ret float %result
@@ -453,7 +453,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zer
define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan ninf norm zero sub) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maxnum.f32(float %must.be.pinf, float %not.nan)
ret float %result
@@ -463,7 +463,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan)
define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float nofpclass(nan) %not.nan) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.maxnum.f32(float %not.nan, float %must.be.pinf)
ret float %result
@@ -492,7 +492,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm
define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(nan pinf norm zero sub) %must.be.ninf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.maxnum.f32(float %must.be.ninf, float %unknown)
@@ -502,7 +502,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.maxnum.f32(float %unknown, float %must.be.ninf)
@@ -1354,7 +1354,7 @@ define nofpclass(snan) float @pinf__maxnum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @pinf__maxnum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf = call float @returns_pinf()
%result = call float @llvm.maxnum.f32(float %pinf, float %unknown)
@@ -1365,7 +1365,7 @@ define nofpclass(snan) float @unknown__maxnum__pinf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__maxnum__pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf = call float @returns_pinf()
%result = call float @llvm.maxnum.f32(float %unknown, float %pinf)
@@ -1400,7 +1400,7 @@ define nofpclass(snan) float @ninf__maxnum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @ninf__maxnum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%ninf = call float @returns_ninf()
@@ -1412,7 +1412,7 @@ define nofpclass(snan) float @unknown__maxnum__ninf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__maxnum__ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%ninf = call float @returns_ninf()
@@ -1588,7 +1588,7 @@ define nofpclass(snan) float @pinf__maxnum__not_nan(float nofpclass(nan) %not.na
; CHECK-LABEL: define nofpclass(snan) float @pinf__maxnum__not_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf.or.nan = call float @returns_pinf()
%result = call float @llvm.maxnum.f32(float %pinf.or.nan, float %not.nan)
@@ -1599,7 +1599,7 @@ define nofpclass(snan) float @not_nan__maxnum__pinf(float nofpclass(nan) %not.na
; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum__pinf(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf.or.nan = call float @returns_pinf()
%result = call float @llvm.maxnum.f32(float %not.nan, float %pinf.or.nan)
@@ -2003,7 +2003,7 @@ define nofpclass(snan) float @known_pinf__maxnum__known_psub() {
; CHECK-LABEL: define nofpclass(snan) float @known_pinf__maxnum__known_psub() {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%pinf = call float @returns_pinf()
%psub = call float @returns_psub()
@@ -2015,7 +2015,7 @@ define nofpclass(snan) float @known_psub__maxnum__known_pinf() {
; CHECK-LABEL: define nofpclass(snan) float @known_psub__maxnum__known_pinf() {
; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub()
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%psub = call float @returns_psub()
%pinf = call float @returns_pinf()
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
index ab1f64209c8d1..e27d1f2052762 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
@@ -49,7 +49,7 @@ declare nofpclass(ninf nnorm nsub zero) float @returns_positive_nonzero_or_nan()
define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.minimum.f32(float %x, float %y)
ret float %result
@@ -68,7 +68,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y
define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.minimum.f32(float %x, float %y)
ret float %result
@@ -87,7 +87,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf(float %x, float %y) {
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minimum.f32(float %x, float %y)
ret float %result
@@ -96,7 +96,7 @@ define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.minimum.f32(float %x, float %y)
ret float %result
@@ -165,7 +165,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_known_positive_or_nan__minimu
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_known_positive_or_nan__minimum__negative_or_nan___negative_or_nan() {
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN0:%.*]] = call float @returns_negative_or_nan()
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN1:%.*]] = call float @returns_negative_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.negative.or.nan0 = call float @returns_negative_or_nan()
%must.be.negative.or.nan1 = call float @returns_negative_or_nan()
@@ -178,7 +178,7 @@ define nofpclass(pinf pnorm psub pzero) float @ret_known_negative_or_nan__minimu
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_known_negative_or_nan__minimum__positive_or_nan___positive_or_nan() {
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN0:%.*]] = call float @returns_positive_or_nan()
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN1:%.*]] = call float @returns_positive_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.positive.or.nan0 = call float @returns_positive_or_nan()
%must.be.positive.or.nan1 = call float @returns_positive_or_nan()
@@ -491,7 +491,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm
define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(nan pinf norm zero sub) %must.be.ninf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.minimum.f32(float %must.be.ninf, float %unknown)
@@ -501,7 +501,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.minimum.f32(float %unknown, float %must.be.ninf)
@@ -513,7 +513,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zer
define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan pinf norm zero sub) %must.be.ninf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minimum.f32(float %must.be.ninf, float %not.nan)
ret float %result
@@ -523,7 +523,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan)
define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float nofpclass(nan) %not.nan) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minimum.f32(float %not.nan, float %must.be.ninf)
ret float %result
@@ -1393,7 +1393,7 @@ define nofpclass(snan) float @ninf__minimum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @ninf__minimum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%ninf = call float @returns_ninf()
@@ -1405,7 +1405,7 @@ define nofpclass(snan) float @unknown__minimum__ninf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__minimum__ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[UNKNOWN]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[UNKNOWN]], float -inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%ninf = call float @returns_ninf()
@@ -1559,7 +1559,7 @@ define nofpclass(snan) float @ninf__minimum__not_nan(float nofpclass(nan) %not.n
; CHECK-LABEL: define nofpclass(snan) float @ninf__minimum__not_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf.or.nan = call float @returns_ninf()
%result = call float @llvm.minimum.f32(float %ninf.or.nan, float %not.nan)
@@ -1570,7 +1570,7 @@ define nofpclass(snan) float @not_nan__minimum__ninf(float nofpclass(nan) %not.n
; CHECK-LABEL: define nofpclass(snan) float @not_nan__minimum__ninf(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf.or.nan = call float @returns_ninf()
%result = call float @llvm.minimum.f32(float %not.nan, float %ninf.or.nan)
@@ -2032,7 +2032,7 @@ define nofpclass(snan) float @known_ninf__minimum__known_nsub() {
; CHECK-LABEL: define nofpclass(snan) float @known_ninf__minimum__known_nsub() {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf = call float @returns_ninf()
%nsub = call float @returns_nsub()
@@ -2044,7 +2044,7 @@ define nofpclass(snan) float @known_nsub__minimum__known_ninf() {
; CHECK-LABEL: define nofpclass(snan) float @known_nsub__minimum__known_ninf() {
; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub()
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%nsub = call float @returns_nsub()
%ninf = call float @returns_ninf()
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
index 4eb1286685b7a..4f7fe0fd453d0 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
@@ -49,7 +49,7 @@ declare nofpclass(ninf nnorm nsub zero) float @returns_positive_nonzero_or_nan()
define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
@@ -68,7 +68,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y
define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
@@ -87,7 +87,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf(float %x, float %y) {
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
@@ -96,7 +96,7 @@ define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
@@ -165,7 +165,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_known_positive_or_nan__minimu
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_known_positive_or_nan__minimumnum__negative_or_nan___negative_or_nan() {
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN0:%.*]] = call float @returns_negative_or_nan()
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN1:%.*]] = call float @returns_negative_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.negative.or.nan0 = call float @returns_negative_or_nan()
%must.be.negative.or.nan1 = call float @returns_negative_or_nan()
@@ -178,7 +178,7 @@ define nofpclass(pinf pnorm psub pzero) float @ret_known_negative_or_nan__minimu
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_known_negative_or_nan__minimumnum__positive_or_nan___positive_or_nan() {
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN0:%.*]] = call float @returns_positive_or_nan()
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN1:%.*]] = call float @returns_positive_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.positive.or.nan0 = call float @returns_positive_or_nan()
%must.be.positive.or.nan1 = call float @returns_positive_or_nan()
@@ -431,7 +431,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm
define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(nan ninf norm zero sub) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.minimumnum.f32(float %must.be.pinf, float %unknown)
@@ -441,7 +441,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.minimumnum.f32(float %unknown, float %must.be.pinf)
@@ -491,7 +491,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm
define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(nan pinf norm zero sub) %must.be.ninf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minimumnum.f32(float %must.be.ninf, float %unknown)
ret float %result
@@ -500,7 +500,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minimumnum.f32(float %unknown, float %must.be.ninf)
ret float %result
@@ -511,7 +511,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zer
define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan pinf norm zero sub) %must.be.ninf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minimumnum.f32(float %must.be.ninf, float %not.nan)
ret float %result
@@ -521,7 +521,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan)
define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float nofpclass(nan) %not.nan) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minimumnum.f32(float %not.nan, float %must.be.ninf)
ret float %result
@@ -1350,7 +1350,7 @@ define nofpclass(snan) float @pinf__minimumnum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @pinf__minimumnum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%pinf = call float @returns_pinf()
@@ -1362,7 +1362,7 @@ define nofpclass(snan) float @unknown__minimumnum__pinf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__minimumnum__pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%pinf = call float @returns_pinf()
@@ -1398,7 +1398,7 @@ define nofpclass(snan) float @ninf__minimumnum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @ninf__minimumnum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf = call float @returns_ninf()
%result = call float @llvm.minimumnum.f32(float %ninf, float %unknown)
@@ -1409,7 +1409,7 @@ define nofpclass(snan) float @unknown__minimumnum__ninf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__minimumnum__ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf = call float @returns_ninf()
%result = call float @llvm.minimumnum.f32(float %unknown, float %ninf)
@@ -1562,7 +1562,7 @@ define nofpclass(snan) float @ninf__minimumnum__not_nan(float nofpclass(nan) %no
; CHECK-LABEL: define nofpclass(snan) float @ninf__minimumnum__not_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf.or.nan = call float @returns_ninf()
%result = call float @llvm.minimumnum.f32(float %ninf.or.nan, float %not.nan)
@@ -1573,7 +1573,7 @@ define nofpclass(snan) float @not_nan__minimumnum__ninf(float nofpclass(nan) %no
; CHECK-LABEL: define nofpclass(snan) float @not_nan__minimumnum__ninf(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf.or.nan = call float @returns_ninf()
%result = call float @llvm.minimumnum.f32(float %not.nan, float %ninf.or.nan)
@@ -2040,7 +2040,7 @@ define nofpclass(snan) float @known_ninf__minimumnum__known_nsub() {
; CHECK-LABEL: define nofpclass(snan) float @known_ninf__minimumnum__known_nsub() {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf = call float @returns_ninf()
%nsub = call float @returns_nsub()
@@ -2052,7 +2052,7 @@ define nofpclass(snan) float @known_nsub__minimumnum__known_ninf() {
; CHECK-LABEL: define nofpclass(snan) float @known_nsub__minimumnum__known_ninf() {
; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub()
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%nsub = call float @returns_nsub()
%ninf = call float @returns_ninf()
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
index adcb9f067a998..dca645741b8b0 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
@@ -49,7 +49,7 @@ declare nofpclass(ninf nnorm nsub zero) float @returns_positive_nonzero_or_nan()
define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.minnum.f32(float %x, float %y)
ret float %result
@@ -68,7 +68,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y
define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y) {
; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.minnum.f32(float %x, float %y)
ret float %result
@@ -87,7 +87,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf(float %x, float %y) {
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minnum.f32(float %x, float %y)
ret float %result
@@ -96,7 +96,7 @@ define nofpclass(nan pinf norm sub zero) float @ret_only_ninf(float %x, float %y
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf(float %x, float %y) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.minnum.f32(float %x, float %y)
ret float %result
@@ -165,7 +165,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_known_positive_or_nan__minnum
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_known_positive_or_nan__minnum__negative_or_nan___negative_or_nan() {
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN0:%.*]] = call float @returns_negative_or_nan()
; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN1:%.*]] = call float @returns_negative_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.negative.or.nan0 = call float @returns_negative_or_nan()
%must.be.negative.or.nan1 = call float @returns_negative_or_nan()
@@ -178,7 +178,7 @@ define nofpclass(pinf pnorm psub pzero) float @ret_known_negative_or_nan__minnum
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_known_negative_or_nan__minnum__positive_or_nan___positive_or_nan() {
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN0:%.*]] = call float @returns_positive_or_nan()
; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN1:%.*]] = call float @returns_positive_or_nan()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%must.be.positive.or.nan0 = call float @returns_positive_or_nan()
%must.be.positive.or.nan1 = call float @returns_positive_or_nan()
@@ -431,7 +431,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm
define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(nan ninf norm zero sub) %must.be.pinf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.minnum.f32(float %must.be.pinf, float %unknown)
@@ -441,7 +441,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%result = call float @llvm.minnum.f32(float %unknown, float %must.be.pinf)
@@ -491,7 +491,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm
define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(nan pinf norm zero sub) %must.be.ninf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minnum.f32(float %must.be.ninf, float %unknown)
ret float %result
@@ -500,7 +500,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(n
define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float %unknown) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float [[UNKNOWN:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minnum.f32(float %unknown, float %must.be.ninf)
ret float %result
@@ -511,7 +511,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zer
define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan pinf norm zero sub) %must.be.ninf) {
; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minnum.f32(float %must.be.ninf, float %not.nan)
ret float %result
@@ -521,7 +521,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan)
define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float nofpclass(nan) %not.nan) {
; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.minnum.f32(float %not.nan, float %must.be.ninf)
ret float %result
@@ -1350,7 +1350,7 @@ define nofpclass(snan) float @pinf__minnum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @pinf__minnum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%pinf = call float @returns_pinf()
@@ -1362,7 +1362,7 @@ define nofpclass(snan) float @unknown__minnum__pinf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__minnum__pinf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf()
-; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float +inf)
; CHECK-NEXT: ret float [[RESULT]]
;
%pinf = call float @returns_pinf()
@@ -1398,7 +1398,7 @@ define nofpclass(snan) float @ninf__minnum__unknown(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @ninf__minnum__unknown(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf = call float @returns_ninf()
%result = call float @llvm.minnum.f32(float %ninf, float %unknown)
@@ -1409,7 +1409,7 @@ define nofpclass(snan) float @unknown__minnum__ninf(float %unknown) {
; CHECK-LABEL: define nofpclass(snan) float @unknown__minnum__ninf(
; CHECK-SAME: float [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf = call float @returns_ninf()
%result = call float @llvm.minnum.f32(float %unknown, float %ninf)
@@ -1562,7 +1562,7 @@ define nofpclass(snan) float @ninf__minnum__not_nan(float nofpclass(nan) %not.na
; CHECK-LABEL: define nofpclass(snan) float @ninf__minnum__not_nan(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf.or.nan = call float @returns_ninf()
%result = call float @llvm.minnum.f32(float %ninf.or.nan, float %not.nan)
@@ -1573,7 +1573,7 @@ define nofpclass(snan) float @not_nan__minnum__ninf(float nofpclass(nan) %not.na
; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum__ninf(
; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) {
; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf.or.nan = call float @returns_ninf()
%result = call float @llvm.minnum.f32(float %not.nan, float %ninf.or.nan)
@@ -2041,7 +2041,7 @@ define nofpclass(snan) float @known_ninf__minnum__known_nsub() {
; CHECK-LABEL: define nofpclass(snan) float @known_ninf__minnum__known_nsub() {
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ninf = call float @returns_ninf()
%nsub = call float @returns_nsub()
@@ -2053,7 +2053,7 @@ define nofpclass(snan) float @known_nsub__minnum__known_ninf() {
; CHECK-LABEL: define nofpclass(snan) float @known_nsub__minnum__known_ninf() {
; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub()
; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%nsub = call float @returns_nsub()
%ninf = call float @returns_ninf()
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-phi.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-phi.ll
index 367a5db8e8ed6..29d0b03a2bcda 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-phi.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-phi.ll
@@ -11,7 +11,7 @@ define nofpclass(nan) half @ret_phi_if_ret_0(i1 %cond1, i1 %cond2, half %unknown
; CHECK: [[IF]]:
; CHECK-NEXT: br label %[[RET]]
; CHECK: [[RET]]:
-; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[UNKNOWN]], %[[IF]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[UNKNOWN]], %[[IF]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: ret half [[PHI]]
;
entry:
@@ -34,7 +34,7 @@ define nofpclass(nan inf norm sub nzero) half @ret_phi_only_pzero(i1 %cond1, i1
; CHECK: [[IF]]:
; CHECK-NEXT: br label %[[RET]]
; CHECK: [[RET]]:
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
br i1 %cond1, label %if, label %ret
@@ -54,7 +54,7 @@ define nofpclass(inf norm sub zero) half @ret_phi_only_nan(i1 %cond1, i1 %cond2,
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br i1 [[COND1]], label %[[IF:.*]], label %[[RET:.*]]
; CHECK: [[IF]]:
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND2]], half 0xH7E00, half [[UNKNOWN]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND2]], half +qnan, half [[UNKNOWN]]
; CHECK-NEXT: br label %[[RET]]
; CHECK: [[RET]]:
; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[SELECT]], %[[IF]] ], [ poison, %[[ENTRY]] ]
@@ -80,7 +80,7 @@ define nofpclass(nan) half @ret_phi_if_ret_1(i1 %cond1, i1 %cond2, half %unknown
; CHECK: [[IF]]:
; CHECK-NEXT: br label %[[RET]]
; CHECK: [[RET]]:
-; CHECK-NEXT: [[PHI:%.*]] = phi half [ 0xH0000, %[[ENTRY]] ], [ [[UNKNOWN]], %[[IF]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi half [ 0.000000e+00, %[[ENTRY]] ], [ [[UNKNOWN]], %[[IF]] ]
; CHECK-NEXT: ret half [[PHI]]
;
entry:
@@ -110,7 +110,7 @@ define nofpclass(nan) half @ret_repeated_switch_pred(i8 %switch.cond, i1 %cond2,
; CHECK: [[DEFAULT]]:
; CHECK-NEXT: unreachable
; CHECK: [[RET]]:
-; CHECK-NEXT: [[PHI:%.*]] = phi half [ 0xH0000, %[[IF]] ], [ [[UNKNOWN]], %[[ENTRY]] ], [ [[UNKNOWN]], %[[ENTRY]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi half [ 0.000000e+00, %[[IF]] ], [ [[UNKNOWN]], %[[ENTRY]] ], [ [[UNKNOWN]], %[[ENTRY]] ]
; CHECK-NEXT: ret half [[PHI]]
;
entry:
@@ -141,10 +141,10 @@ define nofpclass(nan) half @ret_phi_chain(i1 %cond1, i1 %cond2, i1 %cond3, half
; CHECK: [[IF0]]:
; CHECK-NEXT: br i1 [[COND2]], label %[[IF1]], label %[[RET:.*]]
; CHECK: [[IF1]]:
-; CHECK-NEXT: [[PHI0:%.*]] = phi half [ [[UNKNOWN]], %[[IF0]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[PHI0:%.*]] = phi half [ [[UNKNOWN]], %[[IF0]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[RET]]
; CHECK: [[RET]]:
-; CHECK-NEXT: [[PHI1:%.*]] = phi half [ [[PHI0]], %[[IF1]] ], [ 0xH0000, %[[IF0]] ]
+; CHECK-NEXT: [[PHI1:%.*]] = phi half [ [[PHI0]], %[[IF1]] ], [ 0.000000e+00, %[[IF0]] ]
; CHECK-NEXT: ret half [[PHI1]]
;
entry:
@@ -197,7 +197,7 @@ define nofpclass(nan) half @basic_loop_break_mid_loop(i1 %cond1, i1 %cond2, half
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[LOAD:%.*]], %[[LOOP]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[LOAD:%.*]], %[[LOOP]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: [[LOAD]] = load half, ptr [[P1]], align 2
; CHECK-NEXT: [[BREAK_COND:%.*]] = load i1, ptr [[P0]], align 1
; CHECK-NEXT: br i1 [[BREAK_COND]], label %[[RET:.*]], label %[[LOOP]]
@@ -224,7 +224,7 @@ define nofpclass(inf) half @recurrence(i1 %select.cond, half %unknown, ptr %p0,
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[LOAD:%.*]], %[[LOOP]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[LOAD:%.*]], %[[LOOP]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: [[LOAD]] = load half, ptr [[P1]], align 2
; CHECK-NEXT: [[BREAK_COND:%.*]] = load i1, ptr [[P0]], align 1
; CHECK-NEXT: br i1 [[BREAK_COND]], label %[[RET:.*]], label %[[LOOP]]
@@ -249,12 +249,12 @@ define nofpclass(nan) half @path_dependent(i1 %select.cond, half %unknown, half
; CHECK-LABEL: define nofpclass(nan) half @path_dependent(
; CHECK-SAME: i1 [[SELECT_COND:%.*]], half [[UNKNOWN:%.*]], half [[X:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: br i1 [[IS_NAN]], label %[[IF:.*]], label %[[RET:.*]]
; CHECK: [[IF]]:
; CHECK-NEXT: br label %[[RET]]
; CHECK: [[RET]]:
-; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[UNKNOWN]], %[[IF]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[UNKNOWN]], %[[IF]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: ret half [[PHI]]
;
entry:
@@ -274,13 +274,13 @@ define nofpclass(nan) half @path_dependent_wrong(i1 %select.cond, half %unknown,
; CHECK-LABEL: define nofpclass(nan) half @path_dependent_wrong(
; CHECK-SAME: i1 [[SELECT_COND:%.*]], half [[UNKNOWN:%.*]], half [[X:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[IS_NOT_NAN:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[IS_NOT_NAN:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: br i1 [[IS_NOT_NAN]], label %[[IF:.*]], label %[[RET:.*]]
; CHECK: [[IF]]:
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[SELECT_COND]], half [[X]], half [[UNKNOWN]]
; CHECK-NEXT: br label %[[RET]]
; CHECK: [[RET]]:
-; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[SELECT]], %[[IF]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[SELECT]], %[[IF]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: ret half [[PHI]]
;
entry:
@@ -301,7 +301,7 @@ define nofpclass(nan) half @diamond_same_select(i1 %select.cond, half %unknown,
; CHECK-LABEL: define nofpclass(nan) half @diamond_same_select(
; CHECK-SAME: i1 [[SELECT_COND:%.*]], half [[UNKNOWN:%.*]], half [[X:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: br i1 [[IS_NAN]], label %[[IF:.*]], label %[[ELSE:.*]]
; CHECK: [[IF]]:
; CHECK-NEXT: br label %[[ENDIF:.*]]
@@ -361,7 +361,7 @@ define nofpclass(nan) half @keep_nan_start_value_multi_use(i1 %cond1, i1 %cond2,
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[LOAD:%.*]], %[[LOOP]] ], [ 0xH7E00, %[[ENTRY]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[LOAD:%.*]], %[[LOOP]] ], [ +qnan, %[[ENTRY]] ]
; CHECK-NEXT: [[LOAD]] = load half, ptr [[P1]], align 2
; CHECK-NEXT: [[BREAK_COND:%.*]] = load i1, ptr [[P0]], align 1
; CHECK-NEXT: br i1 [[BREAK_COND]], label %[[RET:.*]], label %[[LOOP]]
@@ -392,7 +392,7 @@ define nofpclass(nan) half @loop_break_if_nan(ptr %p0) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[PHI:%.*]] = phi half [ [[LOAD:%.*]], %[[LOOP]] ], [ poison, %[[ENTRY]] ]
; CHECK-NEXT: [[LOAD]] = load half, ptr [[P0]], align 2
-; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[LOAD]], 0xH0000
+; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[LOAD]], 0.000000e+00
; CHECK-NEXT: br i1 [[IS_NAN]], label %[[RET:.*]], label %[[LOOP]]
; CHECK: [[RET]]:
; CHECK-NEXT: ret half [[PHI]]
@@ -417,7 +417,7 @@ define nofpclass(nan) half @loop_break_if_nan_abs(ptr %p0) {
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[LOAD:%.*]] = load half, ptr [[P0]], align 2
-; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[LOAD]], 0xH0000
+; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[LOAD]], 0.000000e+00
; CHECK-NEXT: br i1 [[IS_NAN]], label %[[RET:.*]], label %[[LOOP]]
; CHECK: [[RET]]:
; CHECK-NEXT: ret half poison
@@ -470,7 +470,7 @@ define nofpclass(nan) half @assume_in_loop(half %assumed.nan.in.loop, half %unkn
; CHECK-NEXT: br i1 [[COND]], label %[[LOOP:.*]], label %[[RET:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[LOOP_PHI:%.*]] = phi half [ [[UNKNOWN]], %[[LOOP]] ], [ [[ASSUMED_NAN_IN_LOOP]], %[[ENTRY]] ]
-; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[ASSUMED_NAN_IN_LOOP]], 0xH0000
+; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[ASSUMED_NAN_IN_LOOP]], 0.000000e+00
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_NAN]])
; CHECK-NEXT: [[LOOP_COND:%.*]] = load i1, ptr [[P1]], align 1
; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[RET]], label %[[LOOP]]
@@ -499,7 +499,7 @@ define nofpclass(nan) half @ret_phi_nan_check(half %checked.if.nan, half %unknow
; CHECK-LABEL: define nofpclass(nan) half @ret_phi_nan_check(
; CHECK-SAME: half [[CHECKED_IF_NAN:%.*]], half [[UNKNOWN:%.*]], i1 [[COND:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[CHECKED_IF_NAN]], 0xH0000
+; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[CHECKED_IF_NAN]], 0.000000e+00
; CHECK-NEXT: br i1 [[IS_NAN]], label %[[IF_NAN:.*]], label %[[RET:.*]]
; CHECK: [[IF_NAN]]:
; CHECK-NEXT: br label %[[RET]]
@@ -524,13 +524,13 @@ define nofpclass(nan inf) half @edge_case_if_chain(half %x, i1 %cond, ptr %p0, p
; CHECK-LABEL: define nofpclass(nan inf) half @edge_case_if_chain(
; CHECK-SAME: half [[X:%.*]], i1 [[COND:%.*]], ptr [[P0:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq half [[X]], 0xH7C00
+; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq half [[X]], +inf
; CHECK-NEXT: br i1 [[IS_INF]], label %[[IS_INF:.*]], label %[[ELSE:.*]]
; CHECK: [[IS_INF]]:
; CHECK-NEXT: [[LOAD0:%.*]] = load half, ptr [[P0]], align 2
; CHECK-NEXT: br label %[[RET:.*]]
; CHECK: [[ELSE]]:
-; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: [[LOAD1:%.*]] = load half, ptr [[P0]], align 2
; CHECK-NEXT: [[VAL1:%.*]] = select i1 [[COND]], half [[LOAD1]], half [[X]]
; CHECK-NEXT: br i1 [[IS_NAN]], label %[[IS_NAN:.*]], label %[[RET]]
@@ -572,7 +572,7 @@ define nofpclass(nan) half @evaluate_phi_input_at_incoming_edge(half %known.nan.
; CHECK-LABEL: define nofpclass(nan) half @evaluate_phi_input_at_incoming_edge(
; CHECK-SAME: half [[KNOWN_NAN_IN_BRANCH:%.*]], half [[UNKNOWN:%.*]], i1 [[COND:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[KNOWN_NAN_IN_BRANCH]], 0xH0000
+; CHECK-NEXT: [[IS_NAN:%.*]] = fcmp uno half [[KNOWN_NAN_IN_BRANCH]], 0.000000e+00
; CHECK-NEXT: br i1 [[IS_NAN]], label %[[IS_NAN:.*]], label %[[RET:.*]]
; CHECK: [[IS_NAN]]:
; CHECK-NEXT: br label %[[RET]]
@@ -602,19 +602,19 @@ define nofpclass(nan) half @multi_simplify_lost_phi_context_(half %x, half %y, i
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br i1 [[COND0]], label %[[ASSUME_A:.*]], label %[[ASSUME_B:.*]]
; CHECK: [[ASSUME_A]]:
-; CHECK-NEXT: [[X_IS_NAN:%.*]] = fcmp uno half [[X]], 0xH0000
+; CHECK-NEXT: [[X_IS_NAN:%.*]] = fcmp uno half [[X]], 0.000000e+00
; CHECK-NEXT: call void @llvm.assume(i1 [[X_IS_NAN]])
; CHECK-NEXT: br label %[[A:.*]]
; CHECK: [[A]]:
; CHECK-NEXT: br label %[[RET:.*]]
; CHECK: [[ASSUME_B]]:
-; CHECK-NEXT: [[Y_IS_NAN:%.*]] = fcmp uno half [[Y]], 0xH0000
+; CHECK-NEXT: [[Y_IS_NAN:%.*]] = fcmp uno half [[Y]], 0.000000e+00
; CHECK-NEXT: call void @llvm.assume(i1 [[Y_IS_NAN]])
; CHECK-NEXT: br label %[[B:.*]]
; CHECK: [[B]]:
; CHECK-NEXT: br label %[[RET]]
; CHECK: [[RET]]:
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
entry:
br i1 %cond0, label %assume_a, label %assume_b
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
index 7e2d1bd92fc82..2801d4d79c6c9 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
@@ -61,7 +61,7 @@ define nofpclass(nan norm sub zero) float @ret_only_inf__floor(float %x) {
define nofpclass(nan pinf norm sub zero) float @ret_only_ninf__floor(float %x) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) float @ret_only_ninf__floor(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.floor.f32(float %x)
ret float %result
@@ -70,7 +70,7 @@ define nofpclass(nan pinf norm sub zero) float @ret_only_ninf__floor(float %x) {
define nofpclass(nan ninf norm sub zero) float @ret_only_pinf__floor(float %x) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) float @ret_only_pinf__floor(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.floor.f32(float %x)
ret float %result
@@ -335,7 +335,7 @@ define nofpclass(snan) float @source_known_nsub__floor(float nofpclass(inf nan n
define nofpclass(snan) float @source_known_pinf__floor(float nofpclass(nan ninf norm sub zero) %pinf) {
; CHECK-LABEL: define nofpclass(snan) float @source_known_pinf__floor(
; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[PINF:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.floor.f32(float %pinf)
ret float %result
@@ -353,7 +353,7 @@ define nofpclass(snan) float @source_known_pinf_or_nan__floor(float nofpclass(ni
define nofpclass(snan) float @source_known_ninf__floor(float nofpclass(nan pinf norm sub zero) %ninf) {
; CHECK-LABEL: define nofpclass(snan) float @source_known_ninf__floor(
; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[NINF:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%result = call float @llvm.floor.f32(float %ninf)
ret float %result
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-shufflevector.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-shufflevector.ll
index ee8be3ca1bf89..e03bc5b86a485 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-shufflevector.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-shufflevector.ll
@@ -57,7 +57,7 @@ define nofpclass(nan inf nzero sub norm) <4 x half> @ret_only_pzero__shufflevect
define nofpclass(nan inf pzero sub norm) <4 x half> @ret_only_nzero__shufflevector_unknown(<4 x half> %vec0, <4 x half> %vec1) {
; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) <4 x half> @ret_only_nzero__shufflevector_unknown(
; CHECK-SAME: <4 x half> [[VEC0:%.*]], <4 x half> [[VEC1:%.*]]) {
-; CHECK-NEXT: ret <4 x half> splat (half 0xH8000)
+; CHECK-NEXT: ret <4 x half> splat (half -0.000000e+00)
;
%shuffle = shufflevector <4 x half> %vec0, <4 x half> %vec1, <4 x i32> <i32 6, i32 2, i32 3, i32 0>
ret <4 x half> %shuffle
@@ -76,7 +76,7 @@ define nofpclass(nan zero sub norm) <4 x half> @ret_only_inf__shufflevector_unkn
define nofpclass(nan ninf zero sub norm) <4 x half> @ret_only_pinf__shufflevector_unknown(<4 x half> %vec0, <4 x half> %vec1) {
; CHECK-LABEL: define nofpclass(nan ninf zero sub norm) <4 x half> @ret_only_pinf__shufflevector_unknown(
; CHECK-SAME: <4 x half> [[VEC0:%.*]], <4 x half> [[VEC1:%.*]]) {
-; CHECK-NEXT: ret <4 x half> splat (half 0xH7C00)
+; CHECK-NEXT: ret <4 x half> splat (half +inf)
;
%shuffle = shufflevector <4 x half> %vec0, <4 x half> %vec1, <4 x i32> <i32 6, i32 2, i32 3, i32 0>
ret <4 x half> %shuffle
@@ -85,7 +85,7 @@ define nofpclass(nan ninf zero sub norm) <4 x half> @ret_only_pinf__shufflevecto
define nofpclass(nan pinf zero sub norm) <4 x half> @ret_only_ninf__shufflevector_unknown(<4 x half> %vec0, <4 x half> %vec1) {
; CHECK-LABEL: define nofpclass(nan pinf zero sub norm) <4 x half> @ret_only_ninf__shufflevector_unknown(
; CHECK-SAME: <4 x half> [[VEC0:%.*]], <4 x half> [[VEC1:%.*]]) {
-; CHECK-NEXT: ret <4 x half> splat (half 0xHFC00)
+; CHECK-NEXT: ret <4 x half> splat (half -inf)
;
%shuffle = shufflevector <4 x half> %vec0, <4 x half> %vec1, <4 x i32> <i32 6, i32 2, i32 3, i32 0>
ret <4 x half> %shuffle
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
index 6bde4c1e19e76..c6b5a83c19d35 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll
@@ -18,7 +18,7 @@ declare nofpclass(qnan inf norm sub zero) float @returns_snan()
define nofpclass(inf norm sub zero) float @ret_only_nan_sqrt(float %x) {
; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan_sqrt(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%result = call float @llvm.sqrt.f32(float %x)
ret float %result
@@ -81,7 +81,7 @@ define nofpclass(inf nan norm sub) <2 x float> @ret_only_zero_sqrt_vec(<2 x floa
define nofpclass(nan norm sub zero) float @ret_only_inf_sqrt(float %x) {
; CHECK-LABEL: define nofpclass(nan zero sub norm) float @ret_only_inf_sqrt(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%result = call float @llvm.sqrt.f32(float %x)
ret float %result
@@ -113,7 +113,7 @@ define nofpclass(ninf) float @ret_only_ninf__sqrt__known_negative() {
define nofpclass(ninf) float @ret_only_ninf__sqrt__known_negative_nonzero() {
; CHECK-LABEL: define nofpclass(ninf) float @ret_only_ninf__sqrt__known_negative_nonzero() {
; CHECK-NEXT: [[KNOWN_NEGATIVE_NONZERO:%.*]] = call float @returns_negative_nonzero()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%known.negative.nonzero = call float @returns_negative_nonzero()
%result = call float @llvm.sqrt.f32(float %known.negative.nonzero)
@@ -124,7 +124,7 @@ define nofpclass(ninf) float @ret_only_ninf__sqrt__known_negative_nonzero() {
define nofpclass(ninf) <2 x float> @ret_only_ninf__sqrt__known_negative_nonzero_vec() {
; CHECK-LABEL: define nofpclass(ninf) <2 x float> @ret_only_ninf__sqrt__known_negative_nonzero_vec() {
; CHECK-NEXT: [[KNOWN_NEGATIVE_NONZERO:%.*]] = call <2 x float> @returns_negative_nonzero_vec()
-; CHECK-NEXT: ret <2 x float> splat (float 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x float> splat (float +qnan)
;
%known.negative.nonzero = call <2 x float> @returns_negative_nonzero_vec()
%result = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %known.negative.nonzero)
@@ -162,7 +162,7 @@ define nofpclass(inf norm zero) float @ret_only_nan_or_sub__sqrt__select_unknown
; CHECK-LABEL: define nofpclass(inf zero norm) float @ret_only_nan_or_sub__sqrt__select_unknown_or_known_neg_nonzero(
; CHECK-SAME: i1 [[COND:%.*]], float [[X:%.*]]) {
; CHECK-NEXT: [[KNOWN_NEGATIVE_NONZERO:%.*]] = call float @returns_negative_nonzero()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%known.negative.nonzero = call float @returns_negative_nonzero()
%select = select i1 %cond, float %x, float %known.negative.nonzero
@@ -175,7 +175,7 @@ define nofpclass(inf norm zero) float @ret_only_nan_or_sub__sqrt__select_unknown
; CHECK-LABEL: define nofpclass(inf zero norm) float @ret_only_nan_or_sub__sqrt__select_unknown_or_maybe_ninf(
; CHECK-SAME: i1 [[COND:%.*]], float nofpclass(nan) [[X:%.*]]) {
; CHECK-NEXT: [[MAYBE_NINF:%.*]] = call nofpclass(nan pinf sub norm) float @func()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%maybe.ninf = call nofpclass(pinf norm sub nan) float @func()
%select = select i1 %cond, float %x, float %maybe.ninf
@@ -188,7 +188,7 @@ define nofpclass(inf norm zero) float @ret_only_nan_or_sub__sqrt__select_unknown
; CHECK-LABEL: define nofpclass(inf zero norm) float @ret_only_nan_or_sub__sqrt__select_unknown_or_maybe_nnorm(
; CHECK-SAME: i1 [[COND:%.*]], float nofpclass(nan) [[X:%.*]]) {
; CHECK-NEXT: [[MAYBE_NNORM:%.*]] = call nofpclass(nan inf sub pnorm) float @func()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%maybe.nnorm = call nofpclass(inf pnorm sub nan) float @func()
%select = select i1 %cond, float %x, float %maybe.nnorm
@@ -201,7 +201,7 @@ define nofpclass(inf norm zero) float @ret_only_nan_or_sub__sqrt__select_unknown
; CHECK-LABEL: define nofpclass(inf zero norm) float @ret_only_nan_or_sub__sqrt__select_unknown_or_maybe_nsub(
; CHECK-SAME: i1 [[COND:%.*]], float nofpclass(nan) [[X:%.*]]) {
; CHECK-NEXT: [[MAYBE_NSUB:%.*]] = call nofpclass(nan inf psub norm) float @func()
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%maybe.nsub = call nofpclass(inf norm psub nan) float @func()
%select = select i1 %cond, float %x, float %maybe.nsub
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
index 5d86caca2e545..6870f2967a460 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
@@ -16,7 +16,7 @@ declare nofpclass(inf norm sub zero) float @nan_only()
define float @ninf_user_select_inf(i1 %cond, float %x, float %y) {
; CHECK-LABEL: define float @ninf_user_select_inf
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[NINF_USER:%.*]] = fmul ninf float [[Y]], [[SELECT]]
; CHECK-NEXT: ret float [[NINF_USER]]
;
@@ -97,7 +97,7 @@ define nofpclass(pinf) float @ret_nofpclass_pinf__pinf() {
define nofpclass(pinf) float @ret_nofpclass_pinf__ninf() {
; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__ninf() {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
ret float 0xFFF0000000000000
}
@@ -185,7 +185,7 @@ define nofpclass(inf) float @ret_nofpclass_inf__select_ninf_or_pinf(i1 %cond, fl
define nofpclass(ninf) float @ret_nofpclass_ninf__select_ninf_or_pinf(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(ninf) float @ret_nofpclass_ninf__select_ninf_or_pinf
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%select = select i1 %cond, float 0xFFF0000000000000, float 0x7FF0000000000000
ret float %select
@@ -195,7 +195,7 @@ define nofpclass(ninf) float @ret_nofpclass_ninf__select_ninf_or_pinf(i1 %cond,
define nofpclass(pinf) float @ret_nofpclass_pinf__select_ninf_or_pinf(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__select_ninf_or_pinf
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%select = select i1 %cond, float 0xFFF0000000000000, float 0x7FF0000000000000
ret float %select
@@ -265,7 +265,7 @@ define nofpclass(inf) <2 x float> @ret_nofpclass_inf__select_mixed_inf_lhs_vecto
define nofpclass(inf) float @ret_nofpclass_inf__select_multi_use_pinf_lhs(i1 %cond, float %x, ptr %ptr) {
; CHECK-LABEL: define nofpclass(inf) float @ret_nofpclass_inf__select_multi_use_pinf_lhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]], ptr [[PTR:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float 0x7FF0000000000000, float [[X]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float +inf, float [[X]]
; CHECK-NEXT: store float [[SELECT]], ptr [[PTR]], align 4
; CHECK-NEXT: ret float [[X]]
;
@@ -300,7 +300,7 @@ define nofpclass(inf) float @ret_nofpclass_inf__select_p0_rhs(i1 %cond, float %x
define nofpclass(nan) float @ret_nofpclass_nan__select_pinf_lhs(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(nan) float @ret_nofpclass_nan__select_pinf_lhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float 0x7FF0000000000000, float [[X]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float +inf, float [[X]]
; CHECK-NEXT: ret float [[SELECT]]
;
%select = select i1 %cond, float 0x7FF0000000000000, float %x
@@ -311,7 +311,7 @@ define nofpclass(nan) float @ret_nofpclass_nan__select_pinf_lhs(i1 %cond, float
define nofpclass(nan) float @ret_nofpclass_nan__select_pinf_rhs(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(nan) float @ret_nofpclass_nan__select_pinf_rhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: ret float [[SELECT]]
;
%select = select i1 %cond, float %x, float 0x7FF0000000000000
@@ -341,7 +341,7 @@ define nofpclass(inf nan) float @ret_nofpclass_inf_nan__select_chain_inf_nan_1(i
define nofpclass(nan) float @ret_nofpclass_nan__select_chain_inf_nan(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(nan) float @ret_nofpclass_nan__select_chain_inf_nan
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[SELECT1:%.*]] = select i1 [[COND]], float 0x7FF0000000000000, float [[X]]
+; CHECK-NEXT: [[SELECT1:%.*]] = select i1 [[COND]], float +inf, float [[X]]
; CHECK-NEXT: ret float [[SELECT1]]
;
%select0 = select i1 %cond, float 0x7FF8000000000000, float %x
@@ -362,7 +362,7 @@ define nofpclass(inf) float @ret_nofpclass_inf__select_chain_inf_nan_0(i1 %cond,
define nofpclass(inf) float @ret_nofpclass_inf__select_chain_inf_nan_1(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(inf) float @ret_nofpclass_inf__select_chain_inf_nan_1
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%select0 = select i1 %cond, float 0x7FF8000000000000, float %x
%select1 = select i1 %cond, float %select0, float 0x7FF0000000000000
@@ -397,7 +397,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_nofpclass_no_negatives__fabs_
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_nofpclass_no_negatives__fabs_select_pinf_rhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[FABS:%.*]] = select i1 [[COND]], float [[TMP1]], float 0x7FF0000000000000
+; CHECK-NEXT: [[FABS:%.*]] = select i1 [[COND]], float [[TMP1]], float +inf
; CHECK-NEXT: ret float [[FABS]]
;
%select = select i1 %cond, float %x, float 0x7FF0000000000000
@@ -421,7 +421,7 @@ define nofpclass(nan ninf nnorm nsub nzero) float @ret_nofpclass_no_negatives_na
; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @ret_nofpclass_no_negatives_nan__fabs_select_pinf_rhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[FABS:%.*]] = select i1 [[COND]], float [[TMP1]], float 0x7FF0000000000000
+; CHECK-NEXT: [[FABS:%.*]] = select i1 [[COND]], float [[TMP1]], float +inf
; CHECK-NEXT: ret float [[FABS]]
;
%select = select i1 %cond, float %x, float 0x7FF0000000000000
@@ -480,7 +480,7 @@ define nofpclass(pzero psub pnorm pinf) float @ret_nofpclass_nopositives___fneg_
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_nofpclass_nopositives___fneg_select_pinf_rhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
; CHECK-NEXT: [[X_NEG:%.*]] = fneg float [[X]]
-; CHECK-NEXT: [[FNEG:%.*]] = select i1 [[COND]], float [[X_NEG]], float 0xFFF0000000000000
+; CHECK-NEXT: [[FNEG:%.*]] = select i1 [[COND]], float [[X_NEG]], float -inf
; CHECK-NEXT: ret float [[FNEG]]
;
%select = select i1 %cond, float %x, float 0x7FF0000000000000
@@ -1272,7 +1272,7 @@ define nofpclass(inf pnorm psub pzero) float @ret_nofpclass_no_positives_noinf__
define nofpclass(ninf nnorm nsub nzero) float @ret_nofpclass_no_negatives__copysign_unknown_select_pinf_rhs(i1 %cond, float %x, float %unknown.sign) {
; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_nofpclass_no_negatives__copysign_unknown_select_pinf_rhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]], float [[UNKNOWN_SIGN:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[COPYSIGN:%.*]] = call float @llvm.copysign.f32(float [[SELECT]], float [[UNKNOWN_SIGN]])
; CHECK-NEXT: ret float [[COPYSIGN]]
;
@@ -1285,7 +1285,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_nofpclass_no_negatives__copys
define nofpclass(pinf pnorm psub pzero) float @ret_nofpclass_no_positives__copysign_unknown_select_pinf_rhs(i1 %cond, float %x, float %unknown.sign) {
; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_nofpclass_no_positives__copysign_unknown_select_pinf_rhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]], float [[UNKNOWN_SIGN:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[COPYSIGN:%.*]] = call float @llvm.copysign.f32(float [[SELECT]], float [[UNKNOWN_SIGN]])
; CHECK-NEXT: ret float [[COPYSIGN]]
;
@@ -1299,7 +1299,7 @@ define nofpclass(nan ninf nnorm nsub nzero) float @ret_nofpclass_no_negatives_no
; CHECK-LABEL: define nofpclass(nan ninf nzero nsub nnorm) float @ret_nofpclass_no_negatives_nonan__copysign_unknown_select_pinf_rhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]], float [[UNKNOWN_SIGN:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[COPYSIGN:%.*]] = select i1 [[COND]], float [[TMP1]], float 0x7FF0000000000000
+; CHECK-NEXT: [[COPYSIGN:%.*]] = select i1 [[COND]], float [[TMP1]], float +inf
; CHECK-NEXT: ret float [[COPYSIGN]]
;
%select = select i1 %cond, float %x, float 0x7FF0000000000000
@@ -1313,7 +1313,7 @@ define nofpclass(nan pinf pnorm psub pzero) float @ret_nofpclass_no_positives_no
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]], float [[UNKNOWN_SIGN:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X]])
; CHECK-NEXT: [[DOTNEG:%.*]] = fneg float [[TMP1]]
-; CHECK-NEXT: [[COPYSIGN:%.*]] = select i1 [[COND]], float [[DOTNEG]], float 0xFFF0000000000000
+; CHECK-NEXT: [[COPYSIGN:%.*]] = select i1 [[COND]], float [[DOTNEG]], float -inf
; CHECK-NEXT: ret float [[COPYSIGN]]
;
%select = select i1 %cond, float %x, float 0x7FF0000000000000
@@ -1482,7 +1482,7 @@ define nofpclass(inf) float @ret_nofpclass_noinfs__assumed_isinf__select_pinf_lh
; CHECK-LABEL: define nofpclass(inf) float @ret_nofpclass_noinfs__assumed_isinf__select_pinf_lhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[X_IS_INF:%.*]] = fcmp oeq float [[FABS_X]], 0x7FF0000000000000
+; CHECK-NEXT: [[X_IS_INF:%.*]] = fcmp oeq float [[FABS_X]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[X_IS_INF]])
; CHECK-NEXT: ret float [[Y]]
;
@@ -1634,7 +1634,7 @@ define nofpclass(pinf) float @ret_nofpclass_pinf__nofpclass_call_only_inf(i1 %co
; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__nofpclass_call_only_inf
; CHECK-SAME: (i1 [[COND:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[MUST_BE_INF:%.*]] = call nofpclass(nan zero sub norm) float @extern()
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%must.be.inf = call nofpclass(nan norm zero sub) float @extern()
ret float %must.be.inf
@@ -1644,7 +1644,7 @@ define nofpclass(ninf) float @ret_nofpclass_ninf__nofpclass_call_only_inf(i1 %co
; CHECK-LABEL: define nofpclass(ninf) float @ret_nofpclass_ninf__nofpclass_call_only_inf
; CHECK-SAME: (i1 [[COND:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[MUST_BE_INF:%.*]] = call nofpclass(nan zero sub norm) float @extern()
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%must.be.inf = call nofpclass(nan norm zero sub) float @extern()
ret float %must.be.inf
@@ -1699,7 +1699,7 @@ define nofpclass(inf) float @ret_nofpclass_inf__select_assumed_call_result_only_
; CHECK-SAME: (i1 [[COND:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[MUST_BE_INF:%.*]] = call float @extern()
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[MUST_BE_INF]])
-; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_INF:%.*]] = fcmp oeq float [[FABS]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_INF]])
; CHECK-NEXT: ret float [[Y]]
;
@@ -1863,7 +1863,7 @@ define nofpclass(inf) float @ret_nofpclass_inf__arithmetic_fence_select_pinf_rhs
define nofpclass(snan) float @arithmetic_fence__noinf_callsite_param_attr_select_pinf_rhs(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(snan) float @arithmetic_fence__noinf_callsite_param_attr_select_pinf_rhs
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float +inf
; CHECK-NEXT: [[FENCE:%.*]] = call float @llvm.arithmetic.fence.f32(float nofpclass(inf) [[SELECT]])
; CHECK-NEXT: ret float [[FENCE]]
;
@@ -1876,7 +1876,7 @@ define nofpclass(snan) float @arithmetic_fence__noinf_callsite_param_attr_select
define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_pinf(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_pinf
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[MIN:%.*]] = call nsz float @llvm.minnum.f32(float [[X]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[MIN:%.*]] = call nsz float @llvm.minnum.f32(float [[X]], float +inf)
; CHECK-NEXT: ret float [[MIN]]
;
%min = call float @llvm.minnum.f32(float %x, float 0x7FF0000000000000)
@@ -1887,7 +1887,7 @@ define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_pinf(i1 %cond, float %x
define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_ninf(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_ninf
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%min = call float @llvm.minnum.f32(float %x, float 0xFFF0000000000000)
ret float %min
@@ -1897,7 +1897,7 @@ define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_ninf(i1 %cond, float %x
define nofpclass(ninf) float @ret_nofpclass_ninf__maxnum_ninf(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(ninf) float @ret_nofpclass_ninf__maxnum_ninf
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: [[MAX:%.*]] = call nsz float @llvm.maxnum.f32(float [[X]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[MAX:%.*]] = call nsz float @llvm.maxnum.f32(float [[X]], float -inf)
; CHECK-NEXT: ret float [[MAX]]
;
%max = call float @llvm.maxnum.f32(float %x, float 0xFFF0000000000000)
@@ -1908,7 +1908,7 @@ define nofpclass(ninf) float @ret_nofpclass_ninf__maxnum_ninf(i1 %cond, float %x
define nofpclass(ninf) float @ret_nofpclass_ninf__maxnum_pinf(i1 %cond, float %x) {
; CHECK-LABEL: define nofpclass(ninf) float @ret_nofpclass_ninf__maxnum_pinf
; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) {
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%max = call float @llvm.maxnum.f32(float %x, float 0x7FF0000000000000)
ret float %max
@@ -1935,14 +1935,14 @@ define nofpclass(nan) float @known_class_multiple_uses(i1 %cond0, i1 %cond1, i1
; Do not overdefine the poison element to inf.
define nofpclass(ninf) <2 x float> @single_class_constant_partially_poison_pinf() {
; CHECK-LABEL: define nofpclass(ninf) <2 x float> @single_class_constant_partially_poison_pinf() {
-; CHECK-NEXT: ret <2 x float> <float 0x7FF0000000000000, float poison>
+; CHECK-NEXT: ret <2 x float> <float +inf, float poison>
;
ret <2 x float> <float 0x7FF0000000000000, float poison>
}
define nofpclass(ninf) <2 x float> @single_class_constant_partially_undef_pinf() {
; CHECK-LABEL: define nofpclass(ninf) <2 x float> @single_class_constant_partially_undef_pinf() {
-; CHECK-NEXT: ret <2 x float> <float 0x7FF0000000000000, float undef>
+; CHECK-NEXT: ret <2 x float> <float +inf, float undef>
;
ret <2 x float> <float 0x7FF0000000000000, float undef>
}
@@ -2014,7 +2014,7 @@ define nofpclass(nan) float @ret_nonan_fmul_select_fmul_select_nan_multiple_use_
define nofpclass(nan) float @ret_nonan_fmul_select_nan_other_use(i1 %cond, float noundef %x, float %y, ptr %ptr) {
; CHECK-LABEL: define nofpclass(nan) float @ret_nonan_fmul_select_nan_other_use
; CHECK-SAME: (i1 [[COND:%.*]], float noundef [[X:%.*]], float [[Y:%.*]], ptr [[PTR:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float 0x7FF8000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[X]], float +qnan
; CHECK-NEXT: store float [[SELECT]], ptr [[PTR]], align 4
; CHECK-NEXT: [[NAN_USER:%.*]] = fmul nnan float [[X]], [[Y]]
; CHECK-NEXT: ret float [[NAN_USER]]
@@ -2028,7 +2028,7 @@ define nofpclass(nan) float @ret_nonan_fmul_select_nan_other_use(i1 %cond, float
define nofpclass(nan) float @ret_nonan_fmul_select_nan_other_use_commute(i1 %cond, float noundef %x, float %y, ptr %ptr) {
; CHECK-LABEL: define nofpclass(nan) float @ret_nonan_fmul_select_nan_other_use_commute
; CHECK-SAME: (i1 [[COND:%.*]], float noundef [[X:%.*]], float [[Y:%.*]], ptr [[PTR:%.*]]) {
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float 0x7FF8000000000000, float [[X]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float +qnan, float [[X]]
; CHECK-NEXT: store float [[SELECT]], ptr [[PTR]], align 4
; CHECK-NEXT: [[NAN_USER:%.*]] = fmul nnan float [[X]], [[Y]]
; CHECK-NEXT: ret float [[NAN_USER]]
diff --git a/llvm/test/Transforms/InstCombine/sqrt.ll b/llvm/test/Transforms/InstCombine/sqrt.ll
index 0a1aa21c04696..5965c98ceb231 100644
--- a/llvm/test/Transforms/InstCombine/sqrt.ll
+++ b/llvm/test/Transforms/InstCombine/sqrt.ll
@@ -31,7 +31,7 @@ define float @test2(float %x) nounwind readnone ssp {
define float @test3(ptr %v) nounwind uwtable ssp {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[CALL34:%.*]] = call double @sqrt(double 0x7FF8000000000000) #[[ATTR4]]
+; CHECK-NEXT: [[CALL34:%.*]] = call double @sqrt(double +qnan) #[[ATTR4]]
; CHECK-NEXT: [[CALL36:%.*]] = call i32 @foo(double [[CALL34]]) #[[ATTR5]]
; CHECK-NEXT: [[CONV38:%.*]] = fptrunc double [[CALL34]] to float
; CHECK-NEXT: ret float [[CONV38]]
diff --git a/llvm/test/Transforms/InstCombine/unordered-compare-and-ordered.ll b/llvm/test/Transforms/InstCombine/unordered-compare-and-ordered.ll
index ec015e8ad2aaa..46cbd04a36ffe 100644
--- a/llvm/test/Transforms/InstCombine/unordered-compare-and-ordered.ll
+++ b/llvm/test/Transforms/InstCombine/unordered-compare-and-ordered.ll
@@ -3,7 +3,7 @@
define i1 @fcmp_ord_and_uno(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_uno(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UNO:%.*]] = fcmp uno half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UNO]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -16,7 +16,7 @@ define i1 @fcmp_ord_and_uno(half %x, half %y) {
define i1 @fcmp_ord_and_ueq(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ueq(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -29,7 +29,7 @@ define i1 @fcmp_ord_and_ueq(half %x, half %y) {
define i1 @fcmp_ord_and_ugt(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ugt(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UGT:%.*]] = fcmp ugt half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UGT]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -42,7 +42,7 @@ define i1 @fcmp_ord_and_ugt(half %x, half %y) {
define i1 @fcmp_ord_and_uge(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_uge(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UGE:%.*]] = fcmp uge half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UGE]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -55,7 +55,7 @@ define i1 @fcmp_ord_and_uge(half %x, half %y) {
define i1 @fcmp_ord_and_ult(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ult(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[ULT:%.*]] = fcmp ult half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[ULT]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -68,7 +68,7 @@ define i1 @fcmp_ord_and_ult(half %x, half %y) {
define i1 @fcmp_ord_and_ule(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ule(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[ULE:%.*]] = fcmp ule half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[ULE]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -81,7 +81,7 @@ define i1 @fcmp_ord_and_ule(half %x, half %y) {
define i1 @fcmp_ord_and_une(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_une(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UNE:%.*]] = fcmp une half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UNE]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -119,7 +119,7 @@ define <2 x i1> @fcmp_ord_and_ueq_vector(<2 x half> %x, <2 x half> %y) {
; Negative test
define i1 @fcmp_ord_and_ueq_different_value0(half %x, half %y, half %z) {
; CHECK-LABEL: @fcmp_ord_and_ueq_different_value0(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[Z:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -133,7 +133,7 @@ define i1 @fcmp_ord_and_ueq_different_value0(half %x, half %y, half %z) {
; Negative test
define i1 @fcmp_ord_and_ueq_different_value1(half %x, half %y, half %z) {
; CHECK-LABEL: @fcmp_ord_and_ueq_different_value1(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[Y:%.*]], [[Z:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -150,7 +150,7 @@ define i1 @fcmp_ord_and_ueq_commute0() {
; CHECK-LABEL: @fcmp_ord_and_ueq_commute0(
; CHECK-NEXT: [[X:%.*]] = call half @foo()
; CHECK-NEXT: [[Y:%.*]] = call half @foo()
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[UEQ]], [[ORD]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -167,7 +167,7 @@ define i1 @fcmp_ord_and_ueq_commute1() {
; CHECK-LABEL: @fcmp_ord_and_ueq_commute1(
; CHECK-NEXT: [[X:%.*]] = call half @foo()
; CHECK-NEXT: [[Y:%.*]] = call half @foo()
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -182,7 +182,7 @@ define i1 @fcmp_ord_and_ueq_commute1() {
define i1 @fcmp_oeq_x_x_and_ult(half %x, half %y) {
; CHECK-LABEL: @fcmp_oeq_x_x_and_ult(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[ULT:%.*]] = fcmp ult half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[ULT]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -195,7 +195,7 @@ define i1 @fcmp_oeq_x_x_and_ult(half %x, half %y) {
define i1 @fcmp_ord_and_ueq_preserve_flags(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ueq_preserve_flags(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp nsz ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -208,7 +208,7 @@ define i1 @fcmp_ord_and_ueq_preserve_flags(half %x, half %y) {
define i1 @fcmp_ord_and_ueq_preserve_subset_flags0(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ueq_preserve_subset_flags0(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ninf nsz ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -221,7 +221,7 @@ define i1 @fcmp_ord_and_ueq_preserve_subset_flags0(half %x, half %y) {
define i1 @fcmp_ord_and_ueq_preserve_subset_flags1(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ueq_preserve_subset_flags1(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ninf nsz ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ninf nsz ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp nsz ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -234,7 +234,7 @@ define i1 @fcmp_ord_and_ueq_preserve_subset_flags1(half %x, half %y) {
define i1 @fcmp_ord_and_ueq_flags_lhs(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ueq_flags_lhs(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp nsz ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -247,7 +247,7 @@ define i1 @fcmp_ord_and_ueq_flags_lhs(half %x, half %y) {
define i1 @fcmp_ord_and_ueq_flags_rhs(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_ueq_flags_rhs(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp nsz ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -262,7 +262,7 @@ define i1 @fcmp_ord_and_ueq_flags_rhs(half %x, half %y) {
define i1 @fcmp_ord_and_fabs_ueq(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_fabs_ueq(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[FABS_X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -276,7 +276,7 @@ define i1 @fcmp_ord_and_fabs_ueq(half %x, half %y) {
define i1 @fcmp_ord_fabs_and_ueq(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_fabs_and_ueq(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -293,7 +293,7 @@ define i1 @fcmp_ord_and_fabs_ueq_commute0() {
; CHECK-NEXT: [[X:%.*]] = call half @foo()
; CHECK-NEXT: [[Y:%.*]] = call half @foo()
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[Y]], [[FABS_X]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -312,7 +312,7 @@ define i1 @fcmp_ord_and_fabs_ueq_commute1() {
; CHECK-NEXT: [[X:%.*]] = call half @foo()
; CHECK-NEXT: [[Y:%.*]] = call half @foo()
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[Y]], [[FABS_X]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[UEQ]], [[ORD]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -344,7 +344,7 @@ define <2 x i1> @fcmp_ord_and_fabs_ueq_vector(<2 x half> %x, <2 x half> %y) {
define i1 @fcmp_ord_fabs_and_fabs_ueq(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_fabs_and_fabs_ueq(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[FABS_X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -359,7 +359,7 @@ define i1 @fcmp_ord_fabs_and_fabs_ueq(half %x, half %y) {
define i1 @fcmp_ord_and_fneg_ueq(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_fneg_ueq(
; CHECK-NEXT: [[FNEG_X:%.*]] = fneg half [[X:%.*]]
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[Y:%.*]], [[FNEG_X]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -373,7 +373,7 @@ define i1 @fcmp_ord_and_fneg_ueq(half %x, half %y) {
define i1 @fcmp_ord_fneg_and_ueq(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_fneg_and_ueq(
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -388,7 +388,7 @@ define i1 @fcmp_ord_fneg_and_ueq(half %x, half %y) {
define i1 @fcmp_ord_fneg_and_fneg_ueq(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_fneg_and_fneg_ueq(
; CHECK-NEXT: [[FNEG_X:%.*]] = fneg half [[X:%.*]]
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[Y:%.*]], [[FNEG_X]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -404,7 +404,7 @@ define i1 @fcmp_ord_and_fneg_fabs_ueq(half %x, half %y) {
; CHECK-LABEL: @fcmp_ord_and_fneg_fabs_ueq(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
; CHECK-NEXT: [[FNEG_FABS_X:%.*]] = fneg half [[FABS_X]]
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[Y:%.*]], [[FNEG_FABS_X]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -420,7 +420,7 @@ define i1 @fcmp_ord_and_fneg_fabs_ueq(half %x, half %y) {
define i1 @fcmp_ord_and_copysign_ueq(half %x, half %y, half %z) {
; CHECK-LABEL: @fcmp_ord_and_copysign_ueq(
; CHECK-NEXT: [[COPYSIGN_X_Y:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Z:%.*]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[COPYSIGN_X_Y]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -435,7 +435,7 @@ define i1 @fcmp_ord_and_copysign_ueq(half %x, half %y, half %z) {
define i1 @fcmp_copysign_ord_and_ueq(half %x, half %y, half %z) {
; CHECK-LABEL: @fcmp_copysign_ord_and_ueq(
; CHECK-NEXT: [[COPYSIGN_X_Y:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Z:%.*]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[COPYSIGN_X_Y]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[COPYSIGN_X_Y]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[X]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -450,7 +450,7 @@ define i1 @fcmp_copysign_ord_and_ueq(half %x, half %y, half %z) {
define i1 @fcmp_ord_and_copysign_ueq_commute(half %x, half %y, half %z) {
; CHECK-LABEL: @fcmp_ord_and_copysign_ueq_commute(
; CHECK-NEXT: [[COPYSIGN_X_Y:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Z:%.*]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[Y:%.*]], [[COPYSIGN_X_Y]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -465,7 +465,7 @@ define i1 @fcmp_ord_and_copysign_ueq_commute(half %x, half %y, half %z) {
define i1 @fcmp_ord_and_copysign_fneg_ueq(half %x, half %y, half %z) {
; CHECK-LABEL: @fcmp_ord_and_copysign_fneg_ueq(
; CHECK-NEXT: [[COPYSIGN_X_Y:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Z:%.*]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[COPYSIGN_X_Y]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -482,7 +482,7 @@ define i1 @fcmp_ord_and_fneg_copysign_ueq(half %x, half %y, half %z) {
; CHECK-LABEL: @fcmp_ord_and_fneg_copysign_ueq(
; CHECK-NEXT: [[TMP1:%.*]] = fneg half [[Z:%.*]]
; CHECK-NEXT: [[FNEG_COPYSIGN:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[TMP1]])
-; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0.000000e+00
; CHECK-NEXT: [[UEQ:%.*]] = fcmp ueq half [[FNEG_COPYSIGN]], [[Y:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and i1 [[ORD]], [[UEQ]]
; CHECK-NEXT: ret i1 [[AND]]
diff --git a/llvm/test/Transforms/InstCombine/win-fdim.ll b/llvm/test/Transforms/InstCombine/win-fdim.ll
index a2e9de77cb58d..126175a0cb112 100644
--- a/llvm/test/Transforms/InstCombine/win-fdim.ll
+++ b/llvm/test/Transforms/InstCombine/win-fdim.ll
@@ -22,7 +22,7 @@ define float @fdim_float() {
;fdiml is not supported by windows
define fp128 @fdim_long() {
; MSVC19-LABEL: define fp128 @fdim_long() {
-; MSVC19-NEXT: [[DIM:%.*]] = call fp128 @fdiml(fp128 0xL00000000000000000000000000000000, fp128 0xL00000000000000000000000000000000)
+; MSVC19-NEXT: [[DIM:%.*]] = call fp128 @fdiml(fp128 0.000000e+00, fp128 0.000000e+00)
; MSVC19-NEXT: ret fp128 [[DIM]]
;
%dim = call fp128 @fdiml(fp128 0xL00000000000000000000000000000000 , fp128 0xL00000000000000000000000000000000)
diff --git a/llvm/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll b/llvm/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
index 9c364d16badee..db4c6040f8ab9 100644
--- a/llvm/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
+++ b/llvm/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
@@ -53,7 +53,7 @@ define i32 @test3(i32 %a, float %b) {
define i8 @test4(<8 x i8> %V) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[ADD:%.*]] = add <8 x i8> [[V:%.*]], bitcast (<1 x double> splat (double 0x319BEB8FD172E36) to <8 x i8>)
+; CHECK-NEXT: [[ADD:%.*]] = add <8 x i8> [[V:%.*]], bitcast (<1 x double> splat (double f0x0319BEB8FD172E36) to <8 x i8>)
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <8 x i8> [[ADD]], i32 6
; CHECK-NEXT: ret i8 [[EXTRACT]]
;
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/fract.ll b/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/fract.ll
index 73fc897748f64..bdb801732f758 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/fract.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/fract.ll
@@ -7,17 +7,17 @@ declare double @llvm.amdgcn.fract.f64(double)
define void @test_f16(ptr %p) {
; CHECK-LABEL: @test_f16(
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P:%.*]]
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH0000, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH3400, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH3B00, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH0400, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH3BFF, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH7E00, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH7E00, ptr [[P]]
-; CHECK-NEXT: store volatile half 0xH7E00, ptr [[P]]
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P:%.*]]
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]]
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]]
+; CHECK-NEXT: store volatile half 0.000000e+00, ptr [[P]]
+; CHECK-NEXT: store volatile half 2.500000e-01, ptr [[P]]
+; CHECK-NEXT: store volatile half 8.750000e-01, ptr [[P]]
+; CHECK-NEXT: store volatile half 6.103520e-05, ptr [[P]]
+; CHECK-NEXT: store volatile half 9.995110e-01, ptr [[P]]
+; CHECK-NEXT: store volatile half +qnan, ptr [[P]]
+; CHECK-NEXT: store volatile half +qnan, ptr [[P]]
+; CHECK-NEXT: store volatile half +qnan, ptr [[P]]
; CHECK-NEXT: ret void
;
%p0 = call half @llvm.amdgcn.fract.f16(half +0.0)
@@ -53,11 +53,11 @@ define void @test_f32(ptr %p) {
; CHECK-NEXT: store volatile float 0.000000e+00, ptr [[P]]
; CHECK-NEXT: store volatile float 2.500000e-01, ptr [[P]]
; CHECK-NEXT: store volatile float 8.750000e-01, ptr [[P]]
-; CHECK-NEXT: store volatile float 0x3810000000000000, ptr [[P]]
-; CHECK-NEXT: store volatile float 0x3FEFFFFFE0000000, ptr [[P]]
-; CHECK-NEXT: store volatile float 0x7FF8000000000000, ptr [[P]]
-; CHECK-NEXT: store volatile float 0x7FF8000000000000, ptr [[P]]
-; CHECK-NEXT: store volatile float 0x7FF8000000000000, ptr [[P]]
+; CHECK-NEXT: store volatile float f0x00800000, ptr [[P]]
+; CHECK-NEXT: store volatile float f0x3F7FFFFF, ptr [[P]]
+; CHECK-NEXT: store volatile float +qnan, ptr [[P]]
+; CHECK-NEXT: store volatile float +qnan, ptr [[P]]
+; CHECK-NEXT: store volatile float +qnan, ptr [[P]]
; CHECK-NEXT: ret void
;
%p0 = call float @llvm.amdgcn.fract.f32(float +0.0)
@@ -94,10 +94,10 @@ define void @test_f64(ptr %p) {
; CHECK-NEXT: store volatile double 2.500000e-01, ptr [[P]]
; CHECK-NEXT: store volatile double 8.750000e-01, ptr [[P]]
; CHECK-NEXT: store volatile double 2.000000e-308, ptr [[P]]
-; CHECK-NEXT: store volatile double 0x3FEFFFFFFFFFFFFF, ptr [[P]]
-; CHECK-NEXT: store volatile double 0x7FF8000000000000, ptr [[P]]
-; CHECK-NEXT: store volatile double 0x7FF8000000000000, ptr [[P]]
-; CHECK-NEXT: store volatile double 0x7FF8000000000000, ptr [[P]]
+; CHECK-NEXT: store volatile double f0x3FEFFFFFFFFFFFFF, ptr [[P]]
+; CHECK-NEXT: store volatile double +qnan, ptr [[P]]
+; CHECK-NEXT: store volatile double +qnan, ptr [[P]]
+; CHECK-NEXT: store volatile double +qnan, ptr [[P]]
; CHECK-NEXT: ret void
;
%p0 = call double @llvm.amdgcn.fract.f64(double +0.0)
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/WebAssembly/trunc.ll b/llvm/test/Transforms/InstSimplify/ConstProp/WebAssembly/trunc.ll
index 8a884928dad63..569ff21ce5d2e 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/WebAssembly/trunc.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/WebAssembly/trunc.ll
@@ -29,21 +29,21 @@ define void @test_i32_trunc_f32_s(ptr %p) {
; CHECK-NEXT: store volatile i32 -2, ptr [[P]], align 4
; CHECK-NEXT: store volatile i32 2147483520, ptr [[P]], align 4
; CHECK-NEXT: store volatile i32 -2147483648, ptr [[P]], align 4
-; CHECK-NEXT: [[T14:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float 0x41E0000000000000)
+; CHECK-NEXT: [[T14:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float f0x4F000000)
; CHECK-NEXT: store volatile i32 [[T14]], ptr [[P]], align 4
-; CHECK-NEXT: [[T15:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float 0xC1E0000020000000)
+; CHECK-NEXT: [[T15:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float f0xCF000001)
; CHECK-NEXT: store volatile i32 [[T15]], ptr [[P]], align 4
-; CHECK-NEXT: [[T16:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[T16:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float +inf)
; CHECK-NEXT: store volatile i32 [[T16]], ptr [[P]], align 4
-; CHECK-NEXT: [[T17:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[T17:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float -inf)
; CHECK-NEXT: store volatile i32 [[T17]], ptr [[P]], align 4
-; CHECK-NEXT: [[T18:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[T18:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float +qnan)
; CHECK-NEXT: store volatile i32 [[T18]], ptr [[P]], align 4
-; CHECK-NEXT: [[T19:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float 0x7FFA000000000000)
+; CHECK-NEXT: [[T19:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float +nan(0x100000))
; CHECK-NEXT: store volatile i32 [[T19]], ptr [[P]], align 4
-; CHECK-NEXT: [[T20:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float 0xFFF8000000000000)
+; CHECK-NEXT: [[T20:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float -qnan)
; CHECK-NEXT: store volatile i32 [[T20]], ptr [[P]], align 4
-; CHECK-NEXT: [[T21:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float 0xFFFA000000000000)
+; CHECK-NEXT: [[T21:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f32(float -nan(0x100000))
; CHECK-NEXT: store volatile i32 [[T21]], ptr [[P]], align 4
; CHECK-NEXT: ret void
;
@@ -109,21 +109,21 @@ define void @test_i32_trunc_f32_u(ptr %p) {
; CHECK-NEXT: store volatile i32 -256, ptr [[P]], align 4
; CHECK-NEXT: store volatile i32 0, ptr [[P]], align 4
; CHECK-NEXT: store volatile i32 0, ptr [[P]], align 4
-; CHECK-NEXT: [[T13:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float 0x41F0000000000000)
+; CHECK-NEXT: [[T13:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float f0x4F800000)
; CHECK-NEXT: store volatile i32 [[T13]], ptr [[P]], align 4
; CHECK-NEXT: [[T14:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float -1.000000e+00)
; CHECK-NEXT: store volatile i32 [[T14]], ptr [[P]], align 4
-; CHECK-NEXT: [[T15:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[T15:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float +inf)
; CHECK-NEXT: store volatile i32 [[T15]], ptr [[P]], align 4
-; CHECK-NEXT: [[T16:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[T16:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float -inf)
; CHECK-NEXT: store volatile i32 [[T16]], ptr [[P]], align 4
-; CHECK-NEXT: [[T17:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[T17:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float +qnan)
; CHECK-NEXT: store volatile i32 [[T17]], ptr [[P]], align 4
-; CHECK-NEXT: [[T18:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float 0x7FFA000000000000)
+; CHECK-NEXT: [[T18:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float +nan(0x100000))
; CHECK-NEXT: store volatile i32 [[T18]], ptr [[P]], align 4
-; CHECK-NEXT: [[T19:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float 0xFFF8000000000000)
+; CHECK-NEXT: [[T19:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float -qnan)
; CHECK-NEXT: store volatile i32 [[T19]], ptr [[P]], align 4
-; CHECK-NEXT: [[T20:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float 0xFFFA000000000000)
+; CHECK-NEXT: [[T20:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f32(float -nan(0x100000))
; CHECK-NEXT: store volatile i32 [[T20]], ptr [[P]], align 4
; CHECK-NEXT: ret void
;
@@ -190,21 +190,21 @@ define void @test_i32_trunc_f64_s(ptr %p) {
; CHECK-NEXT: store volatile i32 -2147483648, ptr [[P]], align 4
; CHECK-NEXT: store volatile i32 -2147483648, ptr [[P]], align 4
; CHECK-NEXT: store volatile i32 2147483647, ptr [[P]], align 4
-; CHECK-NEXT: [[T16:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double 0x41E0000000000000)
+; CHECK-NEXT: [[T16:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double f0x41E0000000000000)
; CHECK-NEXT: store volatile i32 [[T16]], ptr [[P]], align 4
-; CHECK-NEXT: [[T17:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double 0xC1E0000000200000)
+; CHECK-NEXT: [[T17:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double f0xC1E0000000200000)
; CHECK-NEXT: store volatile i32 [[T17]], ptr [[P]], align 4
-; CHECK-NEXT: [[T18:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[T18:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double +inf)
; CHECK-NEXT: store volatile i32 [[T18]], ptr [[P]], align 4
-; CHECK-NEXT: [[T19:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[T19:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double -inf)
; CHECK-NEXT: store volatile i32 [[T19]], ptr [[P]], align 4
-; CHECK-NEXT: [[T20:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[T20:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double +qnan)
; CHECK-NEXT: store volatile i32 [[T20]], ptr [[P]], align 4
-; CHECK-NEXT: [[T21:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double 0x7FF4000000000000)
+; CHECK-NEXT: [[T21:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double +snan(0x4000000000000))
; CHECK-NEXT: store volatile i32 [[T21]], ptr [[P]], align 4
-; CHECK-NEXT: [[T22:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double 0xFFF8000000000000)
+; CHECK-NEXT: [[T22:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double -qnan)
; CHECK-NEXT: store volatile i32 [[T22]], ptr [[P]], align 4
-; CHECK-NEXT: [[T23:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double 0x7FF4000000000000)
+; CHECK-NEXT: [[T23:%.*]] = call i32 @llvm.wasm.trunc.signed.i32.f64(double +snan(0x4000000000000))
; CHECK-NEXT: store volatile i32 [[T23]], ptr [[P]], align 4
; CHECK-NEXT: ret void
;
@@ -276,7 +276,7 @@ define void @test_i32_trunc_f64_u(ptr %p) {
; CHECK-NEXT: store volatile i32 0, ptr [[P]], align 4
; CHECK-NEXT: store volatile i32 100000000, ptr [[P]], align 4
; CHECK-NEXT: store volatile i32 -1, ptr [[P]], align 4
-; CHECK-NEXT: [[T15:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 0x41F0000000000000)
+; CHECK-NEXT: [[T15:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double f0x41F0000000000000)
; CHECK-NEXT: store volatile i32 [[T15]], ptr [[P]], align 4
; CHECK-NEXT: [[T16:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double -1.000000e+00)
; CHECK-NEXT: store volatile i32 [[T16]], ptr [[P]], align 4
@@ -284,19 +284,19 @@ define void @test_i32_trunc_f64_u(ptr %p) {
; CHECK-NEXT: store volatile i32 [[T17]], ptr [[P]], align 4
; CHECK-NEXT: [[T18:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 1.000000e+30)
; CHECK-NEXT: store volatile i32 [[T18]], ptr [[P]], align 4
-; CHECK-NEXT: [[T19:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 0x43E0000000000000)
+; CHECK-NEXT: [[T19:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double f0x43E0000000000000)
; CHECK-NEXT: store volatile i32 [[T19]], ptr [[P]], align 4
-; CHECK-NEXT: [[T20:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[T20:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double +inf)
; CHECK-NEXT: store volatile i32 [[T20]], ptr [[P]], align 4
-; CHECK-NEXT: [[T21:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[T21:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double -inf)
; CHECK-NEXT: store volatile i32 [[T21]], ptr [[P]], align 4
-; CHECK-NEXT: [[T22:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[T22:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double +qnan)
; CHECK-NEXT: store volatile i32 [[T22]], ptr [[P]], align 4
-; CHECK-NEXT: [[T23:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 0x7FF4000000000000)
+; CHECK-NEXT: [[T23:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double +snan(0x4000000000000))
; CHECK-NEXT: store volatile i32 [[T23]], ptr [[P]], align 4
-; CHECK-NEXT: [[T24:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 0xFFF8000000000000)
+; CHECK-NEXT: [[T24:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double -qnan)
; CHECK-NEXT: store volatile i32 [[T24]], ptr [[P]], align 4
-; CHECK-NEXT: [[T25:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double 0xFFF4000000000000)
+; CHECK-NEXT: [[T25:%.*]] = call i32 @llvm.wasm.trunc.unsigned.i32.f64(double -snan(0x4000000000000))
; CHECK-NEXT: store volatile i32 [[T25]], ptr [[P]], align 4
; CHECK-NEXT: ret void
;
@@ -373,21 +373,21 @@ define void @test_i64_trunc_f32_s(ptr %p) {
; CHECK-NEXT: store volatile i64 -4294967296, ptr [[P]], align 8
; CHECK-NEXT: store volatile i64 9223371487098961920, ptr [[P]], align 8
; CHECK-NEXT: store volatile i64 -9223372036854775808, ptr [[P]], align 8
-; CHECK-NEXT: [[T16:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float 0x43E0000000000000)
+; CHECK-NEXT: [[T16:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float f0x5F000000)
; CHECK-NEXT: store volatile i64 [[T16]], ptr [[P]], align 8
-; CHECK-NEXT: [[T17:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float 0xC3E0000020000000)
+; CHECK-NEXT: [[T17:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float f0xDF000001)
; CHECK-NEXT: store volatile i64 [[T17]], ptr [[P]], align 8
-; CHECK-NEXT: [[T18:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[T18:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float +inf)
; CHECK-NEXT: store volatile i64 [[T18]], ptr [[P]], align 8
-; CHECK-NEXT: [[T19:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[T19:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float -inf)
; CHECK-NEXT: store volatile i64 [[T19]], ptr [[P]], align 8
-; CHECK-NEXT: [[T20:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[T20:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float +qnan)
; CHECK-NEXT: store volatile i64 [[T20]], ptr [[P]], align 8
-; CHECK-NEXT: [[T21:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float 0x7FFA000000000000)
+; CHECK-NEXT: [[T21:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float +nan(0x100000))
; CHECK-NEXT: store volatile i64 [[T21]], ptr [[P]], align 8
-; CHECK-NEXT: [[T22:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float 0xFFF8000000000000)
+; CHECK-NEXT: [[T22:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float -qnan)
; CHECK-NEXT: store volatile i64 [[T22]], ptr [[P]], align 8
-; CHECK-NEXT: [[T23:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float 0xFFFA000000000000)
+; CHECK-NEXT: [[T23:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f32(float -nan(0x100000))
; CHECK-NEXT: store volatile i64 [[T23]], ptr [[P]], align 8
; CHECK-NEXT: ret void
;
@@ -455,21 +455,21 @@ define void @test_i64_trunc_f32_u(ptr %p) {
; CHECK-NEXT: store volatile i64 -1099511627776, ptr [[P]], align 8
; CHECK-NEXT: store volatile i64 0, ptr [[P]], align 8
; CHECK-NEXT: store volatile i64 0, ptr [[P]], align 8
-; CHECK-NEXT: [[T11:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float 0x43F0000000000000)
+; CHECK-NEXT: [[T11:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float f0x5F800000)
; CHECK-NEXT: store volatile i64 [[T11]], ptr [[P]], align 8
; CHECK-NEXT: [[T12:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float -1.000000e+00)
; CHECK-NEXT: store volatile i64 [[T12]], ptr [[P]], align 8
-; CHECK-NEXT: [[T13:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[T13:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float +inf)
; CHECK-NEXT: store volatile i64 [[T13]], ptr [[P]], align 8
-; CHECK-NEXT: [[T14:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[T14:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float -inf)
; CHECK-NEXT: store volatile i64 [[T14]], ptr [[P]], align 8
-; CHECK-NEXT: [[T15:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[T15:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float +qnan)
; CHECK-NEXT: store volatile i64 [[T15]], ptr [[P]], align 8
-; CHECK-NEXT: [[T16:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float 0x7FFA000000000000)
+; CHECK-NEXT: [[T16:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float +nan(0x100000))
; CHECK-NEXT: store volatile i64 [[T16]], ptr [[P]], align 8
-; CHECK-NEXT: [[T17:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float 0xFFF8000000000000)
+; CHECK-NEXT: [[T17:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float -qnan)
; CHECK-NEXT: store volatile i64 [[T17]], ptr [[P]], align 8
-; CHECK-NEXT: [[T18:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float 0xFFFA000000000000)
+; CHECK-NEXT: [[T18:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f32(float -nan(0x100000))
; CHECK-NEXT: store volatile i64 [[T18]], ptr [[P]], align 8
; CHECK-NEXT: ret void
;
@@ -532,21 +532,21 @@ define void @test_i64_trunc_f64_s(ptr %p) {
; CHECK-NEXT: store volatile i64 -4294967296, ptr [[P]], align 8
; CHECK-NEXT: store volatile i64 9223372036854774784, ptr [[P]], align 8
; CHECK-NEXT: store volatile i64 -9223372036854775808, ptr [[P]], align 8
-; CHECK-NEXT: [[T16:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double 0x43E0000000000000)
+; CHECK-NEXT: [[T16:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double f0x43E0000000000000)
; CHECK-NEXT: store volatile i64 [[T16]], ptr [[P]], align 8
-; CHECK-NEXT: [[T17:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double 0xC3E0000000000001)
+; CHECK-NEXT: [[T17:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double f0xC3E0000000000001)
; CHECK-NEXT: store volatile i64 [[T17]], ptr [[P]], align 8
-; CHECK-NEXT: [[T18:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[T18:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double +inf)
; CHECK-NEXT: store volatile i64 [[T18]], ptr [[P]], align 8
-; CHECK-NEXT: [[T19:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[T19:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double -inf)
; CHECK-NEXT: store volatile i64 [[T19]], ptr [[P]], align 8
-; CHECK-NEXT: [[T20:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[T20:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double +qnan)
; CHECK-NEXT: store volatile i64 [[T20]], ptr [[P]], align 8
-; CHECK-NEXT: [[T21:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double 0x7FF4000000000000)
+; CHECK-NEXT: [[T21:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double +snan(0x4000000000000))
; CHECK-NEXT: store volatile i64 [[T21]], ptr [[P]], align 8
-; CHECK-NEXT: [[T22:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double 0xFFF8000000000000)
+; CHECK-NEXT: [[T22:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double -qnan)
; CHECK-NEXT: store volatile i64 [[T22]], ptr [[P]], align 8
-; CHECK-NEXT: [[T23:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double 0x7FF4000000000000)
+; CHECK-NEXT: [[T23:%.*]] = call i64 @llvm.wasm.trunc.signed.i64.f64(double +snan(0x4000000000000))
; CHECK-NEXT: store volatile i64 [[T23]], ptr [[P]], align 8
; CHECK-NEXT: ret void
;
@@ -618,21 +618,21 @@ define void @test_i64_trunc_f64_u(ptr %p) {
; CHECK-NEXT: store volatile i64 100000000, ptr [[P]], align 8
; CHECK-NEXT: store volatile i64 10000000000000000, ptr [[P]], align 8
; CHECK-NEXT: store volatile i64 -9223372036854775808, ptr [[P]], align 8
-; CHECK-NEXT: [[T15:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double 0x43F0000000000000)
+; CHECK-NEXT: [[T15:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double f0x43F0000000000000)
; CHECK-NEXT: store volatile i64 [[T15]], ptr [[P]], align 8
; CHECK-NEXT: [[T16:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double -1.000000e+00)
; CHECK-NEXT: store volatile i64 [[T16]], ptr [[P]], align 8
-; CHECK-NEXT: [[T17:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[T17:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double +inf)
; CHECK-NEXT: store volatile i64 [[T17]], ptr [[P]], align 8
-; CHECK-NEXT: [[T18:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[T18:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double -inf)
; CHECK-NEXT: store volatile i64 [[T18]], ptr [[P]], align 8
-; CHECK-NEXT: [[T19:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[T19:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double +qnan)
; CHECK-NEXT: store volatile i64 [[T19]], ptr [[P]], align 8
-; CHECK-NEXT: [[T20:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double 0x7FF4000000000000)
+; CHECK-NEXT: [[T20:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double +snan(0x4000000000000))
; CHECK-NEXT: store volatile i64 [[T20]], ptr [[P]], align 8
-; CHECK-NEXT: [[T21:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double 0xFFF8000000000000)
+; CHECK-NEXT: [[T21:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double -qnan)
; CHECK-NEXT: store volatile i64 [[T21]], ptr [[P]], align 8
-; CHECK-NEXT: [[T22:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double 0xFFF4000000000000)
+; CHECK-NEXT: [[T22:%.*]] = call i64 @llvm.wasm.trunc.unsigned.i64.f64(double -snan(0x4000000000000))
; CHECK-NEXT: store volatile i64 [[T22]], ptr [[P]], align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/atan-intrinsic.ll b/llvm/test/Transforms/InstSimplify/ConstProp/atan-intrinsic.ll
index 3cb6290b1a808..0d70afda8c2b8 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/atan-intrinsic.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/atan-intrinsic.ll
@@ -11,7 +11,7 @@ define double @test_atan_0() {
define double @test_atan_one() {
; CHECK-LABEL: define double @test_atan_one() {
-; CHECK-NEXT: ret double 0x3FE921FB54442D18
+; CHECK-NEXT: ret double f0x3FE921FB54442D18
;
%res = call double @llvm.atan.f64(double 1.0)
ret double %res
@@ -52,7 +52,7 @@ define double @test_atan_undef() {
define double @test_atan_snan() {
; CHECK-LABEL: define double @test_atan_snan() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.atan.f64(double 0x7FF0000000000001)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.atan.f64(double +snan(0x1))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.atan.f64(double 0x7ff0000000000001)
@@ -61,7 +61,7 @@ define double @test_atan_snan() {
define double @test_atan_qnan() {
; CHECK-LABEL: define double @test_atan_qnan() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.atan.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.atan.f64(double +qnan)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.atan.f64(double 0x7ff8000000000000)
@@ -70,7 +70,7 @@ define double @test_atan_qnan() {
define double @test_atan_pos_inf() {
; CHECK-LABEL: define double @test_atan_pos_inf() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.atan.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.atan.f64(double +inf)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.atan.f64(double 0x7ff0000000000000)
@@ -79,7 +79,7 @@ define double @test_atan_pos_inf() {
define double @test_atan_neg_inf() {
; CHECK-LABEL: define double @test_atan_neg_inf() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.atan.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.atan.f64(double -inf)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.atan.f64(double 0xfff0000000000000)
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/calls.ll b/llvm/test/Transforms/InstSimplify/ConstProp/calls.ll
index 2fd3880f4b278..aca5d94874543 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/calls.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/calls.ll
@@ -197,7 +197,7 @@ define float @test_intrinsic_pow_f32_overflow() nounwind uwtable ssp {
entry:
; CHECK-LABEL: @test_intrinsic_pow_f32_overflow(
; CHECK-NOT: call
-; CHECK: ret float 0x7FF0000000000000
+; CHECK: ret float +inf
%0 = call float @llvm.pow.f32(float 40.0, float 50.0)
ret float %0
}
@@ -222,19 +222,19 @@ entry:
; log(0.0) -> -inf
; CHECK-NOT: call
-; CHECK: store float 0xFFF0000000000000
+; CHECK: store float -inf
%1 = call float @llvm.log.f32(float 0.0)
store float %1, ptr %f
; log(-0.0) -> -inf
; CHECK-NOT: call
-; CHECK: store float 0xFFF0000000000000
+; CHECK: store float -inf
%2 = call float @llvm.log.f32(float -0.0)
store float %2, ptr %f
; log(-x) -> NaN
; CHECK-NOT: call
-; CHECK: store float 0x7FF8000000000000
+; CHECK: store float +qnan
%3 = call float @llvm.log.f32(float -20.0)
store float %3, ptr %f
@@ -245,7 +245,7 @@ entry:
store float %4, ptr %f
; CHECK-NOT: call
-; CHECK: store <3 x float> <float 0xFFF0000000000000, float 0x7FF8000000000000, float 0.000000e+00>
+; CHECK: store <3 x float> <float -inf, float +qnan, float 0.000000e+00>
%5 = call <3 x float> @llvm.log.v4f32(<3 x float> <float 0.0, float -6.0, float 1.0>)
store <3 x float> %5, ptr %v
@@ -259,17 +259,17 @@ entry:
%f = alloca float
; log2(0.0) -> -inf
-; CHECK: store float 0xFFF0000000000000
+; CHECK: store float -inf
%1 = call float @llvm.log2.f32(float 0.0)
store float %1, ptr %f
; log2(-0.0) -> -inf
-; CHECK: store float 0xFFF0000000000000
+; CHECK: store float -inf
%2 = call float @llvm.log2.f32(float -0.0)
store float %2, ptr %f
; log2(-x) -> NaN
-; CHECK: store float 0x7FF8000000000000
+; CHECK: store float +qnan
%3 = call float @llvm.log2.f32(float -20.0)
store float %3, ptr %f
@@ -278,7 +278,7 @@ entry:
%4 = call float @llvm.log2.f32(float 1.0)
store float %4, ptr %f
-; CHECK: store <3 x float> <float 0xFFF0000000000000, float 0x7FF8000000000000, float 0.000000e+00>
+; CHECK: store <3 x float> <float -inf, float +qnan, float 0.000000e+00>
%5 = call <3 x float> @llvm.log2.v4f32(<3 x float> <float 0.0, float -6.0, float 1.0>)
store <3 x float> %5, ptr %v
@@ -292,17 +292,17 @@ entry:
%f = alloca float
; log10(0.0) -> -inf
-; CHECK: store float 0xFFF0000000000000
+; CHECK: store float -inf
%1 = call float @llvm.log10.f32(float 0.0)
store float %1, ptr %f
; log10(-0.0) -> -inf
-; CHECK: store float 0xFFF0000000000000
+; CHECK: store float -inf
%2 = call float @llvm.log10.f32(float -0.0)
store float %2, ptr %f
; log10(-x) -> NaN
-; CHECK: store float 0x7FF8000000000000
+; CHECK: store float +qnan
%3 = call float @llvm.log10.f32(float -20.0)
store float %3, ptr %f
@@ -311,7 +311,7 @@ entry:
%4 = call float @llvm.log10.f32(float 1.0)
store float %4, ptr %f
-; CHECK: store <3 x float> <float 0xFFF0000000000000, float 0x7FF8000000000000, float 0.000000e+00>
+; CHECK: store <3 x float> <float -inf, float +qnan, float 0.000000e+00>
%5 = call <3 x float> @llvm.log10.v3f32(<3 x float> <float 0.0, float -6.0, float 1.0>)
store <3 x float> %5, ptr %v
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/cast.ll b/llvm/test/Transforms/InstSimplify/ConstProp/cast.ll
index b51f061d7918c..e04c4710b2b0f 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/cast.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/cast.ll
@@ -25,7 +25,7 @@ define i8 @overflow_fptoui() {
define float @overflow_uitofp() {
; CHECK-LABEL: @overflow_uitofp(
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%i = uitofp i130 400000000000000000000000000000000000000 to float
ret float %i
@@ -33,7 +33,7 @@ define float @overflow_uitofp() {
define float @overflow_sitofp() {
; CHECK-LABEL: @overflow_sitofp(
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%i = sitofp i130 400000000000000000000000000000000000000 to float
ret float %i
@@ -44,7 +44,7 @@ define float @overflow_sitofp() {
define float @nan_f64_trunc() {
; CHECK-LABEL: @nan_f64_trunc(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%f = fptrunc double 0x7FF0000000000001 to float
ret float %f
@@ -57,7 +57,7 @@ define float @nan_f64_trunc() {
define <3 x half> @nan_v3f64_trunc() {
; CHECK-LABEL: @nan_v3f64_trunc(
-; CHECK-NEXT: ret <3 x half> splat (half 0xH7E00)
+; CHECK-NEXT: ret <3 x half> splat (half +qnan)
;
%f = fptrunc <3 x double> <double 0x7FF0020000000000, double 0x7FF003FFFFFFFFFF, double 0x7FF8000000000001> to <3 x half>
ret <3 x half> %f
@@ -65,7 +65,7 @@ define <3 x half> @nan_v3f64_trunc() {
define bfloat @nan_bf16_trunc() {
; CHECK-LABEL: @nan_bf16_trunc(
-; CHECK-NEXT: ret bfloat 0xR7FC0
+; CHECK-NEXT: ret bfloat +qnan
;
%f = fptrunc double 0x7FF0000000000001 to bfloat
ret bfloat %f
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/convert-from-fp16.ll b/llvm/test/Transforms/InstSimplify/ConstProp/convert-from-fp16.ll
index 2c1b5f0a6a4cb..16ed8b6e03012 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/convert-from-fp16.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/convert-from-fp16.ll
@@ -22,7 +22,7 @@ define double @fold_from_fp16_to_fp64() {
define x86_fp80 @fold_from_fp16_to_fp80() {
; CHECK-LABEL: @fold_from_fp16_to_fp80(
-; CHECK-NEXT: ret x86_fp80 0xK00000000000000000000
+; CHECK-NEXT: ret x86_fp80 0.000000e+00
;
%r = call x86_fp80 @llvm.convert.from.fp16.f80(i16 0)
ret x86_fp80 %r
@@ -30,7 +30,7 @@ define x86_fp80 @fold_from_fp16_to_fp80() {
define fp128 @fold_from_fp16_to_fp128() {
; CHECK-LABEL: @fold_from_fp16_to_fp128(
-; CHECK-NEXT: ret fp128 0xL00000000000000000000000000000000
+; CHECK-NEXT: ret fp128 0.000000e+00
;
%r = call fp128 @llvm.convert.from.fp16.f128(i16 0)
ret fp128 %r
@@ -38,7 +38,7 @@ define fp128 @fold_from_fp16_to_fp128() {
define ppc_fp128 @fold_from_fp16_to_ppcfp128() {
; CHECK-LABEL: @fold_from_fp16_to_ppcfp128(
-; CHECK-NEXT: ret ppc_fp128 0xM00000000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 0.000000e+00
;
%r = call ppc_fp128 @llvm.convert.from.fp16.ppcf128(i16 0)
ret ppc_fp128 %r
@@ -64,7 +64,7 @@ define double @fold_from_fp16_to_fp64_b() {
define x86_fp80 @fold_from_fp16_to_fp80_b() {
; CHECK-LABEL: @fold_from_fp16_to_fp80_b(
-; CHECK-NEXT: ret x86_fp80 0xK40018000000000000000
+; CHECK-NEXT: ret x86_fp80 4.000000e+00
;
%a = call i16 @llvm.convert.to.fp16.f64(double 4.0)
%r = call x86_fp80 @llvm.convert.from.fp16.f80(i16 %a)
@@ -73,7 +73,7 @@ define x86_fp80 @fold_from_fp16_to_fp80_b() {
define fp128 @fold_from_fp16_to_fp128_b() {
; CHECK-LABEL: @fold_from_fp16_to_fp128_b(
-; CHECK-NEXT: ret fp128 0xL00000000000000004001000000000000
+; CHECK-NEXT: ret fp128 4.000000e+00
;
%a = call i16 @llvm.convert.to.fp16.f64(double 4.0)
%r = call fp128 @llvm.convert.from.fp16.f128(i16 %a)
@@ -82,7 +82,7 @@ define fp128 @fold_from_fp16_to_fp128_b() {
define ppc_fp128 @fold_from_fp16_to_ppcfp128_b() {
; CHECK-LABEL: @fold_from_fp16_to_ppcfp128_b(
-; CHECK-NEXT: ret ppc_fp128 0xM40100000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 4.000000e+00
;
%a = call i16 @llvm.convert.to.fp16.f64(double 4.0)
%r = call ppc_fp128 @llvm.convert.from.fp16.ppcf128(i16 %a)
@@ -94,7 +94,7 @@ define ppc_fp128 @fold_from_fp16_to_ppcfp128_b() {
define float @convert_snan() {
; CHECK-LABEL: @convert_snan(
-; CHECK-NEXT: ret float 0x7FF8040000000000
+; CHECK-NEXT: ret float +nan(0x2000)
;
%r = call float @llvm.convert.from.fp16.f32(i16 31745) ; 0x7c01
ret float %r
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/copysign.ll b/llvm/test/Transforms/InstSimplify/ConstProp/copysign.ll
index 051cb84fd0daf..da2dc138d8656 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/copysign.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/copysign.ll
@@ -57,7 +57,7 @@ define double @f64_03() {
define bfloat @bf16_01() {
; CHECK-LABEL: @bf16_01(
-; CHECK-NEXT: ret bfloat 0xRBF80
+; CHECK-NEXT: ret bfloat -1.000000e+00
;
%x = call bfloat @llvm.copysign.bf16(bfloat 1.0, bfloat -2.0)
ret bfloat %x
@@ -65,7 +65,7 @@ define bfloat @bf16_01() {
define bfloat @bf16_02() {
; CHECK-LABEL: @bf16_02(
-; CHECK-NEXT: ret bfloat 0xR4000
+; CHECK-NEXT: ret bfloat 2.000000e+00
;
%x = call bfloat @llvm.copysign.bf16(bfloat -2.0, bfloat 1.0)
ret bfloat %x
@@ -73,7 +73,7 @@ define bfloat @bf16_02() {
define bfloat @bf16_03() {
; CHECK-LABEL: @bf16_03(
-; CHECK-NEXT: ret bfloat 0xRC000
+; CHECK-NEXT: ret bfloat -2.000000e+00
;
%x = call bfloat @llvm.copysign.bf16(bfloat -2.0, bfloat -1.0)
ret bfloat %x
@@ -81,7 +81,7 @@ define bfloat @bf16_03() {
define fp128 @f128_01() {
; CHECK-LABEL: @f128_01(
-; CHECK-NEXT: ret fp128 0xL00000000000000008000000000000001
+; CHECK-NEXT: ret fp128 f0x80000000000000010000000000000000
;
%x = call fp128 @llvm.copysign.f128(fp128 0xL00000000000000000000000000000001, fp128 0xL00000000000000008000000000000002)
ret fp128 %x
@@ -89,7 +89,7 @@ define fp128 @f128_01() {
define fp128 @f128_02() {
; CHECK-LABEL: @f128_02(
-; CHECK-NEXT: ret fp128 0xL00000000000000000000000000000003
+; CHECK-NEXT: ret fp128 f0x00000000000000030000000000000000
;
%x = call fp128 @llvm.copysign.f128(fp128 0xL00000000000000008000000000000003, fp128 0xL00000000000000000000000000000004)
ret fp128 %x
@@ -97,7 +97,7 @@ define fp128 @f128_02() {
define fp128 @f128_03() {
; CHECK-LABEL: @f128_03(
-; CHECK-NEXT: ret fp128 0xL00000000000000008000000000000005
+; CHECK-NEXT: ret fp128 f0x80000000000000050000000000000000
;
%x = call fp128 @llvm.copysign.f128(fp128 0xL00000000000000008000000000000005, fp128 0xL00000000000000008000000000000006)
ret fp128 %x
@@ -105,7 +105,7 @@ define fp128 @f128_03() {
define ppc_fp128 @ppc128_01() {
; CHECK-LABEL: @ppc128_01(
-; CHECK-NEXT: ret ppc_fp128 0xM80000000000000008000000000000001
+; CHECK-NEXT: ret ppc_fp128 f0x80000000000000018000000000000000
;
%x = call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xM00000000000000000000000000000001, ppc_fp128 0xM80000000000000000000000000000002)
ret ppc_fp128 %x
@@ -113,7 +113,7 @@ define ppc_fp128 @ppc128_01() {
define ppc_fp128 @ppc128_02() {
; CHECK-LABEL: @ppc128_02(
-; CHECK-NEXT: ret ppc_fp128 0xM00000000000000008000000000000003
+; CHECK-NEXT: ret ppc_fp128 f0x80000000000000030000000000000000
;
%x = call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xM80000000000000000000000000000003, ppc_fp128 0xM00000000000000000000000000000004)
ret ppc_fp128 %x
@@ -121,7 +121,7 @@ define ppc_fp128 @ppc128_02() {
define ppc_fp128 @ppc128_03() {
; CHECK-LABEL: @ppc128_03(
-; CHECK-NEXT: ret ppc_fp128 0xM80000000000000000000000000000005
+; CHECK-NEXT: ret ppc_fp128 f0x00000000000000058000000000000000
;
%x = call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xM80000000000000000000000000000005, ppc_fp128 0xM80000000000000000000000000000006)
ret ppc_fp128 %x
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/fma.ll b/llvm/test/Transforms/InstSimplify/ConstProp/fma.ll
index 2f56c2df0ca8f..7b40f34cbabe6 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/fma.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/fma.ll
@@ -36,7 +36,7 @@ define double @test_all_finite() {
; Test builtin fma with a +/-NaN addend.
define double @test_NaN_addend() {
; CHECK-LABEL: @test_NaN_addend(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 7.0, double 8.0, double 0x7FF8000000000000)
ret double %1
@@ -44,7 +44,7 @@ define double @test_NaN_addend() {
define double @test_NaN_addend_2() {
; CHECK-LABEL: @test_NaN_addend_2(
-; CHECK-NEXT: ret double 0xFFF8000000000000
+; CHECK-NEXT: ret double -qnan
;
%1 = call double @llvm.fma.f64(double 7.0, double 8.0, double 0xFFF8000000000000)
ret double %1
@@ -53,7 +53,7 @@ define double @test_NaN_addend_2() {
; Test builtin fma with a +/-Inf addend.
define double @test_Inf_addend() {
; CHECK-LABEL: @test_Inf_addend(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%1 = call double @llvm.fma.f64(double 7.0, double 8.0, double 0x7FF0000000000000)
ret double %1
@@ -61,7 +61,7 @@ define double @test_Inf_addend() {
define double @test_Inf_addend_2() {
; CHECK-LABEL: @test_Inf_addend_2(
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%1 = call double @llvm.fma.f64(double 7.0, double 8.0, double 0xFFF0000000000000)
ret double %1
@@ -70,7 +70,7 @@ define double @test_Inf_addend_2() {
; Test builtin fma with one of the operands to the multiply being +/-NaN.
define double @test_NaN_1() {
; CHECK-LABEL: @test_NaN_1(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0x7FF8000000000000, double 8.0, double 0.0)
ret double %1
@@ -78,7 +78,7 @@ define double @test_NaN_1() {
define double @test_NaN_2() {
; CHECK-LABEL: @test_NaN_2(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 7.0, double 0x7FF8000000000000, double 0.0)
ret double %1
@@ -86,7 +86,7 @@ define double @test_NaN_2() {
define double @test_NaN_3() {
; CHECK-LABEL: @test_NaN_3(
-; CHECK-NEXT: ret double 0xFFF8000000000000
+; CHECK-NEXT: ret double -qnan
;
%1 = call double @llvm.fma.f64(double 0xFFF8000000000000, double 8.0, double 0.0)
ret double %1
@@ -94,7 +94,7 @@ define double @test_NaN_3() {
define double @test_NaN_4() {
; CHECK-LABEL: @test_NaN_4(
-; CHECK-NEXT: ret double 0xFFF8000000000000
+; CHECK-NEXT: ret double -qnan
;
%1 = call double @llvm.fma.f64(double 7.0, double 0xFFF8000000000000, double 0.0)
ret double %1
@@ -103,7 +103,7 @@ define double @test_NaN_4() {
; Test builtin fma with one of the operands to the multiply being +/-Inf.
define double @test_Inf_1() {
; CHECK-LABEL: @test_Inf_1(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%1 = call double @llvm.fma.f64(double 0x7FF0000000000000, double 8.0, double 0.0)
ret double %1
@@ -111,7 +111,7 @@ define double @test_Inf_1() {
define double @test_Inf_2() {
; CHECK-LABEL: @test_Inf_2(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%1 = call double @llvm.fma.f64(double 7.0, double 0x7FF0000000000000, double 0.0)
ret double %1
@@ -119,7 +119,7 @@ define double @test_Inf_2() {
define double @test_Inf_3() {
; CHECK-LABEL: @test_Inf_3(
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%1 = call double @llvm.fma.f64(double 0xFFF0000000000000, double 8.0, double 0.0)
ret double %1
@@ -127,7 +127,7 @@ define double @test_Inf_3() {
define double @test_Inf_4() {
; CHECK-LABEL: @test_Inf_4(
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%1 = call double @llvm.fma.f64(double 7.0, double 0xFFF0000000000000, double 0.0)
ret double %1
@@ -137,7 +137,7 @@ define double @test_Inf_4() {
define double @inf_product_opposite_inf_addend_1() {
; CHECK-LABEL: @inf_product_opposite_inf_addend_1(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 7.0, double 0xFFF0000000000000, double 0x7FF0000000000000)
ret double %1
@@ -147,7 +147,7 @@ define double @inf_product_opposite_inf_addend_1() {
define double @inf_product_opposite_inf_addend_2() {
; CHECK-LABEL: @inf_product_opposite_inf_addend_2(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 7.0, double 0x7FF0000000000000, double 0xFFF0000000000000)
ret double %1
@@ -157,7 +157,7 @@ define double @inf_product_opposite_inf_addend_2() {
define double @inf_product_opposite_inf_addend_3() {
; CHECK-LABEL: @inf_product_opposite_inf_addend_3(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0xFFF0000000000000, double 42.0, double 0x7FF0000000000000)
ret double %1
@@ -167,7 +167,7 @@ define double @inf_product_opposite_inf_addend_3() {
define double @inf_product_opposite_inf_addend_4() {
; CHECK-LABEL: @inf_product_opposite_inf_addend_4(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0x7FF0000000000000, double 42.0, double 0xFFF0000000000000)
ret double %1
@@ -177,7 +177,7 @@ define double @inf_product_opposite_inf_addend_4() {
define double @inf_times_zero_1() {
; CHECK-LABEL: @inf_times_zero_1(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0.0, double 0xFFF0000000000000, double 42.0)
ret double %1
@@ -187,7 +187,7 @@ define double @inf_times_zero_1() {
define double @inf_times_zero_2() {
; CHECK-LABEL: @inf_times_zero_2(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0.0, double 0x7FF0000000000000, double 42.0)
ret double %1
@@ -197,7 +197,7 @@ define double @inf_times_zero_2() {
define double @inf_times_zero_3() {
; CHECK-LABEL: @inf_times_zero_3(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0xFFF0000000000000, double 0.0, double 42.0)
ret double %1
@@ -207,7 +207,7 @@ define double @inf_times_zero_3() {
define double @inf_times_zero_4() {
; CHECK-LABEL: @inf_times_zero_4(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0x7FF0000000000000, double 0.0, double 42.0)
ret double %1
@@ -217,7 +217,7 @@ define double @inf_times_zero_4() {
define double @inf_times_zero_5() {
; CHECK-LABEL: @inf_times_zero_5(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double -0.0, double 0xFFF0000000000000, double 42.0)
ret double %1
@@ -227,7 +227,7 @@ define double @inf_times_zero_5() {
define double @inf_times_zero_6() {
; CHECK-LABEL: @inf_times_zero_6(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double -0.0, double 0x7FF0000000000000, double 42.0)
ret double %1
@@ -237,7 +237,7 @@ define double @inf_times_zero_6() {
define double @inf_times_zero_7() {
; CHECK-LABEL: @inf_times_zero_7(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0xFFF0000000000000, double -0.0, double 42.0)
ret double %1
@@ -247,7 +247,7 @@ define double @inf_times_zero_7() {
define double @inf_times_zero_8() {
; CHECK-LABEL: @inf_times_zero_8(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%1 = call double @llvm.fma.f64(double 0x7FF0000000000000, double -0.0, double 42.0)
ret double %1
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/fp-undef.ll b/llvm/test/Transforms/InstSimplify/ConstProp/fp-undef.ll
index 644fdf1daab01..ac39299efd92e 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/fp-undef.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/fp-undef.ll
@@ -54,7 +54,7 @@ define double @frem_undef_undef(double %x) {
define float @fadd_undef_op0_nnan_constant(float %x) {
; CHECK-LABEL: @fadd_undef_op0_nnan_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fadd nnan float undef, 1.0
ret float %r
@@ -62,7 +62,7 @@ define float @fadd_undef_op0_nnan_constant(float %x) {
define float @fadd_undef_op1_constant(float %x) {
; CHECK-LABEL: @fadd_undef_op1_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fadd float 2.0, undef
ret float %r
@@ -70,7 +70,7 @@ define float @fadd_undef_op1_constant(float %x) {
define float @fsub_undef_op0_fast_constant(float %x) {
; CHECK-LABEL: @fsub_undef_op0_fast_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fsub fast float undef, 3.0
ret float %r
@@ -78,7 +78,7 @@ define float @fsub_undef_op0_fast_constant(float %x) {
define float @fsub_undef_op1_constant(float %x) {
; CHECK-LABEL: @fsub_undef_op1_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fsub float 4.0, undef
ret float %r
@@ -86,7 +86,7 @@ define float @fsub_undef_op1_constant(float %x) {
define float @fmul_undef_op0_nnan_constant(float %x) {
; CHECK-LABEL: @fmul_undef_op0_nnan_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fmul nnan float undef, 5.0
ret float %r
@@ -94,7 +94,7 @@ define float @fmul_undef_op0_nnan_constant(float %x) {
define float @fmul_undef_op1_constant(float %x) {
; CHECK-LABEL: @fmul_undef_op1_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fmul float 6.0, undef
ret float %r
@@ -102,7 +102,7 @@ define float @fmul_undef_op1_constant(float %x) {
define float @fdiv_undef_op0_fast_constant(float %x) {
; CHECK-LABEL: @fdiv_undef_op0_fast_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fdiv fast float undef, 7.0
ret float %r
@@ -110,7 +110,7 @@ define float @fdiv_undef_op0_fast_constant(float %x) {
define float @fdiv_undef_op1_constant(float %x) {
; CHECK-LABEL: @fdiv_undef_op1_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fdiv float 8.0, undef
ret float %r
@@ -118,7 +118,7 @@ define float @fdiv_undef_op1_constant(float %x) {
define float @frem_undef_op0_nnan_constant(float %x) {
; CHECK-LABEL: @frem_undef_op0_nnan_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = frem nnan float undef, 9.0
ret float %r
@@ -126,7 +126,7 @@ define float @frem_undef_op0_nnan_constant(float %x) {
define float @frem_undef_op1_constant(float %x) {
; CHECK-LABEL: @frem_undef_op1_constant(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = frem float 10.0, undef
ret float %r
@@ -136,7 +136,7 @@ define float @frem_undef_op1_constant(float %x) {
define double @fadd_undef_op0_constant_0(double %x) {
; CHECK-LABEL: @fadd_undef_op0_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fadd double undef, 0x0000000000000000
ret double %r
@@ -144,7 +144,7 @@ define double @fadd_undef_op0_constant_0(double %x) {
define double @fadd_undef_op1_constant_0(double %x) {
; CHECK-LABEL: @fadd_undef_op1_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fadd double 0x0000000000000000, undef
ret double %r
@@ -160,7 +160,7 @@ define double @fsub_undef_op0_constant_0(double %x) {
define double @fsub_undef_op1_constant_0(double %x) {
; CHECK-LABEL: @fsub_undef_op1_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fsub double 0x0000000000000000, undef
ret double %r
@@ -168,7 +168,7 @@ define double @fsub_undef_op1_constant_0(double %x) {
define double @fmul_undef_op0_constant_0(double %x) {
; CHECK-LABEL: @fmul_undef_op0_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fmul double undef, 0x0000000000000000
ret double %r
@@ -176,7 +176,7 @@ define double @fmul_undef_op0_constant_0(double %x) {
define double @fmul_undef_op1_constant_0(double %x) {
; CHECK-LABEL: @fmul_undef_op1_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fmul double 0x0000000000000000, undef
ret double %r
@@ -184,7 +184,7 @@ define double @fmul_undef_op1_constant_0(double %x) {
define double @fdiv_undef_op0_constant_0(double %x) {
; CHECK-LABEL: @fdiv_undef_op0_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fdiv double undef, 0x0000000000000000
ret double %r
@@ -192,7 +192,7 @@ define double @fdiv_undef_op0_constant_0(double %x) {
define double @fdiv_undef_op1_constant_0(double %x) {
; CHECK-LABEL: @fdiv_undef_op1_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fdiv double 0x0000000000000000, undef
ret double %r
@@ -200,7 +200,7 @@ define double @fdiv_undef_op1_constant_0(double %x) {
define double @frem_undef_op0_constant_0(double %x) {
; CHECK-LABEL: @frem_undef_op0_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = frem double undef, 0x0000000000000000
ret double %r
@@ -208,7 +208,7 @@ define double @frem_undef_op0_constant_0(double %x) {
define double @frem_undef_op1_constant_0(double %x) {
; CHECK-LABEL: @frem_undef_op1_constant_0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = frem double 0x0000000000000000, undef
ret double %r
@@ -234,7 +234,7 @@ define double @fadd_undef_op1_constant_neg0(double %x) {
define double @fsub_undef_op0_constant_neg0(double %x) {
; CHECK-LABEL: @fsub_undef_op0_constant_neg0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fsub double undef, 0x8000000000000000
ret double %r
@@ -250,7 +250,7 @@ define double @fsub_undef_op1_constant_neg0(double %x) {
define double @fmul_undef_op0_constant_neg0(double %x) {
; CHECK-LABEL: @fmul_undef_op0_constant_neg0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fmul double undef, 0x8000000000000000
ret double %r
@@ -258,7 +258,7 @@ define double @fmul_undef_op0_constant_neg0(double %x) {
define double @fmul_undef_op1_constant_neg0(double %x) {
; CHECK-LABEL: @fmul_undef_op1_constant_neg0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fmul double 0x8000000000000000, undef
ret double %r
@@ -266,7 +266,7 @@ define double @fmul_undef_op1_constant_neg0(double %x) {
define double @fdiv_undef_op0_constant_neg0(double %x) {
; CHECK-LABEL: @fdiv_undef_op0_constant_neg0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fdiv double undef, 0x8000000000000000
ret double %r
@@ -274,7 +274,7 @@ define double @fdiv_undef_op0_constant_neg0(double %x) {
define double @fdiv_undef_op1_constant_neg0(double %x) {
; CHECK-LABEL: @fdiv_undef_op1_constant_neg0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fdiv double 0x8000000000000000, undef
ret double %r
@@ -282,7 +282,7 @@ define double @fdiv_undef_op1_constant_neg0(double %x) {
define double @frem_undef_op0_constant_neg0(double %x) {
; CHECK-LABEL: @frem_undef_op0_constant_neg0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = frem double undef, 0x8000000000000000
ret double %r
@@ -290,7 +290,7 @@ define double @frem_undef_op0_constant_neg0(double %x) {
define double @frem_undef_op1_constant_neg0(double %x) {
; CHECK-LABEL: @frem_undef_op1_constant_neg0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = frem double 0x8000000000000000, undef
ret double %r
@@ -300,7 +300,7 @@ define double @frem_undef_op1_constant_neg0(double %x) {
define double @fadd_undef_op0_constant_nan(double %x) {
; CHECK-LABEL: @fadd_undef_op0_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fadd double undef, 0x7FF8000000000000
ret double %r
@@ -308,7 +308,7 @@ define double @fadd_undef_op0_constant_nan(double %x) {
define double @fadd_undef_op1_fast_constant_nan(double %x) {
; CHECK-LABEL: @fadd_undef_op1_fast_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fadd fast double 0xFFF0000000000001, undef
ret double %r
@@ -316,7 +316,7 @@ define double @fadd_undef_op1_fast_constant_nan(double %x) {
define double @fsub_undef_op0_constant_nan(double %x) {
; CHECK-LABEL: @fsub_undef_op0_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fsub double undef, 0xFFF8000000000010
ret double %r
@@ -324,7 +324,7 @@ define double @fsub_undef_op0_constant_nan(double %x) {
define double @fsub_undef_op1_nnan_constant_nan(double %x) {
; CHECK-LABEL: @fsub_undef_op1_nnan_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fsub nnan double 0x7FF0000000000011, undef
ret double %r
@@ -332,7 +332,7 @@ define double @fsub_undef_op1_nnan_constant_nan(double %x) {
define double @fmul_undef_op0_constant_nan(double %x) {
; CHECK-LABEL: @fmul_undef_op0_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fmul double undef, 0x7FF8000000000100
ret double %r
@@ -340,7 +340,7 @@ define double @fmul_undef_op0_constant_nan(double %x) {
define double @fmul_undef_op1_fast_constant_nan(double %x) {
; CHECK-LABEL: @fmul_undef_op1_fast_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fmul fast double 0xFFF0000000000101, undef
ret double %r
@@ -348,7 +348,7 @@ define double @fmul_undef_op1_fast_constant_nan(double %x) {
define double @fdiv_undef_op0_constant_nan(double %x) {
; CHECK-LABEL: @fdiv_undef_op0_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fdiv double undef, 0xFFF8000000000110
ret double %r
@@ -356,7 +356,7 @@ define double @fdiv_undef_op0_constant_nan(double %x) {
define double @fdiv_undef_op1_nnan_constant_nan(double %x) {
; CHECK-LABEL: @fdiv_undef_op1_nnan_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fdiv nnan double 0x7FF0000000000111, undef
ret double %r
@@ -364,7 +364,7 @@ define double @fdiv_undef_op1_nnan_constant_nan(double %x) {
define double @frem_undef_op0_constant_nan(double %x) {
; CHECK-LABEL: @frem_undef_op0_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = frem double undef, 0x7FF8000000001000
ret double %r
@@ -372,7 +372,7 @@ define double @frem_undef_op0_constant_nan(double %x) {
define double @frem_undef_op1_fast_constant_nan(double %x) {
; CHECK-LABEL: @frem_undef_op1_fast_constant_nan(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = frem fast double 0xFFF0000000001001, undef
ret double %r
@@ -382,7 +382,7 @@ define double @frem_undef_op1_fast_constant_nan(double %x) {
define double @fadd_undef_op0_constant_inf(double %x) {
; CHECK-LABEL: @fadd_undef_op0_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fadd double undef, 0x7FF0000000000000
ret double %r
@@ -390,7 +390,7 @@ define double @fadd_undef_op0_constant_inf(double %x) {
define double @fadd_undef_op1_fast_constant_inf(double %x) {
; CHECK-LABEL: @fadd_undef_op1_fast_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fadd fast double 0xFFF0000000000000, undef
ret double %r
@@ -398,7 +398,7 @@ define double @fadd_undef_op1_fast_constant_inf(double %x) {
define double @fsub_undef_op0_constant_inf(double %x) {
; CHECK-LABEL: @fsub_undef_op0_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fsub double undef, 0xFFF0000000000000
ret double %r
@@ -406,7 +406,7 @@ define double @fsub_undef_op0_constant_inf(double %x) {
define double @fsub_undef_op1_ninf_constant_inf(double %x) {
; CHECK-LABEL: @fsub_undef_op1_ninf_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fsub ninf double 0x7FF0000000000000, undef
ret double %r
@@ -414,7 +414,7 @@ define double @fsub_undef_op1_ninf_constant_inf(double %x) {
define double @fmul_undef_op0_constant_inf(double %x) {
; CHECK-LABEL: @fmul_undef_op0_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fmul double undef, 0x7FF0000000000000
ret double %r
@@ -422,7 +422,7 @@ define double @fmul_undef_op0_constant_inf(double %x) {
define double @fmul_undef_op1_fast_constant_inf(double %x) {
; CHECK-LABEL: @fmul_undef_op1_fast_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fmul fast double 0xFFF0000000000000, undef
ret double %r
@@ -430,7 +430,7 @@ define double @fmul_undef_op1_fast_constant_inf(double %x) {
define double @fdiv_undef_op0_constant_inf(double %x) {
; CHECK-LABEL: @fdiv_undef_op0_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fdiv double undef, 0xFFF0000000000000
ret double %r
@@ -438,7 +438,7 @@ define double @fdiv_undef_op0_constant_inf(double %x) {
define double @fdiv_undef_op1_ninf_constant_inf(double %x) {
; CHECK-LABEL: @fdiv_undef_op1_ninf_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fdiv ninf double 0x7FF0000000000000, undef
ret double %r
@@ -446,7 +446,7 @@ define double @fdiv_undef_op1_ninf_constant_inf(double %x) {
define double @frem_undef_op0_constant_inf(double %x) {
; CHECK-LABEL: @frem_undef_op0_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = frem double undef, 0x7FF0000000000000
ret double %r
@@ -454,7 +454,7 @@ define double @frem_undef_op0_constant_inf(double %x) {
define double @frem_undef_op1_fast_constant_inf(double %x) {
; CHECK-LABEL: @frem_undef_op1_fast_constant_inf(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = frem fast double 0xFFF0000000000000, undef
ret double %r
@@ -462,7 +462,7 @@ define double @frem_undef_op1_fast_constant_inf(double %x) {
define <2 x double> @fadd_undef_op1_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @fadd_undef_op1_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = fadd <2 x double> <double 42.0, double undef>, undef
ret <2 x double> %r
@@ -470,7 +470,7 @@ define <2 x double> @fadd_undef_op1_constant_vec(<2 x double> %x) {
define <2 x double> @fadd_undef_op0_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @fadd_undef_op0_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double undef, double 0x7FF8000000000000>
+; CHECK-NEXT: ret <2 x double> <double undef, double +qnan>
;
%r = fadd <2 x double> undef, <double undef, double 42.0>
ret <2 x double> %r
@@ -478,7 +478,7 @@ define <2 x double> @fadd_undef_op0_constant_vec(<2 x double> %x) {
define <2 x double> @fsub_undef_op1_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @fsub_undef_op1_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double undef, double 0x7FF8000000000000>
+; CHECK-NEXT: ret <2 x double> <double undef, double +qnan>
;
%r = fsub <2 x double> <double undef, double 42.0>, undef
ret <2 x double> %r
@@ -486,7 +486,7 @@ define <2 x double> @fsub_undef_op1_constant_vec(<2 x double> %x) {
define <2 x double> @fsub_undef_op0_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @fsub_undef_op0_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = fsub <2 x double> undef, <double 42.0, double undef>
ret <2 x double> %r
@@ -494,7 +494,7 @@ define <2 x double> @fsub_undef_op0_constant_vec(<2 x double> %x) {
define <2 x double> @fmul_undef_op1_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @fmul_undef_op1_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = fmul <2 x double> <double 42.0, double undef>, undef
ret <2 x double> %r
@@ -502,7 +502,7 @@ define <2 x double> @fmul_undef_op1_constant_vec(<2 x double> %x) {
define <2 x double> @fmul_undef_op0_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @fmul_undef_op0_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double undef, double 0x7FF8000000000000>
+; CHECK-NEXT: ret <2 x double> <double undef, double +qnan>
;
%r = fmul <2 x double> undef, <double undef, double 42.0>
ret <2 x double> %r
@@ -510,7 +510,7 @@ define <2 x double> @fmul_undef_op0_constant_vec(<2 x double> %x) {
define <2 x double> @fdiv_undef_op1_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @fdiv_undef_op1_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = fdiv <2 x double> <double 42.0, double undef>, undef
ret <2 x double> %r
@@ -518,7 +518,7 @@ define <2 x double> @fdiv_undef_op1_constant_vec(<2 x double> %x) {
define <2 x double> @fdiv_undef_op0_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @fdiv_undef_op0_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double undef, double 0x7FF8000000000000>
+; CHECK-NEXT: ret <2 x double> <double undef, double +qnan>
;
%r = fdiv <2 x double> undef, <double undef, double 42.0>
ret <2 x double> %r
@@ -526,7 +526,7 @@ define <2 x double> @fdiv_undef_op0_constant_vec(<2 x double> %x) {
define <2 x double> @frem_undef_op1_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @frem_undef_op1_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double undef, double 0x7FF8000000000000>
+; CHECK-NEXT: ret <2 x double> <double undef, double +qnan>
;
%r = frem <2 x double> <double undef, double 42.0>, undef
ret <2 x double> %r
@@ -534,7 +534,7 @@ define <2 x double> @frem_undef_op1_constant_vec(<2 x double> %x) {
define <2 x double> @frem_undef_op0_constant_vec(<2 x double> %x) {
; CHECK-LABEL: @frem_undef_op0_constant_vec(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = frem <2 x double> undef, <double 42.0, double undef>
ret <2 x double> %r
@@ -542,7 +542,7 @@ define <2 x double> @frem_undef_op0_constant_vec(<2 x double> %x) {
define <2 x double> @maximumnum_nan_op0_vec_partial_poison_op1_poison(<2 x double> %x) {
; CHECK-LABEL: @maximumnum_nan_op0_vec_partial_poison_op1_poison(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double poison>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double poison>
;
%r = call <2 x double> @llvm.maximumnum.v2f64(<2 x double> <double 0x7ff8000000000000, double poison>, <2 x double> poison)
ret <2 x double> %r
@@ -550,7 +550,7 @@ define <2 x double> @maximumnum_nan_op0_vec_partial_poison_op1_poison(<2 x doubl
define <2 x double> @maximumnum_nan_op1_vec_partial_poison_op0_poison(<2 x double> %x) {
; CHECK-LABEL: @maximumnum_nan_op1_vec_partial_poison_op0_poison(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double poison>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double poison>
;
%r = call <2 x double> @llvm.maximumnum.v2f64(<2 x double> poison, <2 x double> <double 0x7ff8000000000000, double poison>)
ret <2 x double> %r
@@ -558,7 +558,7 @@ define <2 x double> @maximumnum_nan_op1_vec_partial_poison_op0_poison(<2 x doubl
define <2 x double> @minimumnum_nan_op0_vec_partial_poison_op1_poison(<2 x double> %x) {
; CHECK-LABEL: @minimumnum_nan_op0_vec_partial_poison_op1_poison(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double poison>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double poison>
;
%r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> <double 0x7ff8000000000000, double poison>, <2 x double> poison)
ret <2 x double> %r
@@ -566,7 +566,7 @@ define <2 x double> @minimumnum_nan_op0_vec_partial_poison_op1_poison(<2 x doubl
define <2 x double> @minimumnum_nan_op1_vec_partial_poison_op0_poison(<2 x double> %x) {
; CHECK-LABEL: @minimumnum_nan_op1_vec_partial_poison_op0_poison(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double poison>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double poison>
;
%r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> poison, <2 x double> <double 0x7ff8000000000000, double poison>)
ret <2 x double> %r
@@ -574,7 +574,7 @@ define <2 x double> @minimumnum_nan_op1_vec_partial_poison_op0_poison(<2 x doubl
define <2 x double> @maximum_nan_op0_vec_partial_undef_op1_undef(<2 x double> %x) {
; CHECK-LABEL: @maximum_nan_op0_vec_partial_undef_op1_undef(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = call <2 x double> @llvm.maximum.v2f64(<2 x double> <double 0x7ff8000000000000, double undef>, <2 x double> undef)
ret <2 x double> %r
@@ -582,7 +582,7 @@ define <2 x double> @maximum_nan_op0_vec_partial_undef_op1_undef(<2 x double> %x
define <2 x double> @maximum_nan_op1_vec_partial_undef_op0_undef(<2 x double> %x) {
; CHECK-LABEL: @maximum_nan_op1_vec_partial_undef_op0_undef(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = call <2 x double> @llvm.maximum.v2f64(<2 x double> undef, <2 x double> <double 0x7ff8000000000000, double undef>)
ret <2 x double> %r
@@ -590,7 +590,7 @@ define <2 x double> @maximum_nan_op1_vec_partial_undef_op0_undef(<2 x double> %x
define <2 x double> @minimum_nan_op0_vec_partial_undef_op1_undef(<2 x double> %x) {
; CHECK-LABEL: @minimum_nan_op0_vec_partial_undef_op1_undef(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = call <2 x double> @llvm.minimum.v2f64(<2 x double> <double 0x7ff8000000000000, double undef>, <2 x double> undef)
ret <2 x double> %r
@@ -598,7 +598,7 @@ define <2 x double> @minimum_nan_op0_vec_partial_undef_op1_undef(<2 x double> %x
define <2 x double> @minimum_nan_op1_vec_partial_undef_op0_undef(<2 x double> %x) {
; CHECK-LABEL: @minimum_nan_op1_vec_partial_undef_op0_undef(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = call <2 x double> @llvm.minimum.v2f64(<2 x double> undef, <2 x double> <double 0x7ff8000000000000, double undef>)
ret <2 x double> %r
@@ -606,7 +606,7 @@ define <2 x double> @minimum_nan_op1_vec_partial_undef_op0_undef(<2 x double> %x
define <2 x double> @maxnum_nan_op0_vec_partial_undef_op1_undef(<2 x double> %x) {
; CHECK-LABEL: @maxnum_nan_op0_vec_partial_undef_op1_undef(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = call <2 x double> @llvm.maxnum.v2f64(<2 x double> <double 0x7ff8000000000000, double undef>, <2 x double> undef)
ret <2 x double> %r
@@ -614,7 +614,7 @@ define <2 x double> @maxnum_nan_op0_vec_partial_undef_op1_undef(<2 x double> %x)
define <2 x double> @maxnum_nan_op1_vec_partial_undef_op0_undef(<2 x double> %x) {
; CHECK-LABEL: @maxnum_nan_op1_vec_partial_undef_op0_undef(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = call <2 x double> @llvm.maxnum.v2f64(<2 x double> undef, <2 x double> <double 0x7ff8000000000000, double undef>)
ret <2 x double> %r
@@ -622,7 +622,7 @@ define <2 x double> @maxnum_nan_op1_vec_partial_undef_op0_undef(<2 x double> %x)
define <2 x double> @minnum_nan_op0_vec_partial_undef_op1_undef(<2 x double> %x) {
; CHECK-LABEL: @minnum_nan_op0_vec_partial_undef_op1_undef(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = call <2 x double> @llvm.minnum.v2f64(<2 x double> <double 0x7ff8000000000000, double undef>, <2 x double> undef)
ret <2 x double> %r
@@ -630,7 +630,7 @@ define <2 x double> @minnum_nan_op0_vec_partial_undef_op1_undef(<2 x double> %x)
define <2 x double> @minnum_nan_op1_vec_partial_undef_op0_undef(<2 x double> %x) {
; CHECK-LABEL: @minnum_nan_op1_vec_partial_undef_op0_undef(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF8000000000000, double undef>
+; CHECK-NEXT: ret <2 x double> <double +qnan, double undef>
;
%r = call <2 x double> @llvm.minnum.v2f64(<2 x double> undef, <2 x double> <double 0x7ff8000000000000, double undef>)
ret <2 x double> %r
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/libfunc.ll b/llvm/test/Transforms/InstSimplify/ConstProp/libfunc.ll
index 348d90225a1a7..6041c19607267 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/libfunc.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/libfunc.ll
@@ -7,7 +7,7 @@ declare double @sin(x86_fp80)
define double @PR50960(x86_fp80 %0) {
; CHECK-LABEL: @PR50960(
-; CHECK-NEXT: [[CALL:%.*]] = call double @sin(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[CALL:%.*]] = call double @sin(x86_fp80 1.000000e+00)
; CHECK-NEXT: ret double [[CALL]]
;
%call = call double @sin(x86_fp80 0xK3FFF8000000000000000)
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/loads.ll b/llvm/test/Transforms/InstSimplify/ConstProp/loads.ll
index d34d08470e83f..96e890899f466 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/loads.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/loads.ll
@@ -89,10 +89,10 @@ define i16 @test7() {
; Double load.
define double @test8() {
; LE-LABEL: @test8(
-; LE-NEXT: ret double 0xBADEADBEEF
+; LE-NEXT: ret double f0x000000BADEADBEEF
;
; BE-LABEL: @test8(
-; BE-NEXT: ret double 0xDEADBEEFBA000000
+; BE-NEXT: ret double f0xDEADBEEFBA000000
;
%r = load double, ptr @g1
ret double %r
@@ -113,10 +113,10 @@ define i128 @test_i128() {
define fp128 @test_fp128() {
; LE-LABEL: @test_fp128(
-; LE-NEXT: ret fp128 0xL000000000000007B0000000006B1BFF8
+; LE-NEXT: ret fp128 f0x0000000006B1BFF8000000000000007B
;
; BE-LABEL: @test_fp128(
-; BE-NEXT: ret fp128 0xL0000000006B1BFF8000000000000007B
+; BE-NEXT: ret fp128 f0x000000000000007B0000000006B1BFF8
;
%r = load fp128, ptr @g3
ret fp128 %r
@@ -135,10 +135,10 @@ define ppc_fp128 @test_ppc_fp128() {
define x86_fp80 @test_x86_fp80() {
; LE-LABEL: @test_x86_fp80(
-; LE-NEXT: ret x86_fp80 0xKFFFF000000000000007B
+; LE-NEXT: ret x86_fp80 -snan(0x7B)
;
; BE-LABEL: @test_x86_fp80(
-; BE-NEXT: ret x86_fp80 0xK000000000000007B0000
+; BE-NEXT: ret x86_fp80 f0x000000000000007B0000
;
%r = load x86_fp80, ptr @g3
ret x86_fp80 %r
@@ -146,10 +146,10 @@ define x86_fp80 @test_x86_fp80() {
define bfloat @test_bfloat() {
; LE-LABEL: @test_bfloat(
-; LE-NEXT: ret bfloat 0xR007B
+; LE-NEXT: ret bfloat 1.129580e-38
;
; BE-LABEL: @test_bfloat(
-; BE-NEXT: ret bfloat 0xR0000
+; BE-NEXT: ret bfloat 0.000000e+00
;
%r = load bfloat, ptr @g3
ret bfloat %r
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/logf128.ll b/llvm/test/Transforms/InstSimplify/ConstProp/logf128.ll
index 82db5e4066cb1..75b49efe2898d 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/logf128.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/logf128.ll
@@ -7,7 +7,7 @@ declare fp128 @logl(fp128)
define fp128 @log_e_64(){
; CHECK-LABEL: define fp128 @log_e_64() {
-; CHECK-NEXT: ret fp128 0xL300000000000000040010A2B23F3BAB7
+; CHECK-NEXT: ret fp128 f0x40010A2B23F3BAB73000000000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000004005000000000000)
ret fp128 %A
@@ -15,7 +15,7 @@ define fp128 @log_e_64(){
define fp128 @log_e_smallest_positive_subnormal_number(){
; CHECK-LABEL: define fp128 @log_e_smallest_positive_subnormal_number() {
-; CHECK-NEXT: ret fp128 0xL3000000000000000C00C654628220780
+; CHECK-NEXT: ret fp128 f0xC00C6546282207803000000000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000010000000000000000)
ret fp128 %A
@@ -23,7 +23,7 @@ define fp128 @log_e_smallest_positive_subnormal_number(){
define fp128 @log_e_largest_subnormal_number(){
; CHECK-LABEL: define fp128 @log_e_largest_subnormal_number() {
-; CHECK-NEXT: ret fp128 0xLD000000000000000C00C62D918CE2421
+; CHECK-NEXT: ret fp128 f0xC00C62D918CE2421D000000000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xLFFFFFFFFFFFFFFFF0000FFFFFFFFFFFF)
ret fp128 %A
@@ -32,7 +32,7 @@ define fp128 @log_e_largest_subnormal_number(){
define fp128 @log_e_smallest_positive_normal_number(){
;
; CHECK-LABEL: define fp128 @log_e_smallest_positive_normal_number() {
-; CHECK-NEXT: ret fp128 0xLD000000000000000C00C62D918CE2421
+; CHECK-NEXT: ret fp128 f0xC00C62D918CE2421D000000000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000000001000000000000)
ret fp128 %A
@@ -40,7 +40,7 @@ define fp128 @log_e_smallest_positive_normal_number(){
define fp128 @log_e_largest_normal_number(){
; CHECK-LABEL: define fp128 @log_e_largest_normal_number() {
-; CHECK-NEXT: ret fp128 0xLF000000000000000400C62E42FEFA39E
+; CHECK-NEXT: ret fp128 f0x400C62E42FEFA39EF000000000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF)
ret fp128 %A
@@ -48,7 +48,7 @@ define fp128 @log_e_largest_normal_number(){
define fp128 @log_e_largest_number_less_than_one(){
; CHECK-LABEL: define fp128 @log_e_largest_number_less_than_one() {
-; CHECK-NEXT: ret fp128 0xL0000000000000000BF8E000000000000
+; CHECK-NEXT: ret fp128 f0xBF8E0000000000000000000000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xLFFFFFFFFFFFFFFFF3FFEFFFFFFFFFFFF)
ret fp128 %A
@@ -56,7 +56,7 @@ define fp128 @log_e_largest_number_less_than_one(){
define fp128 @log_e_1(){
; CHECK-LABEL: define fp128 @log_e_1() {
-; CHECK-NEXT: ret fp128 0xL00000000000000000000000000000000
+; CHECK-NEXT: ret fp128 0.000000e+00
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000003FFF000000000000)
ret fp128 %A
@@ -64,7 +64,7 @@ define fp128 @log_e_1(){
define fp128 @log_e_smallest_number_larger_than_one(){
; CHECK-LABEL: define fp128 @log_e_smallest_number_larger_than_one() {
-; CHECK-NEXT: ret fp128 0xL00000000000000003F8F000000000000
+; CHECK-NEXT: ret fp128 f0x3F8F0000000000000000000000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000013FFF000000000000)
ret fp128 %A
@@ -72,7 +72,7 @@ define fp128 @log_e_smallest_number_larger_than_one(){
define fp128 @log_e_negative_2(){
; CHECK-LABEL: define fp128 @log_e_negative_2() {
-; CHECK-NEXT: ret fp128 0xL0000000000000000{{[7|F]}}FFF800000000000
+; CHECK-NEXT: ret fp128 0.000000e+00{{[7|F]}}FFF800000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL0000000000000000C000000000000000)
ret fp128 %A
@@ -80,7 +80,7 @@ define fp128 @log_e_negative_2(){
define fp128 @log_e_0(){
; CHECK-LABEL: define fp128 @log_e_0() {
-; CHECK-NEXT: ret fp128 0xL0000000000000000FFFF000000000000
+; CHECK-NEXT: ret fp128 -inf
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000000000000000000000)
ret fp128 %A
@@ -88,7 +88,7 @@ define fp128 @log_e_0(){
define fp128 @log_e_negative_0(){
; CHECK-LABEL: define fp128 @log_e_negative_0() {
-; CHECK-NEXT: ret fp128 0xL0000000000000000FFFF000000000000
+; CHECK-NEXT: ret fp128 -inf
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000008000000000000000)
ret fp128 %A
@@ -96,7 +96,7 @@ define fp128 @log_e_negative_0(){
define fp128 @log_e_infinity(){
; CHECK-LABEL: define fp128 @log_e_infinity() {
-; CHECK-NEXT: ret fp128 0xL00000000000000007FFF000000000000
+; CHECK-NEXT: ret fp128 +inf
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000007FFF000000000000)
ret fp128 %A
@@ -104,7 +104,7 @@ define fp128 @log_e_infinity(){
define fp128 @log_e_negative_infinity(){
; CHECK-LABEL: define fp128 @log_e_negative_infinity() {
-; CHECK-NEXT: ret fp128 0xL0000000000000000{{[7|F]}}FFF800000000000
+; CHECK-NEXT: ret fp128 0.000000e+00{{[7|F]}}FFF800000000000
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL0000000000000000FFFF000000000000)
ret fp128 %A
@@ -112,7 +112,7 @@ define fp128 @log_e_negative_infinity(){
define fp128 @log_e_nan(){
; CHECK-LABEL: define fp128 @log_e_nan() {
-; CHECK-NEXT: ret fp128 0xL00000000000000007FFF800000000001
+; CHECK-NEXT: ret fp128 +nan(0x10000000000000000)
;
%A = call fp128 @llvm.log.f128(fp128 noundef 0xL00000000000000007FFF000000000001)
ret fp128 %A
@@ -120,7 +120,7 @@ define fp128 @log_e_nan(){
define <2 x fp128> @log_e_negative_2_vector(){
; CHECK-LABEL: define <2 x fp128> @log_e_negative_2_vector() {
-; CHECK-NEXT: ret <2 x fp128> <fp128 0xL0000000000000000{{[7|F]}}FFF800000000000, fp128 0xL0000000000000000{{[7|F]}}FFF800000000000>
+; CHECK-NEXT: ret <2 x fp128> <fp128 0.000000e+00{{[7|F]}}FFF800000000000, fp128 0.000000e+00{{[7|F]}}FFF800000000000>
;
%A = call <2 x fp128> @llvm.log.v2f128(<2 x fp128> <fp128 0xL0000000000000000C000000000000000, fp128 0xL0000000000000000C000000000000001>)
ret <2 x fp128> %A
@@ -128,8 +128,8 @@ define <2 x fp128> @log_e_negative_2_vector(){
define fp128 @logl_e_64(){
; CHECK-LABEL: define fp128 @logl_e_64() {
-; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef 0xL00000000000000004005000000000000)
-; CHECK-NEXT: ret fp128 0xL300000000000000040010A2B23F3BAB7
+; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef 6.400000e+01)
+; CHECK-NEXT: ret fp128 f0x40010A2B23F3BAB73000000000000000
;
%A = call fp128 @logl(fp128 noundef 0xL00000000000000004005000000000000)
ret fp128 %A
@@ -137,7 +137,7 @@ define fp128 @logl_e_64(){
define fp128 @logl_e_0(){
; CHECK-LABEL: define fp128 @logl_e_0() {
-; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef 0xL00000000000000000000000000000000)
+; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef 0.000000e+00)
; CHECK-NEXT: ret fp128 [[A]]
;
%A = call fp128 @logl(fp128 noundef 0xL00000000000000000000000000000000)
@@ -146,8 +146,8 @@ define fp128 @logl_e_0(){
define fp128 @logl_e_infinity(){
; CHECK-LABEL: define fp128 @logl_e_infinity() {
-; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef 0xL00000000000000007FFF000000000000)
-; CHECK-NEXT: ret fp128 0xL00000000000000007FFF000000000000
+; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef +inf)
+; CHECK-NEXT: ret fp128 +inf
;
%A = call fp128 @logl(fp128 noundef 0xL00000000000000007FFF000000000000)
ret fp128 %A
@@ -155,7 +155,7 @@ define fp128 @logl_e_infinity(){
define fp128 @logl_e_nan(){
; CHECK-LABEL: define fp128 @logl_e_nan() {
-; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef 0xL00000000000000007FFF000000000001)
+; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef +snan(0x10000000000000000))
; CHECK-NEXT: ret fp128 [[A]]
;
%A = call fp128 @logl(fp128 noundef 0xL00000000000000007FFF000000000001)
@@ -165,7 +165,7 @@ define fp128 @logl_e_nan(){
define fp128 @logl_e_negative_2(){
; CHECK-LABEL: define fp128 @logl_e_negative_2() {
-; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef 0xL0000000000000000C000000000000000)
+; CHECK-NEXT: [[A:%.*]] = call fp128 @logl(fp128 noundef -2.000000e+00)
; CHECK-NEXT: ret fp128 [[A]]
;
%A = call fp128 @logl(fp128 noundef 0xL0000000000000000C000000000000000)
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/min-max.ll b/llvm/test/Transforms/InstSimplify/ConstProp/min-max.ll
index a633d29179896..1b3e46d036421 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/min-max.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/min-max.ll
@@ -97,7 +97,7 @@ define float @minnum_float_qnan_p0() {
define float @minnum_float_p0_snan() {
; CHECK-LABEL: @minnum_float_p0_snan(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%min = call float @llvm.minnum.f32(float 0.0, float 0x7FF4000000000000)
ret float %min
@@ -105,7 +105,7 @@ define float @minnum_float_p0_snan() {
define float @minnum_float_snan_p0() {
; CHECK-LABEL: @minnum_float_snan_p0(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%min = call float @llvm.minnum.f32(float 0x7FF4000000000000, float 0.0)
ret float %min
@@ -113,7 +113,7 @@ define float @minnum_float_snan_p0() {
define bfloat @minnum_bfloat() {
; CHECK-LABEL: @minnum_bfloat(
-; CHECK-NEXT: ret bfloat 0xR40A0
+; CHECK-NEXT: ret bfloat 5.000000e+00
;
%1 = call bfloat @llvm.minnum.bf16(bfloat 5.0, bfloat 42.0)
ret bfloat %1
@@ -121,7 +121,7 @@ define bfloat @minnum_bfloat() {
define half @minnum_half() {
; CHECK-LABEL: @minnum_half(
-; CHECK-NEXT: ret half 0xH4500
+; CHECK-NEXT: ret half 5.000000e+00
;
%1 = call half @llvm.minnum.f16(half 5.0, half 42.0)
ret half %1
@@ -131,7 +131,7 @@ define half @minnum_half() {
define <4 x float> @minnum_float_vec() {
; CHECK-LABEL: @minnum_float_vec(
-; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 5.000000e+00, float 4.200000e+01, float 5.000000e+00>
+; CHECK-NEXT: ret <4 x float> <float +qnan, float 5.000000e+00, float 4.200000e+01, float 5.000000e+00>
;
%1 = call <4 x float> @llvm.minnum.v4f32(<4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>, <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>)
ret <4 x float> %1
@@ -139,7 +139,7 @@ define <4 x float> @minnum_float_vec() {
define <4 x bfloat> @minnum_bfloat_vec() {
; CHECK-LABEL: @minnum_bfloat_vec(
-; CHECK-NEXT: ret <4 x bfloat> <bfloat 0xR7FC0, bfloat 0xR40A0, bfloat 0xR4228, bfloat 0xR40A0>
+; CHECK-NEXT: ret <4 x bfloat> <bfloat +qnan, bfloat 5.000000e+00, bfloat 4.200000e+01, bfloat 5.000000e+00>
;
%1 = call <4 x bfloat> @llvm.minnum.v4bf16(<4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 0x7FF8000000000000, bfloat 42., bfloat 42.>, <4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 5., bfloat 0x7FF8000000000000, bfloat 5.>)
ret <4 x bfloat> %1
@@ -147,7 +147,7 @@ define <4 x bfloat> @minnum_bfloat_vec() {
define <4 x half> @minnum_half_vec() {
; CHECK-LABEL: @minnum_half_vec(
-; CHECK-NEXT: ret <4 x half> <half 0xH7E00, half 0xH4500, half 0xH5140, half 0xH4500>
+; CHECK-NEXT: ret <4 x half> <half +qnan, half 5.000000e+00, half 4.200000e+01, half 5.000000e+00>
;
%1 = call <4 x half> @llvm.minnum.v4f16(<4 x half> <half 0x7FF8000000000000, half 0x7FF8000000000000, half 42., half 42.>, <4 x half> <half 0x7FF8000000000000, half 5., half 0x7FF8000000000000, half 5.>)
ret <4 x half> %1
@@ -205,7 +205,7 @@ define float @maxnum_float_qnan_p0() {
define float @maxnum_float_p0_snan() {
; CHECK-LABEL: @maxnum_float_p0_snan(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%max = call float @llvm.maxnum.f32(float 0.0, float 0x7FF4000000000000)
ret float %max
@@ -213,7 +213,7 @@ define float @maxnum_float_p0_snan() {
define float @maxnum_float_snan_p0() {
; CHECK-LABEL: @maxnum_float_snan_p0(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%max = call float @llvm.maxnum.f32(float 0x7FF4000000000000, float 0.0)
ret float %max
@@ -221,7 +221,7 @@ define float @maxnum_float_snan_p0() {
define bfloat @maxnum_bfloat() {
; CHECK-LABEL: @maxnum_bfloat(
-; CHECK-NEXT: ret bfloat 0xR4228
+; CHECK-NEXT: ret bfloat 4.200000e+01
;
%1 = call bfloat @llvm.maxnum.bf16(bfloat 5.0, bfloat 42.0)
ret bfloat %1
@@ -229,7 +229,7 @@ define bfloat @maxnum_bfloat() {
define half @maxnum_half() {
; CHECK-LABEL: @maxnum_half(
-; CHECK-NEXT: ret half 0xH5140
+; CHECK-NEXT: ret half 4.200000e+01
;
%1 = call half @llvm.maxnum.f16(half 5.0, half 42.0)
ret half %1
@@ -239,7 +239,7 @@ define half @maxnum_half() {
define <4 x float> @maxnum_float_vec() {
; CHECK-LABEL: @maxnum_float_vec(
-; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 5.000000e+00, float 4.200000e+01, float 4.200000e+01>
+; CHECK-NEXT: ret <4 x float> <float +qnan, float 5.000000e+00, float 4.200000e+01, float 4.200000e+01>
;
%1 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>, <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>)
ret <4 x float> %1
@@ -247,7 +247,7 @@ define <4 x float> @maxnum_float_vec() {
define <4 x bfloat> @maxnum_bfloat_vec() {
; CHECK-LABEL: @maxnum_bfloat_vec(
-; CHECK-NEXT: ret <4 x bfloat> <bfloat 0xR7FC0, bfloat 0xR40A0, bfloat 0xR4228, bfloat 0xR4228>
+; CHECK-NEXT: ret <4 x bfloat> <bfloat +qnan, bfloat 5.000000e+00, bfloat 4.200000e+01, bfloat 4.200000e+01>
;
%1 = call <4 x bfloat> @llvm.maxnum.v4bf16(<4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 0x7FF8000000000000, bfloat 42., bfloat 42.>, <4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 5., bfloat 0x7FF8000000000000, bfloat 5.>)
ret <4 x bfloat> %1
@@ -255,7 +255,7 @@ define <4 x bfloat> @maxnum_bfloat_vec() {
define <4 x half> @maxnum_half_vec() {
; CHECK-LABEL: @maxnum_half_vec(
-; CHECK-NEXT: ret <4 x half> <half 0xH7E00, half 0xH4500, half 0xH5140, half 0xH5140>
+; CHECK-NEXT: ret <4 x half> <half +qnan, half 5.000000e+00, half 4.200000e+01, half 4.200000e+01>
;
%1 = call <4 x half> @llvm.maxnum.v4f16(<4 x half> <half 0x7FF8000000000000, half 0x7FF8000000000000, half 42., half 42.>, <4 x half> <half 0x7FF8000000000000, half 5., half 0x7FF8000000000000, half 5.>)
ret <4 x half> %1
@@ -281,7 +281,7 @@ define float @minimum_float() {
define bfloat @minimum_bfloat() {
; CHECK-LABEL: @minimum_bfloat(
-; CHECK-NEXT: ret bfloat 0xR40A0
+; CHECK-NEXT: ret bfloat 5.000000e+00
;
%1 = call bfloat @llvm.minimum.bf16(bfloat 5.0, bfloat 42.0)
ret bfloat %1
@@ -289,7 +289,7 @@ define bfloat @minimum_bfloat() {
define half @minimum_half() {
; CHECK-LABEL: @minimum_half(
-; CHECK-NEXT: ret half 0xH4500
+; CHECK-NEXT: ret half 5.000000e+00
;
%1 = call half @llvm.minimum.f16(half 5.0, half 42.0)
ret half %1
@@ -297,7 +297,7 @@ define half @minimum_half() {
define float @minimum_float_p0_qnan() {
; CHECK-LABEL: @minimum_float_p0_qnan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%max = call float @llvm.minimum.f32(float 0.0, float 0x7FF8000000000000)
ret float %max
@@ -305,7 +305,7 @@ define float @minimum_float_p0_qnan() {
define float @minimum_float_qnan_p0() {
; CHECK-LABEL: @minimum_float_qnan_p0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%max = call float @llvm.minimum.f32(float 0x7FF8000000000000, float 0.0)
ret float %max
@@ -313,7 +313,7 @@ define float @minimum_float_qnan_p0() {
define float @minimum_float_p0_snan() {
; CHECK-LABEL: @minimum_float_p0_snan(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%max = call float @llvm.minimum.f32(float 0.0, float 0x7FF4000000000000)
ret float %max
@@ -321,7 +321,7 @@ define float @minimum_float_p0_snan() {
define float @minimum_float_snan_p0() {
; CHECK-LABEL: @minimum_float_snan_p0(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%max = call float @llvm.minimum.f32(float 0x7FF4000000000000, float 0.0)
ret float %max
@@ -331,7 +331,7 @@ define float @minimum_float_snan_p0() {
define <4 x float> @minimum_float_vec() {
; CHECK-LABEL: @minimum_float_vec(
-; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 5.000000e+00>
+; CHECK-NEXT: ret <4 x float> <float +qnan, float +qnan, float +qnan, float 5.000000e+00>
;
%1 = call <4 x float> @llvm.minimum.v4f32(<4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>, <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>)
ret <4 x float> %1
@@ -339,7 +339,7 @@ define <4 x float> @minimum_float_vec() {
define <4 x bfloat> @minimum_bfloat_vec() {
; CHECK-LABEL: @minimum_bfloat_vec(
-; CHECK-NEXT: ret <4 x bfloat> <bfloat 0xR7FC0, bfloat 0xR7FC0, bfloat 0xR7FC0, bfloat 0xR40A0>
+; CHECK-NEXT: ret <4 x bfloat> <bfloat +qnan, bfloat +qnan, bfloat +qnan, bfloat 5.000000e+00>
;
%1 = call <4 x bfloat> @llvm.minimum.v4bf16(<4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 0x7FF8000000000000, bfloat 42., bfloat 42.>, <4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 5., bfloat 0x7FF8000000000000, bfloat 5.>)
ret <4 x bfloat> %1
@@ -347,7 +347,7 @@ define <4 x bfloat> @minimum_bfloat_vec() {
define <4 x half> @minimum_half_vec() {
; CHECK-LABEL: @minimum_half_vec(
-; CHECK-NEXT: ret <4 x half> <half 0xH7E00, half 0xH7E00, half 0xH7E00, half 0xH4500>
+; CHECK-NEXT: ret <4 x half> <half +qnan, half +qnan, half +qnan, half 5.000000e+00>
;
%1 = call <4 x half> @llvm.minimum.v4f16(<4 x half> <half 0x7FF8000000000000, half 0x7FF8000000000000, half 42., half 42.>, <4 x half> <half 0x7FF8000000000000, half 5., half 0x7FF8000000000000, half 5.>)
ret <4 x half> %1
@@ -373,7 +373,7 @@ define float @maximum_float() {
define bfloat @maximum_bfloat() {
; CHECK-LABEL: @maximum_bfloat(
-; CHECK-NEXT: ret bfloat 0xR4228
+; CHECK-NEXT: ret bfloat 4.200000e+01
;
%1 = call bfloat @llvm.maximum.bf16(bfloat 5.0, bfloat 42.0)
ret bfloat %1
@@ -381,7 +381,7 @@ define bfloat @maximum_bfloat() {
define half @maximum_half() {
; CHECK-LABEL: @maximum_half(
-; CHECK-NEXT: ret half 0xH5140
+; CHECK-NEXT: ret half 4.200000e+01
;
%1 = call half @llvm.maximum.f16(half 5.0, half 42.0)
ret half %1
@@ -389,7 +389,7 @@ define half @maximum_half() {
define float @maximum_float_p0_qnan() {
; CHECK-LABEL: @maximum_float_p0_qnan(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%max = call float @llvm.maximum.f32(float 0.0, float 0x7FF8000000000000)
ret float %max
@@ -397,7 +397,7 @@ define float @maximum_float_p0_qnan() {
define float @maximum_float_qnan_p0() {
; CHECK-LABEL: @maximum_float_qnan_p0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%max = call float @llvm.maximum.f32(float 0x7FF8000000000000, float 0.0)
ret float %max
@@ -405,7 +405,7 @@ define float @maximum_float_qnan_p0() {
define float @maximum_float_p0_snan() {
; CHECK-LABEL: @maximum_float_p0_snan(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%max = call float @llvm.maximum.f32(float 0.0, float 0x7FF4000000000000)
ret float %max
@@ -413,7 +413,7 @@ define float @maximum_float_p0_snan() {
define float @maximum_float_snan_p0() {
; CHECK-LABEL: @maximum_float_snan_p0(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%max = call float @llvm.maximum.f32(float 0x7FF4000000000000, float 0.0)
ret float %max
@@ -423,7 +423,7 @@ define float @maximum_float_snan_p0() {
define <4 x float> @maximum_float_vec() {
; CHECK-LABEL: @maximum_float_vec(
-; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 4.200000e+01>
+; CHECK-NEXT: ret <4 x float> <float +qnan, float +qnan, float +qnan, float 4.200000e+01>
;
%1 = call <4 x float> @llvm.maximum.v4f32(<4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>, <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>)
ret <4 x float> %1
@@ -431,7 +431,7 @@ define <4 x float> @maximum_float_vec() {
define <4 x bfloat> @maximum_bfloat_vec() {
; CHECK-LABEL: @maximum_bfloat_vec(
-; CHECK-NEXT: ret <4 x bfloat> <bfloat 0xR7FC0, bfloat 0xR7FC0, bfloat 0xR7FC0, bfloat 0xR4228>
+; CHECK-NEXT: ret <4 x bfloat> <bfloat +qnan, bfloat +qnan, bfloat +qnan, bfloat 4.200000e+01>
;
%1 = call <4 x bfloat> @llvm.maximum.v4bf16(<4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 0x7FF8000000000000, bfloat 42., bfloat 42.>, <4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 5., bfloat 0x7FF8000000000000, bfloat 5.>)
ret <4 x bfloat> %1
@@ -439,7 +439,7 @@ define <4 x bfloat> @maximum_bfloat_vec() {
define <4 x half> @maximum_half_vec() {
; CHECK-LABEL: @maximum_half_vec(
-; CHECK-NEXT: ret <4 x half> <half 0xH7E00, half 0xH7E00, half 0xH7E00, half 0xH5140>
+; CHECK-NEXT: ret <4 x half> <half +qnan, half +qnan, half +qnan, half 4.200000e+01>
;
%1 = call <4 x half> @llvm.maximum.v4f16(<4 x half> <half 0x7FF8000000000000, half 0x7FF8000000000000, half 42., half 42.>, <4 x half> <half 0x7FF8000000000000, half 5., half 0x7FF8000000000000, half 5.>)
ret <4 x half> %1
@@ -513,7 +513,7 @@ define float @minimumnum_float_snan_p0() {
define bfloat @minimumnum_bfloat() {
; CHECK-LABEL: @minimumnum_bfloat(
-; CHECK-NEXT: ret bfloat 0xR40A0
+; CHECK-NEXT: ret bfloat 5.000000e+00
;
%1 = call bfloat @llvm.minimumnum.bf16(bfloat 5.0, bfloat 42.0)
ret bfloat %1
@@ -521,7 +521,7 @@ define bfloat @minimumnum_bfloat() {
define half @minimumnum_half() {
; CHECK-LABEL: @minimumnum_half(
-; CHECK-NEXT: ret half 0xH4500
+; CHECK-NEXT: ret half 5.000000e+00
;
%1 = call half @llvm.minimumnum.f16(half 5.0, half 42.0)
ret half %1
@@ -531,7 +531,7 @@ define half @minimumnum_half() {
define <4 x float> @minimumnum_float_vec() {
; CHECK-LABEL: @minimumnum_float_vec(
-; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 5.000000e+00, float 4.200000e+01, float 5.000000e+00>
+; CHECK-NEXT: ret <4 x float> <float +qnan, float 5.000000e+00, float 4.200000e+01, float 5.000000e+00>
;
%1 = call <4 x float> @llvm.minimumnum.v4f32(<4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>, <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>)
ret <4 x float> %1
@@ -539,7 +539,7 @@ define <4 x float> @minimumnum_float_vec() {
define <4 x bfloat> @minimumnum_bfloat_vec() {
; CHECK-LABEL: @minimumnum_bfloat_vec(
-; CHECK-NEXT: ret <4 x bfloat> <bfloat 0xR7FC0, bfloat 0xR40A0, bfloat 0xR4228, bfloat 0xR40A0>
+; CHECK-NEXT: ret <4 x bfloat> <bfloat +qnan, bfloat 5.000000e+00, bfloat 4.200000e+01, bfloat 5.000000e+00>
;
%1 = call <4 x bfloat> @llvm.minimumnum.v4bf16(<4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 0x7FF8000000000000, bfloat 42., bfloat 42.>, <4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 5., bfloat 0x7FF8000000000000, bfloat 5.>)
ret <4 x bfloat> %1
@@ -547,7 +547,7 @@ define <4 x bfloat> @minimumnum_bfloat_vec() {
define <4 x half> @minimumnum_half_vec() {
; CHECK-LABEL: @minimumnum_half_vec(
-; CHECK-NEXT: ret <4 x half> <half 0xH7E00, half 0xH4500, half 0xH5140, half 0xH4500>
+; CHECK-NEXT: ret <4 x half> <half +qnan, half 5.000000e+00, half 4.200000e+01, half 5.000000e+00>
;
%1 = call <4 x half> @llvm.minimumnum.v4f16(<4 x half> <half 0x7FF8000000000000, half 0x7FF8000000000000, half 42., half 42.>, <4 x half> <half 0x7FF8000000000000, half 5., half 0x7FF8000000000000, half 5.>)
ret <4 x half> %1
@@ -573,7 +573,7 @@ define float @maximumnum_float() {
define bfloat @maximumnum_bfloat() {
; CHECK-LABEL: @maximumnum_bfloat(
-; CHECK-NEXT: ret bfloat 0xR4228
+; CHECK-NEXT: ret bfloat 4.200000e+01
;
%1 = call bfloat @llvm.maximumnum.bf16(bfloat 5.0, bfloat 42.0)
ret bfloat %1
@@ -581,7 +581,7 @@ define bfloat @maximumnum_bfloat() {
define half @maximumnum_half() {
; CHECK-LABEL: @maximumnum_half(
-; CHECK-NEXT: ret half 0xH5140
+; CHECK-NEXT: ret half 4.200000e+01
;
%1 = call half @llvm.maximumnum.f16(half 5.0, half 42.0)
ret half %1
@@ -639,7 +639,7 @@ define float @maximumnum_float_snan_p0() {
define <4 x float> @maximumnum_float_vec() {
; CHECK-LABEL: @maximumnum_float_vec(
-; CHECK-NEXT: ret <4 x float> <float 0x7FF8000000000000, float 5.000000e+00, float 4.200000e+01, float 4.200000e+01>
+; CHECK-NEXT: ret <4 x float> <float +qnan, float 5.000000e+00, float 4.200000e+01, float 4.200000e+01>
;
%1 = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 42., float 42.>, <4 x float> <float 0x7FF8000000000000, float 5., float 0x7FF8000000000000, float 5.>)
ret <4 x float> %1
@@ -647,7 +647,7 @@ define <4 x float> @maximumnum_float_vec() {
define <4 x bfloat> @maximumnum_bfloat_vec() {
; CHECK-LABEL: @maximumnum_bfloat_vec(
-; CHECK-NEXT: ret <4 x bfloat> <bfloat 0xR7FC0, bfloat 0xR40A0, bfloat 0xR4228, bfloat 0xR4228>
+; CHECK-NEXT: ret <4 x bfloat> <bfloat +qnan, bfloat 5.000000e+00, bfloat 4.200000e+01, bfloat 4.200000e+01>
;
%1 = call <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 0x7FF8000000000000, bfloat 42., bfloat 42.>, <4 x bfloat> <bfloat 0x7FF8000000000000, bfloat 5., bfloat 0x7FF8000000000000, bfloat 5.>)
ret <4 x bfloat> %1
@@ -655,7 +655,7 @@ define <4 x bfloat> @maximumnum_bfloat_vec() {
define <4 x half> @maximumnum_half_vec() {
; CHECK-LABEL: @maximumnum_half_vec(
-; CHECK-NEXT: ret <4 x half> <half 0xH7E00, half 0xH4500, half 0xH5140, half 0xH5140>
+; CHECK-NEXT: ret <4 x half> <half +qnan, half 5.000000e+00, half 4.200000e+01, half 4.200000e+01>
;
%1 = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> <half 0x7FF8000000000000, half 0x7FF8000000000000, half 42., half 42.>, <4 x half> <half 0x7FF8000000000000, half 5., half 0x7FF8000000000000, half 5.>)
ret <4 x half> %1
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/sinh-cosh-intrinsics.ll b/llvm/test/Transforms/InstSimplify/ConstProp/sinh-cosh-intrinsics.ll
index 96419382c7b7f..2fb65cece3813 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/sinh-cosh-intrinsics.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/sinh-cosh-intrinsics.ll
@@ -52,7 +52,7 @@ define double @test_sinh_undef() {
define double @test_sinh_snan() {
; CHECK-LABEL: define double @test_sinh_snan() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sinh.f64(double 0x7FF0000000000001)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sinh.f64(double +snan(0x1))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.sinh.f64(double 0x7ff0000000000001)
@@ -61,7 +61,7 @@ define double @test_sinh_snan() {
define double @test_sinh_qnan() {
; CHECK-LABEL: define double @test_sinh_qnan() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sinh.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sinh.f64(double +qnan)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.sinh.f64(double 0x7ff8000000000000)
@@ -70,7 +70,7 @@ define double @test_sinh_qnan() {
define double @test_sinh_pos_inf() {
; CHECK-LABEL: define double @test_sinh_pos_inf() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sinh.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sinh.f64(double +inf)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.sinh.f64(double 0x7ff0000000000000)
@@ -79,7 +79,7 @@ define double @test_sinh_pos_inf() {
define double @test_sinh_neg_inf() {
; CHECK-LABEL: define double @test_sinh_neg_inf() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sinh.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.sinh.f64(double -inf)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.sinh.f64(double 0xfff0000000000000)
@@ -137,7 +137,7 @@ define double @test_cosh_undef() {
define double @test_cosh_snan() {
; CHECK-LABEL: define double @test_cosh_snan() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.cosh.f64(double 0x7FF0000000000001)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.cosh.f64(double +snan(0x1))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.cosh.f64(double 0x7ff0000000000001)
@@ -146,7 +146,7 @@ define double @test_cosh_snan() {
define double @test_cosh_qnan() {
; CHECK-LABEL: define double @test_cosh_qnan() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.cosh.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.cosh.f64(double +qnan)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.cosh.f64(double 0x7ff8000000000000)
@@ -155,7 +155,7 @@ define double @test_cosh_qnan() {
define double @test_cosh_pos_inf() {
; CHECK-LABEL: define double @test_cosh_pos_inf() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.cosh.f64(double 0x7FF0000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.cosh.f64(double +inf)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.cosh.f64(double 0x7ff0000000000000)
@@ -164,7 +164,7 @@ define double @test_cosh_pos_inf() {
define double @test_cosh_neg_inf() {
; CHECK-LABEL: define double @test_cosh_neg_inf() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.cosh.f64(double 0xFFF0000000000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.cosh.f64(double -inf)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.cosh.f64(double 0xfff0000000000000)
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll b/llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll
index 08ec5dfbab774..d4e3c60022876 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll
@@ -45,7 +45,7 @@ define <3 x i8> @or_commute() {
define <3 x float> @fadd() {
; CHECK-LABEL: @fadd(
-; CHECK-NEXT: ret <3 x float> <float undef, float 0x7FF8000000000000, float undef>
+; CHECK-NEXT: ret <3 x float> <float undef, float +qnan, float undef>
;
%c = fadd <3 x float> <float undef, float 42.0, float undef>, undef
ret <3 x float> %c
@@ -53,7 +53,7 @@ define <3 x float> @fadd() {
define <3 x float> @fadd_commute() {
; CHECK-LABEL: @fadd_commute(
-; CHECK-NEXT: ret <3 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float undef>
+; CHECK-NEXT: ret <3 x float> <float +qnan, float +qnan, float undef>
;
%c = fadd <3 x float> undef, <float -42.0, float 42.0, float undef>
ret <3 x float> %c
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll b/llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll
index 0e29e8c53f330..34050fcab4040 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll
@@ -45,7 +45,7 @@ define <3 x i8> @or_commute() {
define <3 x float> @fadd() {
; CHECK-LABEL: @fadd(
-; CHECK-NEXT: ret <3 x float> <float undef, float 0x7FF8000000000000, float undef>
+; CHECK-NEXT: ret <3 x float> <float undef, float +qnan, float undef>
;
%c = fadd <3 x float> <float undef, float 42.0, float undef>, undef
ret <3 x float> %c
@@ -53,7 +53,7 @@ define <3 x float> @fadd() {
define <3 x float> @fadd_commute() {
; CHECK-LABEL: @fadd_commute(
-; CHECK-NEXT: ret <3 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float undef>
+; CHECK-NEXT: ret <3 x float> <float +qnan, float +qnan, float undef>
;
%c = fadd <3 x float> undef, <float -42.0, float 42.0, float undef>
ret <3 x float> %c
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll b/llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll
index edc1260eca821..481269f68677c 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll
@@ -208,7 +208,7 @@ define <vscale x 4 x i32> @shufflevector() {
define <vscale x 4 x float> @bitcast() {
; CHECK-LABEL: @bitcast(
-; CHECK-NEXT: ret <vscale x 4 x float> splat (float 0x36A0000000000000)
+; CHECK-NEXT: ret <vscale x 4 x float> splat (float 1.401300e-45)
;
%i1 = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
%i2 = shufflevector <vscale x 4 x i32> %i1, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/vscale.ll b/llvm/test/Transforms/InstSimplify/ConstProp/vscale.ll
index 8ee6fa6e5f37f..6e94ba7f12327 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/vscale.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/vscale.ll
@@ -208,7 +208,7 @@ define <vscale x 4 x i32> @shufflevector() {
define <vscale x 4 x float> @bitcast() {
; CHECK-LABEL: @bitcast(
-; CHECK-NEXT: ret <vscale x 4 x float> splat (float 0x36A0000000000000)
+; CHECK-NEXT: ret <vscale x 4 x float> splat (float 1.401300e-45)
;
%i1 = insertelement <vscale x 4 x i32> undef, i32 1, i32 0
%i2 = shufflevector <vscale x 4 x i32> %i1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/Transforms/InstSimplify/X86/fp-nan-strictfp.ll b/llvm/test/Transforms/InstSimplify/X86/fp-nan-strictfp.ll
index a9f0662629347..f93726722c132 100644
--- a/llvm/test/Transforms/InstSimplify/X86/fp-nan-strictfp.ll
+++ b/llvm/test/Transforms/InstSimplify/X86/fp-nan-strictfp.ll
@@ -7,7 +7,7 @@
define float @fadd_nan_op0_strict(float %x) #0 {
; CHECK-LABEL: @fadd_nan_op0_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float 0x7FF8000000000000, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float +qnan, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fadd.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -16,7 +16,7 @@ define float @fadd_nan_op0_strict(float %x) #0 {
define float @fadd_nan_op0_maytrap(float %x) #0 {
; CHECK-LABEL: @fadd_nan_op0_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fadd.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -24,7 +24,7 @@ define float @fadd_nan_op0_maytrap(float %x) #0 {
define float @fadd_nan_op0_upward(float %x) #0 {
; CHECK-LABEL: @fadd_nan_op0_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fadd.f32(float 0x7FF8000000000000, float %x, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -32,7 +32,7 @@ define float @fadd_nan_op0_upward(float %x) #0 {
define float @fadd_nan_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @fadd_nan_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fadd.f32(float 0x7FF8000000000000, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -40,7 +40,7 @@ define float @fadd_nan_op0_defaultfp(float %x) #0 {
define float @fadd_nan_op1_strict(float %x) #0 {
; CHECK-LABEL: @fadd_nan_op1_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[X:%.*]], float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[X:%.*]], float +qnan, metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fadd.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -49,7 +49,7 @@ define float @fadd_nan_op1_strict(float %x) #0 {
define float @fadd_nan_op1_maytrap(float %x) #0 {
; CHECK-LABEL: @fadd_nan_op1_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fadd.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -57,7 +57,7 @@ define float @fadd_nan_op1_maytrap(float %x) #0 {
define float @fadd_nan_op1_upward(float %x) #0 {
; CHECK-LABEL: @fadd_nan_op1_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fadd.f32(float %x, float 0x7FF8000000000000, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -65,7 +65,7 @@ define float @fadd_nan_op1_upward(float %x) #0 {
define float @fadd_nan_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @fadd_nan_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fadd.f32(float %x, float 0x7FF8000000000000, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -77,7 +77,7 @@ define float @fadd_nan_op1_defaultfp(float %x) #0 {
define float @fsub_nan_op0_strict(float %x) #0 {
; CHECK-LABEL: @fsub_nan_op0_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fsub.f32(float 0x7FF8000000000000, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fsub.f32(float +qnan, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fsub.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -86,7 +86,7 @@ define float @fsub_nan_op0_strict(float %x) #0 {
define float @fsub_nan_op0_maytrap(float %x) #0 {
; CHECK-LABEL: @fsub_nan_op0_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fsub.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -94,7 +94,7 @@ define float @fsub_nan_op0_maytrap(float %x) #0 {
define float @fsub_nan_op0_upward(float %x) #0 {
; CHECK-LABEL: @fsub_nan_op0_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fsub.f32(float 0x7FF8000000000000, float %x, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -102,7 +102,7 @@ define float @fsub_nan_op0_upward(float %x) #0 {
define float @fsub_nan_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @fsub_nan_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fsub.f32(float 0x7FF8000000000000, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -110,7 +110,7 @@ define float @fsub_nan_op0_defaultfp(float %x) #0 {
define float @fsub_nan_op1_strict(float %x) #0 {
; CHECK-LABEL: @fsub_nan_op1_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fsub.f32(float [[X:%.*]], float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fsub.f32(float [[X:%.*]], float +qnan, metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fsub.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
@@ -119,7 +119,7 @@ define float @fsub_nan_op1_strict(float %x) #0 {
define float @fsub_nan_op1_maytrap(float %x) #0 {
; CHECK-LABEL: @fsub_nan_op1_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fsub.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -127,7 +127,7 @@ define float @fsub_nan_op1_maytrap(float %x) #0 {
define float @fsub_nan_op1_upward(float %x) #0 {
; CHECK-LABEL: @fsub_nan_op1_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fsub.f32(float %x, float 0x7FF8000000000000, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -135,7 +135,7 @@ define float @fsub_nan_op1_upward(float %x) #0 {
define float @fsub_nan_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @fsub_nan_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fsub.f32(float %x, float 0x7FF8000000000000, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -147,7 +147,7 @@ define float @fsub_nan_op1_defaultfp(float %x) #0 {
define float @fmul_nan_op0_strict(float %x) #0 {
; CHECK-LABEL: @fmul_nan_op0_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float 0x7FF8000000000000, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float +qnan, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fmul.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -156,7 +156,7 @@ define float @fmul_nan_op0_strict(float %x) #0 {
define float @fmul_nan_op0_maytrap(float %x) #0 {
; CHECK-LABEL: @fmul_nan_op0_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fmul.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -164,7 +164,7 @@ define float @fmul_nan_op0_maytrap(float %x) #0 {
define float @fmul_nan_op0_upward(float %x) #0 {
; CHECK-LABEL: @fmul_nan_op0_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fmul.f32(float 0x7FF8000000000000, float %x, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -172,7 +172,7 @@ define float @fmul_nan_op0_upward(float %x) #0 {
define float @fmul_nan_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @fmul_nan_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fmul.f32(float 0x7FF8000000000000, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -180,7 +180,7 @@ define float @fmul_nan_op0_defaultfp(float %x) #0 {
define float @fmul_nan_op1_strict(float %x) #0 {
; CHECK-LABEL: @fmul_nan_op1_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[X:%.*]], float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[X:%.*]], float +qnan, metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fmul.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -189,7 +189,7 @@ define float @fmul_nan_op1_strict(float %x) #0 {
define float @fmul_nan_op1_maytrap(float %x) #0 {
; CHECK-LABEL: @fmul_nan_op1_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fmul.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -197,7 +197,7 @@ define float @fmul_nan_op1_maytrap(float %x) #0 {
define float @fmul_nan_op1_upward(float %x) #0 {
; CHECK-LABEL: @fmul_nan_op1_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fmul.f32(float %x, float 0x7FF8000000000000, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -205,7 +205,7 @@ define float @fmul_nan_op1_upward(float %x) #0 {
define float @fmul_nan_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @fmul_nan_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fmul.f32(float %x, float 0x7FF8000000000000, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -217,7 +217,7 @@ define float @fmul_nan_op1_defaultfp(float %x) #0 {
define float @fdiv_nan_op0_strict(float %x) #0 {
; CHECK-LABEL: @fdiv_nan_op0_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fdiv.f32(float 0x7FF8000000000000, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fdiv.f32(float +qnan, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -226,7 +226,7 @@ define float @fdiv_nan_op0_strict(float %x) #0 {
define float @fdiv_nan_op0_maytrap(float %x) #0 {
; CHECK-LABEL: @fdiv_nan_op0_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -234,7 +234,7 @@ define float @fdiv_nan_op0_maytrap(float %x) #0 {
define float @fdiv_nan_op0_upward(float %x) #0 {
; CHECK-LABEL: @fdiv_nan_op0_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float 0x7FF8000000000000, float %x, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -242,7 +242,7 @@ define float @fdiv_nan_op0_upward(float %x) #0 {
define float @fdiv_nan_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @fdiv_nan_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float 0x7FF8000000000000, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -250,7 +250,7 @@ define float @fdiv_nan_op0_defaultfp(float %x) #0 {
define float @fdiv_nan_op1_strict(float %x) #0 {
; CHECK-LABEL: @fdiv_nan_op1_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fdiv.f32(float [[X:%.*]], float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fdiv.f32(float [[X:%.*]], float +qnan, metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -259,7 +259,7 @@ define float @fdiv_nan_op1_strict(float %x) #0 {
define float @fdiv_nan_op1_maytrap(float %x) #0 {
; CHECK-LABEL: @fdiv_nan_op1_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -267,7 +267,7 @@ define float @fdiv_nan_op1_maytrap(float %x) #0 {
define float @fdiv_nan_op1_upward(float %x) #0 {
; CHECK-LABEL: @fdiv_nan_op1_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float %x, float 0x7FF8000000000000, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -275,7 +275,7 @@ define float @fdiv_nan_op1_upward(float %x) #0 {
define float @fdiv_nan_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @fdiv_nan_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float %x, float 0x7FF8000000000000, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -287,7 +287,7 @@ define float @fdiv_nan_op1_defaultfp(float %x) #0 {
define float @frem_nan_op0_strict(float %x) #0 {
; CHECK-LABEL: @frem_nan_op0_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.frem.f32(float 0x7FF8000000000000, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.frem.f32(float +qnan, float [[X:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.frem.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -296,7 +296,7 @@ define float @frem_nan_op0_strict(float %x) #0 {
define float @frem_nan_op0_maytrap(float %x) #0 {
; CHECK-LABEL: @frem_nan_op0_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.frem.f32(float 0x7FF8000000000000, float %x, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -304,7 +304,7 @@ define float @frem_nan_op0_maytrap(float %x) #0 {
define float @frem_nan_op0_upward(float %x) #0 {
; CHECK-LABEL: @frem_nan_op0_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.frem.f32(float 0x7FF8000000000000, float %x, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -312,7 +312,7 @@ define float @frem_nan_op0_upward(float %x) #0 {
define float @frem_nan_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @frem_nan_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.frem.f32(float 0x7FF8000000000000, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -320,7 +320,7 @@ define float @frem_nan_op0_defaultfp(float %x) #0 {
define float @frem_nan_op1_strict(float %x) #0 {
; CHECK-LABEL: @frem_nan_op1_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.frem.f32(float [[X:%.*]], float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.frem.f32(float [[X:%.*]], float +qnan, metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.frem.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -329,7 +329,7 @@ define float @frem_nan_op1_strict(float %x) #0 {
define float @frem_nan_op1_maytrap(float %x) #0 {
; CHECK-LABEL: @frem_nan_op1_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.frem.f32(float %x, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -337,7 +337,7 @@ define float @frem_nan_op1_maytrap(float %x) #0 {
define float @frem_nan_op1_upward(float %x) #0 {
; CHECK-LABEL: @frem_nan_op1_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.frem.f32(float %x, float 0x7FF8000000000000, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -345,7 +345,7 @@ define float @frem_nan_op1_upward(float %x) #0 {
define float @frem_nan_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @frem_nan_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.frem.f32(float %x, float 0x7FF8000000000000, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -357,7 +357,7 @@ define float @frem_nan_op1_defaultfp(float %x) #0 {
define float @fma_nan_op0_strict(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op0_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fma.f32(float 0x7FF8000000000000, float [[X:%.*]], float [[Y:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fma.f32(float +qnan, float [[X:%.*]], float [[Y:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fma.f32(float 0x7FF8000000000000, float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -366,7 +366,7 @@ define float @fma_nan_op0_strict(float %x, float %y) #0 {
define float @fma_nan_op0_maytrap(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op0_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float 0x7FF8000000000000, float %x, float %y, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -374,7 +374,7 @@ define float @fma_nan_op0_maytrap(float %x, float %y) #0 {
define float @fma_nan_op0_upward(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op0_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float 0x7FF8000000000000, float %x, float %y, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -382,7 +382,7 @@ define float @fma_nan_op0_upward(float %x, float %y) #0 {
define float @fma_nan_op0_defaultfp(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float 0x7FF8000000000000, float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -390,7 +390,7 @@ define float @fma_nan_op0_defaultfp(float %x, float %y) #0 {
define float @fma_nan_op1_strict(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op1_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fma.f32(float [[X:%.*]], float 0x7FF8000000000000, float [[Y:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fma.f32(float [[X:%.*]], float +qnan, float [[Y:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float 0x7FF8000000000000, float %y, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -399,7 +399,7 @@ define float @fma_nan_op1_strict(float %x, float %y) #0 {
define float @fma_nan_op1_maytrap(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op1_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float 0x7FF8000000000000, float %y, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -407,7 +407,7 @@ define float @fma_nan_op1_maytrap(float %x, float %y) #0 {
define float @fma_nan_op1_upward(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op1_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float 0x7FF8000000000000, float %y, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -415,7 +415,7 @@ define float @fma_nan_op1_upward(float %x, float %y) #0 {
define float @fma_nan_op1_defaultfp(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float 0x7FF8000000000000, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -423,7 +423,7 @@ define float @fma_nan_op1_defaultfp(float %x, float %y) #0 {
define float @fma_nan_op2_strict(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op2_strict(
-; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fma.f32(float [[X:%.*]], float [[Y:%.*]], float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.experimental.constrained.fma.f32(float [[X:%.*]], float [[Y:%.*]], float +qnan, metadata !"round.dynamic", metadata !"fpexcept.strict")
; CHECK-NEXT: ret float [[R]]
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -432,7 +432,7 @@ define float @fma_nan_op2_strict(float %x, float %y) #0 {
define float @fma_nan_op2_maytrap(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op2_maytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float 0x7FF8000000000000, metadata !"round.dynamic", metadata !"fpexcept.maytrap")
ret float %r
@@ -440,7 +440,7 @@ define float @fma_nan_op2_maytrap(float %x, float %y) #0 {
define float @fma_nan_op2_upward(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op2_upward(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float 0x7FF8000000000000, metadata !"round.upward", metadata !"fpexcept.ignore")
ret float %r
@@ -448,7 +448,7 @@ define float @fma_nan_op2_upward(float %x, float %y) #0 {
define float @fma_nan_op2_defaultfp(float %x, float %y) #0 {
; CHECK-LABEL: @fma_nan_op2_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float 0x7FF8000000000000, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
diff --git a/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll b/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll
index 8d5ac063108c2..2db3d6b5924a8 100644
--- a/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll
+++ b/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll
@@ -2878,7 +2878,7 @@ define i1 @assume_olt_neg1__oeq_ninf(float %arg) {
; CHECK-SAME: float [[ARG:%.*]]) {
; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00
; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%olt.neg1 = fcmp olt float %arg, -1.0
@@ -2892,7 +2892,7 @@ define i1 @assume_olt_neg1__one_ninf(float %arg) {
; CHECK-SAME: float [[ARG:%.*]]) {
; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00
; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%olt.neg1 = fcmp olt float %arg, -1.0
@@ -2955,7 +2955,7 @@ define i1 @assume_olt_2__olt_1(float %arg) {
define i1 @assume_ogt_neginf_one_neginf(float %arg) {
; CHECK-LABEL: define i1 @assume_ogt_neginf_one_neginf(
; CHECK-SAME: float [[ARG:%.*]]) {
-; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ogt float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ogt float [[ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP_OGT_NEGINF]])
; CHECK-NEXT: ret i1 true
;
@@ -2968,9 +2968,9 @@ define i1 @assume_ogt_neginf_one_neginf(float %arg) {
define i1 @assume_ogt_neginf_oeq_posinf(float %arg) {
; CHECK-LABEL: define i1 @assume_ogt_neginf_oeq_posinf(
; CHECK-SAME: float [[ARG:%.*]]) {
-; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ogt float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ogt float [[ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP_OGT_NEGINF]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp.ogt.neginf = fcmp ogt float %arg, 0xFFF0000000000000
@@ -2982,9 +2982,9 @@ define i1 @assume_ogt_neginf_oeq_posinf(float %arg) {
define i1 @assume_ule_neginf_oeq_neginf(float %arg) {
; CHECK-LABEL: define i1 @assume_ule_neginf_oeq_neginf(
; CHECK-SAME: float [[ARG:%.*]]) {
-; CHECK-NEXT: [[CMP_ULE_NEGINF:%.*]] = fcmp ule float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP_ULE_NEGINF:%.*]] = fcmp ule float [[ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP_ULE_NEGINF]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp.ule.neginf = fcmp ule float %arg, 0xFFF0000000000000
@@ -2996,7 +2996,7 @@ define i1 @assume_ule_neginf_oeq_neginf(float %arg) {
define i1 @assume_ult_neginf_oeq_neginf(float %arg) {
; CHECK-LABEL: define i1 @assume_ult_neginf_oeq_neginf(
; CHECK-SAME: float [[ARG:%.*]]) {
-; CHECK-NEXT: [[CMP_ULT_NEGINF:%.*]] = fcmp ult float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP_ULT_NEGINF:%.*]] = fcmp ult float [[ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP_ULT_NEGINF]])
; CHECK-NEXT: ret i1 false
;
@@ -3010,9 +3010,9 @@ define i1 @assume_fabs_ogt_neginf_one_neginf(float %arg) {
; CHECK-LABEL: define i1 @assume_fabs_ogt_neginf_one_neginf(
; CHECK-SAME: float [[ARG:%.*]]) {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]])
-; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ogt float [[FABS_ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ogt float [[FABS_ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP_OGT_NEGINF]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%fabs.arg = call float @llvm.fabs.f32(float %arg)
@@ -3026,9 +3026,9 @@ define i1 @assume_fabs_ogt_neginf_one_posinf(float %arg) {
; CHECK-LABEL: define i1 @assume_fabs_ogt_neginf_one_posinf(
; CHECK-SAME: float [[ARG:%.*]]) {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]])
-; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ogt float [[FABS_ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ogt float [[FABS_ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP_OGT_NEGINF]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%fabs.arg = call float @llvm.fabs.f32(float %arg)
@@ -3042,7 +3042,7 @@ define i1 @assume_fabs_ule_neginf_oeq_neginf(float %arg) {
; CHECK-LABEL: define i1 @assume_fabs_ule_neginf_oeq_neginf(
; CHECK-SAME: float [[ARG:%.*]]) {
; CHECK-NEXT: [[FABS_ARG:%.*]] = call float @llvm.fabs.f32(float [[ARG]])
-; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ule float [[FABS_ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP_OGT_NEGINF:%.*]] = fcmp ule float [[FABS_ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP_OGT_NEGINF]])
; CHECK-NEXT: ret i1 false
;
@@ -3056,9 +3056,9 @@ define i1 @assume_fabs_ule_neginf_oeq_neginf(float %arg) {
define i1 @assume_oge_neginf_oeq_neginf(float %arg) {
; CHECK-LABEL: define i1 @assume_oge_neginf_oeq_neginf(
; CHECK-SAME: float [[ARG:%.*]]) {
-; CHECK-NEXT: [[CMP_OGE_NEGINF:%.*]] = fcmp oge float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP_OGE_NEGINF:%.*]] = fcmp oge float [[ARG]], -inf
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP_OGE_NEGINF]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0xFFF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], -inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp.oge.neginf = fcmp oge float %arg, 0xFFF0000000000000
diff --git a/llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll b/llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
index c4b83dffcd0f8..36ac86d4bb49d 100644
--- a/llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
+++ b/llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
@@ -27,10 +27,10 @@ define <4 x i32> @test2() {
define <2 x double> @test3() {
; LE-LABEL: @test3(
-; LE-NEXT: ret <2 x double> <double 0x100000000, double 0x300000002>
+; LE-NEXT: ret <2 x double> <double f0x0000000100000000, double f0x0000000300000002>
;
; BE-LABEL: @test3(
-; BE-NEXT: ret <2 x double> <double 4.940660e-324, double 0x200000003>
+; BE-NEXT: ret <2 x double> <double 4.940660e-324, double f0x0000000200000003>
;
%tmp3 = bitcast <4 x i32> < i32 0, i32 1, i32 2, i32 3 > to <2 x double>
ret <2 x double> %tmp3
@@ -38,10 +38,10 @@ define <2 x double> @test3() {
define <4 x float> @test4() {
; LE-LABEL: @test4(
-; LE-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0x36A0000000000000, float 0.000000e+00>
+; LE-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 1.401300e-45, float 0.000000e+00>
;
; BE-LABEL: @test4(
-; BE-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0x36A0000000000000>
+; BE-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.401300e-45>
;
%tmp3 = bitcast <2 x i64> < i64 0, i64 1 > to <4 x float>
ret <4 x float> %tmp3
@@ -151,7 +151,7 @@ define <3 x i64> @test14() {
; from MultiSource/Benchmarks/Bullet
define <2 x float> @foo() {
; CHECK-LABEL: @foo(
-; CHECK-NEXT: ret <2 x float> splat (float 0xFFFFFFFFE0000000)
+; CHECK-NEXT: ret <2 x float> splat (float -nan(0x3FFFFF))
;
%cast = bitcast i64 -1 to <2 x float>
ret <2 x float> %cast
@@ -160,7 +160,7 @@ define <2 x float> @foo() {
define <2 x double> @foo2() {
; CHECK-LABEL: @foo2(
-; CHECK-NEXT: ret <2 x double> splat (double 0xFFFFFFFFFFFFFFFF)
+; CHECK-NEXT: ret <2 x double> splat (double -nan(0x7FFFFFFFFFFFF))
;
%cast = bitcast i128 -1 to <2 x double>
ret <2 x double> %cast
@@ -168,7 +168,7 @@ define <2 x double> @foo2() {
define <1 x float> @foo3() {
; CHECK-LABEL: @foo3(
-; CHECK-NEXT: ret <1 x float> splat (float 0xFFFFFFFFE0000000)
+; CHECK-NEXT: ret <1 x float> splat (float -nan(0x3FFFFF))
;
%cast = bitcast i32 -1 to <1 x float>
ret <1 x float> %cast
@@ -176,7 +176,7 @@ define <1 x float> @foo3() {
define float @foo4() {
; CHECK-LABEL: @foo4(
-; CHECK-NEXT: ret float 0xFFFFFFFFE0000000
+; CHECK-NEXT: ret float -nan(0x3FFFFF)
;
%cast = bitcast <1 x i32 ><i32 -1> to float
ret float %cast
@@ -184,7 +184,7 @@ define float @foo4() {
define double @foo5() {
; CHECK-LABEL: @foo5(
-; CHECK-NEXT: ret double 0xFFFFFFFFFFFFFFFF
+; CHECK-NEXT: ret double -nan(0x7FFFFFFFFFFFF)
;
%cast = bitcast <2 x i32 ><i32 -1, i32 -1> to double
ret double %cast
@@ -192,7 +192,7 @@ define double @foo5() {
define <2 x double> @foo6() {
; CHECK-LABEL: @foo6(
-; CHECK-NEXT: ret <2 x double> splat (double 0xFFFFFFFFFFFFFFFF)
+; CHECK-NEXT: ret <2 x double> splat (double -nan(0x7FFFFFFFFFFFF))
;
%cast = bitcast <4 x i32><i32 -1, i32 -1, i32 -1, i32 -1> to <2 x double>
ret <2 x double> %cast
@@ -548,10 +548,10 @@ define <2 x b64> @bitcast_constexpr_4f32_2b64() {
define <4 x float> @bitcast_constexpr_2b64_4f32() {
; LE-LABEL: @bitcast_constexpr_2b64_4f32(
-; LE-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0x36A0000000000000, float 0.000000e+00>
+; LE-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 1.401300e-45, float 0.000000e+00>
;
; BE-LABEL: @bitcast_constexpr_2b64_4f32(
-; BE-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0x36A0000000000000>
+; BE-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.401300e-45>
;
%res = bitcast <2 x b64> <b64 0, b64 1> to <4 x float>
ret <4 x float> %res
@@ -686,10 +686,10 @@ define <4 x i32> @bitcast_constexpr_2b64_4i32_poison() {
define <2 x double> @bitcast_constexpr_4b32_2f64_poison() {
; LE-LABEL: @bitcast_constexpr_4b32_2f64_poison(
-; LE-NEXT: ret <2 x double> <double poison, double 0x300000002>
+; LE-NEXT: ret <2 x double> <double poison, double f0x0000000300000002>
;
; BE-LABEL: @bitcast_constexpr_4b32_2f64_poison(
-; BE-NEXT: ret <2 x double> <double poison, double 0x200000003>
+; BE-NEXT: ret <2 x double> <double poison, double f0x0000000200000003>
;
%res = bitcast <4 x b32> <b32 poison, b32 1, b32 2, b32 3> to <2 x double>
ret <2 x double> %res
@@ -697,10 +697,10 @@ define <2 x double> @bitcast_constexpr_4b32_2f64_poison() {
define <4 x float> @bitcast_constexpr_2b64_4f32_poison() {
; LE-LABEL: @bitcast_constexpr_2b64_4f32_poison(
-; LE-NEXT: ret <4 x float> <float poison, float poison, float 0x36A0000000000000, float 0.000000e+00>
+; LE-NEXT: ret <4 x float> <float poison, float poison, float 1.401300e-45, float 0.000000e+00>
;
; BE-LABEL: @bitcast_constexpr_2b64_4f32_poison(
-; BE-NEXT: ret <4 x float> <float poison, float poison, float 0.000000e+00, float 0x36A0000000000000>
+; BE-NEXT: ret <4 x float> <float poison, float poison, float 0.000000e+00, float 1.401300e-45>
;
%res = bitcast <2 x b64> <b64 poison, b64 1> to <4 x float>
ret <4 x float> %res
@@ -727,10 +727,10 @@ define i128 @bitcast_constexpr_2b64_i128_poison() {
define double @bitcast_constexpr_2b32_f64() {
; LE-LABEL: @bitcast_constexpr_2b32_f64(
-; LE-NEXT: ret double 0x100000002
+; LE-NEXT: ret double f0x0000000100000002
;
; BE-LABEL: @bitcast_constexpr_2b32_f64(
-; BE-NEXT: ret double 0x200000001
+; BE-NEXT: ret double f0x0000000200000001
;
%res = bitcast <2 x b32> <b32 2, b32 1> to double
ret double %res
diff --git a/llvm/test/Transforms/InstSimplify/call.ll b/llvm/test/Transforms/InstSimplify/call.ll
index cea597b4892ce..bf6748a75966b 100644
--- a/llvm/test/Transforms/InstSimplify/call.ll
+++ b/llvm/test/Transforms/InstSimplify/call.ll
@@ -996,7 +996,7 @@ declare double @llvm.fmuladd.f64(double,double,double)
define double @fma_undef_op0(double %x, double %y) {
; CHECK-LABEL: @fma_undef_op0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = call double @llvm.fma.f64(double undef, double %x, double %y)
ret double %r
@@ -1012,7 +1012,7 @@ define double @fma_poison_op0(double %x, double %y) {
define double @fma_undef_op1(double %x, double %y) {
; CHECK-LABEL: @fma_undef_op1(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = call double @llvm.fma.f64(double %x, double undef, double %y)
ret double %r
@@ -1028,7 +1028,7 @@ define double @fma_poison_op1(double %x, double %y) {
define double @fma_undef_op2(double %x, double %y) {
; CHECK-LABEL: @fma_undef_op2(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = call double @llvm.fma.f64(double %x, double %y, double undef)
ret double %r
@@ -1060,7 +1060,7 @@ define double @fma_undef_op0_poison_op2(double %x) {
define double @fmuladd_undef_op0(double %x, double %y) {
; CHECK-LABEL: @fmuladd_undef_op0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = call double @llvm.fmuladd.f64(double undef, double %x, double %y)
ret double %r
@@ -1076,7 +1076,7 @@ define double @fmuladd_poison_op0(double %x, double %y) {
define double @fmuladd_undef_op1(double %x, double %y) {
; CHECK-LABEL: @fmuladd_undef_op1(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = call double @llvm.fmuladd.f64(double %x, double undef, double %y)
ret double %r
@@ -1092,7 +1092,7 @@ define double @fmuladd_poison_op1(double %x, double %y) {
define double @fmuladd_undef_op2(double %x, double %y) {
; CHECK-LABEL: @fmuladd_undef_op2(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = call double @llvm.fmuladd.f64(double %x, double %y, double undef)
ret double %r
@@ -1124,7 +1124,7 @@ define double @fmuladd_nan_op1_poison_op2(double %x) {
define double @fma_nan_op0(double %x, double %y) {
; CHECK-LABEL: @fma_nan_op0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = call double @llvm.fma.f64(double 0x7ff8000000000000, double %x, double %y)
ret double %r
@@ -1132,7 +1132,7 @@ define double @fma_nan_op0(double %x, double %y) {
define double @fma_nan_op1(double %x, double %y) {
; CHECK-LABEL: @fma_nan_op1(
-; CHECK-NEXT: ret double 0x7FF8000000000001
+; CHECK-NEXT: ret double +nan(0x1)
;
%r = call double @llvm.fma.f64(double %x, double 0x7ff8000000000001, double %y)
ret double %r
@@ -1140,7 +1140,7 @@ define double @fma_nan_op1(double %x, double %y) {
define double @fma_nan_op2(double %x, double %y) {
; CHECK-LABEL: @fma_nan_op2(
-; CHECK-NEXT: ret double 0x7FF8000000000002
+; CHECK-NEXT: ret double +nan(0x2)
;
%r = call double @llvm.fma.f64(double %x, double %y, double 0x7ff8000000000002)
ret double %r
@@ -1148,7 +1148,7 @@ define double @fma_nan_op2(double %x, double %y) {
define double @fmuladd_nan_op0_op1(double %x) {
; CHECK-LABEL: @fmuladd_nan_op0_op1(
-; CHECK-NEXT: ret double 0x7FF8000000001234
+; CHECK-NEXT: ret double +nan(0x1234)
;
%r = call double @llvm.fmuladd.f64(double 0x7ff8000000001234, double 0x7ff800000000dead, double %x)
ret double %r
@@ -1156,7 +1156,7 @@ define double @fmuladd_nan_op0_op1(double %x) {
define double @fmuladd_nan_op0_op2(double %x) {
; CHECK-LABEL: @fmuladd_nan_op0_op2(
-; CHECK-NEXT: ret double 0x7FF8000000005678
+; CHECK-NEXT: ret double +nan(0x5678)
;
%r = call double @llvm.fmuladd.f64(double 0x7ff8000000005678, double %x, double 0x7ff800000000dead)
ret double %r
@@ -1164,7 +1164,7 @@ define double @fmuladd_nan_op0_op2(double %x) {
define double @fmuladd_nan_op1_op2(double %x) {
; CHECK-LABEL: @fmuladd_nan_op1_op2(
-; CHECK-NEXT: ret double 0x7FF80000AAAAAAAA
+; CHECK-NEXT: ret double +nan(0xAAAAAAAA)
;
%r = call double @llvm.fmuladd.f64(double %x, double 0x7ff80000aaaaaaaa, double 0x7ff800000000dead)
ret double %r
@@ -1172,7 +1172,7 @@ define double @fmuladd_nan_op1_op2(double %x) {
define double @fma_nan_multiplicand_inf_zero(double %x) {
; CHECK-LABEL: @fma_nan_multiplicand_inf_zero(
-; CHECK-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double 0x7FF0000000000000, double 0.000000e+00, double [[X:%.*]])
+; CHECK-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double +inf, double 0.000000e+00, double [[X:%.*]])
; CHECK-NEXT: ret double [[R]]
;
%r = call double @llvm.fma.f64(double 0x7ff0000000000000, double 0.0, double %x)
@@ -1181,7 +1181,7 @@ define double @fma_nan_multiplicand_inf_zero(double %x) {
define double @fma_nan_multiplicand_zero_inf(double %x) {
; CHECK-LABEL: @fma_nan_multiplicand_zero_inf(
-; CHECK-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double 0.000000e+00, double 0x7FF0000000000000, double [[X:%.*]])
+; CHECK-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double 0.000000e+00, double +inf, double [[X:%.*]])
; CHECK-NEXT: ret double [[R]]
;
%r = call double @llvm.fma.f64(double 0.0, double 0x7ff0000000000000, double %x)
@@ -1191,7 +1191,7 @@ define double @fma_nan_multiplicand_zero_inf(double %x) {
define double @fma_nan_addend_inf_neginf(double %x, i32 %y) {
; CHECK-LABEL: @fma_nan_addend_inf_neginf(
; CHECK-NEXT: [[NOTNAN:%.*]] = uitofp i32 [[Y:%.*]] to double
-; CHECK-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double 0x7FF0000000000000, double [[NOTNAN]], double 0xFFF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double +inf, double [[NOTNAN]], double -inf)
; CHECK-NEXT: ret double [[R]]
;
%notnan = uitofp i32 %y to double
@@ -1202,7 +1202,7 @@ define double @fma_nan_addend_inf_neginf(double %x, i32 %y) {
define double @fma_nan_addend_neginf_inf(double %x, i1 %y) {
; CHECK-LABEL: @fma_nan_addend_neginf_inf(
; CHECK-NEXT: [[NOTNAN:%.*]] = select i1 [[Y:%.*]], double 4.200000e+01, double -1.000000e-01
-; CHECK-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double [[NOTNAN]], double 0xFFF0000000000000, double 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @llvm.fma.f64(double [[NOTNAN]], double -inf, double +inf)
; CHECK-NEXT: ret double [[R]]
;
%notnan = select i1 %y, double 42.0, double -0.1
@@ -1212,7 +1212,7 @@ define double @fma_nan_addend_neginf_inf(double %x, i1 %y) {
define double @fmuladd_nan_multiplicand_neginf_zero(double %x) {
; CHECK-LABEL: @fmuladd_nan_multiplicand_neginf_zero(
-; CHECK-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double 0xFFF0000000000000, double 0.000000e+00, double [[X:%.*]])
+; CHECK-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double -inf, double 0.000000e+00, double [[X:%.*]])
; CHECK-NEXT: ret double [[R]]
;
%r = call double @llvm.fmuladd.f64(double 0xfff0000000000000, double 0.0, double %x)
@@ -1221,7 +1221,7 @@ define double @fmuladd_nan_multiplicand_neginf_zero(double %x) {
define double @fmuladd_nan_multiplicand_negzero_inf(double %x) {
; CHECK-LABEL: @fmuladd_nan_multiplicand_negzero_inf(
-; CHECK-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double -0.000000e+00, double 0x7FF0000000000000, double [[X:%.*]])
+; CHECK-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double -0.000000e+00, double +inf, double [[X:%.*]])
; CHECK-NEXT: ret double [[R]]
;
%r = call double @llvm.fmuladd.f64(double -0.0, double 0x7ff0000000000000, double %x)
@@ -1231,7 +1231,7 @@ define double @fmuladd_nan_multiplicand_negzero_inf(double %x) {
define double @fmuladd_nan_addend_inf_neginf(double %x, i32 %y) {
; CHECK-LABEL: @fmuladd_nan_addend_inf_neginf(
; CHECK-NEXT: [[NOTNAN:%.*]] = sitofp i32 [[Y:%.*]] to double
-; CHECK-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double 0x7FF0000000000000, double [[NOTNAN]], double 0xFFF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double +inf, double [[NOTNAN]], double -inf)
; CHECK-NEXT: ret double [[R]]
;
%notnan = sitofp i32 %y to double
@@ -1242,7 +1242,7 @@ define double @fmuladd_nan_addend_inf_neginf(double %x, i32 %y) {
define double @fmuladd_nan_addend_neginf_inf(double %x, i1 %y) {
; CHECK-LABEL: @fmuladd_nan_addend_neginf_inf(
; CHECK-NEXT: [[NOTNAN:%.*]] = select i1 [[Y:%.*]], double 4.200000e+01, double -1.000000e-01
-; CHECK-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double [[NOTNAN]], double 0xFFF0000000000000, double 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call double @llvm.fmuladd.f64(double [[NOTNAN]], double -inf, double +inf)
; CHECK-NEXT: ret double [[R]]
;
%notnan = select i1 %y, double 42.0, double -0.1
diff --git a/llvm/test/Transforms/InstSimplify/canonicalize.ll b/llvm/test/Transforms/InstSimplify/canonicalize.ll
index 15c45b34826ca..e921e80dcafc2 100644
--- a/llvm/test/Transforms/InstSimplify/canonicalize.ll
+++ b/llvm/test/Transforms/InstSimplify/canonicalize.ll
@@ -75,7 +75,7 @@ define <2 x float> @canonicalize_poison_vector() {
define float @canonicalize_denorm() {
; CHECK-LABEL: @canonicalize_denorm(
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 8388607 to float))
ret float %ret
@@ -147,7 +147,7 @@ define float @canonicalize_neg_denorm_positive_zero_input() denormal_fpenv(ieee|
define float @canonicalize_pos_denorm_dynamic_dynamic() denormal_fpenv(dynamic) {
; CHECK-LABEL: @canonicalize_pos_denorm_dynamic_dynamic(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x380FFFFFC0000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float f0x007FFFFF)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 8388607 to float))
@@ -156,7 +156,7 @@ define float @canonicalize_pos_denorm_dynamic_dynamic() denormal_fpenv(dynamic)
define float @canonicalize_neg_denorm_dynamic_dynamic() denormal_fpenv(dynamic) {
; CHECK-LABEL: @canonicalize_neg_denorm_dynamic_dynamic(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0xB80FFFFFC0000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float f0x807FFFFF)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 -2139095041 to float))
@@ -166,7 +166,7 @@ define float @canonicalize_neg_denorm_dynamic_dynamic() denormal_fpenv(dynamic)
; Dynamic output - cannot flush
define float @canonicalize_pos_denorm_dynamic_output() denormal_fpenv(dynamic|ieee) {
; CHECK-LABEL: @canonicalize_pos_denorm_dynamic_output(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x380FFFFFC0000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float f0x007FFFFF)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 8388607 to float))
@@ -176,7 +176,7 @@ define float @canonicalize_pos_denorm_dynamic_output() denormal_fpenv(dynamic|ie
; Dynamic output - cannot flush
define float @canonicalize_neg_denorm_dynamic_output() denormal_fpenv(dynamic|ieee) {
; CHECK-LABEL: @canonicalize_neg_denorm_dynamic_output(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0xB80FFFFFC0000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float f0x807FFFFF)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 -2139095041 to float))
@@ -186,7 +186,7 @@ define float @canonicalize_neg_denorm_dynamic_output() denormal_fpenv(dynamic|ie
; Dynamic input - cannot flush
define float @canonicalize_pos_denorm_dynamic_input() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @canonicalize_pos_denorm_dynamic_input(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x380FFFFFC0000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float f0x007FFFFF)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 8388607 to float))
@@ -196,7 +196,7 @@ define float @canonicalize_pos_denorm_dynamic_input() denormal_fpenv(ieee|dynami
; Dynamic input - cannot flush
define float @canonicalize_neg_denorm_dynamic_input() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @canonicalize_neg_denorm_dynamic_input(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0xB80FFFFFC0000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float f0x807FFFFF)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 -2139095041 to float))
@@ -224,7 +224,7 @@ define float @canonicalize_neg_denorm_dynamic_output_preserve_sign_input() denor
; Output is known flushed, can fold
define float @canonicalize_pos_preserve_sign_output_denorm_dynamic_input() denormal_fpenv(preservesign|dynamic) {
; CHECK-LABEL: @canonicalize_pos_preserve_sign_output_denorm_dynamic_input(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x380FFFFFC0000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float f0x007FFFFF)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 8388607 to float))
@@ -234,7 +234,7 @@ define float @canonicalize_pos_preserve_sign_output_denorm_dynamic_input() denor
; Output is known flushed, can fold
define float @canonicalize_neg_denorm_preserve_sign_output_dynamic_input() denormal_fpenv(preservesign|dynamic) {
; CHECK-LABEL: @canonicalize_neg_denorm_preserve_sign_output_dynamic_input(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0xB80FFFFFC0000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float f0x807FFFFF)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 -2139095041 to float))
@@ -243,7 +243,7 @@ define float @canonicalize_neg_denorm_preserve_sign_output_dynamic_input() denor
define float @canonicalize_inf() {
; CHECK-LABEL: @canonicalize_inf(
-; CHECK-NEXT: ret float 0x7FF0000000000000
+; CHECK-NEXT: ret float +inf
;
%ret = call float @llvm.canonicalize.f32(float 0x7FF0000000000000)
ret float %ret
@@ -251,7 +251,7 @@ define float @canonicalize_inf() {
define float @canonicalize_neg_inf() {
; CHECK-LABEL: @canonicalize_neg_inf(
-; CHECK-NEXT: ret float 0xFFF0000000000000
+; CHECK-NEXT: ret float -inf
;
%ret = call float @llvm.canonicalize.f32(float 0xFFF0000000000000)
ret float %ret
@@ -259,7 +259,7 @@ define float @canonicalize_neg_inf() {
define float @canonicalize_qnan() {
; CHECK-LABEL: @canonicalize_qnan(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float +qnan)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float 0x7FF8000000000000)
@@ -268,7 +268,7 @@ define float @canonicalize_qnan() {
define float @canonicalize_snan() {
; CHECK-LABEL: @canonicalize_snan(
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x7FF0000020000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float +snan(0x1))
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.canonicalize.f32(float bitcast (i32 2139095041 to float))
@@ -377,7 +377,7 @@ define double @canonicalize_0x00000000000001_f64() {
define double @canonicalize_inf_f64() {
; CHECK-LABEL: @canonicalize_inf_f64(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%ret = call double @llvm.canonicalize.f64(double 0x7FF0000000000000)
ret double %ret
@@ -385,7 +385,7 @@ define double @canonicalize_inf_f64() {
define double @canonicalize_ninf_f64() {
; CHECK-LABEL: @canonicalize_ninf_f64(
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%ret = call double @llvm.canonicalize.f64(double 0xFFF0000000000000)
ret double %ret
@@ -397,7 +397,7 @@ define double @canonicalize_ninf_f64() {
define half @canonicalize_zero_f16() {
; CHECK-LABEL: @canonicalize_zero_f16(
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%ret = call half @llvm.canonicalize.f16(half 0.0)
ret half %ret
@@ -405,7 +405,7 @@ define half @canonicalize_zero_f16() {
define half @canonicalize_1.0_f16() {
; CHECK-LABEL: @canonicalize_1.0_f16(
-; CHECK-NEXT: ret half 0xH3C00
+; CHECK-NEXT: ret half 1.000000e+00
;
%ret = call half @llvm.canonicalize.f16(half 1.0)
ret half %ret
@@ -413,7 +413,7 @@ define half @canonicalize_1.0_f16() {
define half @canonicalize_0x0001_f16() {
; CHECK-LABEL: @canonicalize_0x0001_f16(
-; CHECK-NEXT: ret half 0xH0001
+; CHECK-NEXT: ret half 5.960460e-08
;
%ret = call half @llvm.canonicalize.f16(half 0xH0001)
ret half %ret
@@ -421,7 +421,7 @@ define half @canonicalize_0x0001_f16() {
define half @canonicalize_inf_f16() {
; CHECK-LABEL: @canonicalize_inf_f16(
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%ret = call half @llvm.canonicalize.f16(half 0xH7C00)
ret half %ret
@@ -429,7 +429,7 @@ define half @canonicalize_inf_f16() {
define half @canonicalize_neg_inf_f16() {
; CHECK-LABEL: @canonicalize_neg_inf_f16(
-; CHECK-NEXT: ret half 0xHFC00
+; CHECK-NEXT: ret half -inf
;
%ret = call half @llvm.canonicalize.f16(half 0xHFC00)
ret half %ret
@@ -441,7 +441,7 @@ define half @canonicalize_neg_inf_f16() {
define fp128 @canonicalize_zero_fp128() {
; CHECK-LABEL: @canonicalize_zero_fp128(
-; CHECK-NEXT: ret fp128 0xL00000000000000000000000000000000
+; CHECK-NEXT: ret fp128 0.000000e+00
;
%ret = call fp128 @llvm.canonicalize.fp128(fp128 0xL00000000000000000000000000000000)
ret fp128 %ret
@@ -449,7 +449,7 @@ define fp128 @canonicalize_zero_fp128() {
define fp128 @canonicalize_1.0_fp128() {
; CHECK-LABEL: @canonicalize_1.0_fp128(
-; CHECK-NEXT: ret fp128 0xL00000000000000003FFF000000000000
+; CHECK-NEXT: ret fp128 1.000000e+00
;
%ret = call fp128 @llvm.canonicalize.fp128(fp128 0xL00000000000000003FFF000000000000)
ret fp128 %ret
@@ -457,7 +457,7 @@ define fp128 @canonicalize_1.0_fp128() {
define fp128 @canonicalize_0x00000000000000000000000000000001_fp128() {
; CHECK-LABEL: @canonicalize_0x00000000000000000000000000000001_fp128(
-; CHECK-NEXT: ret fp128 0xL00000000000000000000000000000001
+; CHECK-NEXT: ret fp128 f0x00000000000000010000000000000000
;
%ret = call fp128 @llvm.canonicalize.fp128(fp128 0xL00000000000000000000000000000001)
ret fp128 %ret
@@ -465,7 +465,7 @@ define fp128 @canonicalize_0x00000000000000000000000000000001_fp128() {
define fp128 @canonicalize_inf_fp128() {
; CHECK-LABEL: @canonicalize_inf_fp128(
-; CHECK-NEXT: ret fp128 0xL00000000000000007FFF000000000000
+; CHECK-NEXT: ret fp128 +inf
;
%ret = call fp128 @llvm.canonicalize.fp128(fp128 0xL00000000000000007FFF000000000000)
ret fp128 %ret
@@ -473,7 +473,7 @@ define fp128 @canonicalize_inf_fp128() {
define fp128 @canonicalize_neg_inf_fp128() {
; CHECK-LABEL: @canonicalize_neg_inf_fp128(
-; CHECK-NEXT: ret fp128 0xL0000000000000000FFFF000000000000
+; CHECK-NEXT: ret fp128 -inf
;
%ret = call fp128 @llvm.canonicalize.fp128(fp128 0xL0000000000000000FFFF000000000000)
ret fp128 %ret
@@ -481,7 +481,7 @@ define fp128 @canonicalize_neg_inf_fp128() {
define fp128 @canonicalize_nan_fp128() {
; CHECK-LABEL: @canonicalize_nan_fp128(
-; CHECK-NEXT: [[RET:%.*]] = call fp128 @llvm.canonicalize.f128(fp128 0xL00000000000000007FFF800000000000)
+; CHECK-NEXT: [[RET:%.*]] = call fp128 @llvm.canonicalize.f128(fp128 +qnan)
; CHECK-NEXT: ret fp128 [[RET]]
;
%ret = call fp128 @llvm.canonicalize.fp128(fp128 0xL00000000000000007FFF800000000000)
@@ -494,7 +494,7 @@ define fp128 @canonicalize_nan_fp128() {
define bfloat @canonicalize_zero_bf16() {
; CHECK-LABEL: @canonicalize_zero_bf16(
-; CHECK-NEXT: ret bfloat 0xR0000
+; CHECK-NEXT: ret bfloat 0.000000e+00
;
%ret = call bfloat @llvm.canonicalize.bf16(bfloat 0.0)
ret bfloat %ret
@@ -502,7 +502,7 @@ define bfloat @canonicalize_zero_bf16() {
define bfloat @canonicalize_1.0_bf16() {
; CHECK-LABEL: @canonicalize_1.0_bf16(
-; CHECK-NEXT: ret bfloat 0xR3F80
+; CHECK-NEXT: ret bfloat 1.000000e+00
;
%ret = call bfloat @llvm.canonicalize.bf16(bfloat 1.0)
ret bfloat %ret
@@ -510,7 +510,7 @@ define bfloat @canonicalize_1.0_bf16() {
define bfloat @canonicalize_0x0001_bf16() {
; CHECK-LABEL: @canonicalize_0x0001_bf16(
-; CHECK-NEXT: ret bfloat 0xR0001
+; CHECK-NEXT: ret bfloat 9.183550e-41
;
%ret = call bfloat @llvm.canonicalize.bf16(bfloat 0xR0001)
ret bfloat %ret
@@ -518,7 +518,7 @@ define bfloat @canonicalize_0x0001_bf16() {
define bfloat @canonicalize_inf_bf16() {
; CHECK-LABEL: @canonicalize_inf_bf16(
-; CHECK-NEXT: ret bfloat 0xR7F80
+; CHECK-NEXT: ret bfloat +inf
;
%ret = call bfloat @llvm.canonicalize.bf16(bfloat 0xR7F80)
ret bfloat %ret
@@ -526,7 +526,7 @@ define bfloat @canonicalize_inf_bf16() {
define bfloat @canonicalize_neg_inf_bf16() {
; CHECK-LABEL: @canonicalize_neg_inf_bf16(
-; CHECK-NEXT: ret bfloat 0xRFF80
+; CHECK-NEXT: ret bfloat -inf
;
%ret = call bfloat @llvm.canonicalize.bf16(bfloat 0xRFF80)
ret bfloat %ret
@@ -534,7 +534,7 @@ define bfloat @canonicalize_neg_inf_bf16() {
define bfloat @canonicalize_nan_bf16() {
; CHECK-LABEL: @canonicalize_nan_bf16(
-; CHECK-NEXT: [[RET:%.*]] = call bfloat @llvm.canonicalize.bf16(bfloat 0xR7FC0)
+; CHECK-NEXT: [[RET:%.*]] = call bfloat @llvm.canonicalize.bf16(bfloat +qnan)
; CHECK-NEXT: ret bfloat [[RET]]
;
%ret = call bfloat @llvm.canonicalize.bf16(bfloat 0xR7FC0)
@@ -543,7 +543,7 @@ define bfloat @canonicalize_nan_bf16() {
define bfloat @canonicalize_0xff_bf16() {
; CHECK-LABEL: @canonicalize_0xff_bf16(
-; CHECK-NEXT: ret bfloat 0xR00FF
+; CHECK-NEXT: ret bfloat 2.341810e-38
;
%ret = call bfloat @llvm.canonicalize.bf16(bfloat 0xR00FF)
ret bfloat %ret
@@ -563,7 +563,7 @@ define x86_fp80 @canonicalize_poison_f80() {
define x86_fp80 @canonicalize_undef_f80() {
; CHECK-LABEL: @canonicalize_undef_f80(
-; CHECK-NEXT: ret x86_fp80 0xK00000000000000000000
+; CHECK-NEXT: ret x86_fp80 0.000000e+00
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 undef)
ret x86_fp80 %ret
@@ -571,7 +571,7 @@ define x86_fp80 @canonicalize_undef_f80() {
define x86_fp80 @canonicalize_zero_f80() {
; CHECK-LABEL: @canonicalize_zero_f80(
-; CHECK-NEXT: ret x86_fp80 0xK00000000000000000000
+; CHECK-NEXT: ret x86_fp80 0.000000e+00
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xK00000000000000000000)
ret x86_fp80 %ret
@@ -579,7 +579,7 @@ define x86_fp80 @canonicalize_zero_f80() {
define x86_fp80 @canonicalize_negzero_f80() {
; CHECK-LABEL: @canonicalize_negzero_f80(
-; CHECK-NEXT: ret x86_fp80 0xK80000000000000000000
+; CHECK-NEXT: ret x86_fp80 -0.000000e+00
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xK80000000000000000000)
ret x86_fp80 %ret
@@ -587,7 +587,7 @@ define x86_fp80 @canonicalize_negzero_f80() {
define x86_fp80 @canonicalize_inf_f80() {
; CHECK-LABEL: @canonicalize_inf_f80(
-; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xK7FFF8000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 +inf)
; CHECK-NEXT: ret x86_fp80 [[RET]]
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xK7FFF8000000000000000)
@@ -596,7 +596,7 @@ define x86_fp80 @canonicalize_inf_f80() {
define x86_fp80 @canonicalize_ninf_f80() {
; CHECK-LABEL: @canonicalize_ninf_f80(
-; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xKFFFF8000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 -inf)
; CHECK-NEXT: ret x86_fp80 [[RET]]
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xKFFFF8000000000000000)
@@ -605,7 +605,7 @@ define x86_fp80 @canonicalize_ninf_f80() {
define x86_fp80 @canonicalize_qnan_f80() {
; CHECK-LABEL: @canonicalize_qnan_f80(
-; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xKFFFFC000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 -qnan)
; CHECK-NEXT: ret x86_fp80 [[RET]]
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xKFFFFC000000000000000)
@@ -614,7 +614,7 @@ define x86_fp80 @canonicalize_qnan_f80() {
define x86_fp80 @canonicalize_snan_f80() {
; CHECK-LABEL: @canonicalize_snan_f80(
-; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xKFFFFE000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 -nan(0x2000000000000000))
; CHECK-NEXT: ret x86_fp80 [[RET]]
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xKFFFFE000000000000000)
@@ -623,7 +623,7 @@ define x86_fp80 @canonicalize_snan_f80() {
define x86_fp80 @canonicalize_1.0_f80() {
; CHECK-LABEL: @canonicalize_1.0_f80(
-; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xK3FFF8000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 1.000000e+00)
; CHECK-NEXT: ret x86_fp80 [[RET]]
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xK3FFF8000000000000000)
@@ -632,7 +632,7 @@ define x86_fp80 @canonicalize_1.0_f80() {
define x86_fp80 @canonicalize_neg1.0_f80() {
; CHECK-LABEL: @canonicalize_neg1.0_f80(
-; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xKBFFF8000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 -1.000000e+00)
; CHECK-NEXT: ret x86_fp80 [[RET]]
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xKBFFF8000000000000000)
@@ -641,7 +641,7 @@ define x86_fp80 @canonicalize_neg1.0_f80() {
define x86_fp80 @canonicalize_0xK00000000000000000001_f80() {
; CHECK-LABEL: @canonicalize_0xK00000000000000000001_f80(
-; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xK00000000000000000001)
+; CHECK-NEXT: [[RET:%.*]] = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 3.645200e-4951)
; CHECK-NEXT: ret x86_fp80 [[RET]]
;
%ret = call x86_fp80 @llvm.canonicalize.f80(x86_fp80 0xK00000000000000000001)
@@ -662,7 +662,7 @@ define ppc_fp128 @canonicalize_poison_ppcf128() {
define ppc_fp128 @canonicalize_undef_ppcf128() {
; CHECK-LABEL: @canonicalize_undef_ppcf128(
-; CHECK-NEXT: ret ppc_fp128 0xM00000000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 0.000000e+00
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 undef)
ret ppc_fp128 %ret
@@ -670,7 +670,7 @@ define ppc_fp128 @canonicalize_undef_ppcf128() {
define ppc_fp128 @canonicalize_zero_ppcf128() {
; CHECK-LABEL: @canonicalize_zero_ppcf128(
-; CHECK-NEXT: ret ppc_fp128 0xM00000000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 0.000000e+00
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM00000000000000000000000000000000)
ret ppc_fp128 %ret
@@ -678,7 +678,7 @@ define ppc_fp128 @canonicalize_zero_ppcf128() {
define ppc_fp128 @canonicalize_negzero_ppcf128() {
; CHECK-LABEL: @canonicalize_negzero_ppcf128(
-; CHECK-NEXT: ret ppc_fp128 0xM80000000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 -0.000000e+00
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM80000000000000000000000000000000)
ret ppc_fp128 %ret
@@ -686,7 +686,7 @@ define ppc_fp128 @canonicalize_negzero_ppcf128() {
define ppc_fp128 @canonicalize_noncanonical_zero_0_ppcf128() {
; CHECK-LABEL: @canonicalize_noncanonical_zero_0_ppcf128(
-; CHECK-NEXT: ret ppc_fp128 0xM00000000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 0.000000e+00
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM0000000000000000ffffffffffffffff)
ret ppc_fp128 %ret
@@ -694,7 +694,7 @@ define ppc_fp128 @canonicalize_noncanonical_zero_0_ppcf128() {
define ppc_fp128 @canonicalize_noncanonical_zero_1_ppcf128() {
; CHECK-LABEL: @canonicalize_noncanonical_zero_1_ppcf128(
-; CHECK-NEXT: ret ppc_fp128 0xM00000000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 0.000000e+00
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM00000000000000000000000000000001)
ret ppc_fp128 %ret
@@ -702,7 +702,7 @@ define ppc_fp128 @canonicalize_noncanonical_zero_1_ppcf128() {
define ppc_fp128 @canonicalize_noncanonical_negzero_0_ppcf128() {
; CHECK-LABEL: @canonicalize_noncanonical_negzero_0_ppcf128(
-; CHECK-NEXT: ret ppc_fp128 0xM80000000000000000000000000000000
+; CHECK-NEXT: ret ppc_fp128 -0.000000e+00
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM8000000000000000ffffffffffffffff)
ret ppc_fp128 %ret
@@ -710,7 +710,7 @@ define ppc_fp128 @canonicalize_noncanonical_negzero_0_ppcf128() {
define ppc_fp128 @canonicalize_inf_ppcf128() {
; CHECK-LABEL: @canonicalize_inf_ppcf128(
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM7FF00000000000000000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 +inf)
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM7FF00000000000000000000000000000)
@@ -719,7 +719,7 @@ define ppc_fp128 @canonicalize_inf_ppcf128() {
define ppc_fp128 @canonicalize_neginf_ppcf128() {
; CHECK-LABEL: @canonicalize_neginf_ppcf128(
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xMFFF00000000000000000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 -inf)
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xMFFF00000000000000000000000000000)
@@ -728,7 +728,7 @@ define ppc_fp128 @canonicalize_neginf_ppcf128() {
define ppc_fp128 @canonicalize_qnan_ppcf128() {
; CHECK-LABEL: @canonicalize_qnan_ppcf128(
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xMFFF80000000000000000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 -qnan)
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xMFFF80000000000000000000000000000)
@@ -737,7 +737,7 @@ define ppc_fp128 @canonicalize_qnan_ppcf128() {
define ppc_fp128 @canonicalize_snan_ppcf128() {
; CHECK-LABEL: @canonicalize_snan_ppcf128(
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xMFFFC0000000000000000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 -nan(0x4000000000000))
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xMFFFC0000000000000000000000000000)
@@ -746,7 +746,7 @@ define ppc_fp128 @canonicalize_snan_ppcf128() {
define ppc_fp128 @canonicalize_1.0_ppcf128() {
; CHECK-LABEL: @canonicalize_1.0_ppcf128(
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM3FF00000000000000000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 1.000000e+00)
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xM3FF00000000000000000000000000000)
@@ -755,7 +755,7 @@ define ppc_fp128 @canonicalize_1.0_ppcf128() {
define ppc_fp128 @canonicalize_neg1.0_ppcf128() {
; CHECK-LABEL: @canonicalize_neg1.0_ppcf128(
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xMBFF00000000000000000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 -1.000000e+00)
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.canonicalize.ppcf128(ppc_fp128 0xMBFF00000000000000000000000000000)
@@ -768,7 +768,7 @@ define ppc_fp128 @canonicalize_neg1.0_ppcf128() {
define i1 @is_poszero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_poszero_daz_enabled_check_dynamic(
-; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0x36A0000000000000)
+; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 1.401300e-45)
; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 64)
; CHECK-NEXT: ret i1 [[IS_POS_ZERO]]
;
@@ -779,7 +779,7 @@ define i1 @is_poszero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
define i1 @is_preserve_sign_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_preserve_sign_daz_enabled_check_dynamic(
-; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0xB6A0000000000000)
+; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float -1.401300e-45)
; CHECK-NEXT: [[IS_NEG_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 32)
; CHECK-NEXT: ret i1 [[IS_NEG_ZERO]]
;
@@ -790,7 +790,7 @@ define i1 @is_preserve_sign_daz_enabled_check_dynamic() denormal_fpenv(ieee|dyna
define i1 @is_positive_zero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_positive_zero_daz_enabled_check_dynamic(
-; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0xB6A0000000000000)
+; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float -1.401300e-45)
; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 64)
; CHECK-NEXT: ret i1 [[IS_POS_ZERO]]
;
@@ -801,7 +801,7 @@ define i1 @is_positive_zero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dyna
define i1 @is_any_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_any_daz_enabled_check_dynamic(
-; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0xB6A0000000000000)
+; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float -1.401300e-45)
; CHECK-NEXT: [[IS_ANY_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 96)
; CHECK-NEXT: ret i1 [[IS_ANY_ZERO]]
;
@@ -812,7 +812,7 @@ define i1 @is_any_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
define i1 @is_not_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_not_daz_enabled_check_dynamic(
-; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0x36A0000000000000)
+; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 1.401300e-45)
; CHECK-NEXT: [[IS_NOT_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 959)
; CHECK-NEXT: ret i1 [[IS_NOT_POS_ZERO]]
;
@@ -958,7 +958,7 @@ define i1 @is_not_daz_enabled_check_positive_zero() denormal_fpenv(ieee|positive
define i1 @is_poszero_daz_enabled_check_dynamic_bitcast() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_poszero_daz_enabled_check_dynamic_bitcast(
-; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0x36A0000000000000)
+; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 1.401300e-45)
; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[CANONICAL]] to i32
; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = icmp eq i32 [[BITCAST]], 0
; CHECK-NEXT: ret i1 [[IS_POS_ZERO]]
diff --git a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-add.ll b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-add.ll
index a3d87439d74cf..b23ae275b71b7 100644
--- a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-add.ll
+++ b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-add.ll
@@ -113,7 +113,7 @@ define float @test_1_25_minus_2_rz_ftz_f() {
define double @test_zero_plus_nan_rm_d() {
; CHECK-LABEL: define double @test_zero_plus_nan_rm_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.add.rm.d(double 0.000000e+00, double 0x7FF4444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.add.rm.d(double 0.000000e+00, double +snan(0x4444400000000))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.add.rm.d(double 0.0, double 0x7ff4444400000000)
@@ -122,7 +122,7 @@ define double @test_zero_plus_nan_rm_d() {
define double @test_zero_plus_nan_rn_d() {
; CHECK-LABEL: define double @test_zero_plus_nan_rn_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.add.rn.d(double 0.000000e+00, double 0x7FF4444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.add.rn.d(double 0.000000e+00, double +snan(0x4444400000000))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.add.rn.d(double 0.0, double 0x7ff4444400000000)
@@ -131,7 +131,7 @@ define double @test_zero_plus_nan_rn_d() {
define double @test_zero_plus_nan_rp_d() {
; CHECK-LABEL: define double @test_zero_plus_nan_rp_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.add.rp.d(double 0.000000e+00, double 0x7FF4444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.add.rp.d(double 0.000000e+00, double +snan(0x4444400000000))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.add.rp.d(double 0.0, double 0x7ff4444400000000)
@@ -140,7 +140,7 @@ define double @test_zero_plus_nan_rp_d() {
define double @test_zero_plus_nan_rz_d() {
; CHECK-LABEL: define double @test_zero_plus_nan_rz_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.add.rz.d(double 0.000000e+00, double 0x7FF4444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.add.rz.d(double 0.000000e+00, double +snan(0x4444400000000))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.add.rz.d(double 0.0, double 0x7ff4444400000000)
@@ -149,7 +149,7 @@ define double @test_zero_plus_nan_rz_d() {
define float @test_zero_plus_nan_rm_f() {
; CHECK-LABEL: define float @test_zero_plus_nan_rm_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rm.f(float 0.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rm.f(float 0.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.add.rm.f(float 0.0, float 0x7FFF444400000000)
@@ -158,7 +158,7 @@ define float @test_zero_plus_nan_rm_f() {
define float @test_zero_plus_nan_rn_f() {
; CHECK-LABEL: define float @test_zero_plus_nan_rn_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rn.f(float 0.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rn.f(float 0.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.add.rn.f(float 0.0, float 0x7FFF444400000000)
@@ -167,7 +167,7 @@ define float @test_zero_plus_nan_rn_f() {
define float @test_zero_plus_nan_rp_f() {
; CHECK-LABEL: define float @test_zero_plus_nan_rp_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rp.f(float 0.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rp.f(float 0.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.add.rp.f(float 0.0, float 0x7FFF444400000000)
@@ -176,7 +176,7 @@ define float @test_zero_plus_nan_rp_f() {
define float @test_zero_plus_nan_rz_f() {
; CHECK-LABEL: define float @test_zero_plus_nan_rz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rz.f(float 0.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rz.f(float 0.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.add.rz.f(float 0.0, float 0x7FFF444400000000)
@@ -185,7 +185,7 @@ define float @test_zero_plus_nan_rz_f() {
define float @test_zero_plus_nan_rm_ftz_f() {
; CHECK-LABEL: define float @test_zero_plus_nan_rm_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rm.ftz.f(float 0.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rm.ftz.f(float 0.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.add.rm.ftz.f(float 0.0, float 0x7FFF444400000000)
@@ -194,7 +194,7 @@ define float @test_zero_plus_nan_rm_ftz_f() {
define float @test_zero_plus_nan_rn_ftz_f() {
; CHECK-LABEL: define float @test_zero_plus_nan_rn_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rn.ftz.f(float 0.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rn.ftz.f(float 0.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.add.rn.ftz.f(float 0.0, float 0x7FFF444400000000)
@@ -203,7 +203,7 @@ define float @test_zero_plus_nan_rn_ftz_f() {
define float @test_zero_plus_nan_rp_ftz_f() {
; CHECK-LABEL: define float @test_zero_plus_nan_rp_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rp.ftz.f(float 0.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rp.ftz.f(float 0.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.add.rp.ftz.f(float 0.0, float 0x7FFF444400000000)
@@ -212,7 +212,7 @@ define float @test_zero_plus_nan_rp_ftz_f() {
define float @test_zero_plus_nan_rz_ftz_f() {
; CHECK-LABEL: define float @test_zero_plus_nan_rz_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rz.ftz.f(float 0.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.add.rz.ftz.f(float 0.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.add.rz.ftz.f(float 0.0, float 0x7FFF444400000000)
@@ -228,7 +228,7 @@ define float @test_zero_plus_nan_rz_ftz_f() {
define double @test_subnorm_plus_subnorm_to_normal_rm_d() {
; CHECK-LABEL: define double @test_subnorm_plus_subnorm_to_normal_rm_d() {
-; CHECK-NEXT: ret double 0x3810000000000000
+; CHECK-NEXT: ret double f0x3810000000000000
;
%res = call double @llvm.nvvm.add.rm.d(double 0x3800000000000000, double 0x3800000000000000)
ret double %res
@@ -236,7 +236,7 @@ define double @test_subnorm_plus_subnorm_to_normal_rm_d() {
define double @test_subnorm_plus_subnorm_to_normal_rn_d() {
; CHECK-LABEL: define double @test_subnorm_plus_subnorm_to_normal_rn_d() {
-; CHECK-NEXT: ret double 0x3810000000000000
+; CHECK-NEXT: ret double f0x3810000000000000
;
%res = call double @llvm.nvvm.add.rn.d(double 0x3800000000000000, double 0x3800000000000000)
ret double %res
@@ -244,7 +244,7 @@ define double @test_subnorm_plus_subnorm_to_normal_rn_d() {
define double @test_subnorm_plus_subnorm_to_normal_rp_d() {
; CHECK-LABEL: define double @test_subnorm_plus_subnorm_to_normal_rp_d() {
-; CHECK-NEXT: ret double 0x3810000000000000
+; CHECK-NEXT: ret double f0x3810000000000000
;
%res = call double @llvm.nvvm.add.rp.d(double 0x3800000000000000, double 0x3800000000000000)
ret double %res
@@ -252,7 +252,7 @@ define double @test_subnorm_plus_subnorm_to_normal_rp_d() {
define double @test_subnorm_plus_subnorm_to_normal_rz_d() {
; CHECK-LABEL: define double @test_subnorm_plus_subnorm_to_normal_rz_d() {
-; CHECK-NEXT: ret double 0x3810000000000000
+; CHECK-NEXT: ret double f0x3810000000000000
;
%res = call double @llvm.nvvm.add.rz.d(double 0x3800000000000000, double 0x3800000000000000)
ret double %res
@@ -260,7 +260,7 @@ define double @test_subnorm_plus_subnorm_to_normal_rz_d() {
define float @test_subnorm_plus_subnorm_to_normal_rm_f() {
; CHECK-LABEL: define float @test_subnorm_plus_subnorm_to_normal_rm_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.add.rm.f(float 0x3800000000000000, float 0x3800000000000000)
ret float %res
@@ -268,7 +268,7 @@ define float @test_subnorm_plus_subnorm_to_normal_rm_f() {
define float @test_subnorm_plus_subnorm_to_normal_rn_f() {
; CHECK-LABEL: define float @test_subnorm_plus_subnorm_to_normal_rn_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.add.rn.f(float 0x3800000000000000, float 0x3800000000000000)
ret float %res
@@ -276,7 +276,7 @@ define float @test_subnorm_plus_subnorm_to_normal_rn_f() {
define float @test_subnorm_plus_subnorm_to_normal_rp_f() {
; CHECK-LABEL: define float @test_subnorm_plus_subnorm_to_normal_rp_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.add.rp.f(float 0x3800000000000000, float 0x3800000000000000)
ret float %res
@@ -284,7 +284,7 @@ define float @test_subnorm_plus_subnorm_to_normal_rp_f() {
define float @test_subnorm_plus_subnorm_to_normal_rz_f() {
; CHECK-LABEL: define float @test_subnorm_plus_subnorm_to_normal_rz_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.add.rz.f(float 0x3800000000000000, float 0x3800000000000000)
ret float %res
@@ -333,7 +333,7 @@ define float @test_subnorm_plus_subnorm_to_normal_rz_ftz_f() {
define double @test_normal_minus_subnorm_to_subnorm_rm_d() {
; CHECK-LABEL: define double @test_normal_minus_subnorm_to_subnorm_rm_d() {
-; CHECK-NEXT: ret double 0x3800000000000000
+; CHECK-NEXT: ret double f0x3800000000000000
;
%res = call double @llvm.nvvm.add.rm.d(double 0x3810000000000000, double 0xB800000000000000)
ret double %res
@@ -341,7 +341,7 @@ define double @test_normal_minus_subnorm_to_subnorm_rm_d() {
define double @test_normal_minus_subnorm_to_subnorm_rn_d() {
; CHECK-LABEL: define double @test_normal_minus_subnorm_to_subnorm_rn_d() {
-; CHECK-NEXT: ret double 0x3800000000000000
+; CHECK-NEXT: ret double f0x3800000000000000
;
%res = call double @llvm.nvvm.add.rn.d(double 0x3810000000000000, double 0xB800000000000000)
ret double %res
@@ -349,7 +349,7 @@ define double @test_normal_minus_subnorm_to_subnorm_rn_d() {
define double @test_normal_minus_subnorm_to_subnorm_rp_d() {
; CHECK-LABEL: define double @test_normal_minus_subnorm_to_subnorm_rp_d() {
-; CHECK-NEXT: ret double 0x3800000000000000
+; CHECK-NEXT: ret double f0x3800000000000000
;
%res = call double @llvm.nvvm.add.rp.d(double 0x3810000000000000, double 0xB800000000000000)
ret double %res
@@ -357,7 +357,7 @@ define double @test_normal_minus_subnorm_to_subnorm_rp_d() {
define double @test_normal_minus_subnorm_to_subnorm_rz_d() {
; CHECK-LABEL: define double @test_normal_minus_subnorm_to_subnorm_rz_d() {
-; CHECK-NEXT: ret double 0x3800000000000000
+; CHECK-NEXT: ret double f0x3800000000000000
;
%res = call double @llvm.nvvm.add.rz.d(double 0x3810000000000000, double 0xB800000000000000)
ret double %res
@@ -365,7 +365,7 @@ define double @test_normal_minus_subnorm_to_subnorm_rz_d() {
define float @test_normal_minus_subnorm_to_subnorm_rm_f() {
; CHECK-LABEL: define float @test_normal_minus_subnorm_to_subnorm_rm_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.add.rm.f(float 0x3810000000000000, float 0xB800000000000000)
ret float %res
@@ -373,7 +373,7 @@ define float @test_normal_minus_subnorm_to_subnorm_rm_f() {
define float @test_normal_minus_subnorm_to_subnorm_rn_f() {
; CHECK-LABEL: define float @test_normal_minus_subnorm_to_subnorm_rn_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.add.rn.f(float 0x3810000000000000, float 0xB800000000000000)
ret float %res
@@ -381,7 +381,7 @@ define float @test_normal_minus_subnorm_to_subnorm_rn_f() {
define float @test_normal_minus_subnorm_to_subnorm_rp_f() {
; CHECK-LABEL: define float @test_normal_minus_subnorm_to_subnorm_rp_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.add.rp.f(float 0x3810000000000000, float 0xB800000000000000)
ret float %res
@@ -389,7 +389,7 @@ define float @test_normal_minus_subnorm_to_subnorm_rp_f() {
define float @test_normal_minus_subnorm_to_subnorm_rz_f() {
; CHECK-LABEL: define float @test_normal_minus_subnorm_to_subnorm_rz_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.add.rz.f(float 0x3810000000000000, float 0xB800000000000000)
ret float %res
@@ -397,7 +397,7 @@ define float @test_normal_minus_subnorm_to_subnorm_rz_f() {
define float @test_normal_minus_subnorm_to_subnorm_rm_ftz_f() {
; CHECK-LABEL: define float @test_normal_minus_subnorm_to_subnorm_rm_ftz_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.add.rm.ftz.f(float 0x3810000000000000, float 0xB800000000000000)
ret float %res
@@ -405,7 +405,7 @@ define float @test_normal_minus_subnorm_to_subnorm_rm_ftz_f() {
define float @test_normal_minus_subnorm_to_subnorm_rn_ftz_f() {
; CHECK-LABEL: define float @test_normal_minus_subnorm_to_subnorm_rn_ftz_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.add.rn.ftz.f(float 0x3810000000000000, float 0xB800000000000000)
ret float %res
@@ -453,7 +453,7 @@ define float @test_1_plus_ulp_rn_f() {
define float @test_1_plus_ulp_rp_f() {
; CHECK-LABEL: define float @test_1_plus_ulp_rp_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.add.rp.f(float 1.0, float 0x3E60000000000000)
ret float %res
@@ -485,7 +485,7 @@ define float @test_1_plus_ulp_rn_ftz_f() {
define float @test_1_plus_ulp_rp_ftz_f() {
; CHECK-LABEL: define float @test_1_plus_ulp_rp_ftz_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.add.rp.ftz.f(float 1.0, float 0x3E60000000000000)
ret float %res
@@ -525,7 +525,7 @@ define double @test_1_plus_ulp_rn_d() {
define double @test_1_plus_ulp_rp_d() {
; CHECK-LABEL: define double @test_1_plus_ulp_rp_d() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%res = call double @llvm.nvvm.add.rp.d(double 1.0, double 0x3C90000000000000)
ret double %res
@@ -565,7 +565,7 @@ define float @test_neg_1_plus_ulp_rn_f() {
define float @test_neg_1_plus_ulp_rp_f() {
; CHECK-LABEL: define float @test_neg_1_plus_ulp_rp_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFE0000000
+; CHECK-NEXT: ret float f0xBF7FFFFF
;
%res = call float @llvm.nvvm.add.rp.f(float -1.0, float 0x3E60000000000000)
ret float %res
@@ -573,7 +573,7 @@ define float @test_neg_1_plus_ulp_rp_f() {
define float @test_neg_1_plus_ulp_rz_f() {
; CHECK-LABEL: define float @test_neg_1_plus_ulp_rz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFE0000000
+; CHECK-NEXT: ret float f0xBF7FFFFF
;
%res = call float @llvm.nvvm.add.rz.f(float -1.0, float 0x3E60000000000000)
ret float %res
@@ -597,7 +597,7 @@ define float @test_neg_1_plus_ulp_rn_ftz_f() {
define float @test_neg_1_plus_ulp_rp_ftz_f() {
; CHECK-LABEL: define float @test_neg_1_plus_ulp_rp_ftz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFE0000000
+; CHECK-NEXT: ret float f0xBF7FFFFF
;
%res = call float @llvm.nvvm.add.rp.ftz.f(float -1.0, float 0x3E60000000000000)
ret float %res
@@ -605,7 +605,7 @@ define float @test_neg_1_plus_ulp_rp_ftz_f() {
define float @test_neg_1_plus_ulp_rz_ftz_f() {
; CHECK-LABEL: define float @test_neg_1_plus_ulp_rz_ftz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFE0000000
+; CHECK-NEXT: ret float f0xBF7FFFFF
;
%res = call float @llvm.nvvm.add.rz.ftz.f(float -1.0, float 0x3E60000000000000)
ret float %res
@@ -637,7 +637,7 @@ define double @test_neg_1_plus_ulp_rn_d() {
define double @test_neg_1_plus_ulp_rp_d() {
; CHECK-LABEL: define double @test_neg_1_plus_ulp_rp_d() {
-; CHECK-NEXT: ret double 0xBFEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0xBFEFFFFFFFFFFFFF
;
%res = call double @llvm.nvvm.add.rp.d(double -1.0, double 0x3C90000000000000)
ret double %res
@@ -645,7 +645,7 @@ define double @test_neg_1_plus_ulp_rp_d() {
define double @test_neg_1_plus_ulp_rz_d() {
; CHECK-LABEL: define double @test_neg_1_plus_ulp_rz_d() {
-; CHECK-NEXT: ret double 0xBFEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0xBFEFFFFFFFFFFFFF
;
%res = call double @llvm.nvvm.add.rz.d(double -1.0, double 0x3C90000000000000)
ret double %res
@@ -661,7 +661,7 @@ define double @test_neg_1_plus_ulp_rz_d() {
define float @test_1_minus_ulp_rm_f() {
; CHECK-LABEL: define float @test_1_minus_ulp_rm_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%res = call float @llvm.nvvm.add.rm.f(float 1.0, float 0xBE60000000000000)
ret float %res
@@ -685,7 +685,7 @@ define float @test_1_minus_ulp_rp_f() {
define float @test_1_minus_ulp_rz_f() {
; CHECK-LABEL: define float @test_1_minus_ulp_rz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%res = call float @llvm.nvvm.add.rz.f(float 1.0, float 0xBE60000000000000)
ret float %res
@@ -693,7 +693,7 @@ define float @test_1_minus_ulp_rz_f() {
define float @test_1_minus_ulp_rm_ftz_f() {
; CHECK-LABEL: define float @test_1_minus_ulp_rm_ftz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%res = call float @llvm.nvvm.add.rm.ftz.f(float 1.0, float 0xBE60000000000000)
ret float %res
@@ -717,7 +717,7 @@ define float @test_1_minus_ulp_rp_ftz_f() {
define float @test_1_minus_ulp_rz_ftz_f() {
; CHECK-LABEL: define float @test_1_minus_ulp_rz_ftz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%res = call float @llvm.nvvm.add.rz.ftz.f(float 1.0, float 0xBE60000000000000)
ret float %res
@@ -733,7 +733,7 @@ define float @test_1_minus_ulp_rz_ftz_f() {
define double @test_1_minus_ulp_rm_d() {
; CHECK-LABEL: define double @test_1_minus_ulp_rm_d() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%res = call double @llvm.nvvm.add.rm.d(double 1.0, double 0xBC90000000000000)
ret double %res
@@ -757,7 +757,7 @@ define double @test_1_minus_ulp_rp_d() {
define double @test_1_minus_ulp_rz_d() {
; CHECK-LABEL: define double @test_1_minus_ulp_rz_d() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%res = call double @llvm.nvvm.add.rz.d(double 1.0, double 0xBC90000000000000)
ret double %res
@@ -773,7 +773,7 @@ define double @test_1_minus_ulp_rz_d() {
define float @test_neg_1_minus_ulp_rm_f() {
; CHECK-LABEL: define float @test_neg_1_minus_ulp_rm_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.add.rm.f(float -1.0, float 0xBE60000000000000)
ret float %res
@@ -805,7 +805,7 @@ define float @test_neg_1_minus_ulp_rz_f() {
define float @test_neg_1_minus_ulp_rm_ftz_f() {
; CHECK-LABEL: define float @test_neg_1_minus_ulp_rm_ftz_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.add.rm.ftz.f(float -1.0, float 0xBE60000000000000)
ret float %res
@@ -845,7 +845,7 @@ define float @test_neg_1_minus_ulp_rz_ftz_f() {
define double @test_neg_1_minus_ulp_rm_d() {
; CHECK-LABEL: define double @test_neg_1_minus_ulp_rm_d() {
-; CHECK-NEXT: ret double 0xBFF0000000000001
+; CHECK-NEXT: ret double f0xBFF0000000000001
;
%res = call double @llvm.nvvm.add.rm.d(double -1.0, double 0xBC90000000000000)
ret double %res
diff --git a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-div.ll b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-div.ll
index fab674cd9069b..f7a8ce7092952 100644
--- a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-div.ll
+++ b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-div.ll
@@ -148,7 +148,7 @@ define double @test_subnorm_div_1_rz_d() {
define float @test_subnorm_div_1_rm_f() {
; CHECK-LABEL: define float @test_subnorm_div_1_rm_f() {
-; CHECK-NEXT: ret float 0x36A0000000000000
+; CHECK-NEXT: ret float 1.401300e-45
;
%res = call float @llvm.nvvm.div.rm.f(float 0x36A0000000000000, float 1.0)
ret float %res
@@ -156,7 +156,7 @@ define float @test_subnorm_div_1_rm_f() {
define float @test_subnorm_div_1_rn_f() {
; CHECK-LABEL: define float @test_subnorm_div_1_rn_f() {
-; CHECK-NEXT: ret float 0x36A0000000000000
+; CHECK-NEXT: ret float 1.401300e-45
;
%res = call float @llvm.nvvm.div.rn.f(float 0x36A0000000000000, float 1.0)
ret float %res
@@ -164,7 +164,7 @@ define float @test_subnorm_div_1_rn_f() {
define float @test_subnorm_div_1_rp_f() {
; CHECK-LABEL: define float @test_subnorm_div_1_rp_f() {
-; CHECK-NEXT: ret float 0x36A0000000000000
+; CHECK-NEXT: ret float 1.401300e-45
;
%res = call float @llvm.nvvm.div.rp.f(float 0x36A0000000000000, float 1.0)
ret float %res
@@ -172,7 +172,7 @@ define float @test_subnorm_div_1_rp_f() {
define float @test_subnorm_div_1_rz_f() {
; CHECK-LABEL: define float @test_subnorm_div_1_rz_f() {
-; CHECK-NEXT: ret float 0x36A0000000000000
+; CHECK-NEXT: ret float 1.401300e-45
;
%res = call float @llvm.nvvm.div.rz.f(float 0x36A0000000000000, float 1.0)
ret float %res
@@ -219,7 +219,7 @@ define float @test_subnorm_div_1_rz_ftz_f() {
define double @test_normal_div_normal_to_subnorm_rm_d() {
; CHECK-LABEL: define double @test_normal_div_normal_to_subnorm_rm_d() {
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
%res = call double @llvm.nvvm.div.rm.d(double 0x10000000000000, double 2.0)
ret double %res
@@ -227,7 +227,7 @@ define double @test_normal_div_normal_to_subnorm_rm_d() {
define double @test_normal_div_normal_to_subnorm_rn_d() {
; CHECK-LABEL: define double @test_normal_div_normal_to_subnorm_rn_d() {
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
%res = call double @llvm.nvvm.div.rn.d(double 0x10000000000000, double 2.0)
ret double %res
@@ -235,7 +235,7 @@ define double @test_normal_div_normal_to_subnorm_rn_d() {
define double @test_normal_div_normal_to_subnorm_rp_d() {
; CHECK-LABEL: define double @test_normal_div_normal_to_subnorm_rp_d() {
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
%res = call double @llvm.nvvm.div.rp.d(double 0x10000000000000, double 2.0)
ret double %res
@@ -243,7 +243,7 @@ define double @test_normal_div_normal_to_subnorm_rp_d() {
define double @test_normal_div_normal_to_subnorm_rz_d() {
; CHECK-LABEL: define double @test_normal_div_normal_to_subnorm_rz_d() {
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
%res = call double @llvm.nvvm.div.rz.d(double 0x10000000000000, double 2.0)
ret double %res
@@ -251,7 +251,7 @@ define double @test_normal_div_normal_to_subnorm_rz_d() {
define float @test_normal_div_normal_to_subnorm_rm_f() {
; CHECK-LABEL: define float @test_normal_div_normal_to_subnorm_rm_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.div.rm.f(float 0x3810000000000000, float 2.0)
ret float %res
@@ -259,7 +259,7 @@ define float @test_normal_div_normal_to_subnorm_rm_f() {
define float @test_normal_div_normal_to_subnorm_rn_f() {
; CHECK-LABEL: define float @test_normal_div_normal_to_subnorm_rn_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.div.rn.f(float 0x3810000000000000, float 2.0)
ret float %res
@@ -267,7 +267,7 @@ define float @test_normal_div_normal_to_subnorm_rn_f() {
define float @test_normal_div_normal_to_subnorm_rp_f() {
; CHECK-LABEL: define float @test_normal_div_normal_to_subnorm_rp_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.div.rp.f(float 0x3810000000000000, float 2.0)
ret float %res
@@ -275,7 +275,7 @@ define float @test_normal_div_normal_to_subnorm_rp_f() {
define float @test_normal_div_normal_to_subnorm_rz_f() {
; CHECK-LABEL: define float @test_normal_div_normal_to_subnorm_rz_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.div.rz.f(float 0x3810000000000000, float 2.0)
ret float %res
@@ -331,7 +331,7 @@ define float @test_div_just_above_1_rm_f() {
define float @test_div_just_above_1_rn_f() {
; CHECK-LABEL: define float @test_div_just_above_1_rn_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.div.rn.f(float 0x3FF5555560000000, float 0x3FF5555540000000)
ret float %res
@@ -339,7 +339,7 @@ define float @test_div_just_above_1_rn_f() {
define float @test_div_just_above_1_rp_f() {
; CHECK-LABEL: define float @test_div_just_above_1_rp_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.div.rp.f(float 0x3FF5555560000000, float 0x3FF5555540000000)
ret float %res
@@ -363,7 +363,7 @@ define float @test_div_just_above_1_rm_ftz_f() {
define float @test_div_just_above_1_rn_ftz_f() {
; CHECK-LABEL: define float @test_div_just_above_1_rn_ftz_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.div.rn.ftz.f(float 0x3FF5555560000000, float 0x3FF5555540000000)
ret float %res
@@ -371,7 +371,7 @@ define float @test_div_just_above_1_rn_ftz_f() {
define float @test_div_just_above_1_rp_ftz_f() {
; CHECK-LABEL: define float @test_div_just_above_1_rp_ftz_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.div.rp.ftz.f(float 0x3FF5555560000000, float 0x3FF5555540000000)
ret float %res
@@ -403,7 +403,7 @@ define double @test_div_just_above_1_rm_d() {
define double @test_div_just_above_1_rn_d() {
; CHECK-LABEL: define double @test_div_just_above_1_rn_d() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%res = call double @llvm.nvvm.div.rn.d(double 0x3FF5555555555555, double 0x3FF5555555555554)
ret double %res
@@ -411,7 +411,7 @@ define double @test_div_just_above_1_rn_d() {
define double @test_div_just_above_1_rp_d() {
; CHECK-LABEL: define double @test_div_just_above_1_rp_d() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%res = call double @llvm.nvvm.div.rp.d(double 0x3FF5555555555555, double 0x3FF5555555555554)
ret double %res
@@ -435,7 +435,7 @@ define double @test_div_just_above_1_rz_d() {
define float @test_div_just_below_negative_1_rm_f() {
; CHECK-LABEL: define float @test_div_just_below_negative_1_rm_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.div.rm.f(float 0xBFF5555560000000, float 0x3FF5555540000000)
ret float %res
@@ -443,7 +443,7 @@ define float @test_div_just_below_negative_1_rm_f() {
define float @test_div_just_below_negative_1_rn_f() {
; CHECK-LABEL: define float @test_div_just_below_negative_1_rn_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.div.rn.f(float 0xBFF5555560000000, float 0x3FF5555540000000)
ret float %res
@@ -467,7 +467,7 @@ define float @test_div_just_below_negative_1_rz_f() {
define float @test_div_just_below_negative_1_rm_ftz_f() {
; CHECK-LABEL: define float @test_div_just_below_negative_1_rm_ftz_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.div.rm.ftz.f(float 0xBFF5555560000000, float 0x3FF5555540000000)
ret float %res
@@ -475,7 +475,7 @@ define float @test_div_just_below_negative_1_rm_ftz_f() {
define float @test_div_just_below_negative_1_rn_ftz_f() {
; CHECK-LABEL: define float @test_div_just_below_negative_1_rn_ftz_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.div.rn.ftz.f(float 0xBFF5555560000000, float 0x3FF5555540000000)
ret float %res
@@ -507,7 +507,7 @@ define float @test_div_just_below_negative_1_rz_ftz_f() {
define double @test_div_just_below_negative_1_rm_d() {
; CHECK-LABEL: define double @test_div_just_below_negative_1_rm_d() {
-; CHECK-NEXT: ret double 0xBFF0000000000001
+; CHECK-NEXT: ret double f0xBFF0000000000001
;
%res = call double @llvm.nvvm.div.rm.d(double 0xBFF5555555555555, double 0x3FF5555555555554)
ret double %res
@@ -515,7 +515,7 @@ define double @test_div_just_below_negative_1_rm_d() {
define double @test_div_just_below_negative_1_rn_d() {
; CHECK-LABEL: define double @test_div_just_below_negative_1_rn_d() {
-; CHECK-NEXT: ret double 0xBFF0000000000001
+; CHECK-NEXT: ret double f0xBFF0000000000001
;
%res = call double @llvm.nvvm.div.rn.d(double 0xBFF5555555555555, double 0x3FF5555555555554)
ret double %res
@@ -548,7 +548,7 @@ define double @test_div_just_below_negative_1_rz_d() {
define float @test_div_just_below_1_rm_f() {
; CHECK-LABEL: define float @test_div_just_below_1_rm_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFA0000000
+; CHECK-NEXT: ret float f0x3F7FFFFD
;
%res = call float @llvm.nvvm.div.rm.f(float 0x3FF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -556,7 +556,7 @@ define float @test_div_just_below_1_rm_f() {
define float @test_div_just_below_1_rn_f() {
; CHECK-LABEL: define float @test_div_just_below_1_rn_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFA0000000
+; CHECK-NEXT: ret float f0x3F7FFFFD
;
%res = call float @llvm.nvvm.div.rn.f(float 0x3FF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -564,7 +564,7 @@ define float @test_div_just_below_1_rn_f() {
define float @test_div_just_below_1_rp_f() {
; CHECK-LABEL: define float @test_div_just_below_1_rp_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFC0000000
+; CHECK-NEXT: ret float f0x3F7FFFFE
;
%res = call float @llvm.nvvm.div.rp.f(float 0x3FF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -572,7 +572,7 @@ define float @test_div_just_below_1_rp_f() {
define float @test_div_just_below_1_rz_f() {
; CHECK-LABEL: define float @test_div_just_below_1_rz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFA0000000
+; CHECK-NEXT: ret float f0x3F7FFFFD
;
%res = call float @llvm.nvvm.div.rz.f(float 0x3FF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -580,7 +580,7 @@ define float @test_div_just_below_1_rz_f() {
define float @test_div_just_below_1_rm_ftz_f() {
; CHECK-LABEL: define float @test_div_just_below_1_rm_ftz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFA0000000
+; CHECK-NEXT: ret float f0x3F7FFFFD
;
%res = call float @llvm.nvvm.div.rm.ftz.f(float 0x3FF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -588,7 +588,7 @@ define float @test_div_just_below_1_rm_ftz_f() {
define float @test_div_just_below_1_rn_ftz_f() {
; CHECK-LABEL: define float @test_div_just_below_1_rn_ftz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFA0000000
+; CHECK-NEXT: ret float f0x3F7FFFFD
;
%res = call float @llvm.nvvm.div.rn.ftz.f(float 0x3FF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -596,7 +596,7 @@ define float @test_div_just_below_1_rn_ftz_f() {
define float @test_div_just_below_1_rp_ftz_f() {
; CHECK-LABEL: define float @test_div_just_below_1_rp_ftz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFC0000000
+; CHECK-NEXT: ret float f0x3F7FFFFE
;
%res = call float @llvm.nvvm.div.rp.ftz.f(float 0x3FF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -604,7 +604,7 @@ define float @test_div_just_below_1_rp_ftz_f() {
define float @test_div_just_below_1_rz_ftz_f() {
; CHECK-LABEL: define float @test_div_just_below_1_rz_ftz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFA0000000
+; CHECK-NEXT: ret float f0x3F7FFFFD
;
%res = call float @llvm.nvvm.div.rz.ftz.f(float 0x3FF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -621,7 +621,7 @@ define float @test_div_just_below_1_rz_ftz_f() {
define double @test_div_just_below_1_rm_d() {
; CHECK-LABEL: define double @test_div_just_below_1_rm_d() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFA
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFA
;
%res = call double @llvm.nvvm.div.rm.d(double 0x3FF5555555555554, double 0x3FF5555555555558)
ret double %res
@@ -629,7 +629,7 @@ define double @test_div_just_below_1_rm_d() {
define double @test_div_just_below_1_rn_d() {
; CHECK-LABEL: define double @test_div_just_below_1_rn_d() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFA
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFA
;
%res = call double @llvm.nvvm.div.rn.d(double 0x3FF5555555555554, double 0x3FF5555555555558)
ret double %res
@@ -637,7 +637,7 @@ define double @test_div_just_below_1_rn_d() {
define double @test_div_just_below_1_rp_d() {
; CHECK-LABEL: define double @test_div_just_below_1_rp_d() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFB
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFB
;
%res = call double @llvm.nvvm.div.rp.d(double 0x3FF5555555555554, double 0x3FF5555555555558)
ret double %res
@@ -645,7 +645,7 @@ define double @test_div_just_below_1_rp_d() {
define double @test_div_just_below_1_rz_d() {
; CHECK-LABEL: define double @test_div_just_below_1_rz_d() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFA
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFA
;
%res = call double @llvm.nvvm.div.rz.d(double 0x3FF5555555555554, double 0x3FF5555555555558)
ret double %res
@@ -662,7 +662,7 @@ define double @test_div_just_below_1_rz_d() {
define float @test_div_just_above_negative_1_rm_f() {
; CHECK-LABEL: define float @test_div_just_above_negative_1_rm_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFC0000000
+; CHECK-NEXT: ret float f0xBF7FFFFE
;
%res = call float @llvm.nvvm.div.rm.f(float 0xBFF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -670,7 +670,7 @@ define float @test_div_just_above_negative_1_rm_f() {
define float @test_div_just_above_negative_1_rn_f() {
; CHECK-LABEL: define float @test_div_just_above_negative_1_rn_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFA0000000
+; CHECK-NEXT: ret float f0xBF7FFFFD
;
%res = call float @llvm.nvvm.div.rn.f(float 0xBFF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -678,7 +678,7 @@ define float @test_div_just_above_negative_1_rn_f() {
define float @test_div_just_above_negative_1_rp_f() {
; CHECK-LABEL: define float @test_div_just_above_negative_1_rp_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFA0000000
+; CHECK-NEXT: ret float f0xBF7FFFFD
;
%res = call float @llvm.nvvm.div.rp.f(float 0xBFF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -686,7 +686,7 @@ define float @test_div_just_above_negative_1_rp_f() {
define float @test_div_just_above_negative_1_rz_f() {
; CHECK-LABEL: define float @test_div_just_above_negative_1_rz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFA0000000
+; CHECK-NEXT: ret float f0xBF7FFFFD
;
%res = call float @llvm.nvvm.div.rz.f(float 0xBFF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -694,7 +694,7 @@ define float @test_div_just_above_negative_1_rz_f() {
define float @test_div_just_above_negative_1_rm_ftz_f() {
; CHECK-LABEL: define float @test_div_just_above_negative_1_rm_ftz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFC0000000
+; CHECK-NEXT: ret float f0xBF7FFFFE
;
%res = call float @llvm.nvvm.div.rm.ftz.f(float 0xBFF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -702,7 +702,7 @@ define float @test_div_just_above_negative_1_rm_ftz_f() {
define float @test_div_just_above_negative_1_rn_ftz_f() {
; CHECK-LABEL: define float @test_div_just_above_negative_1_rn_ftz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFA0000000
+; CHECK-NEXT: ret float f0xBF7FFFFD
;
%res = call float @llvm.nvvm.div.rn.ftz.f(float 0xBFF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -710,7 +710,7 @@ define float @test_div_just_above_negative_1_rn_ftz_f() {
define float @test_div_just_above_negative_1_rp_ftz_f() {
; CHECK-LABEL: define float @test_div_just_above_negative_1_rp_ftz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFA0000000
+; CHECK-NEXT: ret float f0xBF7FFFFD
;
%res = call float @llvm.nvvm.div.rp.ftz.f(float 0xBFF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -718,7 +718,7 @@ define float @test_div_just_above_negative_1_rp_ftz_f() {
define float @test_div_just_above_negative_1_rz_ftz_f() {
; CHECK-LABEL: define float @test_div_just_above_negative_1_rz_ftz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFA0000000
+; CHECK-NEXT: ret float f0xBF7FFFFD
;
%res = call float @llvm.nvvm.div.rz.ftz.f(float 0xBFF5555540000000, float 0x3FF5555580000000)
ret float %res
@@ -735,7 +735,7 @@ define float @test_div_just_above_negative_1_rz_ftz_f() {
define double @test_div_just_above_negative_1_rm_d() {
; CHECK-LABEL: define double @test_div_just_above_negative_1_rm_d() {
-; CHECK-NEXT: ret double 0xBFEFFFFFFFFFFFFB
+; CHECK-NEXT: ret double f0xBFEFFFFFFFFFFFFB
;
%res = call double @llvm.nvvm.div.rm.d(double 0xBFF5555555555554, double 0x3FF5555555555558)
ret double %res
@@ -743,7 +743,7 @@ define double @test_div_just_above_negative_1_rm_d() {
define double @test_div_just_above_negative_1_rn_d() {
; CHECK-LABEL: define double @test_div_just_above_negative_1_rn_d() {
-; CHECK-NEXT: ret double 0xBFEFFFFFFFFFFFFA
+; CHECK-NEXT: ret double f0xBFEFFFFFFFFFFFFA
;
%res = call double @llvm.nvvm.div.rn.d(double 0xBFF5555555555554, double 0x3FF5555555555558)
ret double %res
@@ -751,7 +751,7 @@ define double @test_div_just_above_negative_1_rn_d() {
define double @test_div_just_above_negative_1_rp_d() {
; CHECK-LABEL: define double @test_div_just_above_negative_1_rp_d() {
-; CHECK-NEXT: ret double 0xBFEFFFFFFFFFFFFA
+; CHECK-NEXT: ret double f0xBFEFFFFFFFFFFFFA
;
%res = call double @llvm.nvvm.div.rp.d(double 0xBFF5555555555554, double 0x3FF5555555555558)
ret double %res
@@ -759,7 +759,7 @@ define double @test_div_just_above_negative_1_rp_d() {
define double @test_div_just_above_negative_1_rz_d() {
; CHECK-LABEL: define double @test_div_just_above_negative_1_rz_d() {
-; CHECK-NEXT: ret double 0xBFEFFFFFFFFFFFFA
+; CHECK-NEXT: ret double f0xBFEFFFFFFFFFFFFA
;
%res = call double @llvm.nvvm.div.rz.d(double 0xBFF5555555555554, double 0x3FF5555555555558)
ret double %res
@@ -773,7 +773,7 @@ define double @test_div_just_above_negative_1_rz_d() {
define float @test_nan_div_nan_rm_f() {
; CHECK-LABEL: define float @test_nan_div_nan_rm_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rm.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rm.f(float +nan(0x3FFFF8), float +nan(0x3FFFF8))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.div.rm.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
@@ -782,7 +782,7 @@ define float @test_nan_div_nan_rm_f() {
define float @test_nan_div_nan_rn_f() {
; CHECK-LABEL: define float @test_nan_div_nan_rn_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rn.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rn.f(float +nan(0x3FFFF8), float +nan(0x3FFFF8))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.div.rn.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
@@ -791,7 +791,7 @@ define float @test_nan_div_nan_rn_f() {
define float @test_nan_div_nan_rp_f() {
; CHECK-LABEL: define float @test_nan_div_nan_rp_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rp.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rp.f(float +nan(0x3FFFF8), float +nan(0x3FFFF8))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.div.rp.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
@@ -800,7 +800,7 @@ define float @test_nan_div_nan_rp_f() {
define float @test_nan_div_nan_rz_f() {
; CHECK-LABEL: define float @test_nan_div_nan_rz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rz.f(float +nan(0x3FFFF8), float +nan(0x3FFFF8))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.div.rz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
@@ -809,7 +809,7 @@ define float @test_nan_div_nan_rz_f() {
define float @test_nan_div_nan_rm_ftz_f() {
; CHECK-LABEL: define float @test_nan_div_nan_rm_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rm.ftz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rm.ftz.f(float +nan(0x3FFFF8), float +nan(0x3FFFF8))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.div.rm.ftz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
@@ -818,7 +818,7 @@ define float @test_nan_div_nan_rm_ftz_f() {
define float @test_nan_div_nan_rn_ftz_f() {
; CHECK-LABEL: define float @test_nan_div_nan_rn_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rn.ftz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rn.ftz.f(float +nan(0x3FFFF8), float +nan(0x3FFFF8))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.div.rn.ftz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
@@ -827,7 +827,7 @@ define float @test_nan_div_nan_rn_ftz_f() {
define float @test_nan_div_nan_rp_ftz_f() {
; CHECK-LABEL: define float @test_nan_div_nan_rp_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rp.ftz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rp.ftz.f(float +nan(0x3FFFF8), float +nan(0x3FFFF8))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.div.rp.ftz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
@@ -836,7 +836,7 @@ define float @test_nan_div_nan_rp_ftz_f() {
define float @test_nan_div_nan_rz_ftz_f() {
; CHECK-LABEL: define float @test_nan_div_nan_rz_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rz.ftz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.div.rz.ftz.f(float +nan(0x3FFFF8), float +nan(0x3FFFF8))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.div.rz.ftz.f(float 0x7FFFFFFF00000000, float 0x7FFFFFFF00000000)
@@ -845,7 +845,7 @@ define float @test_nan_div_nan_rz_ftz_f() {
define double @test_nan_div_nan_rm_d() {
; CHECK-LABEL: define double @test_nan_div_nan_rm_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.div.rm.d(double 0x7FFFFFFFFFFFFFFF, double 0x7FFFFFFFFFFFFFFF)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.div.rm.d(double +nan(0x7FFFFFFFFFFFF), double +nan(0x7FFFFFFFFFFFF))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.div.rm.d(double 0x7FFFFFFFFFFFFFFF, double 0x7FFFFFFFFFFFFFFF)
@@ -854,7 +854,7 @@ define double @test_nan_div_nan_rm_d() {
define double @test_nan_div_nan_rn_d() {
; CHECK-LABEL: define double @test_nan_div_nan_rn_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.div.rn.d(double 0x7FFFFFFFFFFFFFFF, double 0x7FFFFFFFFFFFFFFF)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.div.rn.d(double +nan(0x7FFFFFFFFFFFF), double +nan(0x7FFFFFFFFFFFF))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.div.rn.d(double 0x7FFFFFFFFFFFFFFF, double 0x7FFFFFFFFFFFFFFF)
@@ -863,7 +863,7 @@ define double @test_nan_div_nan_rn_d() {
define double @test_nan_div_nan_rp_d() {
; CHECK-LABEL: define double @test_nan_div_nan_rp_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.div.rp.d(double 0x7FFFFFFFFFFFFFFF, double 0x7FFFFFFFFFFFFFFF)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.div.rp.d(double +nan(0x7FFFFFFFFFFFF), double +nan(0x7FFFFFFFFFFFF))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.div.rp.d(double 0x7FFFFFFFFFFFFFFF, double 0x7FFFFFFFFFFFFFFF)
@@ -872,7 +872,7 @@ define double @test_nan_div_nan_rp_d() {
define double @test_nan_div_nan_rz_d() {
; CHECK-LABEL: define double @test_nan_div_nan_rz_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.div.rz.d(double 0x7FFFFFFFFFFFFFFF, double 0x7FFFFFFFFFFFFFFF)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.div.rz.d(double +nan(0x7FFFFFFFFFFFF), double +nan(0x7FFFFFFFFFFFF))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.div.rz.d(double 0x7FFFFFFFFFFFFFFF, double 0x7FFFFFFFFFFFFFFF)
diff --git a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fma.ll b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fma.ll
index d52ff1ce66440..24174fdc9fce8 100644
--- a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fma.ll
+++ b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fma.ll
@@ -114,7 +114,7 @@ define float @test_fma_2_3_4_rz_ftz_f() {
define double @test_fma_subnorm_to_norm_rm_d() {
; CHECK-LABEL: define double @test_fma_subnorm_to_norm_rm_d() {
-; CHECK-NEXT: ret double 0x10000000000000
+; CHECK-NEXT: ret double f0x0010000000000000
;
%res = call double @llvm.nvvm.fma.rm.d(double 0x0008000000000000, double 2.0, double 0.0)
ret double %res
@@ -122,7 +122,7 @@ define double @test_fma_subnorm_to_norm_rm_d() {
define double @test_fma_subnorm_to_norm_rn_d() {
; CHECK-LABEL: define double @test_fma_subnorm_to_norm_rn_d() {
-; CHECK-NEXT: ret double 0x10000000000000
+; CHECK-NEXT: ret double f0x0010000000000000
;
%res = call double @llvm.nvvm.fma.rn.d(double 0x0008000000000000, double 2.0, double 0.0)
ret double %res
@@ -130,7 +130,7 @@ define double @test_fma_subnorm_to_norm_rn_d() {
define double @test_fma_subnorm_to_norm_rp_d() {
; CHECK-LABEL: define double @test_fma_subnorm_to_norm_rp_d() {
-; CHECK-NEXT: ret double 0x10000000000000
+; CHECK-NEXT: ret double f0x0010000000000000
;
%res = call double @llvm.nvvm.fma.rp.d(double 0x0008000000000000, double 2.0, double 0.0)
ret double %res
@@ -138,7 +138,7 @@ define double @test_fma_subnorm_to_norm_rp_d() {
define double @test_fma_subnorm_to_norm_rz_d() {
; CHECK-LABEL: define double @test_fma_subnorm_to_norm_rz_d() {
-; CHECK-NEXT: ret double 0x10000000000000
+; CHECK-NEXT: ret double f0x0010000000000000
;
%res = call double @llvm.nvvm.fma.rz.d(double 0x0008000000000000, double 2.0, double 0.0)
ret double %res
@@ -146,7 +146,7 @@ define double @test_fma_subnorm_to_norm_rz_d() {
define float @test_fma_subnorm_to_norm_rm_f() {
; CHECK-LABEL: define float @test_fma_subnorm_to_norm_rm_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.fma.rm.f(float 0x3800000000000000, float 2.0, float 0.0)
ret float %res
@@ -154,7 +154,7 @@ define float @test_fma_subnorm_to_norm_rm_f() {
define float @test_fma_subnorm_to_norm_rn_f() {
; CHECK-LABEL: define float @test_fma_subnorm_to_norm_rn_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.fma.rn.f(float 0x3800000000000000, float 2.0, float 0.0)
ret float %res
@@ -162,7 +162,7 @@ define float @test_fma_subnorm_to_norm_rn_f() {
define float @test_fma_subnorm_to_norm_rp_f() {
; CHECK-LABEL: define float @test_fma_subnorm_to_norm_rp_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.fma.rp.f(float 0x3800000000000000, float 2.0, float 0.0)
ret float %res
@@ -170,7 +170,7 @@ define float @test_fma_subnorm_to_norm_rp_f() {
define float @test_fma_subnorm_to_norm_rz_f() {
; CHECK-LABEL: define float @test_fma_subnorm_to_norm_rz_f() {
-; CHECK-NEXT: ret float 0x3810000000000000
+; CHECK-NEXT: ret float f0x00800000
;
%res = call float @llvm.nvvm.fma.rz.f(float 0x3800000000000000, float 2.0, float 0.0)
ret float %res
@@ -218,7 +218,7 @@ define float @test_fma_subnorm_to_norm_rz_ftz_f() {
define double @test_fma_norm_to_subnorm_rm_d() {
; CHECK-LABEL: define double @test_fma_norm_to_subnorm_rm_d() {
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
%res = call double @llvm.nvvm.fma.rm.d(double 0x10000000000000, double 0.5, double 0.0)
ret double %res
@@ -226,7 +226,7 @@ define double @test_fma_norm_to_subnorm_rm_d() {
define double @test_fma_norm_to_subnorm_rn_d() {
; CHECK-LABEL: define double @test_fma_norm_to_subnorm_rn_d() {
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
%res = call double @llvm.nvvm.fma.rn.d(double 0x10000000000000, double 0.5, double 0.0)
ret double %res
@@ -234,7 +234,7 @@ define double @test_fma_norm_to_subnorm_rn_d() {
define double @test_fma_norm_to_subnorm_rp_d() {
; CHECK-LABEL: define double @test_fma_norm_to_subnorm_rp_d() {
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
%res = call double @llvm.nvvm.fma.rp.d(double 0x10000000000000, double 0.5, double 0.0)
ret double %res
@@ -242,7 +242,7 @@ define double @test_fma_norm_to_subnorm_rp_d() {
define double @test_fma_norm_to_subnorm_rz_d() {
; CHECK-LABEL: define double @test_fma_norm_to_subnorm_rz_d() {
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
%res = call double @llvm.nvvm.fma.rz.d(double 0x10000000000000, double 0.5, double 0.0)
ret double %res
@@ -250,7 +250,7 @@ define double @test_fma_norm_to_subnorm_rz_d() {
define float @test_fma_norm_to_subnorm_rm_f() {
; CHECK-LABEL: define float @test_fma_norm_to_subnorm_rm_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.fma.rm.f(float 0x3810000000000000, float 0.5, float 0.0)
ret float %res
@@ -258,7 +258,7 @@ define float @test_fma_norm_to_subnorm_rm_f() {
define float @test_fma_norm_to_subnorm_rn_f() {
; CHECK-LABEL: define float @test_fma_norm_to_subnorm_rn_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.fma.rn.f(float 0x3810000000000000, float 0.5, float 0.0)
ret float %res
@@ -266,7 +266,7 @@ define float @test_fma_norm_to_subnorm_rn_f() {
define float @test_fma_norm_to_subnorm_rp_f() {
; CHECK-LABEL: define float @test_fma_norm_to_subnorm_rp_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.fma.rp.f(float 0x3810000000000000, float 0.5, float 0.0)
ret float %res
@@ -274,7 +274,7 @@ define float @test_fma_norm_to_subnorm_rp_f() {
define float @test_fma_norm_to_subnorm_rz_f() {
; CHECK-LABEL: define float @test_fma_norm_to_subnorm_rz_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.fma.rz.f(float 0x3810000000000000, float 0.5, float 0.0)
ret float %res
@@ -320,7 +320,7 @@ define float @test_fma_norm_to_subnorm_rz_ftz_f() {
define double @test_fma_nan_rm_d() {
; CHECK-LABEL: define double @test_fma_nan_rm_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.fma.rm.d(double 0x7FF8000000000000, double 1.000000e+00, double 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.fma.rm.d(double +qnan, double 1.000000e+00, double 0.000000e+00)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.fma.rm.d(double 0x7FF8000000000000, double 1.0, double 0.0)
@@ -329,7 +329,7 @@ define double @test_fma_nan_rm_d() {
define double @test_fma_nan_rn_d() {
; CHECK-LABEL: define double @test_fma_nan_rn_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.fma.rn.d(double 0x7FF8000000000000, double 1.000000e+00, double 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.fma.rn.d(double +qnan, double 1.000000e+00, double 0.000000e+00)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.fma.rn.d(double 0x7FF8000000000000, double 1.0, double 0.0)
@@ -338,7 +338,7 @@ define double @test_fma_nan_rn_d() {
define double @test_fma_nan_rp_d() {
; CHECK-LABEL: define double @test_fma_nan_rp_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.fma.rp.d(double 0x7FF8000000000000, double 1.000000e+00, double 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.fma.rp.d(double +qnan, double 1.000000e+00, double 0.000000e+00)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.fma.rp.d(double 0x7FF8000000000000, double 1.0, double 0.0)
@@ -347,7 +347,7 @@ define double @test_fma_nan_rp_d() {
define double @test_fma_nan_rz_d() {
; CHECK-LABEL: define double @test_fma_nan_rz_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.fma.rz.d(double 0x7FF8000000000000, double 1.000000e+00, double 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.fma.rz.d(double +qnan, double 1.000000e+00, double 0.000000e+00)
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.fma.rz.d(double 0x7FF8000000000000, double 1.0, double 0.0)
@@ -356,7 +356,7 @@ define double @test_fma_nan_rz_d() {
define float @test_fma_nan_rm_f() {
; CHECK-LABEL: define float @test_fma_nan_rm_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rm.f(float 0x7FFC000000000000, float 1.000000e+00, float 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rm.f(float +nan(0x200000), float 1.000000e+00, float 0.000000e+00)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.fma.rm.f(float 0x7FFC000000000000, float 1.0, float 0.0)
@@ -365,7 +365,7 @@ define float @test_fma_nan_rm_f() {
define float @test_fma_nan_rn_f() {
; CHECK-LABEL: define float @test_fma_nan_rn_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rn.f(float 0x7FFC000000000000, float 1.000000e+00, float 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rn.f(float +nan(0x200000), float 1.000000e+00, float 0.000000e+00)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.fma.rn.f(float 0x7FFC000000000000, float 1.0, float 0.0)
@@ -374,7 +374,7 @@ define float @test_fma_nan_rn_f() {
define float @test_fma_nan_rp_f() {
; CHECK-LABEL: define float @test_fma_nan_rp_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rp.f(float 0x7FFC000000000000, float 1.000000e+00, float 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rp.f(float +nan(0x200000), float 1.000000e+00, float 0.000000e+00)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.fma.rp.f(float 0x7FFC000000000000, float 1.0, float 0.0)
@@ -383,7 +383,7 @@ define float @test_fma_nan_rp_f() {
define float @test_fma_nan_rz_f() {
; CHECK-LABEL: define float @test_fma_nan_rz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rz.f(float 0x7FFC000000000000, float 1.000000e+00, float 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rz.f(float +nan(0x200000), float 1.000000e+00, float 0.000000e+00)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.fma.rz.f(float 0x7FFC000000000000, float 1.0, float 0.0)
@@ -392,7 +392,7 @@ define float @test_fma_nan_rz_f() {
define float @test_fma_nan_rm_ftz_f() {
; CHECK-LABEL: define float @test_fma_nan_rm_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rm.ftz.f(float 0x7FFC000000000000, float 1.000000e+00, float 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rm.ftz.f(float +nan(0x200000), float 1.000000e+00, float 0.000000e+00)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.fma.rm.ftz.f(float 0x7FFC000000000000, float 1.0, float 0.0)
@@ -401,7 +401,7 @@ define float @test_fma_nan_rm_ftz_f() {
define float @test_fma_nan_rn_ftz_f() {
; CHECK-LABEL: define float @test_fma_nan_rn_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rn.ftz.f(float 0x7FFC000000000000, float 1.000000e+00, float 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rn.ftz.f(float +nan(0x200000), float 1.000000e+00, float 0.000000e+00)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.fma.rn.ftz.f(float 0x7FFC000000000000, float 1.0, float 0.0)
@@ -410,7 +410,7 @@ define float @test_fma_nan_rn_ftz_f() {
define float @test_fma_nan_rp_ftz_f() {
; CHECK-LABEL: define float @test_fma_nan_rp_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rp.ftz.f(float 0x7FFC000000000000, float 1.000000e+00, float 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rp.ftz.f(float +nan(0x200000), float 1.000000e+00, float 0.000000e+00)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.fma.rp.ftz.f(float 0x7FFC000000000000, float 1.0, float 0.0)
@@ -419,7 +419,7 @@ define float @test_fma_nan_rp_ftz_f() {
define float @test_fma_nan_rz_ftz_f() {
; CHECK-LABEL: define float @test_fma_nan_rz_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rz.ftz.f(float 0x7FFC000000000000, float 1.000000e+00, float 0.000000e+00)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fma.rz.ftz.f(float +nan(0x200000), float 1.000000e+00, float 0.000000e+00)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.fma.rz.ftz.f(float 0x7FFC000000000000, float 1.0, float 0.0)
@@ -451,7 +451,7 @@ define float @test_fma_1_plus_ulp_rn_f() {
define float @test_fma_1_plus_ulp_rp_f() {
; CHECK-LABEL: define float @test_fma_1_plus_ulp_rp_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.fma.rp.f(float 1.0, float 1.0, float 0x3E60000000000000)
ret float %res
@@ -483,7 +483,7 @@ define float @test_fma_1_plus_ulp_rn_ftz_f() {
define float @test_fma_1_plus_ulp_rp_ftz_f() {
; CHECK-LABEL: define float @test_fma_1_plus_ulp_rp_ftz_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.fma.rp.ftz.f(float 1.0, float 1.0, float 0x3E60000000000000)
ret float %res
@@ -523,7 +523,7 @@ define double @test_fma_1_plus_ulp_rn_d() {
define double @test_fma_1_plus_ulp_rp_d() {
; CHECK-LABEL: define double @test_fma_1_plus_ulp_rp_d() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%res = call double @llvm.nvvm.fma.rp.d(double 1.0, double 1.0, double 0x3C90000000000000)
ret double %res
@@ -563,7 +563,7 @@ define float @test_fma_neg_1_plus_ulp_rn_f() {
define float @test_fma_neg_1_plus_ulp_rp_f() {
; CHECK-LABEL: define float @test_fma_neg_1_plus_ulp_rp_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFE0000000
+; CHECK-NEXT: ret float f0xBF7FFFFF
;
%res = call float @llvm.nvvm.fma.rp.f(float 1.0, float -1.0, float 0x3E60000000000000)
ret float %res
@@ -571,7 +571,7 @@ define float @test_fma_neg_1_plus_ulp_rp_f() {
define float @test_fma_neg_1_plus_ulp_rz_f() {
; CHECK-LABEL: define float @test_fma_neg_1_plus_ulp_rz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFE0000000
+; CHECK-NEXT: ret float f0xBF7FFFFF
;
%res = call float @llvm.nvvm.fma.rz.f(float 1.0, float -1.0, float 0x3E60000000000000)
ret float %res
@@ -595,7 +595,7 @@ define float @test_fma_neg_1_plus_ulp_rn_ftz_f() {
define float @test_fma_neg_1_plus_ulp_rp_ftz_f() {
; CHECK-LABEL: define float @test_fma_neg_1_plus_ulp_rp_ftz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFE0000000
+; CHECK-NEXT: ret float f0xBF7FFFFF
;
%res = call float @llvm.nvvm.fma.rp.ftz.f(float 1.0, float -1.0, float 0x3E60000000000000)
ret float %res
@@ -603,7 +603,7 @@ define float @test_fma_neg_1_plus_ulp_rp_ftz_f() {
define float @test_fma_neg_1_plus_ulp_rz_ftz_f() {
; CHECK-LABEL: define float @test_fma_neg_1_plus_ulp_rz_ftz_f() {
-; CHECK-NEXT: ret float 0xBFEFFFFFE0000000
+; CHECK-NEXT: ret float f0xBF7FFFFF
;
%res = call float @llvm.nvvm.fma.rz.ftz.f(float 1.0, float -1.0, float 0x3E60000000000000)
ret float %res
@@ -635,7 +635,7 @@ define double @test_fma_neg_1_plus_ulp_rn_d() {
define double @test_fma_neg_1_plus_ulp_rp_d() {
; CHECK-LABEL: define double @test_fma_neg_1_plus_ulp_rp_d() {
-; CHECK-NEXT: ret double 0xBFEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0xBFEFFFFFFFFFFFFF
;
%res = call double @llvm.nvvm.fma.rp.d(double 1.0, double -1.0, double 0x3C90000000000000)
ret double %res
@@ -643,7 +643,7 @@ define double @test_fma_neg_1_plus_ulp_rp_d() {
define double @test_fma_neg_1_plus_ulp_rz_d() {
; CHECK-LABEL: define double @test_fma_neg_1_plus_ulp_rz_d() {
-; CHECK-NEXT: ret double 0xBFEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0xBFEFFFFFFFFFFFFF
;
%res = call double @llvm.nvvm.fma.rz.d(double 1.0, double -1.0, double 0x3C90000000000000)
ret double %res
@@ -659,7 +659,7 @@ define double @test_fma_neg_1_plus_ulp_rz_d() {
define float @test_fma_1_minus_ulp_rm_f() {
; CHECK-LABEL: define float @test_fma_1_minus_ulp_rm_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%res = call float @llvm.nvvm.fma.rm.f(float 1.0, float 1.0, float 0xBE60000000000000)
ret float %res
@@ -683,7 +683,7 @@ define float @test_fma_1_minus_ulp_rp_f() {
define float @test_fma_1_minus_ulp_rz_f() {
; CHECK-LABEL: define float @test_fma_1_minus_ulp_rz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%res = call float @llvm.nvvm.fma.rz.f(float 1.0, float 1.0, float 0xBE60000000000000)
ret float %res
@@ -691,7 +691,7 @@ define float @test_fma_1_minus_ulp_rz_f() {
define float @test_fma_1_minus_ulp_rm_ftz_f() {
; CHECK-LABEL: define float @test_fma_1_minus_ulp_rm_ftz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%res = call float @llvm.nvvm.fma.rm.ftz.f(float 1.0, float 1.0, float 0xBE60000000000000)
ret float %res
@@ -715,7 +715,7 @@ define float @test_fma_1_minus_ulp_rp_ftz_f() {
define float @test_fma_1_minus_ulp_rz_ftz_f() {
; CHECK-LABEL: define float @test_fma_1_minus_ulp_rz_ftz_f() {
-; CHECK-NEXT: ret float 0x3FEFFFFFE0000000
+; CHECK-NEXT: ret float f0x3F7FFFFF
;
%res = call float @llvm.nvvm.fma.rz.ftz.f(float 1.0, float 1.0, float 0xBE60000000000000)
ret float %res
@@ -731,7 +731,7 @@ define float @test_fma_1_minus_ulp_rz_ftz_f() {
define double @test_fma_1_minus_ulp_rm_d() {
; CHECK-LABEL: define double @test_fma_1_minus_ulp_rm_d() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%res = call double @llvm.nvvm.fma.rm.d(double 1.0, double 1.0, double 0xBC90000000000000)
ret double %res
@@ -755,7 +755,7 @@ define double @test_fma_1_minus_ulp_rp_d() {
define double @test_fma_1_minus_ulp_rz_d() {
; CHECK-LABEL: define double @test_fma_1_minus_ulp_rz_d() {
-; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF
+; CHECK-NEXT: ret double f0x3FEFFFFFFFFFFFFF
;
%res = call double @llvm.nvvm.fma.rz.d(double 1.0, double 1.0, double 0xBC90000000000000)
ret double %res
@@ -771,7 +771,7 @@ define double @test_fma_1_minus_ulp_rz_d() {
define float @test_fma_neg_1_minus_ulp_rm_f() {
; CHECK-LABEL: define float @test_fma_neg_1_minus_ulp_rm_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.fma.rm.f(float 1.0, float -1.0, float 0xBE60000000000000)
ret float %res
@@ -803,7 +803,7 @@ define float @test_fma_neg_1_minus_ulp_rz_f() {
define float @test_fma_neg_1_minus_ulp_rm_ftz_f() {
; CHECK-LABEL: define float @test_fma_neg_1_minus_ulp_rm_ftz_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.fma.rm.ftz.f(float 1.0, float -1.0, float 0xBE60000000000000)
ret float %res
@@ -843,7 +843,7 @@ define float @test_fma_neg_1_minus_ulp_rz_ftz_f() {
define double @test_fma_neg_1_minus_ulp_rm_d() {
; CHECK-LABEL: define double @test_fma_neg_1_minus_ulp_rm_d() {
-; CHECK-NEXT: ret double 0xBFF0000000000001
+; CHECK-NEXT: ret double f0xBFF0000000000001
;
%res = call double @llvm.nvvm.fma.rm.d(double 1.0, double -1.0, double 0xBC90000000000000)
ret double %res
diff --git a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
index 4ab6b3cf295bf..6a559ee2a19e9 100644
--- a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
+++ b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
@@ -85,7 +85,7 @@ define float @test_fmax_1_25_neg_2_xorsign_abs_f() {
define double @test_fmax_pos_subnorm_zero_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_zero_d() {
-; CHECK-NEXT: ret double 0x380FFFFFC0000000
+; CHECK-NEXT: ret double f0x380FFFFFC0000000
;
%res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0.0)
ret double %res
@@ -93,7 +93,7 @@ define double @test_fmax_pos_subnorm_zero_d() {
define float @test_fmax_pos_subnorm_zero_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
@@ -133,7 +133,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_xorsign_abs_f() {
define float @test_fmax_pos_subnorm_zero_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_nan_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
@@ -141,7 +141,7 @@ define float @test_fmax_pos_subnorm_zero_nan_f() {
define float @test_fmax_pos_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
@@ -149,7 +149,7 @@ define float @test_fmax_pos_subnorm_zero_nan_xorsign_abs_f() {
define float @test_fmax_pos_subnorm_zero_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
@@ -161,7 +161,7 @@ define float @test_fmax_pos_subnorm_zero_xorsign_abs_f() {
define double @test_fmax_pos_subnorm_neg_subnorm_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_neg_subnorm_d() {
-; CHECK-NEXT: ret double 0x380FFFFFC0000000
+; CHECK-NEXT: ret double f0x380FFFFFC0000000
;
%res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
ret double %res
@@ -169,7 +169,7 @@ define double @test_fmax_pos_subnorm_neg_subnorm_d() {
define float @test_fmax_pos_subnorm_neg_subnorm_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
@@ -209,7 +209,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
define float @test_fmax_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_nan_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
@@ -217,7 +217,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_nan_f() {
define float @test_fmax_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0xB80FFFFFC0000000
+; CHECK-NEXT: ret float f0x807FFFFF
;
%res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
@@ -225,7 +225,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
define float @test_fmax_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0xB80FFFFFC0000000
+; CHECK-NEXT: ret float f0x807FFFFF
;
%res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
@@ -237,7 +237,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_xorsign_abs_f() {
define double @test_fmax_pos_subnorm_nan_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_nan_d() {
-; CHECK-NEXT: ret double 0x380FFFFFC0000000
+; CHECK-NEXT: ret double f0x380FFFFFC0000000
;
%res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0x7fff444400000000)
ret double %res
@@ -245,7 +245,7 @@ define double @test_fmax_pos_subnorm_nan_d() {
define float @test_fmax_pos_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -261,7 +261,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_f() {
define float @test_fmax_pos_subnorm_nan_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_nan_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -269,7 +269,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_nan_f() {
define float @test_fmax_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -285,7 +285,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_xorsign_abs_f() {
define float @test_fmax_pos_subnorm_nan_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_nan_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -293,7 +293,7 @@ define float @test_fmax_pos_subnorm_nan_nan_f() {
define float @test_fmax_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -301,7 +301,7 @@ define float @test_fmax_pos_subnorm_nan_nan_xorsign_abs_f() {
define float @test_fmax_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -313,7 +313,7 @@ define float @test_fmax_pos_subnorm_nan_xorsign_abs_f() {
define double @test_fmax_subnorm_undef_d() {
; CHECK-LABEL: define double @test_fmax_subnorm_undef_d() {
-; CHECK-NEXT: ret double 0x380FFFFFC0000000
+; CHECK-NEXT: ret double f0x380FFFFFC0000000
;
%res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double undef)
ret double %res
@@ -321,7 +321,7 @@ define double @test_fmax_subnorm_undef_d() {
define float @test_fmax_subnorm_undef_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float undef)
ret float %res
@@ -361,7 +361,7 @@ define float @test_fmax_subnorm_undef_ftz_xorsign_abs_f() {
define float @test_fmax_subnorm_undef_nan_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_nan_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float undef)
ret float %res
@@ -369,7 +369,7 @@ define float @test_fmax_subnorm_undef_nan_f() {
define float @test_fmax_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
@@ -377,7 +377,7 @@ define float @test_fmax_subnorm_undef_nan_xorsign_abs_f() {
define float @test_fmax_subnorm_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
@@ -390,7 +390,7 @@ define float @test_fmax_subnorm_undef_xorsign_abs_f() {
define double @test_fmax_nan_undef_d() {
; CHECK-LABEL: define double @test_fmax_nan_undef_d() {
-; CHECK-NEXT: ret double 0x7FF4444400000000
+; CHECK-NEXT: ret double +snan(0x4444400000000)
;
%res = call double @llvm.nvvm.fmax.d(double 0x7ff4444400000000, double undef)
ret double %res
@@ -398,7 +398,7 @@ define double @test_fmax_nan_undef_d() {
define float @test_fmax_nan_undef_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -406,7 +406,7 @@ define float @test_fmax_nan_undef_f() {
define float @test_fmax_nan_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.ftz.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -414,7 +414,7 @@ define float @test_fmax_nan_undef_ftz_f() {
define float @test_fmax_nan_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_nan_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -422,7 +422,7 @@ define float @test_fmax_nan_undef_ftz_nan_f() {
define float @test_fmax_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -430,7 +430,7 @@ define float @test_fmax_nan_undef_ftz_nan_xorsign_abs_f() {
define float @test_fmax_nan_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x7ffff4ff00000000, float undef)
ret float %res
@@ -438,7 +438,7 @@ define float @test_fmax_nan_undef_ftz_xorsign_abs_f() {
define float @test_fmax_nan_undef_nan_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_nan_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.nan.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -446,7 +446,7 @@ define float @test_fmax_nan_undef_nan_f() {
define float @test_fmax_nan_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -454,7 +454,7 @@ define float @test_fmax_nan_undef_nan_xorsign_abs_f() {
define float @test_fmax_nan_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -542,7 +542,7 @@ define float @test_fmin_1_25_neg_2_xorsign_abs_f() {
define double @test_fmin_neg_subnorm_zero_d() {
; CHECK-LABEL: define double @test_fmin_neg_subnorm_zero_d() {
-; CHECK-NEXT: ret double 0xB80FFFFFC0000000
+; CHECK-NEXT: ret double f0xB80FFFFFC0000000
;
%res = call double @llvm.nvvm.fmin.d(double 0xB80FFFFFC0000000, double 0.0)
ret double %res
@@ -550,7 +550,7 @@ define double @test_fmin_neg_subnorm_zero_d() {
define float @test_fmin_neg_subnorm_zero_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_f() {
-; CHECK-NEXT: ret float 0xB80FFFFFC0000000
+; CHECK-NEXT: ret float f0x807FFFFF
;
%res = call float @llvm.nvvm.fmin.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
@@ -590,7 +590,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_xorsign_abs_f() {
define float @test_fmin_neg_subnorm_zero_nan_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_nan_f() {
-; CHECK-NEXT: ret float 0xB80FFFFFC0000000
+; CHECK-NEXT: ret float f0x807FFFFF
;
%res = call float @llvm.nvvm.fmin.nan.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
@@ -618,7 +618,7 @@ define float @test_fmin_neg_subnorm_zero_xorsign_abs_f() {
define double @test_fmin_pos_subnorm_neg_subnorm_d() {
; CHECK-LABEL: define double @test_fmin_pos_subnorm_neg_subnorm_d() {
-; CHECK-NEXT: ret double 0xB80FFFFFC0000000
+; CHECK-NEXT: ret double f0xB80FFFFFC0000000
;
%res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
ret double %res
@@ -626,7 +626,7 @@ define double @test_fmin_pos_subnorm_neg_subnorm_d() {
define float @test_fmin_pos_subnorm_neg_subnorm_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_f() {
-; CHECK-NEXT: ret float 0xB80FFFFFC0000000
+; CHECK-NEXT: ret float f0x807FFFFF
;
%res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
@@ -666,7 +666,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
define float @test_fmin_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_nan_f() {
-; CHECK-NEXT: ret float 0xB80FFFFFC0000000
+; CHECK-NEXT: ret float f0x807FFFFF
;
%res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
@@ -674,7 +674,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_nan_f() {
define float @test_fmin_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0xB80FFFFFC0000000
+; CHECK-NEXT: ret float f0x807FFFFF
;
%res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
@@ -682,7 +682,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
define float @test_fmin_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0xB80FFFFFC0000000
+; CHECK-NEXT: ret float f0x807FFFFF
;
%res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
@@ -694,7 +694,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_xorsign_abs_f() {
define double @test_fmin_pos_subnorm_nan_d() {
; CHECK-LABEL: define double @test_fmin_pos_subnorm_nan_d() {
-; CHECK-NEXT: ret double 0x380FFFFFC0000000
+; CHECK-NEXT: ret double f0x380FFFFFC0000000
;
%res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double 0x7fff444400000000)
ret double %res
@@ -702,7 +702,7 @@ define double @test_fmin_pos_subnorm_nan_d() {
define float @test_fmin_pos_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -718,7 +718,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_f() {
define float @test_fmin_pos_subnorm_nan_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_nan_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -726,7 +726,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_nan_f() {
define float @test_fmin_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -742,7 +742,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_xorsign_abs_f() {
define float @test_fmin_pos_subnorm_nan_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_nan_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -750,7 +750,7 @@ define float @test_fmin_pos_subnorm_nan_nan_f() {
define float @test_fmin_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -758,7 +758,7 @@ define float @test_fmin_pos_subnorm_nan_nan_xorsign_abs_f() {
define float @test_fmin_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
@@ -770,7 +770,7 @@ define float @test_fmin_pos_subnorm_nan_xorsign_abs_f() {
define double @test_fmin_subnorm_undef_d() {
; CHECK-LABEL: define double @test_fmin_subnorm_undef_d() {
-; CHECK-NEXT: ret double 0x380FFFFFC0000000
+; CHECK-NEXT: ret double f0x380FFFFFC0000000
;
%res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double undef)
ret double %res
@@ -778,7 +778,7 @@ define double @test_fmin_subnorm_undef_d() {
define float @test_fmin_subnorm_undef_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float undef)
ret float %res
@@ -818,7 +818,7 @@ define float @test_fmin_subnorm_undef_ftz_xorsign_abs_f() {
define float @test_fmin_subnorm_undef_nan_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_nan_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float undef)
ret float %res
@@ -826,7 +826,7 @@ define float @test_fmin_subnorm_undef_nan_f() {
define float @test_fmin_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
@@ -834,7 +834,7 @@ define float @test_fmin_subnorm_undef_nan_xorsign_abs_f() {
define float @test_fmin_subnorm_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
@@ -847,7 +847,7 @@ define float @test_fmin_subnorm_undef_xorsign_abs_f() {
define double @test_fmin_nan_undef_d() {
; CHECK-LABEL: define double @test_fmin_nan_undef_d() {
-; CHECK-NEXT: ret double 0x7FF4444400000000
+; CHECK-NEXT: ret double +snan(0x4444400000000)
;
%res = call double @llvm.nvvm.fmin.d(double 0x7ff4444400000000, double undef)
ret double %res
@@ -855,7 +855,7 @@ define double @test_fmin_nan_undef_d() {
define float @test_fmin_nan_undef_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -863,7 +863,7 @@ define float @test_fmin_nan_undef_f() {
define float @test_fmin_nan_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.ftz.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -871,7 +871,7 @@ define float @test_fmin_nan_undef_ftz_f() {
define float @test_fmin_nan_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_nan_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -879,7 +879,7 @@ define float @test_fmin_nan_undef_ftz_nan_f() {
define float @test_fmin_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -887,7 +887,7 @@ define float @test_fmin_nan_undef_ftz_nan_xorsign_abs_f() {
define float @test_fmin_nan_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x7ffff4ff00000000, float undef)
ret float %res
@@ -895,7 +895,7 @@ define float @test_fmin_nan_undef_ftz_xorsign_abs_f() {
define float @test_fmin_nan_undef_nan_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_nan_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.nan.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -903,7 +903,7 @@ define float @test_fmin_nan_undef_nan_f() {
define float @test_fmin_nan_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_nan_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
@@ -911,7 +911,7 @@ define float @test_fmin_nan_undef_nan_xorsign_abs_f() {
define float @test_fmin_nan_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_xorsign_abs_f() {
-; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
+; CHECK-NEXT: ret float +nan(0x3FFFFF)
;
%res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
diff --git a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-mul.ll b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-mul.ll
index 12391e8bf0631..e643c02524d1d 100644
--- a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-mul.ll
+++ b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-mul.ll
@@ -148,7 +148,7 @@ define double @test_1_times_subnorm_rz_d() {
define float @test_1_times_subnorm_rm_f() {
; CHECK-LABEL: define float @test_1_times_subnorm_rm_f() {
-; CHECK-NEXT: ret float 0x36A0000000000000
+; CHECK-NEXT: ret float 1.401300e-45
;
%res = call float @llvm.nvvm.mul.rm.f(float 1.0, float 0x36A0000000000000)
ret float %res
@@ -156,7 +156,7 @@ define float @test_1_times_subnorm_rm_f() {
define float @test_1_times_subnorm_rn_f() {
; CHECK-LABEL: define float @test_1_times_subnorm_rn_f() {
-; CHECK-NEXT: ret float 0x36A0000000000000
+; CHECK-NEXT: ret float 1.401300e-45
;
%res = call float @llvm.nvvm.mul.rn.f(float 1.0, float 0x36A0000000000000)
ret float %res
@@ -164,7 +164,7 @@ define float @test_1_times_subnorm_rn_f() {
define float @test_1_times_subnorm_rp_f() {
; CHECK-LABEL: define float @test_1_times_subnorm_rp_f() {
-; CHECK-NEXT: ret float 0x36A0000000000000
+; CHECK-NEXT: ret float 1.401300e-45
;
%res = call float @llvm.nvvm.mul.rp.f(float 1.0, float 0x36A0000000000000)
ret float %res
@@ -172,7 +172,7 @@ define float @test_1_times_subnorm_rp_f() {
define float @test_1_times_subnorm_rz_f() {
; CHECK-LABEL: define float @test_1_times_subnorm_rz_f() {
-; CHECK-NEXT: ret float 0x36A0000000000000
+; CHECK-NEXT: ret float 1.401300e-45
;
%res = call float @llvm.nvvm.mul.rz.f(float 1.0, float 0x36A0000000000000)
ret float %res
@@ -253,7 +253,7 @@ define double @test_1_times_neg_subnorm_rz_d() {
define float @test_1_times_neg_subnorm_rm_f() {
; CHECK-LABEL: define float @test_1_times_neg_subnorm_rm_f() {
-; CHECK-NEXT: ret float 0xB6A0000000000000
+; CHECK-NEXT: ret float -1.401300e-45
;
%res = call float @llvm.nvvm.mul.rm.f(float 1.0, float 0xB6A0000000000000)
ret float %res
@@ -261,7 +261,7 @@ define float @test_1_times_neg_subnorm_rm_f() {
define float @test_1_times_neg_subnorm_rn_f() {
; CHECK-LABEL: define float @test_1_times_neg_subnorm_rn_f() {
-; CHECK-NEXT: ret float 0xB6A0000000000000
+; CHECK-NEXT: ret float -1.401300e-45
;
%res = call float @llvm.nvvm.mul.rn.f(float 1.0, float 0xB6A0000000000000)
ret float %res
@@ -269,7 +269,7 @@ define float @test_1_times_neg_subnorm_rn_f() {
define float @test_1_times_neg_subnorm_rp_f() {
; CHECK-LABEL: define float @test_1_times_neg_subnorm_rp_f() {
-; CHECK-NEXT: ret float 0xB6A0000000000000
+; CHECK-NEXT: ret float -1.401300e-45
;
%res = call float @llvm.nvvm.mul.rp.f(float 1.0, float 0xB6A0000000000000)
ret float %res
@@ -277,7 +277,7 @@ define float @test_1_times_neg_subnorm_rp_f() {
define float @test_1_times_neg_subnorm_rz_f() {
; CHECK-LABEL: define float @test_1_times_neg_subnorm_rz_f() {
-; CHECK-NEXT: ret float 0xB6A0000000000000
+; CHECK-NEXT: ret float -1.401300e-45
;
%res = call float @llvm.nvvm.mul.rz.f(float 1.0, float 0xB6A0000000000000)
ret float %res
@@ -325,7 +325,7 @@ define float @test_1_times_neg_subnorm_rz_ftz_f() {
define double @test_normal_times_normal_to_subnorm_rm_d() {
; CHECK-LABEL: define double @test_normal_times_normal_to_subnorm_rm_d() {
-; CHECK-NEXT: ret double 0x3800000000000000
+; CHECK-NEXT: ret double f0x3800000000000000
;
%res = call double @llvm.nvvm.mul.rm.d(double 0x3810000000000000, double 0.5)
ret double %res
@@ -333,7 +333,7 @@ define double @test_normal_times_normal_to_subnorm_rm_d() {
define double @test_normal_times_normal_to_subnorm_rn_d() {
; CHECK-LABEL: define double @test_normal_times_normal_to_subnorm_rn_d() {
-; CHECK-NEXT: ret double 0x3800000000000000
+; CHECK-NEXT: ret double f0x3800000000000000
;
%res = call double @llvm.nvvm.mul.rn.d(double 0x3810000000000000, double 0.5)
ret double %res
@@ -341,7 +341,7 @@ define double @test_normal_times_normal_to_subnorm_rn_d() {
define double @test_normal_times_normal_to_subnorm_rp_d() {
; CHECK-LABEL: define double @test_normal_times_normal_to_subnorm_rp_d() {
-; CHECK-NEXT: ret double 0x3800000000000000
+; CHECK-NEXT: ret double f0x3800000000000000
;
%res = call double @llvm.nvvm.mul.rp.d(double 0x3810000000000000, double 0.5)
ret double %res
@@ -349,7 +349,7 @@ define double @test_normal_times_normal_to_subnorm_rp_d() {
define double @test_normal_times_normal_to_subnorm_rz_d() {
; CHECK-LABEL: define double @test_normal_times_normal_to_subnorm_rz_d() {
-; CHECK-NEXT: ret double 0x3800000000000000
+; CHECK-NEXT: ret double f0x3800000000000000
;
%res = call double @llvm.nvvm.mul.rz.d(double 0x3810000000000000, double 0.5)
ret double %res
@@ -357,7 +357,7 @@ define double @test_normal_times_normal_to_subnorm_rz_d() {
define float @test_normal_times_normal_to_subnorm_rm_f() {
; CHECK-LABEL: define float @test_normal_times_normal_to_subnorm_rm_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.mul.rm.f(float 0x3810000000000000, float 0.5)
ret float %res
@@ -365,7 +365,7 @@ define float @test_normal_times_normal_to_subnorm_rm_f() {
define float @test_normal_times_normal_to_subnorm_rn_f() {
; CHECK-LABEL: define float @test_normal_times_normal_to_subnorm_rn_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.mul.rn.f(float 0x3810000000000000, float 0.5)
ret float %res
@@ -373,7 +373,7 @@ define float @test_normal_times_normal_to_subnorm_rn_f() {
define float @test_normal_times_normal_to_subnorm_rp_f() {
; CHECK-LABEL: define float @test_normal_times_normal_to_subnorm_rp_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.mul.rp.f(float 0x3810000000000000, float 0.5)
ret float %res
@@ -381,7 +381,7 @@ define float @test_normal_times_normal_to_subnorm_rp_f() {
define float @test_normal_times_normal_to_subnorm_rz_f() {
; CHECK-LABEL: define float @test_normal_times_normal_to_subnorm_rz_f() {
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
%res = call float @llvm.nvvm.mul.rz.f(float 0x3810000000000000, float 0.5)
ret float %res
@@ -427,7 +427,7 @@ define float @test_normal_times_normal_to_subnorm_rz_ftz_f() {
define double @test_2_times_nan_rm_d() {
; CHECK-LABEL: define double @test_2_times_nan_rm_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.mul.rm.d(double 2.000000e+00, double 0x7FF4444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.mul.rm.d(double 2.000000e+00, double +snan(0x4444400000000))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.mul.rm.d(double 2.0, double 0x7FF4444400000000)
@@ -436,7 +436,7 @@ define double @test_2_times_nan_rm_d() {
define double @test_2_times_nan_rn_d() {
; CHECK-LABEL: define double @test_2_times_nan_rn_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.mul.rn.d(double 2.000000e+00, double 0x7FF4444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.mul.rn.d(double 2.000000e+00, double +snan(0x4444400000000))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.mul.rn.d(double 2.0, double 0x7FF4444400000000)
@@ -445,7 +445,7 @@ define double @test_2_times_nan_rn_d() {
define double @test_2_times_nan_rp_d() {
; CHECK-LABEL: define double @test_2_times_nan_rp_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.mul.rp.d(double 2.000000e+00, double 0x7FF4444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.mul.rp.d(double 2.000000e+00, double +snan(0x4444400000000))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.mul.rp.d(double 2.0, double 0x7FF4444400000000)
@@ -454,7 +454,7 @@ define double @test_2_times_nan_rp_d() {
define double @test_2_times_nan_rz_d() {
; CHECK-LABEL: define double @test_2_times_nan_rz_d() {
-; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.mul.rz.d(double 2.000000e+00, double 0x7FF4444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call double @llvm.nvvm.mul.rz.d(double 2.000000e+00, double +snan(0x4444400000000))
; CHECK-NEXT: ret double [[RES]]
;
%res = call double @llvm.nvvm.mul.rz.d(double 2.0, double 0x7FF4444400000000)
@@ -463,7 +463,7 @@ define double @test_2_times_nan_rz_d() {
define float @test_2_times_nan_rm_f() {
; CHECK-LABEL: define float @test_2_times_nan_rm_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rm.f(float 2.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rm.f(float 2.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.mul.rm.f(float 2.0, float 0x7FFF444400000000)
@@ -472,7 +472,7 @@ define float @test_2_times_nan_rm_f() {
define float @test_2_times_nan_rn_f() {
; CHECK-LABEL: define float @test_2_times_nan_rn_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rn.f(float 2.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rn.f(float 2.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.mul.rn.f(float 2.0, float 0x7FFF444400000000)
@@ -481,7 +481,7 @@ define float @test_2_times_nan_rn_f() {
define float @test_2_times_nan_rp_f() {
; CHECK-LABEL: define float @test_2_times_nan_rp_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rp.f(float 2.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rp.f(float 2.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.mul.rp.f(float 2.0, float 0x7FFF444400000000)
@@ -490,7 +490,7 @@ define float @test_2_times_nan_rp_f() {
define float @test_2_times_nan_rz_f() {
; CHECK-LABEL: define float @test_2_times_nan_rz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rz.f(float 2.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rz.f(float 2.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.mul.rz.f(float 2.0, float 0x7FFF444400000000)
@@ -499,7 +499,7 @@ define float @test_2_times_nan_rz_f() {
define float @test_2_times_nan_rm_ftz_f() {
; CHECK-LABEL: define float @test_2_times_nan_rm_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rm.ftz.f(float 2.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rm.ftz.f(float 2.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.mul.rm.ftz.f(float 2.0, float 0x7FFF444400000000)
@@ -508,7 +508,7 @@ define float @test_2_times_nan_rm_ftz_f() {
define float @test_2_times_nan_rn_ftz_f() {
; CHECK-LABEL: define float @test_2_times_nan_rn_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rn.ftz.f(float 2.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rn.ftz.f(float 2.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.mul.rn.ftz.f(float 2.0, float 0x7FFF444400000000)
@@ -517,7 +517,7 @@ define float @test_2_times_nan_rn_ftz_f() {
define float @test_2_times_nan_rp_ftz_f() {
; CHECK-LABEL: define float @test_2_times_nan_rp_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rp.ftz.f(float 2.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rp.ftz.f(float 2.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.mul.rp.ftz.f(float 2.0, float 0x7FFF444400000000)
@@ -526,7 +526,7 @@ define float @test_2_times_nan_rp_ftz_f() {
define float @test_2_times_nan_rz_ftz_f() {
; CHECK-LABEL: define float @test_2_times_nan_rz_ftz_f() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rz.ftz.f(float 2.000000e+00, float 0x7FFF444400000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.mul.rz.ftz.f(float 2.000000e+00, float +nan(0x3A2220))
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.mul.rz.ftz.f(float 2.0, float 0x7FFF444400000000)
@@ -561,7 +561,7 @@ define float @test_mul_just_above_1_rn_f() {
define float @test_mul_just_above_1_rp_f() {
; CHECK-LABEL: define float @test_mul_just_above_1_rp_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.mul.rp.f(float 0.75, float 0x3FF5555560000000)
ret float %res
@@ -593,7 +593,7 @@ define float @test_mul_just_above_1_rn_ftz_f() {
define float @test_mul_just_above_1_rp_ftz_f() {
; CHECK-LABEL: define float @test_mul_just_above_1_rp_ftz_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.mul.rp.ftz.f(float 0.75, float 0x3FF5555560000000)
ret float %res
@@ -635,7 +635,7 @@ define double @test_mul_just_above_1_rn_d() {
define double @test_mul_just_above_1_rp_d() {
; CHECK-LABEL: define double @test_mul_just_above_1_rp_d() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%res = call double @llvm.nvvm.mul.rp.d(double 0.75, double 0x3FF5555555555556)
ret double %res
@@ -661,7 +661,7 @@ define double @test_mul_just_above_1_rz_d() {
define float @test_mul_just_below_negative_1_rm_f() {
; CHECK-LABEL: define float @test_mul_just_below_negative_1_rm_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.mul.rm.f(float -0.75, float 0x3FF5555560000000)
ret float %res
@@ -693,7 +693,7 @@ define float @test_mul_just_below_negative_1_rz_f() {
define float @test_mul_just_below_negative_1_rm_ftz_f() {
; CHECK-LABEL: define float @test_mul_just_below_negative_1_rm_ftz_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.mul.rm.ftz.f(float -0.75, float 0x3FF5555560000000)
ret float %res
@@ -735,7 +735,7 @@ define float @test_mul_just_below_negative_1_rz_ftz_f() {
define double @test_mul_just_below_negative_1_rm_d() {
; CHECK-LABEL: define double @test_mul_just_below_negative_1_rm_d() {
-; CHECK-NEXT: ret double 0xBFF0000000000001
+; CHECK-NEXT: ret double f0xBFF0000000000001
;
%res = call double @llvm.nvvm.mul.rm.d(double -0.75, double 0x3FF5555555555556)
ret double %res
@@ -784,7 +784,7 @@ define float @test_mul_slightly_more_above_1_rm_f() {
define float @test_mul_slightly_more_above_1_rn_f() {
; CHECK-LABEL: define float @test_mul_slightly_more_above_1_rn_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.mul.rn.f(float 0x3FE4000000000000, float 0x3FF99999C0000000)
ret float %res
@@ -792,7 +792,7 @@ define float @test_mul_slightly_more_above_1_rn_f() {
define float @test_mul_slightly_more_above_1_rp_f() {
; CHECK-LABEL: define float @test_mul_slightly_more_above_1_rp_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.mul.rp.f(float 0x3FE4000000000000, float 0x3FF99999C0000000 )
ret float %res
@@ -816,7 +816,7 @@ define float @test_mul_slightly_more_above_1_rm_ftz_f() {
define float @test_mul_slightly_more_above_1_rn_ftz_f() {
; CHECK-LABEL: define float @test_mul_slightly_more_above_1_rn_ftz_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.mul.rn.ftz.f(float 0x3FE4000000000000, float 0x3FF99999C0000000 )
ret float %res
@@ -824,7 +824,7 @@ define float @test_mul_slightly_more_above_1_rn_ftz_f() {
define float @test_mul_slightly_more_above_1_rp_ftz_f() {
; CHECK-LABEL: define float @test_mul_slightly_more_above_1_rp_ftz_f() {
-; CHECK-NEXT: ret float 0x3FF0000020000000
+; CHECK-NEXT: ret float f0x3F800001
;
%res = call float @llvm.nvvm.mul.rp.ftz.f(float 0x3FE4000000000000, float 0x3FF99999C0000000 )
ret float %res
@@ -857,7 +857,7 @@ define double @test_mul_slightly_more_above_1_rm_d() {
define double @test_mul_slightly_more_above_1_rn_d() {
; CHECK-LABEL: define double @test_mul_slightly_more_above_1_rn_d() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%res = call double @llvm.nvvm.mul.rn.d(double 0x3FE4000000000000, double 0x3FF999999999999B)
ret double %res
@@ -865,7 +865,7 @@ define double @test_mul_slightly_more_above_1_rn_d() {
define double @test_mul_slightly_more_above_1_rp_d() {
; CHECK-LABEL: define double @test_mul_slightly_more_above_1_rp_d() {
-; CHECK-NEXT: ret double 0x3FF0000000000001
+; CHECK-NEXT: ret double f0x3FF0000000000001
;
%res = call double @llvm.nvvm.mul.rp.d(double 0x3FE4000000000000, double 0x3FF999999999999B)
ret double %res
@@ -890,7 +890,7 @@ define double @test_mul_slightly_more_above_1_rz_d() {
define float @test_mul_slightly_more_below_negative_1_rm_f() {
; CHECK-LABEL: define float @test_mul_slightly_more_below_negative_1_rm_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.mul.rm.f(float 0x3FE4000000000000, float 0xBFF99999C0000000)
ret float %res
@@ -898,7 +898,7 @@ define float @test_mul_slightly_more_below_negative_1_rm_f() {
define float @test_mul_slightly_more_below_negative_1_rn_f() {
; CHECK-LABEL: define float @test_mul_slightly_more_below_negative_1_rn_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.mul.rn.f(float 0x3FE4000000000000, float 0xBFF99999C0000000)
ret float %res
@@ -922,7 +922,7 @@ define float @test_mul_slightly_more_below_negative_1_rz_f() {
define float @test_mul_slightly_more_below_negative_1_rm_ftz_f() {
; CHECK-LABEL: define float @test_mul_slightly_more_below_negative_1_rm_ftz_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.mul.rm.ftz.f(float 0x3FE4000000000000, float 0xBFF99999C0000000)
ret float %res
@@ -930,7 +930,7 @@ define float @test_mul_slightly_more_below_negative_1_rm_ftz_f() {
define float @test_mul_slightly_more_below_negative_1_rn_ftz_f() {
; CHECK-LABEL: define float @test_mul_slightly_more_below_negative_1_rn_ftz_f() {
-; CHECK-NEXT: ret float 0xBFF0000020000000
+; CHECK-NEXT: ret float f0xBF800001
;
%res = call float @llvm.nvvm.mul.rn.ftz.f(float 0x3FE4000000000000, float 0xBFF99999C0000000)
ret float %res
@@ -963,7 +963,7 @@ define float @test_mul_slightly_more_below_negative_1_rz_ftz_f() {
define double @test_mul_slightly_more_below_negative_1_rm_d() {
; CHECK-LABEL: define double @test_mul_slightly_more_below_negative_1_rm_d() {
-; CHECK-NEXT: ret double 0xBFF0000000000001
+; CHECK-NEXT: ret double f0xBFF0000000000001
;
%res = call double @llvm.nvvm.mul.rm.d(double 0x3FE4000000000000, double 0xBFF999999999999B)
ret double %res
@@ -971,7 +971,7 @@ define double @test_mul_slightly_more_below_negative_1_rm_d() {
define double @test_mul_slightly_more_below_negative_1_rn_d() {
; CHECK-LABEL: define double @test_mul_slightly_more_below_negative_1_rn_d() {
-; CHECK-NEXT: ret double 0xBFF0000000000001
+; CHECK-NEXT: ret double f0xBFF0000000000001
;
%res = call double @llvm.nvvm.mul.rn.d(double 0x3FE4000000000000, double 0xBFF999999999999B)
ret double %res
diff --git a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-unary-arithmetic.ll b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-unary-arithmetic.ll
index 6eed7f8f1a2ae..32f9b83f6ca39 100644
--- a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-unary-arithmetic.ll
+++ b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-unary-arithmetic.ll
@@ -93,7 +93,7 @@ define float @test_fabs_ftz_1_25() {
define float @test_fabs_neg_subnorm() {
; CHECK-LABEL: define float @test_fabs_neg_subnorm() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fabs(float 0xB80FFFFFC0000000)
ret float %res
@@ -109,7 +109,7 @@ define float @test_fabs_ftz_neg_subnorm() {
define float @test_fabs_pos_subnorm() {
; CHECK-LABEL: define float @test_fabs_pos_subnorm() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.fabs(float 0x380FFFFFC0000000)
ret float %res
@@ -209,7 +209,7 @@ define float @test_rcp_rm_ftz_f_0_5() {
define double @test_rcp_rm_d_neg_subnorm() {
; CHECK-LABEL: define double @test_rcp_rm_d_neg_subnorm() {
-; CHECK-NEXT: ret double 0xC7D0000020000041
+; CHECK-NEXT: ret double f0xC7D0000020000041
;
%res = call double @llvm.nvvm.rcp.rm.d(double 0xB80FFFFFC0000000)
ret double %res
@@ -217,7 +217,7 @@ define double @test_rcp_rm_d_neg_subnorm() {
define float @test_rcp_rm_f_neg_subnorm() {
; CHECK-LABEL: define float @test_rcp_rm_f_neg_subnorm() {
-; CHECK-NEXT: ret float 0xC7D0000040000000
+; CHECK-NEXT: ret float f0xFE800002
;
%res = call float @llvm.nvvm.rcp.rm.f(float 0xB80FFFFFC0000000)
ret float %res
@@ -225,7 +225,7 @@ define float @test_rcp_rm_f_neg_subnorm() {
define float @test_rcp_rm_ftz_f_neg_subnorm() {
; CHECK-LABEL: define float @test_rcp_rm_ftz_f_neg_subnorm() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.rcp.rm.ftz.f(float 0xB80FFFFFC0000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.rcp.rm.ftz.f(float f0x807FFFFF)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.rcp.rm.ftz.f(float 0xB80FFFFFC0000000)
@@ -261,7 +261,7 @@ define float @test_rcp_rn_ftz_f_0_5() {
define double @test_rcp_rn_d_neg_subnorm() {
; CHECK-LABEL: define double @test_rcp_rn_d_neg_subnorm() {
-; CHECK-NEXT: ret double 0xC7D0000020000040
+; CHECK-NEXT: ret double f0xC7D0000020000040
;
%res = call double @llvm.nvvm.rcp.rn.d(double 0xB80FFFFFC0000000)
ret double %res
@@ -269,7 +269,7 @@ define double @test_rcp_rn_d_neg_subnorm() {
define float @test_rcp_rn_f_neg_subnorm() {
; CHECK-LABEL: define float @test_rcp_rn_f_neg_subnorm() {
-; CHECK-NEXT: ret float 0xC7D0000020000000
+; CHECK-NEXT: ret float -8.507060e+37
;
%res = call float @llvm.nvvm.rcp.rn.f(float 0xB80FFFFFC0000000)
ret float %res
@@ -277,7 +277,7 @@ define float @test_rcp_rn_f_neg_subnorm() {
define float @test_rcp_rn_ftz_f_neg_subnorm() {
; CHECK-LABEL: define float @test_rcp_rn_ftz_f_neg_subnorm() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.rcp.rn.ftz.f(float 0xB80FFFFFC0000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.rcp.rn.ftz.f(float f0x807FFFFF)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.rcp.rn.ftz.f(float 0xB80FFFFFC0000000)
@@ -313,7 +313,7 @@ define float @test_rcp_rp_ftz_f_0_5() {
define double @test_rcp_rp_d_neg_subnorm() {
; CHECK-LABEL: define double @test_rcp_rp_d_neg_subnorm() {
-; CHECK-NEXT: ret double 0xC7D0000020000040
+; CHECK-NEXT: ret double f0xC7D0000020000040
;
%res = call double @llvm.nvvm.rcp.rp.d(double 0xB80FFFFFC0000000)
ret double %res
@@ -321,7 +321,7 @@ define double @test_rcp_rp_d_neg_subnorm() {
define float @test_rcp_rp_f_neg_subnorm() {
; CHECK-LABEL: define float @test_rcp_rp_f_neg_subnorm() {
-; CHECK-NEXT: ret float 0xC7D0000020000000
+; CHECK-NEXT: ret float -8.507060e+37
;
%res = call float @llvm.nvvm.rcp.rp.f(float 0xB80FFFFFC0000000)
ret float %res
@@ -329,7 +329,7 @@ define float @test_rcp_rp_f_neg_subnorm() {
define float @test_rcp_rp_ftz_f_neg_subnorm() {
; CHECK-LABEL: define float @test_rcp_rp_ftz_f_neg_subnorm() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.rcp.rp.ftz.f(float 0xB80FFFFFC0000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.rcp.rp.ftz.f(float f0x807FFFFF)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.rcp.rp.ftz.f(float 0xB80FFFFFC0000000)
@@ -365,7 +365,7 @@ define float @test_rcp_rz_ftz_f_0_5() {
define double @test_rcp_rz_d_neg_subnorm() {
; CHECK-LABEL: define double @test_rcp_rz_d_neg_subnorm() {
-; CHECK-NEXT: ret double 0xC7D0000020000040
+; CHECK-NEXT: ret double f0xC7D0000020000040
;
%res = call double @llvm.nvvm.rcp.rz.d(double 0xB80FFFFFC0000000)
ret double %res
@@ -373,7 +373,7 @@ define double @test_rcp_rz_d_neg_subnorm() {
define float @test_rcp_rz_f_neg_subnorm() {
; CHECK-LABEL: define float @test_rcp_rz_f_neg_subnorm() {
-; CHECK-NEXT: ret float 0xC7D0000020000000
+; CHECK-NEXT: ret float -8.507060e+37
;
%res = call float @llvm.nvvm.rcp.rz.f(float 0xB80FFFFFC0000000)
ret float %res
@@ -381,7 +381,7 @@ define float @test_rcp_rz_f_neg_subnorm() {
define float @test_rcp_rz_ftz_f_neg_subnorm() {
; CHECK-LABEL: define float @test_rcp_rz_ftz_f_neg_subnorm() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.rcp.rz.ftz.f(float 0xB80FFFFFC0000000)
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.rcp.rz.ftz.f(float f0x807FFFFF)
; CHECK-NEXT: ret float [[RES]]
;
%res = call float @llvm.nvvm.rcp.rz.ftz.f(float 0xB80FFFFFC0000000)
@@ -566,7 +566,7 @@ define float @test_saturate_ftz_f_0_5() {
define double @test_saturate_d_pos_subnorm() {
; CHECK-LABEL: define double @test_saturate_d_pos_subnorm() {
-; CHECK-NEXT: ret double 0x380FFFFFC0000000
+; CHECK-NEXT: ret double f0x380FFFFFC0000000
;
%res = call double @llvm.nvvm.saturate.d(double 0x380FFFFFC0000000)
ret double %res
@@ -574,7 +574,7 @@ define double @test_saturate_d_pos_subnorm() {
define float @test_saturate_f_pos_subnorm() {
; CHECK-LABEL: define float @test_saturate_f_pos_subnorm() {
-; CHECK-NEXT: ret float 0x380FFFFFC0000000
+; CHECK-NEXT: ret float f0x007FFFFF
;
%res = call float @llvm.nvvm.saturate.f(float 0x380FFFFFC0000000)
ret float %res
@@ -626,7 +626,7 @@ define float @test_sqrt_rn_ftz_f_4() {
define float @test_sqrt_f_pos_subnorm() {
; CHECK-LABEL: define float @test_sqrt_f_pos_subnorm() {
-; CHECK-NEXT: ret float 0x3BFFFFFFE0000000
+; CHECK-NEXT: ret float f0x1FFFFFFF
;
%res = call float @llvm.nvvm.sqrt.f(float 0x380FFFFFC0000000)
ret float %res
@@ -634,7 +634,7 @@ define float @test_sqrt_f_pos_subnorm() {
define float @test_sqrt_rn_f_pos_subnorm() {
; CHECK-LABEL: define float @test_sqrt_rn_f_pos_subnorm() {
-; CHECK-NEXT: ret float 0x3BFFFFFFE0000000
+; CHECK-NEXT: ret float f0x1FFFFFFF
;
%res = call float @llvm.nvvm.sqrt.rn.f(float 0x380FFFFFC0000000)
ret float %res
@@ -642,7 +642,7 @@ define float @test_sqrt_rn_f_pos_subnorm() {
define double @test_sqrt_rn_d_pos_subnorm() {
; CHECK-LABEL: define double @test_sqrt_rn_d_pos_subnorm() {
-; CHECK-NEXT: ret double 0x3BFFFFFFDFFFFFF0
+; CHECK-NEXT: ret double f0x3BFFFFFFDFFFFFF0
;
%res = call double @llvm.nvvm.sqrt.rn.d(double 0x380FFFFFC0000000)
ret double %res
diff --git a/llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll b/llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll
index 679774b09b098..0162c803e2460 100644
--- a/llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll
+++ b/llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll
@@ -15,7 +15,7 @@
define float @test_float_fadd_ieee() #0 {
; CHECK-LABEL: @test_float_fadd_ieee(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
; default ieee mode leaves result as a denormal
%result = fadd float 0xB810000000000000, 0x3800000000000000
@@ -24,7 +24,7 @@ define float @test_float_fadd_ieee() #0 {
define <4 x float> @test_float_fadd_ieee_vector() #0 {
; CHECK-LABEL: @test_float_fadd_ieee_vector(
-; CHECK-NEXT: ret <4 x float> splat (float 0xB800000000000000)
+; CHECK-NEXT: ret <4 x float> splat (float f0x80400000)
;
; default ieee mode leaves result as a denormal
%result = fadd <4 x float> splat(float 0xB810000000000000), splat(float 0x3800000000000000)
@@ -69,7 +69,7 @@ define <4 x float> @test_float_fadd_psign_out_vector() #2 {
define float @test_float_fadd_pzero_in() #3 {
; CHECK-LABEL: @test_float_fadd_pzero_in(
-; CHECK-NEXT: ret float 0xB810000000000000
+; CHECK-NEXT: ret float f0x80800000
;
; denormal operand is treated as zero
; normal operand added to zero results in the same operand as a result
@@ -79,7 +79,7 @@ define float @test_float_fadd_pzero_in() #3 {
define float @test_float_fadd_psign_in() #4 {
; CHECK-LABEL: @test_float_fadd_psign_in(
-; CHECK-NEXT: ret float 0xB810000000000000
+; CHECK-NEXT: ret float f0x80800000
;
; denormal operand is treated as zero
; normal operand added to zero results in the same operand as a result
@@ -99,7 +99,7 @@ define float @test_float_fadd_pzero_f32_out() #5 {
define double @test_double_fadd_ieee() #0 {
; CHECK-LABEL: @test_double_fadd_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; default ieee mode leaves result as a denormal
%result = fadd double 0x8010000000000000, 0x0008000000000000
@@ -108,7 +108,7 @@ define double @test_double_fadd_ieee() #0 {
define <2 x double> @test_double_fadd_ieee_vector() #0 {
; CHECK-LABEL: @test_double_fadd_ieee_vector(
-; CHECK-NEXT: ret <2 x double> splat (double 0x8008000000000000)
+; CHECK-NEXT: ret <2 x double> splat (double f0x8008000000000000)
;
; default ieee mode leaves result as a denormal
%result = fadd <2 x double> splat(double 0x8010000000000000), splat(double 0x0008000000000000)
@@ -153,7 +153,7 @@ define <2 x double> @test_double_fadd_psign_out_vector() #2 {
define double @test_double_fadd_pzero_in() #3 {
; CHECK-LABEL: @test_double_fadd_pzero_in(
-; CHECK-NEXT: ret double 0x8010000000000000
+; CHECK-NEXT: ret double f0x8010000000000000
;
; denormal operand is treated as zero
; normal operand added to zero results in the same operand as a result
@@ -163,7 +163,7 @@ define double @test_double_fadd_pzero_in() #3 {
define double @test_double_fadd_psign_in() #4 {
; CHECK-LABEL: @test_double_fadd_psign_in(
-; CHECK-NEXT: ret double 0x8010000000000000
+; CHECK-NEXT: ret double f0x8010000000000000
;
; denormal operand is treated as zero
; normal operand added to zero results in the same operand as a result
@@ -173,7 +173,7 @@ define double @test_double_fadd_psign_in() #4 {
define double @test_double_fadd_f32_ieee() #5 {
; CHECK-LABEL: @test_double_fadd_f32_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; f32 only attribute should not flush doubles
; default ieee mode leaves result as a denormal
@@ -191,7 +191,7 @@ define double @test_double_fadd_f32_ieee() #5 {
define float @test_float_fsub_ieee() #0 {
; CHECK-LABEL: @test_float_fsub_ieee(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
; default ieee mode leaves result as a denormal
%result = fsub float 0x3800000000000000, 0x3810000000000000
@@ -218,7 +218,7 @@ define float @test_float_fsub_psign_out() #2 {
define float @test_float_fsub_pzero_in() #3 {
; CHECK-LABEL: @test_float_fsub_pzero_in(
-; CHECK-NEXT: ret float 0xB810000000000000
+; CHECK-NEXT: ret float f0x80800000
;
; denormal operand is treated as zero
; normal operand subtracted from zero produces the same operand, negated
@@ -228,7 +228,7 @@ define float @test_float_fsub_pzero_in() #3 {
define float @test_float_fsub_psign_in() #4 {
; CHECK-LABEL: @test_float_fsub_psign_in(
-; CHECK-NEXT: ret float 0xB810000000000000
+; CHECK-NEXT: ret float f0x80800000
;
; denormal operand is treated as zero
; normal operand subtracted from zero produces the same operand, negated
@@ -248,7 +248,7 @@ define float @test_float_fsub_pzero_f32_out() #5 {
define double @test_double_fsub_ieee() #0 {
; CHECK-LABEL: @test_double_fsub_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; default ieee mode leaves result as a denormal
%result = fsub double 0x0008000000000000, 0x0010000000000000
@@ -275,7 +275,7 @@ define double @test_double_fsub_psign_out() #2 {
define double @test_double_fsub_pzero_in() #3 {
; CHECK-LABEL: @test_double_fsub_pzero_in(
-; CHECK-NEXT: ret double 0x8010000000000000
+; CHECK-NEXT: ret double f0x8010000000000000
;
; denormal operand is treated as zero
; normal operand subtracted from zero produces the same operand, negated
@@ -285,7 +285,7 @@ define double @test_double_fsub_pzero_in() #3 {
define double @test_double_fsub_psign_in() #4 {
; CHECK-LABEL: @test_double_fsub_psign_in(
-; CHECK-NEXT: ret double 0x8010000000000000
+; CHECK-NEXT: ret double f0x8010000000000000
;
; denormal operand is treated as zero
; normal operand subtracted from zero produces the same operand, negated
@@ -295,7 +295,7 @@ define double @test_double_fsub_psign_in() #4 {
define double @test_double_fsub_f32_ieee() #5 {
; CHECK-LABEL: @test_double_fsub_f32_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; f32 only attribute should not flush doubles
; default ieee mode leaves result as a denormal
@@ -315,7 +315,7 @@ define double @test_double_fsub_f32_ieee() #5 {
define float @test_float_fmul_ieee() #0 {
; CHECK-LABEL: @test_float_fmul_ieee(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
; default ieee mode leaves result as a denormal
%result = fmul float 0x3810000000000000, -5.000000e-01
@@ -372,7 +372,7 @@ define float @test_float_fmul_pzero_f32_out() #1 {
define double @test_double_fmul_ieee() #0 {
; CHECK-LABEL: @test_double_fmul_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; default ieee mode leaves result as a denormal
%result = fmul double 0x00010000000000000, -5.000000e-01
@@ -419,7 +419,7 @@ define double @test_double_fmul_psign_in() #4 {
define double @test_double_fmul_f32_ieee() #5 {
; CHECK-LABEL: @test_double_fmul_f32_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; f32 only attribute should not flush doubles
; default ieee mode leaves result as a denormal
@@ -439,7 +439,7 @@ define double @test_double_fmul_f32_ieee() #5 {
define float @test_float_fdiv_ieee() #0 {
; CHECK-LABEL: @test_float_fdiv_ieee(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
; default ieee mode leaves result as a denormal
%result = fdiv float 0x3810000000000000, -2.000000e-00
@@ -496,7 +496,7 @@ define float @test_float_fdiv_pzero_f32_out() #1 {
define double @test_double_fdiv_ieee() #0 {
; CHECK-LABEL: @test_double_fdiv_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; default ieee mode leaves result as a denormal
%result = fdiv double 0x0010000000000000, -2.000000e-00
@@ -543,7 +543,7 @@ define double @test_double_fdiv_psign_in() #4 {
define double @test_double_fdiv_f32_ieee() #5 {
; CHECK-LABEL: @test_double_fdiv_f32_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; f32 only attribute should not flush doubles
; default ieee mode leaves result as a denormal
@@ -563,7 +563,7 @@ define double @test_double_fdiv_f32_ieee() #5 {
define float @test_float_frem_ieee_out() #0 {
; CHECK-LABEL: @test_float_frem_ieee_out(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
; default ieee mode leaves result as a denormal
%result = frem float 0xB818000000000000, 0x3810000000000000
@@ -590,7 +590,7 @@ define float @test_float_frem_psign_out() #2 {
define float @test_float_frem_ieee_in() #0 {
; CHECK-LABEL: @test_float_frem_ieee_in(
-; CHECK-NEXT: ret float 0x3800000000000000
+; CHECK-NEXT: ret float f0x00400000
;
; default ieee mode leaves result same as input
%result = frem float 0x3800000000000000, 2.000000e+00
@@ -629,7 +629,7 @@ define float @test_float_frem_pzero_f32_out() #1 {
define double @test_double_frem_ieee_out() #0 {
; CHECK-LABEL: @test_double_frem_ieee_out(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; default ieee mode leaves result as a denormal
%result = frem double 0x8018000000000000, 0x0010000000000000
@@ -656,7 +656,7 @@ define double @test_double_frem_psign_out() #2 {
define double @test_double_frem_ieee_in() #0 {
; CHECK-LABEL: @test_double_frem_ieee_in(
-; CHECK-NEXT: ret double 0x8000000000000
+; CHECK-NEXT: ret double f0x0008000000000000
;
; default ieee mode leaves result same as input
%result = frem double 0x0008000000000000, 2.000000e+00
@@ -685,7 +685,7 @@ define double @test_double_frem_psign_in() #4 {
define double @test_double_frem_f32_ieee() #5 {
; CHECK-LABEL: @test_double_frem_f32_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
; f32 only attribute should not flush doubles
; default ieee mode leaves result as a denormal
@@ -701,7 +701,7 @@ define double @test_double_frem_f32_ieee() #5 {
define float @test_float_fneg_ieee() #0 {
; CHECK-LABEL: @test_float_fneg_ieee(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
%result = fneg float 0x3800000000000000
ret float %result
@@ -709,7 +709,7 @@ define float @test_float_fneg_ieee() #0 {
define float @test_float_fneg_pzero_out() #0 {
; CHECK-LABEL: @test_float_fneg_pzero_out(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
%result = fneg float 0x3800000000000000
ret float %result
@@ -717,7 +717,7 @@ define float @test_float_fneg_pzero_out() #0 {
define float @test_float_fneg_psign_out() #0 {
; CHECK-LABEL: @test_float_fneg_psign_out(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
%result = fneg float 0x3800000000000000
ret float %result
@@ -725,7 +725,7 @@ define float @test_float_fneg_psign_out() #0 {
define float @test_float_fneg_pzero_in() #0 {
; CHECK-LABEL: @test_float_fneg_pzero_in(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
%result = fneg float 0x3800000000000000
ret float %result
@@ -733,7 +733,7 @@ define float @test_float_fneg_pzero_in() #0 {
define float @test_float_fneg_psign_in() #0 {
; CHECK-LABEL: @test_float_fneg_psign_in(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
%result = fneg float 0x3800000000000000
ret float %result
@@ -741,7 +741,7 @@ define float @test_float_fneg_psign_in() #0 {
define float @test_float_fneg_pzero_f32_out() #5 {
; CHECK-LABEL: @test_float_fneg_pzero_f32_out(
-; CHECK-NEXT: ret float 0xB800000000000000
+; CHECK-NEXT: ret float f0x80400000
;
%result = fneg float 0x3800000000000000
ret float %result
@@ -749,7 +749,7 @@ define float @test_float_fneg_pzero_f32_out() #5 {
define double @test_double_fneg_ieee() #0 {
; CHECK-LABEL: @test_double_fneg_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
%result = fneg double 0x0008000000000000
ret double %result
@@ -757,7 +757,7 @@ define double @test_double_fneg_ieee() #0 {
define double @test_double_fneg_pzero_out() #1 {
; CHECK-LABEL: @test_double_fneg_pzero_out(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
%result = fneg double 0x0008000000000000
ret double %result
@@ -765,7 +765,7 @@ define double @test_double_fneg_pzero_out() #1 {
define double @test_double_fneg_psign_out() #2 {
; CHECK-LABEL: @test_double_fneg_psign_out(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
%result = fneg double 0x0008000000000000
ret double %result
@@ -773,7 +773,7 @@ define double @test_double_fneg_psign_out() #2 {
define double @test_double_fneg_pzero_in() #3 {
; CHECK-LABEL: @test_double_fneg_pzero_in(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
%result = fneg double 0x0008000000000000
ret double %result
@@ -781,7 +781,7 @@ define double @test_double_fneg_pzero_in() #3 {
define double @test_double_fneg_psign_in() #4 {
; CHECK-LABEL: @test_double_fneg_psign_in(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
%result = fneg double 0x0008000000000000
ret double %result
@@ -789,7 +789,7 @@ define double @test_double_fneg_psign_in() #4 {
define double @test_double_fneg_f32_ieee() #5 {
; CHECK-LABEL: @test_double_fneg_f32_ieee(
-; CHECK-NEXT: ret double 0x8008000000000000
+; CHECK-NEXT: ret double f0x8008000000000000
;
%result = fneg double 0x0008000000000000
ret double %result
@@ -1161,7 +1161,7 @@ entry:
define float @test_float_fadd_dynamic_ieee() #9 {
; CHECK-LABEL: @test_float_fadd_dynamic_ieee(
-; CHECK-NEXT: [[RESULT:%.*]] = fadd float 0xB810000000000000, 0x3800000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fadd float f0x80800000, f0x00400000
; CHECK-NEXT: ret float [[RESULT]]
;
%result = fadd float 0xB810000000000000, 0x3800000000000000
@@ -1170,7 +1170,7 @@ define float @test_float_fadd_dynamic_ieee() #9 {
define float @test_float_fadd_ieee_dynamic() #10 {
; CHECK-LABEL: @test_float_fadd_ieee_dynamic(
-; CHECK-NEXT: [[RESULT:%.*]] = fadd float 0xB810000000000000, 0x3800000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fadd float f0x80800000, f0x00400000
; CHECK-NEXT: ret float [[RESULT]]
;
%result = fadd float 0xB810000000000000, 0x3800000000000000
@@ -1179,7 +1179,7 @@ define float @test_float_fadd_ieee_dynamic() #10 {
define float @test_float_fadd_dynamic_dynamic() #11 {
; CHECK-LABEL: @test_float_fadd_dynamic_dynamic(
-; CHECK-NEXT: [[RESULT:%.*]] = fadd float 0xB810000000000000, 0x3800000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fadd float f0x80800000, f0x00400000
; CHECK-NEXT: ret float [[RESULT]]
;
%result = fadd float 0xB810000000000000, 0x3800000000000000
@@ -1189,7 +1189,7 @@ define float @test_float_fadd_dynamic_dynamic() #11 {
; Check for failed to fold on each operand
define float @test_float_fadd_dynamic_dynamic_commute() #11 {
; CHECK-LABEL: @test_float_fadd_dynamic_dynamic_commute(
-; CHECK-NEXT: [[RESULT:%.*]] = fadd float 0x3800000000000000, 0xB810000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = fadd float f0x00400000, f0x80800000
; CHECK-NEXT: ret float [[RESULT]]
;
%result = fadd float 0x3800000000000000, 0xB810000000000000
@@ -1214,7 +1214,7 @@ define <2 x i1> @fcmp_double_dynamic_ieee_vector() #9 {
define i1 @fcmp_double_ieee_dynamic() #10 {
; CHECK-LABEL: @fcmp_double_ieee_dynamic(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double 0x8000000000000, 0.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double f0x0008000000000000, 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp une double 0x0008000000000000, 0x0
@@ -1223,7 +1223,7 @@ define i1 @fcmp_double_ieee_dynamic() #10 {
define <2 x i1> @fcmp_double_ieee_dynamic_vector() #10 {
; CHECK-LABEL: @fcmp_double_ieee_dynamic_vector(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une <2 x double> splat (double 0x8000000000000), zeroinitializer
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une <2 x double> splat (double f0x0008000000000000), zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%cmp = fcmp une <2 x double> splat(double 0x0008000000000000), zeroinitializer
@@ -1232,7 +1232,7 @@ define <2 x i1> @fcmp_double_ieee_dynamic_vector() #10 {
define i1 @fcmp_double_dynamic_dynamic() #11 {
; CHECK-LABEL: @fcmp_double_dynamic_dynamic(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double 0x8000000000000, 0.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double f0x0008000000000000, 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp une double 0x0008000000000000, 0x0
@@ -1241,7 +1241,7 @@ define i1 @fcmp_double_dynamic_dynamic() #11 {
define i1 @fcmp_double_dynamic_dynamic_commute() #11 {
; CHECK-LABEL: @fcmp_double_dynamic_dynamic_commute(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double 0.000000e+00, 0x8000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double 0.000000e+00, f0x0008000000000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp une double 0x0, 0x0008000000000000
diff --git a/llvm/test/Transforms/InstSimplify/constfold-constrained.ll b/llvm/test/Transforms/InstSimplify/constfold-constrained.ll
index a9ef7f6a765d1..bab7d0ca1b23f 100644
--- a/llvm/test/Transforms/InstSimplify/constfold-constrained.ll
+++ b/llvm/test/Transforms/InstSimplify/constfold-constrained.ll
@@ -156,7 +156,7 @@ entry:
define double @nonfinite_01() #0 {
; CHECK-LABEL: @nonfinite_01(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.trunc.f64(double 0x7FF4000000000000, metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.trunc.f64(double +snan(0x4000000000000), metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret double [[RESULT]]
;
entry:
@@ -168,7 +168,7 @@ entry:
define double @nonfinite_02() #0 {
; CHECK-LABEL: @nonfinite_02(
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
entry:
%result = call double @llvm.experimental.constrained.trunc.f64(double 0x7ff4000000000000, metadata !"fpexcept.ignore") #0
@@ -179,8 +179,8 @@ entry:
define double @nonfinite_03() #0 {
; CHECK-LABEL: @nonfinite_03(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.trunc.f64(double 0x7FF8000000000000, metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.trunc.f64(double +qnan, metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: ret double +qnan
;
entry:
%result = call double @llvm.experimental.constrained.trunc.f64(double 0x7ff8000000000000, metadata !"fpexcept.strict") #0
@@ -191,8 +191,8 @@ entry:
define double @nonfinite_04() #0 {
; CHECK-LABEL: @nonfinite_04(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.trunc.f64(double 0x7FF0000000000000, metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.trunc.f64(double +inf, metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: ret double +inf
;
entry:
%result = call double @llvm.experimental.constrained.trunc.f64(double 0x7ff0000000000000, metadata !"fpexcept.strict") #0
@@ -259,7 +259,7 @@ entry:
define double @fadd_03() #0 {
; CHECK-LABEL: @fadd_03(
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret double 0x4000000000000001
+; CHECK-NEXT: ret double f0x4000000000000001
;
entry:
%result = call double @llvm.experimental.constrained.fadd.f64(double 1.0, double 0x3FF0000000000001, metadata !"round.upward", metadata !"fpexcept.ignore") #0
@@ -270,7 +270,7 @@ entry:
define double @fadd_04() #0 {
; CHECK-LABEL: @fadd_04(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double 1.000000e+00, double 0x3FF0000000000001, metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double 1.000000e+00, double f0x3FF0000000000001, metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret double [[RESULT]]
;
entry:
@@ -306,7 +306,7 @@ entry:
define double @fadd_07() #0 {
; CHECK-LABEL: @fadd_07(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double 1.000000e+00, double 0x3FF0000000000001, metadata !"round.dynamic", metadata !"fpexcept.ignore") #[[ATTR0]]
+; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double 1.000000e+00, double f0x3FF0000000000001, metadata !"round.dynamic", metadata !"fpexcept.ignore") #[[ATTR0]]
; CHECK-NEXT: ret double [[RESULT]]
;
entry:
@@ -318,7 +318,7 @@ entry:
define double @fadd_08() #0 {
; CHECK-LABEL: @fadd_08(
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
entry:
%result = call double @llvm.experimental.constrained.fadd.f64(double 0x7fEFFFFFFFFFFFFF, double 0x7fEFFFFFFFFFFFFF, metadata !"round.tonearest", metadata !"fpexcept.ignore") #0
@@ -328,7 +328,7 @@ entry:
define double @fadd_09() #0 {
; CHECK-LABEL: @fadd_09(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF, metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[RESULT:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double f0x7FEFFFFFFFFFFFFF, double f0x7FEFFFFFFFFFFFFF, metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret double [[RESULT]]
;
entry:
@@ -339,7 +339,7 @@ entry:
define half @fadd_10() #0 {
; CHECK-LABEL: @fadd_10(
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret half 0xH4200
+; CHECK-NEXT: ret half 3.000000e+00
;
entry:
%result = call half @llvm.experimental.constrained.fadd.f16(half 1.0, half 2.0, metadata !"round.tonearest", metadata !"fpexcept.ignore") #0
@@ -349,7 +349,7 @@ entry:
define bfloat @fadd_11() #0 {
; CHECK-LABEL: @fadd_11(
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret bfloat 0xR4040
+; CHECK-NEXT: ret bfloat 3.000000e+00
;
entry:
%result = call bfloat @llvm.experimental.constrained.fadd.bf16(bfloat 1.0, bfloat 2.0, metadata !"round.tonearest", metadata !"fpexcept.ignore") #0
@@ -492,7 +492,7 @@ entry:
define i1 @cmp_eq_nan_01() #0 {
; CHECK-LABEL: @cmp_eq_nan_01(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double 0x7FF4000000000000, double 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[RESULT:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double +snan(0x4000000000000), double 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret i1 [[RESULT]]
;
entry:
@@ -503,7 +503,7 @@ entry:
define i1 @cmp_eq_nan_02() #0 {
; CHECK-LABEL: @cmp_eq_nan_02(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double 0x7FF4000000000000, double 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[RESULT:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double +snan(0x4000000000000), double 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret i1 [[RESULT]]
;
entry:
@@ -515,7 +515,7 @@ entry:
define i1 @cmp_eq_nan_03() #0 {
; CHECK-LABEL: @cmp_eq_nan_03(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double 0x7FF8000000000000, double 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[RESULT:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double +qnan, double 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret i1 false
;
entry:
@@ -526,7 +526,7 @@ entry:
define i1 @cmp_eq_nan_04() #0 {
; CHECK-LABEL: @cmp_eq_nan_04(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RESULT:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double 0x7FF8000000000000, double 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[RESULT:%.*]] = call i1 @llvm.experimental.constrained.fcmps.f64(double +qnan, double 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret i1 [[RESULT]]
;
entry:
diff --git a/llvm/test/Transforms/InstSimplify/disable_folding.ll b/llvm/test/Transforms/InstSimplify/disable_folding.ll
index 66adf6af1e97f..69892012629bc 100644
--- a/llvm/test/Transforms/InstSimplify/disable_folding.ll
+++ b/llvm/test/Transforms/InstSimplify/disable_folding.ll
@@ -20,7 +20,7 @@ define float @test_fmax_ftz_nan_xorsign_abs_f() {
; Check that -disable-fp-call-folding triggers for LLVM instrincis, not just NVPTX target-specific ones.
define float @test_llvm_sin() {
; FOLDING_ENABLED-LABEL: define float @test_llvm_sin() {
-; FOLDING_ENABLED-NEXT: ret float 0x3FDEAEE880000000
+; FOLDING_ENABLED-NEXT: ret float f0x3EF57744
;
; FOLDING_DISABLED-LABEL: define float @test_llvm_sin() {
; FOLDING_DISABLED-NEXT: [[RES:%.*]] = call float @llvm.sin.f32(float 5.000000e-01)
diff --git a/llvm/test/Transforms/InstSimplify/exp10.ll b/llvm/test/Transforms/InstSimplify/exp10.ll
index 17c081137ad1c..edb2871e523bb 100644
--- a/llvm/test/Transforms/InstSimplify/exp10.ll
+++ b/llvm/test/Transforms/InstSimplify/exp10.ll
@@ -35,7 +35,7 @@ define <2 x float> @exp10_exp10_vector(<2 x float> %x) {
define float @exp10_exp10_const(float %x) {
; CHECK-LABEL: define float @exp10_exp10_const(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[EXP101:%.*]] = call float @llvm.exp10.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[EXP101:%.*]] = call float @llvm.exp10.f32(float +inf)
; CHECK-NEXT: ret float [[EXP101]]
;
%exp100 = call float @llvm.exp10.f32(float 42.0)
@@ -155,7 +155,7 @@ define float @exp10_one() {
define float @exp10_negone() {
; CHECK-LABEL: define float @exp10_negone() {
-; CHECK-NEXT: ret float 0x3FB99999A0000000
+; CHECK-NEXT: ret float 1.000000e-01
;
%ret = call float @llvm.exp10.f32(float -1.0)
ret float %ret
@@ -171,7 +171,7 @@ define float @exp10_two() {
define float @exp10_negtwo() {
; CHECK-LABEL: define float @exp10_negtwo() {
-; CHECK-NEXT: ret float 0x3F847AE140000000
+; CHECK-NEXT: ret float f0x3C23D70A
;
%ret = call float @llvm.exp10.f32(float -2.0)
ret float %ret
@@ -179,7 +179,7 @@ define float @exp10_negtwo() {
define float @exp10_inf() {
; CHECK-LABEL: define float @exp10_inf() {
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.exp10.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.exp10.f32(float +inf)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.exp10.f32(float 0x7FF0000000000000)
@@ -188,7 +188,7 @@ define float @exp10_inf() {
define float @exp10_neginf() {
; CHECK-LABEL: define float @exp10_neginf() {
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.exp10.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.exp10.f32(float -inf)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.exp10.f32(float 0xFFF0000000000000)
@@ -197,7 +197,7 @@ define float @exp10_neginf() {
define float @exp10_qnan() {
; CHECK-LABEL: define float @exp10_qnan() {
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.exp10.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.exp10.f32(float +qnan)
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.exp10.f32(float 0x7FF8000000000000)
@@ -206,7 +206,7 @@ define float @exp10_qnan() {
define float @exp10_snan() {
; CHECK-LABEL: define float @exp10_snan() {
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.exp10.f32(float 0x7FF0000020000000)
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.exp10.f32(float +snan(0x1))
; CHECK-NEXT: ret float [[RET]]
;
%ret = call float @llvm.exp10.f32(float bitcast (i32 2139095041 to float))
@@ -231,7 +231,7 @@ define float @exp10_neg_denorm() {
define ppc_fp128 @exp10_one_ppcf128() {
; CHECK-LABEL: define ppc_fp128 @exp10_one_ppcf128() {
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 0xM3FF00000000000000000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 1.000000e+00)
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 0xM3FF00000000000000000000000000000)
@@ -240,7 +240,7 @@ define ppc_fp128 @exp10_one_ppcf128() {
define ppc_fp128 @exp10_negone_ppcf128() {
; CHECK-LABEL: define ppc_fp128 @exp10_negone_ppcf128() {
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 0xMBFF00000000000000000000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 -1.000000e+00)
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 0xMBFF00000000000000000000000000000)
@@ -249,7 +249,7 @@ define ppc_fp128 @exp10_negone_ppcf128() {
define ppc_fp128 @canonicalize_noncanonical_zero_1_ppcf128() {
; CHECK-LABEL: define ppc_fp128 @canonicalize_noncanonical_zero_1_ppcf128() {
-; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 0xM00000000000000000000000000000001)
+; CHECK-NEXT: [[RET:%.*]] = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 f0x00000000000000010000000000000000)
; CHECK-NEXT: ret ppc_fp128 [[RET]]
;
%ret = call ppc_fp128 @llvm.exp10.ppcf128(ppc_fp128 0xM00000000000000000000000000000001)
@@ -266,7 +266,7 @@ define <2 x float> @exp10_splat_4() {
define <2 x float> @exp10_splat_qnan() {
; CHECK-LABEL: define <2 x float> @exp10_splat_qnan() {
-; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.exp10.v2f32(<2 x float> splat (float 0x7FF8000000000000))
+; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.exp10.v2f32(<2 x float> splat (float +qnan))
; CHECK-NEXT: ret <2 x float> [[RET]]
;
%ret = call <2 x float> @llvm.exp10.v2f32(<2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>)
@@ -275,7 +275,7 @@ define <2 x float> @exp10_splat_qnan() {
define <2 x float> @exp10_splat_inf() {
; CHECK-LABEL: define <2 x float> @exp10_splat_inf() {
-; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.exp10.v2f32(<2 x float> splat (float 0x7FF0000000000000))
+; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.exp10.v2f32(<2 x float> splat (float +inf))
; CHECK-NEXT: ret <2 x float> [[RET]]
;
%ret = call <2 x float> @llvm.exp10.v2f32(<2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>)
@@ -284,7 +284,7 @@ define <2 x float> @exp10_splat_inf() {
define <2 x float> @exp10_splat_neginf() {
; CHECK-LABEL: define <2 x float> @exp10_splat_neginf() {
-; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.exp10.v2f32(<2 x float> splat (float 0xFFF0000000000000))
+; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.exp10.v2f32(<2 x float> splat (float -inf))
; CHECK-NEXT: ret <2 x float> [[RET]]
;
%ret = call <2 x float> @llvm.exp10.v2f32(<2 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000>)
@@ -293,7 +293,7 @@ define <2 x float> @exp10_splat_neginf() {
define <2 x float> @exp10_splat_undef_inf() {
; CHECK-LABEL: define <2 x float> @exp10_splat_undef_inf() {
-; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.exp10.v2f32(<2 x float> <float undef, float 0x7FF0000000000000>)
+; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.exp10.v2f32(<2 x float> <float undef, float +inf>)
; CHECK-NEXT: ret <2 x float> [[RET]]
;
%ret = call <2 x float> @llvm.exp10.v2f32(<2 x float> <float undef, float 0x7FF0000000000000>)
diff --git a/llvm/test/Transforms/InstSimplify/fcmp.ll b/llvm/test/Transforms/InstSimplify/fcmp.ll
index 8c0a1a55cb2cb..fd474b119826f 100644
--- a/llvm/test/Transforms/InstSimplify/fcmp.ll
+++ b/llvm/test/Transforms/InstSimplify/fcmp.ll
@@ -23,7 +23,7 @@ define i1 @pr130408(x86_fp80 %x) {
; CHECK-NEXT: [[MASKED:%.*]] = and i80 [[BITS]], -604444463063240877801473
; CHECK-NEXT: [[OR:%.*]] = or i80 [[MASKED]], 302194561415509874573312
; CHECK-NEXT: [[FP:%.*]] = bitcast i80 [[OR]] to x86_fp80
-; CHECK-NEXT: [[RES:%.*]] = fcmp uno x86_fp80 [[FP]], 0xK00000000000000000000
+; CHECK-NEXT: [[RES:%.*]] = fcmp uno x86_fp80 [[FP]], 0.000000e+00
; CHECK-NEXT: ret i1 [[RES]]
;
%bits = bitcast x86_fp80 %x to i80
diff --git a/llvm/test/Transforms/InstSimplify/floating-point-arithmetic.ll b/llvm/test/Transforms/InstSimplify/floating-point-arithmetic.ll
index 0312e8ed7d9ba..25a46c65b3c56 100644
--- a/llvm/test/Transforms/InstSimplify/floating-point-arithmetic.ll
+++ b/llvm/test/Transforms/InstSimplify/floating-point-arithmetic.ll
@@ -172,7 +172,7 @@ define double @fmul_X_1(double %a) {
define half @fmul_nnan_ninf_nneg_0.0(i15 %x) {
; CHECK-LABEL: @fmul_nnan_ninf_nneg_0.0(
-; CHECK-NEXT: ret half 0xH0000
+; CHECK-NEXT: ret half 0.000000e+00
;
%f = uitofp i15 %x to half
%r = fmul half %f, 0.0
@@ -181,7 +181,7 @@ define half @fmul_nnan_ninf_nneg_0.0(i15 %x) {
define half @fmul_nnan_ninf_nneg_n0.0(i15 %x) {
; CHECK-LABEL: @fmul_nnan_ninf_nneg_n0.0(
-; CHECK-NEXT: ret half 0xH8000
+; CHECK-NEXT: ret half -0.000000e+00
;
%f = uitofp i15 %x to half
%r = fmul half %f, -0.0
@@ -193,7 +193,7 @@ define half @fmul_nnan_ninf_nneg_n0.0(i15 %x) {
define half @fmul_nnan_nneg_0.0(i16 %x) {
; CHECK-LABEL: @fmul_nnan_nneg_0.0(
; CHECK-NEXT: [[F:%.*]] = uitofp i16 [[X:%.*]] to half
-; CHECK-NEXT: [[R:%.*]] = fmul half [[F]], 0xH0000
+; CHECK-NEXT: [[R:%.*]] = fmul half [[F]], 0.000000e+00
; CHECK-NEXT: ret half [[R]]
;
%f = uitofp i16 %x to half
@@ -275,7 +275,7 @@ define float @src_fma_nzero_neg(float nofpclass(inf nan pzero psub pnorm) %f, fl
define { float, float } @test_fmul_0_assumed_finite(float %x) {
; CHECK-LABEL: @test_fmul_0_assumed_finite(
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[IS_FINITE_X:%.*]] = fcmp one float [[FABS_X]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_FINITE_X:%.*]] = fcmp one float [[FABS_X]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_FINITE_X]])
; CHECK-NEXT: ret { float, float } { float 0.000000e+00, float -0.000000e+00 }
;
@@ -478,7 +478,7 @@ define <2 x float> @fabs_select_neg0_neg1_vector(i32 %c) {
define float @fabs_select_nan_nan(i32 %c) {
; CHECK-LABEL: @fabs_select_nan_nan(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float 0x7FF8000000000000, float 0x7FF8000100000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float +qnan, float +nan(0x8)
; CHECK-NEXT: ret float [[SELECT]]
;
%cmp = icmp eq i32 %c, 0
@@ -490,7 +490,7 @@ define float @fabs_select_nan_nan(i32 %c) {
define <2 x float> @fabs_select_nan_nan_vector(i32 %c) {
; CHECK-LABEL: @fabs_select_nan_nan_vector(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> splat (float 0x7FF8000100000000)
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float +qnan), <2 x float> splat (float +nan(0x8))
; CHECK-NEXT: ret <2 x float> [[SELECT]]
;
%cmp = icmp eq i32 %c, 0
@@ -502,7 +502,7 @@ define <2 x float> @fabs_select_nan_nan_vector(i32 %c) {
define float @fabs_select_negnan_nan(i32 %c) {
; CHECK-LABEL: @fabs_select_negnan_nan(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float 0xFFF8000000000000, float 0x7FF8000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float -qnan, float +qnan
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
; CHECK-NEXT: ret float [[FABS]]
;
@@ -515,7 +515,7 @@ define float @fabs_select_negnan_nan(i32 %c) {
define <2 x float> @fabs_select_negnan_nan_vector(i32 %c) {
; CHECK-LABEL: @fabs_select_negnan_nan_vector(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float 0xFFF8000000000000), <2 x float> splat (float 0x7FF8000000000000)
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float -qnan), <2 x float> splat (float +qnan)
; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[SELECT]])
; CHECK-NEXT: ret <2 x float> [[FABS]]
;
@@ -528,7 +528,7 @@ define <2 x float> @fabs_select_negnan_nan_vector(i32 %c) {
define float @fabs_select_negnan_negnan(i32 %c) {
; CHECK-LABEL: @fabs_select_negnan_negnan(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float 0xFFF8000000000000, float 0x7FF8000100000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float -qnan, float +nan(0x8)
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
; CHECK-NEXT: ret float [[FABS]]
;
@@ -541,7 +541,7 @@ define float @fabs_select_negnan_negnan(i32 %c) {
define <2 x float> @fabs_select_negnan_negnan_vector(i32 %c) {
; CHECK-LABEL: @fabs_select_negnan_negnan_vector(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float 0xFFF8000000000000), <2 x float> splat (float 0x7FF8000100000000)
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float -qnan), <2 x float> splat (float +nan(0x8))
; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[SELECT]])
; CHECK-NEXT: ret <2 x float> [[FABS]]
;
@@ -554,7 +554,7 @@ define <2 x float> @fabs_select_negnan_negnan_vector(i32 %c) {
define float @fabs_select_negnan_negzero(i32 %c) {
; CHECK-LABEL: @fabs_select_negnan_negzero(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float 0xFFF8000000000000, float -0.000000e+00
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float -qnan, float -0.000000e+00
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
; CHECK-NEXT: ret float [[FABS]]
;
@@ -567,7 +567,7 @@ define float @fabs_select_negnan_negzero(i32 %c) {
define <2 x float> @fabs_select_negnan_negzero_vector(i32 %c) {
; CHECK-LABEL: @fabs_select_negnan_negzero_vector(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float 0xFFF8000000000000), <2 x float> splat (float -0.000000e+00)
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float -qnan), <2 x float> splat (float -0.000000e+00)
; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[SELECT]])
; CHECK-NEXT: ret <2 x float> [[FABS]]
;
@@ -580,7 +580,7 @@ define <2 x float> @fabs_select_negnan_negzero_vector(i32 %c) {
define float @fabs_select_negnan_zero(i32 %c) {
; CHECK-LABEL: @fabs_select_negnan_zero(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float 0xFFF8000000000000, float 0.000000e+00
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], float -qnan, float 0.000000e+00
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
; CHECK-NEXT: ret float [[FABS]]
;
@@ -593,7 +593,7 @@ define float @fabs_select_negnan_zero(i32 %c) {
define <2 x float> @fabs_select_negnan_zero_vector(i32 %c) {
; CHECK-LABEL: @fabs_select_negnan_zero_vector(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float 0xFFF8000000000000), <2 x float> zeroinitializer
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x float> splat (float -qnan), <2 x float> zeroinitializer
; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[SELECT]])
; CHECK-NEXT: ret <2 x float> [[FABS]]
;
@@ -910,7 +910,7 @@ define float @maxnum_with_pos_one_op(float %a) {
define double @fadd_nnan_inf_op0(double %x) {
; CHECK-LABEL: @fadd_nnan_inf_op0(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%r = fadd nnan double 0x7ff0000000000000, %x
ret double %r
@@ -918,7 +918,7 @@ define double @fadd_nnan_inf_op0(double %x) {
define double @fadd_nnan_inf_op1(double %x) {
; CHECK-LABEL: @fadd_nnan_inf_op1(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%r = fadd nnan double %x, 0x7ff0000000000000
ret double %r
@@ -926,7 +926,7 @@ define double @fadd_nnan_inf_op1(double %x) {
define <2 x double> @fadd_nnan_neginf_op1(<2 x double> %x) {
; CHECK-LABEL: @fadd_nnan_neginf_op1(
-; CHECK-NEXT: ret <2 x double> <double 0xFFF0000000000000, double poison>
+; CHECK-NEXT: ret <2 x double> <double -inf, double poison>
;
%r = fadd nnan <2 x double> %x, <double 0xfff0000000000000, double poison>
ret <2 x double> %r
@@ -934,7 +934,7 @@ define <2 x double> @fadd_nnan_neginf_op1(<2 x double> %x) {
define double @fadd_nnan_neginf_op0(double %x) {
; CHECK-LABEL: @fadd_nnan_neginf_op0(
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%r = fadd nnan double 0xfff0000000000000, %x
ret double %r
@@ -944,7 +944,7 @@ define double @fadd_nnan_neginf_op0(double %x) {
define double @fadd_inf_op0(double %x) {
; CHECK-LABEL: @fadd_inf_op0(
-; CHECK-NEXT: [[R:%.*]] = fadd double 0x7FF0000000000000, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = fadd double +inf, [[X:%.*]]
; CHECK-NEXT: ret double [[R]]
;
%r = fadd double 0x7ff0000000000000, %x
@@ -953,7 +953,7 @@ define double @fadd_inf_op0(double %x) {
define double @fsub_nnan_inf_op0(double %x) {
; CHECK-LABEL: @fsub_nnan_inf_op0(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%r = fsub nnan double 0x7ff0000000000000, %x
ret double %r
@@ -963,7 +963,7 @@ define double @fsub_nnan_inf_op0(double %x) {
define double @fsub_nnan_inf_op1(double %x) {
; CHECK-LABEL: @fsub_nnan_inf_op1(
-; CHECK-NEXT: ret double 0xFFF0000000000000
+; CHECK-NEXT: ret double -inf
;
%r = fsub nnan double %x, 0x7ff0000000000000
ret double %r
@@ -971,7 +971,7 @@ define double @fsub_nnan_inf_op1(double %x) {
define <2 x double> @fsub_nnan_inf_op1_vec(<2 x double> %x) {
; CHECK-LABEL: @fsub_nnan_inf_op1_vec(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF0000000000000, double poison>
+; CHECK-NEXT: ret <2 x double> <double +inf, double poison>
;
%r = fsub nnan <2 x double> %x, <double 0xfff0000000000000, double poison>
ret <2 x double> %r
@@ -979,7 +979,7 @@ define <2 x double> @fsub_nnan_inf_op1_vec(<2 x double> %x) {
define <2 x double> @fsub_nnan_neginf_op0(<2 x double> %x) {
; CHECK-LABEL: @fsub_nnan_neginf_op0(
-; CHECK-NEXT: ret <2 x double> <double 0xFFF0000000000000, double poison>
+; CHECK-NEXT: ret <2 x double> <double -inf, double poison>
;
%r = fsub nnan <2 x double> <double 0xfff0000000000000, double poison>, %x
ret <2 x double> %r
@@ -989,7 +989,7 @@ define <2 x double> @fsub_nnan_neginf_op0(<2 x double> %x) {
define double @fsub_nnan_neginf_op1(double %x) {
; CHECK-LABEL: @fsub_nnan_neginf_op1(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%r = fsub nnan double %x, 0xfff0000000000000
ret double %r
@@ -999,7 +999,7 @@ define double @fsub_nnan_neginf_op1(double %x) {
define double @fsub_inf_op0(double %x) {
; CHECK-LABEL: @fsub_inf_op0(
-; CHECK-NEXT: [[R:%.*]] = fsub double 0x7FF0000000000000, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = fsub double +inf, [[X:%.*]]
; CHECK-NEXT: ret double [[R]]
;
%r = fsub double 0x7ff0000000000000, %x
@@ -1260,8 +1260,8 @@ define half @fabs_select_fabs(half noundef %x) {
; CHECK-LABEL: @fabs_select_fabs(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ABS1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt half [[ABS1]], 0xH0000
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], half [[X]], half 0xH0000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt half [[ABS1]], 0.000000e+00
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], half [[X]], half 0.000000e+00
; CHECK-NEXT: [[ABS2:%.*]] = call half @llvm.fabs.f16(half [[SEL]])
; CHECK-NEXT: ret half [[ABS2]]
;
@@ -1277,7 +1277,7 @@ entry:
define float @fabs_fmul_nan(float %x) {
; CHECK-LABEL: @fabs_fmul_nan(
; CHECK-NEXT: [[ABS:%.*]] = call nnan float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[MUL:%.*]] = fmul float [[ABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[MUL:%.*]] = fmul float [[ABS]], +inf
; CHECK-NEXT: [[ABS2:%.*]] = call float @llvm.fabs.f32(float [[MUL]])
; CHECK-NEXT: ret float [[ABS2]]
;
@@ -1290,7 +1290,7 @@ define float @fabs_fmul_nan(float %x) {
define <2 x float> @fabs_fmul_nan_vector(<2 x float> %x) {
; CHECK-LABEL: @fabs_fmul_nan_vector(
; CHECK-NEXT: [[ABS:%.*]] = call nnan <2 x float> @llvm.fabs.v2f32(<2 x float> [[X:%.*]])
-; CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[ABS]], splat (float 0x7FF0000000000000)
+; CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[ABS]], splat (float +inf)
; CHECK-NEXT: [[ABS2:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[MUL]])
; CHECK-NEXT: ret <2 x float> [[ABS2]]
;
diff --git a/llvm/test/Transforms/InstSimplify/floating-point-compare.ll b/llvm/test/Transforms/InstSimplify/floating-point-compare.ll
index 912869fb581b3..66d84a03c254c 100644
--- a/llvm/test/Transforms/InstSimplify/floating-point-compare.ll
+++ b/llvm/test/Transforms/InstSimplify/floating-point-compare.ll
@@ -1719,7 +1719,7 @@ define i1 @is_infinite(float %x) {
define i1 @is_infinite_assumed_finite(float %x) {
; CHECK-LABEL: @is_infinite_assumed_finite(
; CHECK-NEXT: [[XABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[NOT_INF:%.*]] = fcmp one float [[XABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[NOT_INF:%.*]] = fcmp one float [[XABS]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[NOT_INF]])
; CHECK-NEXT: ret i1 false
;
@@ -1733,7 +1733,7 @@ define i1 @is_infinite_assumed_finite(float %x) {
define i1 @une_inf_assumed_not_inf(float %x) {
; CHECK-LABEL: @une_inf_assumed_not_inf(
; CHECK-NEXT: [[XABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[NOT_INF:%.*]] = fcmp one float [[XABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[NOT_INF:%.*]] = fcmp one float [[XABS]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[NOT_INF]])
; CHECK-NEXT: ret i1 true
;
@@ -1758,7 +1758,7 @@ define <2 x i1> @is_infinite_neg(<2 x float> %x) {
define i1 @is_infinite_or_nan(float %x) {
; CHECK-LABEL: @is_infinite_or_nan(
; CHECK-NEXT: [[X42:%.*]] = fadd ninf float [[X:%.*]], 4.200000e+01
-; CHECK-NEXT: [[R:%.*]] = fcmp ueq float [[X42]], 0xFFF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp ueq float [[X42]], -inf
; CHECK-NEXT: ret i1 [[R]]
;
%x42 = fadd ninf float %x, 42.0
@@ -1778,7 +1778,7 @@ define i1 @is_infinite_or_nan2(float %x) {
define i1 @is_infinite_or_nan2_assume(float %x) {
; CHECK-LABEL: @is_infinite_or_nan2_assume(
; CHECK-NEXT: [[XABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[IS_INF_OR_NAN:%.*]] = fcmp one float [[XABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_INF_OR_NAN:%.*]] = fcmp one float [[XABS]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_INF_OR_NAN]])
; CHECK-NEXT: ret i1 false
;
@@ -1822,7 +1822,7 @@ define <2 x i1> @is_finite_or_nan_commute(<2 x i8> %x) {
define i1 @is_finite_and_ordered(double %x) {
; CHECK-LABEL: @is_finite_and_ordered(
; CHECK-NEXT: [[XX:%.*]] = fmul ninf double [[X:%.*]], [[X]]
-; CHECK-NEXT: [[R:%.*]] = fcmp one double [[XX]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp one double [[XX]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%xx = fmul ninf double %x, %x
@@ -1843,7 +1843,7 @@ define i1 @is_finite(i1 %c, double %x) {
define i1 @is_finite_assume(i1 %c, double %x) {
; CHECK-LABEL: @is_finite_assume(
; CHECK-NEXT: [[XABS:%.*]] = call double @llvm.fabs.f64(double [[X:%.*]])
-; CHECK-NEXT: [[IS_INF_OR_NAN:%.*]] = fcmp one double [[XABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[IS_INF_OR_NAN:%.*]] = fcmp one double [[XABS]], +inf
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_INF_OR_NAN]])
; CHECK-NEXT: ret i1 true
;
@@ -2046,7 +2046,7 @@ bb:
define i1 @is_olt_smallest_normal_dynamic(float %x) denormal_fpenv(dynamic) {
; CHECK-LABEL: @is_olt_smallest_normal_dynamic(
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], f0x00800000
; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]]
;
%is.denorm.or.zero = fcmp olt float %x, 0x3810000000000000
@@ -2055,7 +2055,7 @@ define i1 @is_olt_smallest_normal_dynamic(float %x) denormal_fpenv(dynamic) {
define i1 @is_olt_smallest_normal_ieee(float %x) denormal_fpenv(dynamic|ieee) {
; CHECK-LABEL: @is_olt_smallest_normal_ieee(
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], f0x00800000
; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]]
;
%is.denorm.or.zero = fcmp olt float %x, 0x3810000000000000
@@ -2064,7 +2064,7 @@ define i1 @is_olt_smallest_normal_ieee(float %x) denormal_fpenv(dynamic|ieee) {
define i1 @is_olt_smallest_normal_preserve_sign(float %x) denormal_fpenv(dynamic|preservesign) {
; CHECK-LABEL: @is_olt_smallest_normal_preserve_sign(
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], f0x00800000
; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]]
;
%is.denorm.or.zero = fcmp olt float %x, 0x3810000000000000
@@ -2073,7 +2073,7 @@ define i1 @is_olt_smallest_normal_preserve_sign(float %x) denormal_fpenv(dynamic
define i1 @is_olt_smallest_normal_positive_zero(float %x) denormal_fpenv(dynamic|positivezero) {
; CHECK-LABEL: @is_olt_smallest_normal_positive_zero(
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], f0x00800000
; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]]
;
%is.denorm.or.zero = fcmp olt float %x, 0x3810000000000000
@@ -2083,7 +2083,7 @@ define i1 @is_olt_smallest_normal_positive_zero(float %x) denormal_fpenv(dynamic
define i1 @is_fabs_olt_smallest_normal_dynamic(float %x) denormal_fpenv(dynamic) {
; CHECK-LABEL: @is_fabs_olt_smallest_normal_dynamic(
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], f0x00800000
; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]]
;
%fabs.x = call float @llvm.fabs.f32(float %x)
@@ -2094,7 +2094,7 @@ define i1 @is_fabs_olt_smallest_normal_dynamic(float %x) denormal_fpenv(dynamic)
define i1 @is_fabs_olt_smallest_normal_ieee(float %x) denormal_fpenv(dynamic|ieee) {
; CHECK-LABEL: @is_fabs_olt_smallest_normal_ieee(
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], f0x00800000
; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]]
;
%fabs.x = call float @llvm.fabs.f32(float %x)
@@ -2105,7 +2105,7 @@ define i1 @is_fabs_olt_smallest_normal_ieee(float %x) denormal_fpenv(dynamic|iee
define i1 @is_fabs_olt_smallest_normal_preserve_sign(float %x) denormal_fpenv(dynamic|preservesign) {
; CHECK-LABEL: @is_fabs_olt_smallest_normal_preserve_sign(
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], f0x00800000
; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]]
;
%fabs.x = call float @llvm.fabs.f32(float %x)
@@ -2116,7 +2116,7 @@ define i1 @is_fabs_olt_smallest_normal_preserve_sign(float %x) denormal_fpenv(dy
define i1 @is_fabs_olt_smallest_normal_positive_zero(float %x) denormal_fpenv(dynamic|positivezero) {
; CHECK-LABEL: @is_fabs_olt_smallest_normal_positive_zero(
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], 0x3810000000000000
+; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], f0x00800000
; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]]
;
%fabs.x = call float @llvm.fabs.f32(float %x)
diff --git a/llvm/test/Transforms/InstSimplify/fminmax-folds.ll b/llvm/test/Transforms/InstSimplify/fminmax-folds.ll
index 091e85920c0df..f849e406cf76f 100644
--- a/llvm/test/Transforms/InstSimplify/fminmax-folds.ll
+++ b/llvm/test/Transforms/InstSimplify/fminmax-folds.ll
@@ -17,8 +17,8 @@ define void @minmax_qnan_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %mi
; CHECK-LABEL: @minmax_qnan_f32(
; CHECK-NEXT: store float [[X:%.*]], ptr [[MINNUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X]], ptr [[MAXNUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x7FFF000000000000, ptr [[MINIMUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x7FFF000000000000, ptr [[MAXIMUM_RES:%.*]], align 4
+; CHECK-NEXT: store float +nan(0x380000), ptr [[MINIMUM_RES:%.*]], align 4
+; CHECK-NEXT: store float +nan(0x380000), ptr [[MAXIMUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X]], ptr [[MINIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X]], ptr [[MAXIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: ret void
@@ -43,10 +43,10 @@ define void @minmax_qnan_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %mi
; Note that maxnum/minnum return qnan here for snan inputs, unlike maximumnum/minimumnum
define void @minmax_snan_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_snan_f32(
-; CHECK-NEXT: store float 0x7FFC000000000000, ptr [[MINNUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x7FFC000000000000, ptr [[MAXNUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x7FFC000000000000, ptr [[MINIMUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x7FFC000000000000, ptr [[MAXIMUM_RES:%.*]], align 4
+; CHECK-NEXT: store float +nan(0x200000), ptr [[MINNUM_RES:%.*]], align 4
+; CHECK-NEXT: store float +nan(0x200000), ptr [[MAXNUM_RES:%.*]], align 4
+; CHECK-NEXT: store float +nan(0x200000), ptr [[MINIMUM_RES:%.*]], align 4
+; CHECK-NEXT: store float +nan(0x200000), ptr [[MAXIMUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X:%.*]], ptr [[MINIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X]], ptr [[MAXIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: ret void
@@ -72,8 +72,8 @@ define void @minmax_qnan_nxv2f64_op0(<vscale x 2 x double> %x, ptr %minnum_res,
; CHECK-LABEL: @minmax_qnan_nxv2f64_op0(
; CHECK-NEXT: store <vscale x 2 x double> [[X:%.*]], ptr [[MINNUM_RES:%.*]], align 16
; CHECK-NEXT: store <vscale x 2 x double> [[X]], ptr [[MAXNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <vscale x 2 x double> splat (double 0x7FF8000DEAD00000), ptr [[MINIMUM_RES:%.*]], align 16
-; CHECK-NEXT: store <vscale x 2 x double> splat (double 0x7FF8000DEAD00000), ptr [[MAXIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <vscale x 2 x double> splat (double +nan(0xDEAD00000)), ptr [[MINIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <vscale x 2 x double> splat (double +nan(0xDEAD00000)), ptr [[MAXIMUM_RES:%.*]], align 16
; CHECK-NEXT: store <vscale x 2 x double> [[X]], ptr [[MINIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: store <vscale x 2 x double> [[X]], ptr [[MAXIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: ret void
@@ -98,10 +98,10 @@ define void @minmax_qnan_nxv2f64_op0(<vscale x 2 x double> %x, ptr %minnum_res,
; Note that maxnum/minnum return qnan here for snan inputs, unlike maximumnum/minimumnum
define void @minmax_snan_nxv2f64_op1(<vscale x 2 x double> %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_snan_nxv2f64_op1(
-; CHECK-NEXT: store <vscale x 2 x double> splat (double 0x7FFC00DEAD00DEAD), ptr [[MINNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <vscale x 2 x double> splat (double 0x7FFC00DEAD00DEAD), ptr [[MAXNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <vscale x 2 x double> splat (double 0x7FFC00DEAD00DEAD), ptr [[MINIMUM_RES:%.*]], align 16
-; CHECK-NEXT: store <vscale x 2 x double> splat (double 0x7FFC00DEAD00DEAD), ptr [[MAXIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <vscale x 2 x double> splat (double +nan(0x400DEAD00DEAD)), ptr [[MINNUM_RES:%.*]], align 16
+; CHECK-NEXT: store <vscale x 2 x double> splat (double +nan(0x400DEAD00DEAD)), ptr [[MAXNUM_RES:%.*]], align 16
+; CHECK-NEXT: store <vscale x 2 x double> splat (double +nan(0x400DEAD00DEAD)), ptr [[MINIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <vscale x 2 x double> splat (double +nan(0x400DEAD00DEAD)), ptr [[MAXIMUM_RES:%.*]], align 16
; CHECK-NEXT: store <vscale x 2 x double> [[X:%.*]], ptr [[MINIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: store <vscale x 2 x double> [[X]], ptr [[MAXIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: ret void
@@ -127,12 +127,12 @@ define void @minmax_snan_nxv2f64_op1(<vscale x 2 x double> %x, ptr %minnum_res,
; return <%x0, QNaN> and InstSimplify cannot create the extra instructions required to construct this.
define void @minmax_mixed_snan_qnan_v2f64(<2 x double> %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_mixed_snan_qnan_v2f64(
-; CHECK-NEXT: [[MINNUM:%.*]] = call <2 x double> @llvm.minnum.v2f64(<2 x double> <double 0x7FF400DEAD00DEAD, double 0x7FF8000FEED00000>, <2 x double> [[X:%.*]])
+; CHECK-NEXT: [[MINNUM:%.*]] = call <2 x double> @llvm.minnum.v2f64(<2 x double> <double +snan(0x400DEAD00DEAD), double +nan(0xFEED00000)>, <2 x double> [[X:%.*]])
; CHECK-NEXT: store <2 x double> [[MINNUM]], ptr [[MINNUM_RES:%.*]], align 16
-; CHECK-NEXT: [[MAXNUM:%.*]] = call <2 x double> @llvm.maxnum.v2f64(<2 x double> <double 0x7FF400DEAD00DEAD, double 0x7FF8000FEED00000>, <2 x double> [[X]])
+; CHECK-NEXT: [[MAXNUM:%.*]] = call <2 x double> @llvm.maxnum.v2f64(<2 x double> <double +snan(0x400DEAD00DEAD), double +nan(0xFEED00000)>, <2 x double> [[X]])
; CHECK-NEXT: store <2 x double> [[MAXNUM]], ptr [[MAXNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> <double 0x7FFC00DEAD00DEAD, double 0x7FF8000FEED00000>, ptr [[MINIMUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> <double 0x7FFC00DEAD00DEAD, double 0x7FF8000FEED00000>, ptr [[MAXIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> <double +nan(0x400DEAD00DEAD), double +nan(0xFEED00000)>, ptr [[MINIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> <double +nan(0x400DEAD00DEAD), double +nan(0xFEED00000)>, ptr [[MAXIMUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MINIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MAXIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: ret void
@@ -160,8 +160,8 @@ define void @minmax_mixed_qnan_poison_v2f64(<2 x double> %x, ptr %minnum_res, pt
; CHECK-LABEL: @minmax_mixed_qnan_poison_v2f64(
; CHECK-NEXT: store <2 x double> [[X:%.*]], ptr [[MINNUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MAXNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> <double poison, double 0x7FF8000DEAD00000>, ptr [[MINIMUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> <double poison, double 0x7FF8000DEAD00000>, ptr [[MAXIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> <double poison, double +nan(0xDEAD00000)>, ptr [[MINIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> <double poison, double +nan(0xDEAD00000)>, ptr [[MAXIMUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MINIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MAXIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: ret void
@@ -253,15 +253,15 @@ define void @minmax_poison_op1_nxv2f64(<vscale x 2 x double> %x, ptr %minnum_res
; Can only optimize maxnum, minimum, and maximumnum without the nnan flag
define void @minmax_pos_inf_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_pos_inf_f32(
-; CHECK-NEXT: [[MINNUM:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[MINNUM:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float +inf)
; CHECK-NEXT: store float [[MINNUM]], ptr [[MINNUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x7FF0000000000000, ptr [[MAXNUM_RES:%.*]], align 4
+; CHECK-NEXT: store float +inf, ptr [[MAXNUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X]], ptr [[MINIMUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXIMUM:%.*]] = call float @llvm.maximum.f32(float [[X]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[MAXIMUM:%.*]] = call float @llvm.maximum.f32(float [[X]], float +inf)
; CHECK-NEXT: store float [[MAXIMUM]], ptr [[MAXIMUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MINIMUMNUM:%.*]] = call float @llvm.minimumnum.f32(float [[X]], float 0x7FF0000000000000)
+; CHECK-NEXT: [[MINIMUMNUM:%.*]] = call float @llvm.minimumnum.f32(float [[X]], float +inf)
; CHECK-NEXT: store float [[MINIMUMNUM]], ptr [[MINIMUMNUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x7FF0000000000000, ptr [[MAXIMUMNUM_RES:%.*]], align 4
+; CHECK-NEXT: store float +inf, ptr [[MAXIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: ret void
;
%minnum = call float @llvm.minnum.f32(float %x, float 0x7FF0000000000000)
@@ -285,11 +285,11 @@ define void @minmax_pos_inf_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr
define void @minmax_pos_inf_nnan_v2f32(<2 x float> %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_pos_inf_nnan_v2f32(
; CHECK-NEXT: store <2 x float> [[X:%.*]], ptr [[MINNUM_RES:%.*]], align 8
-; CHECK-NEXT: store <2 x float> splat (float 0x7FF0000000000000), ptr [[MAXNUM_RES:%.*]], align 8
+; CHECK-NEXT: store <2 x float> splat (float +inf), ptr [[MAXNUM_RES:%.*]], align 8
; CHECK-NEXT: store <2 x float> [[X]], ptr [[MINIMUM_RES:%.*]], align 8
-; CHECK-NEXT: store <2 x float> splat (float 0x7FF0000000000000), ptr [[MAXIMUM_RES:%.*]], align 8
+; CHECK-NEXT: store <2 x float> splat (float +inf), ptr [[MAXIMUM_RES:%.*]], align 8
; CHECK-NEXT: store <2 x float> [[X]], ptr [[MINIMUMNUM_RES:%.*]], align 8
-; CHECK-NEXT: store <2 x float> splat (float 0x7FF0000000000000), ptr [[MAXIMUMNUM_RES:%.*]], align 8
+; CHECK-NEXT: store <2 x float> splat (float +inf), ptr [[MAXIMUMNUM_RES:%.*]], align 8
; CHECK-NEXT: ret void
;
%minnum = call nnan <2 x float> @llvm.minnum.v2f32(<2 x float> splat (float 0x7FF0000000000000), <2 x float> %x)
@@ -322,14 +322,14 @@ define void @minmax_pos_inf_nnan_v2f32(<2 x float> %x, ptr %minnum_res, ptr %max
; Can only optimize minnum, maximum, and minimumnum without the nnan flag
define void @minmax_neg_inf_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_neg_inf_f32(
-; CHECK-NEXT: store float 0xFFF0000000000000, ptr [[MINNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXNUM:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 0xFFF0000000000000)
+; CHECK-NEXT: store float -inf, ptr [[MINNUM_RES:%.*]], align 4
+; CHECK-NEXT: [[MAXNUM:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float -inf)
; CHECK-NEXT: store float [[MAXNUM]], ptr [[MAXNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MINIMUM:%.*]] = call float @llvm.minimum.f32(float [[X]], float 0xFFF0000000000000)
+; CHECK-NEXT: [[MINIMUM:%.*]] = call float @llvm.minimum.f32(float [[X]], float -inf)
; CHECK-NEXT: store float [[MINIMUM]], ptr [[MINIMUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X]], ptr [[MAXIMUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0xFFF0000000000000, ptr [[MINIMUMNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call float @llvm.maximumnum.f32(float [[X]], float 0xFFF0000000000000)
+; CHECK-NEXT: store float -inf, ptr [[MINIMUMNUM_RES:%.*]], align 4
+; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call float @llvm.maximumnum.f32(float [[X]], float -inf)
; CHECK-NEXT: store float [[MAXIMUMNUM]], ptr [[MAXIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -353,11 +353,11 @@ define void @minmax_neg_inf_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr
; Can optimize all minmax variants if the nnan flag is set
define void @minmax_neg_inf_nnan_v2f64(<2 x double> %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_neg_inf_nnan_v2f64(
-; CHECK-NEXT: store <2 x double> splat (double 0xFFF0000000000000), ptr [[MINNUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> splat (double -inf), ptr [[MINNUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X:%.*]], ptr [[MAXNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> splat (double 0xFFF0000000000000), ptr [[MINIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> splat (double -inf), ptr [[MINIMUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MAXIMUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> splat (double 0xFFF0000000000000), ptr [[MINIMUMNUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> splat (double -inf), ptr [[MINIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MAXIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: ret void
;
@@ -391,17 +391,17 @@ define void @minmax_neg_inf_nnan_v2f64(<2 x double> %x, ptr %minnum_res, ptr %ma
; None of these should be optimized away without the nnan/ninf flags
define void @minmax_largest_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_largest_f32(
-; CHECK-NEXT: [[MINNUM:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MINNUM:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MINNUM]], ptr [[MINNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXNUM:%.*]] = call float @llvm.maxnum.f32(float [[X]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MAXNUM:%.*]] = call float @llvm.maxnum.f32(float [[X]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MAXNUM]], ptr [[MAXNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MINIMUM:%.*]] = call float @llvm.minimum.f32(float [[X]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MINIMUM:%.*]] = call float @llvm.minimum.f32(float [[X]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MINIMUM]], ptr [[MINIMUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXIMUM:%.*]] = call float @llvm.maximum.f32(float [[X]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MAXIMUM:%.*]] = call float @llvm.maximum.f32(float [[X]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MAXIMUM]], ptr [[MAXIMUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MINIMUMNUM:%.*]] = call float @llvm.minimumnum.f32(float [[X]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MINIMUMNUM:%.*]] = call float @llvm.minimumnum.f32(float [[X]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MINIMUMNUM]], ptr [[MINIMUMNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call float @llvm.maximumnum.f32(float [[X]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call float @llvm.maximumnum.f32(float [[X]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MAXIMUMNUM]], ptr [[MAXIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -425,15 +425,15 @@ define void @minmax_largest_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr
; We can optimize maxnum, minimum, and maximumnum if we know ninf is set
define void @minmax_largest_f32_ninf(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_largest_f32_ninf(
-; CHECK-NEXT: [[MINNUM:%.*]] = call ninf float @llvm.minnum.f32(float [[X:%.*]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MINNUM:%.*]] = call ninf float @llvm.minnum.f32(float [[X:%.*]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MINNUM]], ptr [[MINNUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x47EFFFFFE0000000, ptr [[MAXNUM_RES:%.*]], align 4
+; CHECK-NEXT: store float f0x7F7FFFFF, ptr [[MAXNUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X]], ptr [[MINIMUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXIMUM:%.*]] = call ninf float @llvm.maximum.f32(float [[X]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MAXIMUM:%.*]] = call ninf float @llvm.maximum.f32(float [[X]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MAXIMUM]], ptr [[MAXIMUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MINIMUMNUM:%.*]] = call ninf float @llvm.minimumnum.f32(float [[X]], float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[MINIMUMNUM:%.*]] = call ninf float @llvm.minimumnum.f32(float [[X]], float f0x7F7FFFFF)
; CHECK-NEXT: store float [[MINIMUMNUM]], ptr [[MINIMUMNUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0x47EFFFFFE0000000, ptr [[MAXIMUMNUM_RES:%.*]], align 4
+; CHECK-NEXT: store float f0x7F7FFFFF, ptr [[MAXIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: ret void
;
%minnum = call ninf float @llvm.minnum.f32(float %x, float 0x47EFFFFFE0000000)
@@ -457,11 +457,11 @@ define void @minmax_largest_f32_ninf(float %x, ptr %minnum_res, ptr %maxnum_res,
define void @minmax_largest_v2f32_ninf_nnan(<2 x float> %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_largest_v2f32_ninf_nnan(
; CHECK-NEXT: store <2 x float> [[X:%.*]], ptr [[MINNUM_RES:%.*]], align 8
-; CHECK-NEXT: store <2 x float> splat (float 0x47EFFFFFE0000000), ptr [[MAXNUM_RES:%.*]], align 8
+; CHECK-NEXT: store <2 x float> splat (float f0x7F7FFFFF), ptr [[MAXNUM_RES:%.*]], align 8
; CHECK-NEXT: store <2 x float> [[X]], ptr [[MINIMUM_RES:%.*]], align 8
-; CHECK-NEXT: store <2 x float> splat (float 0x47EFFFFFE0000000), ptr [[MAXIMUM_RES:%.*]], align 8
+; CHECK-NEXT: store <2 x float> splat (float f0x7F7FFFFF), ptr [[MAXIMUM_RES:%.*]], align 8
; CHECK-NEXT: store <2 x float> [[X]], ptr [[MINIMUMNUM_RES:%.*]], align 8
-; CHECK-NEXT: store <2 x float> splat (float 0x47EFFFFFE0000000), ptr [[MAXIMUMNUM_RES:%.*]], align 8
+; CHECK-NEXT: store <2 x float> splat (float f0x7F7FFFFF), ptr [[MAXIMUMNUM_RES:%.*]], align 8
; CHECK-NEXT: ret void
;
%minnum = call ninf nnan <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> splat (float 0x47EFFFFFE0000000))
@@ -494,17 +494,17 @@ define void @minmax_largest_v2f32_ninf_nnan(<2 x float> %x, ptr %minnum_res, ptr
; None of these should be optimized away without the nnan/ninf flags
define void @minmax_neg_largest_f32(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_neg_largest_f32(
-; CHECK-NEXT: [[MINNUM:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: [[MINNUM:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MINNUM]], ptr [[MINNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXNUM:%.*]] = call float @llvm.maxnum.f32(float [[X]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: [[MAXNUM:%.*]] = call float @llvm.maxnum.f32(float [[X]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MAXNUM]], ptr [[MAXNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MINIMUM:%.*]] = call float @llvm.minimum.f32(float [[X]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: [[MINIMUM:%.*]] = call float @llvm.minimum.f32(float [[X]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MINIMUM]], ptr [[MINIMUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXIMUM:%.*]] = call float @llvm.maximum.f32(float [[X]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: [[MAXIMUM:%.*]] = call float @llvm.maximum.f32(float [[X]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MAXIMUM]], ptr [[MAXIMUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MINIMUMNUM:%.*]] = call float @llvm.minimumnum.f32(float [[X]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: [[MINIMUMNUM:%.*]] = call float @llvm.minimumnum.f32(float [[X]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MINIMUMNUM]], ptr [[MINIMUMNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call float @llvm.maximumnum.f32(float [[X]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call float @llvm.maximumnum.f32(float [[X]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MAXIMUMNUM]], ptr [[MAXIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -528,14 +528,14 @@ define void @minmax_neg_largest_f32(float %x, ptr %minnum_res, ptr %maxnum_res,
; We can optimize minnum, maximum, and minimumnum if we know ninf is set
define void @minmax_neg_largest_f32_ninf(float %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_neg_largest_f32_ninf(
-; CHECK-NEXT: store float 0xC7EFFFFFE0000000, ptr [[MINNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXNUM:%.*]] = call ninf float @llvm.maxnum.f32(float [[X:%.*]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: store float f0xFF7FFFFF, ptr [[MINNUM_RES:%.*]], align 4
+; CHECK-NEXT: [[MAXNUM:%.*]] = call ninf float @llvm.maxnum.f32(float [[X:%.*]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MAXNUM]], ptr [[MAXNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MINIMUM:%.*]] = call ninf float @llvm.minimum.f32(float [[X]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: [[MINIMUM:%.*]] = call ninf float @llvm.minimum.f32(float [[X]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MINIMUM]], ptr [[MINIMUM_RES:%.*]], align 4
; CHECK-NEXT: store float [[X]], ptr [[MAXIMUM_RES:%.*]], align 4
-; CHECK-NEXT: store float 0xC7EFFFFFE0000000, ptr [[MINIMUMNUM_RES:%.*]], align 4
-; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call ninf float @llvm.maximumnum.f32(float [[X]], float 0xC7EFFFFFE0000000)
+; CHECK-NEXT: store float f0xFF7FFFFF, ptr [[MINIMUMNUM_RES:%.*]], align 4
+; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call ninf float @llvm.maximumnum.f32(float [[X]], float f0xFF7FFFFF)
; CHECK-NEXT: store float [[MAXIMUMNUM]], ptr [[MAXIMUMNUM_RES:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -559,11 +559,11 @@ define void @minmax_neg_largest_f32_ninf(float %x, ptr %minnum_res, ptr %maxnum_
; All can be optimized if both the ninf and nnan flags are set (ignoring SNaN propagation in minnum/maxnum)
define void @minmax_neg_largest_nxv2f32_nnan_ninf(<vscale x 2 x float> %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_neg_largest_nxv2f32_nnan_ninf(
-; CHECK-NEXT: store <vscale x 2 x float> splat (float 0xC7EFFFFFE0000000), ptr [[MINNUM_RES:%.*]], align 8
+; CHECK-NEXT: store <vscale x 2 x float> splat (float f0xFF7FFFFF), ptr [[MINNUM_RES:%.*]], align 8
; CHECK-NEXT: store <vscale x 2 x float> [[X:%.*]], ptr [[MAXNUM_RES:%.*]], align 8
-; CHECK-NEXT: store <vscale x 2 x float> splat (float 0xC7EFFFFFE0000000), ptr [[MINIMUM_RES:%.*]], align 8
+; CHECK-NEXT: store <vscale x 2 x float> splat (float f0xFF7FFFFF), ptr [[MINIMUM_RES:%.*]], align 8
; CHECK-NEXT: store <vscale x 2 x float> [[X]], ptr [[MAXIMUM_RES:%.*]], align 8
-; CHECK-NEXT: store <vscale x 2 x float> splat (float 0xC7EFFFFFE0000000), ptr [[MINIMUMNUM_RES:%.*]], align 8
+; CHECK-NEXT: store <vscale x 2 x float> splat (float f0xFF7FFFFF), ptr [[MINIMUMNUM_RES:%.*]], align 8
; CHECK-NEXT: store <vscale x 2 x float> [[X]], ptr [[MAXIMUMNUM_RES:%.*]], align 8
; CHECK-NEXT: ret void
;
@@ -594,11 +594,11 @@ define void @minmax_neg_largest_nxv2f32_nnan_ninf(<vscale x 2 x float> %x, ptr %
define void @minmax_mixed_pos_inf_poison_v2f64_nnan(<2 x double> %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_mixed_pos_inf_poison_v2f64_nnan(
; CHECK-NEXT: store <2 x double> [[X:%.*]], ptr [[MINNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> <double poison, double 0x7FF0000000000000>, ptr [[MAXNUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> <double poison, double +inf>, ptr [[MAXNUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MINIMUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> <double poison, double 0x7FF0000000000000>, ptr [[MAXIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> <double poison, double +inf>, ptr [[MAXIMUM_RES:%.*]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[MINIMUMNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <2 x double> <double poison, double 0x7FF0000000000000>, ptr [[MAXIMUMNUM_RES:%.*]], align 16
+; CHECK-NEXT: store <2 x double> <double poison, double +inf>, ptr [[MAXIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: ret void
;
%minnum = call nnan <2 x double> @llvm.minnum.v2f64(<2 x double> <double poison, double 0x7FF0000000000000>, <2 x double> %x)
@@ -630,14 +630,14 @@ define void @minmax_mixed_pos_inf_poison_v2f64_nnan(<2 x double> %x, ptr %minnum
; nnan maximumnum(<poison, +Inf, SNaN>, X) = <???, +Inf, X2>
define void @minmax_mixed_pos_inf_poison_snan_v3f32(<3 x float> %x, ptr %minnum_res, ptr %maxnum_res, ptr %minimum_res, ptr %maximum_res, ptr %minimumnum_res, ptr %maximumnum_res) {
; CHECK-LABEL: @minmax_mixed_pos_inf_poison_snan_v3f32(
-; CHECK-NEXT: [[MINNUM:%.*]] = call nnan <3 x float> @llvm.minnum.v3f32(<3 x float> <float poison, float 0x7FF0000000000000, float 0x7FF4000000000000>, <3 x float> [[X:%.*]])
+; CHECK-NEXT: [[MINNUM:%.*]] = call nnan <3 x float> @llvm.minnum.v3f32(<3 x float> <float poison, float +inf, float +snan(0x200000)>, <3 x float> [[X:%.*]])
; CHECK-NEXT: store <3 x float> [[MINNUM]], ptr [[MINNUM_RES:%.*]], align 16
-; CHECK-NEXT: store <3 x float> <float poison, float 0x7FF0000000000000, float 0x7FFC000000000000>, ptr [[MAXNUM_RES:%.*]], align 16
-; CHECK-NEXT: [[MINIMUM:%.*]] = call nnan <3 x float> @llvm.minimum.v3f32(<3 x float> <float poison, float 0x7FF0000000000000, float 0x7FF4000000000000>, <3 x float> [[X]])
+; CHECK-NEXT: store <3 x float> <float poison, float +inf, float +nan(0x200000)>, ptr [[MAXNUM_RES:%.*]], align 16
+; CHECK-NEXT: [[MINIMUM:%.*]] = call nnan <3 x float> @llvm.minimum.v3f32(<3 x float> <float poison, float +inf, float +snan(0x200000)>, <3 x float> [[X]])
; CHECK-NEXT: store <3 x float> [[MINIMUM]], ptr [[MINIMUM_RES:%.*]], align 16
-; CHECK-NEXT: store <3 x float> <float poison, float 0x7FF0000000000000, float 0x7FFC000000000000>, ptr [[MAXIMUM_RES:%.*]], align 16
+; CHECK-NEXT: store <3 x float> <float poison, float +inf, float +nan(0x200000)>, ptr [[MAXIMUM_RES:%.*]], align 16
; CHECK-NEXT: store <3 x float> [[X]], ptr [[MINIMUMNUM_RES:%.*]], align 16
-; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call nnan <3 x float> @llvm.maximumnum.v3f32(<3 x float> <float poison, float 0x7FF0000000000000, float 0x7FF4000000000000>, <3 x float> [[X]])
+; CHECK-NEXT: [[MAXIMUMNUM:%.*]] = call nnan <3 x float> @llvm.maximumnum.v3f32(<3 x float> <float poison, float +inf, float +snan(0x200000)>, <3 x float> [[X]])
; CHECK-NEXT: store <3 x float> [[MAXIMUMNUM]], ptr [[MAXIMUMNUM_RES:%.*]], align 16
; CHECK-NEXT: ret void
;
@@ -929,7 +929,7 @@ define <2 x float> @minmax_bitcast_v2f32_minimum(<2 x float> %x) {
; Test with bitcast from <1 x double> to <4 x half> (type size mismatch)
define <4 x half> @minmax_bitcast_v4f16_maximum(<4 x half> %x) {
; CHECK-LABEL: @minmax_bitcast_v4f16_maximum(
-; CHECK-NEXT: [[RESULT:%.*]] = call <4 x half> @llvm.maximum.v4f16(<4 x half> [[X:%.*]], <4 x half> bitcast (<1 x double> splat (double 0x400921FB54442D18) to <4 x half>))
+; CHECK-NEXT: [[RESULT:%.*]] = call <4 x half> @llvm.maximum.v4f16(<4 x half> [[X:%.*]], <4 x half> bitcast (<1 x double> splat (double f0x400921FB54442D18) to <4 x half>))
; CHECK-NEXT: ret <4 x half> [[RESULT]]
;
%result = call <4 x half> @llvm.maximum.v4f16(<4 x half> %x, <4 x half> bitcast (<1 x double> <double 0x400921FB54442D18> to <4 x half>))
@@ -939,7 +939,7 @@ define <4 x half> @minmax_bitcast_v4f16_maximum(<4 x half> %x) {
; Test with bitcast from <2 x i16> to <2 x half> (integer to float)
define <2 x half> @minmax_bitcast_v2f16_minimumnum(<2 x half> %x) {
; CHECK-LABEL: @minmax_bitcast_v2f16_minimumnum(
-; CHECK-NEXT: [[RESULT:%.*]] = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> [[X:%.*]], <2 x half> <half 0xH3F80, half 0xH3F00>)
+; CHECK-NEXT: [[RESULT:%.*]] = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> [[X:%.*]], <2 x half> <half 1.875000e+00, half 1.750000e+00>)
; CHECK-NEXT: ret <2 x half> [[RESULT]]
;
%result = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %x, <2 x half> bitcast (<2 x i16> <i16 16256, i16 16128> to <2 x half>))
@@ -949,7 +949,7 @@ define <2 x half> @minmax_bitcast_v2f16_minimumnum(<2 x half> %x) {
; Test with bitcast from <4 x i16> to <4 x half> (matching element count but getAggregateElement may fail)
define <4 x half> @minmax_bitcast_v4f16_maximumnum(<4 x half> %x) {
; CHECK-LABEL: @minmax_bitcast_v4f16_maximumnum(
-; CHECK-NEXT: [[RESULT:%.*]] = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> [[X:%.*]], <4 x half> <half 0xH3C00, half 0xH3F00, half 0xH3F80, half 0xH4000>)
+; CHECK-NEXT: [[RESULT:%.*]] = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> [[X:%.*]], <4 x half> <half 1.000000e+00, half 1.750000e+00, half 1.875000e+00, half 2.000000e+00>)
; CHECK-NEXT: ret <4 x half> [[RESULT]]
;
%result = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> %x, <4 x half> bitcast (<4 x i16> <i16 15360, i16 16128, i16 16256, i16 16384> to <4 x half>))
diff --git a/llvm/test/Transforms/InstSimplify/fold-bfloat-half-bitcasts.ll b/llvm/test/Transforms/InstSimplify/fold-bfloat-half-bitcasts.ll
index 8567f23a5fed0..c989624cb6d62 100644
--- a/llvm/test/Transforms/InstSimplify/fold-bfloat-half-bitcasts.ll
+++ b/llvm/test/Transforms/InstSimplify/fold-bfloat-half-bitcasts.ll
@@ -3,7 +3,7 @@
define bfloat @bfloat_to_half() {
; CHECK-LABEL: define bfloat @bfloat_to_half() {
-; CHECK-NEXT: ret bfloat 0xR7C00
+; CHECK-NEXT: ret bfloat 2.658460e+36
;
%val = bitcast half 0xH7C00 to bfloat
ret bfloat %val
@@ -11,7 +11,7 @@ define bfloat @bfloat_to_half() {
define <2 x bfloat> @bfloat_to_half_vec() {
; CHECK-LABEL: define <2 x bfloat> @bfloat_to_half_vec() {
-; CHECK-NEXT: ret <2 x bfloat> splat (bfloat 0xR7C00)
+; CHECK-NEXT: ret <2 x bfloat> splat (bfloat 2.658460e+36)
;
%val = bitcast <2 x half> splat (half 0xH7C00) to <2 x bfloat>
ret <2 x bfloat> %val
@@ -19,7 +19,7 @@ define <2 x bfloat> @bfloat_to_half_vec() {
define half @half_to_bfloat() {
; CHECK-LABEL: define half @half_to_bfloat() {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%val = bitcast bfloat 0xR7C00 to half
ret half %val
@@ -27,7 +27,7 @@ define half @half_to_bfloat() {
define <2 x half> @half_to_bfloat_vec() {
; CHECK-LABEL: define <2 x half> @half_to_bfloat_vec() {
-; CHECK-NEXT: ret <2 x half> splat (half 0xH7C00)
+; CHECK-NEXT: ret <2 x half> splat (half +inf)
;
%val = bitcast <2 x bfloat> splat (bfloat 0xR7C00) to <2 x half>
ret <2 x half> %val
@@ -35,7 +35,7 @@ define <2 x half> @half_to_bfloat_vec() {
define half @recursive() {
; CHECK-LABEL: define half @recursive() {
-; CHECK-NEXT: ret half 0xH7C00
+; CHECK-NEXT: ret half +inf
;
%first = bitcast bfloat 0xR7C00 to half
%second = bitcast half %first to bfloat
diff --git a/llvm/test/Transforms/InstSimplify/fp-nan.ll b/llvm/test/Transforms/InstSimplify/fp-nan.ll
index fe3a8c68674c5..ff80a984c6bfa 100644
--- a/llvm/test/Transforms/InstSimplify/fp-nan.ll
+++ b/llvm/test/Transforms/InstSimplify/fp-nan.ll
@@ -5,7 +5,7 @@
define double @fadd_nan_op0(double %x) {
; CHECK-LABEL: @fadd_nan_op0(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fadd double 0x7FF8000000000000, %x
ret double %r
@@ -15,7 +15,7 @@ define double @fadd_nan_op0(double %x) {
define double @fadd_nan_op1(double %x) {
; CHECK-LABEL: @fadd_nan_op1(
-; CHECK-NEXT: ret double 0xFFF8000000000000
+; CHECK-NEXT: ret double -qnan
;
%r = fadd double %x, 0xFFF8000000000000
ret double %r
@@ -25,7 +25,7 @@ define double @fadd_nan_op1(double %x) {
define float @fsub_nan_op0(float %x) {
; CHECK-LABEL: @fsub_nan_op0(
-; CHECK-NEXT: ret float 0x7FFFFF0000000000
+; CHECK-NEXT: ret float +nan(0x3FF800)
;
%r = fsub float 0x7FFFFF0000000000, %x
ret float %r
@@ -35,7 +35,7 @@ define float @fsub_nan_op0(float %x) {
define float @fsub_nan_op1(float %x) {
; CHECK-LABEL: @fsub_nan_op1(
-; CHECK-NEXT: ret float 0x7FF9000000000000
+; CHECK-NEXT: ret float +nan(0x80000)
;
%r = fsub float %x, 0x7FF1000000000000
ret float %r
@@ -43,7 +43,7 @@ define float @fsub_nan_op1(float %x) {
define <2 x float> @fsub_nan_op1_vec(<2 x float> %x) {
; CHECK-LABEL: @fsub_nan_op1_vec(
-; CHECK-NEXT: ret <2 x float> <float 0x7FF9000000000000, float 0xFFF9000000000000>
+; CHECK-NEXT: ret <2 x float> <float +nan(0x80000), float -nan(0x80000)>
;
%r = fsub <2 x float> %x, <float 0x7FF1000000000000, float 0xFFF1000000000000>
ret <2 x float> %r
@@ -51,7 +51,7 @@ define <2 x float> @fsub_nan_op1_vec(<2 x float> %x) {
define <vscale x 1 x float> @fsub_nan_op1_scalable_vec_0(<vscale x 1 x float> %x) {
; CHECK-LABEL: @fsub_nan_op1_scalable_vec_0(
-; CHECK-NEXT: ret <vscale x 1 x float> splat (float 0x7FF9000000000000)
+; CHECK-NEXT: ret <vscale x 1 x float> splat (float +nan(0x80000))
;
%r = fsub <vscale x 1 x float> %x, splat (float 0x7FF1000000000000)
ret <vscale x 1 x float> %r
@@ -59,7 +59,7 @@ define <vscale x 1 x float> @fsub_nan_op1_scalable_vec_0(<vscale x 1 x float> %x
define <vscale x 1 x float> @fsub_nan_op1_scalable_vec_1(<vscale x 1 x float> %x) {
; CHECK-LABEL: @fsub_nan_op1_scalable_vec_1(
-; CHECK-NEXT: ret <vscale x 1 x float> splat (float 0xFFF9000000000000)
+; CHECK-NEXT: ret <vscale x 1 x float> splat (float -nan(0x80000))
;
%r = fsub <vscale x 1 x float> %x, splat (float 0xFFF1000000000000)
ret <vscale x 1 x float> %r
@@ -69,7 +69,7 @@ define <vscale x 1 x float> @fsub_nan_op1_scalable_vec_1(<vscale x 1 x float> %x
define double @fmul_nan_op0(double %x) {
; CHECK-LABEL: @fmul_nan_op0(
-; CHECK-NEXT: ret double 0xFFF8000000000001
+; CHECK-NEXT: ret double -nan(0x1)
;
%r = fmul double 0xFFF0000000000001, %x
ret double %r
@@ -77,7 +77,7 @@ define double @fmul_nan_op0(double %x) {
define <2 x double> @fmul_nan_op0_vec(<2 x double> %x) {
; CHECK-LABEL: @fmul_nan_op0_vec(
-; CHECK-NEXT: ret <2 x double> <double 0xFFF8000000000001, double 0xFFF8DEADDEADDEAD>
+; CHECK-NEXT: ret <2 x double> <double -nan(0x1), double -nan(0xDEADDEADDEAD)>
;
%r = fmul <2 x double> <double 0xFFF0000000000001, double 0xFFF0DEADDEADDEAD>, %x
ret <2 x double> %r
@@ -85,7 +85,7 @@ define <2 x double> @fmul_nan_op0_vec(<2 x double> %x) {
define <vscale x 1 x double> @fmul_nan_op0_scalable_vec_0(<vscale x 1 x double> %x) {
; CHECK-LABEL: @fmul_nan_op0_scalable_vec_0(
-; CHECK-NEXT: ret <vscale x 1 x double> splat (double 0xFFF8000000000001)
+; CHECK-NEXT: ret <vscale x 1 x double> splat (double -nan(0x1))
;
%r = fmul <vscale x 1 x double> splat (double 0xFFF0000000000001), %x
ret <vscale x 1 x double> %r
@@ -93,7 +93,7 @@ define <vscale x 1 x double> @fmul_nan_op0_scalable_vec_0(<vscale x 1 x double>
define <vscale x 1 x double> @fmul_nan_op0_scalable_vec_1(<vscale x 1 x double> %x) {
; CHECK-LABEL: @fmul_nan_op0_scalable_vec_1(
-; CHECK-NEXT: ret <vscale x 1 x double> splat (double 0xFFF8DEADDEADDEAD)
+; CHECK-NEXT: ret <vscale x 1 x double> splat (double -nan(0xDEADDEADDEAD))
;
%r = fmul <vscale x 1 x double> splat (double 0xFFF0DEADDEADDEAD), %x
ret <vscale x 1 x double> %r
@@ -103,7 +103,7 @@ define <vscale x 1 x double> @fmul_nan_op0_scalable_vec_1(<vscale x 1 x double>
define <2 x float> @fmul_nan_op1(<2 x float> %x) {
; CHECK-LABEL: @fmul_nan_op1(
-; CHECK-NEXT: ret <2 x float> splat (float 0x7FF8000000000000)
+; CHECK-NEXT: ret <2 x float> splat (float +qnan)
;
%r = fmul <2 x float> %x, <float 0x7FF8000000000000, float 0x7FF8000000000000>
ret <2 x float> %r
@@ -111,7 +111,7 @@ define <2 x float> @fmul_nan_op1(<2 x float> %x) {
define <vscale x 1 x double> @fmul_nan_op1_scalable_vec(<vscale x 1 x double> %x) {
; CHECK-LABEL: @fmul_nan_op1_scalable_vec(
-; CHECK-NEXT: ret <vscale x 1 x double> splat (double 0x7FF8000000000000)
+; CHECK-NEXT: ret <vscale x 1 x double> splat (double +qnan)
;
%r = fmul <vscale x 1 x double> %x, splat (double 0x7FF8000000000000)
ret <vscale x 1 x double> %r
@@ -121,7 +121,7 @@ define <vscale x 1 x double> @fmul_nan_op1_scalable_vec(<vscale x 1 x double> %x
define <2 x double> @fdiv_nan_op0(<2 x double> %x) {
; CHECK-LABEL: @fdiv_nan_op0(
-; CHECK-NEXT: ret <2 x double> splat (double 0xFFF800000000000F)
+; CHECK-NEXT: ret <2 x double> splat (double -nan(0xF))
;
%r = fdiv <2 x double> <double 0xFFF800000000000F, double 0xFFF800000000000F>, %x
ret <2 x double> %r
@@ -129,7 +129,7 @@ define <2 x double> @fdiv_nan_op0(<2 x double> %x) {
define <vscale x 1 x double> @fdivl_nan_op0_scalable_vec(<vscale x 1 x double> %x) {
; CHECK-LABEL: @fdivl_nan_op0_scalable_vec(
-; CHECK-NEXT: ret <vscale x 1 x double> splat (double 0xFFF800000000000F)
+; CHECK-NEXT: ret <vscale x 1 x double> splat (double -nan(0xF))
;
%r = fdiv <vscale x 1 x double> splat (double 0xFFF800000000000F), %x
ret <vscale x 1 x double> %r
@@ -139,7 +139,7 @@ define <vscale x 1 x double> @fdivl_nan_op0_scalable_vec(<vscale x 1 x double> %
define <2 x half> @fdiv_nan_op1(<2 x half> %x) {
; CHECK-LABEL: @fdiv_nan_op1(
-; CHECK-NEXT: ret <2 x half> <half 0xH7FFF, half 0xHFF00>
+; CHECK-NEXT: ret <2 x half> <half +nan(0x1FF), half -nan(0x100)>
;
%r = fdiv <2 x half> %x, <half 0xH7FFF, half 0xHFF00>
ret <2 x half> %r
@@ -147,7 +147,7 @@ define <2 x half> @fdiv_nan_op1(<2 x half> %x) {
define <vscale x 1 x half> @fdiv_nan_op1_scalable_vec(<vscale x 1 x half> %x) {
; CHECK-LABEL: @fdiv_nan_op1_scalable_vec(
-; CHECK-NEXT: ret <vscale x 1 x half> splat (half 0xH7FFF)
+; CHECK-NEXT: ret <vscale x 1 x half> splat (half +nan(0x1FF))
;
%r = fdiv <vscale x 1 x half> %x, splat (half 0xH7FFF)
ret <vscale x 1 x half> %r
@@ -157,7 +157,7 @@ define <vscale x 1 x half> @fdiv_nan_op1_scalable_vec(<vscale x 1 x half> %x) {
define <2 x double> @fsub_nan_poison_op1(<2 x double> %x) {
; CHECK-LABEL: @fsub_nan_poison_op1(
-; CHECK-NEXT: ret <2 x double> <double 0xFFFF00000000DEAD, double poison>
+; CHECK-NEXT: ret <2 x double> <double -nan(0x700000000DEAD), double poison>
;
%r = fsub <2 x double> %x, <double 0xFFFF00000000DEAD, double poison>
ret <2 x double> %r
@@ -167,7 +167,7 @@ define <2 x double> @fsub_nan_poison_op1(<2 x double> %x) {
define <2 x double> @frem_nan_poison_op0(<2 x double> %x) {
; CHECK-LABEL: @frem_nan_poison_op0(
-; CHECK-NEXT: ret <2 x double> <double 0xFFFF00000000DEAD, double poison>
+; CHECK-NEXT: ret <2 x double> <double -nan(0x700000000DEAD), double poison>
;
%r = frem <2 x double> <double 0xFFFF00000000DEAD, double poison>, %x
ret <2 x double> %r
@@ -177,7 +177,7 @@ define <2 x double> @frem_nan_poison_op0(<2 x double> %x) {
define <3 x double> @fadd_nan_poison_undef_op1(<3 x double> %x) {
; CHECK-LABEL: @fadd_nan_poison_undef_op1(
-; CHECK-NEXT: [[R:%.*]] = fadd <3 x double> [[X:%.*]], <double 0xFFFF00000000DEAD, double poison, double undef>
+; CHECK-NEXT: [[R:%.*]] = fadd <3 x double> [[X:%.*]], <double -nan(0x700000000DEAD), double poison, double undef>
; CHECK-NEXT: ret <3 x double> [[R]]
;
%r = fadd <3 x double> %x, <double 0xFFFF00000000DEAD, double poison, double undef>
@@ -186,7 +186,7 @@ define <3 x double> @fadd_nan_poison_undef_op1(<3 x double> %x) {
define float @frem_nan_op1(float %x) {
; CHECK-LABEL: @frem_nan_op1(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = frem float %x, 0x7FF8000000000000
ret float %r
@@ -196,7 +196,7 @@ define float @frem_nan_op1(float %x) {
define double @fneg_nan_1(double %x) {
; CHECK-LABEL: @fneg_nan_1(
-; CHECK-NEXT: ret double 0x7FFABCDEF0123456
+; CHECK-NEXT: ret double +nan(0x2BCDEF0123456)
;
%r = fsub double -0.0, 0x7FFABCDEF0123456
ret double %r
@@ -204,7 +204,7 @@ define double @fneg_nan_1(double %x) {
define double @unary_fneg_nan_1(double %x) {
; CHECK-LABEL: @unary_fneg_nan_1(
-; CHECK-NEXT: ret double 0xFFFABCDEF0123456
+; CHECK-NEXT: ret double -nan(0x2BCDEF0123456)
;
%r = fneg double 0x7FFABCDEF0123456
ret double %r
@@ -212,7 +212,7 @@ define double @unary_fneg_nan_1(double %x) {
define <2 x double> @fneg_nan_2(<2 x double> %x) {
; CHECK-LABEL: @fneg_nan_2(
-; CHECK-NEXT: ret <2 x double> <double 0xFFF9234567890ABC, double 0x7FF8000000000001>
+; CHECK-NEXT: ret <2 x double> <double -nan(0x1234567890ABC), double +nan(0x1)>
;
%r = fsub <2 x double> <double -0.0, double -0.0>, <double 0xFFF1234567890ABC, double 0x7FF0000000000001>
ret <2 x double> %r
@@ -220,7 +220,7 @@ define <2 x double> @fneg_nan_2(<2 x double> %x) {
define <vscale x 1 x double> @fneg_nan_2_scalable_vec() {
; CHECK-LABEL: @fneg_nan_2_scalable_vec(
-; CHECK-NEXT: ret <vscale x 1 x double> splat (double 0xFFF9234567890ABC)
+; CHECK-NEXT: ret <vscale x 1 x double> splat (double -nan(0x1234567890ABC))
;
%r = fsub <vscale x 1 x double> splat (double -0.0), splat (double 0xFFF1234567890ABC)
ret <vscale x 1 x double> %r
@@ -228,7 +228,7 @@ define <vscale x 1 x double> @fneg_nan_2_scalable_vec() {
define <2 x double> @unary_fneg_nan_2(<2 x double> %x) {
; CHECK-LABEL: @unary_fneg_nan_2(
-; CHECK-NEXT: ret <2 x double> <double 0x7FF1234567890ABC, double 0xFFF0000000000001>
+; CHECK-NEXT: ret <2 x double> <double +snan(0x1234567890ABC), double -snan(0x1)>
;
%r = fneg <2 x double> <double 0xFFF1234567890ABC, double 0x7FF0000000000001>
ret <2 x double> %r
@@ -237,7 +237,7 @@ define <2 x double> @unary_fneg_nan_2(<2 x double> %x) {
; FIXME: This doesn't behave the same way as the fixed-length vectors above
define <vscale x 1 x double> @unary_fneg_nan_2_scalable_vec_0() {
; CHECK-LABEL: @unary_fneg_nan_2_scalable_vec_0(
-; CHECK-NEXT: ret <vscale x 1 x double> splat (double 0x7FF1234567890ABC)
+; CHECK-NEXT: ret <vscale x 1 x double> splat (double +snan(0x1234567890ABC))
;
%r = fneg <vscale x 1 x double> splat (double 0xFFF1234567890ABC)
ret <vscale x 1 x double> %r
@@ -246,7 +246,7 @@ define <vscale x 1 x double> @unary_fneg_nan_2_scalable_vec_0() {
; FIXME: This doesn't behave the same way as the fixed-length vectors above
define <vscale x 1 x double> @unary_fneg_nan_2_scalable_vec_1() {
; CHECK-LABEL: @unary_fneg_nan_2_scalable_vec_1(
-; CHECK-NEXT: ret <vscale x 1 x double> splat (double 0xFFF0000000000001)
+; CHECK-NEXT: ret <vscale x 1 x double> splat (double -snan(0x1))
;
%r = fneg <vscale x 1 x double> splat (double 0x7FF0000000000001)
ret <vscale x 1 x double> %r
diff --git a/llvm/test/Transforms/InstSimplify/fp-undef-poison-strictfp.ll b/llvm/test/Transforms/InstSimplify/fp-undef-poison-strictfp.ll
index 801fd75a24a71..f45dbb0f661ee 100644
--- a/llvm/test/Transforms/InstSimplify/fp-undef-poison-strictfp.ll
+++ b/llvm/test/Transforms/InstSimplify/fp-undef-poison-strictfp.ll
@@ -36,7 +36,7 @@ define float @fadd_undef_op0_upward(float %x) #0 {
define float @fadd_undef_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @fadd_undef_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fadd.f32(float undef, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -104,7 +104,7 @@ define float @fadd_undef_op1_upward(float %x) #0 {
define float @fadd_undef_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @fadd_undef_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fadd.f32(float %x, float undef, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -176,7 +176,7 @@ define float @fsub_undef_op0_upward(float %x) #0 {
define float @fsub_undef_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @fsub_undef_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fsub.f32(float undef, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -244,7 +244,7 @@ define float @fsub_undef_op1_upward(float %x) #0 {
define float @fsub_undef_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @fsub_undef_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fsub.f32(float %x, float undef, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -316,7 +316,7 @@ define float @fmul_undef_op0_upward(float %x) #0 {
define float @fmul_undef_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @fmul_undef_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fmul.f32(float undef, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -384,7 +384,7 @@ define float @fmul_undef_op1_upward(float %x) #0 {
define float @fmul_undef_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @fmul_undef_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fmul.f32(float %x, float undef, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -456,7 +456,7 @@ define float @fdiv_undef_op0_upward(float %x) #0 {
define float @fdiv_undef_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @fdiv_undef_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float undef, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -524,7 +524,7 @@ define float @fdiv_undef_op1_upward(float %x) #0 {
define float @fdiv_undef_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @fdiv_undef_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fdiv.f32(float %x, float undef, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -596,7 +596,7 @@ define float @frem_undef_op0_upward(float %x) #0 {
define float @frem_undef_op0_defaultfp(float %x) #0 {
; CHECK-LABEL: @frem_undef_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.frem.f32(float undef, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -664,7 +664,7 @@ define float @frem_undef_op1_upward(float %x) #0 {
define float @frem_undef_op1_defaultfp(float %x) #0 {
; CHECK-LABEL: @frem_undef_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.frem.f32(float %x, float undef, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -736,7 +736,7 @@ define float @fma_undef_op0_upward(float %x, float %y) #0 {
define float @fma_undef_op0_defaultfp(float %x, float %y) #0 {
; CHECK-LABEL: @fma_undef_op0_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float undef, float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -804,7 +804,7 @@ define float @fma_undef_op1_upward(float %x, float %y) #0 {
define float @fma_undef_op1_defaultfp(float %x, float %y) #0 {
; CHECK-LABEL: @fma_undef_op1_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float undef, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
@@ -872,7 +872,7 @@ define float @fma_undef_op2_upward(float %x, float %y) #0 {
define float @fma_undef_op2_defaultfp(float %x, float %y) #0 {
; CHECK-LABEL: @fma_undef_op2_defaultfp(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float undef, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret float %r
diff --git a/llvm/test/Transforms/InstSimplify/fp-undef-poison.ll b/llvm/test/Transforms/InstSimplify/fp-undef-poison.ll
index ffab9c94ddf42..9522f642352da 100644
--- a/llvm/test/Transforms/InstSimplify/fp-undef-poison.ll
+++ b/llvm/test/Transforms/InstSimplify/fp-undef-poison.ll
@@ -3,7 +3,7 @@
define float @fadd_undef_op0(float %x) {
; CHECK-LABEL: @fadd_undef_op0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fadd float undef, %x
ret float %r
@@ -19,7 +19,7 @@ define float @fadd_poison_op0(float %x) {
define float @fadd_undef_op1(float %x) {
; CHECK-LABEL: @fadd_undef_op1(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fadd float %x, undef
ret float %r
@@ -35,7 +35,7 @@ define float @fadd_poison_op1(float %x) {
define float @fsub_undef_op0(float %x) {
; CHECK-LABEL: @fsub_undef_op0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fsub float undef, %x
ret float %r
@@ -51,7 +51,7 @@ define float @fsub_poison_op0(float %x) {
define float @fsub_undef_op1(float %x) {
; CHECK-LABEL: @fsub_undef_op1(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fsub float %x, undef
ret float %r
@@ -67,7 +67,7 @@ define float @fsub_poison_op1(float %x) {
define float @fmul_undef_op0(float %x) {
; CHECK-LABEL: @fmul_undef_op0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fmul float undef, %x
ret float %r
@@ -83,7 +83,7 @@ define float @fmul_poison_op0(float %x) {
define float @fmul_undef_op1(float %x) {
; CHECK-LABEL: @fmul_undef_op1(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fmul float %x, undef
ret float %r
@@ -99,7 +99,7 @@ define float @fmul_poison_op1(float %x) {
define float @fdiv_undef_op0(float %x) {
; CHECK-LABEL: @fdiv_undef_op0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fdiv float undef, %x
ret float %r
@@ -115,7 +115,7 @@ define float @fdiv_poison_op0(float %x) {
define float @fdiv_undef_op1(float %x) {
; CHECK-LABEL: @fdiv_undef_op1(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = fdiv float %x, undef
ret float %r
@@ -131,7 +131,7 @@ define float @fdiv_poison_op1(float %x) {
define float @frem_undef_op0(float %x) {
; CHECK-LABEL: @frem_undef_op0(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = frem float undef, %x
ret float %r
@@ -147,7 +147,7 @@ define float @frem_poison_op0(float %x) {
define float @frem_undef_op1(float %x) {
; CHECK-LABEL: @frem_undef_op1(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%r = frem float %x, undef
ret float %r
@@ -245,7 +245,7 @@ define float @frem_undef_op1_fast(float %x) {
define double @fdiv_ninf_nan_op0(double %x) {
; CHECK-LABEL: @fdiv_ninf_nan_op0(
-; CHECK-NEXT: ret double 0xFFF8000000000000
+; CHECK-NEXT: ret double -qnan
;
%r = fdiv ninf double 0xfff8000000000000, %x
ret double %r
@@ -253,7 +253,7 @@ define double @fdiv_ninf_nan_op0(double %x) {
define double @fadd_ninf_nan_op1(double %x) {
; CHECK-LABEL: @fadd_ninf_nan_op1(
-; CHECK-NEXT: ret double 0x7FF8000000000000
+; CHECK-NEXT: ret double +qnan
;
%r = fadd ninf double %x, 0x7ff8000000000000
ret double %r
@@ -277,7 +277,7 @@ define double @fadd_ninf_inf_op1(double %x) {
define double @fsub_nnan_inf_op0(double %x) {
; CHECK-LABEL: @fsub_nnan_inf_op0(
-; CHECK-NEXT: ret double 0x7FF0000000000000
+; CHECK-NEXT: ret double +inf
;
%r = fsub nnan double 0x7ff0000000000000, %x
ret double %r
@@ -287,7 +287,7 @@ define double @fsub_nnan_inf_op0(double %x) {
define double @fmul_nnan_inf_op1(double %x) {
; CHECK-LABEL: @fmul_nnan_inf_op1(
-; CHECK-NEXT: [[R:%.*]] = fmul nnan double [[X:%.*]], 0xFFF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fmul nnan double [[X:%.*]], -inf
; CHECK-NEXT: ret double [[R]]
;
%r = fmul nnan double %x, 0xfff0000000000000
@@ -328,7 +328,7 @@ define <vscale x 2 x float> @sqrt_poison_scalable_vec() {
define float @sqrt_nnan_nan() {
; CHECK-LABEL: @sqrt_nnan_nan(
-; CHECK-NEXT: [[SQRT:%.*]] = call nnan float @llvm.sqrt.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[SQRT:%.*]] = call nnan float @llvm.sqrt.f32(float +qnan)
; CHECK-NEXT: ret float [[SQRT]]
;
%sqrt = call nnan float @llvm.sqrt(float 0x7ff8000000000000)
@@ -337,7 +337,7 @@ define float @sqrt_nnan_nan() {
define float @sqrt_ninf_inf() {
; CHECK-LABEL: @sqrt_ninf_inf(
-; CHECK-NEXT: [[SQRT:%.*]] = call ninf float @llvm.sqrt.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[SQRT:%.*]] = call ninf float @llvm.sqrt.f32(float -inf)
; CHECK-NEXT: ret float [[SQRT]]
;
%sqrt = call ninf float @llvm.sqrt(float 0xfff0000000000000)
diff --git a/llvm/test/Transforms/InstSimplify/known-never-infinity.ll b/llvm/test/Transforms/InstSimplify/known-never-infinity.ll
index 23fda1b3044e8..d58edb4c91a75 100644
--- a/llvm/test/Transforms/InstSimplify/known-never-infinity.ll
+++ b/llvm/test/Transforms/InstSimplify/known-never-infinity.ll
@@ -20,7 +20,7 @@ define i1 @isNotKnownNeverInfinity_uitofp(i16 %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_uitofp
; CHECK-SAME: (i16 [[X:%.*]]) {
; CHECK-NEXT: [[F:%.*]] = uitofp i16 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fcmp une half [[F]], 0xH7C00
+; CHECK-NEXT: [[R:%.*]] = fcmp une half [[F]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%f = uitofp i16 %x to half
@@ -69,7 +69,7 @@ define i1 @isNotKnownNeverInfinity_sitofp(i17 %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_sitofp
; CHECK-SAME: (i17 [[X:%.*]]) {
; CHECK-NEXT: [[F:%.*]] = sitofp i17 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fcmp une half [[F]], 0xH7C00
+; CHECK-NEXT: [[R:%.*]] = fcmp une half [[F]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%f = sitofp i17 %x to half
@@ -93,7 +93,7 @@ define i1 @isNotKnownNeverNegativeInfinity_sitofp(i17 %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverNegativeInfinity_sitofp
; CHECK-SAME: (i17 [[X:%.*]]) {
; CHECK-NEXT: [[F:%.*]] = sitofp i17 [[X]] to half
-; CHECK-NEXT: [[R:%.*]] = fcmp oeq half [[F]], 0xHFC00
+; CHECK-NEXT: [[R:%.*]] = fcmp oeq half [[F]], -inf
; CHECK-NEXT: ret i1 [[R]]
;
%f = sitofp i17 %x to half
@@ -128,7 +128,7 @@ define i1 @isKnownNeverInfinity_fptrunc(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[E:%.*]] = fptrunc double [[A]] to float
-; CHECK-NEXT: [[R:%.*]] = fcmp une float [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une float [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf double %x, 1.0
@@ -141,7 +141,7 @@ define i1 @isNotKnownNeverInfinity_fptrunc(double %unknown) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_fptrunc
; CHECK-SAME: (double [[UNKNOWN:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = fptrunc double [[UNKNOWN]] to float
-; CHECK-NEXT: [[R:%.*]] = fcmp une float [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une float [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = fptrunc double %unknown to float
@@ -164,7 +164,7 @@ define i1 @isNotKnownNeverInfinity_canonicalize(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_canonicalize
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.canonicalize.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.canonicalize.f64(double %x)
@@ -187,7 +187,7 @@ define i1 @isNotKnownNeverInfinity_fabs(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_fabs
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.fabs.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.fabs.f64(double %x)
@@ -210,7 +210,7 @@ define i1 @isNotKnownNeverInfinity_fneg(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_fneg
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = fneg double [[X]]
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = fneg double %x
@@ -233,7 +233,7 @@ define i1 @isNotKnownNeverInfinity_copysign(double %x, double %sign) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_copysign
; CHECK-SAME: (double [[X:%.*]], double [[SIGN:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.copysign.f64(double [[X]], double [[SIGN]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.copysign.f64(double %x, double %sign)
@@ -256,7 +256,7 @@ define i1 @isNotKnownNeverInfinity_arithmetic_fence(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_arithmetic_fence
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.arithmetic.fence.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.arithmetic.fence.f64(double %x)
@@ -279,7 +279,7 @@ define i1 @isNotKnownNeverInfinity_floor(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_floor
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.floor.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.floor.f64(double %x)
@@ -302,7 +302,7 @@ define i1 @isNotKnownNeverInfinity_ceil(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_ceil
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.ceil.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.ceil.f64(double %x)
@@ -325,7 +325,7 @@ define i1 @isNotKnownNeverInfinity_trunc(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_trunc
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.trunc.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.trunc.f64(double %x)
@@ -348,7 +348,7 @@ define i1 @isNotKnownNeverInfinity_rint(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_rint
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.rint.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.rint.f64(double %x)
@@ -371,7 +371,7 @@ define i1 @isNotKnownNeverInfinity_nearbyint(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_nearbyint
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.nearbyint.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.nearbyint.f64(double %x)
@@ -394,7 +394,7 @@ define i1 @isNotKnownNeverInfinity_round(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_round
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.round.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.round.f64(double %x)
@@ -417,7 +417,7 @@ define i1 @isNotKnownNeverInfinity_roundeven(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_roundeven
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.roundeven.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.roundeven.f64(double %x)
@@ -430,7 +430,7 @@ define i1 @isNotKnownNeverInfinity_fptrunc_round(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[E:%.*]] = call float @llvm.fptrunc.round.f32.f64(double [[A]], metadata !"round.downward")
-; CHECK-NEXT: [[R:%.*]] = fcmp une float [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une float [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf double %x, 1.0
@@ -444,7 +444,7 @@ define i1 @isKnownNeverInfinity_floor_ppcf128(ppc_fp128 %x) {
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf ppc_fp128 [[X]], [[X]]
; CHECK-NEXT: [[E:%.*]] = call ppc_fp128 @llvm.floor.ppcf128(ppc_fp128 [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], 0xM7FF00000000000000000000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf ppc_fp128 %x, %x
@@ -458,7 +458,7 @@ define i1 @isKnownNeverInfinity_ceil_ppcf128(ppc_fp128 %x) {
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf ppc_fp128 [[X]], [[X]]
; CHECK-NEXT: [[E:%.*]] = call ppc_fp128 @llvm.ceil.ppcf128(ppc_fp128 [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], 0xM7FF00000000000000000000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf ppc_fp128 %x, %x
@@ -472,7 +472,7 @@ define i1 @isKnownNeverInfinity_rint_ppcf128(ppc_fp128 %x) {
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf ppc_fp128 [[X]], [[X]]
; CHECK-NEXT: [[E:%.*]] = call ppc_fp128 @llvm.rint.ppcf128(ppc_fp128 [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], 0xM7FF00000000000000000000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf ppc_fp128 %x, %x
@@ -486,7 +486,7 @@ define i1 @isKnownNeverInfinity_nearbyint_ppcf128(ppc_fp128 %x) {
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf ppc_fp128 [[X]], [[X]]
; CHECK-NEXT: [[E:%.*]] = call ppc_fp128 @llvm.nearbyint.ppcf128(ppc_fp128 [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], 0xM7FF00000000000000000000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf ppc_fp128 %x, %x
@@ -500,7 +500,7 @@ define i1 @isKnownNeverInfinity_round_ppcf128(ppc_fp128 %x) {
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf ppc_fp128 [[X]], [[X]]
; CHECK-NEXT: [[E:%.*]] = call ppc_fp128 @llvm.round.ppcf128(ppc_fp128 [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], 0xM7FF00000000000000000000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf ppc_fp128 %x, %x
@@ -514,7 +514,7 @@ define i1 @isKnownNeverInfinity_roundeven_ppcf128(ppc_fp128 %x) {
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf ppc_fp128 [[X]], [[X]]
; CHECK-NEXT: [[E:%.*]] = call ppc_fp128 @llvm.roundeven.ppcf128(ppc_fp128 [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], 0xM7FF00000000000000000000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une ppc_fp128 [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf ppc_fp128 %x, %x
@@ -562,7 +562,7 @@ define i1 @isNotKnownNeverInfinity_minnum_lhs(double %x, double %y) {
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[NINF_Y:%.*]] = fadd ninf double [[Y]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.minnum.f64(double [[X]], double [[NINF_Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.y = fadd ninf double %y, 1.0
@@ -576,7 +576,7 @@ define i1 @isNotKnownNeverInfinity_minnum_rhs(double %x, double %y) {
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.minnum.f64(double [[NINF_X]], double [[Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd ninf double %x, 1.0
@@ -602,7 +602,7 @@ define i1 @isNotKnownNeverInfinity_maxnum_lhs(double %x, double %y) {
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[NINF_Y:%.*]] = fadd ninf double [[Y]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.maxnum.f64(double [[X]], double [[NINF_Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.y = fadd ninf double %y, 1.0
@@ -616,7 +616,7 @@ define i1 @isNotKnownNeverInfinity_maxnum_rhs(double %x, double %y) {
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.maxnum.f64(double [[NINF_X]], double [[Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd ninf double %x, 1.0
@@ -642,7 +642,7 @@ define i1 @isNotKnownNeverInfinity_minimum_lhs(double %x, double %y) {
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[NINF_Y:%.*]] = fadd ninf double [[Y]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.minimum.f64(double [[X]], double [[NINF_Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.y = fadd ninf double %y, 1.0
@@ -656,7 +656,7 @@ define i1 @isNotKnownNeverInfinity_minimum_rhs(double %x, double %y) {
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.minimum.f64(double [[NINF_X]], double [[Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd ninf double %x, 1.0
@@ -682,7 +682,7 @@ define i1 @isNotKnownNeverInfinity_maximum_lhs(double %x, double %y) {
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[NINF_Y:%.*]] = fadd ninf double [[Y]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.maximum.f64(double [[X]], double [[NINF_Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.y = fadd ninf double %y, 1.0
@@ -696,7 +696,7 @@ define i1 @isNotKnownNeverInfinity_maximum_rhs(double %x, double %y) {
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.maximum.f64(double [[NINF_X]], double [[Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd ninf double %x, 1.0
@@ -720,7 +720,7 @@ define i1 @isNotKnownNeverInfinity_sqrt(double %x) {
; CHECK-LABEL: define i1 @isNotKnownNeverInfinity_sqrt
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[E:%.*]] = call double @llvm.sqrt.f64(double [[X]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%e = call double @llvm.sqrt.f64(double %x)
@@ -757,7 +757,7 @@ define i1 @isNotKnownNeverInfinity_log_maybe_inf(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[X_CLAMP_ZERO:%.*]] = call double @llvm.maxnum.f64(double [[X]], double 0.000000e+00)
; CHECK-NEXT: [[E:%.*]] = call double @llvm.log.f64(double [[X_CLAMP_ZERO]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%x.clamp.zero = call double @llvm.maxnum.f64(double %x, double 0.0)
@@ -771,7 +771,7 @@ define i1 @isKnownNeverNegInfinity_log_maybe_0(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = call ninf double @llvm.sqrt.f64(double [[X]])
; CHECK-NEXT: [[E:%.*]] = call double @llvm.log.f64(double [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0xFFF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], -inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = call ninf double @llvm.sqrt.f64(double %x) ; could be 0.0
@@ -809,7 +809,7 @@ define i1 @isNotKnownNeverInfinity_log10_maybe_inf(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[X_CLAMP_ZERO:%.*]] = call double @llvm.maxnum.f64(double [[X]], double 0.000000e+00)
; CHECK-NEXT: [[E:%.*]] = call double @llvm.log10.f64(double [[X_CLAMP_ZERO]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%x.clamp.zero = call double @llvm.maxnum.f64(double %x, double 0.0)
@@ -823,7 +823,7 @@ define i1 @isKnownNeverNegInfinity_log10_maybe_0(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = call ninf double @llvm.sqrt.f64(double [[X]])
; CHECK-NEXT: [[E:%.*]] = call double @llvm.log10.f64(double [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0xFFF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], -inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = call ninf double @llvm.sqrt.f64(double %x) ; could be 0.0
@@ -861,7 +861,7 @@ define i1 @isNotKnownNeverInfinity_log2_maybe_inf(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[X_CLAMP_ZERO:%.*]] = call double @llvm.maxnum.f64(double [[X]], double 0.000000e+00)
; CHECK-NEXT: [[E:%.*]] = call double @llvm.log2.f64(double [[X_CLAMP_ZERO]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%x.clamp.zero = call double @llvm.maxnum.f64(double %x, double 0.0)
@@ -875,7 +875,7 @@ define i1 @isKnownNeverNegInfinity_log2_maybe_0(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = call ninf double @llvm.sqrt.f64(double [[X]])
; CHECK-NEXT: [[E:%.*]] = call double @llvm.log2.f64(double [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0xFFF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], -inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = call ninf double @llvm.sqrt.f64(double %x) ; could be 0.0
@@ -890,7 +890,7 @@ define i1 @isNotKnownNeverInfinity_pow(double %x, double %y) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[NINF_Y:%.*]] = fadd ninf double [[Y]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.pow.f64(double [[NINF_X]], double [[NINF_Y]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd ninf double %x, 1.0
@@ -905,7 +905,7 @@ define i1 @isNotKnownNeverInfinity_powi(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.powi.f64.i32(double [[NINF_X]], i32 2)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd ninf double %x, 1.0
@@ -919,7 +919,7 @@ define i1 @isNotKnownNeverInfinity_exp(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[E:%.*]] = call double @llvm.exp.f64(double [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf double %x, 1.0
@@ -933,7 +933,7 @@ define i1 @isNotKnownNeverInfinity_exp2(double %x) {
; CHECK-SAME: (double [[X:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = fadd ninf double [[X]], 1.000000e+00
; CHECK-NEXT: [[E:%.*]] = call double @llvm.exp2.f64(double [[A]])
-; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], 0x7FF0000000000000
+; CHECK-NEXT: [[R:%.*]] = fcmp une double [[E]], +inf
; CHECK-NEXT: ret i1 [[R]]
;
%a = fadd ninf double %x, 1.0
@@ -949,7 +949,7 @@ define i1 @isNotKnownNeverInfinity_fma(double %x, double %y, double %z) {
; CHECK-NEXT: [[NINF_Y:%.*]] = fadd ninf double [[Y]], 1.000000e+00
; CHECK-NEXT: [[NINF_Z:%.*]] = fadd ninf double [[Z]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.fma.f64(double [[NINF_X]], double [[NINF_Y]], double [[NINF_Z]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd ninf double %x, 1.0
@@ -967,7 +967,7 @@ define i1 @isNotKnownNeverInfinity_fmuladd(double %x, double %y, double %z) {
; CHECK-NEXT: [[NINF_Y:%.*]] = fadd ninf double [[Y]], 1.000000e+00
; CHECK-NEXT: [[NINF_Z:%.*]] = fadd ninf double [[Z]], 1.000000e+00
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.fmuladd.f64(double [[NINF_X]], double [[NINF_Y]], double [[NINF_Z]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd ninf double %x, 1.0
@@ -982,9 +982,9 @@ define i1 @not_inf_fabs_select_pzero_or_ninf(i1 %cond) {
; CHECK-LABEL: define i1 @not_inf_fabs_select_pzero_or_ninf
; CHECK-SAME: (i1 [[COND:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float 0.000000e+00, float 0xFFF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float 0.000000e+00, float -inf
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
-; CHECK-NEXT: [[ONE:%.*]] = fcmp one float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[ONE:%.*]] = fcmp one float [[FABS]], +inf
; CHECK-NEXT: ret i1 [[ONE]]
;
entry:
@@ -998,9 +998,9 @@ define i1 @not_inf_fabs_select_nzero_or_pinf(i1 %cond) {
; CHECK-LABEL: define i1 @not_inf_fabs_select_nzero_or_pinf
; CHECK-SAME: (i1 [[COND:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float -0.000000e+00, float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float -0.000000e+00, float +inf
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
-; CHECK-NEXT: [[ONE:%.*]] = fcmp one float [[FABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[ONE:%.*]] = fcmp one float [[FABS]], +inf
; CHECK-NEXT: ret i1 [[ONE]]
;
entry:
@@ -1027,10 +1027,10 @@ define i1 @not_ninf_fneg_fabs_select_nzero_or_pinf(i1 %cond) {
; CHECK-LABEL: define i1 @not_ninf_fneg_fabs_select_nzero_or_pinf
; CHECK-SAME: (i1 [[COND:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float -0.000000e+00, float 0x7FF0000000000000
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float -0.000000e+00, float +inf
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
; CHECK-NEXT: [[FNEG_FABS:%.*]] = fneg float [[FABS]]
-; CHECK-NEXT: [[ONE:%.*]] = fcmp one float [[FNEG_FABS]], 0xFFF0000000000000
+; CHECK-NEXT: [[ONE:%.*]] = fcmp one float [[FNEG_FABS]], -inf
; CHECK-NEXT: ret i1 [[ONE]]
;
entry:
@@ -1103,7 +1103,7 @@ define i1 @isKnownNeverInfinity_vector_reduce_maximum_fail(<4 x double> %x) {
; CHECK-SAME: (<4 x double> [[X:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd <4 x double> [[X]], splat (double 1.000000e+00)
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> [[NINF_X]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd <4 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0>
@@ -1128,7 +1128,7 @@ define i1 @isKnownNeverInfinity_vector_reduce_minimum_fail(<4 x double> %x) {
; CHECK-SAME: (<4 x double> [[X:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd <4 x double> [[X]], splat (double 1.000000e+00)
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> [[NINF_X]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd <4 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0>
@@ -1153,7 +1153,7 @@ define i1 @isKnownNeverInfinity_vector_reduce_fmax_fail(<4 x double> %x) {
; CHECK-SAME: (<4 x double> [[X:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd <4 x double> [[X]], splat (double 1.000000e+00)
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> [[NINF_X]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd <4 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0>
@@ -1178,7 +1178,7 @@ define i1 @isKnownNeverInfinity_vector_reduce_fmin_fail(<4 x double> %x) {
; CHECK-SAME: (<4 x double> [[X:%.*]]) {
; CHECK-NEXT: [[NINF_X:%.*]] = fadd <4 x double> [[X]], splat (double 1.000000e+00)
; CHECK-NEXT: [[OP:%.*]] = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> [[NINF_X]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], 0x7FF0000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[OP]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%ninf.x = fadd <4 x double> %x, <double 1.0, double 1.0, double 1.0, double 1.0>
diff --git a/llvm/test/Transforms/InstSimplify/known-never-nan.ll b/llvm/test/Transforms/InstSimplify/known-never-nan.ll
index bafbeed68d566..8d18e5e994391 100644
--- a/llvm/test/Transforms/InstSimplify/known-never-nan.ll
+++ b/llvm/test/Transforms/InstSimplify/known-never-nan.ll
@@ -575,7 +575,7 @@ define i1 @isKnownNeverNaN_atan2_nonan(double nofpclass(nan) %x, double nofpclas
define i1 @issue63316(i64 %arg) {
; CHECK-LABEL: @issue63316(
; CHECK-NEXT: [[SITOFP:%.*]] = sitofp i64 [[ARG:%.*]] to float
-; CHECK-NEXT: [[FMUL:%.*]] = fmul float [[SITOFP]], 0x7FF0000000000000
+; CHECK-NEXT: [[FMUL:%.*]] = fmul float [[SITOFP]], +inf
; CHECK-NEXT: [[FCMP:%.*]] = fcmp uno float [[FMUL]], 0.000000e+00
; CHECK-NEXT: ret i1 [[FCMP]]
;
@@ -588,7 +588,7 @@ define i1 @issue63316(i64 %arg) {
define i1 @issue63316_commute(i64 %arg) {
; CHECK-LABEL: @issue63316_commute(
; CHECK-NEXT: [[SITOFP:%.*]] = sitofp i64 [[ARG:%.*]] to float
-; CHECK-NEXT: [[FMUL:%.*]] = fmul float 0x7FF0000000000000, [[SITOFP]]
+; CHECK-NEXT: [[FMUL:%.*]] = fmul float +inf, [[SITOFP]]
; CHECK-NEXT: [[FCMP:%.*]] = fcmp uno float [[FMUL]], 0.000000e+00
; CHECK-NEXT: ret i1 [[FCMP]]
;
diff --git a/llvm/test/Transforms/InstSimplify/ldexp.ll b/llvm/test/Transforms/InstSimplify/ldexp.ll
index d39f6a1e49673..e2a5ad2eb9fbf 100644
--- a/llvm/test/Transforms/InstSimplify/ldexp.ll
+++ b/llvm/test/Transforms/InstSimplify/ldexp.ll
@@ -3,7 +3,7 @@
define float @ldexp_f32_undef_undef() {
; CHECK-LABEL: @ldexp_f32_undef_undef(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%call = call float @llvm.ldexp.f32.i32(float undef, i32 undef)
ret float %call
@@ -78,7 +78,7 @@ define void @ldexp_f32_val0(i32 %y) {
; CHECK-LABEL: @ldexp_f32_val0(
; CHECK-NEXT: store volatile float 0.000000e+00, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float -0.000000e+00, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x7FF8000000000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +qnan, ptr addrspace(1) undef, align 4
; CHECK-NEXT: ret void
;
%zero = call float @llvm.ldexp.f32.i32(float 0.0, i32 %y)
@@ -94,10 +94,10 @@ define void @ldexp_f32_val0(i32 %y) {
define void @ldexp_f32_val_infinity(i32 %y) {
; CHECK-LABEL: @ldexp_f32_val_infinity(
-; CHECK-NEXT: store volatile float 0x7FF0000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0xFFF0000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x7FF0000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0xFFF0000000000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +inf, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float -inf, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +inf, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float -inf, ptr addrspace(1) undef, align 4
; CHECK-NEXT: ret void
;
%inf = call float @llvm.ldexp.f32.i32(float 0x7ff0000000000000, i32 %y)
@@ -119,10 +119,10 @@ define void @ldexp_f32_val_infinity(i32 %y) {
; Technically this depends on the ieee_mode in the mode register.
define void @ldexp_f32_val_nan(i32 %y) {
; CHECK-LABEL: @ldexp_f32_val_nan(
-; CHECK-NEXT: store volatile float 0x7FF8001000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0xFFF8000100000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x7FF8000020000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0xFFFFFFFFE0000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +nan(0x80), ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float -nan(0x8), ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +nan(0x1), ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float -nan(0x3FFFFF), ptr addrspace(1) undef, align 4
; CHECK-NEXT: ret void
;
%plus.qnan = call float @llvm.ldexp.f32.i32(float 0x7ff0001000000000, i32 %y)
@@ -142,15 +142,15 @@ define void @ldexp_f32_val_nan(i32 %y) {
define void @ldexp_f32_val_nan_strictfp_maytrap(i32 %y) #0 {
; CHECK-LABEL: @ldexp_f32_val_nan_strictfp_maytrap(
-; CHECK-NEXT: [[PLUS_QNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x7FF0001000000000, i32 [[Y:%.*]], metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0:[0-9]+]]
+; CHECK-NEXT: [[PLUS_QNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float +snan(0x80), i32 [[Y:%.*]], metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0:[0-9]+]]
; CHECK-NEXT: store volatile float [[PLUS_QNAN]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[NEG_QNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0xFFF0000100000000, i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
+; CHECK-NEXT: [[NEG_QNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float -snan(0x8), i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[NEG_QNAN]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[PLUS_SNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x7FF0000020000000, i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
+; CHECK-NEXT: [[PLUS_SNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float +snan(0x1), i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[PLUS_SNAN]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[NEG_SNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0xFFF7FFFFE0000000, i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
+; CHECK-NEXT: [[NEG_SNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float -snan(0x3FFFFF), i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[NEG_SNAN]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x7FF8000000000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +qnan, ptr addrspace(1) undef, align 4
; CHECK-NEXT: ret void
;
%plus.qnan = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x7ff0001000000000, i32 %y, metadata !"round.dynamic", metadata !"fpexcept.maytrap") #0
@@ -174,16 +174,16 @@ define void @ldexp_f32_val_nan_strictfp_maytrap(i32 %y) #0 {
define void @ldexp_f32_val_nan_strictfp_strict(i32 %y) #0 {
; CHECK-LABEL: @ldexp_f32_val_nan_strictfp_strict(
-; CHECK-NEXT: [[PLUS_QNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x7FF0001000000000, i32 [[Y:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[PLUS_QNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float +snan(0x80), i32 [[Y:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[PLUS_QNAN]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[NEG_QNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0xFFF0000100000000, i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[NEG_QNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float -snan(0x8), i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[NEG_QNAN]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[PLUS_SNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x7FF0000020000000, i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[PLUS_SNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float +snan(0x1), i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[PLUS_SNAN]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[NEG_SNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0xFFF7FFFFE0000000, i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[NEG_SNAN:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float -snan(0x3FFFFF), i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[NEG_SNAN]], ptr addrspace(1) undef, align 4
; CHECK-NEXT: [[UNDEF:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float undef, i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: store volatile float 0x7FF8000000000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +qnan, ptr addrspace(1) undef, align 4
; CHECK-NEXT: ret void
;
%plus.qnan = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x7ff0001000000000, i32 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
@@ -244,7 +244,7 @@ define void @ldexp_f32_undef_strictfp(float %x, i32 %y) #0 {
; CHECK-NEXT: [[UNDEF_EXP:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float [[X:%.*]], i32 undef, metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[UNDEF_EXP]], ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float [[X]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x7FF8000000000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +qnan, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float poison, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float poison, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float undef, ptr addrspace(1) undef, align 4
@@ -275,9 +275,9 @@ define void @ldexp_f32_0_strictfp(float %x) #0 {
; CHECK-NEXT: store volatile float [[UNKNOWN_ZERO]], ptr addrspace(1) undef, align 4
; CHECK-NEXT: [[UNKNOWN_UNDEF:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float [[X]], i32 undef, metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[UNKNOWN_UNDEF]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[DENORMAL_0:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x380FFFFFC0000000, i32 0, metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
+; CHECK-NEXT: [[DENORMAL_0:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float f0x007FFFFF, i32 0, metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[DENORMAL_0]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[DENORMAL_1:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x380FFFFFC0000000, i32 1, metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
+; CHECK-NEXT: [[DENORMAL_1:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float f0x007FFFFF, i32 1, metadata !"round.dynamic", metadata !"fpexcept.maytrap") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[DENORMAL_1]], ptr addrspace(1) undef, align 4
; CHECK-NEXT: ret void
;
@@ -311,19 +311,19 @@ define void @ldexp_f32() {
; CHECK-NEXT: store volatile float 4.000000e+00, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float 8.000000e+00, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float 5.000000e-01, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x3810000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x3800000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x47E0000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x7FF0000000000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0x00800000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0x00400000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0x7F000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float +inf, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float -2.000000e+00, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float -4.000000e+00, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float -8.000000e+00, ptr addrspace(1) undef, align 4
; CHECK-NEXT: store volatile float -5.000000e-01, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0xB810000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0xB800000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0xC7E0000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0xFFF0000000000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x44D5000000000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0x80800000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0x80400000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0xFF000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float -inf, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0x66A80000, ptr addrspace(1) undef, align 4
; CHECK-NEXT: ret void
;
%one.one = call float @llvm.ldexp.f32.i32(float 1.0, i32 1)
@@ -385,8 +385,8 @@ define void @ldexp_f32() {
; considers this.
define void @ldexp_f32_denormal() {
; CHECK-LABEL: @ldexp_f32_denormal(
-; CHECK-NEXT: store volatile float 0x380FFFFFC0000000, ptr addrspace(1) undef, align 4
-; CHECK-NEXT: store volatile float 0x381FFFFFC0000000, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0x007FFFFF, ptr addrspace(1) undef, align 4
+; CHECK-NEXT: store volatile float f0x00FFFFFE, ptr addrspace(1) undef, align 4
; CHECK-NEXT: ret void
;
%denormal.0 = call float @llvm.ldexp.f32.i32(float 0x380FFFFFC0000000, i32 0)
@@ -402,7 +402,7 @@ define void @ldexp_f64() {
; CHECK-LABEL: @ldexp_f64(
; CHECK-NEXT: store volatile double 2.000000e+00, ptr addrspace(1) undef, align 8
; CHECK-NEXT: store volatile double 4.000000e+00, ptr addrspace(1) undef, align 8
-; CHECK-NEXT: store volatile double 0x44D5000000000000, ptr addrspace(1) undef, align 8
+; CHECK-NEXT: store volatile double f0x44D5000000000000, ptr addrspace(1) undef, align 8
; CHECK-NEXT: ret void
;
%one.one = call double @llvm.ldexp.f64.i32(double 1.0, i32 1)
@@ -419,9 +419,9 @@ define void @ldexp_f64() {
define void @ldexp_f16() {
; CHECK-LABEL: @ldexp_f16(
-; CHECK-NEXT: store volatile half 0xH4000, ptr addrspace(1) undef, align 2
-; CHECK-NEXT: store volatile half 0xH4400, ptr addrspace(1) undef, align 2
-; CHECK-NEXT: store volatile half 0xH7C00, ptr addrspace(1) undef, align 2
+; CHECK-NEXT: store volatile half 2.000000e+00, ptr addrspace(1) undef, align 2
+; CHECK-NEXT: store volatile half 4.000000e+00, ptr addrspace(1) undef, align 2
+; CHECK-NEXT: store volatile half +inf, ptr addrspace(1) undef, align 2
; CHECK-NEXT: ret void
;
%one.one = call half @llvm.ldexp.f16.i32(half 1.0, i32 1)
@@ -438,11 +438,11 @@ define void @ldexp_f16() {
define void @ldexp_ppcf128() {
; CHECK-LABEL: @ldexp_ppcf128(
-; CHECK-NEXT: store volatile ppc_fp128 0xMFFF00000000000000000000000000000, ptr addrspace(1) undef, align 16
-; CHECK-NEXT: store volatile ppc_fp128 0xMFFFC0000000000000000000000000000, ptr addrspace(1) undef, align 16
-; CHECK-NEXT: store volatile ppc_fp128 0xM3FD00000000000000000000000000000, ptr addrspace(1) undef, align 16
-; CHECK-NEXT: store volatile ppc_fp128 0xM41700000000000000000000000000000, ptr addrspace(1) undef, align 16
-; CHECK-NEXT: store volatile ppc_fp128 0xMC0700000000000000000000000000000, ptr addrspace(1) undef, align 16
+; CHECK-NEXT: store volatile ppc_fp128 -inf, ptr addrspace(1) undef, align 16
+; CHECK-NEXT: store volatile ppc_fp128 -nan(0x4000000000000), ptr addrspace(1) undef, align 16
+; CHECK-NEXT: store volatile ppc_fp128 2.500000e-01, ptr addrspace(1) undef, align 16
+; CHECK-NEXT: store volatile ppc_fp128 f0x00000000000000004170000000000000, ptr addrspace(1) undef, align 16
+; CHECK-NEXT: store volatile ppc_fp128 -2.560000e+02, ptr addrspace(1) undef, align 16
; CHECK-NEXT: ret void
;
%neginf = call ppc_fp128 @llvm.ldexp.ppcf128.i32(ppc_fp128 0xMFFF00000000000000000000000000000, i32 0)
@@ -465,9 +465,9 @@ define void @ldexp_ppcf128() {
define void @constant_fold_ldexp_f32_val_strictfp(i32 %y) #0 {
; CHECK-LABEL: @constant_fold_ldexp_f32_val_strictfp(
-; CHECK-NEXT: [[SNAN_MAY_TRAP:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x7FF0000020000000, i32 3, metadata !"round.tonearest", metadata !"fpexcept.maytrap") #[[ATTR0]]
+; CHECK-NEXT: [[SNAN_MAY_TRAP:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float +snan(0x1), i32 3, metadata !"round.tonearest", metadata !"fpexcept.maytrap") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[SNAN_MAY_TRAP]], ptr addrspace(1) undef, align 4
-; CHECK-NEXT: [[SNAN_MAY_NOT_TRAP:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 0x7FF0000020000000, i32 3, metadata !"round.tonearest", metadata !"fpexcept.ignore") #[[ATTR0]]
+; CHECK-NEXT: [[SNAN_MAY_NOT_TRAP:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float +snan(0x1), i32 3, metadata !"round.tonearest", metadata !"fpexcept.ignore") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[SNAN_MAY_NOT_TRAP]], ptr addrspace(1) undef, align 4
; CHECK-NEXT: [[UNKNOWN_ROUNDING:%.*]] = call float @llvm.experimental.constrained.ldexp.f32.i32(float 2.500000e+00, i32 42, metadata !"round.dynamic", metadata !"fpexcept.ignore") #[[ATTR0]]
; CHECK-NEXT: store volatile float [[UNKNOWN_ROUNDING]], ptr addrspace(1) undef, align 4
diff --git a/llvm/test/Transforms/InstSimplify/pr122582.ll b/llvm/test/Transforms/InstSimplify/pr122582.ll
index 0c341334b1773..ab4933d793973 100644
--- a/llvm/test/Transforms/InstSimplify/pr122582.ll
+++ b/llvm/test/Transforms/InstSimplify/pr122582.ll
@@ -75,7 +75,7 @@ define i32 @ilogb_neg_zero() {
define i32 @ilogbf_inf() {
; CHECK-LABEL: define i32 @ilogbf_inf() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float +inf)
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogbf(float 0x7FF0000000000000)
@@ -84,7 +84,7 @@ define i32 @ilogbf_inf() {
define i32 @ilogb_inf() {
; CHECK-LABEL: define i32 @ilogb_inf() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double 0x7FF0000000000000)
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double +inf)
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogb(double 0x7FF0000000000000)
@@ -93,7 +93,7 @@ define i32 @ilogb_inf() {
define i32 @ilogbf_nan() {
; CHECK-LABEL: define i32 @ilogbf_nan() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float +qnan)
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogbf(float 0x7FF8000000000000)
@@ -102,7 +102,7 @@ define i32 @ilogbf_nan() {
define i32 @ilogb_nan() {
; CHECK-LABEL: define i32 @ilogb_nan() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double 0x7FF8000000000000)
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double +qnan)
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogb(double 0x7FF8000000000000)
@@ -147,7 +147,7 @@ define i32 @ilogb_neg_zero_readnone() {
define i32 @ilogbf_inf_readnone() {
; CHECK-LABEL: define i32 @ilogbf_inf_readnone() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float 0x7FF0000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float +inf) #[[ATTR1]]
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogbf(float 0x7FF0000000000000) readnone
@@ -156,7 +156,7 @@ define i32 @ilogbf_inf_readnone() {
define i32 @ilogb_inf_readnone() {
; CHECK-LABEL: define i32 @ilogb_inf_readnone() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double 0x7FF0000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double +inf) #[[ATTR1]]
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogb(double 0x7FF0000000000000) readnone
@@ -165,7 +165,7 @@ define i32 @ilogb_inf_readnone() {
define i32 @ilogbf_nan_readnone() {
; CHECK-LABEL: define i32 @ilogbf_nan_readnone() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float 0x7FF8000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogbf(float +qnan) #[[ATTR1]]
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogbf(float 0x7FF8000000000000) readnone
@@ -174,7 +174,7 @@ define i32 @ilogbf_nan_readnone() {
define i32 @ilogb_nan_readnone() {
; CHECK-LABEL: define i32 @ilogb_nan_readnone() {
-; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double 0x7FF8000000000000) #[[ATTR1]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @ilogb(double +qnan) #[[ATTR1]]
; CHECK-NEXT: ret i32 [[R]]
;
%r = call i32 @ilogb(double 0x7FF8000000000000) readnone
diff --git a/llvm/test/Transforms/InstSimplify/select-equivalence-fp.ll b/llvm/test/Transforms/InstSimplify/select-equivalence-fp.ll
index 81132029466f9..a4d09a306415a 100644
--- a/llvm/test/Transforms/InstSimplify/select-equivalence-fp.ll
+++ b/llvm/test/Transforms/InstSimplify/select-equivalence-fp.ll
@@ -195,7 +195,7 @@ define <4 x float> @select_fcmp_shufflevector_select(<4 x float> %x) {
; The hexfloat constant is PI / 2.
define float @select_fcmp_sin_nonrefinement(float %x) {
; CHECK-LABEL: @select_fcmp_sin_nonrefinement(
-; CHECK-NEXT: [[FCMP:%.*]] = fcmp oeq float [[X:%.*]], 0x3FF921FB60000000
+; CHECK-NEXT: [[FCMP:%.*]] = fcmp oeq float [[X:%.*]], f0x3FC90FDB
; CHECK-NEXT: [[SIN:%.*]] = call float @llvm.sin.f32(float [[X]])
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[FCMP]], float 1.000000e+00, float [[SIN]]
; CHECK-NEXT: ret float [[SEL]]
@@ -220,7 +220,7 @@ define float @select_fcmp_sin(float %x) {
; The hexfloat constant is PI.
define float @select_fcmp_cos_nonrefinement(float %x) {
; CHECK-LABEL: @select_fcmp_cos_nonrefinement(
-; CHECK-NEXT: [[FCMP:%.*]] = fcmp oeq float [[X:%.*]], 0x400921FB60000000
+; CHECK-NEXT: [[FCMP:%.*]] = fcmp oeq float [[X:%.*]], f0x40490FDB
; CHECK-NEXT: [[COS:%.*]] = call float @llvm.cos.f32(float [[X]])
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[FCMP]], float -1.000000e+00, float [[COS]]
; CHECK-NEXT: ret float [[SEL]]
diff --git a/llvm/test/Transforms/InstSimplify/sincos.ll b/llvm/test/Transforms/InstSimplify/sincos.ll
index 144da53c6917b..2774e2e1ec76e 100644
--- a/llvm/test/Transforms/InstSimplify/sincos.ll
+++ b/llvm/test/Transforms/InstSimplify/sincos.ll
@@ -110,7 +110,7 @@ define { <vscale x 2 x float>, <vscale x 2 x float> } @sincos_zero_scalable_vect
define { float, float } @sincos_inf() {
; CHECK-LABEL: define { float, float } @sincos_inf() {
-; CHECK-NEXT: [[RET:%.*]] = call { float, float } @llvm.sincos.f32(float 0x7FF0000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call { float, float } @llvm.sincos.f32(float +inf)
; CHECK-NEXT: ret { float, float } [[RET]]
;
%ret = call { float, float } @llvm.sincos.f32(float 0x7FF0000000000000)
@@ -119,7 +119,7 @@ define { float, float } @sincos_inf() {
define { float, float } @sincos_neginf() {
; CHECK-LABEL: define { float, float } @sincos_neginf() {
-; CHECK-NEXT: [[RET:%.*]] = call { float, float } @llvm.sincos.f32(float 0xFFF0000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call { float, float } @llvm.sincos.f32(float -inf)
; CHECK-NEXT: ret { float, float } [[RET]]
;
%ret = call { float, float } @llvm.sincos.f32(float 0xFFF0000000000000)
@@ -128,7 +128,7 @@ define { float, float } @sincos_neginf() {
define { float, float } @sincos_qnan() {
; CHECK-LABEL: define { float, float } @sincos_qnan() {
-; CHECK-NEXT: [[RET:%.*]] = call { float, float } @llvm.sincos.f32(float 0x7FF8000000000000)
+; CHECK-NEXT: [[RET:%.*]] = call { float, float } @llvm.sincos.f32(float +qnan)
; CHECK-NEXT: ret { float, float } [[RET]]
;
%ret = call { float, float } @llvm.sincos.f32(float 0x7FF8000000000000)
@@ -137,7 +137,7 @@ define { float, float } @sincos_qnan() {
define { float, float } @sincos_snan() {
; CHECK-LABEL: define { float, float } @sincos_snan() {
-; CHECK-NEXT: [[RET:%.*]] = call { float, float } @llvm.sincos.f32(float 0x7FF0000020000000)
+; CHECK-NEXT: [[RET:%.*]] = call { float, float } @llvm.sincos.f32(float +snan(0x1))
; CHECK-NEXT: ret { float, float } [[RET]]
;
%ret = call { float, float } @llvm.sincos.f32(float bitcast (i32 2139095041 to float))
diff --git a/llvm/test/Transforms/InstSimplify/strictfp-fadd.ll b/llvm/test/Transforms/InstSimplify/strictfp-fadd.ll
index d75c00e04c4eb..bfc7c038322d4 100644
--- a/llvm/test/Transforms/InstSimplify/strictfp-fadd.ll
+++ b/llvm/test/Transforms/InstSimplify/strictfp-fadd.ll
@@ -355,7 +355,7 @@ define <2 x float> @fold_fadd_vec_nsz_0_x_ebmaytrap(<2 x float> %a) #0 {
define float @fold_fadd_qnan_qnan_ebmaytrap() #0 {
; CHECK-LABEL: @fold_fadd_qnan_qnan_ebmaytrap(
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: ret float +qnan
;
%add = call float @llvm.experimental.constrained.fadd.f32(float 0x7ff8000000000000, float 0x7ff8000000000000, metadata !"round.tonearest", metadata !"fpexcept.maytrap") #0
ret float %add
@@ -363,8 +363,8 @@ define float @fold_fadd_qnan_qnan_ebmaytrap() #0 {
define float @fold_fadd_qnan_qnan_ebstrict() #0 {
; CHECK-LABEL: @fold_fadd_qnan_qnan_ebstrict(
-; CHECK-NEXT: [[ADD:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float 0x7FF8000000000000, float 0x7FF8000000000000, metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: ret float 0x7FF8000000000000
+; CHECK-NEXT: [[ADD:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float +qnan, float +qnan, metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: ret float +qnan
;
%add = call float @llvm.experimental.constrained.fadd.f32(float 0x7ff8000000000000, float 0x7ff8000000000000, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret float %add
@@ -374,7 +374,7 @@ define float @fold_fadd_qnan_qnan_ebstrict() #0 {
define float @fold_fadd_snan_variable_ebignore(float %x) #0 {
; CHECK-LABEL: @fold_fadd_snan_variable_ebignore(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%add = call float @llvm.experimental.constrained.fadd.f32(float 0x7ff4000000000000, float %x, metadata !"round.tonearest", metadata !"fpexcept.ignore") #0
ret float %add
@@ -384,7 +384,7 @@ define float @fold_fadd_snan_variable_ebignore(float %x) #0 {
define float @fold_fadd_snan_variable_ebmaytrap(float %x) #0 {
; CHECK-LABEL: @fold_fadd_snan_variable_ebmaytrap(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%add = call float @llvm.experimental.constrained.fadd.f32(float 0x7ff4000000000000, float %x, metadata !"round.tonearest", metadata !"fpexcept.maytrap") #0
ret float %add
@@ -394,7 +394,7 @@ define float @fold_fadd_snan_variable_ebmaytrap(float %x) #0 {
define <2 x float> @fold_fadd_vec_snan_variable_ebignore(<2 x float> %x) #0 {
; CHECK-LABEL: @fold_fadd_vec_snan_variable_ebignore(
-; CHECK-NEXT: ret <2 x float> <float 0x7FFC000000000000, float 0xFFFC000000000000>
+; CHECK-NEXT: ret <2 x float> <float +nan(0x200000), float -nan(0x200000)>
;
%add = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float><float 0x7ff4000000000000, float 0xfff4000000000000>, <2 x float> %x, metadata !"round.tonearest", metadata !"fpexcept.ignore") #0
ret <2 x float> %add
@@ -404,7 +404,7 @@ define <2 x float> @fold_fadd_vec_snan_variable_ebignore(<2 x float> %x) #0 {
define <2 x float> @fold_fadd_vec_snan_variable_ebmaytrap(<2 x float> %x) #0 {
; CHECK-LABEL: @fold_fadd_vec_snan_variable_ebmaytrap(
-; CHECK-NEXT: ret <2 x float> <float 0xFFFC000000000000, float 0x7FFC000000000000>
+; CHECK-NEXT: ret <2 x float> <float -nan(0x200000), float +nan(0x200000)>
;
%add = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float><float 0xfff4000000000000, float 0x7ff4000000000000>, <2 x float> %x, metadata !"round.tonearest", metadata !"fpexcept.maytrap") #0
ret <2 x float> %add
@@ -414,7 +414,7 @@ define <2 x float> @fold_fadd_vec_snan_variable_ebmaytrap(<2 x float> %x) #0 {
define <2 x float> @fold_fadd_vec_partial_snan_variable_ebignore(<2 x float> %x) #0 {
; CHECK-LABEL: @fold_fadd_vec_partial_snan_variable_ebignore(
-; CHECK-NEXT: ret <2 x float> <float 0x7FFC000000000000, float 0xFFFF000000000000>
+; CHECK-NEXT: ret <2 x float> <float +nan(0x200000), float -nan(0x380000)>
;
%add = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float><float 0x7ff4000000000000, float 0xffff000000000000>, <2 x float> %x, metadata !"round.tonearest", metadata !"fpexcept.ignore") #0
ret <2 x float> %add
@@ -424,7 +424,7 @@ define <2 x float> @fold_fadd_vec_partial_snan_variable_ebignore(<2 x float> %x)
define <2 x float> @fold_fadd_vec_partial_snan_variable_ebmaytrap(<2 x float> %x) #0 {
; CHECK-LABEL: @fold_fadd_vec_partial_snan_variable_ebmaytrap(
-; CHECK-NEXT: ret <2 x float> <float 0xFFF8000000000000, float 0x7FFC000000000000>
+; CHECK-NEXT: ret <2 x float> <float -qnan, float +nan(0x200000)>
;
%add = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float><float 0xfff8000000000000, float 0x7ff4000000000000>, <2 x float> %x, metadata !"round.tonearest", metadata !"fpexcept.maytrap") #0
ret <2 x float> %add
@@ -432,7 +432,7 @@ define <2 x float> @fold_fadd_vec_partial_snan_variable_ebmaytrap(<2 x float> %x
define float @fold_fadd_snan_variable_ebstrict(float %x) #0 {
; CHECK-LABEL: @fold_fadd_snan_variable_ebstrict(
-; CHECK-NEXT: [[ADD:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float 0x7FF4000000000000, float [[X:%.*]], metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[ADD:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float +snan(0x200000), float [[X:%.*]], metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret float [[ADD]]
;
%add = call float @llvm.experimental.constrained.fadd.f32(float 0x7ff4000000000000, float %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
@@ -441,7 +441,7 @@ define float @fold_fadd_snan_variable_ebstrict(float %x) #0 {
define float @fold_fadd_snan_qnan_ebmaytrap() #0 {
; CHECK-LABEL: @fold_fadd_snan_qnan_ebmaytrap(
-; CHECK-NEXT: ret float 0x7FFC000000000000
+; CHECK-NEXT: ret float +nan(0x200000)
;
%add = call float @llvm.experimental.constrained.fadd.f32(float 0x7ff4000000000000, float 0x7ff8000000000000, metadata !"round.tonearest", metadata !"fpexcept.maytrap") #0
ret float %add
@@ -449,7 +449,7 @@ define float @fold_fadd_snan_qnan_ebmaytrap() #0 {
define float @fold_fadd_snan_qnan_ebstrict() #0 {
; CHECK-LABEL: @fold_fadd_snan_qnan_ebstrict(
-; CHECK-NEXT: [[ADD:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float 0x7FF4000000000000, float 0x7FF8000000000000, metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
+; CHECK-NEXT: [[ADD:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float +snan(0x200000), float +qnan, metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR0]]
; CHECK-NEXT: ret float [[ADD]]
;
%add = call float @llvm.experimental.constrained.fadd.f32(float 0x7ff4000000000000, float 0x7ff8000000000000, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
diff --git a/llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll b/llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll
index 593f334abac1e..693ec343759e2 100644
--- a/llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll
+++ b/llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll
@@ -140,7 +140,7 @@ define <vscale x 2 x i1> @cmp_le_smax_always_true(<vscale x 2 x i64> %x) {
define <vscale x 4 x float> @bitcast() {
; CHECK-LABEL: @bitcast(
-; CHECK-NEXT: ret <vscale x 4 x float> splat (float 0x36A0000000000000)
+; CHECK-NEXT: ret <vscale x 4 x float> splat (float 1.401300e-45)
;
%i1 = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
%i2 = shufflevector <vscale x 4 x i32> %i1, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/Transforms/InstSimplify/vscale.ll b/llvm/test/Transforms/InstSimplify/vscale.ll
index c09a0c201d761..b21603067d42e 100644
--- a/llvm/test/Transforms/InstSimplify/vscale.ll
+++ b/llvm/test/Transforms/InstSimplify/vscale.ll
@@ -152,7 +152,7 @@ define <vscale x 2 x i1> @cmp_le_smax_always_true(<vscale x 2 x i64> %x) {
define <vscale x 4 x float> @bitcast() {
; CHECK-LABEL: @bitcast(
-; CHECK-NEXT: ret <vscale x 4 x float> splat (float 0x36A0000000000000)
+; CHECK-NEXT: ret <vscale x 4 x float> splat (float 1.401300e-45)
;
%i1 = insertelement <vscale x 4 x i32> undef, i32 1, i32 0
%i2 = shufflevector <vscale x 4 x i32> %i1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/Transforms/LICM/hoist-fast-fdiv.ll b/llvm/test/Transforms/LICM/hoist-fast-fdiv.ll
index 594dff446c0b6..4549e3f0e6c87 100644
--- a/llvm/test/Transforms/LICM/hoist-fast-fdiv.ll
+++ b/llvm/test/Transforms/LICM/hoist-fast-fdiv.ll
@@ -36,7 +36,7 @@ define void @invariant_fdiv(ptr %out, float %arg) {
; CHECK-LABEL: @invariant_fdiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: %div = fdiv fast float 4.000000e+00, %arg
-; CHECK-NEXT: fmul fast float %div, 0x41F0000000000000
+; CHECK-NEXT: fmul fast float %div, f0x4F800000
entry:
br label %loop
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
index 70c46f035636a..6c9f888d69849 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
@@ -80,7 +80,7 @@ define amdgpu_kernel void @merge_global_store_2_constants_i16_align_1(ptr addrsp
define amdgpu_kernel void @merge_global_store_2_constants_half_natural_align(ptr addrspace(1) %out) #0 {
; CHECK-LABEL: @merge_global_store_2_constants_half_natural_align(
-; CHECK-NEXT: store <2 x half> <half 0xH3C00, half 0xH4000>, ptr addrspace(1) [[OUT:%.*]], align 2
+; CHECK-NEXT: store <2 x half> <half 1.000000e+00, half 2.000000e+00>, ptr addrspace(1) [[OUT:%.*]], align 2
; CHECK-NEXT: ret void
;
%out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1
@@ -92,7 +92,7 @@ define amdgpu_kernel void @merge_global_store_2_constants_half_natural_align(ptr
define amdgpu_kernel void @merge_global_store_2_constants_half_align_1(ptr addrspace(1) %out) #0 {
; CHECK-LABEL: @merge_global_store_2_constants_half_align_1(
-; CHECK-NEXT: store <2 x half> <half 0xH3C00, half 0xH4000>, ptr addrspace(1) [[OUT:%.*]], align 1
+; CHECK-NEXT: store <2 x half> <half 1.000000e+00, half 2.000000e+00>, ptr addrspace(1) [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
%out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
index fe8a7e58a6a57..6a7a5dac40c83 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
@@ -96,10 +96,10 @@ define void @v1_4_4_4_2_1_to_v8_8_levels_6_7(i32 %arg0, ptr addrspace(3) align 1
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP5]], i32 [[ARG4]]
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[GEP]], i32 [[ARG5]]
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> poison, half [[ARG6_HALF]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x half> [[TMP7]], half 0xH0000, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x half> [[TMP8]], half 0xH0000, i32 2
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x half> [[TMP9]], half 0xH0000, i32 3
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x half> [[TMP10]], half 0xH0000, i32 4
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x half> [[TMP7]], half 0.000000e+00, i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x half> [[TMP8]], half 0.000000e+00, i32 2
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x half> [[TMP9]], half 0.000000e+00, i32 3
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x half> [[TMP10]], half 0.000000e+00, i32 4
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x half> [[ARG8_2XHALF]], i32 0
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x half> [[TMP11]], half [[TMP12]], i32 5
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x half> [[ARG8_2XHALF]], i32 1
diff --git a/llvm/test/Transforms/LoopLoadElim/type-mismatch-opaque-ptr.ll b/llvm/test/Transforms/LoopLoadElim/type-mismatch-opaque-ptr.ll
index e6a8af60f1287..303b4f20c36f9 100644
--- a/llvm/test/Transforms/LoopLoadElim/type-mismatch-opaque-ptr.ll
+++ b/llvm/test/Transforms/LoopLoadElim/type-mismatch-opaque-ptr.ll
@@ -217,7 +217,7 @@ define void @f4(ptr noalias %A, ptr noalias %B, ptr noalias %C, i64 %N) {
; CHECK-NEXT: [[STORE_FORWARD_CAST]] = bitcast i32 [[A_P1]] to <2 x half>
; CHECK-NEXT: store i32 [[A_P1]], ptr [[AIDX_NEXT]], align 4
; CHECK-NEXT: [[A:%.*]] = load <2 x half>, ptr [[AIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = fmul <2 x half> [[STORE_FORWARDED]], splat (half 0xH4000)
+; CHECK-NEXT: [[C:%.*]] = fmul <2 x half> [[STORE_FORWARDED]], splat (half 2.000000e+00)
; CHECK-NEXT: [[C_INT:%.*]] = bitcast <2 x half> [[C]] to i32
; CHECK-NEXT: store i32 [[C_INT]], ptr [[CIDX]], align 4
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
diff --git a/llvm/test/Transforms/LoopLoadElim/type-mismatch.ll b/llvm/test/Transforms/LoopLoadElim/type-mismatch.ll
index 56b910eebea92..167074db2a84e 100644
--- a/llvm/test/Transforms/LoopLoadElim/type-mismatch.ll
+++ b/llvm/test/Transforms/LoopLoadElim/type-mismatch.ll
@@ -217,7 +217,7 @@ define void @f4(ptr noalias %A, ptr noalias %B, ptr noalias %C, i64 %N) {
; CHECK-NEXT: [[STORE_FORWARD_CAST]] = bitcast i32 [[A_P1]] to <2 x half>
; CHECK-NEXT: store i32 [[A_P1]], ptr [[AIDX_NEXT]], align 4
; CHECK-NEXT: [[A:%.*]] = load <2 x half>, ptr [[AIDX]], align 4
-; CHECK-NEXT: [[C:%.*]] = fmul <2 x half> [[STORE_FORWARDED]], splat (half 0xH4000)
+; CHECK-NEXT: [[C:%.*]] = fmul <2 x half> [[STORE_FORWARDED]], splat (half 2.000000e+00)
; CHECK-NEXT: [[C_INT:%.*]] = bitcast <2 x half> [[C]] to i32
; CHECK-NEXT: store i32 [[C_INT]], ptr [[CIDX]], align 4
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/preserving-debugloc-phi-binop.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/preserving-debugloc-phi-binop.ll
index 1aecd34082a2a..fd608158691ad 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/preserving-debugloc-phi-binop.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/preserving-debugloc-phi-binop.ll
@@ -10,7 +10,7 @@ define i32 @foobar6() !dbg !5 {
; CHECK-LABEL: define i32 @foobar6(
; CHECK: loop:
; CHECK: [[IV_S_:%.*]] = phi double [ -3.220000e+03, %[[ENTRY:.*]] ], [ [[IV_S_NEXT_:%.*]], %loop ], !dbg [[DBG9:![0-9]+]]
-; CHECK: [[IV_S_NEXT_]] = fadd double [[IV_S_]], 0x41624E65A0000000, !dbg [[DBG11:![0-9]+]]
+; CHECK: [[IV_S_NEXT_]] = fadd double [[IV_S_]], f0x41624E65A0000000, !dbg [[DBG11:![0-9]+]]
; CHECK: exit:
;
entry:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll b/llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
index f91a248700694..e2fd747cc2dbf 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
@@ -107,7 +107,7 @@ define void @loop_contains_store_fcmp_condition(ptr dereferenceable(40) noalias
; CHECK-NEXT: store i16 [[INC]], ptr [[ST_ADDR]], align 2
; CHECK-NEXT: [[EE_ADDR:%.*]] = getelementptr inbounds nuw half, ptr [[PRED]], i64 [[IV]]
; CHECK-NEXT: [[EE_VAL:%.*]] = load half, ptr [[EE_ADDR]], align 2
-; CHECK-NEXT: [[EE_COND:%.*]] = fcmp ugt half [[EE_VAL]], 0xH5FD0
+; CHECK-NEXT: [[EE_COND:%.*]] = fcmp ugt half [[EE_VAL]], 5.000000e+02
; CHECK-NEXT: br i1 [[EE_COND]], label %[[EXIT:.*]], label %[[FOR_INC]]
; CHECK: [[FOR_INC]]:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
index f7b73371345bc..07b3480b4964e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
@@ -278,7 +278,7 @@ define fp128 @not_fdot_f64_f128(ptr %a, ptr %b, fp128 %zero) #0 {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x fp128> splat (fp128 0xL00000000000000008000000000000000), fp128 [[ZERO]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x fp128> splat (fp128 -0.000000e+00), fp128 [[ZERO]], i32 0
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
@@ -295,7 +295,7 @@ define fp128 @not_fdot_f64_f128(ptr %a, ptr %b, fp128 %zero) #0 {
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP14:%.*]] = call reassoc contract fp128 @llvm.vector.reduce.fadd.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> [[TMP12]])
+; CHECK-NEXT: [[TMP14:%.*]] = call reassoc contract fp128 @llvm.vector.reduce.fadd.v2f128(fp128 -0.000000e+00, <2 x fp128> [[TMP12]])
; CHECK-NEXT: br label %[[FOR_EXIT:.*]]
; CHECK: [[FOR_EXIT]]:
; CHECK-NEXT: ret fp128 [[TMP14]]
@@ -426,7 +426,7 @@ define fp128 @not_fdot_f64_f128_nosve(ptr %a, ptr %b, fp128 %zero) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x fp128> splat (fp128 0xL00000000000000008000000000000000), fp128 [[ZERO]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x fp128> splat (fp128 -0.000000e+00), fp128 [[ZERO]], i32 0
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
@@ -443,7 +443,7 @@ define fp128 @not_fdot_f64_f128_nosve(ptr %a, ptr %b, fp128 %zero) {
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP14:%.*]] = call reassoc contract fp128 @llvm.vector.reduce.fadd.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> [[TMP12]])
+; CHECK-NEXT: [[TMP14:%.*]] = call reassoc contract fp128 @llvm.vector.reduce.fadd.v2f128(fp128 -0.000000e+00, <2 x fp128> [[TMP12]])
; CHECK-NEXT: br label %[[FOR_EXIT:.*]]
; CHECK: [[FOR_EXIT]]:
; CHECK-NEXT: ret fp128 [[TMP14]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
index 4b4c73c032247..a82a2ec2e98be 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
@@ -105,7 +105,7 @@ define float @cond_cmp_sel(ptr noalias %a, ptr noalias %cond, i64 %N) {
; CHECK-NEXT: [[TMP9:%.*]] = fcmp une <vscale x 4 x float> [[WIDE_LOAD]], splat (float 3.000000e+00)
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr float, ptr [[A:%.*]], i64 [[INDEX]]
; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0(ptr align 4 [[TMP10]], <vscale x 4 x i1> [[TMP9]], <vscale x 4 x float> poison)
-; CHECK-NEXT: [[TMP12:%.*]] = select fast <vscale x 4 x i1> [[TMP9]], <vscale x 4 x float> [[WIDE_MASKED_LOAD]], <vscale x 4 x float> splat (float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[TMP12:%.*]] = select fast <vscale x 4 x i1> [[TMP9]], <vscale x 4 x float> [[WIDE_MASKED_LOAD]], <vscale x 4 x float> splat (float f0x7F7FFFFF)
; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> [[TMP12]])
; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = fcmp fast olt float [[TMP13]], [[VEC_PHI]]
; CHECK-NEXT: [[RDX_MINMAX_SELECT]] = select fast i1 [[RDX_MINMAX_CMP]], float [[TMP13]], float [[VEC_PHI]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
index 0b118e3acc063..6adb5e5dd8a1f 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll
@@ -231,7 +231,7 @@ define bfloat @fadd_fast_bfloat(ptr noalias nocapture readonly %a, i64 %n) {
; CHECK: %[[FADD2:.*]] = fadd fast <8 x bfloat> %[[LOAD2]]
; CHECK: middle.block:
; CHECK: %[[RDX:.*]] = fadd fast <8 x bfloat> %[[FADD2]], %[[FADD1]]
-; CHECK: call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0xR0000, <8 x bfloat> %[[RDX]])
+; CHECK: call fast bfloat @llvm.vector.reduce.fadd.v8bf16(bfloat 0.000000e+00, <8 x bfloat> %[[RDX]])
entry:
br label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll
index 2c476b8d8c54e..aaf67f4a92794 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalar_interleave.ll
@@ -51,7 +51,7 @@ define void @arm_correlate_f16(ptr nocapture noundef readonly %pSrcA, i32 nounde
; CHECK-NEXT: br label [[FOR_BODY16:%.*]]
; CHECK: for.body16:
; CHECK-NEXT: [[J_074:%.*]] = phi i32 [ 0, [[FOR_COND14_PREHEADER]] ], [ [[INC:%.*]], [[FOR_INC:%.*]] ]
-; CHECK-NEXT: [[SUM_073:%.*]] = phi half [ 0xH0000, [[FOR_COND14_PREHEADER]] ], [ [[SUM_1:%.*]], [[FOR_INC]] ]
+; CHECK-NEXT: [[SUM_073:%.*]] = phi half [ 0.000000e+00, [[FOR_COND14_PREHEADER]] ], [ [[SUM_1:%.*]], [[FOR_INC]] ]
; CHECK-NEXT: [[SUB17:%.*]] = sub i32 [[I_077]], [[J_074]]
; CHECK-NEXT: [[CMP18:%.*]] = icmp ult i32 [[SUB17]], [[SRCBLEN_ADDR_0]]
; CHECK-NEXT: [[CMP19:%.*]] = icmp ult i32 [[J_074]], [[SRCALEN_ADDR_0]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
index b78fee37eb623..44e8487523e6d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
@@ -23,7 +23,7 @@ define float @fadd_strict(ptr noalias nocapture readonly %a, i64 %n) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi float [ 0xFFFFFFFFE0000000, [[VECTOR_PH]] ], [ [[TMP19:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi float [ -nan(0x3FFFFF), [[VECTOR_PH]] ], [ [[TMP19:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[INDEX]]
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[TMP4]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP12]], align 4
@@ -41,7 +41,7 @@ define float @fadd_strict(ptr noalias nocapture readonly %a, i64 %n) {
; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
; CHECK: vec.epilog.ph:
; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP19]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0xFFFFFFFFE0000000, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP19]], [[VEC_EPILOG_ITER_CHECK]] ], [ -nan(0x3FFFFF), [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
; CHECK-NEXT: [[N_MOD_VF3:%.*]] = urem i64 [[N]], 2
; CHECK-NEXT: [[N_VEC4:%.*]] = sub i64 [[N]], [[N_MOD_VF3]]
; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
@@ -59,7 +59,7 @@ define float @fadd_strict(ptr noalias nocapture readonly %a, i64 %n) {
; CHECK-NEXT: br i1 [[CMP_N5]], label [[FOR_END]], label [[VEC_EPILOG_SCALAR_PH]]
; CHECK: vec.epilog.scalar.ph:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC4]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX10:%.*]] = phi float [ [[TMP24]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP19]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0xFFFFFFFFE0000000, [[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX10:%.*]] = phi float [ [[TMP24]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP19]], [[VEC_EPILOG_ITER_CHECK]] ], [ -nan(0x3FFFFF), [[ITER_CHECK]] ]
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
;
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll
index 836ece3b311bd..e735fad4e56ae 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll
@@ -36,8 +36,8 @@ define void @loop_sve_f128(ptr nocapture %ptr, i64 %N) {
; CHECK: vector.body
; CHECK: %[[LOAD1:.*]] = load fp128, ptr
; CHECK-NEXT: %[[LOAD2:.*]] = load fp128, ptr
-; CHECK-NEXT: %[[FSUB1:.*]] = fsub fp128 %[[LOAD1]], 0xL00000000000000008000000000000000
-; CHECK-NEXT: %[[FSUB2:.*]] = fsub fp128 %[[LOAD2]], 0xL00000000000000008000000000000000
+; CHECK-NEXT: %[[FSUB1:.*]] = fsub fp128 %[[LOAD1]], -0.000000e+00
+; CHECK-NEXT: %[[FSUB2:.*]] = fsub fp128 %[[LOAD2]], -0.000000e+00
; CHECK-NEXT: store fp128 %[[FSUB1]], ptr {{.*}}
; CHECK-NEXT: store fp128 %[[FSUB2]], ptr {{.*}}
entry:
diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
index c9f2495030972..8f298bd678014 100644
--- a/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
+++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
@@ -26,7 +26,7 @@ define half @vectorize_v2f16_loop(ptr addrspace(1) noalias %s) {
; GFX9-NEXT: br label [[FOR_BODY:%.*]]
; GFX9: for.end:
; GFX9-NEXT: [[BIN_RDX:%.*]] = fadd fast <2 x half> [[TMP3]], [[TMP2]]
-; GFX9-NEXT: [[ADD_LCSSA:%.*]] = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> [[BIN_RDX]])
+; GFX9-NEXT: [[ADD_LCSSA:%.*]] = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> [[BIN_RDX]])
; GFX9-NEXT: ret half [[ADD_LCSSA]]
;
; VI-LABEL: @vectorize_v2f16_loop(
@@ -51,7 +51,7 @@ define half @vectorize_v2f16_loop(ptr addrspace(1) noalias %s) {
; VI-NEXT: br label [[FOR_BODY:%.*]]
; VI: for.end:
; VI-NEXT: [[BIN_RDX:%.*]] = fadd fast <2 x half> [[TMP3]], [[TMP2]]
-; VI-NEXT: [[ADD_LCSSA:%.*]] = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> [[BIN_RDX]])
+; VI-NEXT: [[ADD_LCSSA:%.*]] = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> [[BIN_RDX]])
; VI-NEXT: ret half [[ADD_LCSSA]]
;
; CI-LABEL: @vectorize_v2f16_loop(
@@ -59,7 +59,7 @@ define half @vectorize_v2f16_loop(ptr addrspace(1) noalias %s) {
; CI-NEXT: br label [[FOR_BODY:%.*]]
; CI: for.body:
; CI-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
-; CI-NEXT: [[Q_04:%.*]] = phi half [ 0xH0000, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
+; CI-NEXT: [[Q_04:%.*]] = phi half [ 0.000000e+00, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CI-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [2 x i8], ptr addrspace(1) [[S:%.*]], i64 [[INDVARS_IV]]
; CI-NEXT: [[TMP0:%.*]] = load half, ptr addrspace(1) [[ARRAYIDX]], align 2
; CI-NEXT: [[ADD]] = fadd fast half [[Q_04]], [[TMP0]]
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
index 9e27205a67f35..384ecd5e11782 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
@@ -421,7 +421,7 @@ define void @fptrunc_not_allowed(ptr noalias nocapture %A, ptr noalias nocapture
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i32 [[INDEX]]
; CHECK-NEXT: store <4 x float> [[TMP5]], ptr [[TMP6]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = fptrunc <4 x float> [[TMP5]] to <4 x half>
-; CHECK-NEXT: [[TMP9:%.*]] = fmul fast <4 x half> [[TMP8]], splat (half 0xH4000)
+; CHECK-NEXT: [[TMP9:%.*]] = fmul fast <4 x half> [[TMP8]], splat (half 2.000000e+00)
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds half, ptr [[D:%.*]], i32 [[INDEX]]
; CHECK-NEXT: store <4 x half> [[TMP9]], ptr [[TMP10]], align 2
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
@@ -443,7 +443,7 @@ define void @fptrunc_not_allowed(ptr noalias nocapture %A, ptr noalias nocapture
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[A]], i32 [[I_017]]
; CHECK-NEXT: store float [[ADD]], ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[CONV:%.*]] = fptrunc float [[ADD]] to half
-; CHECK-NEXT: [[FACTOR:%.*]] = fmul fast half [[CONV]], 0xH4000
+; CHECK-NEXT: [[FACTOR:%.*]] = fmul fast half [[CONV]], 2.000000e+00
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds half, ptr [[D]], i32 [[I_017]]
; CHECK-NEXT: store half [[FACTOR]], ptr [[ARRAYIDX5]], align 2
; CHECK-NEXT: [[ADD6]] = add nuw nsw i32 [[I_017]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll b/llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
index 4c3d11d6c982e..e1361126b6331 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
@@ -105,7 +105,7 @@ define void @loop_contains_store_fcmp_condition(ptr dereferenceable(40) noalias
; CHECK-NEXT: store i16 [[INC]], ptr [[ST_ADDR]], align 2
; CHECK-NEXT: [[EE_ADDR:%.*]] = getelementptr inbounds nuw half, ptr [[PRED]], i64 [[IV]]
; CHECK-NEXT: [[EE_VAL:%.*]] = load half, ptr [[EE_ADDR]], align 2
-; CHECK-NEXT: [[EE_COND:%.*]] = fcmp ugt half [[EE_VAL]], 0xH5FD0
+; CHECK-NEXT: [[EE_COND:%.*]] = fcmp ugt half [[EE_VAL]], 5.000000e+02
; CHECK-NEXT: br i1 [[EE_COND]], label %[[EXIT:.*]], label %[[FOR_INC]]
; CHECK: [[FOR_INC]]:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll b/llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
index c110c1bc001f2..b2407d4f5a401 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
@@ -44,7 +44,7 @@ define void @loop_f128(ptr nocapture %ptr, i64 %N) {
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds fp128, ptr [[PTR:%.*]], i64 [[IV]]
; CHECK-NEXT: [[TMP0:%.*]] = load fp128, ptr [[ARRAYIDX]], align 16
-; CHECK-NEXT: [[ADD:%.*]] = fsub fp128 [[TMP0]], 0xL00000000000000008000000000000000
+; CHECK-NEXT: [[ADD:%.*]] = fsub fp128 [[TMP0]], -0.000000e+00
; CHECK-NEXT: store fp128 [[ADD]], ptr [[ARRAYIDX]], align 16
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N:%.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
index 743ff4767b912..a09ffdeb25691 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
@@ -446,7 +446,7 @@ define half @fadd_fast_half_zvfh(ptr noalias nocapture readonly %a, i64 %n) "tar
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP11:%.*]] = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, <vscale x 8 x half> [[TMP8]])
+; CHECK-NEXT: [[TMP11:%.*]] = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0.000000e+00, <vscale x 8 x half> [[TMP8]])
; CHECK-NEXT: br label %[[FOR_END:.*]]
; CHECK: [[FOR_END]]:
; CHECK-NEXT: ret half [[TMP11]]
@@ -493,12 +493,12 @@ define half @fadd_fast_half_zvfhmin(ptr noalias nocapture readonly %a, i64 %n) "
; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <16 x half> [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP5:%.*]] = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> [[BIN_RDX]])
+; CHECK-NEXT: [[TMP5:%.*]] = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> [[BIN_RDX]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi half [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi half [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
@@ -555,12 +555,12 @@ define bfloat @fadd_fast_bfloat(ptr noalias nocapture readonly %a, i64 %n) "targ
; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <16 x bfloat> [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP5:%.*]] = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR0000, <16 x bfloat> [[BIN_RDX]])
+; CHECK-NEXT: [[TMP5:%.*]] = call fast bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0.000000e+00, <16 x bfloat> [[BIN_RDX]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi bfloat [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0xR0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi bfloat [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
@@ -1071,7 +1071,7 @@ define half @fmuladd_f16_zvfh(ptr %a, ptr %b, i64 %n) "target-features"="+zvfh"
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x half> [ insertelement (<vscale x 8 x half> splat (half 0xH8000), half 0xH0000, i32 0), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x half> [ insertelement (<vscale x 8 x half> splat (half -0.000000e+00), half 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[INDEX]]
@@ -1086,7 +1086,7 @@ define half @fmuladd_f16_zvfh(ptr %a, ptr %b, i64 %n) "target-features"="+zvfh"
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP27:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP16:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP9]])
+; CHECK-NEXT: [[TMP16:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half -0.000000e+00, <vscale x 8 x half> [[TMP9]])
; CHECK-NEXT: br label %[[FOR_END:.*]]
; CHECK: [[FOR_END]]:
; CHECK-NEXT: ret half [[TMP16]]
@@ -1125,8 +1125,8 @@ define half @fmuladd_f16_zvfhmin(ptr %a, ptr %b, i64 %n) "target-features"="+zvf
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <16 x half> [ <half 0xH0000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <16 x half> [ splat (half 0xH8000), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <16 x half> [ <half 0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <16 x half> [ splat (half -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[INDEX]]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds half, ptr [[TMP0]], i64 16
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x half>, ptr [[TMP0]], align 4
@@ -1142,12 +1142,12 @@ define half @fmuladd_f16_zvfhmin(ptr %a, ptr %b, i64 %n) "target-features"="+zvf
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP28:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <16 x half> [[TMP5]], [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = call reassoc half @llvm.vector.reduce.fadd.v16f16(half 0xH8000, <16 x half> [[BIN_RDX]])
+; CHECK-NEXT: [[TMP7:%.*]] = call reassoc half @llvm.vector.reduce.fadd.v16f16(half -0.000000e+00, <16 x half> [[BIN_RDX]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi half [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi half [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
@@ -1195,8 +1195,8 @@ define bfloat @fmuladd_bf16(ptr %a, ptr %b, i64 %n) "target-features"="+zvfbfmin
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <16 x bfloat> [ <bfloat 0xR0000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000, bfloat 0xR8000>, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <16 x bfloat> [ splat (bfloat 0xR8000), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <16 x bfloat> [ <bfloat 0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00, bfloat -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <16 x bfloat> [ splat (bfloat -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds bfloat, ptr [[A]], i64 [[INDEX]]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds bfloat, ptr [[TMP0]], i64 16
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x bfloat>, ptr [[TMP0]], align 4
@@ -1212,12 +1212,12 @@ define bfloat @fmuladd_bf16(ptr %a, ptr %b, i64 %n) "target-features"="+zvfbfmin
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <16 x bfloat> [[TMP5]], [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = call reassoc bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat 0xR8000, <16 x bfloat> [[BIN_RDX]])
+; CHECK-NEXT: [[TMP7:%.*]] = call reassoc bfloat @llvm.vector.reduce.fadd.v16bf16(bfloat -0.000000e+00, <16 x bfloat> [[BIN_RDX]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi bfloat [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0xR0000, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi bfloat [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
index cda500a54ed8e..33dfe3670a580 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
@@ -1000,7 +1000,7 @@ define float @fmin(ptr %a, i64 %n, float %start) {
; IF-EVL-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[TMP14:%.*]] = call fast float @llvm.vp.reduce.fmin.nxv4f32(float 0x47EFFFFFE0000000, <vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
+; IF-EVL-NEXT: [[TMP14:%.*]] = call fast float @llvm.vp.reduce.fmin.nxv4f32(float f0x7F7FFFFF, <vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
; IF-EVL-NEXT: [[RDX_MINMAX_CMP:%.*]] = fcmp fast olt float [[TMP14]], [[VEC_PHI]]
; IF-EVL-NEXT: [[RDX_MINMAX_SELECT]] = select fast i1 [[RDX_MINMAX_CMP]], float [[TMP14]], float [[VEC_PHI]]
; IF-EVL-NEXT: [[TMP8:%.*]] = zext i32 [[TMP11]] to i64
@@ -1088,7 +1088,7 @@ define float @fmax(ptr %a, i64 %n, float %start) {
; IF-EVL-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
; IF-EVL-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[EVL_BASED_IV]]
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
-; IF-EVL-NEXT: [[TMP14:%.*]] = call fast float @llvm.vp.reduce.fmax.nxv4f32(float 0xC7EFFFFFE0000000, <vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
+; IF-EVL-NEXT: [[TMP14:%.*]] = call fast float @llvm.vp.reduce.fmax.nxv4f32(float f0xFF7FFFFF, <vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]])
; IF-EVL-NEXT: [[RDX_MINMAX_CMP:%.*]] = fcmp fast ogt float [[TMP14]], [[VEC_PHI]]
; IF-EVL-NEXT: [[RDX_MINMAX_SELECT]] = select fast i1 [[RDX_MINMAX_CMP]], float [[TMP14]], float [[VEC_PHI]]
; IF-EVL-NEXT: [[TMP8:%.*]] = zext i32 [[TMP11]] to i64
diff --git a/llvm/test/Transforms/LoopVectorize/X86/cast-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/cast-costs.ll
index e28e18871e2fd..26b3a4326113a 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/cast-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/cast-costs.ll
@@ -287,7 +287,7 @@ define i16 @bitcast_half_to_i16(ptr %src, ptr %dst, i64 %n) {
; CHECK-NEXT: [[RDX:%.*]] = phi i16 [ [[BC_MERGE_RDX11]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[OR:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr half, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[LOAD1:%.*]] = load half, ptr [[GEP]], align 2
-; CHECK-NEXT: [[FADD1:%.*]] = fadd half [[LOAD1]], 0xH0000
+; CHECK-NEXT: [[FADD1:%.*]] = fadd half [[LOAD1]], 0.000000e+00
; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast half [[FADD1]] to i16
; CHECK-NEXT: [[OR]] = or i16 [[RDX]], [[BITCAST1]]
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/X86/fp80-widest-type.ll b/llvm/test/Transforms/LoopVectorize/X86/fp80-widest-type.ll
index bd5f69f6a1a2d..19918cb9fe49c 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/fp80-widest-type.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/fp80-widest-type.ll
@@ -14,8 +14,8 @@ define x86_fp80 @test() {
; CHECK-NEXT: br label [[FOR_BODY3_I_3:%.*]]
; CHECK: for.body3.i.3:
; CHECK-NEXT: [[N_ADDR_112_I_3:%.*]] = phi i64 [ [[DEC_I_3:%.*]], [[FOR_BODY3_I_3]] ], [ 24, [[FOO_EXIT:%.*]] ]
-; CHECK-NEXT: [[X_ADDR_111_I_3:%.*]] = phi x86_fp80 [ [[MUL_I_3:%.*]], [[FOR_BODY3_I_3]] ], [ 0xK00000000000000000000, [[FOO_EXIT]] ]
-; CHECK-NEXT: [[MUL_I_3]] = fmul x86_fp80 [[X_ADDR_111_I_3]], 0xK40008000000000000000
+; CHECK-NEXT: [[X_ADDR_111_I_3:%.*]] = phi x86_fp80 [ [[MUL_I_3:%.*]], [[FOR_BODY3_I_3]] ], [ 0.000000e+00, [[FOO_EXIT]] ]
+; CHECK-NEXT: [[MUL_I_3]] = fmul x86_fp80 [[X_ADDR_111_I_3]], 2.000000e+00
; CHECK-NEXT: [[DEC_I_3]] = add nsw i64 [[N_ADDR_112_I_3]], -1
; CHECK-NEXT: [[CMP2_I_3:%.*]] = icmp sgt i64 [[N_ADDR_112_I_3]], 1
; CHECK-NEXT: br i1 [[CMP2_I_3]], label [[FOR_BODY3_I_3]], label [[FOO_EXIT_3:%.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll b/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
index a80fd0bf6ddd7..ffba4f87c07b0 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
@@ -73,7 +73,7 @@ define void @test_replicating_store_x86_fp80_cost(i32 %n, ptr %dst) #0 {
; COST-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; COST-NEXT: [[TMP22:%.*]] = zext i32 [[IV]] to i64
; COST-NEXT: [[TMP23:%.*]] = getelementptr x86_fp80, ptr [[DST]], i64 [[TMP22]]
-; COST-NEXT: store x86_fp80 0xK00000000000000000000, ptr [[TMP23]], align 16
+; COST-NEXT: store x86_fp80 0.000000e+00, ptr [[TMP23]], align 16
; COST-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; COST-NEXT: [[EC:%.*]] = icmp ugt i32 [[IV]], [[N]]
; COST-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
@@ -103,8 +103,8 @@ define void @test_replicating_store_x86_fp80_cost(i32 %n, ptr %dst) #0 {
; FORCED-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP4]], i64 1
; FORCED-NEXT: [[TMP6:%.*]] = getelementptr x86_fp80, ptr [[DST]], i64 [[TMP5]]
; FORCED-NEXT: [[TMP8:%.*]] = getelementptr x86_fp80, ptr [[DST]], i64 [[TMP7]]
-; FORCED-NEXT: store x86_fp80 0xK00000000000000000000, ptr [[TMP6]], align 16
-; FORCED-NEXT: store x86_fp80 0xK00000000000000000000, ptr [[TMP8]], align 16
+; FORCED-NEXT: store x86_fp80 0.000000e+00, ptr [[TMP6]], align 16
+; FORCED-NEXT: store x86_fp80 0.000000e+00, ptr [[TMP8]], align 16
; FORCED-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
; FORCED-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], splat (i32 2)
; FORCED-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
diff --git a/llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll b/llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
index 631da7fe73b74..5c881560b8607 100644
--- a/llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
+++ b/llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
@@ -729,10 +729,10 @@ define void @irregular_type(ptr %a, i64 %n) {
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds x86_fp80, ptr [[A]], i64 [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds x86_fp80, ptr [[A]], i64 [[TMP5]]
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds x86_fp80, ptr [[A]], i64 [[TMP3]]
-; CHECK-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[TMP0]], align 16
-; CHECK-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[TMP2]], align 16
-; CHECK-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[TMP4]], align 16
-; CHECK-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[TMP6]], align 16
+; CHECK-NEXT: store x86_fp80 1.000000e+00, ptr [[TMP0]], align 16
+; CHECK-NEXT: store x86_fp80 1.000000e+00, ptr [[TMP2]], align 16
+; CHECK-NEXT: store x86_fp80 1.000000e+00, ptr [[TMP4]], align 16
+; CHECK-NEXT: store x86_fp80 1.000000e+00, ptr [[TMP6]], align 16
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 4
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
@@ -772,10 +772,10 @@ define void @irregular_type(ptr %a, i64 %n) {
; INTER-NEXT: [[TMP2:%.*]] = getelementptr inbounds x86_fp80, ptr [[A]], i64 [[TMP1]]
; INTER-NEXT: [[TMP4:%.*]] = getelementptr inbounds x86_fp80, ptr [[A]], i64 [[TMP5]]
; INTER-NEXT: [[TMP6:%.*]] = getelementptr inbounds x86_fp80, ptr [[A]], i64 [[TMP3]]
-; INTER-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[TMP0]], align 16
-; INTER-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[TMP2]], align 16
-; INTER-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[TMP4]], align 16
-; INTER-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[TMP6]], align 16
+; INTER-NEXT: store x86_fp80 1.000000e+00, ptr [[TMP0]], align 16
+; INTER-NEXT: store x86_fp80 1.000000e+00, ptr [[TMP2]], align 16
+; INTER-NEXT: store x86_fp80 1.000000e+00, ptr [[TMP4]], align 16
+; INTER-NEXT: store x86_fp80 1.000000e+00, ptr [[TMP6]], align 16
; INTER-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 4
; INTER-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; INTER-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
@@ -1172,10 +1172,10 @@ define void @pointer_iv_non_uniform_1(ptr %a, i64 %n) {
; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP3]]
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP4]]
; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP6]]
-; CHECK-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[NEXT_GEP]], align 16
-; CHECK-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[NEXT_GEP1]], align 16
-; CHECK-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[NEXT_GEP2]], align 16
-; CHECK-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[NEXT_GEP3]], align 16
+; CHECK-NEXT: store x86_fp80 1.000000e+00, ptr [[NEXT_GEP]], align 16
+; CHECK-NEXT: store x86_fp80 1.000000e+00, ptr [[NEXT_GEP1]], align 16
+; CHECK-NEXT: store x86_fp80 1.000000e+00, ptr [[NEXT_GEP2]], align 16
+; CHECK-NEXT: store x86_fp80 1.000000e+00, ptr [[NEXT_GEP3]], align 16
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
@@ -1220,10 +1220,10 @@ define void @pointer_iv_non_uniform_1(ptr %a, i64 %n) {
; INTER-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP3]]
; INTER-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP4]]
; INTER-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP6]]
-; INTER-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[NEXT_GEP]], align 16
-; INTER-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[NEXT_GEP1]], align 16
-; INTER-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[NEXT_GEP2]], align 16
-; INTER-NEXT: store x86_fp80 0xK3FFF8000000000000000, ptr [[NEXT_GEP3]], align 16
+; INTER-NEXT: store x86_fp80 1.000000e+00, ptr [[NEXT_GEP]], align 16
+; INTER-NEXT: store x86_fp80 1.000000e+00, ptr [[NEXT_GEP1]], align 16
+; INTER-NEXT: store x86_fp80 1.000000e+00, ptr [[NEXT_GEP2]], align 16
+; INTER-NEXT: store x86_fp80 1.000000e+00, ptr [[NEXT_GEP3]], align 16
; INTER-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; INTER-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; INTER-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
diff --git a/llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll b/llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
index 173fb59a12402..ed495b33e1fbd 100644
--- a/llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
+++ b/llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
@@ -105,7 +105,7 @@ define void @loop_contains_store_fcmp_condition(ptr dereferenceable(40) noalias
; CHECK-NEXT: store i16 [[INC]], ptr [[ST_ADDR]], align 2
; CHECK-NEXT: [[EE_ADDR:%.*]] = getelementptr inbounds nuw half, ptr [[PRED]], i64 [[IV]]
; CHECK-NEXT: [[EE_VAL:%.*]] = load half, ptr [[EE_ADDR]], align 2
-; CHECK-NEXT: [[EE_COND:%.*]] = fcmp ugt half [[EE_VAL]], 0xH5FD0
+; CHECK-NEXT: [[EE_COND:%.*]] = fcmp ugt half [[EE_VAL]], 5.000000e+02
; CHECK-NEXT: br i1 [[EE_COND]], label %[[EXIT:.*]], label %[[FOR_INC]]
; CHECK: [[FOR_INC]]:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/float-induction.ll b/llvm/test/Transforms/LoopVectorize/float-induction.ll
index cffe78ba0123a..09421aa2b2934 100644
--- a/llvm/test/Transforms/LoopVectorize/float-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/float-induction.ll
@@ -754,7 +754,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 2147483644
; VEC4_INTERL1-NEXT: [[DOTCAST:%.*]] = uitofp nneg i64 [[N_VEC]] to float
; VEC4_INTERL1-NEXT: [[TMP2:%.*]] = fmul fast float [[DOTCAST]], -5.000000e-01
-; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 0x3FB99999A0000000
+; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 1.000000e-01
; VEC4_INTERL1-NEXT: [[DOTCAST2:%.*]] = uitofp nneg i64 [[N_VEC]] to float
; VEC4_INTERL1-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[DOTCAST2]]
; VEC4_INTERL1-NEXT: [[IND_END3:%.*]] = fadd fast float [[INIT:%.*]], [[TMP3]]
@@ -772,7 +772,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC4_INTERL1-NEXT: br label [[VECTOR_BODY:%.*]]
; VEC4_INTERL1: vector.body:
; VEC4_INTERL1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; VEC4_INTERL1-NEXT: [[VEC_IND:%.*]] = phi <4 x float> [ <float 0x3FB99999A0000000, float 0xBFD99999A0000000, float 0xBFECCCCCC0000000, float 0xBFF6666660000000>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
+; VEC4_INTERL1-NEXT: [[VEC_IND:%.*]] = phi <4 x float> [ <float 1.000000e-01, float -4.000000e-01, float f0xBF666666, float -1.400000e+00>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; VEC4_INTERL1-NEXT: [[VEC_IND9:%.*]] = phi <4 x float> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT10:%.*]], [[VECTOR_BODY]] ]
; VEC4_INTERL1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8], ptr [[A:%.*]], i64 [[INDEX]]
; VEC4_INTERL1-NEXT: store <4 x float> [[VEC_IND9]], ptr [[TMP6]], align 4
@@ -793,7 +793,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC4_INTERL1-NEXT: br i1 [[CMP_N]], label [[FOR_END_LOOPEXIT:%.*]], label [[SCALAR_PH]]
; VEC4_INTERL1: scalar.ph:
; VEC4_INTERL1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_LR_PH]] ]
-; VEC4_INTERL1-NEXT: [[BC_RESUME_VAL1:%.*]] = phi float [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0x3FB99999A0000000, [[FOR_BODY_LR_PH]] ]
+; VEC4_INTERL1-NEXT: [[BC_RESUME_VAL1:%.*]] = phi float [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1.000000e-01, [[FOR_BODY_LR_PH]] ]
; VEC4_INTERL1-NEXT: [[BC_RESUME_VAL4:%.*]] = phi float [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ [[INIT]], [[FOR_BODY_LR_PH]] ]
; VEC4_INTERL1-NEXT: br label [[FOR_BODY:%.*]]
; VEC4_INTERL1: for.body:
@@ -833,7 +833,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC4_INTERL2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT2]], <4 x float> poison, <4 x i32> zeroinitializer
; VEC4_INTERL2-NEXT: [[DOTCAST:%.*]] = uitofp nneg i64 [[N_VEC]] to float
; VEC4_INTERL2-NEXT: [[TMP2:%.*]] = fmul fast float [[DOTCAST]], -5.000000e-01
-; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 0x3FB99999A0000000
+; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 1.000000e-01
; VEC4_INTERL2-NEXT: [[DOTCAST2:%.*]] = uitofp nneg i64 [[N_VEC]] to float
; VEC4_INTERL2-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[DOTCAST2]]
; VEC4_INTERL2-NEXT: [[IND_END3:%.*]] = fadd fast float [[INIT:%.*]], [[TMP3]]
@@ -847,7 +847,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC4_INTERL2-NEXT: br label [[VECTOR_BODY:%.*]]
; VEC4_INTERL2: vector.body:
; VEC4_INTERL2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; VEC4_INTERL2-NEXT: [[VEC_IND:%.*]] = phi <4 x float> [ <float 0x3FB99999A0000000, float 0xBFD99999A0000000, float 0xBFECCCCCC0000000, float 0xBFF6666660000000>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
+; VEC4_INTERL2-NEXT: [[VEC_IND:%.*]] = phi <4 x float> [ <float 1.000000e-01, float -4.000000e-01, float f0xBF666666, float -1.400000e+00>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; VEC4_INTERL2-NEXT: [[VEC_IND10:%.*]] = phi <4 x float> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT13:%.*]], [[VECTOR_BODY]] ]
; VEC4_INTERL2-NEXT: [[STEP_ADD11:%.*]] = fadd fast <4 x float> [[VEC_IND10]], [[DOTSPLAT5]]
; VEC4_INTERL2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8], ptr [[A:%.*]], i64 [[INDEX]]
@@ -878,7 +878,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC4_INTERL2-NEXT: br i1 [[CMP_N]], label [[FOR_END_LOOPEXIT:%.*]], label [[SCALAR_PH]]
; VEC4_INTERL2: scalar.ph:
; VEC4_INTERL2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_LR_PH]] ]
-; VEC4_INTERL2-NEXT: [[BC_RESUME_VAL1:%.*]] = phi float [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0x3FB99999A0000000, [[FOR_BODY_LR_PH]] ]
+; VEC4_INTERL2-NEXT: [[BC_RESUME_VAL1:%.*]] = phi float [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1.000000e-01, [[FOR_BODY_LR_PH]] ]
; VEC4_INTERL2-NEXT: [[BC_RESUME_VAL4:%.*]] = phi float [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ [[INIT]], [[FOR_BODY_LR_PH]] ]
; VEC4_INTERL2-NEXT: br label [[FOR_BODY:%.*]]
; VEC4_INTERL2: for.body:
@@ -916,7 +916,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 2147483646
; VEC1_INTERL2-NEXT: [[DOTCAST:%.*]] = uitofp nneg i64 [[N_VEC]] to float
; VEC1_INTERL2-NEXT: [[TMP2:%.*]] = fmul fast float [[DOTCAST]], -5.000000e-01
-; VEC1_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 0x3FB99999A0000000
+; VEC1_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 1.000000e-01
; VEC1_INTERL2-NEXT: [[DOTCAST2:%.*]] = uitofp nneg i64 [[N_VEC]] to float
; VEC1_INTERL2-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[DOTCAST2]]
; VEC1_INTERL2-NEXT: [[IND_END3:%.*]] = fadd fast float [[INIT:%.*]], [[TMP3]]
@@ -936,8 +936,8 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC1_INTERL2-NEXT: store float [[TMP7]], ptr [[TMP9]], align 4
; VEC1_INTERL2-NEXT: [[TMP10:%.*]] = fadd fast float [[OFFSET_IDX7]], [[TMP0]]
; VEC1_INTERL2-NEXT: [[TMP11:%.*]] = fadd fast float [[TMP7]], [[TMP0]]
-; VEC1_INTERL2-NEXT: [[TMP12:%.*]] = fadd fast float [[TMP5]], 0xBFD99999A0000000
-; VEC1_INTERL2-NEXT: [[TMP13:%.*]] = fadd fast float [[TMP5]], 0xBFECCCCCC0000000
+; VEC1_INTERL2-NEXT: [[TMP12:%.*]] = fadd fast float [[TMP5]], -4.000000e-01
+; VEC1_INTERL2-NEXT: [[TMP13:%.*]] = fadd fast float [[TMP5]], f0xBF666666
; VEC1_INTERL2-NEXT: [[TMP14:%.*]] = fadd fast float [[TMP12]], [[TMP10]]
; VEC1_INTERL2-NEXT: [[TMP15:%.*]] = fadd fast float [[TMP13]], [[TMP11]]
; VEC1_INTERL2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8], ptr [[B:%.*]], i64 [[INDEX]]
@@ -956,7 +956,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC1_INTERL2-NEXT: br i1 [[CMP_N]], label [[FOR_END_LOOPEXIT:%.*]], label [[SCALAR_PH]]
; VEC1_INTERL2: scalar.ph:
; VEC1_INTERL2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_LR_PH]] ]
-; VEC1_INTERL2-NEXT: [[BC_RESUME_VAL1:%.*]] = phi float [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0x3FB99999A0000000, [[FOR_BODY_LR_PH]] ]
+; VEC1_INTERL2-NEXT: [[BC_RESUME_VAL1:%.*]] = phi float [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1.000000e-01, [[FOR_BODY_LR_PH]] ]
; VEC1_INTERL2-NEXT: [[BC_RESUME_VAL4:%.*]] = phi float [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ [[INIT]], [[FOR_BODY_LR_PH]] ]
; VEC1_INTERL2-NEXT: br label [[FOR_BODY:%.*]]
; VEC1_INTERL2: for.body:
@@ -994,7 +994,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 2147483646
; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTCAST:%.*]] = uitofp nneg i64 [[N_VEC]] to float
; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP2:%.*]] = fmul fast float [[DOTCAST]], -5.000000e-01
-; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 0x3FB99999A0000000
+; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 1.000000e-01
; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTCAST2:%.*]] = uitofp nneg i64 [[N_VEC]] to float
; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[DOTCAST2]]
; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END3:%.*]] = fadd fast float [[INIT:%.*]], [[TMP3]]
@@ -1012,7 +1012,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC2_INTERL1_PRED_STORE-NEXT: br label [[VECTOR_BODY:%.*]]
; VEC2_INTERL1_PRED_STORE: vector.body:
; VEC2_INTERL1_PRED_STORE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; VEC2_INTERL1_PRED_STORE-NEXT: [[VEC_IND:%.*]] = phi <2 x float> [ <float 0x3FB99999A0000000, float 0xBFD99999A0000000>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
+; VEC2_INTERL1_PRED_STORE-NEXT: [[VEC_IND:%.*]] = phi <2 x float> [ <float 1.000000e-01, float -4.000000e-01>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
; VEC2_INTERL1_PRED_STORE-NEXT: [[VEC_IND9:%.*]] = phi <2 x float> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT10:%.*]], [[VECTOR_BODY]] ]
; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8], ptr [[A:%.*]], i64 [[INDEX]]
; VEC2_INTERL1_PRED_STORE-NEXT: store <2 x float> [[VEC_IND9]], ptr [[TMP6]], align 4
@@ -1033,7 +1033,7 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca
; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[CMP_N]], label [[FOR_END]], label [[FOR_BODY]]
; VEC2_INTERL1_PRED_STORE: for.body:
; VEC2_INTERL1_PRED_STORE-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_LR_PH]] ]
-; VEC2_INTERL1_PRED_STORE-NEXT: [[Y_012:%.*]] = phi float [ [[CONV1:%.*]], [[FOR_BODY]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0x3FB99999A0000000, [[FOR_BODY_LR_PH]] ]
+; VEC2_INTERL1_PRED_STORE-NEXT: [[Y_012:%.*]] = phi float [ [[CONV1:%.*]], [[FOR_BODY]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1.000000e-01, [[FOR_BODY_LR_PH]] ]
; VEC2_INTERL1_PRED_STORE-NEXT: [[X_011:%.*]] = phi float [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ [[INIT]], [[FOR_BODY_LR_PH]] ]
; VEC2_INTERL1_PRED_STORE-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i8], ptr [[A]], i64 [[INDVARS_IV]]
; VEC2_INTERL1_PRED_STORE-NEXT: store float [[X_011]], ptr [[ARRAYIDX]], align 4
diff --git a/llvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll b/llvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
index d3c109e412b35..dc969726284a7 100644
--- a/llvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
+++ b/llvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
@@ -171,7 +171,7 @@ define void @not_a_min_max() {
; CHECK: loop:
; CHECK-NEXT: [[F9_S0_V0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[T14:%.*]] = icmp eq i32 [[F9_S0_V0]], 5
-; CHECK-NEXT: [[T15:%.*]] = select reassoc nnan ninf nsz contract afn i1 [[T14]], float 0x36A0000000000000, float 0.000000e+00
+; CHECK-NEXT: [[T15:%.*]] = select reassoc nnan ninf nsz contract afn i1 [[T14]], float 1.401300e-45, float 0.000000e+00
; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[F9_S0_V0]], 1
; CHECK-NEXT: br i1 false, label [[END:%.*]], label [[LOOP]]
; CHECK: end:
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
index 3da5e6894247d..c8c30c727b667 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
@@ -169,7 +169,7 @@ define float @cond_cmp_sel(ptr noalias %a, ptr noalias %cond, i64 %N) {
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE6]]
; CHECK: pred.load.continue6:
; CHECK-NEXT: [[TMP24:%.*]] = phi <4 x float> [ [[TMP18]], [[PRED_LOAD_CONTINUE4]] ], [ [[TMP23]], [[PRED_LOAD_IF5]] ]
-; CHECK-NEXT: [[TMP25:%.*]] = select fast <4 x i1> [[TMP1]], <4 x float> [[TMP24]], <4 x float> splat (float 0x47EFFFFFE0000000)
+; CHECK-NEXT: [[TMP25:%.*]] = select fast <4 x i1> [[TMP1]], <4 x float> [[TMP24]], <4 x float> splat (float f0x7F7FFFFF)
; CHECK-NEXT: [[TMP26:%.*]] = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[TMP25]])
; CHECK-NEXT: [[RDX_MINMAX_SELECT]] = call fast float @llvm.minnum.f32(float [[TMP26]], float [[VEC_PHI]])
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll b/llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
index afcfb085bec36..6f021ab4ddd94 100644
--- a/llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
+++ b/llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
@@ -1099,7 +1099,7 @@ define i32 @multi_user_cmp_fmax(ptr readonly %a, i64 noundef %n) {
; CHECK-VF4-IC1-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-VF4-IC1-NEXT: [[ALL_0_OFF010:%.*]] = phi i1 [ true, [[ENTRY]] ], [ [[ALL_0_OFF0_:%.*]], [[FOR_BODY]] ]
; CHECK-VF4-IC1-NEXT: [[ANY_0_OFF09:%.*]] = phi i1 [ false, [[ENTRY]] ], [ [[DOTANY_0_OFF0:%.*]], [[FOR_BODY]] ]
-; CHECK-VF4-IC1-NEXT: [[MAX_015:%.*]] = phi float [ 0xFFF0000000000000, [[ENTRY]] ], [ [[DOTMAX_0:%.*]], [[FOR_BODY]] ]
+; CHECK-VF4-IC1-NEXT: [[MAX_015:%.*]] = phi float [ -inf, [[ENTRY]] ], [ [[DOTMAX_0:%.*]], [[FOR_BODY]] ]
; CHECK-VF4-IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDVARS_IV]]
; CHECK-VF4-IC1-NEXT: [[LOAD1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-VF4-IC1-NEXT: [[CMP1:%.*]] = fcmp ogt float [[LOAD1]], [[MAX_015]]
@@ -1124,7 +1124,7 @@ define i32 @multi_user_cmp_fmax(ptr readonly %a, i64 noundef %n) {
; CHECK-VF4-IC2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-VF4-IC2-NEXT: [[ALL_0_OFF010:%.*]] = phi i1 [ true, [[ENTRY]] ], [ [[ALL_0_OFF0_:%.*]], [[FOR_BODY]] ]
; CHECK-VF4-IC2-NEXT: [[ANY_0_OFF09:%.*]] = phi i1 [ false, [[ENTRY]] ], [ [[DOTANY_0_OFF0:%.*]], [[FOR_BODY]] ]
-; CHECK-VF4-IC2-NEXT: [[MAX_015:%.*]] = phi float [ 0xFFF0000000000000, [[ENTRY]] ], [ [[DOTMAX_0:%.*]], [[FOR_BODY]] ]
+; CHECK-VF4-IC2-NEXT: [[MAX_015:%.*]] = phi float [ -inf, [[ENTRY]] ], [ [[DOTMAX_0:%.*]], [[FOR_BODY]] ]
; CHECK-VF4-IC2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDVARS_IV]]
; CHECK-VF4-IC2-NEXT: [[LOAD1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-VF4-IC2-NEXT: [[CMP1:%.*]] = fcmp ogt float [[LOAD1]], [[MAX_015]]
@@ -1149,7 +1149,7 @@ define i32 @multi_user_cmp_fmax(ptr readonly %a, i64 noundef %n) {
; CHECK-VF1-IC2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-VF1-IC2-NEXT: [[ALL_0_OFF010:%.*]] = phi i1 [ true, [[ENTRY]] ], [ [[ALL_0_OFF0_:%.*]], [[FOR_BODY]] ]
; CHECK-VF1-IC2-NEXT: [[ANY_0_OFF09:%.*]] = phi i1 [ false, [[ENTRY]] ], [ [[DOTANY_0_OFF0:%.*]], [[FOR_BODY]] ]
-; CHECK-VF1-IC2-NEXT: [[MAX_015:%.*]] = phi float [ 0xFFF0000000000000, [[ENTRY]] ], [ [[DOTMAX_0:%.*]], [[FOR_BODY]] ]
+; CHECK-VF1-IC2-NEXT: [[MAX_015:%.*]] = phi float [ -inf, [[ENTRY]] ], [ [[DOTMAX_0:%.*]], [[FOR_BODY]] ]
; CHECK-VF1-IC2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDVARS_IV]]
; CHECK-VF1-IC2-NEXT: [[LOAD1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-VF1-IC2-NEXT: [[CMP1:%.*]] = fcmp ogt float [[LOAD1]], [[MAX_015]]
diff --git a/llvm/test/Transforms/LoopVectorize/select-first-index-fp.ll b/llvm/test/Transforms/LoopVectorize/select-first-index-fp.ll
index df9a15a5b422a..4ab5eaee6b749 100644
--- a/llvm/test/Transforms/LoopVectorize/select-first-index-fp.ll
+++ b/llvm/test/Transforms/LoopVectorize/select-first-index-fp.ll
@@ -11,7 +11,7 @@ define i64 @test_fmin_first_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ogt float [[MIN_VAL]], [[L]]
@@ -54,7 +54,7 @@ define i64 @test_fmin_first_idx_select_min(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ogt float [[MIN_VAL]], [[L]]
@@ -97,7 +97,7 @@ define i64 @test_fmin_first_idx_cond_flipped(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan olt float [[L]], [[MIN_VAL]]
@@ -140,7 +140,7 @@ define i64 @test_fmax_first_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan olt float [[MAX_VAL]], [[L]]
@@ -183,7 +183,7 @@ define i64 @test_fmax_first_idx_cond_flipped(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ogt float [[L]], [[MAX_VAL]]
@@ -227,7 +227,7 @@ define i64 @test_fmin_first_idx_non_canonical_iv(ptr %src) {
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[WIDE_IV:%.*]] = phi i64 [ 5, %[[ENTRY]] ], [ [[WIDE_IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 5, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[SRC]], i64 [[INDEX]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[TMP0]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ogt float [[MIN_VAL]], [[L]]
@@ -273,7 +273,7 @@ define i64 @test_fmin_first_idx_no_nnan(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[MIN_VAL]], [[L]]
@@ -316,7 +316,7 @@ define i64 @test_fmin_first_idx_double(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi double [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi double [ f0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr double, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load double, ptr [[GEP]], align 8
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ogt double [[MIN_VAL]], [[L]]
@@ -359,7 +359,7 @@ define i64 @test_fminimum_first_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ogt float [[MIN_VAL]], [[L]]
@@ -402,7 +402,7 @@ define i64 @test_fmaximumnum_first_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan olt float [[MAX_VAL]], [[L]]
@@ -445,7 +445,7 @@ define i64 @test_fminimumnum_first_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ogt float [[MIN_VAL]], [[L]]
@@ -488,7 +488,7 @@ define i64 @test_fmaximum_first_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan olt float [[MAX_VAL]], [[L]]
diff --git a/llvm/test/Transforms/LoopVectorize/select-last-index-fp.ll b/llvm/test/Transforms/LoopVectorize/select-last-index-fp.ll
index 4d232c707fba5..0ae2141178a0c 100644
--- a/llvm/test/Transforms/LoopVectorize/select-last-index-fp.ll
+++ b/llvm/test/Transforms/LoopVectorize/select-last-index-fp.ll
@@ -10,7 +10,7 @@ define i64 @test_fmax_last_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ole float [[MAX_VAL]], [[L]]
@@ -53,7 +53,7 @@ define i64 @test_fmax_last_idx_cond_flipped(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oge float [[L]], [[MAX_VAL]]
@@ -96,7 +96,7 @@ define i64 @test_fmin_last_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oge float [[MIN_VAL]], [[L]]
@@ -139,7 +139,7 @@ define i64 @test_fmin_last_idx_cond_flipped(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ole float [[L]], [[MIN_VAL]]
@@ -182,7 +182,7 @@ define i64 @test_fmax_last_idx_no_nnan(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[MAX_VAL]], [[L]]
@@ -225,7 +225,7 @@ define i64 @test_fmax_last_idx_double(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi double [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi double [ f0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr double, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load double, ptr [[GEP]], align 8
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ole double [[MAX_VAL]], [[L]]
@@ -268,7 +268,7 @@ define i64 @test_fmaximum_last_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ole float [[MAX_VAL]], [[L]]
@@ -311,7 +311,7 @@ define i64 @test_fminimumnum_last_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oge float [[MIN_VAL]], [[L]]
@@ -354,7 +354,7 @@ define i64 @test_fminimum_last_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ 0x47EFFFFFE0000000, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN_VAL:%.*]] = phi float [ f0x7F7FFFFF, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oge float [[MIN_VAL]], [[L]]
@@ -397,7 +397,7 @@ define i64 @test_fmaximumnum_last_idx(ptr %src, i64 %n) {
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MAX_IDX_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ 0xC7EFFFFFE0000000, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MAX_VAL:%.*]] = phi float [ f0xFF7FFFFF, %[[ENTRY]] ], [ [[MAX_VAL_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, ptr [[SRC]], i64 [[IV]]
; CHECK-NEXT: [[L:%.*]] = load float, ptr [[GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ole float [[MAX_VAL]], [[L]]
diff --git a/llvm/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll b/llvm/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll
index 66e109ae0bca9..52b5c427b6b17 100644
--- a/llvm/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll
+++ b/llvm/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll
@@ -10,9 +10,9 @@ target triple = "i386-pc-linux-gnu"
define internal fastcc void @initialize(ptr noalias nocapture sret(%0) %agg.result) nounwind {
; CHECK-LABEL: @initialize(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store x86_fp80 0xK00000000000000000000, ptr [[AGG_RESULT:%.*]], align 4
+; CHECK-NEXT: store x86_fp80 0.000000e+00, ptr [[AGG_RESULT:%.*]], align 4
; CHECK-NEXT: [[AGG_RESULT_15:%.*]] = getelementptr [[TMP0:%.*]], ptr [[AGG_RESULT]], i32 0, i32 1
-; CHECK-NEXT: store x86_fp80 0xK00000000000000000000, ptr [[AGG_RESULT_15]], align 4
+; CHECK-NEXT: store x86_fp80 0.000000e+00, ptr [[AGG_RESULT_15]], align 4
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/MemCpyOpt/memcpy-tbaa.ll b/llvm/test/Transforms/MemCpyOpt/memcpy-tbaa.ll
index 6e446e5ff267c..79cc12ebb4298 100644
--- a/llvm/test/Transforms/MemCpyOpt/memcpy-tbaa.ll
+++ b/llvm/test/Transforms/MemCpyOpt/memcpy-tbaa.ll
@@ -5,7 +5,7 @@ define void @test() local_unnamed_addr {
; CHECK-LABEL: define void @test() local_unnamed_addr {
; CHECK-NEXT: [[TEST_ARRAY_B:%.*]] = alloca [31 x float], align 4
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[TEST_ARRAY_B]], i64 1
-; CHECK-NEXT: store float 0x3E6AA51880000000, ptr [[TMP1]], align 4
+; CHECK-NEXT: store float f0x335528C4, ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[TEST_ARRAY_B]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[TMP2]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/MemCpyOpt/memcpy.ll b/llvm/test/Transforms/MemCpyOpt/memcpy.ll
index 571f5dc5fcfe9..937b3bf281034 100644
--- a/llvm/test/Transforms/MemCpyOpt/memcpy.ll
+++ b/llvm/test/Transforms/MemCpyOpt/memcpy.ll
@@ -25,7 +25,7 @@ define void @test1(ptr sret(%0) %agg.result, x86_fp80 %z.0, x86_fp80 %z.1) noun
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP2:%.*]] = alloca [[TMP0:%.*]], align 16
; CHECK-NEXT: [[MEMTMP:%.*]] = alloca [[TMP0]], align 16
-; CHECK-NEXT: [[TMP5:%.*]] = fsub x86_fp80 0xK80000000000000000000, [[Z_1:%.*]]
+; CHECK-NEXT: [[TMP5:%.*]] = fsub x86_fp80 -0.000000e+00, [[Z_1:%.*]]
; CHECK-NEXT: call void @ccoshl(ptr sret([[TMP0]]) [[TMP2]], x86_fp80 [[TMP5]], x86_fp80 [[Z_0:%.*]]) #[[ATTR2:[0-9]+]]
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 16 [[AGG_RESULT:%.*]], ptr align 16 [[TMP2]], i32 32, i1 false)
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/MemCpyOpt/sret.ll b/llvm/test/Transforms/MemCpyOpt/sret.ll
index 1d0f0934ec2da..64f27192ce20d 100644
--- a/llvm/test/Transforms/MemCpyOpt/sret.ll
+++ b/llvm/test/Transforms/MemCpyOpt/sret.ll
@@ -13,7 +13,7 @@ define void @ccosl(ptr noalias writable sret(%0) %agg.result, ptr byval(%0) alig
; CHECK-NEXT: [[MEMTMP:%.*]] = alloca [[TMP0]], align 16
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [[TMP0]], ptr [[Z:%.*]], i32 0, i32 1
; CHECK-NEXT: [[TMP2:%.*]] = load x86_fp80, ptr [[TMP1]], align 16
-; CHECK-NEXT: [[TMP3:%.*]] = fsub x86_fp80 0xK80000000000000000000, [[TMP2]]
+; CHECK-NEXT: [[TMP3:%.*]] = fsub x86_fp80 -0.000000e+00, [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr [[TMP0]], ptr [[IZ]], i32 0, i32 1
; CHECK-NEXT: [[TMP8:%.*]] = load x86_fp80, ptr [[Z]], align 16
; CHECK-NEXT: store x86_fp80 [[TMP3]], ptr [[IZ]], align 16
diff --git a/llvm/test/Transforms/OpenMP/parallel_region_merging.ll b/llvm/test/Transforms/OpenMP/parallel_region_merging.ll
index deeddce2e395a..6d3e5935d2e11 100644
--- a/llvm/test/Transforms/OpenMP/parallel_region_merging.ll
+++ b/llvm/test/Transforms/OpenMP/parallel_region_merging.ll
@@ -4973,7 +4973,7 @@ entry:
; CHECK2: omp_region.body:
; CHECK2-NEXT: br label [[SEQ_PAR_MERGED:%.*]]
; CHECK2: seq.par.merged:
-; CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP2]], 0x40091EB860000000
+; CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP2]], 3.140000e+00
; CHECK2-NEXT: store float [[ADD]], ptr [[LOADGEP_P]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split:
diff --git a/llvm/test/Transforms/OpenMP/spmdization_assumes.ll b/llvm/test/Transforms/OpenMP/spmdization_assumes.ll
index 8b6f9d3c7fb12..689b9af0cc3fe 100644
--- a/llvm/test/Transforms/OpenMP/spmdization_assumes.ll
+++ b/llvm/test/Transforms/OpenMP/spmdization_assumes.ll
@@ -40,7 +40,7 @@ define weak ptx_kernel void @__omp_offloading_fd02_404433c2_main_l5(ptr %dyn, pt
; CHECK-NEXT: ret void
; CHECK: [[USER_CODE_ENTRY]]:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr nonnull @[[GLOB1]]) #[[ATTR3]]
-; CHECK-NEXT: [[CALL_I:%.*]] = call double @__nv_sin(double 0x400921FB54442D18) #[[ATTR7:[0-9]+]]
+; CHECK-NEXT: [[CALL_I:%.*]] = call double @__nv_sin(double f0x400921FB54442D18) #[[ATTR7:[0-9]+]]
; CHECK-NEXT: br label %[[REGION_CHECK_TID:.*]]
; CHECK: [[REGION_CHECK_TID]]:
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
index 1e7799f301c1a..2b38cfe7f21bd 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
@@ -280,8 +280,8 @@ define i1 @cmp_lt_gt(double %a, double %b, double %c) {
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = fdiv <2 x double> [[TMP3]], [[TMP6]]
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x double> [[TMP7]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp ule <4 x double> [[TMP9]], <double 1.000000e+00, double 1.000000e+00, double 0x3EB0C6F7A0B5ED8D, double 0x3EB0C6F7A0B5ED8D>
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp uge <4 x double> [[TMP9]], <double 1.000000e+00, double 1.000000e+00, double 0x3EB0C6F7A0B5ED8D, double 0x3EB0C6F7A0B5ED8D>
+; CHECK-NEXT: [[TMP10:%.*]] = fcmp ule <4 x double> [[TMP9]], <double 1.000000e+00, double 1.000000e+00, double f0x3EB0C6F7A0B5ED8D, double f0x3EB0C6F7A0B5ED8D>
+; CHECK-NEXT: [[TMP11:%.*]] = fcmp uge <4 x double> [[TMP9]], <double 1.000000e+00, double 1.000000e+00, double f0x3EB0C6F7A0B5ED8D, double f0x3EB0C6F7A0B5ED8D>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i1> [[TMP10]], <4 x i1> [[TMP11]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i1> [[TMP11]], <4 x i1> poison, <4 x i32> <i32 poison, i32 poison, i32 3, i32 poison>
; CHECK-NEXT: [[FOLDEXTEXTBINOP:%.*]] = or <4 x i1> [[SHIFT]], [[TMP8]]
diff --git a/llvm/test/Transforms/PlaceSafepoints/libcall.ll b/llvm/test/Transforms/PlaceSafepoints/libcall.ll
index 6e26f924a5ba3..d7c09129f6c24 100644
--- a/llvm/test/Transforms/PlaceSafepoints/libcall.ll
+++ b/llvm/test/Transforms/PlaceSafepoints/libcall.ll
@@ -18,7 +18,7 @@ loop:
; CHECK: loop
; CHECK-NEXT: %x_loop = phi double [ %x, %entry ], [ %x_exp, %loop ]
; CHECK-NEXT: %x_exp = call double @ldexp(double %x_loop, i32 5)
-; CHECK-NEXT: %done = fcmp ogt double %x_exp, 1.5
+; CHECK-NEXT: %done = fcmp ogt double %x_exp, 1.500000e+00
; WITHLDEXPF-NEXT: call void @do_safepoint
; CHECK-NEXT: br
%x_loop = phi double [ %x, %entry ], [ %x_exp, %loop ]
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp.ll
index 8fef808f193a9..bc85a1fd7ff96 100644
--- a/llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp.ll
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp.ll
@@ -289,42 +289,42 @@ define void @test_vp_cmp_v8(<8 x i32> %i0, <8 x i32> %i1, <8 x float> %f0, <8 x
; ALL-CONVERT-NEXT: [[NSPLAT:%.+]] = shufflevector <4 x i32> [[NINS]], <4 x i32> poison, <4 x i32> zeroinitializer
; ALL-CONVERT-NEXT: [[EVLM:%.+]] = icmp ult <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[NSPLAT]]
; ALL-CONVERT-NEXT: [[NEWM:%.+]] = and <4 x i1> [[EVLM]], %m
-; ALL-CONVERT-NEXT: [[FMIN:%.+]] = select <4 x i1> [[NEWM]], <4 x float> %vf, <4 x float> splat (float 0x7FF8000000000000)
+; ALL-CONVERT-NEXT: [[FMIN:%.+]] = select <4 x i1> [[NEWM]], <4 x float> %vf, <4 x float> splat (float +qnan)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[FMIN]])
; ALL-CONVERT-NEXT: %{{.+}} = call float @llvm.minnum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMIN_NNAN:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0x7FF0000000000000)
+; ALL-CONVERT: [[FMIN_NNAN:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float +inf)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[FMIN_NNAN]])
; ALL-CONVERT-NEXT: %{{.+}} = call nnan float @llvm.minnum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMIN_NNAN_NINF:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0x47EFFFFFE0000000)
+; ALL-CONVERT: [[FMIN_NNAN_NINF:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float f0x7F7FFFFF)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[FMIN_NNAN_NINF]])
; ALL-CONVERT-NEXT: %{{.+}} = call nnan ninf float @llvm.minnum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMAX:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0xFFF8000000000000)
+; ALL-CONVERT: [[FMAX:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float -qnan)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[FMAX]])
; ALL-CONVERT-NEXT: %{{.+}} = call float @llvm.maxnum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMAX_NNAN:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0xFFF0000000000000)
+; ALL-CONVERT: [[FMAX_NNAN:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float -inf)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[FMAX_NNAN]])
; ALL-CONVERT-NEXT: %{{.+}} = call nnan float @llvm.maxnum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMAX_NNAN_NINF:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0xC7EFFFFFE0000000)
+; ALL-CONVERT: [[FMAX_NNAN_NINF:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float f0xFF7FFFFF)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[FMAX_NNAN_NINF]])
; ALL-CONVERT-NEXT: %{{.+}} = call nnan ninf float @llvm.maxnum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMINIMUM:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0x7FF0000000000000)
+; ALL-CONVERT: [[FMINIMUM:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float +inf)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> [[FMINIMUM]])
; ALL-CONVERT-NEXT: %{{.+}} = call float @llvm.minimum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMINIMUM_NNAN:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0x7FF0000000000000)
+; ALL-CONVERT: [[FMINIMUM_NNAN:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float +inf)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> [[FMINIMUM_NNAN]])
; ALL-CONVERT-NEXT: %{{.+}} = call nnan float @llvm.minimum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMINIMUM_NNAN_NINF:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0x47EFFFFFE0000000)
+; ALL-CONVERT: [[FMINIMUM_NNAN_NINF:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float f0x7F7FFFFF)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call nnan ninf float @llvm.vector.reduce.fminimum.v4f32(<4 x float> [[FMINIMUM_NNAN_NINF]])
; ALL-CONVERT-NEXT: %{{.+}} = call nnan ninf float @llvm.minimum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMAXIMUM:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0xFFF0000000000000)
+; ALL-CONVERT: [[FMAXIMUM:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float -inf)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> [[FMAXIMUM]])
; ALL-CONVERT-NEXT: %{{.+}} = call float @llvm.maximum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMAXIMUM_NNAN:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0xFFF0000000000000)
+; ALL-CONVERT: [[FMAXIMUM_NNAN:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float -inf)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call nnan float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> [[FMAXIMUM_NNAN]])
; ALL-CONVERT-NEXT: %{{.+}} = call nnan float @llvm.maximum.f32(float [[RED]], float %f)
-; ALL-CONVERT: [[FMAXIMUM_NNAN_NINF:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float 0xC7EFFFFFE0000000)
+; ALL-CONVERT: [[FMAXIMUM_NNAN_NINF:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> splat (float f0xFF7FFFFF)
; ALL-CONVERT-NEXT: [[RED:%.+]] = call nnan ninf float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> [[FMAXIMUM_NNAN_NINF]])
; ALL-CONVERT-NEXT: %{{.+}} = call nnan ninf float @llvm.maximum.f32(float [[RED]], float %f)
diff --git a/llvm/test/Transforms/Reassociate/pointer-collision-non-determinism.ll b/llvm/test/Transforms/Reassociate/pointer-collision-non-determinism.ll
index feb595dbe5b48..500006e2604e3 100644
--- a/llvm/test/Transforms/Reassociate/pointer-collision-non-determinism.ll
+++ b/llvm/test/Transforms/Reassociate/pointer-collision-non-determinism.ll
@@ -28,9 +28,9 @@
define float @test(float %arg) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP:%.*]] = fmul fast float [[ARG:%.*]], 0x3FE99999A0000000
+; CHECK-NEXT: [[TMP:%.*]] = fmul fast float [[ARG:%.*]], 8.000000e-01
; CHECK-NEXT: [[TMP110:%.*]] = fsub fast float 1.000000e+00, [[TMP]]
-; CHECK-NEXT: [[TMP2:%.*]] = fmul fast float [[ARG]], 0x3FE99999A0000000
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast float [[ARG]], 8.000000e-01
; CHECK-NEXT: [[TMP311:%.*]] = fsub fast float 1.000000e+00, [[TMP2]]
; CHECK-NEXT: [[REASS_MUL160:%.*]] = fmul fast float [[TMP110]], [[ARG]]
; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[REASS_MUL160]], [[TMP311]]
@@ -59,7 +59,7 @@ define float @test(float %arg) {
; CHECK-NEXT: [[TMP26:%.*]] = fmul fast float [[TMP25]], [[ARG]]
; CHECK-NEXT: [[TMP27:%.*]] = fadd fast float [[TMP26]], [[ARG]]
; CHECK-NEXT: [[TMP29:%.*]] = fmul fast float [[ARG]], [[ARG]]
-; CHECK-NEXT: [[TMP31:%.*]] = fmul fast float [[TMP29]], 0x3FEA2E8B80000000
+; CHECK-NEXT: [[TMP31:%.*]] = fmul fast float [[TMP29]], f0x3F51745C
; CHECK-NEXT: [[TMP33:%.*]] = fmul fast float [[TMP31]], [[TMP27]]
; CHECK-NEXT: [[TMP34:%.*]] = fadd fast float [[TMP33]], [[ARG]]
; CHECK-NEXT: ret float [[TMP34]]
diff --git a/llvm/test/Transforms/Reassociate/pr42349.ll b/llvm/test/Transforms/Reassociate/pr42349.ll
index 3bed0598a377c..7e357d0c46f4c 100644
--- a/llvm/test/Transforms/Reassociate/pr42349.ll
+++ b/llvm/test/Transforms/Reassociate/pr42349.ll
@@ -5,7 +5,7 @@ define float @wibble(float %tmp6) #0 {
; CHECK-LABEL: @wibble(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[TMP7:%.*]] = fmul float [[TMP6:%.*]], -1.000000e+00
-; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], 0xFFF0000000000000
+; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], -inf
; CHECK-NEXT: ret float [[TMP9]]
;
bb:
diff --git a/llvm/test/Transforms/Reassociate/reassoc-intermediate-fnegs.ll b/llvm/test/Transforms/Reassociate/reassoc-intermediate-fnegs.ll
index 9b2bbf2483f86..2757f68958132 100644
--- a/llvm/test/Transforms/Reassociate/reassoc-intermediate-fnegs.ll
+++ b/llvm/test/Transforms/Reassociate/reassoc-intermediate-fnegs.ll
@@ -6,8 +6,8 @@
define half @faddsubAssoc1(half %a, half %b) {
; CHECK-LABEL: @faddsubAssoc1(
-; CHECK-NEXT: [[T2_NEG:%.*]] = fmul fast half [[A:%.*]], 0xHC500
-; CHECK-NEXT: [[REASS_MUL:%.*]] = fmul fast half [[B:%.*]], 0xH4500
+; CHECK-NEXT: [[T2_NEG:%.*]] = fmul fast half [[A:%.*]], -5.000000e+00
+; CHECK-NEXT: [[REASS_MUL:%.*]] = fmul fast half [[B:%.*]], 5.000000e+00
; CHECK-NEXT: [[T5:%.*]] = fadd fast half [[REASS_MUL]], [[T2_NEG]]
; CHECK-NEXT: ret half [[T5]]
;
@@ -23,7 +23,7 @@ define half @faddsubAssoc1(half %a, half %b) {
define half @faddsubAssoc2(half %a, half %b) {
; CHECK-LABEL: @faddsubAssoc2(
-; CHECK-NEXT: [[T2:%.*]] = fmul fast half [[A:%.*]], 0xH4500
+; CHECK-NEXT: [[T2:%.*]] = fmul fast half [[A:%.*]], 5.000000e+00
; CHECK-NEXT: [[T5:%.*]] = fadd fast half [[B:%.*]], [[T2]]
; CHECK-NEXT: ret half [[T5]]
;
diff --git a/llvm/test/Transforms/SCCP/float-denormal-simplification.ll b/llvm/test/Transforms/SCCP/float-denormal-simplification.ll
index b99c4025490ac..d2fa795c311bb 100644
--- a/llvm/test/Transforms/SCCP/float-denormal-simplification.ll
+++ b/llvm/test/Transforms/SCCP/float-denormal-simplification.ll
@@ -3,7 +3,7 @@
define float @test_ieee() #0 {
; CHECK-LABEL: @test_ieee(
-; CHECK-NEXT: ret float 0x36F4000000000000
+; CHECK-NEXT: ret float 5.605190e-44
;
%1 = fmul float 2.802596928649634e-44, 2.000000e+00
ret float %1
diff --git a/llvm/test/Transforms/SCCP/float-nan-simplification.ll b/llvm/test/Transforms/SCCP/float-nan-simplification.ll
index 5a97518b8d137..1f86f9e58b634 100644
--- a/llvm/test/Transforms/SCCP/float-nan-simplification.ll
+++ b/llvm/test/Transforms/SCCP/float-nan-simplification.ll
@@ -15,9 +15,9 @@ define float @test1(float %a, i1 %bc) {
; CHECK: bb2:
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
-; CHECK-NEXT: [[P:%.*]] = phi float [ [[A:%.*]], [[BB1]] ], [ 0x7FF8000000000000, [[BB2]] ]
+; CHECK-NEXT: [[P:%.*]] = phi float [ [[A:%.*]], [[BB1]] ], [ +qnan, [[BB2]] ]
; CHECK-NEXT: [[V_1:%.*]] = fmul float [[P]], 0.000000e+00
-; CHECK-NEXT: [[V_2:%.*]] = fadd float [[V_1]], 0xFFF8000000000000
+; CHECK-NEXT: [[V_2:%.*]] = fadd float [[V_1]], -qnan
; CHECK-NEXT: ret float [[V_2]]
;
entry:
@@ -46,9 +46,9 @@ define float @test2(float %a, i1 %bc) {
; CHECK: bb2:
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
-; CHECK-NEXT: [[P:%.*]] = phi float [ 0x7FF8000000000000, [[BB1]] ], [ [[A:%.*]], [[BB2]] ]
+; CHECK-NEXT: [[P:%.*]] = phi float [ +qnan, [[BB1]] ], [ [[A:%.*]], [[BB2]] ]
; CHECK-NEXT: [[V_1:%.*]] = fmul float [[P]], 0.000000e+00
-; CHECK-NEXT: ret float 0xFFF8000000000000
+; CHECK-NEXT: ret float -qnan
;
entry:
br i1 %bc, label %bb1, label %bb2
diff --git a/llvm/test/Transforms/SCCP/loadtest.ll b/llvm/test/Transforms/SCCP/loadtest.ll
index 3cb11e96ee95b..16fb99346ac54 100644
--- a/llvm/test/Transforms/SCCP/loadtest.ll
+++ b/llvm/test/Transforms/SCCP/loadtest.ll
@@ -19,7 +19,7 @@ define i32 @test1() {
define float @test2() {
; CHECK-LABEL: @test2(
; CHECK-NEXT: #dbg_value(ptr getelementptr
-; CHECK-NEXT: #dbg_value(float 0x3FF3B2FEC0000000
+; CHECK-NEXT: #dbg_value(float 1.231200e+00
; CHECK-NEXT: ret
%A = getelementptr [2 x { i32, float }], ptr @Y, i64 0, i64 1, i32 1 ; <ptr> [#uses=1]
%B = load float, ptr %A ; <float> [#uses=1]
diff --git a/llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll b/llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll
index 78609ec8b0e51..2117a2ba6cc4a 100644
--- a/llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll
+++ b/llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll
@@ -5,7 +5,7 @@
define i1 @no_fold_fcmp_denormal_double_ieee_dynamic_denormal_undef() #0 {
; CHECK-LABEL: define i1 @no_fold_fcmp_denormal_double_ieee_dynamic_denormal_undef(
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double 0x8000000000000, undef
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double f0x0008000000000000, undef
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp une double 0x8000000000000, undef
@@ -15,7 +15,7 @@ define i1 @no_fold_fcmp_denormal_double_ieee_dynamic_denormal_undef() #0 {
define i1 @no_fold_fcmp_denormal_double_ieee_dynamic_denormal_poison() #0 {
; CHECK-LABEL: define i1 @no_fold_fcmp_denormal_double_ieee_dynamic_denormal_poison(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double 0x8000000000000, poison
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double f0x0008000000000000, poison
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp une double 0x8000000000000, poison
@@ -25,7 +25,7 @@ define i1 @no_fold_fcmp_denormal_double_ieee_dynamic_denormal_poison() #0 {
define i1 @no_fold_fcmp_denormal_double_ieee_dynamic() #0 {
; CHECK-LABEL: define i1 @no_fold_fcmp_denormal_double_ieee_dynamic(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une double 0x8000000000000, 0.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double f0x0008000000000000, 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%cmp = fcmp une double 0x8000000000000, 0.0
@@ -44,7 +44,7 @@ define i1 @fold_fcmp_nondenormal_double_ieee_dynamic() #0 {
define <2 x i1> @no_fold_fcmp_denormal_double_ieee_dynamic_vector_splat() #0 {
; CHECK-LABEL: define <2 x i1> @no_fold_fcmp_denormal_double_ieee_dynamic_vector_splat(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une <2 x double> splat (double 0x8000000000000), zeroinitializer
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une <2 x double> splat (double f0x0008000000000000), zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%cmp = fcmp une <2 x double> splat (double 0x8000000000000), zeroinitializer
@@ -90,7 +90,7 @@ define <2 x i1> @fold_fcmp_nondenormal_double_ieee_dynamic_zero() #0 {
define <2 x i1> @no_fold_fcmp_denormal_double_ieee_dynamic_vector_nonsplat() #0 {
; CHECK-LABEL: define <2 x i1> @no_fold_fcmp_denormal_double_ieee_dynamic_vector_nonsplat(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une <2 x double> <double 0x8000000000000, double 1.000000e+00>, zeroinitializer
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une <2 x double> <double f0x0008000000000000, double 1.000000e+00>, zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%cmp = fcmp une <2 x double> <double 0x8000000000000, double 1.0>, zeroinitializer
@@ -109,7 +109,7 @@ define <vscale x 2 x i1> @fold_fcmp_nondenormal_double_ieee_dynamic_scalable_vec
define <vscale x 2 x i1> @no_fold_fcmp_denormal_double_ieee_dynamic_scalable_vector_splat() #0 {
; CHECK-LABEL: define <vscale x 2 x i1> @no_fold_fcmp_denormal_double_ieee_dynamic_scalable_vector_splat(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une <vscale x 2 x double> splat (double 0x8000000000000), zeroinitializer
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une <vscale x 2 x double> splat (double f0x0008000000000000), zeroinitializer
; CHECK-NEXT: ret <vscale x 2 x i1> [[CMP]]
;
%cmp = fcmp une <vscale x 2 x double> splat (double 0x8000000000000), zeroinitializer
diff --git a/llvm/test/Transforms/SCCP/sitofp.ll b/llvm/test/Transforms/SCCP/sitofp.ll
index 24f04ae1fccb9..27749be4c0e88 100644
--- a/llvm/test/Transforms/SCCP/sitofp.ll
+++ b/llvm/test/Transforms/SCCP/sitofp.ll
@@ -14,7 +14,7 @@ define float @sitofp_and(i8 %x) {
define half @sitofp_const(i8 %x) {
; CHECK-LABEL: @sitofp_const(
-; CHECK-NEXT: ret half 0xH5140
+; CHECK-NEXT: ret half 4.200000e+01
;
%r = sitofp i8 42 to half
ret half %r
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-load-128.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-load-128.ll
index 3f02f974e59e6..a75264cb79bc1 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-load-128.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-load-128.ll
@@ -8,10 +8,10 @@ define void @gather_load_fp128(ptr %arg) #0 {
; CHECK-NEXT: [[LOAD1:%.*]] = load fp128, ptr [[GEP]], align 1
; CHECK-NEXT: [[LOAD2:%.*]] = load fp128, ptr null, align 1
; CHECK-NEXT: [[LOAD3:%.*]] = load fp128, ptr null, align 1
-; CHECK-NEXT: [[FCMP0:%.*]] = fcmp oeq fp128 [[LOAD0]], 0xL00000000000000000000000000000000
-; CHECK-NEXT: [[FCMP1:%.*]] = fcmp oeq fp128 [[LOAD1]], 0xL00000000000000000000000000000000
-; CHECK-NEXT: [[FCMP2:%.*]] = fcmp oeq fp128 [[LOAD2]], 0xL00000000000000000000000000000000
-; CHECK-NEXT: [[FCMP3:%.*]] = fcmp oeq fp128 [[LOAD3]], 0xL00000000000000000000000000000000
+; CHECK-NEXT: [[FCMP0:%.*]] = fcmp oeq fp128 [[LOAD0]], 0.000000e+00
+; CHECK-NEXT: [[FCMP1:%.*]] = fcmp oeq fp128 [[LOAD1]], 0.000000e+00
+; CHECK-NEXT: [[FCMP2:%.*]] = fcmp oeq fp128 [[LOAD2]], 0.000000e+00
+; CHECK-NEXT: [[FCMP3:%.*]] = fcmp oeq fp128 [[LOAD3]], 0.000000e+00
; CHECK-NEXT: ret void
;
%gep = getelementptr i8, ptr %arg, i64 16
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
index 0e3d79900d435..8d7d7b0f4e9e6 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
@@ -14,7 +14,7 @@ define half @reduce_fast_half2(<2 x half> %vec2) {
; FULLFP16-LABEL: define half @reduce_fast_half2(
; FULLFP16-SAME: <2 x half> [[VEC2:%.*]]) #[[ATTR0:[0-9]+]] {
; FULLFP16-NEXT: [[ENTRY:.*:]]
-; FULLFP16-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> [[VEC2]])
+; FULLFP16-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v2f16(half 0.000000e+00, <2 x half> [[VEC2]])
; FULLFP16-NEXT: ret half [[TMP0]]
;
entry:
@@ -44,7 +44,7 @@ define half @reduce_fast_half4(<4 x half> %vec4) {
; CHECK-LABEL: define half @reduce_fast_half4(
; CHECK-SAME: <4 x half> [[VEC4:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> [[VEC4]])
+; CHECK-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> [[VEC4]])
; CHECK-NEXT: ret half [[TMP0]]
;
entry:
@@ -89,13 +89,13 @@ define half @reduce_fast_half8(<8 x half> %vec8) {
; NOFP16-NEXT: [[TMP0:%.*]] = shufflevector <8 x half> [[VEC8]], <8 x half> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; NOFP16-NEXT: [[TMP2:%.*]] = shufflevector <8 x half> [[VEC8]], <8 x half> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; NOFP16-NEXT: [[RDX_OP:%.*]] = fadd fast <4 x half> [[TMP0]], [[TMP2]]
-; NOFP16-NEXT: [[OP_RDX3:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> [[RDX_OP]])
+; NOFP16-NEXT: [[OP_RDX3:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> [[RDX_OP]])
; NOFP16-NEXT: ret half [[OP_RDX3]]
;
; FULLFP16-LABEL: define half @reduce_fast_half8(
; FULLFP16-SAME: <8 x half> [[VEC8:%.*]]) #[[ATTR0]] {
; FULLFP16-NEXT: [[ENTRY:.*:]]
-; FULLFP16-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> [[VEC8]])
+; FULLFP16-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> [[VEC8]])
; FULLFP16-NEXT: ret half [[TMP0]]
;
entry:
@@ -161,7 +161,7 @@ define half @reduce_fast_half16(<16 x half> %vec16) {
; CHECK-LABEL: define half @reduce_fast_half16(
; CHECK-SAME: <16 x half> [[VEC16:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> [[VEC16]])
+; CHECK-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> [[VEC16]])
; CHECK-NEXT: ret half [[TMP0]]
;
entry:
@@ -781,7 +781,7 @@ define half @reduce_unordered_fast_half4(<4 x half> %vec4) {
; CHECK-LABEL: define half @reduce_unordered_fast_half4(
; CHECK-SAME: <4 x half> [[VEC4:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> [[VEC4]])
+; CHECK-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> [[VEC4]])
; CHECK-NEXT: ret half [[TMP0]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
index 26d61cb6bc28d..90ed713dbef8d 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
@@ -8,8 +8,8 @@ define amdgpu_kernel void @test_with_wmma( ptr addrspace(1) %input, ptr addrspac
; GCN-NEXT: [[IN0:%.*]] = load float, ptr addrspace(1) [[INPUT]], align 4
; GCN-NEXT: [[PTR1:%.*]] = getelementptr float, ptr addrspace(1) [[INPUT]], i64 1
; GCN-NEXT: [[IN1:%.*]] = load float, ptr addrspace(1) [[PTR1]], align 4
-; GCN-NEXT: [[MUL0:%.*]] = fmul contract float [[IN0]], 0x3FC0527DC0000000
-; GCN-NEXT: [[MUL1:%.*]] = fmul contract float [[IN1]], 0x3FC0527DC0000000
+; GCN-NEXT: [[MUL0:%.*]] = fmul contract float [[IN0]], f0x3E0293EE
+; GCN-NEXT: [[MUL1:%.*]] = fmul contract float [[IN1]], f0x3E0293EE
; GCN-NEXT: [[SUB0:%.*]] = fsub contract float [[MUL0]], [[SCALED_MAX]]
; GCN-NEXT: [[SUB1:%.*]] = fsub contract float [[MUL1]], [[SCALED_MAX]]
; GCN-NEXT: [[EXP0:%.*]] = tail call float @llvm.amdgcn.exp2.f32(float [[SUB0]])
@@ -69,8 +69,8 @@ define amdgpu_kernel void @test_amdgcn_exp_log(ptr addrspace(1) %input, ptr addr
; GCN-NEXT: [[SCALE0:%.*]] = load float, ptr addrspace(1) [[SCALES]], align 4
; GCN-NEXT: [[SPTR1:%.*]] = getelementptr float, ptr addrspace(1) [[SCALES]], i64 1
; GCN-NEXT: [[SCALE1:%.*]] = load float, ptr addrspace(1) [[SPTR1]], align 4
-; GCN-NEXT: [[MUL0:%.*]] = fmul contract float [[IN0]], 0x3FC0527DC0000000
-; GCN-NEXT: [[MUL1:%.*]] = fmul contract float [[IN1]], 0x3FC0527DC0000000
+; GCN-NEXT: [[MUL0:%.*]] = fmul contract float [[IN0]], f0x3E0293EE
+; GCN-NEXT: [[MUL1:%.*]] = fmul contract float [[IN1]], f0x3E0293EE
; GCN-NEXT: [[SUB0:%.*]] = fsub contract float [[MUL0]], [[SCALE0]]
; GCN-NEXT: [[SUB1:%.*]] = fsub contract float [[MUL1]], [[SCALE1]]
; GCN-NEXT: [[EXP0:%.*]] = tail call float @llvm.amdgcn.exp2.f32(float [[SUB0]])
@@ -111,8 +111,8 @@ define amdgpu_kernel void @test_amdgcn_exp_f16(ptr addrspace(1) %input, ptr addr
; GCN-NEXT: [[SCALE0:%.*]] = load half, ptr addrspace(1) [[SCALES]], align 2
; GCN-NEXT: [[SPTR1:%.*]] = getelementptr half, ptr addrspace(1) [[SCALES]], i64 1
; GCN-NEXT: [[SCALE1:%.*]] = load half, ptr addrspace(1) [[SPTR1]], align 2
-; GCN-NEXT: [[MUL0:%.*]] = fmul contract half [[IN0]], 0xH3E14
-; GCN-NEXT: [[MUL1:%.*]] = fmul contract half [[IN1]], 0xH3E14
+; GCN-NEXT: [[MUL0:%.*]] = fmul contract half [[IN0]], 1.519530e+00
+; GCN-NEXT: [[MUL1:%.*]] = fmul contract half [[IN1]], 1.519530e+00
; GCN-NEXT: [[SUB0:%.*]] = fsub contract half [[MUL0]], [[SCALE0]]
; GCN-NEXT: [[SUB1:%.*]] = fsub contract half [[MUL1]], [[SCALE1]]
; GCN-NEXT: [[EXP0:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB0]])
@@ -149,8 +149,8 @@ define amdgpu_kernel void @kernel_f16(ptr addrspace(1) %input, ptr addrspace(1)
; GCN-NEXT: [[SCALE0:%.*]] = load half, ptr addrspace(1) [[SCALES]], align 2
; GCN-NEXT: [[SPTR1:%.*]] = getelementptr half, ptr addrspace(1) [[SCALES]], i64 1
; GCN-NEXT: [[SCALE1:%.*]] = load half, ptr addrspace(1) [[SPTR1]], align 2
-; GCN-NEXT: [[MUL0:%.*]] = fmul contract half [[IN0]], 0xH3E14
-; GCN-NEXT: [[MUL1:%.*]] = fmul contract half [[IN1]], 0xH3E14
+; GCN-NEXT: [[MUL0:%.*]] = fmul contract half [[IN0]], 1.519530e+00
+; GCN-NEXT: [[MUL1:%.*]] = fmul contract half [[IN1]], 1.519530e+00
; GCN-NEXT: [[SUB0:%.*]] = fsub contract half [[MUL0]], [[SCALE0]]
; GCN-NEXT: [[SUB1:%.*]] = fsub contract half [[MUL1]], [[SCALE1]]
; GCN-NEXT: [[EXP0:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB0]])
@@ -191,8 +191,8 @@ define amdgpu_kernel void @look_through_reuse_shuffle(
; GCN-NEXT: [[IN1:%.*]] = load half, ptr addrspace(1) [[IPTR1]], align 2
; GCN-NEXT: [[S0:%.*]] = load half, ptr addrspace(1) [[SCALES]], align 2
; GCN-NEXT: [[S1:%.*]] = load half, ptr addrspace(1) [[SPTR1]], align 2
-; GCN-NEXT: [[ADD0:%.*]] = fadd contract half [[IN0]], 0xH3E14
-; GCN-NEXT: [[ADD1:%.*]] = fadd contract half [[IN1]], 0xH3E14
+; GCN-NEXT: [[ADD0:%.*]] = fadd contract half [[IN0]], 1.519530e+00
+; GCN-NEXT: [[ADD1:%.*]] = fadd contract half [[IN1]], 1.519530e+00
; GCN-NEXT: [[MUL0:%.*]] = fmul contract half [[ADD0]], [[S0]]
; GCN-NEXT: [[MUL1:%.*]] = fmul contract half [[ADD1]], [[S1]]
; GCN-NEXT: [[EXP0:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[MUL0]])
@@ -251,10 +251,10 @@ define amdgpu_kernel void @wider_exp2_f32(ptr addrspace(1) %input, ptr addrspace
; GCN-NEXT: [[SCALE2:%.*]] = load float, ptr addrspace(1) [[SPTR2]], align 4
; GCN-NEXT: [[SPTR3:%.*]] = getelementptr float, ptr addrspace(1) [[SCALES]], i64 3
; GCN-NEXT: [[SCALE3:%.*]] = load float, ptr addrspace(1) [[SPTR3]], align 4
-; GCN-NEXT: [[MUL0:%.*]] = fmul contract float [[IN0]], 0x3FC0527DC0000000
-; GCN-NEXT: [[MUL1:%.*]] = fmul contract float [[IN1]], 0x3FC0527DC0000000
-; GCN-NEXT: [[MUL2:%.*]] = fmul contract float [[IN2]], 0x3FC0527DC0000000
-; GCN-NEXT: [[MUL3:%.*]] = fmul contract float [[IN3]], 0x3FC0527DC0000000
+; GCN-NEXT: [[MUL0:%.*]] = fmul contract float [[IN0]], f0x3E0293EE
+; GCN-NEXT: [[MUL1:%.*]] = fmul contract float [[IN1]], f0x3E0293EE
+; GCN-NEXT: [[MUL2:%.*]] = fmul contract float [[IN2]], f0x3E0293EE
+; GCN-NEXT: [[MUL3:%.*]] = fmul contract float [[IN3]], f0x3E0293EE
; GCN-NEXT: [[SUB0:%.*]] = fsub contract float [[MUL0]], [[SCALE0]]
; GCN-NEXT: [[SUB1:%.*]] = fsub contract float [[MUL1]], [[SCALE1]]
; GCN-NEXT: [[SUB2:%.*]] = fsub contract float [[MUL2]], [[SCALE2]]
@@ -327,10 +327,10 @@ define amdgpu_kernel void @wider_exp2_half(ptr addrspace(1) %input, ptr addrspac
; GCN-NEXT: [[SCALE2:%.*]] = load half, ptr addrspace(1) [[SPTR2]], align 2
; GCN-NEXT: [[SPTR3:%.*]] = getelementptr half, ptr addrspace(1) [[SCALES]], i64 3
; GCN-NEXT: [[SCALE3:%.*]] = load half, ptr addrspace(1) [[SPTR3]], align 2
-; GCN-NEXT: [[MUL0:%.*]] = fmul contract half [[IN0]], 0xH3E14
-; GCN-NEXT: [[MUL1:%.*]] = fmul contract half [[IN1]], 0xH3E14
-; GCN-NEXT: [[MUL2:%.*]] = fmul contract half [[IN2]], 0xH3E14
-; GCN-NEXT: [[MUL3:%.*]] = fmul contract half [[IN3]], 0xH3E14
+; GCN-NEXT: [[MUL0:%.*]] = fmul contract half [[IN0]], 1.519530e+00
+; GCN-NEXT: [[MUL1:%.*]] = fmul contract half [[IN1]], 1.519530e+00
+; GCN-NEXT: [[MUL2:%.*]] = fmul contract half [[IN2]], 1.519530e+00
+; GCN-NEXT: [[MUL3:%.*]] = fmul contract half [[IN3]], 1.519530e+00
; GCN-NEXT: [[SUB0:%.*]] = fsub contract half [[MUL0]], [[SCALE0]]
; GCN-NEXT: [[SUB1:%.*]] = fsub contract half [[MUL1]], [[SCALE1]]
; GCN-NEXT: [[SUB2:%.*]] = fsub contract half [[MUL2]], [[SCALE2]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
index 126d195314772..f89a9b6287dae 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
@@ -5,7 +5,7 @@
define half @reduction_half4(<4 x half> %a) {
; GFX9-LABEL: @reduction_half4(
; GFX9-NEXT: entry:
-; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> [[A:%.*]])
+; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> [[A:%.*]])
; GFX9-NEXT: ret half [[TMP0]]
;
; VI-LABEL: @reduction_half4(
@@ -35,7 +35,7 @@ entry:
define half @reduction_half8(<8 x half> %vec8) {
; GFX9-LABEL: @reduction_half8(
; GFX9-NEXT: entry:
-; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> [[VEC8:%.*]])
+; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v8f16(half 0.000000e+00, <8 x half> [[VEC8:%.*]])
; GFX9-NEXT: ret half [[TMP0]]
;
; VI-LABEL: @reduction_half8(
@@ -81,7 +81,7 @@ entry:
define half @reduction_half16(<16 x half> %vec16) {
; GFX9-LABEL: @reduction_half16(
; GFX9-NEXT: entry:
-; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> [[VEC16:%.*]])
+; GFX9-NEXT: [[TMP0:%.*]] = call fast half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> [[VEC16:%.*]])
; GFX9-NEXT: ret half [[TMP0]]
;
; VI-LABEL: @reduction_half16(
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
index ccccd5383c456..e6384bec97398 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
@@ -14,7 +14,7 @@ define void @fadd_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = fadd <2 x half> [[TMP0]], splat (half 0xH3C00)
+; GCN-NEXT: [[TMP1:%.*]] = fadd <2 x half> [[TMP0]], splat (half 1.000000e+00)
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
@@ -42,7 +42,7 @@ define void @fsub_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = fsub <2 x half> [[TMP0]], splat (half 0xH3C00)
+; GCN-NEXT: [[TMP1:%.*]] = fsub <2 x half> [[TMP0]], splat (half 1.000000e+00)
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
@@ -70,7 +70,7 @@ define void @fmul_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = fmul <2 x half> [[TMP0]], splat (half 0xH3C00)
+; GCN-NEXT: [[TMP1:%.*]] = fmul <2 x half> [[TMP0]], splat (half 1.000000e+00)
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
@@ -97,7 +97,7 @@ define void @fdiv_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = fdiv <2 x half> [[TMP0]], splat (half 0xH3C00)
+; GCN-NEXT: [[TMP1:%.*]] = fdiv <2 x half> [[TMP0]], splat (half 1.000000e+00)
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
@@ -124,7 +124,7 @@ define void @frem_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = frem <2 x half> [[TMP0]], splat (half 0xH3C00)
+; GCN-NEXT: [[TMP1:%.*]] = frem <2 x half> [[TMP0]], splat (half 1.000000e+00)
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
@@ -152,7 +152,7 @@ define amdgpu_kernel void @fma_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00), <2 x half> splat (half 0xH3C00))
+; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 1.000000e+00), <2 x half> splat (half 1.000000e+00))
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
@@ -180,7 +180,7 @@ define amdgpu_kernel void @fmuladd_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fmuladd.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00), <2 x half> splat (half 0xH3C00))
+; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fmuladd.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 1.000000e+00), <2 x half> splat (half 1.000000e+00))
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
@@ -208,12 +208,12 @@ define void @minnum_combine_v2f16(ptr addrspace(1) %arg) {
; GFX8-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GFX8-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GFX8-NEXT: [[ITMP3:%.*]] = load half, ptr addrspace(1) [[ITMP2]], align 2
-; GFX8-NEXT: [[ITMP4:%.*]] = call half @llvm.minnum.f16(half [[ITMP3]], half 0xH3C00)
+; GFX8-NEXT: [[ITMP4:%.*]] = call half @llvm.minnum.f16(half [[ITMP3]], half 1.000000e+00)
; GFX8-NEXT: store half [[ITMP4]], ptr addrspace(1) [[ITMP2]], align 2
; GFX8-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1
; GFX8-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]
; GFX8-NEXT: [[ITMP7:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2
-; GFX8-NEXT: [[ITMP8:%.*]] = call half @llvm.minnum.f16(half [[ITMP7]], half 0xH3C00)
+; GFX8-NEXT: [[ITMP8:%.*]] = call half @llvm.minnum.f16(half [[ITMP7]], half 1.000000e+00)
; GFX8-NEXT: store half [[ITMP8]], ptr addrspace(1) [[ITMP6]], align 2
; GFX8-NEXT: ret void
;
@@ -224,7 +224,7 @@ define void @minnum_combine_v2f16(ptr addrspace(1) %arg) {
; GFX9-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GFX9-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GFX9-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GFX9-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.minnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00))
+; GFX9-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.minnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 1.000000e+00))
; GFX9-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GFX9-NEXT: ret void
;
@@ -252,12 +252,12 @@ define void @maxnum_combine_v2f16(ptr addrspace(1) %arg) {
; GFX8-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GFX8-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GFX8-NEXT: [[ITMP3:%.*]] = load half, ptr addrspace(1) [[ITMP2]], align 2
-; GFX8-NEXT: [[ITMP4:%.*]] = call half @llvm.maxnum.f16(half [[ITMP3]], half 0xH3C00)
+; GFX8-NEXT: [[ITMP4:%.*]] = call half @llvm.maxnum.f16(half [[ITMP3]], half 1.000000e+00)
; GFX8-NEXT: store half [[ITMP4]], ptr addrspace(1) [[ITMP2]], align 2
; GFX8-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1
; GFX8-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]
; GFX8-NEXT: [[ITMP7:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2
-; GFX8-NEXT: [[ITMP8:%.*]] = call half @llvm.maxnum.f16(half [[ITMP7]], half 0xH3C00)
+; GFX8-NEXT: [[ITMP8:%.*]] = call half @llvm.maxnum.f16(half [[ITMP7]], half 1.000000e+00)
; GFX8-NEXT: store half [[ITMP8]], ptr addrspace(1) [[ITMP6]], align 2
; GFX8-NEXT: ret void
;
@@ -268,7 +268,7 @@ define void @maxnum_combine_v2f16(ptr addrspace(1) %arg) {
; GFX9-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GFX9-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GFX9-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GFX9-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.maxnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00))
+; GFX9-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.maxnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 1.000000e+00))
; GFX9-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GFX9-NEXT: ret void
;
@@ -296,12 +296,12 @@ define void @minimum_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[ITMP3:%.*]] = load half, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[ITMP4:%.*]] = call half @llvm.minimum.f16(half [[ITMP3]], half 0xH3C00)
+; GCN-NEXT: [[ITMP4:%.*]] = call half @llvm.minimum.f16(half [[ITMP3]], half 1.000000e+00)
; GCN-NEXT: store half [[ITMP4]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1
; GCN-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]
; GCN-NEXT: [[ITMP7:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2
-; GCN-NEXT: [[ITMP8:%.*]] = call half @llvm.minimum.f16(half [[ITMP7]], half 0xH3C00)
+; GCN-NEXT: [[ITMP8:%.*]] = call half @llvm.minimum.f16(half [[ITMP7]], half 1.000000e+00)
; GCN-NEXT: store half [[ITMP8]], ptr addrspace(1) [[ITMP6]], align 2
; GCN-NEXT: ret void
;
@@ -328,12 +328,12 @@ define void @maximum_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[ITMP3:%.*]] = load half, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[ITMP4:%.*]] = call half @llvm.maximum.f16(half [[ITMP3]], half 0xH3C00)
+; GCN-NEXT: [[ITMP4:%.*]] = call half @llvm.maximum.f16(half [[ITMP3]], half 1.000000e+00)
; GCN-NEXT: store half [[ITMP4]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1
; GCN-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]
; GCN-NEXT: [[ITMP7:%.*]] = load half, ptr addrspace(1) [[ITMP6]], align 2
-; GCN-NEXT: [[ITMP8:%.*]] = call half @llvm.maximum.f16(half [[ITMP7]], half 0xH3C00)
+; GCN-NEXT: [[ITMP8:%.*]] = call half @llvm.maximum.f16(half [[ITMP7]], half 1.000000e+00)
; GCN-NEXT: store half [[ITMP8]], ptr addrspace(1) [[ITMP6]], align 2
; GCN-NEXT: ret void
;
@@ -605,7 +605,7 @@ define void @minimumnum_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00))
+; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 1.000000e+00))
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
@@ -633,7 +633,7 @@ define void @maximumnum_combine_v2f16(ptr addrspace(1) %arg) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 0xH3C00))
+; GCN-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> [[TMP0]], <2 x half> splat (half 1.000000e+00))
; GCN-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ITMP2]], align 2
; GCN-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll b/llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll
index 3fafc07d65e8b..65638df56f75c 100644
--- a/llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll
+++ b/llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll
@@ -13,8 +13,8 @@ define void @fusion(ptr noalias nocapture align 256 dereferenceable(19267584) %a
; VECTOR-NEXT: [[TMP5:%.*]] = getelementptr inbounds half, ptr [[ARG1:%.*]], i64 [[TMP4]]
; VECTOR-NEXT: [[TMP6:%.*]] = getelementptr inbounds half, ptr [[ARG:%.*]], i64 [[TMP4]]
; VECTOR-NEXT: [[TMP7:%.*]] = load <2 x half>, ptr [[TMP5]], align 8
-; VECTOR-NEXT: [[TMP8:%.*]] = fmul fast <2 x half> [[TMP7]], splat (half 0xH5380)
-; VECTOR-NEXT: [[TMP9:%.*]] = fadd fast <2 x half> [[TMP8]], splat (half 0xH57F0)
+; VECTOR-NEXT: [[TMP8:%.*]] = fmul fast <2 x half> [[TMP7]], splat (half 6.000000e+01)
+; VECTOR-NEXT: [[TMP9:%.*]] = fadd fast <2 x half> [[TMP8]], splat (half 1.270000e+02)
; VECTOR-NEXT: store <2 x half> [[TMP9]], ptr [[TMP6]], align 8
; VECTOR-NEXT: ret void
;
@@ -26,14 +26,14 @@ define void @fusion(ptr noalias nocapture align 256 dereferenceable(19267584) %a
; NOVECTOR-NEXT: [[TMP10:%.*]] = or disjoint i64 [[TMP4]], 1
; NOVECTOR-NEXT: [[TMP5:%.*]] = getelementptr inbounds half, ptr [[ARG1:%.*]], i64 [[TMP4]]
; NOVECTOR-NEXT: [[TMP7:%.*]] = load half, ptr [[TMP5]], align 8
-; NOVECTOR-NEXT: [[TMP8:%.*]] = fmul fast half [[TMP7]], 0xH5380
-; NOVECTOR-NEXT: [[TMP9:%.*]] = fadd fast half [[TMP8]], 0xH57F0
+; NOVECTOR-NEXT: [[TMP8:%.*]] = fmul fast half [[TMP7]], 6.000000e+01
+; NOVECTOR-NEXT: [[TMP9:%.*]] = fadd fast half [[TMP8]], 1.270000e+02
; NOVECTOR-NEXT: [[TMP6:%.*]] = getelementptr inbounds half, ptr [[ARG:%.*]], i64 [[TMP4]]
; NOVECTOR-NEXT: store half [[TMP9]], ptr [[TMP6]], align 8
; NOVECTOR-NEXT: [[TMP11:%.*]] = getelementptr inbounds half, ptr [[ARG1]], i64 [[TMP10]]
; NOVECTOR-NEXT: [[TMP12:%.*]] = load half, ptr [[TMP11]], align 2
-; NOVECTOR-NEXT: [[TMP18:%.*]] = fmul fast half [[TMP12]], 0xH5380
-; NOVECTOR-NEXT: [[TMP19:%.*]] = fadd fast half [[TMP18]], 0xH57F0
+; NOVECTOR-NEXT: [[TMP18:%.*]] = fmul fast half [[TMP12]], 6.000000e+01
+; NOVECTOR-NEXT: [[TMP19:%.*]] = fadd fast half [[TMP18]], 1.270000e+02
; NOVECTOR-NEXT: [[TMP15:%.*]] = getelementptr inbounds half, ptr [[ARG]], i64 [[TMP10]]
; NOVECTOR-NEXT: store half [[TMP19]], ptr [[TMP15]], align 2
; NOVECTOR-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
index ee0ca6fe14418..d71e4f8f5906e 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
@@ -1229,7 +1229,7 @@ define half @fadd_4xf16(ptr %p) {
;
; ZVFH-LABEL: @fadd_4xf16(
; ZVFH-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr [[P:%.*]], align 2
-; ZVFH-NEXT: [[TMP2:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> [[TMP1]])
+; ZVFH-NEXT: [[TMP2:%.*]] = call fast half @llvm.vector.reduce.fadd.v4f16(half 0.000000e+00, <4 x half> [[TMP1]])
; ZVFH-NEXT: ret half [[TMP2]]
;
%x0 = load half, ptr %p
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
index e13dfce8c29f3..ed937dd9fc250 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
@@ -229,7 +229,7 @@ define i32 @test5() {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_END47:%.*]]
; CHECK: for.end47:
-; CHECK-NEXT: [[TMP0:%.*]] = phi <8 x double> [ <double 0x7FF8000000000000, double 0x7FF8000000000000, double 0.000000e+00, double 0.000000e+00, double 0x7FF8000000000000, double 0x7FF8000000000000, double 0.000000e+00, double 0.000000e+00>, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = phi <8 x double> [ <double +qnan, double +qnan, double 0.000000e+00, double 0.000000e+00, double +qnan, double +qnan, double 0.000000e+00, double 0.000000e+00>, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 0
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll
index f8522bc546e6b..519f38a8c9718 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll
@@ -4,9 +4,9 @@
define void @b() {
; CHECK-LABEL: @b(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float 0x7FF8000000000000, i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> <float 0xFFF8000000000000, float 0xFFF8000000000000, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 0x7FF8000000000000, i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float +qnan, i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> <float -qnan, float -qnan, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float +qnan, i32 3
; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP2]], <4 x float> zeroinitializer, <4 x float> zeroinitializer)
; CHECK-NEXT: [[TMP4:%.*]] = fmul <4 x float> [[TMP3]], <float undef, float undef, float undef, float 2.000000e+00>
; CHECK-NEXT: [[TMP5:%.*]] = fdiv <4 x float> [[TMP4]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll b/llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
index 694199f1f7b95..bbd4cfd057a0f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
@@ -69,8 +69,8 @@ define i32 @ray_sphere(ptr nocapture noundef readonly %sph, ptr nocapture nounde
; SSE2-NEXT: [[TMP34:%.*]] = fdiv double [[ADD]], [[MUL88]]
; SSE2-NEXT: [[SUB90:%.*]] = fsub double [[FNEG87]], [[CALL]]
; SSE2-NEXT: [[TMP35:%.*]] = fdiv double [[SUB90]], [[MUL88]]
-; SSE2-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP34]], 0x3EB0C6F7A0B5ED8D
-; SSE2-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP35]], 0x3EB0C6F7A0B5ED8D
+; SSE2-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP34]], f0x3EB0C6F7A0B5ED8D
+; SSE2-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP35]], f0x3EB0C6F7A0B5ED8D
; SSE2-NEXT: [[OR_COND:%.*]] = select i1 [[CMP93]], i1 [[CMP94]], i1 false
; SSE2-NEXT: br i1 [[OR_COND]], label [[CLEANUP]], label [[LOR_LHS_FALSE:%.*]]
; SSE2: lor.lhs.false:
@@ -143,8 +143,8 @@ define i32 @ray_sphere(ptr nocapture noundef readonly %sph, ptr nocapture nounde
; AVX-NEXT: [[TMP31:%.*]] = fdiv double [[ADD]], [[MUL88]]
; AVX-NEXT: [[SUB90:%.*]] = fsub double [[FNEG87]], [[CALL]]
; AVX-NEXT: [[TMP32:%.*]] = fdiv double [[SUB90]], [[MUL88]]
-; AVX-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP31]], 0x3EB0C6F7A0B5ED8D
-; AVX-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP32]], 0x3EB0C6F7A0B5ED8D
+; AVX-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP31]], f0x3EB0C6F7A0B5ED8D
+; AVX-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP32]], f0x3EB0C6F7A0B5ED8D
; AVX-NEXT: [[OR_COND:%.*]] = select i1 [[CMP93]], i1 [[CMP94]], i1 false
; AVX-NEXT: br i1 [[OR_COND]], label [[CLEANUP]], label [[LOR_LHS_FALSE:%.*]]
; AVX: lor.lhs.false:
@@ -217,8 +217,8 @@ define i32 @ray_sphere(ptr nocapture noundef readonly %sph, ptr nocapture nounde
; AVX2-NEXT: [[TMP31:%.*]] = fdiv double [[ADD]], [[MUL88]]
; AVX2-NEXT: [[SUB90:%.*]] = fsub double [[FNEG87]], [[CALL]]
; AVX2-NEXT: [[TMP32:%.*]] = fdiv double [[SUB90]], [[MUL88]]
-; AVX2-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP31]], 0x3EB0C6F7A0B5ED8D
-; AVX2-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP32]], 0x3EB0C6F7A0B5ED8D
+; AVX2-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP31]], f0x3EB0C6F7A0B5ED8D
+; AVX2-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP32]], f0x3EB0C6F7A0B5ED8D
; AVX2-NEXT: [[OR_COND:%.*]] = select i1 [[CMP93]], i1 [[CMP94]], i1 false
; AVX2-NEXT: br i1 [[OR_COND]], label [[CLEANUP]], label [[LOR_LHS_FALSE:%.*]]
; AVX2: lor.lhs.false:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp-values-non-full-registers.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp-values-non-full-registers.ll
index 35b49944541b2..a5ca1026aa669 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/cmp-values-non-full-registers.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp-values-non-full-registers.ll
@@ -6,10 +6,10 @@ define void @test() {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br i1 false, label %[[BB1:.*]], label %[[BB2:.*]]
; CHECK: [[BB2]]:
-; CHECK-NEXT: [[CMP14_US:%.*]] = fcmp ogt x86_fp80 0xK00000000000000000000, 0xK00000000000000000000
+; CHECK-NEXT: [[CMP14_US:%.*]] = fcmp ogt x86_fp80 0.000000e+00, 0.000000e+00
; CHECK-NEXT: [[IMAX_2_US:%.*]] = select i1 [[CMP14_US]], i64 0, i64 0
; CHECK-NEXT: [[JMAX_2_US:%.*]] = select i1 [[CMP14_US]], i64 0, i64 0
-; CHECK-NEXT: [[CMP13_US:%.*]] = fcmp olt x86_fp80 0xK00000000000000000000, 0xK00000000000000000000
+; CHECK-NEXT: [[CMP13_US:%.*]] = fcmp olt x86_fp80 0.000000e+00, 0.000000e+00
; CHECK-NEXT: [[IMIN_2_US:%.*]] = select i1 [[CMP13_US]], i64 0, i64 0
; CHECK-NEXT: [[JMIN_2_US:%.*]] = select i1 [[CMP13_US]], i64 0, i64 0
; CHECK-NEXT: br label %[[BB1]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
index def73d7ffeabb..8cd493c542b15 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
@@ -24,7 +24,7 @@ define void @_ZN11HullLibrary15CleanupVerticesEjPK9btVector3jRjPS0_fRS0_(ptr %ve
; CHECK: for.body233:
; CHECK-NEXT: br i1 [[ARG]], label [[FOR_BODY233]], label [[FOR_END271]]
; CHECK: for.end271:
-; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x float> [ splat (float 0x47EFFFFFE0000000), [[FOR_END227]] ], [ undef, [[FOR_BODY233]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x float> [ splat (float f0x7F7FFFFF), [[FOR_END227]] ], [ undef, [[FOR_BODY233]] ]
; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x float> undef, [[TMP0]]
; CHECK-NEXT: br i1 [[ARG]], label [[IF_THEN291:%.*]], label [[RETURN]]
; CHECK: if.then291:
@@ -41,7 +41,7 @@ define void @_ZN11HullLibrary15CleanupVerticesEjPK9btVector3jRjPS0_fRS0_(ptr %ve
; CHECK: if.then329:
; CHECK-NEXT: br label [[IF_END332]]
; CHECK: if.end332:
-; CHECK-NEXT: [[TMP4:%.*]] = phi <2 x float> [ [[TMP6]], [[IF_THEN329]] ], [ [[TMP6]], [[IF_END327]] ], [ splat (float 0x3F847AE140000000), [[IF_THEN291]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = phi <2 x float> [ [[TMP6]], [[IF_THEN329]] ], [ [[TMP6]], [[IF_END327]] ], [ splat (float f0x3C23D70A), [[IF_THEN291]] ]
; CHECK-NEXT: [[TMP5:%.*]] = fsub <2 x float> [[TMP3]], [[TMP4]]
; CHECK-NEXT: store <2 x float> [[TMP5]], ptr [[VERTICES:%.*]], align 4
; CHECK-NEXT: br label [[RETURN]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
index c1cc3f2dfc9e5..aa936a4cff8d3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
@@ -24,8 +24,8 @@ define void @main(i1 %arg) {
; CHECK: cond.true48.us:
; CHECK-NEXT: br i1 [[ARG]], label [[COND_TRUE63_US:%.*]], label [[COND_FALSE66_US:%.*]]
; CHECK: cond.false66.us:
-; CHECK-NEXT: store <2 x double> <double 0x404900049667B5F2, double 0x404E0515D587DA7B>, ptr undef, align 8
-; CHECK-NEXT: store <2 x double> <double 2.000000e-07, double 0x3F91A436DC4B6CE6>, ptr [[AGG_TMP101211_SROA_0_0_IDX]], align 8
+; CHECK-NEXT: store <2 x double> <double f0x404900049667B5F2, double f0x404E0515D587DA7B>, ptr undef, align 8
+; CHECK-NEXT: store <2 x double> <double 2.000000e-07, double f0x3F91A436DC4B6CE6>, ptr [[AGG_TMP101211_SROA_0_0_IDX]], align 8
; CHECK-NEXT: ret void
; CHECK: cond.true63.us:
; CHECK-NEXT: unreachable
@@ -93,7 +93,7 @@ define void @test(i1 %arg) {
; CHECK-NEXT: br i1 [[ARG:%.*]], label [[IF_THEN78:%.*]], label [[IF_THEN38:%.*]]
; CHECK: if.then38:
; CHECK-NEXT: [[AGG_TMP74663_SROA_0_0_IDX:%.*]] = getelementptr inbounds [[STRUCT_RAY:%.*]], ptr undef, i64 0, i32 1, i32 0
-; CHECK-NEXT: store <2 x double> <double 0x3FFA356C1D8A7F76, double 0x3FFDC4F38B38BEF4>, ptr [[AGG_TMP74663_SROA_0_0_IDX]], align 8
+; CHECK-NEXT: store <2 x double> <double f0x3FFA356C1D8A7F76, double f0x3FFDC4F38B38BEF4>, ptr [[AGG_TMP74663_SROA_0_0_IDX]], align 8
; CHECK-NEXT: br label [[IF_THEN78]]
; CHECK: if.then78:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll b/llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll
index 1f02be057194c..5c2e22eace0d2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll
@@ -7,7 +7,7 @@ define double @test(ptr %0, double %1) {
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = tail call double @llvm.exp.f64(double 0x7FF8000000000000)
+; CHECK-NEXT: [[TMP6:%.*]] = tail call double @llvm.exp.f64(double +qnan)
; CHECK-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP7]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll b/llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll
index 155b1ce27ac9d..c945dc7f2c043 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll
@@ -18,7 +18,7 @@ define void @test(ptr %nExp, float %0, i1 %cmp, float %1) {
; CHECK-NEXT: [[TMP6:%.*]] = phi float [ [[TMP1]], %[[IF_THEN]] ], [ [[TMP0]], %[[ENTRY]] ]
; CHECK-NEXT: [[TMP7:%.*]] = phi float [ 0.000000e+00, %[[IF_THEN]] ], [ [[TMP1]], %[[ENTRY]] ]
; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x float> [ [[TMP9]], %[[IF_THEN]] ], [ zeroinitializer, %[[ENTRY]] ]
-; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x float> [ zeroinitializer, %[[IF_THEN]] ], [ <float 0x7FF8000000000000, float 1.000000e+00>, %[[ENTRY]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x float> [ zeroinitializer, %[[IF_THEN]] ], [ <float +qnan, float 1.000000e+00>, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP15:%.*]] = phi <2 x float> [ [[TMP5]], %[[IF_THEN]] ], [ zeroinitializer, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x float> [[TMP14]], <2 x float> <float poison, float 0.000000e+00>, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP18:%.*]] = fmul <2 x float> [[TMP15]], [[TMP13]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll b/llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
index f7bba85a8c485..ef0a7fa6a3812 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
@@ -14,7 +14,7 @@ define void @vectorize_fp128(fp128 %c, fp128 %d) #0 {
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x fp128> poison, fp128 [[C:%.*]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x fp128> [[TMP0]], fp128 [[D:%.*]], i32 1
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x fp128> @llvm.fabs.v2f128(<2 x fp128> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp oeq <2 x fp128> [[TMP2]], splat (fp128 0xL00000000000000007FFF000000000000)
+; CHECK-NEXT: [[TMP3:%.*]] = fcmp oeq <2 x fp128> [[TMP2]], splat (fp128 +inf)
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1
; CHECK-NEXT: [[OR_COND39:%.*]] = or i1 [[TMP4]], [[TMP5]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
index 990803870ec23..ce11457bfecde 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
@@ -473,15 +473,15 @@ define void @foo(ptr nocapture readonly %arg_A, i32 %arg_B, ptr nocapture %array
; CHECK-NEXT: [[J_098:%.*]] = phi i32 [ 0, [[FOR_BODY16_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY16]] ]
; CHECK-NEXT: [[W3_097:%.*]] = phi float [ [[TMP7]], [[FOR_BODY16_LR_PH]] ], [ [[W2_096]], [[FOR_BODY16]] ]
; CHECK-NEXT: [[W2_096]] = phi float [ [[TMP5]], [[FOR_BODY16_LR_PH]] ], [ [[SUB28]], [[FOR_BODY16]] ]
-; CHECK-NEXT: [[MUL17:%.*]] = fmul fast float [[W0_0100]], 0x3FF19999A0000000
-; CHECK-NEXT: [[MUL18_NEG:%.*]] = fmul fast float [[W1_099]], 0xBFF3333340000000
+; CHECK-NEXT: [[MUL17:%.*]] = fmul fast float [[W0_0100]], 1.100000e+00
+; CHECK-NEXT: [[MUL18_NEG:%.*]] = fmul fast float [[W1_099]], -1.200000e+00
; CHECK-NEXT: [[SUB92:%.*]] = fadd fast float [[MUL17]], [[MUL18_NEG]]
; CHECK-NEXT: [[SUB19]] = fadd fast float [[SUB92]], [[TMP8]]
-; CHECK-NEXT: [[MUL20:%.*]] = fmul fast float [[SUB19]], 0x4000CCCCC0000000
-; CHECK-NEXT: [[MUL21_NEG:%.*]] = fmul fast float [[W0_0100]], 0xC0019999A0000000
-; CHECK-NEXT: [[MUL23:%.*]] = fmul fast float [[W1_099]], 0x4002666660000000
-; CHECK-NEXT: [[MUL25:%.*]] = fmul fast float [[W2_096]], 0x4008CCCCC0000000
-; CHECK-NEXT: [[MUL27_NEG:%.*]] = fmul fast float [[W3_097]], 0xC0099999A0000000
+; CHECK-NEXT: [[MUL20:%.*]] = fmul fast float [[SUB19]], 2.100000e+00
+; CHECK-NEXT: [[MUL21_NEG:%.*]] = fmul fast float [[W0_0100]], -2.200000e+00
+; CHECK-NEXT: [[MUL23:%.*]] = fmul fast float [[W1_099]], 2.300000e+00
+; CHECK-NEXT: [[MUL25:%.*]] = fmul fast float [[W2_096]], 3.100000e+00
+; CHECK-NEXT: [[MUL27_NEG:%.*]] = fmul fast float [[W3_097]], -3.200000e+00
; CHECK-NEXT: [[ADD2293:%.*]] = fadd fast float [[MUL27_NEG]], [[MUL25]]
; CHECK-NEXT: [[ADD24:%.*]] = fadd fast float [[ADD2293]], [[MUL23]]
; CHECK-NEXT: [[SUB2694:%.*]] = fadd fast float [[ADD24]], [[MUL21_NEG]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
index 4a2c1eacb0643..1d75d84f2f22b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
@@ -91,8 +91,8 @@ define i1 @fcmp_lt_gt(double %a, double %b, double %c) {
; CHECK-NEXT: [[TMP8:%.*]] = fdiv double [[ADD]], [[MUL]]
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[FNEG]], [[C]]
; CHECK-NEXT: [[TMP9:%.*]] = fdiv double [[SUB]], [[MUL]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[TMP8]], 0x3EB0C6F7A0B5ED8D
-; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt double [[TMP9]], 0x3EB0C6F7A0B5ED8D
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[TMP8]], f0x3EB0C6F7A0B5ED8D
+; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt double [[TMP9]], f0x3EB0C6F7A0B5ED8D
; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP4]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[CLEANUP:%.*]], label [[LOR_LHS_FALSE:%.*]]
; CHECK: lor.lhs.false:
@@ -133,8 +133,8 @@ define i1 @fcmp_lt(double %a, double %b, double %c) {
; CHECK-NEXT: [[DIV:%.*]] = fdiv double [[ADD]], [[MUL]]
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[FNEG]], [[C]]
; CHECK-NEXT: [[DIV3:%.*]] = fdiv double [[SUB]], [[MUL]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp uge double [[DIV]], 0x3EB0C6F7A0B5ED8D
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp uge double [[DIV3]], 0x3EB0C6F7A0B5ED8D
+; CHECK-NEXT: [[TMP11:%.*]] = fcmp uge double [[DIV]], f0x3EB0C6F7A0B5ED8D
+; CHECK-NEXT: [[TMP10:%.*]] = fcmp uge double [[DIV3]], f0x3EB0C6F7A0B5ED8D
; CHECK-NEXT: [[NOT_OR_COND:%.*]] = or i1 [[TMP10]], [[TMP11]]
; CHECK-NEXT: ret i1 [[NOT_OR_COND]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll
index f6bf138944749..80d0c40ee422e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll
@@ -26,7 +26,7 @@ define void @test(double %0) {
; CHECK: [[BB14]]:
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <6 x double> [[TMP12]], <6 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <4 x double> [[TMP14]], <4 x double> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <6 x double> [[TMP15]], <6 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000, double undef, double undef, double undef, double undef>, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 6, i32 7>
+; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <6 x double> [[TMP15]], <6 x double> <double +qnan, double +qnan, double undef, double undef, double undef, double undef>, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 6, i32 7>
; CHECK-NEXT: br i1 false, label %[[BB18:.*]], [[DOT_CRIT_EDGE]]
; CHECK: [[BB18]]:
; CHECK-NEXT: [[TMP18:%.*]] = insertelement <6 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double poison, double 0.000000e+00, double 0.000000e+00>, double [[TMP0]], i32 3
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll b/llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll
index 88a0ba59fa633..e26b716122079 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll
@@ -6,7 +6,7 @@ define void @stackrestore1(ptr %out) {
; CHECK-LABEL: @stackrestore1(
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[LOCAL_ALLOCA:%.*]] = alloca [16 x i8], align 4
-; CHECK-NEXT: store <4 x float> splat (float 0x3FF3333340000000), ptr [[LOCAL_ALLOCA]], align 4
+; CHECK-NEXT: store <4 x float> splat (float 1.200000e+00), ptr [[LOCAL_ALLOCA]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[LOCAL_ALLOCA]], align 4
; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/catchswitch.ll b/llvm/test/Transforms/SLPVectorizer/catchswitch.ll
index 2cd555fa9373b..19f253eec70f2 100644
--- a/llvm/test/Transforms/SLPVectorizer/catchswitch.ll
+++ b/llvm/test/Transforms/SLPVectorizer/catchswitch.ll
@@ -27,16 +27,16 @@ define void @important_func() personality ptr @__CxxFrameHandler3 {
; CHECK-NEXT: [[TMP0:%.*]] = cleanuppad within none []
; CHECK-NEXT: unreachable
; CHECK: labelE:
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0xFFF0000000000000>, i64 1
-; CHECK-NEXT: [[F:%.*]] = extractelement <4 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0xFFF0000000000000>, i64 2
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> <float +inf, float +inf, float +inf, float -inf>, i64 1
+; CHECK-NEXT: [[F:%.*]] = extractelement <4 x float> <float +inf, float +inf, float +inf, float -inf>, i64 2
; CHECK-NEXT: invoke void @funcA()
; CHECK-NEXT: to label [[LABELG:%.*]] unwind label [[CATCH_DISPATCH:%.*]]
; CHECK: labelF:
; CHECK-NEXT: [[TMP2:%.*]] = cleanuppad within none []
; CHECK-NEXT: cleanupret from [[TMP2]] unwind to caller
; CHECK: labelG:
-; CHECK-NEXT: [[G:%.*]] = extractelement <4 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0xFFF0000000000000>, i64 0
-; CHECK-NEXT: [[H:%.*]] = extractelement <4 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0xFFF0000000000000>, i64 3
+; CHECK-NEXT: [[G:%.*]] = extractelement <4 x float> <float +inf, float +inf, float +inf, float -inf>, i64 0
+; CHECK-NEXT: [[H:%.*]] = extractelement <4 x float> <float +inf, float +inf, float +inf, float -inf>, i64 3
; CHECK-NEXT: invoke void @funcA()
; CHECK-NEXT: to label [[LABELH:%.*]] unwind label [[CATCH_DISPATCH]]
; CHECK: labelH:
diff --git a/llvm/test/Transforms/SROA/ppcf128-no-fold.ll b/llvm/test/Transforms/SROA/ppcf128-no-fold.ll
index f5804ee3557a0..bb00ec125be7b 100644
--- a/llvm/test/Transforms/SROA/ppcf128-no-fold.ll
+++ b/llvm/test/Transforms/SROA/ppcf128-no-fold.ll
@@ -10,9 +10,9 @@ declare void @bar(ptr, [2 x i128])
define void @foo(ptr %v) #0 {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast ppc_fp128 0xM403B0000000000000000000000000000 to i128
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast ppc_fp128 2.700000e+01 to i128
; CHECK-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [2 x i128] poison, i128 [[TMP0]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast ppc_fp128 0xM4093B400000000000000000000000000 to i128
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast ppc_fp128 1.261000e+03 to i128
; CHECK-NEXT: [[DOTFCA_1_INSERT:%.*]] = insertvalue [2 x i128] [[DOTFCA_0_INSERT]], i128 [[TMP1]], 1
; CHECK-NEXT: call void @bar(ptr [[V:%.*]], [2 x i128] [[DOTFCA_1_INSERT]])
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SROA/select-load.ll b/llvm/test/Transforms/SROA/select-load.ll
index 359ecaa09111f..0a7a6d5e5ed4b 100644
--- a/llvm/test/Transforms/SROA/select-load.ll
+++ b/llvm/test/Transforms/SROA/select-load.ll
@@ -9,12 +9,12 @@
define <2 x i16> @test_load_bitcast_select(i1 %cond1, i1 %cond2) {
; CHECK-LABEL: @test_load_bitcast_select(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast half 0xHFFFF to i16
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast half 0xH0000 to i16
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast half -nan(0x1FF) to i16
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast half 0.000000e+00 to i16
; CHECK-NEXT: [[LD1_SROA_SPECULATED:%.*]] = select i1 [[COND1:%.*]], i16 [[TMP0]], i16 [[TMP1]]
; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x i16> poison, i16 [[LD1_SROA_SPECULATED]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast half 0xHFFFF to i16
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast half 0xH0000 to i16
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast half -nan(0x1FF) to i16
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast half 0.000000e+00 to i16
; CHECK-NEXT: [[LD2_SROA_SPECULATED:%.*]] = select i1 [[COND2:%.*]], i16 [[TMP2]], i16 [[TMP3]]
; CHECK-NEXT: [[V2:%.*]] = insertelement <2 x i16> [[V1]], i16 [[LD2_SROA_SPECULATED]], i32 1
; CHECK-NEXT: ret <2 x i16> [[V2]]
diff --git a/llvm/test/Transforms/SROA/vector-promotion.ll b/llvm/test/Transforms/SROA/vector-promotion.ll
index 0a5e741d10bec..7fcb49c299b2e 100644
--- a/llvm/test/Transforms/SROA/vector-promotion.ll
+++ b/llvm/test/Transforms/SROA/vector-promotion.ll
@@ -483,9 +483,9 @@ define <4 x float> @test_subvec_memset() {
; CHECK-LABEL: @test_subvec_memset(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_0_VECBLEND:%.*]] = shufflevector <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[A_4_VECBLEND:%.*]] = shufflevector <4 x float> <float undef, float 0x3820202020000000, float 0x3820202020000000, float undef>, <4 x float> [[A_0_VECBLEND]], <4 x i32> <i32 4, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[A_8_VECBLEND:%.*]] = shufflevector <4 x float> <float undef, float undef, float 0x3860606060000000, float 0x3860606060000000>, <4 x float> [[A_4_VECBLEND]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
-; CHECK-NEXT: [[A_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[A_8_VECBLEND]], float 0x38E0E0E0E0000000, i32 3
+; CHECK-NEXT: [[A_4_VECBLEND:%.*]] = shufflevector <4 x float> <float undef, float f0x01010101, float f0x01010101, float undef>, <4 x float> [[A_0_VECBLEND]], <4 x i32> <i32 4, i32 1, i32 2, i32 7>
+; CHECK-NEXT: [[A_8_VECBLEND:%.*]] = shufflevector <4 x float> <float undef, float undef, float f0x03030303, float f0x03030303>, <4 x float> [[A_4_VECBLEND]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+; CHECK-NEXT: [[A_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[A_8_VECBLEND]], float f0x07070707, i32 3
; CHECK-NEXT: ret <4 x float> [[A_12_VEC_INSERT]]
;
; DEBUG-LABEL: @test_subvec_memset(
@@ -493,11 +493,11 @@ define <4 x float> @test_subvec_memset() {
; DEBUG-NEXT: #dbg_value(ptr poison, [[META215:![0-9]+]], !DIExpression(), [[META220:![0-9]+]])
; DEBUG-NEXT: [[A_0_VECBLEND:%.*]] = shufflevector <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 7>, !dbg [[DBG221:![0-9]+]]
; DEBUG-NEXT: #dbg_value(ptr undef, [[META216:![0-9]+]], !DIExpression(), [[META222:![0-9]+]])
-; DEBUG-NEXT: [[A_4_VECBLEND:%.*]] = shufflevector <4 x float> <float undef, float 0x3820202020000000, float 0x3820202020000000, float undef>, <4 x float> [[A_0_VECBLEND]], <4 x i32> <i32 4, i32 1, i32 2, i32 7>, !dbg [[DBG223:![0-9]+]]
+; DEBUG-NEXT: [[A_4_VECBLEND:%.*]] = shufflevector <4 x float> <float undef, float f0x01010101, float f0x01010101, float undef>, <4 x float> [[A_0_VECBLEND]], <4 x i32> <i32 4, i32 1, i32 2, i32 7>, !dbg [[DBG223:![0-9]+]]
; DEBUG-NEXT: #dbg_value(ptr undef, [[META217:![0-9]+]], !DIExpression(), [[META224:![0-9]+]])
-; DEBUG-NEXT: [[A_8_VECBLEND:%.*]] = shufflevector <4 x float> <float undef, float undef, float 0x3860606060000000, float 0x3860606060000000>, <4 x float> [[A_4_VECBLEND]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>, !dbg [[DBG225:![0-9]+]]
+; DEBUG-NEXT: [[A_8_VECBLEND:%.*]] = shufflevector <4 x float> <float undef, float undef, float f0x03030303, float f0x03030303>, <4 x float> [[A_4_VECBLEND]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>, !dbg [[DBG225:![0-9]+]]
; DEBUG-NEXT: #dbg_value(ptr undef, [[META218:![0-9]+]], !DIExpression(), [[META226:![0-9]+]])
-; DEBUG-NEXT: [[A_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[A_8_VECBLEND]], float 0x38E0E0E0E0000000, i32 3, !dbg [[DBG227:![0-9]+]]
+; DEBUG-NEXT: [[A_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[A_8_VECBLEND]], float f0x07070707, i32 3, !dbg [[DBG227:![0-9]+]]
; DEBUG-NEXT: #dbg_value(<4 x float> [[A_12_VEC_INSERT]], [[META219:![0-9]+]], !DIExpression(), [[META228:![0-9]+]])
; DEBUG-NEXT: ret <4 x float> [[A_12_VEC_INSERT]], !dbg [[DBG229:![0-9]+]]
;
diff --git a/llvm/test/Transforms/Scalarizer/min-bits.ll b/llvm/test/Transforms/Scalarizer/min-bits.ll
index ca174f1a61e7a..d4340dd88e17f 100644
--- a/llvm/test/Transforms/Scalarizer/min-bits.ll
+++ b/llvm/test/Transforms/Scalarizer/min-bits.ll
@@ -931,8 +931,8 @@ define void @phi_v2f16(ptr %base, i64 %bound) {
; MIN16-NEXT: [[BASE_I1:%.*]] = getelementptr half, ptr [[BASE:%.*]], i32 1
; MIN16-NEXT: br label [[LOOP:%.*]]
; MIN16: loop:
-; MIN16-NEXT: [[X_I0:%.*]] = phi half [ 0xH0000, [[ENTRY:%.*]] ], [ [[X_NEXT_I0:%.*]], [[LOOP]] ]
-; MIN16-NEXT: [[X_I1:%.*]] = phi half [ 0xH0000, [[ENTRY]] ], [ [[X_NEXT_I1:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I0:%.*]] = phi half [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[X_NEXT_I0:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I1:%.*]] = phi half [ 0.000000e+00, [[ENTRY]] ], [ [[X_NEXT_I1:%.*]], [[LOOP]] ]
; MIN16-NEXT: [[IDX:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IDX_NEXT:%.*]], [[LOOP]] ]
; MIN16-NEXT: [[P:%.*]] = getelementptr <2 x half>, ptr [[BASE]], i64 [[IDX]]
; MIN16-NEXT: [[A_I0:%.*]] = load half, ptr [[P]], align 2
@@ -1005,9 +1005,9 @@ define void @phi_v3f16(ptr %base, i64 %bound) {
; MIN16-NEXT: [[BASE_I2:%.*]] = getelementptr half, ptr [[BASE]], i32 2
; MIN16-NEXT: br label [[LOOP:%.*]]
; MIN16: loop:
-; MIN16-NEXT: [[X_I0:%.*]] = phi half [ 0xH0000, [[ENTRY:%.*]] ], [ [[X_NEXT_I0:%.*]], [[LOOP]] ]
-; MIN16-NEXT: [[X_I1:%.*]] = phi half [ 0xH0000, [[ENTRY]] ], [ [[X_NEXT_I1:%.*]], [[LOOP]] ]
-; MIN16-NEXT: [[X_I2:%.*]] = phi half [ 0xH0000, [[ENTRY]] ], [ [[X_NEXT_I2:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I0:%.*]] = phi half [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[X_NEXT_I0:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I1:%.*]] = phi half [ 0.000000e+00, [[ENTRY]] ], [ [[X_NEXT_I1:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I2:%.*]] = phi half [ 0.000000e+00, [[ENTRY]] ], [ [[X_NEXT_I2:%.*]], [[LOOP]] ]
; MIN16-NEXT: [[IDX:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IDX_NEXT:%.*]], [[LOOP]] ]
; MIN16-NEXT: [[P:%.*]] = getelementptr <3 x half>, ptr [[BASE]], i64 [[IDX]]
; MIN16-NEXT: [[A_I0:%.*]] = load half, ptr [[P]], align 2
@@ -1033,7 +1033,7 @@ define void @phi_v3f16(ptr %base, i64 %bound) {
; MIN32-NEXT: br label [[LOOP:%.*]]
; MIN32: loop:
; MIN32-NEXT: [[X_I0:%.*]] = phi <2 x half> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[X_NEXT_I0:%.*]], [[LOOP]] ]
-; MIN32-NEXT: [[X_I1:%.*]] = phi half [ 0xH0000, [[ENTRY]] ], [ [[X_NEXT_I1:%.*]], [[LOOP]] ]
+; MIN32-NEXT: [[X_I1:%.*]] = phi half [ 0.000000e+00, [[ENTRY]] ], [ [[X_NEXT_I1:%.*]], [[LOOP]] ]
; MIN32-NEXT: [[IDX:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IDX_NEXT:%.*]], [[LOOP]] ]
; MIN32-NEXT: [[P:%.*]] = getelementptr <3 x half>, ptr [[BASE]], i64 [[IDX]]
; MIN32-NEXT: [[A_I0:%.*]] = load <2 x half>, ptr [[P]], align 2
@@ -1091,10 +1091,10 @@ define void @phi_v4f16(ptr %base, i64 %bound) {
; MIN16-NEXT: [[BASE_I3:%.*]] = getelementptr half, ptr [[BASE]], i32 3
; MIN16-NEXT: br label [[LOOP:%.*]]
; MIN16: loop:
-; MIN16-NEXT: [[X_I0:%.*]] = phi half [ 0xH0000, [[ENTRY:%.*]] ], [ [[X_NEXT_I0:%.*]], [[LOOP]] ]
-; MIN16-NEXT: [[X_I1:%.*]] = phi half [ 0xH0000, [[ENTRY]] ], [ [[X_NEXT_I1:%.*]], [[LOOP]] ]
-; MIN16-NEXT: [[X_I2:%.*]] = phi half [ 0xH0000, [[ENTRY]] ], [ [[X_NEXT_I2:%.*]], [[LOOP]] ]
-; MIN16-NEXT: [[X_I3:%.*]] = phi half [ 0xH0000, [[ENTRY]] ], [ [[X_NEXT_I3:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I0:%.*]] = phi half [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[X_NEXT_I0:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I1:%.*]] = phi half [ 0.000000e+00, [[ENTRY]] ], [ [[X_NEXT_I1:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I2:%.*]] = phi half [ 0.000000e+00, [[ENTRY]] ], [ [[X_NEXT_I2:%.*]], [[LOOP]] ]
+; MIN16-NEXT: [[X_I3:%.*]] = phi half [ 0.000000e+00, [[ENTRY]] ], [ [[X_NEXT_I3:%.*]], [[LOOP]] ]
; MIN16-NEXT: [[IDX:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IDX_NEXT:%.*]], [[LOOP]] ]
; MIN16-NEXT: [[P:%.*]] = getelementptr <4 x half>, ptr [[BASE]], i64 [[IDX]]
; MIN16-NEXT: [[A_I0:%.*]] = load half, ptr [[P]], align 2
diff --git a/llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll b/llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
index bd35708752193..3576f49ababac 100644
--- a/llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
+++ b/llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
@@ -52,7 +52,7 @@ define void @sqrt_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwi
; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #[[ATTR3:[0-9]+]]
-; CHECK-MVE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void
;
@@ -60,7 +60,7 @@ define void @sqrt_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwi
; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #[[ATTR2:[0-9]+]]
-; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void
;
@@ -68,7 +68,7 @@ define void @sqrt_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwi
; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #[[ATTR2:[0-9]+]]
-; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void
;
@@ -91,7 +91,7 @@ define void @fabs_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwi
; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #[[ATTR3]]
-; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void
;
@@ -99,7 +99,7 @@ define void @fabs_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwi
; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #[[ATTR2]]
-; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void
;
@@ -107,7 +107,7 @@ define void @fabs_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwi
; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #[[ATTR2]]
-; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void
;
@@ -130,7 +130,7 @@ define void @fma_test(ptr addrspace(1) noalias nocapture %out, float %a, float %
; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR3]]
-; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void
;
@@ -138,7 +138,7 @@ define void @fma_test(ptr addrspace(1) noalias nocapture %out, float %a, float %
; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
-; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void
;
@@ -146,7 +146,7 @@ define void @fma_test(ptr addrspace(1) noalias nocapture %out, float %a, float %
; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
-; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void
;
@@ -169,7 +169,7 @@ define void @fmuladd_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR3]]
-; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void
;
@@ -177,7 +177,7 @@ define void @fmuladd_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
-; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void
;
@@ -185,7 +185,7 @@ define void @fmuladd_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
-; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void
;
@@ -208,7 +208,7 @@ define void @minnum_test(ptr addrspace(1) noalias nocapture %out, float %a, floa
; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR3]]
-; CHECK-MVE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void
;
@@ -216,7 +216,7 @@ define void @minnum_test(ptr addrspace(1) noalias nocapture %out, float %a, floa
; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void
;
@@ -224,7 +224,7 @@ define void @minnum_test(ptr addrspace(1) noalias nocapture %out, float %a, floa
; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void
;
@@ -247,7 +247,7 @@ define void @maxnum_test(ptr addrspace(1) noalias nocapture %out, float %a, floa
; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR3]]
-; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void
;
@@ -255,7 +255,7 @@ define void @maxnum_test(ptr addrspace(1) noalias nocapture %out, float %a, floa
; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void
;
@@ -263,7 +263,7 @@ define void @maxnum_test(ptr addrspace(1) noalias nocapture %out, float %a, floa
; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void
;
@@ -286,7 +286,7 @@ define void @minimum_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #[[ATTR3]]
-; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void
;
@@ -294,7 +294,7 @@ define void @minimum_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void
;
@@ -302,7 +302,7 @@ define void @minimum_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void
;
@@ -325,7 +325,7 @@ define void @maximum_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-MVE-NEXT: entry:
; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #[[ATTR3]]
-; CHECK-MVE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-MVE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-MVE-NEXT: ret void
;
@@ -333,7 +333,7 @@ define void @maximum_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-V8M-MAIN-NEXT: entry:
; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-MAIN-NEXT: ret void
;
@@ -341,7 +341,7 @@ define void @maximum_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-V8M-BASE-NEXT: entry:
; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-V8M-BASE-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-V8M-BASE-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv32.ll b/llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv32.ll
index 18a3c9a6f7545..2f819d1d8d501 100644
--- a/llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv32.ll
+++ b/llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv32.ll
@@ -17,7 +17,7 @@ target triple = "riscv32-unknown-elf"
; CHECK: @.str4 = private unnamed_addr constant [6 x i8] c"error\00", align 1
; CHECK: @switch.table.f = private unnamed_addr constant [7 x i32] [i32 55, i32 123, i32 0, i32 -1, i32 27, i32 62, i32 1], align 4
; CHECK: @switch.table.char = private unnamed_addr constant [9 x i8] c"7{\00\FF\1B>\01!T", align 1
-; CHECK: @switch.table.h = private unnamed_addr constant [4 x float] [float 0x40091EB860000000, float 0x3FF3BE76C0000000, float 0x4012449BA0000000, float 0x4001AE1480000000], align 4
+; CHECK: @switch.table.h = private unnamed_addr constant [4 x float] [float 3.140000e+00, float 1.234000e+00, float 4.567000e+00, float 2.210000e+00], align 4
; CHECK: @switch.table.foostring = private unnamed_addr constant [4 x ptr] [ptr @.str, ptr @.str1, ptr @.str2, ptr @.str3], align 4
;.
define i32 @f(i32 %c) {
@@ -119,7 +119,7 @@ define void @h(i32 %x) {
; CHECK-NEXT: br label [[SW_EPILOG]]
; CHECK: sw.epilog:
; CHECK-NEXT: [[A_0:%.*]] = phi i8 [ [[SWITCH_MASKED]], [[SWITCH_LOOKUP]] ], [ 7, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[B_0:%.*]] = phi float [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 0x4023FAE140000000, [[ENTRY]] ]
+; CHECK-NEXT: [[B_0:%.*]] = phi float [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ f0x411FD70A, [[ENTRY]] ]
; CHECK-NEXT: call void @dummy(i8 signext [[A_0]], float [[B_0]])
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv64.ll b/llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv64.ll
index fe9fdc8dd4af9..ade4fad68772f 100644
--- a/llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv64.ll
+++ b/llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv64.ll
@@ -17,7 +17,7 @@ target triple = "riscv64-unknown-elf"
; CHECK: @.str4 = private unnamed_addr constant [6 x i8] c"error\00", align 1
; CHECK: @switch.table.f = private unnamed_addr constant [7 x i32] [i32 55, i32 123, i32 0, i32 -1, i32 27, i32 62, i32 1], align 4
; CHECK: @switch.table.char = private unnamed_addr constant [9 x i8] c"7{\00\FF\1B>\01!T", align 1
-; CHECK: @switch.table.h = private unnamed_addr constant [4 x float] [float 0x40091EB860000000, float 0x3FF3BE76C0000000, float 0x4012449BA0000000, float 0x4001AE1480000000], align 4
+; CHECK: @switch.table.h = private unnamed_addr constant [4 x float] [float 3.140000e+00, float 1.234000e+00, float 4.567000e+00, float 2.210000e+00], align 4
; CHECK: @switch.table.foostring = private unnamed_addr constant [4 x ptr] [ptr @.str, ptr @.str1, ptr @.str2, ptr @.str3], align 8
;.
define i32 @f(i32 %c) {
@@ -122,7 +122,7 @@ define void @h(i32 %x) {
; CHECK-NEXT: br label [[SW_EPILOG]]
; CHECK: sw.epilog:
; CHECK-NEXT: [[A_0:%.*]] = phi i8 [ [[SWITCH_MASKED]], [[SWITCH_LOOKUP]] ], [ 7, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[B_0:%.*]] = phi float [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 0x4023FAE140000000, [[ENTRY]] ]
+; CHECK-NEXT: [[B_0:%.*]] = phi float [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ f0x411FD70A, [[ENTRY]] ]
; CHECK-NEXT: call void @dummy(i8 signext [[A_0]], float [[B_0]])
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll b/llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
index f91adcc9707d8..9209c355f7585 100644
--- a/llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
+++ b/llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
@@ -25,7 +25,7 @@ target triple = "x86_64-unknown-linux-gnu"
; CHECK: @dllimport_d = external dllimport global [3 x i32]
; CHECK: @switch.table.f = private unnamed_addr constant [7 x i32] [i32 55, i32 123, i32 0, i32 -1, i32 27, i32 62, i32 1], align 4
; CHECK: @switch.table.char = private unnamed_addr constant [9 x i8] c"7{\00\FF\1B>\01!T", align 1
-; CHECK: @switch.table.h = private unnamed_addr constant [4 x float] [float 0x40091EB860000000, float 0x3FF3BE76C0000000, float 0x4012449BA0000000, float 0x4001AE1480000000], align 4
+; CHECK: @switch.table.h = private unnamed_addr constant [4 x float] [float 3.140000e+00, float 1.234000e+00, float 4.567000e+00, float 2.210000e+00], align 4
; CHECK: @switch.table.foostring = private unnamed_addr constant [4 x ptr] [ptr @.str, ptr @.str1, ptr @.str2, ptr @.str3], align 8
; CHECK: @switch.table.earlyreturncrash = private unnamed_addr constant [4 x i32] [i32 42, i32 9, i32 88, i32 5], align 4
; CHECK: @switch.table.earlyreturncrash.1 = private unnamed_addr constant [4 x i32] [i32 3, i32 4, i32 1, i32 5], align 4
@@ -145,7 +145,7 @@ define void @h(i32 %x) {
; CHECK-NEXT: br label [[SW_EPILOG]]
; CHECK: sw.epilog:
; CHECK-NEXT: [[A_0:%.*]] = phi i8 [ [[SWITCH_MASKED]], [[SWITCH_LOOKUP]] ], [ 7, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[B_0:%.*]] = phi float [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 0x4023FAE140000000, [[ENTRY]] ]
+; CHECK-NEXT: [[B_0:%.*]] = phi float [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ f0x411FD70A, [[ENTRY]] ]
; CHECK-NEXT: call void @dummy(i8 signext [[A_0]], float [[B_0]])
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SimplifyCFG/X86/two-entry-phi-fold-unpredictable.ll b/llvm/test/Transforms/SimplifyCFG/X86/two-entry-phi-fold-unpredictable.ll
index 82566d47b0328..5ebfbe6f10202 100644
--- a/llvm/test/Transforms/SimplifyCFG/X86/two-entry-phi-fold-unpredictable.ll
+++ b/llvm/test/Transforms/SimplifyCFG/X86/two-entry-phi-fold-unpredictable.ll
@@ -9,7 +9,7 @@ define { <2 x float>, <2 x float> } @foo(float %arg, <2 x float> %arg1, <2 x flo
; CHECK-NOFOLD-LABEL: define { <2 x float>, <2 x float> } @foo(
; CHECK-NOFOLD-SAME: float [[ARG:%.*]], <2 x float> [[ARG1:%.*]], <2 x float> [[ARG2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NOFOLD-NEXT: [[BB:.*]]:
-; CHECK-NOFOLD-NEXT: [[I:%.*]] = fcmp fast ogt float [[ARG]], 0x3F747AE140000000
+; CHECK-NOFOLD-NEXT: [[I:%.*]] = fcmp fast ogt float [[ARG]], 5.000000e-03
; CHECK-NOFOLD-NEXT: br i1 [[I]], label %[[BB3:.*]], label %[[BB20:.*]], !unpredictable [[META0:![0-9]+]]
; CHECK-NOFOLD: [[BB3]]:
; CHECK-NOFOLD-NEXT: [[I4:%.*]] = extractelement <2 x float> [[ARG1]], i64 0
@@ -21,7 +21,7 @@ define { <2 x float>, <2 x float> } @foo(float %arg, <2 x float> %arg1, <2 x flo
; CHECK-NOFOLD-NEXT: [[I10:%.*]] = fmul fast float [[I9]], [[I9]]
; CHECK-NOFOLD-NEXT: [[I11:%.*]] = fadd fast float [[I8]], [[I10]]
; CHECK-NOFOLD-NEXT: [[I12:%.*]] = tail call fast noundef float @llvm.sqrt.f32(float [[I11]])
-; CHECK-NOFOLD-NEXT: [[I13:%.*]] = fdiv fast float 0x3FEFD70A40000000, [[I12]]
+; CHECK-NOFOLD-NEXT: [[I13:%.*]] = fdiv fast float 9.950000e-01, [[I12]]
; CHECK-NOFOLD-NEXT: [[I14:%.*]] = fmul fast float [[I13]], [[I4]]
; CHECK-NOFOLD-NEXT: [[I15:%.*]] = insertelement <2 x float> poison, float [[I14]], i64 0
; CHECK-NOFOLD-NEXT: [[I16:%.*]] = fmul fast float [[I13]], [[I6]]
@@ -39,7 +39,7 @@ define { <2 x float>, <2 x float> } @foo(float %arg, <2 x float> %arg1, <2 x flo
; CHECK-FOLD-LABEL: define { <2 x float>, <2 x float> } @foo(
; CHECK-FOLD-SAME: float [[ARG:%.*]], <2 x float> [[ARG1:%.*]], <2 x float> [[ARG2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-FOLD-NEXT: [[BB:.*:]]
-; CHECK-FOLD-NEXT: [[I:%.*]] = fcmp fast ogt float [[ARG]], 0x3F747AE140000000
+; CHECK-FOLD-NEXT: [[I:%.*]] = fcmp fast ogt float [[ARG]], 5.000000e-03
; CHECK-FOLD-NEXT: [[I4:%.*]] = extractelement <2 x float> [[ARG1]], i64 0
; CHECK-FOLD-NEXT: [[I5:%.*]] = fmul fast float [[I4]], [[I4]]
; CHECK-FOLD-NEXT: [[I6:%.*]] = extractelement <2 x float> [[ARG1]], i64 1
@@ -49,7 +49,7 @@ define { <2 x float>, <2 x float> } @foo(float %arg, <2 x float> %arg1, <2 x flo
; CHECK-FOLD-NEXT: [[I10:%.*]] = fmul fast float [[I9]], [[I9]]
; CHECK-FOLD-NEXT: [[I11:%.*]] = fadd fast float [[I8]], [[I10]]
; CHECK-FOLD-NEXT: [[I12:%.*]] = tail call fast float @llvm.sqrt.f32(float [[I11]])
-; CHECK-FOLD-NEXT: [[I13:%.*]] = fdiv fast float 0x3FEFD70A40000000, [[I12]]
+; CHECK-FOLD-NEXT: [[I13:%.*]] = fdiv fast float 9.950000e-01, [[I12]]
; CHECK-FOLD-NEXT: [[I14:%.*]] = fmul fast float [[I13]], [[I4]]
; CHECK-FOLD-NEXT: [[I15:%.*]] = insertelement <2 x float> poison, float [[I14]], i64 0
; CHECK-FOLD-NEXT: [[I16:%.*]] = fmul fast float [[I13]], [[I6]]
diff --git a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-phis.ll b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-phis.ll
index 150bdfcff92a1..e281e9bcc5e4d 100644
--- a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-phis.ll
+++ b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-phis.ll
@@ -464,13 +464,13 @@ define float @D139275_c4001580(float %val) {
; ALL-NEXT: [[CMP1:%.*]] = fcmp ult float [[VAL]], 1.000000e+00
; ALL-NEXT: br i1 [[CMP1]], label [[IF_END3:%.*]], label [[RETURN]]
; ALL: if.end3:
-; ALL-NEXT: [[CMP4:%.*]] = fcmp olt float [[VAL]], 0x3FC99999A0000000
+; ALL-NEXT: [[CMP4:%.*]] = fcmp olt float [[VAL]], 2.000000e-01
; ALL-NEXT: br i1 [[CMP4]], label [[RETURN]], label [[IF_END6:%.*]]
; ALL: if.end6:
-; ALL-NEXT: [[SUB:%.*]] = fadd float [[VAL]], 0xBFB99999A0000000
+; ALL-NEXT: [[SUB:%.*]] = fadd float [[VAL]], -1.000000e-01
; ALL-NEXT: br label [[RETURN]]
; ALL: return:
-; ALL-NEXT: [[RETVAL_0:%.*]] = phi float [ [[SUB]], [[IF_END6]] ], [ 0.000000e+00, [[ENTRY:%.*]] ], [ 0x3FB99999A0000000, [[IF_END]] ], [ 0.000000e+00, [[IF_END3]] ]
+; ALL-NEXT: [[RETVAL_0:%.*]] = phi float [ [[SUB]], [[IF_END6]] ], [ 0.000000e+00, [[ENTRY:%.*]] ], [ 1.000000e-01, [[IF_END]] ], [ 0.000000e+00, [[IF_END3]] ]
; ALL-NEXT: ret float [[RETVAL_0]]
;
entry:
diff --git a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
index 7b88ec338cf5e..e6d4f32e1abc8 100644
--- a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
+++ b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
@@ -1158,10 +1158,10 @@ define i32 @test_builtin_fpclassify(float %x) {
; CHECK-NEXT: br i1 [[CMP]], label [[FPCLASSIFY_END]], label [[FPCLASSIFY_NOT_NAN]]
; CHECK: fpclassify_not_nan:
; CHECK-NEXT: [[X_ABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq float [[X_ABS]], 0x7FF0000000000000
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq float [[X_ABS]], +inf
; CHECK-NEXT: br i1 [[ISINF]], label [[FPCLASSIFY_END]], label [[FPCLASSIFY_NOT_INF]]
; CHECK: fpclassify_not_inf:
-; CHECK-NEXT: [[ISNORMAL:%.*]] = fcmp uge float [[X_ABS]], 0x3810000000000000
+; CHECK-NEXT: [[ISNORMAL:%.*]] = fcmp uge float [[X_ABS]], f0x00800000
; CHECK-NEXT: [[NORMAL_OR_SUBNORMAL]] = select i1 [[ISNORMAL]], i32 4, i32 3
; CHECK-NEXT: br label [[FPCLASSIFY_END]]
;
diff --git a/llvm/test/Transforms/SimplifyCFG/speculate-math.ll b/llvm/test/Transforms/SimplifyCFG/speculate-math.ll
index f6f50c303206b..b3f5a54bfe186 100644
--- a/llvm/test/Transforms/SimplifyCFG/speculate-math.ll
+++ b/llvm/test/Transforms/SimplifyCFG/speculate-math.ll
@@ -37,7 +37,7 @@ define void @sqrt_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwi
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #[[ATTR2:[0-9]+]]
-; CHECK-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -60,7 +60,7 @@ define void @fabs_test(ptr addrspace(1) noalias nocapture %out, float %a) nounwi
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #[[ATTR2]]
-; CHECK-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -83,7 +83,7 @@ define void @fma_test(ptr addrspace(1) noalias nocapture %out, float %a, float %
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
-; CHECK-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -106,7 +106,7 @@ define void @fmuladd_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #[[ATTR2]]
-; CHECK-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -129,7 +129,7 @@ define void @minnum_test(ptr addrspace(1) noalias nocapture %out, float %a, floa
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -152,7 +152,7 @@ define void @maxnum_test(ptr addrspace(1) noalias nocapture %out, float %a, floa
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -175,7 +175,7 @@ define void @minimum_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -198,7 +198,7 @@ define void @maximum_test(ptr addrspace(1) noalias nocapture %out, float %a, flo
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
; CHECK-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #[[ATTR2]]
-; CHECK-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float +qnan, float [[TMP0]]
; CHECK-NEXT: store float [[COND_I]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SpeculativeExecution/spec-fp.ll b/llvm/test/Transforms/SpeculativeExecution/spec-fp.ll
index d302fe8a00088..05745075c1dd4 100644
--- a/llvm/test/Transforms/SpeculativeExecution/spec-fp.ll
+++ b/llvm/test/Transforms/SpeculativeExecution/spec-fp.ll
@@ -31,7 +31,7 @@ b:
}
; CHECK-LABEL: @ifThen_binary_fneg(
-; CHECK: fsub float -0.0
+; CHECK: fsub float -0.000000e+00
; CHECK: br i1 true
define void @ifThen_binary_fneg() {
br i1 true, label %a, label %b
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/bitcast.ll b/llvm/test/Transforms/TypePromotion/AArch64/bitcast.ll
index 883674a0f64e0..b3990ce4a02bc 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/bitcast.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/bitcast.ll
@@ -22,7 +22,7 @@ entry:
define i1 @halfbitcast() {
; CHECK-LABEL: define i1 @halfbitcast() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast half 0xH8000 to i16
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast half -0.000000e+00 to i16
; CHECK-NEXT: [[DOTNOT114:%.*]] = icmp eq i16 [[TMP0]], 0
; CHECK-NEXT: ret i1 [[DOTNOT114]]
;
diff --git a/llvm/test/Transforms/Util/libcalls-shrinkwrap-double.ll b/llvm/test/Transforms/Util/libcalls-shrinkwrap-double.ll
index 4ac216f85c74c..1ae8c34162049 100644
--- a/llvm/test/Transforms/Util/libcalls-shrinkwrap-double.ll
+++ b/llvm/test/Transforms/Util/libcalls-shrinkwrap-double.ll
@@ -138,8 +138,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_02 = call double @cos(double %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp oeq double %value, 0xFFF0000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp oeq double %value, 0x7FF0000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp oeq double %value, -inf
+; CHECK: [[COND2:%[0-9]+]] = fcmp oeq double %value, +inf
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -148,8 +148,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_03 = call double @sin(double %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp oeq double %value, 0xFFF0000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp oeq double %value, 0x7FF0000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp oeq double %value, -inf
+; CHECK: [[COND2:%[0-9]+]] = fcmp oeq double %value, +inf
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -249,8 +249,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_02 = call double @cos(double %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %value, double 0xFFF0000000000000, metadata !"oeq", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %value, double 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %value, double -inf, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %value, double +inf, metadata !"oeq", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -259,8 +259,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_03 = call double @sin(double %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %value, double 0xFFF0000000000000, metadata !"oeq", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %value, double 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %value, double -inf, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f64(double %value, double +inf, metadata !"oeq", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
diff --git a/llvm/test/Transforms/Util/libcalls-shrinkwrap-float.ll b/llvm/test/Transforms/Util/libcalls-shrinkwrap-float.ll
index f4dc79759d17e..6f25beb46631c 100644
--- a/llvm/test/Transforms/Util/libcalls-shrinkwrap-float.ll
+++ b/llvm/test/Transforms/Util/libcalls-shrinkwrap-float.ll
@@ -139,8 +139,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_02 = call float @cosf(float %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp oeq float %value, 0xFFF0000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp oeq float %value, 0x7FF0000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp oeq float %value, -inf
+; CHECK: [[COND2:%[0-9]+]] = fcmp oeq float %value, +inf
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -149,8 +149,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_03 = call float @sinf(float %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp oeq float %value, 0xFFF0000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp oeq float %value, 0x7FF0000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp oeq float %value, -inf
+; CHECK: [[COND2:%[0-9]+]] = fcmp oeq float %value, +inf
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -250,8 +250,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_02 = call float @cosf(float %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[VALUE]], float 0xFFF0000000000000, metadata !"oeq", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[VALUE]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[VALUE]], float -inf, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[VALUE]], float +inf, metadata !"oeq", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -260,8 +260,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_03 = call float @sinf(float %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[VALUE]], float 0xFFF0000000000000, metadata !"oeq", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[VALUE]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[VALUE]], float -inf, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[VALUE]], float +inf, metadata !"oeq", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
diff --git a/llvm/test/Transforms/Util/libcalls-shrinkwrap-long-double.ll b/llvm/test/Transforms/Util/libcalls-shrinkwrap-long-double.ll
index c2b981c81c75d..1b218cf279578 100644
--- a/llvm/test/Transforms/Util/libcalls-shrinkwrap-long-double.ll
+++ b/llvm/test/Transforms/Util/libcalls-shrinkwrap-long-double.ll
@@ -6,8 +6,8 @@ target triple = "x86_64-unknown-linux-gnu"
define void @test_range_error(x86_fp80 %value) {
entry:
%call_0 = call x86_fp80 @coshl(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00CB174000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK400CB174000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, -1.135700e+04
+; CHECK: [[COND2:%[0-9]+]] = fcmp ogt x86_fp80 %value, 1.135700e+04
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT:[0-9]+]]
; CHECK: [[CALL_LABEL]]:
@@ -16,8 +16,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_1 = call x86_fp80 @expl(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00CB21C000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK400CB170000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, -1.139900e+04
+; CHECK: [[COND2:%[0-9]+]] = fcmp ogt x86_fp80 %value, 1.135600e+04
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -26,8 +26,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_3 = call x86_fp80 @exp2l(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00D807A000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK400CB1DC000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, -1.644500e+04
+; CHECK: [[COND2:%[0-9]+]] = fcmp ogt x86_fp80 %value, 1.138300e+04
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -36,8 +36,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_4 = call x86_fp80 @sinhl(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00CB174000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK400CB174000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, -1.135700e+04
+; CHECK: [[COND2:%[0-9]+]] = fcmp ogt x86_fp80 %value, 1.135700e+04
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -46,7 +46,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_5 = call x86_fp80 @expm1l(x86_fp80 %value)
-; CHECK: [[COND:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK400CB170000000000000
+; CHECK: [[COND:%[0-9]+]] = fcmp ogt x86_fp80 %value, 1.135600e+04
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_5 = call x86_fp80 @expm1l(x86_fp80 %value)
@@ -59,8 +59,8 @@ entry:
define void @test_range_error_strictfp(x86_fp80 %value) strictfp {
entry:
%call_0 = call x86_fp80 @coshl(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE:%.*]], x86_fp80 0xKC00CB174000000000000, metadata !"olt", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK400CB174000000000000, metadata !"ogt", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE:%.*]], x86_fp80 -1.135700e+04, metadata !"olt", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 1.135700e+04, metadata !"ogt", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT:[0-9]+]]
; CHECK: [[CALL_LABEL]]:
@@ -69,8 +69,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_1 = call x86_fp80 @expl(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKC00CB21C000000000000, metadata !"olt", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK400CB170000000000000, metadata !"ogt", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -1.139900e+04, metadata !"olt", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 1.135600e+04, metadata !"ogt", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -79,8 +79,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_3 = call x86_fp80 @exp2l(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKC00D807A000000000000, metadata !"olt", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK400CB1DC000000000000, metadata !"ogt", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -1.644500e+04, metadata !"olt", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 1.138300e+04, metadata !"ogt", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -89,8 +89,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_4 = call x86_fp80 @sinhl(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKC00CB174000000000000, metadata !"olt", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK400CB174000000000000, metadata !"ogt", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -1.135700e+04, metadata !"olt", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 1.135700e+04, metadata !"ogt", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -99,7 +99,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_5 = call x86_fp80 @expm1l(x86_fp80 %value) strictfp
-; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK400CB170000000000000, metadata !"ogt", metadata !"fpexcept.strict")
+; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 1.135600e+04, metadata !"ogt", metadata !"fpexcept.strict")
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_5 = call x86_fp80 @expm1l(x86_fp80 %value)
@@ -119,8 +119,8 @@ declare x86_fp80 @expm1l(x86_fp80)
define void @test_domain_error(x86_fp80 %value) {
entry:
%call_00 = call x86_fp80 @acosl(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK3FFF8000000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKBFFF8000000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp ogt x86_fp80 %value, 1.000000e+00
+; CHECK: [[COND2:%[0-9]+]] = fcmp olt x86_fp80 %value, -1.000000e+00
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -129,8 +129,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_01 = call x86_fp80 @asinl(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK3FFF8000000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKBFFF8000000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp ogt x86_fp80 %value, 1.000000e+00
+; CHECK: [[COND2:%[0-9]+]] = fcmp olt x86_fp80 %value, -1.000000e+00
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -139,8 +139,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_02 = call x86_fp80 @cosl(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp oeq x86_fp80 %value, 0xKFFFF8000000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp oeq x86_fp80 %value, 0xK7FFF8000000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp oeq x86_fp80 %value, -inf
+; CHECK: [[COND2:%[0-9]+]] = fcmp oeq x86_fp80 %value, +inf
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -149,8 +149,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_03 = call x86_fp80 @sinl(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp oeq x86_fp80 %value, 0xKFFFF8000000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp oeq x86_fp80 %value, 0xK7FFF8000000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp oeq x86_fp80 %value, -inf
+; CHECK: [[COND2:%[0-9]+]] = fcmp oeq x86_fp80 %value, +inf
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -159,7 +159,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_04 = call x86_fp80 @acoshl(x86_fp80 %value)
-; CHECK: [[COND:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xK3FFF8000000000000000
+; CHECK: [[COND:%[0-9]+]] = fcmp olt x86_fp80 %value, 1.000000e+00
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_04 = call x86_fp80 @acoshl(x86_fp80 %value)
@@ -167,7 +167,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_05 = call x86_fp80 @sqrtl(x86_fp80 %value)
-; CHECK: [[COND:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xK00000000000000000000
+; CHECK: [[COND:%[0-9]+]] = fcmp olt x86_fp80 %value, 0.000000e+00
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_05 = call x86_fp80 @sqrtl(x86_fp80 %value)
@@ -175,8 +175,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_06 = call x86_fp80 @atanhl(x86_fp80 %value)
-; CHECK: [[COND1:%[0-9]+]] = fcmp oge x86_fp80 %value, 0xK3FFF8000000000000000
-; CHECK: [[COND2:%[0-9]+]] = fcmp ole x86_fp80 %value, 0xKBFFF8000000000000000
+; CHECK: [[COND1:%[0-9]+]] = fcmp oge x86_fp80 %value, 1.000000e+00
+; CHECK: [[COND2:%[0-9]+]] = fcmp ole x86_fp80 %value, -1.000000e+00
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -185,7 +185,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_07 = call x86_fp80 @logl(x86_fp80 %value)
-; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0xK00000000000000000000
+; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0.000000e+00
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_07 = call x86_fp80 @logl(x86_fp80 %value)
@@ -193,7 +193,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_08 = call x86_fp80 @log10l(x86_fp80 %value)
-; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0xK00000000000000000000
+; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0.000000e+00
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_08 = call x86_fp80 @log10l(x86_fp80 %value)
@@ -201,7 +201,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_09 = call x86_fp80 @log2l(x86_fp80 %value)
-; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0xK00000000000000000000
+; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0.000000e+00
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_09 = call x86_fp80 @log2l(x86_fp80 %value)
@@ -209,7 +209,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_10 = call x86_fp80 @logbl(x86_fp80 %value)
-; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0xK00000000000000000000
+; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0.000000e+00
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_10 = call x86_fp80 @logbl(x86_fp80 %value)
@@ -217,7 +217,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_11 = call x86_fp80 @log1pl(x86_fp80 %value)
-; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, 0xKBFFF8000000000000000
+; CHECK: [[COND:%[0-9]+]] = fcmp ole x86_fp80 %value, -1.000000e+00
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_11 = call x86_fp80 @log1pl(x86_fp80 %value)
@@ -230,8 +230,8 @@ entry:
define void @test_domain_error_strictfp(x86_fp80 %value) strictfp {
entry:
%call_00 = call x86_fp80 @acosl(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE:%.*]], x86_fp80 0xK3FFF8000000000000000, metadata !"ogt", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKBFFF8000000000000000, metadata !"olt", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE:%.*]], x86_fp80 1.000000e+00, metadata !"ogt", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -1.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -240,8 +240,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_01 = call x86_fp80 @asinl(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK3FFF8000000000000000, metadata !"ogt", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKBFFF8000000000000000, metadata !"olt", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 1.000000e+00, metadata !"ogt", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -1.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -250,8 +250,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_02 = call x86_fp80 @cosl(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKFFFF8000000000000000, metadata !"oeq", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK7FFF8000000000000000, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -inf, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 +inf, metadata !"oeq", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -260,8 +260,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_03 = call x86_fp80 @sinl(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKFFFF8000000000000000, metadata !"oeq", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK7FFF8000000000000000, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -inf, metadata !"oeq", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 +inf, metadata !"oeq", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -270,7 +270,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_04 = call x86_fp80 @acoshl(x86_fp80 %value) strictfp
-; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK3FFF8000000000000000, metadata !"olt", metadata !"fpexcept.strict")
+; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 1.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_04 = call x86_fp80 @acoshl(x86_fp80 %value)
@@ -278,7 +278,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_05 = call x86_fp80 @sqrtl(x86_fp80 %value) strictfp
-; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK00000000000000000000, metadata !"olt", metadata !"fpexcept.strict")
+; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict")
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_05 = call x86_fp80 @sqrtl(x86_fp80 %value)
@@ -286,8 +286,8 @@ entry:
; CHECK: [[END_LABEL]]:
%call_06 = call x86_fp80 @atanhl(x86_fp80 %value) strictfp
-; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK3FFF8000000000000000, metadata !"oge", metadata !"fpexcept.strict")
-; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKBFFF8000000000000000, metadata !"ole", metadata !"fpexcept.strict")
+; CHECK: [[COND1:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 1.000000e+00, metadata !"oge", metadata !"fpexcept.strict")
+; CHECK: [[COND2:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -1.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
@@ -296,7 +296,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_07 = call x86_fp80 @logl(x86_fp80 %value) strictfp
-; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK00000000000000000000, metadata !"ole", metadata !"fpexcept.strict")
+; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_07 = call x86_fp80 @logl(x86_fp80 %value)
@@ -304,7 +304,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_08 = call x86_fp80 @log10l(x86_fp80 %value) strictfp
-; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK00000000000000000000, metadata !"ole", metadata !"fpexcept.strict")
+; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_08 = call x86_fp80 @log10l(x86_fp80 %value)
@@ -312,7 +312,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_09 = call x86_fp80 @log2l(x86_fp80 %value) strictfp
-; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK00000000000000000000, metadata !"ole", metadata !"fpexcept.strict")
+; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_09 = call x86_fp80 @log2l(x86_fp80 %value)
@@ -320,7 +320,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_10 = call x86_fp80 @logbl(x86_fp80 %value) strictfp
-; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xK00000000000000000000, metadata !"ole", metadata !"fpexcept.strict")
+; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_10 = call x86_fp80 @logbl(x86_fp80 %value)
@@ -328,7 +328,7 @@ entry:
; CHECK: [[END_LABEL]]:
%call_11 = call x86_fp80 @log1pl(x86_fp80 %value) strictfp
-; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 0xKBFFF8000000000000000, metadata !"ole", metadata !"fpexcept.strict")
+; CHECK: [[COND:%[0-9]+]] = call i1 @llvm.experimental.constrained.fcmp.f80(x86_fp80 [[VALUE]], x86_fp80 -1.000000e+00, metadata !"ole", metadata !"fpexcept.strict")
; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]], !prof ![[BRANCH_WEIGHT]]
; CHECK: [[CALL_LABEL]]:
; CHECK-NEXT: %call_11 = call x86_fp80 @log1pl(x86_fp80 %value)
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
index 72b75148f027e..40dff3721e609 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
@@ -339,7 +339,7 @@ define <8 x i8> @constantdiff2(<8 x i8> %a) {
define <8 x half> @constantsplatf(<8 x half> %a) {
; CHECK-LABEL: @constantsplatf(
-; CHECK-NEXT: [[R:%.*]] = fadd <8 x half> [[A:%.*]], splat (half 0xH4900)
+; CHECK-NEXT: [[R:%.*]] = fadd <8 x half> [[A:%.*]], splat (half 1.000000e+01)
; CHECK-NEXT: ret <8 x half> [[R]]
;
%ab = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
@@ -1202,7 +1202,7 @@ define <16 x i32> @const_types(<16 x i32> %wide.vec, <16 x i32> %wide.vec116) {
define <32 x half> @cast_types(<32 x i16> %wide.vec) {
; CHECK-LABEL: @cast_types(
; CHECK-NEXT: [[TMP1:%.*]] = sitofp <32 x i16> [[WIDE_VEC:%.*]] to <32 x half>
-; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = fmul fast <32 x half> [[TMP1]], splat (half 0xH0200)
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = fmul fast <32 x half> [[TMP1]], splat (half 3.051760e-05)
; CHECK-NEXT: ret <32 x half> [[INTERLEAVED_VEC]]
;
%strided.vec = shufflevector <32 x i16> %wide.vec, <32 x i16> poison, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
diff --git a/llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll b/llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll
index f4aee898ec838..2373ff877c1db 100644
--- a/llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll
+++ b/llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll
@@ -1515,7 +1515,7 @@ define <vscale x 8 x half> @fadd_nxv1f16_allonesmask(<vscale x 8 x half> %x, hal
; VEC-COMBINE-LABEL: @fadd_nxv1f16_allonesmask(
; VEC-COMBINE-NEXT: [[SPLAT:%.*]] = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
; VEC-COMBINE-NEXT: [[MASK:%.*]] = shufflevector <vscale x 8 x i1> [[SPLAT]], <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
-; VEC-COMBINE-NEXT: [[TMP1:%.*]] = fadd half [[Y:%.*]], 0xH5140
+; VEC-COMBINE-NEXT: [[TMP1:%.*]] = fadd half [[Y:%.*]], 4.200000e+01
; VEC-COMBINE-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x half> poison, half [[TMP1]], i64 0
; VEC-COMBINE-NEXT: [[TMP2:%.*]] = shufflevector <vscale x 8 x half> [[DOTSPLATINSERT]], <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
; VEC-COMBINE-NEXT: [[TMP3:%.*]] = call <vscale x 8 x half> @llvm.vp.fadd.nxv8f16(<vscale x 8 x half> [[X:%.*]], <vscale x 8 x half> [[TMP2]], <vscale x 8 x i1> [[MASK]], i32 [[EVL:%.*]])
@@ -1526,7 +1526,7 @@ define <vscale x 8 x half> @fadd_nxv1f16_allonesmask(<vscale x 8 x half> %x, hal
; NO-VEC-COMBINE-NEXT: [[MASK:%.*]] = shufflevector <vscale x 8 x i1> [[SPLAT]], <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
; NO-VEC-COMBINE-NEXT: [[TMP1:%.*]] = insertelement <vscale x 8 x half> poison, half [[Y:%.*]], i64 0
; NO-VEC-COMBINE-NEXT: [[TMP2:%.*]] = shufflevector <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
-; NO-VEC-COMBINE-NEXT: [[TMP3:%.*]] = call <vscale x 8 x half> @llvm.vp.fadd.nxv8f16(<vscale x 8 x half> [[TMP2]], <vscale x 8 x half> splat (half 0xH5140), <vscale x 8 x i1> [[MASK]], i32 [[EVL:%.*]])
+; NO-VEC-COMBINE-NEXT: [[TMP3:%.*]] = call <vscale x 8 x half> @llvm.vp.fadd.nxv8f16(<vscale x 8 x half> [[TMP2]], <vscale x 8 x half> splat (half 4.200000e+01), <vscale x 8 x i1> [[MASK]], i32 [[EVL:%.*]])
; NO-VEC-COMBINE-NEXT: [[TMP4:%.*]] = call <vscale x 8 x half> @llvm.vp.fadd.nxv8f16(<vscale x 8 x half> [[X:%.*]], <vscale x 8 x half> [[TMP3]], <vscale x 8 x i1> [[MASK]], i32 [[EVL]])
; NO-VEC-COMBINE-NEXT: ret <vscale x 8 x half> [[TMP4]]
;
@@ -1543,7 +1543,7 @@ define <vscale x 8 x half> @fadd_nxv8f16_anymask(<vscale x 8 x half> %x, half %y
; ALL-LABEL: @fadd_nxv8f16_anymask(
; ALL-NEXT: [[TMP1:%.*]] = insertelement <vscale x 8 x half> poison, half [[Y:%.*]], i64 0
; ALL-NEXT: [[TMP2:%.*]] = shufflevector <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
-; ALL-NEXT: [[TMP3:%.*]] = call <vscale x 8 x half> @llvm.vp.fadd.nxv8f16(<vscale x 8 x half> [[TMP2]], <vscale x 8 x half> splat (half 0xH5140), <vscale x 8 x i1> [[MASK:%.*]], i32 [[EVL:%.*]])
+; ALL-NEXT: [[TMP3:%.*]] = call <vscale x 8 x half> @llvm.vp.fadd.nxv8f16(<vscale x 8 x half> [[TMP2]], <vscale x 8 x half> splat (half 4.200000e+01), <vscale x 8 x i1> [[MASK:%.*]], i32 [[EVL:%.*]])
; ALL-NEXT: [[TMP4:%.*]] = call <vscale x 8 x half> @llvm.vp.fadd.nxv8f16(<vscale x 8 x half> [[X:%.*]], <vscale x 8 x half> [[TMP3]], <vscale x 8 x i1> [[MASK]], i32 [[EVL]])
; ALL-NEXT: ret <vscale x 8 x half> [[TMP4]]
;
diff --git a/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll b/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
index cf3bd00527f81..b6517f5ac98c5 100644
--- a/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
@@ -573,7 +573,7 @@ define <2 x double> @fadd_constant(double %x) {
define <2 x double> @fadd_constant_not_undef_lane(double %x) {
; CHECK-LABEL: @fadd_constant_not_undef_lane(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = fadd double [[X:%.*]], -4.200000e+01
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double 0x7FF8000000000000), double [[BO_SCALAR]], i64 1
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double +qnan), double [[BO_SCALAR]], i64 1
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 1
@@ -595,7 +595,7 @@ define <2 x double> @fsub_constant_op0(double %x) {
define <2 x double> @fsub_constant_op0_not_undef_lane(double %x) {
; CHECK-LABEL: @fsub_constant_op0_not_undef_lane(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = fsub nsz double -4.200000e+01, [[X:%.*]]
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double 0x7FF8000000000000), double [[BO_SCALAR]], i64 1
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double +qnan), double [[BO_SCALAR]], i64 1
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 1
@@ -606,7 +606,7 @@ define <2 x double> @fsub_constant_op0_not_undef_lane(double %x) {
define <2 x double> @fsub_constant_op1(double %x) {
; CHECK-LABEL: @fsub_constant_op1(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = fsub double [[X:%.*]], 4.200000e+01
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> <double undef, double 0x7FF8000000000000>, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> <double undef, double +qnan>, double [[BO_SCALAR]], i64 1
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 1
@@ -639,7 +639,7 @@ define <2 x double> @fmul_constant(double %x) {
define <2 x double> @fmul_constant_not_undef_lane(double %x) {
; CHECK-LABEL: @fmul_constant_not_undef_lane(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = fmul double [[X:%.*]], -4.200000e+01
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double 0x7FF8000000000000), double [[BO_SCALAR]], i64 1
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double +qnan), double [[BO_SCALAR]], i64 1
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 1
@@ -650,7 +650,7 @@ define <2 x double> @fmul_constant_not_undef_lane(double %x) {
define <2 x double> @fdiv_constant_op0(double %x) {
; CHECK-LABEL: @fdiv_constant_op0(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = fdiv nnan double 4.200000e+01, [[X:%.*]]
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> <double undef, double 0x7FF8000000000000>, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> <double undef, double +qnan>, double [[BO_SCALAR]], i64 1
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 1
@@ -661,7 +661,7 @@ define <2 x double> @fdiv_constant_op0(double %x) {
define <2 x double> @fdiv_constant_op0_not_undef_lane(double %x) {
; SSE-LABEL: @fdiv_constant_op0_not_undef_lane(
; SSE-NEXT: [[BO_SCALAR:%.*]] = fdiv ninf double 4.200000e+01, [[X:%.*]]
-; SSE-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double 0x7FF8000000000000), double [[BO_SCALAR]], i64 0
+; SSE-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double +qnan), double [[BO_SCALAR]], i64 0
; SSE-NEXT: ret <2 x double> [[BO]]
;
; AVX-LABEL: @fdiv_constant_op0_not_undef_lane(
@@ -677,7 +677,7 @@ define <2 x double> @fdiv_constant_op0_not_undef_lane(double %x) {
define <2 x double> @fdiv_constant_op1(double %x) {
; SSE-LABEL: @fdiv_constant_op1(
; SSE-NEXT: [[BO_SCALAR:%.*]] = fdiv double [[X:%.*]], 4.200000e+01
-; SSE-NEXT: [[BO:%.*]] = insertelement <2 x double> <double 0x7FF8000000000000, double undef>, double [[BO_SCALAR]], i64 0
+; SSE-NEXT: [[BO:%.*]] = insertelement <2 x double> <double +qnan, double undef>, double [[BO_SCALAR]], i64 0
; SSE-NEXT: ret <2 x double> [[BO]]
;
; AVX-LABEL: @fdiv_constant_op1(
@@ -693,7 +693,7 @@ define <2 x double> @fdiv_constant_op1(double %x) {
define <2 x double> @fdiv_constant_op1_not_undef_lane(double %x) {
; SSE-LABEL: @fdiv_constant_op1_not_undef_lane(
; SSE-NEXT: [[BO_SCALAR:%.*]] = fdiv double [[X:%.*]], 4.200000e+01
-; SSE-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double 0x7FF8000000000000), double [[BO_SCALAR]], i64 0
+; SSE-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double +qnan), double [[BO_SCALAR]], i64 0
; SSE-NEXT: ret <2 x double> [[BO]]
;
; AVX-LABEL: @fdiv_constant_op1_not_undef_lane(
@@ -709,7 +709,7 @@ define <2 x double> @fdiv_constant_op1_not_undef_lane(double %x) {
define <2 x double> @frem_constant_op0(double %x) {
; CHECK-LABEL: @frem_constant_op0(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = frem fast double 4.200000e+01, [[X:%.*]]
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> <double 0x7FF8000000000000, double undef>, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> <double +qnan, double undef>, double [[BO_SCALAR]], i64 0
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 0
@@ -720,7 +720,7 @@ define <2 x double> @frem_constant_op0(double %x) {
define <2 x double> @frem_constant_op0_not_undef_lane(double %x) {
; CHECK-LABEL: @frem_constant_op0_not_undef_lane(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = frem double -4.200000e+01, [[X:%.*]]
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double 0x7FF8000000000000), double [[BO_SCALAR]], i64 1
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double +qnan), double [[BO_SCALAR]], i64 1
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 1
@@ -731,7 +731,7 @@ define <2 x double> @frem_constant_op0_not_undef_lane(double %x) {
define <2 x double> @frem_constant_op1(double %x) {
; CHECK-LABEL: @frem_constant_op1(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = frem ninf double [[X:%.*]], 4.200000e+01
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> <double undef, double 0x7FF8000000000000>, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> <double undef, double +qnan>, double [[BO_SCALAR]], i64 1
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 1
@@ -742,7 +742,7 @@ define <2 x double> @frem_constant_op1(double %x) {
define <2 x double> @frem_constant_op1_not_undef_lane(double %x) {
; CHECK-LABEL: @frem_constant_op1_not_undef_lane(
; CHECK-NEXT: [[BO_SCALAR:%.*]] = frem nnan double [[X:%.*]], 4.200000e+01
-; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double 0x7FF8000000000000), double [[BO_SCALAR]], i64 0
+; CHECK-NEXT: [[BO:%.*]] = insertelement <2 x double> splat (double +qnan), double [[BO_SCALAR]], i64 0
; CHECK-NEXT: ret <2 x double> [[BO]]
;
%ins = insertelement <2 x double> undef, double %x, i32 0
diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-fma-const.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-fma-const.ll
index 78879d4903a97..e99bb9380d299 100644
--- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-fma-const.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-fma-const.ll
@@ -5,14 +5,14 @@
define <4 x float> @shuffle_fma_const_chain(<4 x float> %a0) {
; SSE-LABEL: define <4 x float> @shuffle_fma_const_chain(
; SSE-SAME: <4 x float> [[A0:%.*]]) #[[ATTR0:[0-9]+]] {
-; SSE-NEXT: [[F:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
+; SSE-NEXT: [[F:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> splat (float f0x3C6F4682), <4 x float> splat (float f0xBD9B8AF7))
; SSE-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[F]], <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: ret <4 x float> [[RES]]
;
; AVX-LABEL: define <4 x float> @shuffle_fma_const_chain(
; AVX-SAME: <4 x float> [[A0:%.*]]) #[[ATTR0:[0-9]+]] {
; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[A0]], <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; AVX-NEXT: [[RES:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
+; AVX-NEXT: [[RES:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> splat (float f0x3C6F4682), <4 x float> splat (float f0xBD9B8AF7))
; AVX-NEXT: ret <4 x float> [[RES]]
;
%f = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
@@ -24,7 +24,7 @@ define <8 x float> @concat_fma_const_chain(<4 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: define <8 x float> @concat_fma_const_chain(
; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[A0]], <4 x float> [[A1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> splat (float 0x3F8DE8D040000000), <8 x float> splat (float 0xBFB3715EE0000000))
+; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> splat (float f0x3C6F4682), <8 x float> splat (float f0xBD9B8AF7))
; CHECK-NEXT: ret <8 x float> [[RES]]
;
%l = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
@@ -36,15 +36,15 @@ define <8 x float> @concat_fma_const_chain(<4 x float> %a0, <4 x float> %a1) {
define <8 x float> @interleave_fma_const_chain(<4 x float> %a0, <4 x float> %a1) {
; SSE-LABEL: define <8 x float> @interleave_fma_const_chain(
; SSE-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) #[[ATTR0]] {
-; SSE-NEXT: [[L:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
-; SSE-NEXT: [[H:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A1]], <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
+; SSE-NEXT: [[L:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> splat (float f0x3C6F4682), <4 x float> splat (float f0xBD9B8AF7))
+; SSE-NEXT: [[H:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A1]], <4 x float> splat (float f0x3C6F4682), <4 x float> splat (float f0xBD9B8AF7))
; SSE-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[L]], <4 x float> [[H]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
; SSE-NEXT: ret <8 x float> [[RES]]
;
; AVX-LABEL: define <8 x float> @interleave_fma_const_chain(
; AVX-SAME: <4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) #[[ATTR0]] {
; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[A0]], <4 x float> [[A1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-; AVX-NEXT: [[RES:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> splat (float 0x3F8DE8D040000000), <8 x float> splat (float 0xBFB3715EE0000000))
+; AVX-NEXT: [[RES:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> splat (float f0x3C6F4682), <8 x float> splat (float f0xBD9B8AF7))
; AVX-NEXT: ret <8 x float> [[RES]]
;
%l = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> %a0, <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
@@ -57,7 +57,7 @@ define <8 x float> @interleave_fma_const_chain(<4 x float> %a0, <4 x float> %a1)
define <4 x float> @shuffle_fma_const_chain_multiuse(<4 x float> %a0, ptr %p) {
; CHECK-LABEL: define <4 x float> @shuffle_fma_const_chain_multiuse(
; CHECK-SAME: <4 x float> [[A0:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[F:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
+; CHECK-NEXT: [[F:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> splat (float f0x3C6F4682), <4 x float> splat (float f0xBD9B8AF7))
; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[F]], <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: store <4 x float> [[F]], ptr [[P]], align 16
; CHECK-NEXT: ret <4 x float> [[RES]]
@@ -72,7 +72,7 @@ define <4 x float> @shuffle_fma_const_chain_multiuse(<4 x float> %a0, ptr %p) {
define <4 x float> @shuffle_fma_multiuse_with_arith(<4 x float> %a0, <4 x float> %b) {
; CHECK-LABEL: define <4 x float> @shuffle_fma_multiuse_with_arith(
; CHECK-SAME: <4 x float> [[A0:%.*]], <4 x float> [[B:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[F:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> splat (float 0x3F8DE8D040000000), <4 x float> splat (float 0xBFB3715EE0000000))
+; CHECK-NEXT: [[F:%.*]] = tail call noundef <4 x float> @llvm.fma.v4f32(<4 x float> [[A0]], <4 x float> splat (float f0x3C6F4682), <4 x float> splat (float f0xBD9B8AF7))
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[F]], <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[F]], [[B]]
; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[SHUF]], [[ADD]]
diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
index 17a4a8d89c5c1..821e59a9bafb8 100644
--- a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
+++ b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
@@ -89,22 +89,22 @@ declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1,
define void @exp_compr_invalid_inputs(i32 %tgt, i32 %en, i1 %bool) {
; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i32 %en
- ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 %en, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 true, i1 false)
+ ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 %en, <2 x half> <half 1.000000e+00, half 2.000000e+00>, <2 x half> <half 5.000000e-01, half 4.000000e+00>, i1 true, i1 false)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 %en, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)
; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i32 %tgt
- ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 %tgt, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 true, i1 false)
+ ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 %tgt, i32 5, <2 x half> <half 1.000000e+00, half 2.000000e+00>, <2 x half> <half 5.000000e-01, half 4.000000e+00>, i1 true, i1 false)
call void @llvm.amdgcn.exp.compr.v2f16(i32 %tgt, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)
; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i1 %bool
- ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 %bool, i1 false)
+ ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 1.000000e+00, half 2.000000e+00>, <2 x half> <half 5.000000e-01, half 4.000000e+00>, i1 %bool, i1 false)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 %bool, i1 false)
; CHECK: immarg operand has non-immediate parameter
; CHECK-NEXT: i1 %bool
- ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 false, i1 %bool)
+ ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 1.000000e+00, half 2.000000e+00>, <2 x half> <half 5.000000e-01, half 4.000000e+00>, i1 false, i1 %bool)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 false, i1 %bool)
ret void
}
diff --git a/llvm/test/tools/llvm-reduce/reduce-operands-fp.ll b/llvm/test/tools/llvm-reduce/reduce-operands-fp.ll
index e10a3f8c010ce..022c97d60bb6c 100644
--- a/llvm/test/tools/llvm-reduce/reduce-operands-fp.ll
+++ b/llvm/test/tools/llvm-reduce/reduce-operands-fp.ll
@@ -60,19 +60,19 @@
; ZERO: %fadd12 = fadd <2 x float> zeroinitializer, zeroinitializer
-; NAN: %fadd0 = fadd float %arg0, 0x7FF8000000000000
-; NAN: %fadd1 = fadd float 0x7FF8000000000000, 0x7FF8000000000000
-; NAN: %fadd2 = fadd float 0x7FF8000000000000, 0.000000e+00
-; NAN: %fadd3 = fadd float 0x7FF8000000000000, 1.000000e+00
-; NAN: %fadd4 = fadd float 0x7FF8000000000000, 0x7FF8000000000000
-; NAN: %fadd5 = fadd float 0x7FF8000000000000, 0x7FF8000000000000
-; NAN: %fadd6 = fadd <2 x float> %arg2, splat (float 0x7FF8000000000000)
-; NAN: %fadd7 = fadd <2 x float> splat (float 0x7FF8000000000000), splat (float 0x7FF8000000000000)
-; NAN: %fadd8 = fadd <2 x float> splat (float 0x7FF8000000000000), zeroinitializer
-; NAN: %fadd9 = fadd <2 x float> splat (float 0x7FF8000000000000), splat (float 1.000000e+00)
-; NAN: %fadd10 = fadd <2 x float> splat (float 0x7FF8000000000000), splat (float 0x7FF8000000000000)
-; NAN: %fadd11 = fadd <2 x float> splat (float 0x7FF8000000000000), splat (float 0x7FF8000000000000)
-; NAN: %fadd12 = fadd <2 x float> splat (float 0x7FF8000000000000), splat (float 0x7FF8000000000000)
+; NAN: %fadd0 = fadd float %arg0, +qnan
+; NAN: %fadd1 = fadd float +qnan, +qnan
+; NAN: %fadd2 = fadd float +qnan, 0.000000e+00
+; NAN: %fadd3 = fadd float +qnan, 1.000000e+00
+; NAN: %fadd4 = fadd float +qnan, +qnan
+; NAN: %fadd5 = fadd float +qnan, +qnan
+; NAN: %fadd6 = fadd <2 x float> %arg2, splat (float +qnan)
+; NAN: %fadd7 = fadd <2 x float> splat (float +qnan), splat (float +qnan)
+; NAN: %fadd8 = fadd <2 x float> splat (float +qnan), zeroinitializer
+; NAN: %fadd9 = fadd <2 x float> splat (float +qnan), splat (float 1.000000e+00)
+; NAN: %fadd10 = fadd <2 x float> splat (float +qnan), splat (float +qnan)
+; NAN: %fadd11 = fadd <2 x float> splat (float +qnan), splat (float +qnan)
+; NAN: %fadd12 = fadd <2 x float> splat (float +qnan), splat (float +qnan)
define void @foo(float %arg0, float %arg1, <2 x float> %arg2, <2 x float> %arg3) {
bb0:
diff --git a/mlir/test/Target/LLVMIR/openmp-distribute-private.mlir b/mlir/test/Target/LLVMIR/openmp-distribute-private.mlir
index ef118e0ad1df2..75e7714ec24fb 100644
--- a/mlir/test/Target/LLVMIR/openmp-distribute-private.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-distribute-private.mlir
@@ -39,7 +39,7 @@ llvm.func @_QQmain() {
// CHECK: omp.loop_nest.region:
// CHECK-NEXT: store i32 %{{.*}}, ptr %[[IV_ALLOC]], align 4
-// CHECK-NEXT: store float 0x40091EB860000000, ptr %[[PRIV_VAR_ALLOC]], align 4
+// CHECK-NEXT: store float 3.140000e+00, ptr %[[PRIV_VAR_ALLOC]], align 4
// CHECK: }
// -----
@@ -82,7 +82,7 @@ llvm.func @_QQmain() {
// CHECK-NEXT: store float %[[SHARED_VAR_VAL]], ptr %[[PRIV_VAR_ALLOC]], align 4
// CHECK: omp.loop_nest.region:
-// CHECK-NEXT: store float 0x40091EB860000000, ptr %[[PRIV_VAR_ALLOC]], align 4
+// CHECK-NEXT: store float 3.140000e+00, ptr %[[PRIV_VAR_ALLOC]], align 4
// CHECK: omp_loop.after:
// CHECK-NEXT: br label %omp.region.cont
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