[Mlir-commits] [mlir] [MLIR][NVVM] Update SM version requirements of Ops (PR #192257)

[Durgadoss R]

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@@ -5075,7 +5075,8 @@ def Tcgen05WaitKindAttr :
   let assemblyFormat = "`<` $value `>`";
 }
 
-def NVVM_Tcgen05AllocOp : NVVM_Op<"tcgen05.alloc", [NVVMRequiresSMa<[100, 101]>]> {
+def NVVM_Tcgen05AllocOp : NVVM_Op<"tcgen05.alloc",
+    [NVVMRequiresSMaOrSMf<[100, 101, 110], [100, 101, 110]>]> {
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durga4github wrote:

ok, it seems like we should have had the option to use a single-list when both the arch-lists are same.
(since the trait-name itself says "SMaOrSMf"...)

https://github.com/llvm/llvm-project/pull/192257