[Mlir-commits] [clang] [clang-tools-extra] [compiler-rt] [flang] [libc] [libclc] [libcxx] [llvm] [mlir] [openmp] [X86] Truncates i64 add arithmetic to i32 when known zeroes in upper 33 bits (PR #191619)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Mon Apr 13 03:25:39 PDT 2026
=?utf-8?b?8J+NjFNoYXdu?= <m18824909883 at 163.com>,Wenju He <wenju.he at intel.com>,Wenju
He <wenju.he at intel.com>,Wenju He <wenju.he at intel.com>,Cullen Rhodes
<cullen.rhodes at arm.com>,Craig Topper <craig.topper at sifive.com>,Ryan Buchner
<rbuchner at qti.qualcomm.com>,Arun Thangamani <arun.thangamani at intel.com>,Luke
Lau <luke at igalia.com>,Amit Tiwari <amtiwari at amd.com>,David Green
<david.green at arm.com>,Chandana Mudda <quic_csinderi at quicinc.com>,Tomer
Shafir <tomer.shafir8 at gmail.com>,Luke Lau <luke at igalia.com>,Luke Hutton
<luke.hutton at arm.com>,Florian Hahn <flo at fhahn.com>,Mao Chuanjun
<10255501521 at stu.ecnu.edu.cn>,Timm Baeder <tbaeder at redhat.com>,Benjamin
Maxwell <benjamin.maxwell at arm.com>,Zorojuro <sawantsukumar at gmail.com>,Zorojuro
<sawantsukumar at gmail.com>,Younan Zhang <zyn7109 at gmail.com>,2elliti
<forstoic724321 at gmail.com>,Lang Hames <lhames at gmail.com>,eiytoq
<eiytoq at outlook.com>,Alexis Engelke <engelke at in.tum.de>,Muhammad Bassiouni
<60100307+bassiounix at users.noreply.github.com>,Matthew Nagy
<matthew.nagy at sony.com>,2elliti <forstoic724321 at gmail.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/191619 at github.com>
https://github.com/2elliti updated https://github.com/llvm/llvm-project/pull/191619
>From 570b5156eb816729aa5c872ea847603695ec783f Mon Sep 17 00:00:00 2001
From: 2elliti <forstoic724321 at gmail.com>
Date: Sat, 11 Apr 2026 16:35:22 +0530
Subject: [PATCH 01/36] [X86] Truncates i64 add arithmetic to i32 when known
zeroes in upper 33 bits
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 25 +++
llvm/test/CodeGen/X86/truncate-i64-add.ll | 178 ++++++++++++++++++++++
2 files changed, 203 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/truncate-i64-add.ll
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7ccfc412ff184..e2e6a5ad1d5e9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -59402,6 +59402,31 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
if (SDValue IFMA52 = matchVPMADD52(N, DAG, DL, VT, Subtarget))
return IFMA52;
+ // If upper 33 bits of operands are 0, truncates opcode from i64 to i32.
+ if (VT == MVT::i64) {
+ APInt mask = APInt::getHighBitsSet(64, 33);
+ if (DAG.MaskedValueIsZero(Op0, mask) && DAG.MaskedValueIsZero(Op1, mask)) {
+ // Truncate operands MVT::i64 -> MVT::i32
+ SDValue X = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op0);
+ SDValue Y = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
+
+ // now check for NUW and NSW
+ SDNodeFlags flags;
+ // No unsigned wrap, both operands has their upper 33bits 0, making their
+ // sum lower then max unsigned int32.
+ flags.setNoUnsignedWrap(true);
+ // Now check id node had NSW set true or false.
+ bool isNSW = N->getFlags().hasNoSignedWrap();
+
+ // Verify if new nodes has NSW.
+ isNSW = isNSW & DAG.willNotOverflowAdd(true, X, Y);
+ flags.setNoSignedWrap(isNSW);
+ auto addl = DAG.getNode(ISD::ADD, DL, MVT::i32, X, Y, flags);
+
+ return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, addl);
+ }
+ }
+
return combineAddOrSubToADCOrSBB(N, DL, DAG);
}
diff --git a/llvm/test/CodeGen/X86/truncate-i64-add.ll b/llvm/test/CodeGen/X86/truncate-i64-add.ll
new file mode 100644
index 0000000000000..b51e0d954163d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/truncate-i64-add.ll
@@ -0,0 +1,178 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64-LINUX
+; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=X64-WIN32
+
+; Both operands upper 33 bits are zero
+define i64 @test_add_i64_narrow(i64 %a, i64 %b) {
+; X86-LABEL: test_add_i64_narrow:
+; X86: # %bb.0:
+; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: andl %eax, %ecx
+; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LINUX-LABEL: test_add_i64_narrow:
+; X64-LINUX: # %bb.0:
+; X64-LINUX-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF
+; X64-LINUX-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
+; X64-LINUX-NEXT: leal (%rsi,%rdi), %eax
+; X64-LINUX-NEXT: retq
+;
+; X64-WIN32-LABEL: test_add_i64_narrow:
+; X64-WIN32: # %bb.0:
+; X64-WIN32-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-WIN32-NEXT: andl $2147483647, %edx # imm = 0x7FFFFFFF
+; X64-WIN32-NEXT: leal (%rdx,%rcx), %eax
+; X64-WIN32-NEXT: retq
+ %a_masked = and i64 %a, 2147483647
+ %b_masked = and i64 %b, 2147483647
+ %res = add i64 %a_masked, %b_masked
+ ret i64 %res
+}
+
+; Both operands zero-extended from i16, should truncate to 32-bit add
+define i64 @add_zext_i16(i16 %a, i16 %b) nounwind {
+; X86-LABEL: add_zext_i16:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LINUX-LABEL: add_zext_i16:
+; X64-LINUX: # %bb.0:
+; X64-LINUX-NEXT: movzwl %si, %ecx
+; X64-LINUX-NEXT: movzwl %di, %eax
+; X64-LINUX-NEXT: addl %ecx, %eax
+; X64-LINUX-NEXT: retq
+;
+; X64-WIN32-LABEL: add_zext_i16:
+; X64-WIN32: # %bb.0:
+; X64-WIN32-NEXT: movzwl %dx, %edx
+; X64-WIN32-NEXT: movzwl %cx, %eax
+; X64-WIN32-NEXT: addl %edx, %eax
+; X64-WIN32-NEXT: retq
+ %za = zext i16 %a to i64
+ %zb = zext i16 %b to i64
+ %sum = add nuw nsw i64 %za, %zb
+ ret i64 %sum
+}
+
+; One operand is a small constant
+define i64 @add_zext_i16_const(i16 %a) nounwind {
+; X86-LABEL: add_zext_i16_const:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl $42, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LINUX-LABEL: add_zext_i16_const:
+; X64-LINUX: # %bb.0:
+; X64-LINUX-NEXT: movzwl %di, %eax
+; X64-LINUX-NEXT: addl $42, %eax
+; X64-LINUX-NEXT: retq
+;
+; X64-WIN32-LABEL: add_zext_i16_const:
+; X64-WIN32: # %bb.0:
+; X64-WIN32-NEXT: movzwl %cx, %eax
+; X64-WIN32-NEXT: addl $42, %eax
+; X64-WIN32-NEXT: retq
+ %za = zext i16 %a to i64
+ %sum = add nuw nsw i64 %za, 42
+ ret i64 %sum
+}
+
+; Bit 32 set — must NOT truncate
+define i64 @add_bit32_set(i16 %a) nounwind {
+; X86-LABEL: add_bit32_set:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl $42, %eax
+; X86-NEXT: movl $1, %edx
+; X86-NEXT: retl
+;
+; X64-LINUX-LABEL: add_bit32_set:
+; X64-LINUX: # %bb.0:
+; X64-LINUX-NEXT: movzwl %di, %ecx
+; X64-LINUX-NEXT: movabsq $4294967338, %rax # imm = 0x10000002A
+; X64-LINUX-NEXT: addq %rcx, %rax
+; X64-LINUX-NEXT: retq
+;
+; X64-WIN32-LABEL: add_bit32_set:
+; X64-WIN32: # %bb.0:
+; X64-WIN32-NEXT: movzwl %cx, %ecx
+; X64-WIN32-NEXT: movabsq $4294967338, %rax # imm = 0x10000002A
+; X64-WIN32-NEXT: addq %rcx, %rax
+; X64-WIN32-NEXT: retq
+ %za = zext i16 %a to i64
+ %or = or i64 %za, 4294967296
+ %sum = add nuw nsw i64 %or, 42
+ ret i64 %sum
+}
+
+; Sign-extended — must NOT truncate
+define i64 @add_sext_i16(i16 %a, i16 %b) nounwind {
+; X86-LABEL: add_sext_i16:
+; X86: # %bb.0:
+; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: adcl $0, %edx
+; X86-NEXT: retl
+;
+; X64-LINUX-LABEL: add_sext_i16:
+; X64-LINUX: # %bb.0:
+; X64-LINUX-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-LINUX-NEXT: movswq %di, %rcx
+; X64-LINUX-NEXT: movzwl %si, %eax
+; X64-LINUX-NEXT: addq %rcx, %rax
+; X64-LINUX-NEXT: retq
+;
+; X64-WIN32-LABEL: add_sext_i16:
+; X64-WIN32: # %bb.0:
+; X64-WIN32-NEXT: movswq %cx, %rcx
+; X64-WIN32-NEXT: movzwl %dx, %eax
+; X64-WIN32-NEXT: addq %rcx, %rax
+; X64-WIN32-NEXT: retq
+ %sa = sext i16 %a to i64
+ %zb = zext i16 %b to i64
+ %sum = add nuw nsw i64 %sa, %zb
+ ret i64 %sum
+}
+
+; i8 source
+define i64 @test_i8_add(i8 %a, i8 %b) nounwind {
+; X86-LABEL: test_i8_add:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: retl
+;
+; X64-LINUX-LABEL: test_i8_add:
+; X64-LINUX: # %bb.0:
+; X64-LINUX-NEXT: movzbl %sil, %ecx
+; X64-LINUX-NEXT: movzbl %dil, %eax
+; X64-LINUX-NEXT: addl %ecx, %eax
+; X64-LINUX-NEXT: retq
+;
+; X64-WIN32-LABEL: test_i8_add:
+; X64-WIN32: # %bb.0:
+; X64-WIN32-NEXT: movzbl %dl, %edx
+; X64-WIN32-NEXT: movzbl %cl, %eax
+; X64-WIN32-NEXT: addl %edx, %eax
+; X64-WIN32-NEXT: retq
+ %za = zext i8 %a to i64
+ %zb = zext i8 %b to i64
+ %sum = add i64 %za, %zb ; no nuw/nsw — should still fire
+ ret i64 %sum
+}
>From 4ac21a2f563c5431bd10c1e2651c48bbdb401064 Mon Sep 17 00:00:00 2001
From: 2elliti <forstoic724321 at gmail.com>
Date: Mon, 13 Apr 2026 00:44:38 +0530
Subject: [PATCH 02/36] Address review feedback: simplify wrap flags and update
tests
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 14 +--
llvm/test/CodeGen/X86/truncate-i64-add.ll | 137 +++++++++-------------
2 files changed, 63 insertions(+), 88 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e2e6a5ad1d5e9..15c7264f61249 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -59411,19 +59411,15 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
SDValue Y = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
// now check for NUW and NSW
- SDNodeFlags flags;
+ SDNodeFlags Flags;
// No unsigned wrap, both operands has their upper 33bits 0, making their
// sum lower then max unsigned int32.
- flags.setNoUnsignedWrap(true);
- // Now check id node had NSW set true or false.
- bool isNSW = N->getFlags().hasNoSignedWrap();
+ Flags.setNoUnsignedWrap(true);
+ Flags.setNoSignedWrap(DAG.willNotOverflowAdd(true, X, Y));
- // Verify if new nodes has NSW.
- isNSW = isNSW & DAG.willNotOverflowAdd(true, X, Y);
- flags.setNoSignedWrap(isNSW);
- auto addl = DAG.getNode(ISD::ADD, DL, MVT::i32, X, Y, flags);
+ SDValue Add32 = DAG.getNode(ISD::ADD, DL, MVT::i32, X, Y, Flags);
- return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, addl);
+ return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Add32);
}
}
diff --git a/llvm/test/CodeGen/X86/truncate-i64-add.ll b/llvm/test/CodeGen/X86/truncate-i64-add.ll
index b51e0d954163d..1ea5374b91694 100644
--- a/llvm/test/CodeGen/X86/truncate-i64-add.ll
+++ b/llvm/test/CodeGen/X86/truncate-i64-add.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64-LINUX
-; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=X64-WIN32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
; Both operands upper 33 bits are zero
define i64 @test_add_i64_narrow(i64 %a, i64 %b) {
@@ -15,19 +14,12 @@ define i64 @test_add_i64_narrow(i64 %a, i64 %b) {
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
-; X64-LINUX-LABEL: test_add_i64_narrow:
-; X64-LINUX: # %bb.0:
-; X64-LINUX-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF
-; X64-LINUX-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
-; X64-LINUX-NEXT: leal (%rsi,%rdi), %eax
-; X64-LINUX-NEXT: retq
-;
-; X64-WIN32-LABEL: test_add_i64_narrow:
-; X64-WIN32: # %bb.0:
-; X64-WIN32-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-WIN32-NEXT: andl $2147483647, %edx # imm = 0x7FFFFFFF
-; X64-WIN32-NEXT: leal (%rdx,%rcx), %eax
-; X64-WIN32-NEXT: retq
+; X64-LABEL: test_add_i64_narrow:
+; X64: # %bb.0:
+; X64-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF
+; X64-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
+; X64-NEXT: leal (%rsi,%rdi), %eax
+; X64-NEXT: retq
%a_masked = and i64 %a, 2147483647
%b_masked = and i64 %b, 2147483647
%res = add i64 %a_masked, %b_masked
@@ -44,19 +36,12 @@ define i64 @add_zext_i16(i16 %a, i16 %b) nounwind {
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
-; X64-LINUX-LABEL: add_zext_i16:
-; X64-LINUX: # %bb.0:
-; X64-LINUX-NEXT: movzwl %si, %ecx
-; X64-LINUX-NEXT: movzwl %di, %eax
-; X64-LINUX-NEXT: addl %ecx, %eax
-; X64-LINUX-NEXT: retq
-;
-; X64-WIN32-LABEL: add_zext_i16:
-; X64-WIN32: # %bb.0:
-; X64-WIN32-NEXT: movzwl %dx, %edx
-; X64-WIN32-NEXT: movzwl %cx, %eax
-; X64-WIN32-NEXT: addl %edx, %eax
-; X64-WIN32-NEXT: retq
+; X64-LABEL: add_zext_i16:
+; X64: # %bb.0:
+; X64-NEXT: movzwl %si, %ecx
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
%za = zext i16 %a to i64
%zb = zext i16 %b to i64
%sum = add nuw nsw i64 %za, %zb
@@ -72,17 +57,11 @@ define i64 @add_zext_i16_const(i16 %a) nounwind {
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
-; X64-LINUX-LABEL: add_zext_i16_const:
-; X64-LINUX: # %bb.0:
-; X64-LINUX-NEXT: movzwl %di, %eax
-; X64-LINUX-NEXT: addl $42, %eax
-; X64-LINUX-NEXT: retq
-;
-; X64-WIN32-LABEL: add_zext_i16_const:
-; X64-WIN32: # %bb.0:
-; X64-WIN32-NEXT: movzwl %cx, %eax
-; X64-WIN32-NEXT: addl $42, %eax
-; X64-WIN32-NEXT: retq
+; X64-LABEL: add_zext_i16_const:
+; X64: # %bb.0:
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: addl $42, %eax
+; X64-NEXT: retq
%za = zext i16 %a to i64
%sum = add nuw nsw i64 %za, 42
ret i64 %sum
@@ -97,19 +76,12 @@ define i64 @add_bit32_set(i16 %a) nounwind {
; X86-NEXT: movl $1, %edx
; X86-NEXT: retl
;
-; X64-LINUX-LABEL: add_bit32_set:
-; X64-LINUX: # %bb.0:
-; X64-LINUX-NEXT: movzwl %di, %ecx
-; X64-LINUX-NEXT: movabsq $4294967338, %rax # imm = 0x10000002A
-; X64-LINUX-NEXT: addq %rcx, %rax
-; X64-LINUX-NEXT: retq
-;
-; X64-WIN32-LABEL: add_bit32_set:
-; X64-WIN32: # %bb.0:
-; X64-WIN32-NEXT: movzwl %cx, %ecx
-; X64-WIN32-NEXT: movabsq $4294967338, %rax # imm = 0x10000002A
-; X64-WIN32-NEXT: addq %rcx, %rax
-; X64-WIN32-NEXT: retq
+; X64-LABEL: add_bit32_set:
+; X64: # %bb.0:
+; X64-NEXT: movzwl %di, %ecx
+; X64-NEXT: movabsq $4294967338, %rax # imm = 0x10000002A
+; X64-NEXT: addq %rcx, %rax
+; X64-NEXT: retq
%za = zext i16 %a to i64
%or = or i64 %za, 4294967296
%sum = add nuw nsw i64 %or, 42
@@ -128,20 +100,13 @@ define i64 @add_sext_i16(i16 %a, i16 %b) nounwind {
; X86-NEXT: adcl $0, %edx
; X86-NEXT: retl
;
-; X64-LINUX-LABEL: add_sext_i16:
-; X64-LINUX: # %bb.0:
-; X64-LINUX-NEXT: # kill: def $edi killed $edi def $rdi
-; X64-LINUX-NEXT: movswq %di, %rcx
-; X64-LINUX-NEXT: movzwl %si, %eax
-; X64-LINUX-NEXT: addq %rcx, %rax
-; X64-LINUX-NEXT: retq
-;
-; X64-WIN32-LABEL: add_sext_i16:
-; X64-WIN32: # %bb.0:
-; X64-WIN32-NEXT: movswq %cx, %rcx
-; X64-WIN32-NEXT: movzwl %dx, %eax
-; X64-WIN32-NEXT: addq %rcx, %rax
-; X64-WIN32-NEXT: retq
+; X64-LABEL: add_sext_i16:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: movswq %di, %rcx
+; X64-NEXT: movzwl %si, %eax
+; X64-NEXT: addq %rcx, %rax
+; X64-NEXT: retq
%sa = sext i16 %a to i64
%zb = zext i16 %b to i64
%sum = add nuw nsw i64 %sa, %zb
@@ -158,21 +123,35 @@ define i64 @test_i8_add(i8 %a, i8 %b) nounwind {
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
-; X64-LINUX-LABEL: test_i8_add:
-; X64-LINUX: # %bb.0:
-; X64-LINUX-NEXT: movzbl %sil, %ecx
-; X64-LINUX-NEXT: movzbl %dil, %eax
-; X64-LINUX-NEXT: addl %ecx, %eax
-; X64-LINUX-NEXT: retq
-;
-; X64-WIN32-LABEL: test_i8_add:
-; X64-WIN32: # %bb.0:
-; X64-WIN32-NEXT: movzbl %dl, %edx
-; X64-WIN32-NEXT: movzbl %cl, %eax
-; X64-WIN32-NEXT: addl %edx, %eax
-; X64-WIN32-NEXT: retq
+; X64-LABEL: test_i8_add:
+; X64: # %bb.0:
+; X64-NEXT: movzbl %sil, %ecx
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
%za = zext i8 %a to i64
%zb = zext i8 %b to i64
%sum = add i64 %za, %zb ; no nuw/nsw — should still fire
ret i64 %sum
}
+
+define i64 @add_zext_i32(i32 %a, i32 %b) {
+; X86-LABEL: add_zext_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: setb %dl
+; X86-NEXT: retl
+;
+; X64-LABEL: add_zext_i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: addq %rcx, %rax
+; X64-NEXT: retq
+ %za = zext i32 %a to i64
+ %zb = zext i32 %b to i64
+ %sum = add i64 %za, %zb
+ ret i64 %sum
+}
>From 6adfbd04029bd325741b0b63196644059b13c509 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Sun, 12 Apr 2026 20:24:45 +0100
Subject: [PATCH 03/36] [VPlan] Handle calls in
VPInstruction:opcodeMayReadOrWriteFromMemory. (#190681)
Retrieve the called function and check its memory attributes, to
determine if a VPInstruction calling a function reads or writes memory.
Use it to strengthen assert in areAllLoadsDereferenceable.
PR: https://github.com/llvm/llvm-project/pull/190681
---
.../Vectorize/VPlanConstruction.cpp | 6 ++--
.../lib/Transforms/Vectorize/VPlanRecipes.cpp | 33 ++++++++++++++-----
2 files changed, 29 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
index c1df51841076f..c9234b88fb084 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
@@ -951,12 +951,14 @@ static bool areAllLoadsDereferenceable(VPBasicBlock *HeaderVPBB,
for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly<VPBasicBlock>(
vp_depth_first_shallow(HeaderVPBB))) {
// Skip blocks outside the loop (exit blocks and their successors).
- if (VPBB == MiddleVPBB)
+ if (VPBB == MiddleVPBB || isa<VPIRBasicBlock>(VPBB))
continue;
for (VPRecipeBase &R : *VPBB) {
auto *VPI = dyn_cast<VPInstructionWithType>(&R);
- if (!VPI || VPI->getOpcode() != Instruction::Load)
+ if (!VPI || VPI->getOpcode() != Instruction::Load) {
+ assert(!R.mayReadFromMemory() && "unexpected recipe reading memory");
continue;
+ }
// Get the pointer SCEV for dereferenceability checking.
VPValue *Ptr = VPI->getOperand(0);
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 2c2f3915c41d4..44aec2ce62bc9 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -440,6 +440,27 @@ VPInstruction::VPInstruction(unsigned Opcode, ArrayRef<VPValue *> Operands,
"number of operands does not match opcode");
}
+/// For call VPInstructions, return the operand index of the called function.
+/// The function is either the last operand (for unmasked calls) or the
+/// second-to-last operand (for masked calls).
+static unsigned getCalledFnOperandIndex(const VPInstruction &VPI) {
+ assert(VPI.getOpcode() == Instruction::Call && "must be a call");
+ unsigned NumOps = VPI.getNumOperands();
+ auto *LastOp = dyn_cast<VPIRValue>(VPI.getOperand(NumOps - 1));
+ if (LastOp && isa<Function>(LastOp->getValue()))
+ return NumOps - 1;
+ assert(
+ isa<Function>(cast<VPIRValue>(VPI.getOperand(NumOps - 2))->getValue()) &&
+ "expected function operand");
+ return NumOps - 2;
+}
+
+/// For call VPInstructions, return the called function.
+static Function *getCalledFunction(const VPInstruction &VPI) {
+ unsigned Idx = getCalledFnOperandIndex(VPI);
+ return cast<Function>(cast<VPIRValue>(VPI.getOperand(Idx))->getValue());
+}
+
unsigned VPInstruction::getNumOperandsForOpcode() const {
if (Instruction::isUnaryOp(Opcode) || Instruction::isCast(Opcode))
return 1;
@@ -486,14 +507,8 @@ unsigned VPInstruction::getNumOperandsForOpcode() const {
case VPInstruction::ActiveLaneMask:
case VPInstruction::ReductionStartVector:
return 3;
- case Instruction::Call: {
- // For unmasked calls, the last argument will the called function. Use that
- // to compute the number of operands without the mask.
- VPValue *LastOp = getOperand(getNumOperands() - 1);
- if (isa<VPIRValue>(LastOp) && isa<Function>(LastOp->getLiveInIRValue()))
- return getNumOperands();
- return getNumOperands() - 1;
- }
+ case Instruction::Call:
+ return getCalledFnOperandIndex(*this) + 1;
case Instruction::GetElementPtr:
case Instruction::PHI:
case Instruction::Switch:
@@ -1358,6 +1373,8 @@ bool VPInstruction::opcodeMayReadOrWriteFromMemory() const {
case VPInstruction::VScale:
case VPInstruction::Unpack:
return false;
+ case Instruction::Call:
+ return !getCalledFunction(*this)->doesNotAccessMemory();
default:
return true;
}
>From 628bd13a4e887a6afbcf1694ee12e1ec9c280f6c Mon Sep 17 00:00:00 2001
From: Timm Baeder <tbaeder at redhat.com>
Date: Sun, 12 Apr 2026 22:41:19 +0200
Subject: [PATCH 04/36] [clang][bytecode] Stop using QualTypes when checking
evaluation results (#191732)
They might not match the descriptor contents exactly, so just look at
the descriptors.
---
clang/lib/AST/ByteCode/EvaluationResult.cpp | 59 +++++++++------------
1 file changed, 25 insertions(+), 34 deletions(-)
diff --git a/clang/lib/AST/ByteCode/EvaluationResult.cpp b/clang/lib/AST/ByteCode/EvaluationResult.cpp
index 039848f00764e..5d1eb89a2ed6f 100644
--- a/clang/lib/AST/ByteCode/EvaluationResult.cpp
+++ b/clang/lib/AST/ByteCode/EvaluationResult.cpp
@@ -30,43 +30,35 @@ static bool CheckFieldsInitialized(InterpState &S, SourceLocation Loc,
const Pointer &BasePtr, const Record *R);
static bool CheckArrayInitialized(InterpState &S, SourceLocation Loc,
- const Pointer &BasePtr,
- const ConstantArrayType *CAT) {
- size_t NumElems = CAT->getZExtSize();
+ const Pointer &BasePtr) {
+ const Descriptor *BaseDesc = BasePtr.getFieldDesc();
+ assert(BaseDesc->isArray());
+ size_t NumElems = BaseDesc->getNumElems();
if (NumElems == 0)
return true;
bool Result = true;
- QualType ElemType = CAT->getElementType();
- if (ElemType->isRecordType()) {
- const Record *R = BasePtr.getElemRecord();
+ if (BaseDesc->isPrimitiveArray()) {
+ if (BasePtr.allElementsInitialized())
+ return true;
+ DiagnoseUninitializedSubobject(S, Loc, BasePtr.getField());
+ return false;
+ }
+ const Descriptor *ElemDesc = BaseDesc->ElemDesc;
+
+ if (ElemDesc->isRecord()) {
+ const Record *R = ElemDesc->ElemRecord;
for (size_t I = 0; I != NumElems; ++I) {
Pointer ElemPtr = BasePtr.atIndex(I).narrow();
Result &= CheckFieldsInitialized(S, Loc, ElemPtr, R);
}
- } else if (const auto *ElemCAT = dyn_cast<ConstantArrayType>(ElemType)) {
- for (size_t I = 0; I != NumElems; ++I) {
- Pointer ElemPtr = BasePtr.atIndex(I).narrow();
- Result &= CheckArrayInitialized(S, Loc, ElemPtr, ElemCAT);
- }
} else {
- // Primitive arrays.
- if (S.getContext().canClassify(ElemType)) {
- if (BasePtr.allElementsInitialized()) {
- return true;
- } else {
- DiagnoseUninitializedSubobject(S, Loc, BasePtr.getField());
- return false;
- }
- }
-
+ assert(ElemDesc->isArray());
for (size_t I = 0; I != NumElems; ++I) {
- if (!BasePtr.isElementInitialized(I)) {
- DiagnoseUninitializedSubobject(S, Loc, BasePtr.getField());
- Result = false;
- }
+ Pointer ElemPtr = BasePtr.atIndex(I).narrow();
+ Result &= CheckArrayInitialized(S, Loc, ElemPtr);
}
}
@@ -80,22 +72,22 @@ static bool CheckFieldsInitialized(InterpState &S, SourceLocation Loc,
// Check all fields of this record are initialized.
for (const Record::Field &F : R->fields()) {
Pointer FieldPtr = BasePtr.atField(F.Offset);
- QualType FieldType = F.Decl->getType();
// Don't check inactive union members.
if (R->isUnion() && !FieldPtr.isActive())
continue;
- if (FieldType->isRecordType()) {
+ QualType FieldType = F.Decl->getType();
+ const Descriptor *FieldDesc = FieldPtr.getFieldDesc();
+
+ if (FieldDesc->isRecord()) {
Result &= CheckFieldsInitialized(S, Loc, FieldPtr, FieldPtr.getRecord());
} else if (FieldType->isIncompleteArrayType()) {
// Nothing to do here.
} else if (F.Decl->isUnnamedBitField()) {
// Nothing do do here.
- } else if (FieldType->isArrayType()) {
- const auto *CAT =
- cast<ConstantArrayType>(FieldType->getAsArrayTypeUnsafe());
- Result &= CheckArrayInitialized(S, Loc, FieldPtr, CAT);
+ } else if (FieldDesc->isArray()) {
+ Result &= CheckArrayInitialized(S, Loc, FieldPtr);
} else if (!FieldPtr.isInitialized()) {
DiagnoseUninitializedSubobject(S, Loc, F.Decl);
Result = false;
@@ -150,9 +142,8 @@ bool EvaluationResult::checkFullyInitialized(InterpState &S,
if (const Record *R = Ptr.getRecord())
return CheckFieldsInitialized(S, InitLoc, Ptr, R);
- if (const auto *CAT = dyn_cast_if_present<ConstantArrayType>(
- Ptr.getType()->getAsArrayTypeUnsafe()))
- return CheckArrayInitialized(S, InitLoc, Ptr, CAT);
+ if (isa_and_nonnull<ConstantArrayType>(Ptr.getType()->getAsArrayTypeUnsafe()))
+ return CheckArrayInitialized(S, InitLoc, Ptr);
return true;
}
>From c1cb4889810e0bb6bd3888b289a8977810f91306 Mon Sep 17 00:00:00 2001
From: Robert Imschweiler <robert.imschweiler at amd.com>
Date: Sun, 12 Apr 2026 23:03:59 +0200
Subject: [PATCH 05/36] [CallGraphUpdater] Replace dead function in metadata
with null instead of poison (#191729)
Assisted-by: claude-4.6-opus
---
.../lib/Transforms/Utils/CallGraphUpdater.cpp | 7 ++++-
.../Inline/inline-history-dead-function.ll | 29 +++++++++++++++++++
2 files changed, 35 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/Transforms/Inline/inline-history-dead-function.ll
diff --git a/llvm/lib/Transforms/Utils/CallGraphUpdater.cpp b/llvm/lib/Transforms/Utils/CallGraphUpdater.cpp
index 3b6fce578ffcc..46823c387be63 100644
--- a/llvm/lib/Transforms/Utils/CallGraphUpdater.cpp
+++ b/llvm/lib/Transforms/Utils/CallGraphUpdater.cpp
@@ -29,7 +29,12 @@ bool CallGraphUpdater::finalize() {
// no call graph was provided.
for (Function *DeadFn : DeadFunctions) {
DeadFn->removeDeadConstantUsers();
- DeadFn->replaceAllUsesWith(PoisonValue::get(DeadFn->getType()));
+ // If the function is used by metadata, we don't want it to be replaced with
+ // poison in the metadata, so we replace it with nullptr in the metadata
+ // before RAUW'ing the non-metadata uses below.
+ if (DeadFn->isUsedByMetadata())
+ ValueAsMetadata::handleDeletion(DeadFn);
+ DeadFn->replaceNonMetadataUsesWith(PoisonValue::get(DeadFn->getType()));
if (LCG && !ReplacedFunctions.count(DeadFn)) {
// Taken mostly from the inliner:
diff --git a/llvm/test/Transforms/Inline/inline-history-dead-function.ll b/llvm/test/Transforms/Inline/inline-history-dead-function.ll
new file mode 100644
index 0000000000000..367b0f70d07ac
--- /dev/null
+++ b/llvm/test/Transforms/Inline/inline-history-dead-function.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=attributor -S < %s 2>&1 | FileCheck %s
+
+; When a function referenced in !inline_history metadata is deleted by a pass
+; that uses CallGraphUpdater (e.g. Attributor), the function must not simply
+; get RAUW'd with poison before being erased. Reason: this causes the
+; !inline_history metadata to contain "ptr poison" instead of null, which would
+; be the correct choice.
+; This test verifies that the metadata contains null instead of poison.
+
+define internal void @dead_fn() {
+ unreachable
+}
+
+define void @live_fn() {
+; CHECK-LABEL: define void @live_fn() {
+; CHECK-NEXT: call void @ext(), !inline_history [[META0:![0-9]+]]
+; CHECK-NEXT: ret void
+;
+ call void @ext(), !inline_history !0
+ ret void
+}
+
+declare void @ext()
+
+!0 = !{ptr @dead_fn}
+;.
+; CHECK: [[META0]] = distinct !{null}
+;.
>From 0f90bbeadbad61d8901274658f085735632beb60 Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Sun, 12 Apr 2026 14:42:15 -0700
Subject: [PATCH 06/36] [NFC][LLVM] Rename IRBuilder/LLVM C API params for
overload types (#191674)
Rename IRBuilder and LLVM C API function params for overload types to
use names to better reflect their meaning.
---
llvm/include/llvm-c/Core.h | 24 ++++++++++-----------
llvm/include/llvm/IR/IRBuilder.h | 9 ++++----
llvm/lib/IR/Core.cpp | 37 +++++++++++++++++---------------
llvm/lib/IR/IRBuilder.cpp | 4 ++--
4 files changed, 39 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h
index 7f648dd53d9f7..86f636c636783 100644
--- a/llvm/include/llvm-c/Core.h
+++ b/llvm/include/llvm-c/Core.h
@@ -3147,25 +3147,25 @@ LLVM_C_ABI unsigned LLVMLookupIntrinsicID(const char *Name, size_t NameLen);
LLVM_C_ABI unsigned LLVMGetIntrinsicID(LLVMValueRef Fn);
/**
- * Get or insert the declaration of an intrinsic. For overloaded intrinsics,
- * parameter types must be provided to uniquely identify an overload.
+ * Get or insert the declaration of an intrinsic. For overloaded intrinsics,
+ * overload types must be provided to uniquely identify an overload.
*
* @see llvm::Intrinsic::getOrInsertDeclaration()
*/
LLVM_C_ABI LLVMValueRef LLVMGetIntrinsicDeclaration(LLVMModuleRef Mod,
unsigned ID,
- LLVMTypeRef *ParamTypes,
- size_t ParamCount);
+ LLVMTypeRef *OverloadTypes,
+ size_t OverloadCount);
/**
- * Retrieves the type of an intrinsic. For overloaded intrinsics, parameter
+ * Retrieves the type of an intrinsic. For overloaded intrinsics, overload
* types must be provided to uniquely identify an overload.
*
* @see llvm::Intrinsic::getType()
*/
LLVM_C_ABI LLVMTypeRef LLVMIntrinsicGetType(LLVMContextRef Ctx, unsigned ID,
- LLVMTypeRef *ParamTypes,
- size_t ParamCount);
+ LLVMTypeRef *OverloadTypes,
+ size_t OverloadCount);
/**
* Retrieves the name of an intrinsic.
@@ -3176,13 +3176,13 @@ LLVM_C_ABI const char *LLVMIntrinsicGetName(unsigned ID, size_t *NameLength);
/** Deprecated: Use LLVMIntrinsicCopyOverloadedName2 instead. */
LLVM_C_ABI char *LLVMIntrinsicCopyOverloadedName(unsigned ID,
- LLVMTypeRef *ParamTypes,
- size_t ParamCount,
+ LLVMTypeRef *OverloadTypes,
+ size_t OverloadCount,
size_t *NameLength);
/**
* Copies the name of an overloaded intrinsic identified by a given list of
- * parameter types.
+ * overload types.
*
* Unlike LLVMIntrinsicGetName, the caller is responsible for freeing the
* returned string.
@@ -3193,8 +3193,8 @@ LLVM_C_ABI char *LLVMIntrinsicCopyOverloadedName(unsigned ID,
*/
LLVM_C_ABI char *LLVMIntrinsicCopyOverloadedName2(LLVMModuleRef Mod,
unsigned ID,
- LLVMTypeRef *ParamTypes,
- size_t ParamCount,
+ LLVMTypeRef *OverloadTypes,
+ size_t OverloadCount,
size_t *NameLength);
/**
diff --git a/llvm/include/llvm/IR/IRBuilder.h b/llvm/include/llvm/IR/IRBuilder.h
index 4ed3d73c4a057..bdec42516b8cd 100644
--- a/llvm/include/llvm/IR/IRBuilder.h
+++ b/llvm/include/llvm/IR/IRBuilder.h
@@ -1011,10 +1011,11 @@ class IRBuilderBase {
Value *RHS, FMFSource FMFSource = {},
const Twine &Name = "");
- /// Create a call to intrinsic \p ID with \p Args, mangled using \p Types. If
- /// \p FMFSource is provided, copy fast-math-flags from that instruction to
- /// the intrinsic.
- LLVM_ABI CallInst *CreateIntrinsic(Intrinsic::ID ID, ArrayRef<Type *> Types,
+ /// Create a call to intrinsic \p ID with \p Args, mangled using
+ /// \p OverloadTypes. If \p FMFSource is provided, copy fast-math-flags from
+ /// that instruction to the intrinsic.
+ LLVM_ABI CallInst *CreateIntrinsic(Intrinsic::ID ID,
+ ArrayRef<Type *> OverloadTypes,
ArrayRef<Value *> Args,
FMFSource FMFSource = {},
const Twine &Name = "");
diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp
index ba5d1c5c486d6..5e6b03d01b6ba 100644
--- a/llvm/lib/IR/Core.cpp
+++ b/llvm/lib/IR/Core.cpp
@@ -2552,13 +2552,13 @@ static Intrinsic::ID llvm_map_to_intrinsic_id(unsigned ID) {
return llvm::Intrinsic::ID(ID);
}
-LLVMValueRef LLVMGetIntrinsicDeclaration(LLVMModuleRef Mod,
- unsigned ID,
- LLVMTypeRef *ParamTypes,
- size_t ParamCount) {
- ArrayRef<Type*> Tys(unwrap(ParamTypes), ParamCount);
+LLVMValueRef LLVMGetIntrinsicDeclaration(LLVMModuleRef Mod, unsigned ID,
+ LLVMTypeRef *OverloadTypes,
+ size_t OverloadCount) {
+ ArrayRef<Type *> OverloadTys(unwrap(OverloadTypes), OverloadCount);
auto IID = llvm_map_to_intrinsic_id(ID);
- return wrap(llvm::Intrinsic::getOrInsertDeclaration(unwrap(Mod), IID, Tys));
+ return wrap(
+ llvm::Intrinsic::getOrInsertDeclaration(unwrap(Mod), IID, OverloadTys));
}
const char *LLVMIntrinsicGetName(unsigned ID, size_t *NameLength) {
@@ -2569,27 +2569,30 @@ const char *LLVMIntrinsicGetName(unsigned ID, size_t *NameLength) {
}
LLVMTypeRef LLVMIntrinsicGetType(LLVMContextRef Ctx, unsigned ID,
- LLVMTypeRef *ParamTypes, size_t ParamCount) {
+ LLVMTypeRef *OverloadTypes,
+ size_t OverloadCount) {
auto IID = llvm_map_to_intrinsic_id(ID);
- ArrayRef<Type*> Tys(unwrap(ParamTypes), ParamCount);
- return wrap(llvm::Intrinsic::getType(*unwrap(Ctx), IID, Tys));
+ ArrayRef<Type *> OverloadTys(unwrap(OverloadTypes), OverloadCount);
+ return wrap(llvm::Intrinsic::getType(*unwrap(Ctx), IID, OverloadTys));
}
-char *LLVMIntrinsicCopyOverloadedName(unsigned ID, LLVMTypeRef *ParamTypes,
- size_t ParamCount, size_t *NameLength) {
+char *LLVMIntrinsicCopyOverloadedName(unsigned ID, LLVMTypeRef *OverloadTypes,
+ size_t OverloadCount,
+ size_t *NameLength) {
auto IID = llvm_map_to_intrinsic_id(ID);
- ArrayRef<Type*> Tys(unwrap(ParamTypes), ParamCount);
- auto Str = llvm::Intrinsic::getNameNoUnnamedTypes(IID, Tys);
+ ArrayRef<Type *> OverloadTys(unwrap(OverloadTypes), OverloadCount);
+ auto Str = llvm::Intrinsic::getNameNoUnnamedTypes(IID, OverloadTys);
*NameLength = Str.length();
return strdup(Str.c_str());
}
char *LLVMIntrinsicCopyOverloadedName2(LLVMModuleRef Mod, unsigned ID,
- LLVMTypeRef *ParamTypes,
- size_t ParamCount, size_t *NameLength) {
+ LLVMTypeRef *OverloadTypes,
+ size_t OverloadCount,
+ size_t *NameLength) {
auto IID = llvm_map_to_intrinsic_id(ID);
- ArrayRef<Type *> Tys(unwrap(ParamTypes), ParamCount);
- auto Str = llvm::Intrinsic::getName(IID, Tys, unwrap(Mod));
+ ArrayRef<Type *> OverloadTys(unwrap(OverloadTypes), OverloadCount);
+ auto Str = llvm::Intrinsic::getName(IID, OverloadTys, unwrap(Mod));
*NameLength = Str.length();
return strdup(Str.c_str());
}
diff --git a/llvm/lib/IR/IRBuilder.cpp b/llvm/lib/IR/IRBuilder.cpp
index 4c6f2326fe149..8b8f8e68ee2b9 100644
--- a/llvm/lib/IR/IRBuilder.cpp
+++ b/llvm/lib/IR/IRBuilder.cpp
@@ -927,12 +927,12 @@ Value *IRBuilderBase::CreateBinaryIntrinsic(Intrinsic::ID ID, Value *LHS,
}
CallInst *IRBuilderBase::CreateIntrinsic(Intrinsic::ID ID,
- ArrayRef<Type *> Types,
+ ArrayRef<Type *> OverloadTypes,
ArrayRef<Value *> Args,
FMFSource FMFSource,
const Twine &Name) {
Module *M = BB->getModule();
- Function *Fn = Intrinsic::getOrInsertDeclaration(M, ID, Types);
+ Function *Fn = Intrinsic::getOrInsertDeclaration(M, ID, OverloadTypes);
return createCallHelper(Fn, Args, Name, FMFSource);
}
>From f17aad5ffdb5485679aa5c0c43938578fd11d2e6 Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Sun, 12 Apr 2026 14:44:43 -0700
Subject: [PATCH 07/36] [LLVM][Intrinsics] Eliminate range check for IIT table
in `DecodeIITType` (#190260)
`DecodeIITType` does a range check each time the next entry from the IIT
encoding table is read. This is required to handle IIT encodings that
are in-lined into the `IIT_Table` entries, since the `IITEntries` array
in `getIntrinsicInfoTableEntries` is terminated after the last non-zero
nibble is seen in the inlined encoding (but that may not be the actual
end). Change this code to instead have the `IITEntries` array for the
inlined case point to the full `IITValues` array payload + a IIT_Done
terminator, so that such entries look exactly like they would if they
were encoded in the long encoding table and then remove the range check
in `DecodeIITType` to streamline that code a bit.
Additionally, change some use if 0s (in loop conditions and default
constructed terminator in the IIT long encoding table) to explicitly use
IIT_Done to clarify the code better.
Also use `consume_front()` in a few places instead of `front()` followed
by `slice(1)`.
---
llvm/lib/IR/Intrinsics.cpp | 53 ++++++++++---------
.../utils/TableGen/Basic/IntrinsicEmitter.cpp | 8 ++-
2 files changed, 34 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/IR/Intrinsics.cpp b/llvm/lib/IR/Intrinsics.cpp
index 0e01529bda711..0220d74ca9f12 100644
--- a/llvm/lib/IR/Intrinsics.cpp
+++ b/llvm/lib/IR/Intrinsics.cpp
@@ -202,6 +202,8 @@ enum IIT_Info {
#include "llvm/IR/IntrinsicImpl.inc"
};
+static_assert(IIT_Done == 0, "IIT_Done expected to be 0");
+
static void
DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
IIT_Info LastInfo,
@@ -354,42 +356,39 @@ DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
IITDescriptor::get(IITDescriptor::Pointer, Infos[NextElt++]));
return;
case IIT_ANY: {
- unsigned OverloadInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned OverloadInfo = Infos[NextElt++];
OutputTable.push_back(
IITDescriptor::get(IITDescriptor::Overloaded, OverloadInfo));
return;
}
case IIT_EXTEND_ARG: {
- unsigned OverloadIndex = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned OverloadIndex = Infos[NextElt++];
OutputTable.push_back(
IITDescriptor::get(IITDescriptor::Extend, OverloadIndex));
return;
}
case IIT_TRUNC_ARG: {
- unsigned OverloadIndex = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned OverloadIndex = Infos[NextElt++];
OutputTable.push_back(
IITDescriptor::get(IITDescriptor::Trunc, OverloadIndex));
return;
}
case IIT_ONE_NTH_ELTS_VEC_ARG: {
- unsigned short OverloadIndex =
- (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
- unsigned short N = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned short OverloadIndex = Infos[NextElt++];
+ unsigned short N = Infos[NextElt++];
OutputTable.push_back(IITDescriptor::get(IITDescriptor::OneNthEltsVec,
/*Hi=*/N, /*Lo=*/OverloadIndex));
return;
}
case IIT_SAME_VEC_WIDTH_ARG: {
- unsigned OverloadIndex = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned OverloadIndex = Infos[NextElt++];
OutputTable.push_back(
IITDescriptor::get(IITDescriptor::SameVecWidth, OverloadIndex));
return;
}
case IIT_VEC_OF_ANYPTRS_TO_ELT: {
- unsigned short OverloadIndex =
- (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
- unsigned short RefOverloadIndex =
- (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned short OverloadIndex = Infos[NextElt++];
+ unsigned short RefOverloadIndex = Infos[NextElt++];
OutputTable.push_back(IITDescriptor::get(IITDescriptor::VecOfAnyPtrsToElt,
/*Hi=*/RefOverloadIndex,
/*Lo=*/OverloadIndex));
@@ -409,19 +408,19 @@ DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
return;
}
case IIT_SUBDIVIDE2_ARG: {
- unsigned OverloadIndex = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned OverloadIndex = Infos[NextElt++];
OutputTable.push_back(
IITDescriptor::get(IITDescriptor::Subdivide2, OverloadIndex));
return;
}
case IIT_SUBDIVIDE4_ARG: {
- unsigned OverloadIndex = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned OverloadIndex = Infos[NextElt++];
OutputTable.push_back(
IITDescriptor::get(IITDescriptor::Subdivide4, OverloadIndex));
return;
}
case IIT_VEC_ELEMENT: {
- unsigned OverloadIndex = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned OverloadIndex = Infos[NextElt++];
OutputTable.push_back(
IITDescriptor::get(IITDescriptor::VecElement, OverloadIndex));
return;
@@ -431,7 +430,7 @@ DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
return;
}
case IIT_VEC_OF_BITCASTS_TO_INT: {
- unsigned OverloadIndex = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned OverloadIndex = Infos[NextElt++];
OutputTable.push_back(
IITDescriptor::get(IITDescriptor::VecOfBitcastsToInt, OverloadIndex));
return;
@@ -457,8 +456,13 @@ void Intrinsic::getIntrinsicInfoTableEntries(
// Array to hold the inlined fixed encoding values expanded from nibbles to
// bytes. Its size can be be atmost FixedEncodingBits / 4 i.e., number
- // of nibbles that can fit in `FixedEncodingTy`.
- unsigned char IITValues[FixedEncodingBits / 4];
+ // of nibbles that can fit in `FixedEncodingTy` + 1 (the IIT_Done terminator
+ // that is not explicitly encoded). Note that if there are trailing 0 bytes
+ // in the encoding (for example, payload following one of the IIT tokens),
+ // the inlined encoding does not encode the actual size of the encoding, so
+ // we always assume its size of this maximum length possible, followed by the
+ // IIT_Done terminator token (whose value is 0).
+ unsigned char IITValues[FixedEncodingBits / 4 + 1] = {0};
ArrayRef<unsigned char> IITEntries;
unsigned NextElt = 0;
@@ -478,13 +482,13 @@ void Intrinsic::getIntrinsicInfoTableEntries(
TableVal >>= 4;
} while (TableVal);
- IITEntries = ArrayRef(IITValues).take_front(NextElt);
+ IITEntries = IITValues;
NextElt = 0;
}
// Okay, decode the table into the output vector of IITDescriptors.
DecodeIITType(NextElt, IITEntries, IIT_Done, T);
- while (NextElt != IITEntries.size() && IITEntries[NextElt] != 0)
+ while (IITEntries[NextElt] != IIT_Done)
DecodeIITType(NextElt, IITEntries, IIT_Done, T);
}
@@ -493,8 +497,7 @@ static Type *DecodeFixedType(ArrayRef<Intrinsic::IITDescriptor> &Infos,
LLVMContext &Context) {
using namespace Intrinsic;
- IITDescriptor D = Infos.front();
- Infos = Infos.slice(1);
+ IITDescriptor D = Infos.consume_front();
switch (D.Kind) {
case IITDescriptor::Void:
@@ -862,8 +865,7 @@ matchIntrinsicType(Type *Ty, ArrayRef<Intrinsic::IITDescriptor> &Infos,
return false;
};
- IITDescriptor D = Infos.front();
- Infos = Infos.slice(1);
+ IITDescriptor D = Infos.consume_front();
switch (D.Kind) {
case IITDescriptor::Void:
@@ -997,7 +999,7 @@ matchIntrinsicType(Type *Ty, ArrayRef<Intrinsic::IITDescriptor> &Infos,
case IITDescriptor::SameVecWidth: {
if (D.getOverloadIndex() >= OverloadTys.size()) {
// Defer check and subsequent check for the vector element type.
- Infos = Infos.slice(1);
+ Infos.consume_front();
return IsDeferredCheck || DeferCheck(Ty);
}
auto *ReferenceType =
@@ -1114,8 +1116,7 @@ bool Intrinsic::matchIntrinsicVarArg(
return true;
// Check and verify the descriptor.
- IITDescriptor D = Infos.front();
- Infos = Infos.slice(1);
+ IITDescriptor D = Infos.consume_front();
if (D.Kind == IITDescriptor::VarArg)
return !isVarArg;
diff --git a/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp b/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
index bda911b50d813..85524981a2a57 100644
--- a/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
@@ -224,6 +224,8 @@ void IntrinsicEmitter::EmitIITInfo(raw_ostream &OS) {
RecsByNumber[Number] = Rec->getName();
}
if (IIT_Base.size() > 0) {
+ if (RecsByNumber[0] != "IIT_Done")
+ PrintFatalError("IIT_Done expected to have value 0");
for (unsigned I = 0, E = RecsByNumber.size(); I < E; ++I)
if (!RecsByNumber[I].empty())
OS << " " << RecsByNumber[I] << " = " << I << ",\n";
@@ -351,7 +353,11 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
// If we can compute a 16/32-bit fixed encoding for this intrinsic, do so and
// capture it in this vector, otherwise store a ~0U.
std::vector<FixedEncodingTy> FixedEncodings;
- SequenceToOffsetTable<TypeSigTy> LongEncodingTable;
+
+ // Each IIT encoding sequence in the long encoding table is terminated by
+ // IIT_Done(=0) token.
+ constexpr unsigned char IIT_Done = 0;
+ SequenceToOffsetTable<TypeSigTy> LongEncodingTable(IIT_Done);
FixedEncodings.reserve(Ints.size());
>From 0835e065d1d447ea2c54d4b9996f994815581ed7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=F0=9F=8D=8CShawn?= <m18824909883 at 163.com>
Date: Mon, 13 Apr 2026 07:52:40 +0800
Subject: [PATCH 08/36] [flang][NFC] Fix typo in comment for multi-image
environment (#191722)
---
flang/lib/Optimizer/Transforms/MIFOpConversion.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/flang/lib/Optimizer/Transforms/MIFOpConversion.cpp b/flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
index 81dbd67e66620..9c6c9a0b7cd49 100644
--- a/flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
+++ b/flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
@@ -226,7 +226,7 @@ struct MIFInitOpConversion : public mlir::OpRewritePattern<mif::InitOp> {
builder, loc, errorFunc.getFunctionType(), failImageOp);
fir::CallOp::create(builder, loc, failImageFunc, args3);
- // Intialize the multi-image parallel environment
+ // Initialize the multi-image parallel environment
mlir::FunctionType ftype = mlir::FunctionType::get(
builder.getContext(),
/*inputs*/ {builder.getRefType(i32Ty)}, /*results*/ {});
>From 9357d1c92df32595a1cb863cd55138e6d31f77f1 Mon Sep 17 00:00:00 2001
From: Wenju He <wenju.he at intel.com>
Date: Mon, 13 Apr 2026 08:16:06 +0800
Subject: [PATCH 09/36] [libclc] Refine generic __clc_get_sub_group_size with
fast full sub-group path (#188895)
Add a fast path for the common case that total work-group size is
multiple of max sub-group size.
The fallback path is ported from amdgpu/workitem/clc_get_sub_group_size.cl.
Compiler can generate predicated instructions for the fallback path to
avoid branches.
---
.../workitem/clc_get_sub_group_size.cl | 24 +++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/libclc/clc/lib/generic/workitem/clc_get_sub_group_size.cl b/libclc/clc/lib/generic/workitem/clc_get_sub_group_size.cl
index 7944486aac0f0..7f96fc8c31717 100644
--- a/libclc/clc/lib/generic/workitem/clc_get_sub_group_size.cl
+++ b/libclc/clc/lib/generic/workitem/clc_get_sub_group_size.cl
@@ -6,21 +6,21 @@
//
//===----------------------------------------------------------------------===//
+#include "clc/shared/clc_min.h"
+#include "clc/workitem/clc_get_local_linear_id.h"
#include "clc/workitem/clc_get_local_size.h"
#include "clc/workitem/clc_get_max_sub_group_size.h"
-#include "clc/workitem/clc_get_num_sub_groups.h"
-#include "clc/workitem/clc_get_sub_group_id.h"
#include "clc/workitem/clc_get_sub_group_size.h"
_CLC_OVERLOAD _CLC_DEF uint __clc_get_sub_group_size() {
- if (__clc_get_sub_group_id() != __clc_get_num_sub_groups() - 1) {
- return __clc_get_max_sub_group_size();
- }
- size_t size_x = __clc_get_local_size(0);
- size_t size_y = __clc_get_local_size(1);
- size_t size_z = __clc_get_local_size(2);
- size_t linear_size = size_z * size_y * size_x;
- size_t uniform_groups = __clc_get_num_sub_groups() - 1;
- size_t uniform_size = __clc_get_max_sub_group_size() * uniform_groups;
- return linear_size - uniform_size;
+ uint local_linear_size = (uint)__clc_get_local_size(0) *
+ (uint)__clc_get_local_size(1) *
+ (uint)__clc_get_local_size(2);
+ uint max_sg_size = __clc_get_max_sub_group_size();
+ // Assume max_sg_size is power of 2.
+ uint remainder = local_linear_size & (max_sg_size - 1);
+ if (remainder == 0)
+ return max_sg_size;
+ uint lid = (uint)__clc_get_local_linear_id();
+ return __clc_min(max_sg_size, local_linear_size - (lid & ~(max_sg_size - 1)));
}
>From 0c4e4ec8dde75c11a1d15b1cf3a19bdbc850c916 Mon Sep 17 00:00:00 2001
From: Wenju He <wenju.he at intel.com>
Date: Mon, 13 Apr 2026 08:18:28 +0800
Subject: [PATCH 10/36] [LSR] Use TTI to check if zero-start IV is free in
getSetupCost (#190587)
This avoids a downstream regression where LSR prefers {-1,+1}.
When constant zero typically doesn't require preheader initialization
(queried via TTI::getIntImmCost), consider it as free in getSetupCost.
Three test changes are improvements: amx-across-func.ll,
2011-11-29-postincphi.ll and pr62660-normalization-failure.ll.
Other test changes are neutral.
---
.../Transforms/Scalar/LoopStrengthReduce.cpp | 24 ++++++++++++-------
llvm/test/CodeGen/X86/AMX/amx-across-func.ll | 10 ++++----
.../RISCV/lsr-drop-solution-dbg-msg.ll | 2 +-
.../X86/2011-11-29-postincphi.ll | 10 ++++----
.../X86/postinc-iv-used-by-urem-and-udiv.ll | 8 +++----
.../X86/pr62660-normalization-failure.ll | 13 +++++-----
.../LoopStrengthReduce/duplicated-phis.ll | 8 +++----
7 files changed, 39 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index 5421cad31c3ba..01322c26aa77e 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -1366,23 +1366,31 @@ static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
bool HasBaseReg, int64_t Scale,
Instruction *Fixup = nullptr);
-static unsigned getSetupCost(const SCEV *Reg, unsigned Depth) {
- if (isa<SCEVUnknown>(Reg) || isa<SCEVConstant>(Reg))
+static unsigned getSetupCost(const SCEV *Reg, unsigned Depth,
+ const TargetTransformInfo &TTI) {
+ if (isa<SCEVUnknown>(Reg))
return 1;
+ if (const auto *C = dyn_cast<SCEVConstant>(Reg)) {
+ if (TTI.getIntImmCost(C->getAPInt(), C->getType(),
+ TargetTransformInfo::TCK_RecipThroughput) ==
+ TargetTransformInfo::TCC_Free)
+ return 0;
+ return 1;
+ }
if (Depth == 0)
return 0;
if (const auto *S = dyn_cast<SCEVAddRecExpr>(Reg))
- return getSetupCost(S->getStart(), Depth - 1);
+ return getSetupCost(S->getStart(), Depth - 1, TTI);
if (auto S = dyn_cast<SCEVIntegralCastExpr>(Reg))
- return getSetupCost(S->getOperand(), Depth - 1);
+ return getSetupCost(S->getOperand(), Depth - 1, TTI);
if (auto S = dyn_cast<SCEVNAryExpr>(Reg))
return std::accumulate(S->operands().begin(), S->operands().end(), 0,
[&](unsigned i, const SCEV *Reg) {
- return i + getSetupCost(Reg, Depth - 1);
+ return i + getSetupCost(Reg, Depth - 1, TTI);
});
if (auto S = dyn_cast<SCEVUDivExpr>(Reg))
- return getSetupCost(S->getLHS(), Depth - 1) +
- getSetupCost(S->getRHS(), Depth - 1);
+ return getSetupCost(S->getLHS(), Depth - 1, TTI) +
+ getSetupCost(S->getRHS(), Depth - 1, TTI);
return 0;
}
@@ -1452,7 +1460,7 @@ void Cost::RateRegister(const Formula &F, const SCEV *Reg,
// Rough heuristic; favor registers which don't require extra setup
// instructions in the preheader.
- C.SetupCost += getSetupCost(Reg, SetupCostDepthLimit);
+ C.SetupCost += getSetupCost(Reg, SetupCostDepthLimit, *TTI);
// Ensure we don't, even with the recusion limit, produce invalid costs.
C.SetupCost = std::min<unsigned>(C.SetupCost, 1 << 16);
diff --git a/llvm/test/CodeGen/X86/AMX/amx-across-func.ll b/llvm/test/CodeGen/X86/AMX/amx-across-func.ll
index 2bda8db040296..1e752ef981960 100644
--- a/llvm/test/CodeGen/X86/AMX/amx-across-func.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-across-func.ll
@@ -230,7 +230,7 @@ define dso_local i32 @test_loop(i32 %0) nounwind {
; CHECK-NEXT: testl %ebx, %ebx
; CHECK-NEXT: jg .LBB2_4
; CHECK-NEXT: # %bb.1: # %.preheader
-; CHECK-NEXT: movl $7, %ebp
+; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: movl $buf, %r14d
; CHECK-NEXT: movl $32, %r15d
; CHECK-NEXT: movw $8, %r12w
@@ -248,13 +248,12 @@ define dso_local i32 @test_loop(i32 %0) nounwind {
; CHECK-NEXT: callq foo
; CHECK-NEXT: ldtilecfg (%rsp)
; CHECK-NEXT: decl %ebp
-; CHECK-NEXT: cmpl $7, %ebp
; CHECK-NEXT: jne .LBB2_2
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: cmpl $3, %ebx
; CHECK-NEXT: jne .LBB2_4
; CHECK-NEXT: # %bb.6:
-; CHECK-NEXT: testl %ebp, %ebp
+; CHECK-NEXT: cmpl $-7, %ebp
; CHECK-NEXT: jne .LBB2_5
; CHECK-NEXT: # %bb.7:
; CHECK-NEXT: incl %ebx
@@ -295,7 +294,7 @@ define dso_local i32 @test_loop(i32 %0) nounwind {
; IPRA-NEXT: testl %edi, %edi
; IPRA-NEXT: jg .LBB2_4
; IPRA-NEXT: # %bb.1: # %.preheader
-; IPRA-NEXT: movl $7, %ecx
+; IPRA-NEXT: xorl %ecx, %ecx
; IPRA-NEXT: movl $buf, %edx
; IPRA-NEXT: movl $32, %esi
; IPRA-NEXT: movw $8, %di
@@ -307,13 +306,12 @@ define dso_local i32 @test_loop(i32 %0) nounwind {
; IPRA-NEXT: tilestored %tmm0, (%r8,%rsi)
; IPRA-NEXT: callq foo
; IPRA-NEXT: decl %ecx
-; IPRA-NEXT: cmpl $7, %ecx
; IPRA-NEXT: jne .LBB2_2
; IPRA-NEXT: # %bb.3:
; IPRA-NEXT: cmpl $3, %eax
; IPRA-NEXT: jne .LBB2_4
; IPRA-NEXT: # %bb.6:
-; IPRA-NEXT: testl %ecx, %ecx
+; IPRA-NEXT: cmpl $-7, %ecx
; IPRA-NEXT: jne .LBB2_5
; IPRA-NEXT: # %bb.7:
; IPRA-NEXT: incl %eax
diff --git a/llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution-dbg-msg.ll b/llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution-dbg-msg.ll
index 8d9d43202f0d9..3eade6474e61f 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution-dbg-msg.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution-dbg-msg.ll
@@ -7,7 +7,7 @@ target triple = "riscv64-unknown-linux-gnu"
define ptr @foo(ptr %a0, ptr %a1, i64 %a2) {
;DEBUG: The baseline solution requires 2 instructions 4 regs, with addrec cost 2, plus 3 setup cost
-;DEBUG: The chosen solution requires 3 instructions 6 regs, with addrec cost 1, plus 2 base adds, plus 5 setup cost
+;DEBUG: The chosen solution requires 3 instructions 6 regs, with addrec cost 1, plus 2 base adds, plus 4 setup cost
;DEBUG: Baseline is more profitable than chosen solution, dropping LSR solution.
;DEBUG2: Baseline is more profitable than chosen solution, add option 'lsr-drop-solution' to drop LSR solution.
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
index 7ae78ae6a1fd4..565b1c6c71195 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
@@ -15,21 +15,19 @@ define i64 @sqlite3DropTriggerPtr() nounwind {
; CHECK-LABEL: sqlite3DropTriggerPtr:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: pushq %rbx
-; CHECK-NEXT: movl $1, %ebx
+; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: callq check at PLT
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: incq %rbx
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je .LBB0_4
+; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.2: # %bb4
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
-; CHECK-NEXT: incq %rbx
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_1
-; CHECK-NEXT: # %bb.3: # %bb8split
-; CHECK-NEXT: decq %rbx
-; CHECK-NEXT: .LBB0_4: # %bb8
+; CHECK-NEXT: .LBB0_3: # %bb8
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/postinc-iv-used-by-urem-and-udiv.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/postinc-iv-used-by-urem-and-udiv.ll
index 838b48aa56906..1fec73972ec51 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/postinc-iv-used-by-urem-and-udiv.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/postinc-iv-used-by-urem-and-udiv.ll
@@ -93,19 +93,19 @@ define i32 @test_pr62852() {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], [[LOOP]] ], [ -1, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 2, [[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 2, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 1, [[ENTRY]] ], [ [[DEC_1:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV1]], 1
+; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INC_1:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[INC_1]] = add nsw i64 [[TMP0]], 1
; CHECK-NEXT: [[DEC_1]] = add nsw i32 [[IV_1]], -1
; CHECK-NEXT: call void @use(i64 [[TMP0]])
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], -1
; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[LSR_IV_NEXT]] to i32
-; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nsw i64 [[LSR_IV1]], 1
; CHECK-NEXT: [[CMP6_1:%.*]] = icmp sgt i32 [[TMP]], 0
; CHECK-NEXT: br i1 [[CMP6_1]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: call void @use(i64 [[LSR_IV_NEXT]])
+; CHECK-NEXT: [[LSR_IV_NEXT2:%.*]] = add i64 [[INC_1]], -1
; CHECK-NEXT: call void @use(i64 [[LSR_IV_NEXT2]])
; CHECK-NEXT: [[TMP3:%.*]] = urem i32 [[DEC_1]], 53
; CHECK-NEXT: ret i32 [[TMP3]]
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll
index 2d9478e476cb1..e6ee9b467c5e0 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll
@@ -9,18 +9,17 @@ define i64 @test_pr62660() {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ -1, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV]], 1
+; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ [[LSR_IV_NEXT1:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[TMP0]] to i32
-; CHECK-NEXT: [[CONV1:%.*]] = and i32 [[TMP]], 65535
-; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[IV]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
+; CHECK-NEXT: [[CONV1:%.*]] = and i32 [[TMP1]], 65535
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP]], -1
; CHECK-NEXT: [[SUB:%.*]] = add i32 [[ADD]], [[CONV1]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 1
+; CHECK-NEXT: [[LSR_IV_NEXT1]] = add nuw nsw i64 [[TMP0]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SUB]], 8
; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
+; CHECK-NEXT: [[LSR_IV_NEXT:%.*]] = add i64 [[LSR_IV_NEXT1]], -1
; CHECK-NEXT: ret i64 [[LSR_IV_NEXT]]
;
entry:
diff --git a/llvm/test/Transforms/LoopStrengthReduce/duplicated-phis.ll b/llvm/test/Transforms/LoopStrengthReduce/duplicated-phis.ll
index 43389b5df8f00..9e0cfb1e39f61 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/duplicated-phis.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/duplicated-phis.ll
@@ -19,7 +19,7 @@ define i64 @test_duplicated_phis(i64 noundef %N) {
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[MUL]], -4
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[UNROLL_ITER]], -4
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP4]], 1
-; CHECK-NEXT: [[LSR_IV_NEXT:%.*]] = sub i64 -3, [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 -2, [[TMP3]]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[I_07:%.*]] = phi i64 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[INC_3:%.*]], %[[FOR_BODY]] ]
@@ -27,11 +27,11 @@ define i64 @test_duplicated_phis(i64 noundef %N) {
; CHECK-NEXT: [[NITER_NCMP_3_NOT:%.*]] = icmp eq i64 [[UNROLL_ITER]], [[INC_3]]
; CHECK-NEXT: br i1 [[NITER_NCMP_3_NOT]], label %[[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT:.*]], label %[[FOR_BODY]]
; CHECK: [[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT]]:
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[LSR_IV_NEXT]], 1
+; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], -1
; CHECK-NEXT: br label %[[FOR_END_LOOPEXIT_UNR_LCSSA]]
; CHECK: [[FOR_END_LOOPEXIT_UNR_LCSSA]]:
-; CHECK-NEXT: [[RES_1_LCSSA_PH:%.*]] = phi i64 [ undef, %[[FOR_BODY_PREHEADER]] ], [ [[TMP1]], %[[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT]] ]
-; CHECK-NEXT: [[RES_09_UNR:%.*]] = phi i64 [ -1, %[[FOR_BODY_PREHEADER]] ], [ [[LSR_IV_NEXT]], %[[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT]] ]
+; CHECK-NEXT: [[RES_1_LCSSA_PH:%.*]] = phi i64 [ undef, %[[FOR_BODY_PREHEADER]] ], [ [[TMP5]], %[[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT]] ]
+; CHECK-NEXT: [[RES_09_UNR:%.*]] = phi i64 [ -1, %[[FOR_BODY_PREHEADER]] ], [ [[TMP6]], %[[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT]] ]
; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[N]], 1
; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[TMP2]], 0
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[LCMP_MOD_NOT]], i64 [[RES_1_LCSSA_PH]], i64 [[RES_09_UNR]]
>From aeb1fc8789a7b7f44f035118d3e8d8df187e645d Mon Sep 17 00:00:00 2001
From: Wenju He <wenju.he at intel.com>
Date: Mon, 13 Apr 2026 08:19:08 +0800
Subject: [PATCH 11/36] [libclc] Enable LLVM_RUNTIME_TARGETS in build system
(#189892)
libclc target is now passed in from LLVM_RUNTIME_TARGETS.
The old configure flow based on `-DLLVM_ENABLE_RUNTIMES=libclc` is
deprecated because libclc no longer has a default target.
`-DLLVM_ENABLE_RUNTIMES=libclc -DLLVM_RUNTIME_TARGETS="<target-triple>"`
still works but it is considered legacy.
The new standard build requires:
Each target must now be selected explicitly on the CMake command line
through the runtimes target-specific cache entry and
LLVM_RUNTIME_TARGETS.
For example:
-DRUNTIMES_amdgcn-amd-amdhsa-llvm_LLVM_ENABLE_RUNTIMES=libclc
-DLLVM_RUNTIME_TARGETS="amdgcn-amd-amdhsa-llvm"
-DRUNTIMES_nvptx64-nvidia-cuda_LLVM_ENABLE_RUNTIMES=libclc
-DLLVM_RUNTIME_TARGETS="nvptx64-nvidia-cuda"
-DRUNTIMES_clspv--_LLVM_ENABLE_RUNTIMES=libclc
-DLLVM_RUNTIME_TARGETS="clspv--"
-DRUNTIMES_clspv64--_LLVM_ENABLE_RUNTIMES=libclc
-DLLVM_RUNTIME_TARGETS="clspv64--"
-DRUNTIMES_spirv-mesa3d-_LLVM_ENABLE_RUNTIMES=libclc
-DLLVM_RUNTIME_TARGETS="spirv-mesa3d-"
-DRUNTIMES_spirv64-mesa3d-_LLVM_ENABLE_RUNTIMES=libclc
-DLLVM_RUNTIME_TARGETS="spirv64-mesa3d-"
To build multiple targets, pass them as a semicolon-separated list in
`LLVM_RUNTIME_TARGETS` and provide a matching
`RUNTIMES_<target-triple>_LLVM_ENABLE_RUNTIMES=libclc` entry for each
target.
Updated README.md to document the new build flow.
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
---
.ci/compute_projects.py | 17 +-
.ci/compute_projects_test.py | 23 +--
.ci/monolithic-linux.sh | 12 +-
.ci/monolithic-windows.sh | 12 +-
libclc/CMakeLists.txt | 322 +++++++++++++++++------------------
libclc/README.md | 81 +++++++--
libclc/test/CMakeLists.txt | 21 +--
llvm/runtimes/CMakeLists.txt | 12 +-
8 files changed, 289 insertions(+), 211 deletions(-)
diff --git a/.ci/compute_projects.py b/.ci/compute_projects.py
index 9c7ad73710ae2..e4532adc12787 100644
--- a/.ci/compute_projects.py
+++ b/.ci/compute_projects.py
@@ -98,6 +98,12 @@
"openmp", # https://github.com/google/llvm-premerge-checks/issues/410
}
+# Runtimes configured for cross-compilation using LLVM_RUNTIME_TARGETS.
+# The same build may also use LLVM_ENABLE_RUNTIMES for other runtimes.
+CROSS_COMPILATION_RUNTIMES = {
+ "libclc",
+}
+
EXCLUDE_WINDOWS = {
"cross-project-tests", # TODO(issues/132797): Tests are failing.
"openmp", # TODO(issues/132799): Does not detect perl installation.
@@ -147,7 +153,7 @@
"flang": "check-flang",
"flang-rt": "check-flang-rt",
"libc": "check-libc",
- "libclc": "check-libclc",
+ "libclc": "check-libclc-amdgcn-amd-amdhsa-llvm",
"lld": "check-lld",
"lldb": "check-lldb",
"mlir": "check-mlir",
@@ -276,7 +282,9 @@ def _compute_runtimes_to_build(
for modified_project in modified_projects:
if modified_project in DEPENDENT_RUNTIMES_TO_BUILD:
runtimes_to_build.update(DEPENDENT_RUNTIMES_TO_BUILD[modified_project])
- return _exclude_projects(runtimes_to_build, platform)
+ runtimes_to_build = _exclude_projects(runtimes_to_build, platform)
+ runtimes_to_build -= CROSS_COMPILATION_RUNTIMES
+ return runtimes_to_build
def _path_matches(matcher: tuple[str], file_path: tuple[str]) -> bool:
@@ -320,7 +328,10 @@ def get_env_variables(modified_files: list[str], platform: str) -> Set[str]:
runtimes_to_build = _compute_runtimes_to_build(
runtimes_to_test | runtimes_to_test_needs_reconfig, modified_projects, platform
)
- projects_to_build = _compute_projects_to_build(projects_to_test, runtimes_to_build)
+ cross_runtimes_to_test = runtimes_to_test & CROSS_COMPILATION_RUNTIMES
+ projects_to_build = _compute_projects_to_build(
+ projects_to_test, runtimes_to_build | cross_runtimes_to_test
+ )
projects_check_targets = _compute_project_check_targets(projects_to_test)
runtimes_check_targets = _compute_project_check_targets(runtimes_to_test)
runtimes_check_targets_needs_reconfig = _compute_project_check_targets(
diff --git a/.ci/compute_projects_test.py b/.ci/compute_projects_test.py
index 3069c66940c3a..b8504a57b6dca 100644
--- a/.ci/compute_projects_test.py
+++ b/.ci/compute_projects_test.py
@@ -265,8 +265,11 @@ def test_include_libclc_in_runtimes(self):
)
self.assertEqual(env_variables["projects_to_build"], "clang;llvm")
self.assertEqual(env_variables["project_check_targets"], "")
- self.assertEqual(env_variables["runtimes_to_build"], "libclc")
- self.assertEqual(env_variables["runtimes_check_targets"], "check-libclc")
+ self.assertEqual(env_variables["runtimes_to_build"], "")
+ self.assertEqual(
+ env_variables["runtimes_check_targets"],
+ "check-libclc-amdgcn-amd-amdhsa-llvm",
+ )
self.assertEqual(env_variables["runtimes_check_targets_needs_reconfig"], "")
def test_exclude_docs(self):
@@ -303,11 +306,11 @@ def test_ci(self):
)
self.assertEqual(
env_variables["runtimes_to_build"],
- "compiler-rt;flang-rt;libc;libclc;libcxx;libcxxabi;libunwind",
+ "compiler-rt;flang-rt;libc;libcxx;libcxxabi;libunwind",
)
self.assertEqual(
env_variables["runtimes_check_targets"],
- "check-compiler-rt check-flang-rt check-libc check-libclc",
+ "check-compiler-rt check-flang-rt check-libc check-libclc-amdgcn-amd-amdhsa-llvm",
)
self.assertEqual(
env_variables["runtimes_check_targets_needs_reconfig"],
@@ -328,11 +331,11 @@ def test_windows_ci(self):
)
self.assertEqual(
env_variables["runtimes_to_build"],
- "compiler-rt;libclc",
+ "compiler-rt",
)
self.assertEqual(
env_variables["runtimes_check_targets"],
- "check-compiler-rt check-libclc",
+ "check-compiler-rt check-libclc-amdgcn-amd-amdhsa-llvm",
)
self.assertEqual(
env_variables["runtimes_check_targets_needs_reconfig"],
@@ -377,11 +380,11 @@ def test_premerge_workflow(self):
)
self.assertEqual(
env_variables["runtimes_to_build"],
- "compiler-rt;flang-rt;libc;libclc;libcxx;libcxxabi;libunwind",
+ "compiler-rt;flang-rt;libc;libcxx;libcxxabi;libunwind",
)
self.assertEqual(
env_variables["runtimes_check_targets"],
- "check-compiler-rt check-flang-rt check-libc check-libclc",
+ "check-compiler-rt check-flang-rt check-libc check-libclc-amdgcn-amd-amdhsa-llvm",
)
self.assertEqual(
env_variables["runtimes_check_targets_needs_reconfig"],
@@ -412,11 +415,11 @@ def test_third_party_benchmark(self):
)
self.assertEqual(
env_variables["runtimes_to_build"],
- "compiler-rt;flang-rt;libc;libclc;libcxx;libcxxabi;libunwind",
+ "compiler-rt;flang-rt;libc;libcxx;libcxxabi;libunwind",
)
self.assertEqual(
env_variables["runtimes_check_targets"],
- "check-compiler-rt check-flang-rt check-libc check-libclc",
+ "check-compiler-rt check-flang-rt check-libc check-libclc-amdgcn-amd-amdhsa-llvm",
)
self.assertEqual(
env_variables["runtimes_check_targets_needs_reconfig"],
diff --git a/.ci/monolithic-linux.sh b/.ci/monolithic-linux.sh
index 79fc891b729d7..9d9c3de905b99 100755
--- a/.ci/monolithic-linux.sh
+++ b/.ci/monolithic-linux.sh
@@ -31,6 +31,14 @@ enable_cir="${6}"
lit_args="-v --xunit-xml-output ${BUILD_DIR}/test-results.xml --use-unique-output-file-name --timeout=1200 --time-tests --succinct"
+runtime_cmake_args=()
+if [[ " ${runtime_targets} " == *" check-libclc-amdgcn-amd-amdhsa-llvm "* ]]; then
+ runtime_cmake_args+=(
+ -D RUNTIMES_amdgcn-amd-amdhsa-llvm_LLVM_ENABLE_RUNTIMES=libclc
+ -D LLVM_RUNTIME_TARGETS="default;amdgcn-amd-amdhsa-llvm"
+ )
+fi
+
start-group "CMake"
# Set the system llvm-symbolizer as preferred.
@@ -56,14 +64,14 @@ cmake -S "${MONOREPO_ROOT}"/llvm -B "${BUILD_DIR}" \
-D CMAKE_CXX_COMPILER_LAUNCHER=sccache \
-D CMAKE_DISABLE_PRECOMPILE_HEADERS=ON \
-D LIBCXX_CXX_ABI=libcxxabi \
- -D LIBCLC_TARGETS_TO_BUILD="amdgcn-amd-amdhsa-llvm" \
-D MLIR_ENABLE_BINDINGS_PYTHON=ON \
-D LLDB_ENABLE_PYTHON=ON \
-D LLDB_ENFORCE_STRICT_TEST_REQUIREMENTS=ON \
-D CMAKE_INSTALL_PREFIX="${INSTALL_DIR}" \
-D CMAKE_EXE_LINKER_FLAGS="-no-pie" \
-D LLVM_ENABLE_WERROR=ON \
- -D LLVM_BINUTILS_INCDIR=/usr
+ -D LLVM_BINUTILS_INCDIR=/usr \
+ "${runtime_cmake_args[@]}"
start-group "ninja"
diff --git a/.ci/monolithic-windows.sh b/.ci/monolithic-windows.sh
index f35f17350022f..795893c305665 100755
--- a/.ci/monolithic-windows.sh
+++ b/.ci/monolithic-windows.sh
@@ -20,6 +20,14 @@ targets="${2}"
runtimes="${3}"
runtimes_targets="${4}"
+runtime_cmake_args=()
+if [[ " ${runtimes_targets} " == *" check-libclc-amdgcn-amd-amdhsa-llvm "* ]]; then
+ runtime_cmake_args+=(
+ -D RUNTIMES_amdgcn-amd-amdhsa-llvm_LLVM_ENABLE_RUNTIMES=libclc
+ -D LLVM_RUNTIME_TARGETS="default;amdgcn-amd-amdhsa-llvm"
+ )
+fi
+
start-group "CMake"
pip install -q -r "${MONOREPO_ROOT}"/.ci/all_requirements.txt
@@ -45,11 +53,11 @@ cmake -S "${MONOREPO_ROOT}"/llvm -B "${BUILD_DIR}" \
-D CMAKE_CXX_COMPILER_LAUNCHER=sccache \
-D CMAKE_DISABLE_PRECOMPILE_HEADERS=ON \
-D MLIR_ENABLE_BINDINGS_PYTHON=ON \
- -D LIBCLC_TARGETS_TO_BUILD="amdgcn-amd-amdhsa-llvm" \
-D CMAKE_EXE_LINKER_FLAGS="/MANIFEST:NO" \
-D CMAKE_MODULE_LINKER_FLAGS="/MANIFEST:NO" \
-D CMAKE_SHARED_LINKER_FLAGS="/MANIFEST:NO" \
- -D LLVM_ENABLE_RUNTIMES="${runtimes}"
+ -D LLVM_ENABLE_RUNTIMES="${runtimes}" \
+ "${runtime_cmake_args[@]}"
start-group "ninja"
diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt
index 99235e32812b9..685b9032aa92e 100644
--- a/libclc/CMakeLists.txt
+++ b/libclc/CMakeLists.txt
@@ -18,14 +18,6 @@ include( GNUInstallDirs )
set( LIBCLC_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR} )
-# A runtimes cross-build should only use the requested target.
-set( LIBCLC_DEFAULT_TARGET "all" )
-if( LLVM_RUNTIMES_BUILD AND LLVM_DEFAULT_TARGET_TRIPLE MATCHES "^nvptx|^amdgcn" )
- set( LIBCLC_DEFAULT_TARGET ${LLVM_DEFAULT_TARGET_TRIPLE} )
-endif()
-set( LIBCLC_TARGETS_TO_BUILD ${LIBCLC_DEFAULT_TARGET}
- CACHE STRING "Semicolon-separated list of libclc targets to build, or 'all'." )
-
option(
LIBCLC_USE_SPIRV_BACKEND "Build SPIR-V targets with the SPIR-V backend." OFF
)
@@ -38,8 +30,20 @@ set( LIBCLC_TARGETS_ALL
nvptx64--
nvptx64--nvidiacl
nvptx64-nvidia-cuda
+ spirv-mesa3d-
+ spirv64-mesa3d-
)
+set(LIBCLC_TARGET ${LLVM_RUNTIMES_TARGET})
+
+if(NOT LIBCLC_TARGET)
+ message(FATAL_ERROR "libclc target is empty\n")
+endif()
+if(NOT "${LIBCLC_TARGET}" IN_LIST LIBCLC_TARGETS_ALL)
+ message(FATAL_ERROR "Unknown libclc target: ${LIBCLC_TARGET}\n"
+ "Valid targets are: ${LIBCLC_TARGETS_ALL}\n")
+endif()
+
if( LIBCLC_STANDALONE_BUILD OR CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR )
set( LIBCLC_STANDALONE_BUILD TRUE )
@@ -97,23 +101,17 @@ if( NOT LIBCLC_USE_SPIRV_BACKEND )
endif()
endif()
-if( LIBCLC_USE_SPIRV_BACKEND OR llvm-spirv_exe )
- list( APPEND LIBCLC_TARGETS_ALL spirv-mesa3d- spirv64-mesa3d- )
-endif()
+message(STATUS "libclc target '${LIBCLC_TARGET}' is enabled")
-if( LIBCLC_TARGETS_TO_BUILD STREQUAL "all" )
- set( LIBCLC_TARGETS_TO_BUILD ${LIBCLC_TARGETS_ALL} )
-else()
- foreach(TARGET_TO_BUILD ${LIBCLC_TARGETS_TO_BUILD})
- if (NOT ${TARGET_TO_BUILD} IN_LIST LIBCLC_TARGETS_ALL)
- message( FATAL_ERROR
- "Unknown target in LIBCLC_TARGETS_TO_BUILD: \"${TARGET_TO_BUILD}\"\n"
- "Valid targets are: ${LIBCLC_TARGETS_ALL}\n")
- endif()
- endforeach()
-endif()
+string( REPLACE "-" ";" TRIPLE ${LIBCLC_TARGET} )
+list(GET TRIPLE 0 ARCH)
+list(GET TRIPLE 2 OS)
-list( SORT LIBCLC_TARGETS_TO_BUILD )
+if(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
+ if(NOT LIBCLC_USE_SPIRV_BACKEND AND NOT llvm-spirv_exe)
+ message(FATAL_ERROR "SPIR-V backend or llvm-spirv is required for libclc ${LIBCLC_TARGET}")
+ endif()
+endif()
foreach( tool IN ITEMS opt llvm-link )
if( NOT EXISTS "${${tool}_exe}" AND "${${tool}_target}" STREQUAL "" )
@@ -122,160 +120,156 @@ foreach( tool IN ITEMS opt llvm-link )
endforeach()
add_subdirectory(clc/lib/generic)
-add_subdirectory(clc/lib/amdgpu)
-add_subdirectory(clc/lib/ptx-nvidiacl)
-add_subdirectory(clc/lib/spirv)
-add_subdirectory(clc/lib/clspv)
-
add_subdirectory(opencl/lib/generic)
-add_subdirectory(opencl/lib/amdgpu)
-add_subdirectory(opencl/lib/clspv)
-add_subdirectory(opencl/lib/spirv)
+
+if(ARCH STREQUAL amdgcn)
+ add_subdirectory(clc/lib/amdgpu)
+ add_subdirectory(opencl/lib/amdgpu)
+elseif(ARCH STREQUAL nvptx64)
+ add_subdirectory(clc/lib/ptx-nvidiacl)
+elseif(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
+ add_subdirectory(clc/lib/spirv)
+ add_subdirectory(opencl/lib/spirv)
+elseif(ARCH STREQUAL clspv OR ARCH STREQUAL clspv64)
+ add_subdirectory(clc/lib/clspv)
+ add_subdirectory(opencl/lib/clspv)
+endif()
add_custom_target( libclc ALL )
add_custom_target( libclc-opencl-builtins COMMENT "Build libclc OpenCL builtins" )
add_dependencies( libclc libclc-opencl-builtins )
-foreach( t ${LIBCLC_TARGETS_TO_BUILD} )
- message( STATUS "libclc target '${t}' is enabled" )
- string( REPLACE "-" ";" TRIPLE ${t} )
- list( GET TRIPLE 0 ARCH )
- list( GET TRIPLE 1 VENDOR )
- list( GET TRIPLE 2 OS )
-
- # Determine the clang target triple.
- set(clang_triple ${t})
- if(ARCH STREQUAL spirv AND LIBCLC_USE_SPIRV_BACKEND)
- set(clang_triple spirv32--)
- elseif(ARCH STREQUAL spirv64 AND LIBCLC_USE_SPIRV_BACKEND)
- set(clang_triple spirv64--)
- elseif(ARCH STREQUAL spirv OR ARCH STREQUAL clspv)
- set(clang_triple spir--)
- elseif(ARCH STREQUAL spirv64 OR ARCH STREQUAL clspv64)
- set(clang_triple spir64--)
- endif()
+# Determine the clang target triple.
+set(clang_triple ${LIBCLC_TARGET})
+if(ARCH STREQUAL spirv AND LIBCLC_USE_SPIRV_BACKEND)
+ set(clang_triple spirv32--)
+elseif(ARCH STREQUAL spirv64 AND LIBCLC_USE_SPIRV_BACKEND)
+ set(clang_triple spirv64--)
+elseif(ARCH STREQUAL spirv OR ARCH STREQUAL clspv)
+ set(clang_triple spir--)
+elseif(ARCH STREQUAL spirv64 OR ARCH STREQUAL clspv64)
+ set(clang_triple spir64--)
+endif()
- # Determine the preprocessor identifier for this target.
- set(MACRO_ARCH ${ARCH})
- if(ARCH STREQUAL spirv)
- set(MACRO_ARCH SPIRV32)
- elseif(ARCH STREQUAL spirv64)
- set(MACRO_ARCH SPIRV64)
- elseif(ARCH STREQUAL clspv)
- set(MACRO_ARCH CLSPV32)
- elseif(ARCH STREQUAL clspv64)
- set(MACRO_ARCH CLSPV64)
- endif()
- string(TOUPPER "CLC_${MACRO_ARCH}" target_define)
+# Determine the preprocessor identifier for this target.
+set(MACRO_ARCH ${ARCH})
+if(ARCH STREQUAL spirv)
+ set(MACRO_ARCH SPIRV32)
+elseif(ARCH STREQUAL spirv64)
+ set(MACRO_ARCH SPIRV64)
+elseif(ARCH STREQUAL clspv)
+ set(MACRO_ARCH CLSPV32)
+elseif(ARCH STREQUAL clspv64)
+ set(MACRO_ARCH CLSPV64)
+endif()
+string(TOUPPER "CLC_${MACRO_ARCH}" target_define)
- # Address space values.
- set(private_addrspace_val 0)
- set(generic_addrspace_val 0)
- if(ARCH STREQUAL amdgcn)
- set(private_addrspace_val 5)
- endif()
- if(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
- set(generic_addrspace_val 4)
- endif()
+# Address space values.
+set(private_addrspace_val 0)
+set(generic_addrspace_val 0)
+if(ARCH STREQUAL amdgcn)
+ set(private_addrspace_val 5)
+endif()
+if(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
+ set(generic_addrspace_val 4)
+endif()
- # Target-specific compile flags and defines.
- set(target_compile_flags)
- set(target_extra_defines)
- set(opt_flags -O3)
-
- if(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
- list(APPEND target_compile_flags -O0 -finline-hint-functions)
- list(APPEND target_extra_defines CLC_SPIRV)
- set(opt_flags)
- elseif(ARCH STREQUAL clspv OR ARCH STREQUAL clspv64)
- list(APPEND target_compile_flags -Wno-unknown-assumption
- -U__opencl_c_int64)
- list(APPEND target_extra_defines CLC_CLSPV)
- elseif(ARCH STREQUAL amdgcn)
- list(APPEND target_compile_flags "SHELL:-Xclang -mcode-object-version=none")
- endif()
+# Target-specific compile flags and defines.
+set(target_compile_flags)
+set(target_extra_defines)
+set(opt_flags -O3)
+
+if(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
+ list(APPEND target_compile_flags -O0 -finline-hint-functions)
+ list(APPEND target_extra_defines CLC_SPIRV)
+ set(opt_flags)
+elseif(ARCH STREQUAL clspv OR ARCH STREQUAL clspv64)
+ list(APPEND target_compile_flags -Wno-unknown-assumption -U__opencl_c_int64)
+ list(APPEND target_extra_defines CLC_CLSPV)
+elseif(ARCH STREQUAL amdgcn)
+ list(APPEND target_compile_flags "SHELL:-Xclang -mcode-object-version=none")
+endif()
- # Collect CLC sources; target-specific sources override generic ones by basename.
- set(_clc_overrides)
+# Collect CLC sources; target-specific sources override generic ones by basename.
+set(_clc_overrides)
+if(ARCH STREQUAL amdgcn)
+ list(APPEND _clc_overrides ${CLC_AMDGPU_SOURCES})
+elseif(ARCH STREQUAL nvptx64 AND (OS STREQUAL nvidiacl OR OS STREQUAL cuda))
+ list(APPEND _clc_overrides ${CLC_PTX_NVIDIACL_SOURCES})
+elseif(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
+ list(APPEND _clc_overrides ${CLC_SPIRV_SOURCES})
+elseif(ARCH STREQUAL clspv OR ARCH STREQUAL clspv64)
+ list(APPEND _clc_overrides ${CLC_CLSPV_SOURCES})
+endif()
+libclc_merge_sources(clc_sources ${CLC_GENERIC_SOURCES} ${_clc_overrides})
+
+# Collect OpenCL sources. SPIR-V and Clspv targets use self-contained
+# subsets while others merge with target-specific overrides.
+if(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
+ set(opencl_sources ${OPENCL_SPIRV_SOURCES})
+elseif(ARCH STREQUAL clspv OR ARCH STREQUAL clspv64)
+ set(opencl_sources ${OPENCL_CLSPV_SOURCES})
+else()
+ set(_opencl_overrides)
if(ARCH STREQUAL amdgcn)
- list(APPEND _clc_overrides ${CLC_AMDGPU_SOURCES})
- elseif(ARCH STREQUAL nvptx64 AND (OS STREQUAL nvidiacl OR OS STREQUAL cuda))
- list(APPEND _clc_overrides ${CLC_PTX_NVIDIACL_SOURCES})
- elseif(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
- list(APPEND _clc_overrides ${CLC_SPIRV_SOURCES})
- elseif(ARCH STREQUAL clspv OR ARCH STREQUAL clspv64)
- list(APPEND _clc_overrides ${CLC_CLSPV_SOURCES})
- endif()
- libclc_merge_sources(clc_sources ${CLC_GENERIC_SOURCES} ${_clc_overrides})
-
- # Collect OpenCL sources. SPIR-V and Clspv targets use self-contained
- # subsets while others merge with target-specific overrides.
- if(ARCH STREQUAL spirv OR ARCH STREQUAL spirv64)
- set(opencl_sources ${OPENCL_SPIRV_SOURCES})
- elseif(ARCH STREQUAL clspv OR ARCH STREQUAL clspv64)
- set(opencl_sources ${OPENCL_CLSPV_SOURCES})
- else()
- set(_opencl_overrides)
- if(ARCH STREQUAL amdgcn)
- list(APPEND _opencl_overrides ${OPENCL_AMDGCN_SOURCES})
- endif()
- libclc_merge_sources(opencl_sources
- ${OPENCL_GENERIC_SOURCES} ${_opencl_overrides})
+ list(APPEND _opencl_overrides ${OPENCL_AMDGCN_SOURCES})
endif()
+ libclc_merge_sources(opencl_sources
+ ${OPENCL_GENERIC_SOURCES} ${_opencl_overrides})
+endif()
- # Common compile options shared by CLC and OpenCL libraries.
- set(compile_flags
- -flto
- --target=${clang_triple}
- -nostdlib
- -nostdlibinc
- -cl-no-stdinc
- -cl-std=CL3.0
- -include opencl-c-base.h
- -Werror=undef
- -Wall
- -Wextra
- -fdiscard-value-names
- -ffp-contract=fast-honor-pragmas
- -fdenormal-fp-math=dynamic
- ${target_compile_flags}
- )
-
- set(_common_defs
- ${target_define}
- ${target_extra_defines}
- __CLC_PRIVATE_ADDRSPACE_VAL=${private_addrspace_val}
- __CLC_GENERIC_ADDRSPACE_VAL=${generic_addrspace_val}
- )
-
- # Build the CLC internal builtins library.
- string(REPLACE "-" "_" lib_suffix ${t})
- set(clc_lib clc_builtins_${lib_suffix})
- add_libclc_builtin_library(${clc_lib}
- SOURCES ${clc_sources}
- COMPILE_OPTIONS ${compile_flags}
- INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/clc/include
- COMPILE_DEFINITIONS ${_common_defs}
- FOLDER "libclc/Device IR/CLC"
- )
-
- # Build, link, and install the final OpenCL builtins library.
- add_libclc_library(libclc-${t}
- ARCH ${ARCH}
- TRIPLE ${clang_triple}
- TARGET_TRIPLE ${t}
- SOURCES ${opencl_sources}
- COMPILE_OPTIONS ${compile_flags} "SHELL:-Xclang -fdeclare-opencl-builtins"
- INCLUDE_DIRS
- ${CMAKE_CURRENT_SOURCE_DIR}/clc/include
- ${CMAKE_CURRENT_SOURCE_DIR}/opencl/include
- COMPILE_DEFINITIONS ${_common_defs}
- INTERNALIZE_LIBRARIES ${clc_lib}
- OPT_FLAGS ${opt_flags}
- OUTPUT_FILENAME libclc
- PARENT_TARGET libclc-opencl-builtins
- )
-endforeach()
+# Common compile options shared by CLC and OpenCL libraries.
+set(compile_flags
+ -flto
+ --target=${clang_triple}
+ -nostdlib
+ -nostdlibinc
+ -cl-no-stdinc
+ -cl-std=CL3.0
+ -include opencl-c-base.h
+ -Werror=undef
+ -Wall
+ -Wextra
+ -fdiscard-value-names
+ -ffp-contract=fast-honor-pragmas
+ -fdenormal-fp-math=dynamic
+ ${target_compile_flags}
+)
+
+set(_common_defs
+ ${target_define}
+ ${target_extra_defines}
+ __CLC_PRIVATE_ADDRSPACE_VAL=${private_addrspace_val}
+ __CLC_GENERIC_ADDRSPACE_VAL=${generic_addrspace_val}
+)
+
+# Build the CLC internal builtins library.
+string(REPLACE "-" "_" lib_suffix ${LIBCLC_TARGET})
+set(clc_lib clc_builtins_${lib_suffix})
+add_libclc_builtin_library(${clc_lib}
+ SOURCES ${clc_sources}
+ COMPILE_OPTIONS ${compile_flags}
+ INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/clc/include
+ COMPILE_DEFINITIONS ${_common_defs}
+ FOLDER "libclc/Device IR/CLC"
+)
+
+# Build, link, and install the final OpenCL builtins library.
+add_libclc_library(libclc-${LIBCLC_TARGET}
+ ARCH ${ARCH}
+ TRIPLE ${clang_triple}
+ TARGET_TRIPLE ${LIBCLC_TARGET}
+ SOURCES ${opencl_sources}
+ COMPILE_OPTIONS ${compile_flags} "SHELL:-Xclang -fdeclare-opencl-builtins"
+ INCLUDE_DIRS
+ ${CMAKE_CURRENT_SOURCE_DIR}/clc/include
+ ${CMAKE_CURRENT_SOURCE_DIR}/opencl/include
+ COMPILE_DEFINITIONS ${_common_defs}
+ INTERNALIZE_LIBRARIES ${clc_lib}
+ OPT_FLAGS ${opt_flags}
+ OUTPUT_FILENAME libclc
+ PARENT_TARGET libclc-opencl-builtins
+)
add_subdirectory(test)
diff --git a/libclc/README.md b/libclc/README.md
index 4f14066425d2d..f50a931a67f6c 100644
--- a/libclc/README.md
+++ b/libclc/README.md
@@ -25,36 +25,87 @@ functions.
libclc currently supports PTX, AMDGPU, SPIRV and CLSPV targets, but support for
more targets is welcome.
-## Compiling and installing
+## Configure, build, and install
-(in the following instructions you can use `make` or `ninja`)
+libclc is built as part of an LLVM runtimes build.
-For an in-tree build, Clang must also be built at the same time:
+Select the targets to build with `LLVM_RUNTIME_TARGETS`, and enable libclc for
+each selected target with the matching
+`RUNTIMES_<target-triple>_LLVM_ENABLE_RUNTIMES` cache entry.
+
+#### Configure for the AMDGPU target
```
-$ cmake <path-to>/llvm-project/llvm/CMakeLists.txt -DLLVM_ENABLE_PROJECTS="clang" \
- -DLLVM_ENABLE_RUNTIMES="libclc" -DCMAKE_BUILD_TYPE=Release -G Ninja
-$ ninja
+cd llvm-project
+mkdir build
+cd build
+cmake ../llvm -G Ninja -DLLVM_ENABLE_PROJECTS="clang" -DCMAKE_BUILD_TYPE=Release \
+ -DRUNTIMES_amdgcn-amd-amdhsa-llvm_LLVM_ENABLE_RUNTIMES=libclc \
+ -DLLVM_RUNTIME_TARGETS="amdgcn-amd-amdhsa-llvm"
+```
+
+#### Configure for the NVPTX64 target
+```
+cmake ../llvm -G Ninja -DLLVM_ENABLE_PROJECTS="clang" -DCMAKE_BUILD_TYPE=Release \
+ -DRUNTIMES_nvptx64-nvidia-cuda_LLVM_ENABLE_RUNTIMES=libclc \
+ -DLLVM_RUNTIME_TARGETS="nvptx64-nvidia-cuda"
+```
+
+#### Configure for CLSPV targets
```
-Then install:
+cmake ../llvm -G Ninja -DLLVM_ENABLE_PROJECTS="clang" -DCMAKE_BUILD_TYPE=Release \
+ -DRUNTIMES_clspv--_LLVM_ENABLE_RUNTIMES=libclc \
+ -DRUNTIMES_clspv64--_LLVM_ENABLE_RUNTIMES=libclc \
+ -DLLVM_RUNTIME_TARGETS="clspv--;clspv64--"
+```
+
+#### Configure for SPIR-V targets
+```
+cmake ../llvm -G Ninja -DLLVM_ENABLE_PROJECTS="clang" -DCMAKE_BUILD_TYPE=Release \
+ -DRUNTIMES_spirv-mesa3d-_LLVM_ENABLE_RUNTIMES=libclc \
+ -DRUNTIMES_spirv64-mesa3d-_LLVM_ENABLE_RUNTIMES=libclc \
+ -DLLVM_RUNTIME_TARGETS="spirv-mesa3d-;spirv64-mesa3d-"
+```
+
+To build multiple targets, pass them as a semicolon-separated list in
+`LLVM_RUNTIME_TARGETS` and provide a matching
+`RUNTIMES_<target-triple>_LLVM_ENABLE_RUNTIMES=libclc` entry for each target.
+
+#### Build
```
-$ ninja install
+ninja
```
+
+#### Install
+```
+ninja install
+```
+
Note you can use the `DESTDIR` Makefile variable to do staged installs.
```
-$ DESTDIR=/path/for/staged/install ninja install
+DESTDIR=/path/for/staged/install ninja install
+```
+
+## Run tests
+```
+ninja check-libclc-<target-triple>
+```
+or
+```
+ninja -C runtimes/runtimes-<target-triple>-bins check-libclc
```
+
+## Out-of-tree build
+
To build out of tree, or in other words, against an existing LLVM build or install:
```
-$ cmake <path-to>/llvm-project/libclc/CMakeLists.txt -DCMAKE_BUILD_TYPE=Release \
- -G Ninja -DLLVM_DIR=$(<path-to>/llvm-config --cmakedir)
+CC=$(<path-to>/llvm-config --bindir)/clang cmake \
+ <path-to>/llvm-project/libclc/CMakeLists.txt -DCMAKE_BUILD_TYPE=Release \
+ -G Ninja -DLLVM_DIR=$(<path-to>/llvm-config --cmakedir) \
+ -DLLVM_RUNTIMES_TARGET=<target-triple>
$ ninja
```
Then install as before.
-In both cases this will include all supported targets. You can choose which
-targets are enabled by passing `-DLIBCLC_TARGETS_TO_BUILD` to CMake. The default
-is `all`.
-
In both cases, the LLVM used must include the targets you want libclc support for
(`AMDGPU` and `NVPTX` are enabled in LLVM by default). Apart from `SPIRV` where you do
not need an LLVM target but you do need the
diff --git a/libclc/test/CMakeLists.txt b/libclc/test/CMakeLists.txt
index 4d8bb60b52b0d..c65346ec893f1 100644
--- a/libclc/test/CMakeLists.txt
+++ b/libclc/test/CMakeLists.txt
@@ -7,19 +7,12 @@ set(LIBCLC_TEST_DEPS
umbrella_lit_testsuite_begin(check-libclc)
# Testing unresolved symbols.
-foreach(t ${LIBCLC_TARGETS_TO_BUILD})
- string(REPLACE "-" ";" TRIPLE ${t})
- list(GET TRIPLE 0 ARCH)
-
- # Skip nvptx, clspv, spirv targets
- if(ARCH MATCHES "^(nvptx|clspv)(64)?$" OR ARCH MATCHES "^spirv(64)?$")
- continue()
- endif()
-
+# Skip nvptx, clspv, spirv targets
+if(ARCH MATCHES amdgcn)
# Get the output file from the target property
- set(target_file "$<TARGET_PROPERTY:libclc-${t},TARGET_FILE>")
+ set(target_file "$<TARGET_PROPERTY:libclc-${LIBCLC_TARGET},TARGET_FILE>")
- set(LIBCLC_TARGET_TEST_DIR ${CMAKE_CURRENT_BINARY_DIR}/${t})
+ set(LIBCLC_TARGET_TEST_DIR ${CMAKE_CURRENT_BINARY_DIR}/${LIBCLC_TARGET})
file(MAKE_DIRECTORY ${LIBCLC_TARGET_TEST_DIR})
file(GENERATE OUTPUT ${LIBCLC_TARGET_TEST_DIR}/check-external-funcs.test
CONTENT "; RUN: llvm-nm -u \"${target_file}\" | FileCheck %s --allow-empty\n\n; CHECK-NOT: {{.+}}\n"
@@ -32,11 +25,11 @@ foreach(t ${LIBCLC_TARGETS_TO_BUILD})
${CMAKE_CURRENT_SOURCE_DIR}/lit.cfg.py
)
- add_lit_testsuite(check-libclc-external-funcs-${t} "Running ${t} tests"
+ add_lit_testsuite(check-libclc-external-funcs-${LIBCLC_TARGET} "Running ${LIBCLC_TARGET} tests"
${LIBCLC_TARGET_TEST_DIR}
DEPENDS ${LIBCLC_TEST_DEPS}
)
- set_target_properties(check-libclc-external-funcs-${t} PROPERTIES FOLDER "libclc tests")
-endforeach()
+ set_target_properties(check-libclc-external-funcs-${LIBCLC_TARGET} PROPERTIES FOLDER "libclc tests")
+endif()
umbrella_lit_testsuite_end(check-libclc)
diff --git a/llvm/runtimes/CMakeLists.txt b/llvm/runtimes/CMakeLists.txt
index 20c79a2c2e2ef..dfa8369bad7b4 100644
--- a/llvm/runtimes/CMakeLists.txt
+++ b/llvm/runtimes/CMakeLists.txt
@@ -552,8 +552,18 @@ if(build_runtimes)
list(APPEND extra_cmake_args "-DCMAKE_PROGRAM_PATH=${CMAKE_PROGRAM_PATH}")
endif()
- # TODO: We need to consider passing it as '-DRUNTIMES_x86_64_LLVM_ENABLE_RUNTIMES'.
+ set(libclc_enabled FALSE)
if("libclc" IN_LIST LLVM_ENABLE_RUNTIMES)
+ set(libclc_enabled TRUE)
+ else()
+ foreach(target ${LLVM_RUNTIME_TARGETS})
+ if("libclc" IN_LIST RUNTIMES_${target}_LLVM_ENABLE_RUNTIMES)
+ set(libclc_enabled TRUE)
+ break()
+ endif()
+ endforeach()
+ endif()
+ if(libclc_enabled)
foreach(dep clang llvm-link opt llvm-ar llvm-ranlib llvm-spirv)
if(TARGET ${dep})
list(APPEND extra_deps ${dep})
>From 76a33f7dab5dde55b18ed1a6c0449b24816f6cc0 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Mon, 13 Apr 2026 06:30:31 +0100
Subject: [PATCH 12/36] [AArch64] Skip non-pseudo instructions in
AArch64ExpandPseudoInsts (#191395)
AArch64::getSVEPseudoMap calls are visible in compile-time profiles even on
non-SVE targets. I think CodeGenMapTable could be improved, it's currently
emitting a constexpr array sorted by opcode and a hand-rolled binary search
over that array, however the AArch64ExpandPseudoInsts pass is missing a simple
check for pseudo instructions before expanding. This avoids the compile-time
cost.
https://llvm-compile-time-tracker.com/compare.php?from=0d42811ea4658b3e86a3801b3bc848324f8540f8&to=9e2434de84577ca1c5e6de8fe8d75c6b8e282b3f&stat=instructions%3Au
---
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 638a3a59b983e..f3aea26b3bbad 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -2004,7 +2004,8 @@ bool AArch64ExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
while (MBBI != E) {
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
- Modified |= expandMI(MBB, MBBI, NMBBI);
+ if (MBBI->isPseudo())
+ Modified |= expandMI(MBB, MBBI, NMBBI);
MBBI = NMBBI;
}
>From f5ee06e640079c329642945d7ca90c7ecd94d45f Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 12 Apr 2026 22:57:39 -0700
Subject: [PATCH 13/36] [TargetLowering] Support larger divisors in
expandDIVREMByConstant. (#191119)
Instead of bailing out if the original divisor exceeds HBitWidth,
allow divisors that fit in HBitWidth after removing trailing zeros.
PartialRem now needs a low and high part. Shifting RemL left
now needs to handle shifting into RemH.
Assisted-by: Claude Sonnet 4.5
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 94 ++++--
.../CodeGen/RISCV/split-udiv-by-constant.ll | 289 +++++++++++++++++-
.../CodeGen/RISCV/split-urem-by-constant.ll | 212 ++++++++++++-
llvm/test/CodeGen/X86/i128-udiv.ll | 28 +-
4 files changed, 590 insertions(+), 33 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 80db54cece319..3989cf83289fc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8130,11 +8130,6 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
assert(VT.getScalarSizeInBits() == BitWidth &&
HiLoVT.getScalarSizeInBits() == HBitWidth && "Unexpected VTs");
- // Divisor needs to less than (1 << HBitWidth).
- APInt HalfMaxPlus1 = APInt::getOneBitSet(BitWidth, HBitWidth);
- if (Divisor.uge(HalfMaxPlus1))
- return false;
-
// We depend on the UREM by constant optimization in DAGCombiner that requires
// high multiply.
if (!isOperationLegalOrCustom(ISD::MULHU, HiLoVT) &&
@@ -8156,6 +8151,12 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
Divisor.lshrInPlace(TrailingZeros);
}
+ // After removing trailing zeros, the divisor needs to be less than
+ // (1 << HBitWidth).
+ APInt HalfMaxPlus1 = APInt::getOneBitSet(BitWidth, HBitWidth);
+ if (Divisor.uge(HalfMaxPlus1))
+ return false;
+
// Look for the largest chunk width W such that (1 << W) % Divisor == 1 or
// (1 << W) % Divisor == -1.
unsigned BestChunkWidth = 0, AltChunkWidth = 0;
@@ -8207,14 +8208,45 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
DAG.getShiftAmountConstant(HBitWidth - ShiftAmt, HiLoVT, dl)));
};
+ // Helper to perform a right shift on a 128-bit value split into two halves.
+ // Handles shifts >= HBitWidth by moving Hi to Lo and shifting Hi.
+ auto ShiftRight = [&](SDValue &Lo, SDValue &Hi, unsigned ShiftAmt) {
+ if (ShiftAmt == 0)
+ return;
+ if (ShiftAmt < HBitWidth) {
+ Lo = GetFSHR(Lo, Hi, ShiftAmt);
+ Hi = DAG.getNode(ISD::SRL, dl, HiLoVT, Hi,
+ DAG.getShiftAmountConstant(ShiftAmt, HiLoVT, dl));
+ } else if (ShiftAmt == HBitWidth) {
+ Lo = Hi;
+ Hi = DAG.getConstant(0, dl, HiLoVT);
+ } else {
+ Lo = DAG.getNode(
+ ISD::SRL, dl, HiLoVT, Hi,
+ DAG.getShiftAmountConstant(ShiftAmt - HBitWidth, HiLoVT, dl));
+ Hi = DAG.getConstant(0, dl, HiLoVT);
+ }
+ };
+
// Shift the input by the number of TrailingZeros in the divisor. The
// shifted out bits will be added to the remainder later.
- SDValue PartialRem;
+ SDValue PartialRemL, PartialRemH;
if (TrailingZeros && Opcode != ISD::UDIV) {
// Save the shifted off bits if we need the remainder.
- APInt Mask = APInt::getLowBitsSet(HBitWidth, TrailingZeros);
- PartialRem = DAG.getNode(ISD::AND, dl, HiLoVT, LL,
- DAG.getConstant(Mask, dl, HiLoVT));
+ if (TrailingZeros < HBitWidth) {
+ APInt Mask = APInt::getLowBitsSet(HBitWidth, TrailingZeros);
+ PartialRemL = DAG.getNode(ISD::AND, dl, HiLoVT, LL,
+ DAG.getConstant(Mask, dl, HiLoVT));
+ } else if (TrailingZeros == HBitWidth) {
+ // All of LL is part of the remainder.
+ PartialRemL = LL;
+ } else {
+ // TrailingZeros > HBitWidth: LL and part of LH are the remainder.
+ PartialRemL = LL;
+ APInt Mask = APInt::getLowBitsSet(HBitWidth, TrailingZeros - HBitWidth);
+ PartialRemH = DAG.getNode(ISD::AND, dl, HiLoVT, LH,
+ DAG.getConstant(Mask, dl, HiLoVT));
+ }
}
SDValue Sum;
@@ -8223,11 +8255,7 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
if (BestChunkWidth == HBitWidth) {
assert(!Alternate);
// Shift LH:LL right if there were trailing zeros in the divisor.
- if (TrailingZeros) {
- LL = GetFSHR(LL, LH, TrailingZeros);
- LH = DAG.getNode(ISD::SRL, dl, HiLoVT, LH,
- DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
- }
+ ShiftRight(LL, LH, TrailingZeros);
// Use uaddo_carry if we can, otherwise use a compare to detect overflow.
EVT SetCCType =
@@ -8309,11 +8337,8 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
if (Opcode != ISD::UREM) {
// If we didn't shift LH/LR earlier, do it now.
- if (BestChunkWidth != HBitWidth && TrailingZeros) {
- LL = GetFSHR(LL, LH, TrailingZeros);
- LH = DAG.getNode(ISD::SRL, dl, HiLoVT, LH,
- DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
- }
+ if (BestChunkWidth != HBitWidth)
+ ShiftRight(LL, LH, TrailingZeros);
// Subtract the remainder from the shifted dividend.
SDValue Dividend = DAG.getNode(ISD::BUILD_PAIR, dl, VT, LL, LH);
@@ -8339,11 +8364,32 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
// If we shifted the input, shift the remainder left and add the bits we
// shifted off the input.
if (TrailingZeros) {
- RemL = DAG.getNode(ISD::SHL, dl, HiLoVT, RemL,
- DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
-
- RemL = DAG.getNode(ISD::OR, dl, HiLoVT, RemL, PartialRem,
- SDNodeFlags::Disjoint);
+ if (TrailingZeros < HBitWidth) {
+ // Shift RemH:RemL left by TrailingZeros.
+ // RemH gets the high bits shifted out of RemL.
+ RemH = DAG.getNode(
+ ISD::SRL, dl, HiLoVT, RemL,
+ DAG.getShiftAmountConstant(HBitWidth - TrailingZeros, HiLoVT, dl));
+ RemL =
+ DAG.getNode(ISD::SHL, dl, HiLoVT, RemL,
+ DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
+ // OR in the partial remainder.
+ RemL = DAG.getNode(ISD::OR, dl, HiLoVT, RemL, PartialRemL,
+ SDNodeFlags::Disjoint);
+ } else if (TrailingZeros == HBitWidth) {
+ // Shift left by exactly HBitWidth: RemH becomes RemL, RemL becomes
+ // PartialRemL.
+ RemH = RemL;
+ RemL = PartialRemL;
+ } else {
+ // Shift left by more than HBitWidth.
+ RemH = DAG.getNode(
+ ISD::SHL, dl, HiLoVT, RemL,
+ DAG.getShiftAmountConstant(TrailingZeros - HBitWidth, HiLoVT, dl));
+ RemH = DAG.getNode(ISD::OR, dl, HiLoVT, RemH, PartialRemH,
+ SDNodeFlags::Disjoint);
+ RemL = PartialRemL;
+ }
}
Result.push_back(RemL);
Result.push_back(RemH);
diff --git a/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll b/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
index 3ded13cc31c7b..d1f5577c04454 100644
--- a/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
+++ b/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen2/i64/g' %s | llc -mtriple=riscv32 -mattr=+m | \
+; RUN: sed 's/iXLen2/i64/g' %s | sed 's/XLen/32/g' |llc -mtriple=riscv32 -mattr=+m | \
; RUN: FileCheck %s --check-prefix=RV32
-; RUN: sed 's/iXLen2/i128/g' %s | llc -mtriple=riscv64 -mattr=+m | \
+; RUN: sed 's/iXLen2/i128/g' %s | sed 's/XLen/64/g'| llc -mtriple=riscv64 -mattr=+m | \
; RUN: FileCheck %s --check-prefix=RV64
define iXLen2 @test_udiv_3(iXLen2 %x) nounwind {
@@ -678,3 +678,288 @@ define iXLen2 @test_udiv_12(iXLen2 %x) nounwind {
%a = udiv iXLen2 %x, 12
ret iXLen2 %a
}
+
+; Divisor: 7 * 2^30 (has 30 trailing zeros, < HBitWidth for RV32 and RV64)
+define iXLen2 @test_udiv_7_shl_30(iXLen2 %x) nounwind {
+; RV32-LABEL: test_udiv_7_shl_30:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a2, a1, 2
+; RV32-NEXT: srli a0, a0, 30
+; RV32-NEXT: srli a3, a1, 28
+; RV32-NEXT: lui a4, 599186
+; RV32-NEXT: lui a5, 449390
+; RV32-NEXT: lui a6, 748983
+; RV32-NEXT: srli a1, a1, 30
+; RV32-NEXT: or a0, a0, a2
+; RV32-NEXT: addi a2, a4, 1171
+; RV32-NEXT: addi a4, a5, -1171
+; RV32-NEXT: addi a5, a6, -585
+; RV32-NEXT: slli a6, a0, 2
+; RV32-NEXT: srli a6, a6, 2
+; RV32-NEXT: add a3, a6, a3
+; RV32-NEXT: mulhu a2, a3, a2
+; RV32-NEXT: srli a2, a2, 2
+; RV32-NEXT: slli a6, a2, 3
+; RV32-NEXT: sub a2, a2, a6
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: sub a3, a0, a2
+; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: mul a2, a3, a4
+; RV32-NEXT: mulhu a4, a3, a5
+; RV32-NEXT: sub a1, a1, a0
+; RV32-NEXT: add a2, a4, a2
+; RV32-NEXT: mul a1, a1, a5
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: mul a0, a3, a5
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_udiv_7_shl_30:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a1, 34
+; RV64-NEXT: srli a0, a0, 30
+; RV64-NEXT: srli a3, a1, 26
+; RV64-NEXT: lui a4, %hi(.LCPI11_0)
+; RV64-NEXT: lui a5, %hi(.LCPI11_1)
+; RV64-NEXT: lui a6, 748983
+; RV64-NEXT: srli a1, a1, 30
+; RV64-NEXT: or a0, a0, a2
+; RV64-NEXT: ld a2, %lo(.LCPI11_0)(a4)
+; RV64-NEXT: ld a4, %lo(.LCPI11_1)(a5)
+; RV64-NEXT: addi a5, a6, -585
+; RV64-NEXT: slli a6, a5, 33
+; RV64-NEXT: add a5, a5, a6
+; RV64-NEXT: slli a6, a0, 4
+; RV64-NEXT: srli a6, a6, 4
+; RV64-NEXT: add a3, a6, a3
+; RV64-NEXT: mulhu a2, a3, a2
+; RV64-NEXT: slli a6, a2, 3
+; RV64-NEXT: sub a2, a2, a6
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: sub a3, a0, a2
+; RV64-NEXT: sltu a0, a0, a2
+; RV64-NEXT: mul a2, a3, a4
+; RV64-NEXT: mulhu a4, a3, a5
+; RV64-NEXT: sub a1, a1, a0
+; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: mul a1, a1, a5
+; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: mul a0, a3, a5
+; RV64-NEXT: ret
+ %a = udiv iXLen2 %x, u0x1C0000000
+ ret iXLen2 %a
+}
+
+; Divisor: 3 * 2^32 (has 32 trailing zeros, exactly HBitWidth for RV32)
+define iXLen2 @test_udiv_3_shl_32(iXLen2 %x) nounwind {
+; RV32-LABEL: test_udiv_3_shl_32:
+; RV32: # %bb.0:
+; RV32-NEXT: lui a0, 699051
+; RV32-NEXT: addi a2, a0, -1365
+; RV32-NEXT: mulhu a3, a1, a2
+; RV32-NEXT: srli a0, a3, 1
+; RV32-NEXT: andi a3, a3, -2
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: mulhu a5, a4, a2
+; RV32-NEXT: sub a4, a1, a4
+; RV32-NEXT: sub a5, a5, a3
+; RV32-NEXT: sltu a1, a1, a4
+; RV32-NEXT: neg a1, a1
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, a5, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_udiv_3_shl_32:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a1, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: srli a1, a1, 32
+; RV64-NEXT: lui a3, 699051
+; RV64-NEXT: lui a4, %hi(.LCPI12_0)
+; RV64-NEXT: or a0, a0, a2
+; RV64-NEXT: addi a2, a3, -1365
+; RV64-NEXT: ld a3, %lo(.LCPI12_0)(a4)
+; RV64-NEXT: add a4, a0, a1
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: sltu a6, a4, a0
+; RV64-NEXT: add a2, a2, a5
+; RV64-NEXT: add a4, a4, a6
+; RV64-NEXT: mulhu a5, a4, a2
+; RV64-NEXT: srli a6, a5, 1
+; RV64-NEXT: andi a5, a5, -2
+; RV64-NEXT: add a5, a5, a6
+; RV64-NEXT: sub a4, a4, a5
+; RV64-NEXT: sub a5, a0, a4
+; RV64-NEXT: sltu a0, a0, a4
+; RV64-NEXT: mul a3, a5, a3
+; RV64-NEXT: mulhu a4, a5, a2
+; RV64-NEXT: sub a1, a1, a0
+; RV64-NEXT: add a3, a4, a3
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, a3, a1
+; RV64-NEXT: mul a0, a5, a2
+; RV64-NEXT: ret
+ %a = udiv iXLen2 %x, u0x300000000
+ ret iXLen2 %a
+}
+
+; Divisor: 7 * 2^60 (has 60 trailing zeros, > HBitWidth for RV32)
+define iXLen2 @test_udiv_7_shl_60(iXLen2 %x) nounwind {
+; RV32-LABEL: test_udiv_7_shl_60:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a1, a1, 28
+; RV32-NEXT: lui a0, 149797
+; RV32-NEXT: lui a2, 748983
+; RV32-NEXT: addi a0, a0, -1755
+; RV32-NEXT: addi a2, a2, -585
+; RV32-NEXT: mulhu a0, a1, a0
+; RV32-NEXT: slli a3, a0, 2
+; RV32-NEXT: slli a4, a0, 3
+; RV32-NEXT: or a3, a3, a0
+; RV32-NEXT: sub a4, a4, a0
+; RV32-NEXT: mulhu a5, a4, a2
+; RV32-NEXT: sub a4, a1, a4
+; RV32-NEXT: sub a5, a5, a3
+; RV32-NEXT: sltu a1, a1, a4
+; RV32-NEXT: neg a1, a1
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, a5, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_udiv_7_shl_60:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a1, 4
+; RV64-NEXT: srli a0, a0, 60
+; RV64-NEXT: srli a3, a1, 56
+; RV64-NEXT: lui a4, %hi(.LCPI13_0)
+; RV64-NEXT: lui a5, %hi(.LCPI13_1)
+; RV64-NEXT: lui a6, 748983
+; RV64-NEXT: srli a1, a1, 60
+; RV64-NEXT: or a0, a0, a2
+; RV64-NEXT: ld a2, %lo(.LCPI13_0)(a4)
+; RV64-NEXT: ld a4, %lo(.LCPI13_1)(a5)
+; RV64-NEXT: addi a5, a6, -585
+; RV64-NEXT: slli a6, a5, 33
+; RV64-NEXT: add a5, a5, a6
+; RV64-NEXT: slli a6, a0, 4
+; RV64-NEXT: srli a6, a6, 4
+; RV64-NEXT: add a3, a6, a3
+; RV64-NEXT: mulhu a2, a3, a2
+; RV64-NEXT: slli a6, a2, 3
+; RV64-NEXT: sub a2, a2, a6
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: sub a3, a0, a2
+; RV64-NEXT: sltu a0, a0, a2
+; RV64-NEXT: mul a2, a3, a4
+; RV64-NEXT: mulhu a4, a3, a5
+; RV64-NEXT: sub a1, a1, a0
+; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: mul a1, a1, a5
+; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: mul a0, a3, a5
+; RV64-NEXT: ret
+ %a = udiv iXLen2 %x, u0x7000000000000000
+ ret iXLen2 %a
+}
+
+; Divisor: 37 * 2^XLen (has XLen trailing zeros)
+define iXLen2 @test_udiv_37_shl_XL(iXLen2 %x) nounwind {
+; RV32-LABEL: test_udiv_37_shl_XL:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a0, a1, 18
+; RV32-NEXT: slli a2, a1, 14
+; RV32-NEXT: lui a3, 64
+; RV32-NEXT: lui a4, 765177
+; RV32-NEXT: li a5, 37
+; RV32-NEXT: srli a2, a2, 14
+; RV32-NEXT: sub a2, a2, a0
+; RV32-NEXT: lui a0, 85020
+; RV32-NEXT: addi a3, a3, 1
+; RV32-NEXT: addi a4, a4, 333
+; RV32-NEXT: add a2, a2, a3
+; RV32-NEXT: mulhu a3, a2, a4
+; RV32-NEXT: sub a4, a2, a3
+; RV32-NEXT: srli a4, a4, 1
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: lui a4, 595138
+; RV32-NEXT: addi a0, a0, -1329
+; RV32-NEXT: addi a4, a4, -1107
+; RV32-NEXT: srli a3, a3, 5
+; RV32-NEXT: mul a3, a3, a5
+; RV32-NEXT: sub a2, a2, a3
+; RV32-NEXT: sub a3, a1, a2
+; RV32-NEXT: sltu a1, a1, a2
+; RV32-NEXT: mul a0, a3, a0
+; RV32-NEXT: mulhu a2, a3, a4
+; RV32-NEXT: neg a1, a1
+; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: mul a1, a1, a4
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: mul a0, a3, a4
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_udiv_37_shl_XL:
+; RV64: # %bb.0:
+; RV64-NEXT: srli a0, a1, 36
+; RV64-NEXT: slli a2, a1, 28
+; RV64-NEXT: lui a3, %hi(.LCPI14_0)
+; RV64-NEXT: li a4, 37
+; RV64-NEXT: lui a5, 595138
+; RV64-NEXT: srli a2, a2, 28
+; RV64-NEXT: ld a3, %lo(.LCPI14_0)(a3)
+; RV64-NEXT: addi a5, a5, -1107
+; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: slli a2, a5, 36
+; RV64-NEXT: add a2, a5, a2
+; RV64-NEXT: lui a5, %hi(.LCPI14_1)
+; RV64-NEXT: ld a5, %lo(.LCPI14_1)(a5)
+; RV64-NEXT: mulhu a3, a0, a3
+; RV64-NEXT: mul a3, a3, a4
+; RV64-NEXT: sub a0, a0, a3
+; RV64-NEXT: sub a3, a1, a0
+; RV64-NEXT: sltu a0, a1, a0
+; RV64-NEXT: mul a1, a3, a5
+; RV64-NEXT: mulhu a4, a3, a2
+; RV64-NEXT: neg a0, a0
+; RV64-NEXT: add a1, a4, a1
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a1, a1, a0
+; RV64-NEXT: mul a0, a3, a2
+; RV64-NEXT: ret
+ %a = shl iXLen2 37, XLen
+ %b = udiv iXLen2 %x, %a
+ ret iXLen2 %b
+}
+
+; Divisor: 3 * 2^(XLen+5) (has XLen+5 trailing zeros)
+define iXLen2 @test_urem_3_shl_XLplus5(iXLen2 %x) nounwind {
+; RV32-LABEL: test_urem_3_shl_XLplus5:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a2, a1, 5
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: addi a3, a3, 1366
+; RV32-NEXT: mulhu a3, a2, a3
+; RV32-NEXT: slli a4, a3, 1
+; RV32-NEXT: sub a2, a2, a3
+; RV32-NEXT: sub a2, a2, a4
+; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: andi a1, a1, 31
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_urem_3_shl_XLplus5:
+; RV64: # %bb.0:
+; RV64-NEXT: lui a2, %hi(.LCPI15_0)
+; RV64-NEXT: ld a2, %lo(.LCPI15_0)(a2)
+; RV64-NEXT: srli a3, a1, 5
+; RV64-NEXT: mulhu a2, a3, a2
+; RV64-NEXT: slli a4, a2, 1
+; RV64-NEXT: sub a3, a3, a2
+; RV64-NEXT: sub a3, a3, a4
+; RV64-NEXT: slli a3, a3, 5
+; RV64-NEXT: andi a1, a1, 31
+; RV64-NEXT: or a1, a3, a1
+; RV64-NEXT: ret
+ %a = shl iXLen2 96, XLen
+ %b = urem iXLen2 %x, %a
+ ret iXLen2 %b
+}
diff --git a/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll b/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
index 2a890e8bb1aa4..61bb4ffc2e48c 100644
--- a/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
+++ b/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen2/i64/g' %s | llc -mtriple=riscv32 -mattr=+m | \
+; RUN: sed 's/iXLen2/i64/g' %s | sed 's/XLen/32/g' |llc -mtriple=riscv32 -mattr=+m | \
; RUN: FileCheck %s --check-prefix=RV32
-; RUN: sed 's/iXLen2/i128/g' %s | llc -mtriple=riscv64 -mattr=+m | \
+; RUN: sed 's/iXLen2/i128/g' %s | sed 's/XLen/64/g'| llc -mtriple=riscv64 -mattr=+m | \
; RUN: FileCheck %s --check-prefix=RV64
define iXLen2 @test_urem_3(iXLen2 %x) nounwind {
@@ -439,3 +439,211 @@ define iXLen2 @test_urem_12(iXLen2 %x) nounwind {
%a = urem iXLen2 %x, 12
ret iXLen2 %a
}
+
+; Divisor: 7 * 2^30 (has 30 trailing zeros, < HBitWidth for RV32 and RV64)
+define iXLen2 @test_urem_7_shl_30(iXLen2 %x) nounwind {
+; RV32-LABEL: test_urem_7_shl_30:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a2, a1, 2
+; RV32-NEXT: srli a3, a0, 30
+; RV32-NEXT: lui a4, 262144
+; RV32-NEXT: srli a1, a1, 28
+; RV32-NEXT: or a2, a3, a2
+; RV32-NEXT: lui a3, 599186
+; RV32-NEXT: addi a4, a4, -1
+; RV32-NEXT: addi a3, a3, 1171
+; RV32-NEXT: and a2, a2, a4
+; RV32-NEXT: and a0, a0, a4
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: mulhu a2, a1, a3
+; RV32-NEXT: srli a2, a2, 2
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: sub a2, a2, a3
+; RV32-NEXT: add a1, a1, a2
+; RV32-NEXT: slli a2, a1, 30
+; RV32-NEXT: or a0, a2, a0
+; RV32-NEXT: srli a1, a1, 2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_urem_7_shl_30:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a1, 34
+; RV64-NEXT: srli a3, a0, 30
+; RV64-NEXT: srli a1, a1, 26
+; RV64-NEXT: or a2, a3, a2
+; RV64-NEXT: lui a3, %hi(.LCPI11_0)
+; RV64-NEXT: slli a0, a0, 34
+; RV64-NEXT: ld a3, %lo(.LCPI11_0)(a3)
+; RV64-NEXT: slli a2, a2, 4
+; RV64-NEXT: srli a2, a2, 4
+; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: mulhu a2, a1, a3
+; RV64-NEXT: slli a3, a2, 3
+; RV64-NEXT: sub a2, a2, a3
+; RV64-NEXT: add a1, a1, a2
+; RV64-NEXT: slli a1, a1, 30
+; RV64-NEXT: srli a0, a0, 34
+; RV64-NEXT: or a0, a1, a0
+; RV64-NEXT: li a1, 0
+; RV64-NEXT: ret
+ %a = urem iXLen2 %x, u0x1C0000000
+ ret iXLen2 %a
+}
+
+; Divisor: 3 * 2^32 (has 32 trailing zeros, exactly HBitWidth for RV32)
+define iXLen2 @test_urem_3_shl_32(iXLen2 %x) nounwind {
+; RV32-LABEL: test_urem_3_shl_32:
+; RV32: # %bb.0:
+; RV32-NEXT: lui a2, 699051
+; RV32-NEXT: addi a2, a2, -1365
+; RV32-NEXT: mulhu a2, a1, a2
+; RV32-NEXT: srli a3, a2, 1
+; RV32-NEXT: andi a2, a2, -2
+; RV32-NEXT: add a2, a2, a3
+; RV32-NEXT: sub a1, a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_urem_3_shl_32:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a1, 32
+; RV64-NEXT: srli a3, a0, 32
+; RV64-NEXT: lui a4, 699051
+; RV64-NEXT: or a2, a3, a2
+; RV64-NEXT: addi a3, a4, -1365
+; RV64-NEXT: slli a4, a3, 32
+; RV64-NEXT: add a3, a3, a4
+; RV64-NEXT: srli a1, a1, 32
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: sltu a2, a1, a2
+; RV64-NEXT: add a1, a1, a2
+; RV64-NEXT: mulhu a2, a1, a3
+; RV64-NEXT: srli a3, a2, 1
+; RV64-NEXT: andi a2, a2, -2
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: sub a1, a1, a2
+; RV64-NEXT: slli a1, a1, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: or a0, a1, a0
+; RV64-NEXT: li a1, 0
+; RV64-NEXT: ret
+ %a = urem iXLen2 %x, u0x300000000
+ ret iXLen2 %a
+}
+
+; Divisor: 7 * 2^60 (has 60 trailing zeros, > HBitWidth for RV32)
+define iXLen2 @test_urem_7_shl_60(iXLen2 %x) nounwind {
+; RV32-LABEL: test_urem_7_shl_60:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a2, a1, 28
+; RV32-NEXT: lui a3, 149797
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: addi a3, a3, -1755
+; RV32-NEXT: mulhu a3, a2, a3
+; RV32-NEXT: slli a4, a3, 3
+; RV32-NEXT: add a2, a2, a3
+; RV32-NEXT: sub a2, a2, a4
+; RV32-NEXT: slli a2, a2, 28
+; RV32-NEXT: srli a1, a1, 4
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_urem_7_shl_60:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a2, a1, 4
+; RV64-NEXT: srli a3, a0, 60
+; RV64-NEXT: li a4, -1
+; RV64-NEXT: srli a1, a1, 56
+; RV64-NEXT: or a2, a3, a2
+; RV64-NEXT: lui a3, %hi(.LCPI13_0)
+; RV64-NEXT: ld a3, %lo(.LCPI13_0)(a3)
+; RV64-NEXT: srli a4, a4, 4
+; RV64-NEXT: and a2, a2, a4
+; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: mulhu a2, a1, a3
+; RV64-NEXT: slli a3, a2, 3
+; RV64-NEXT: add a1, a1, a2
+; RV64-NEXT: sub a1, a1, a3
+; RV64-NEXT: slli a1, a1, 60
+; RV64-NEXT: and a0, a0, a4
+; RV64-NEXT: or a0, a1, a0
+; RV64-NEXT: li a1, 0
+; RV64-NEXT: ret
+ %a = urem iXLen2 %x, u0x7000000000000000
+ ret iXLen2 %a
+}
+
+; Divisor: 37 * 2^XLen (has XLen trailing zeros)
+define iXLen2 @test_urem_37_shl_XL(iXLen2 %x) nounwind {
+; RV32-LABEL: test_urem_37_shl_XL:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a2, a1, 18
+; RV32-NEXT: slli a1, a1, 14
+; RV32-NEXT: lui a3, 64
+; RV32-NEXT: srli a1, a1, 14
+; RV32-NEXT: sub a1, a1, a2
+; RV32-NEXT: lui a2, 765177
+; RV32-NEXT: addi a3, a3, 1
+; RV32-NEXT: addi a2, a2, 333
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: mulhu a2, a1, a2
+; RV32-NEXT: sub a3, a1, a2
+; RV32-NEXT: srli a3, a3, 1
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: srli a2, a2, 5
+; RV32-NEXT: li a3, 37
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: sub a1, a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_urem_37_shl_XL:
+; RV64: # %bb.0:
+; RV64-NEXT: srli a2, a1, 36
+; RV64-NEXT: lui a3, %hi(.LCPI14_0)
+; RV64-NEXT: ld a3, %lo(.LCPI14_0)(a3)
+; RV64-NEXT: slli a1, a1, 28
+; RV64-NEXT: srli a1, a1, 28
+; RV64-NEXT: add a1, a1, a2
+; RV64-NEXT: mulhu a2, a1, a3
+; RV64-NEXT: li a3, 37
+; RV64-NEXT: mul a2, a2, a3
+; RV64-NEXT: sub a1, a1, a2
+; RV64-NEXT: ret
+ %a = shl iXLen2 37, XLen
+ %b = urem iXLen2 %x, %a
+ ret iXLen2 %b
+}
+
+; Divisor: 3 * 2^(XLen+5) (has XLen+ trailing zeros)
+define iXLen2 @test_urem_3_shl_XLplus5(iXLen2 %x) nounwind {
+; RV32-LABEL: test_urem_3_shl_XLplus5:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a2, a1, 5
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: addi a3, a3, 1366
+; RV32-NEXT: mulhu a3, a2, a3
+; RV32-NEXT: slli a4, a3, 1
+; RV32-NEXT: sub a2, a2, a3
+; RV32-NEXT: sub a2, a2, a4
+; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: andi a1, a1, 31
+; RV32-NEXT: or a1, a2, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_urem_3_shl_XLplus5:
+; RV64: # %bb.0:
+; RV64-NEXT: lui a2, %hi(.LCPI15_0)
+; RV64-NEXT: ld a2, %lo(.LCPI15_0)(a2)
+; RV64-NEXT: srli a3, a1, 5
+; RV64-NEXT: mulhu a2, a3, a2
+; RV64-NEXT: slli a4, a2, 1
+; RV64-NEXT: sub a3, a3, a2
+; RV64-NEXT: sub a3, a3, a4
+; RV64-NEXT: slli a3, a3, 5
+; RV64-NEXT: andi a1, a1, 31
+; RV64-NEXT: or a1, a3, a1
+; RV64-NEXT: ret
+ %a = shl iXLen2 96, XLen
+ %b = urem iXLen2 %x, %a
+ ret iXLen2 %b
+}
diff --git a/llvm/test/CodeGen/X86/i128-udiv.ll b/llvm/test/CodeGen/X86/i128-udiv.ll
index 9a72520fb1a01..e25584c64496a 100644
--- a/llvm/test/CodeGen/X86/i128-udiv.ll
+++ b/llvm/test/CodeGen/X86/i128-udiv.ll
@@ -320,11 +320,29 @@ define i128 @test2(i128 %x) nounwind {
;
; X64-LABEL: test2:
; X64: # %bb.0:
-; X64-NEXT: pushq %rax
-; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: movq $-4, %rcx
-; X64-NEXT: callq __udivti3 at PLT
-; X64-NEXT: popq %rcx
+; X64-NEXT: shrq $2, %rsi
+; X64-NEXT: movabsq $2305843009213693953, %rcx # imm = 0x2000000000000001
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: mulq %rcx
+; X64-NEXT: shrq $59, %rdx
+; X64-NEXT: movq %rdx, %rax
+; X64-NEXT: shlq $62, %rax
+; X64-NEXT: subq %rax, %rdx
+; X64-NEXT: addq %rsi, %rdx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: subq %rdx, %rsi
+; X64-NEXT: sbbq %rax, %rax
+; X64-NEXT: movq %rax, %rcx
+; X64-NEXT: shlq $62, %rcx
+; X64-NEXT: addq %rax, %rcx
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: shlq $60, %rax
+; X64-NEXT: leaq (%rsi,%rax), %rdi
+; X64-NEXT: movabsq $-4611686018427387905, %rdx # imm = 0xBFFFFFFFFFFFFFFF
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: mulq %rdx
+; X64-NEXT: subq %rdi, %rdx
+; X64-NEXT: subq %rcx, %rdx
; X64-NEXT: retq
%tmp = udiv i128 %x, -73786976294838206464
ret i128 %tmp
>From 6d4fb5bc94a004f2f285450411c5565926281d5c Mon Sep 17 00:00:00 2001
From: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: Sun, 12 Apr 2026 23:18:43 -0700
Subject: [PATCH 14/36] [SLP] Fix handling of strided loads during
re-vectorization (#191294)
Fixes #191292
---
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 7 ++++---
.../SLPVectorizer/RISCV/revec-strided-load.ll | 10 ++++++++--
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 0e647fa235916..87830329be1e2 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -7260,6 +7260,7 @@ bool BoUpSLP::analyzeConstantStrideCandidate(
// Quick detour: at this point we can say what the type of strided load would
// be if all the checks pass. Check if this type is legal for the target.
bool NeedsWidening = Sz != GroupSize;
+ const uint64_t UnitBitWidth = DL->getTypeSizeInBits(ScalarTy).getFixedValue();
if (NeedsWidening) {
if (Sz % GroupSize != 0)
return false;
@@ -7267,9 +7268,9 @@ bool BoUpSLP::analyzeConstantStrideCandidate(
if (StrideWithinGroup != 1)
return false;
VecSz = Sz / GroupSize;
- NewScalarTy = Type::getIntNTy(
- SE->getContext(),
- DL->getTypeSizeInBits(ScalarTy).getFixedValue() * GroupSize);
+ NewScalarTy = Type::getIntNTy(SE->getContext(), UnitBitWidth * GroupSize);
+ } else if (ScalarTy->isVectorTy()) {
+ NewScalarTy = Type::getIntNTy(SE->getContext(), UnitBitWidth);
}
if (!isStridedLoad(PointerOps, NewScalarTy, Alignment, Diff, VecSz))
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
index 8c7ba2f980bf7..6d62659c2fef1 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
@@ -5,7 +5,8 @@
define void @widened_strided_load(ptr %in0, ptr %out0) {
; CHECK-LABEL: @widened_strided_load(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.experimental.vp.strided.load.v16i8.p0.i64(ptr align 2 [[IN0:%.*]], i64 16, <16 x i1> splat (i1 true), i32 16)
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.experimental.vp.strided.load.v2i64.p0.i64(ptr align 2 [[IN0:%.*]], i64 16, <2 x i1> splat (i1 true), i32 2)
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
; CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[OUT0:%.*]], align 2
; CHECK-NEXT: ret void
;
@@ -50,7 +51,12 @@ entry:
define void @too_wide(ptr %in0, ptr %out0) {
; CHECK-LABEL: @too_wide(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call <16 x i16> @llvm.experimental.vp.strided.load.v16i16.p0.i64(ptr align 2 [[IN0:%.*]], i64 32, <16 x i1> splat (i1 true), i32 16)
+; CHECK-NEXT: [[IN1:%.*]] = getelementptr i16, ptr [[IN0:%.*]], i64 16
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr> poison, ptr [[IN0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP4]], ptr [[IN1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x ptr> [[TMP1]], <2 x ptr> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, <16 x ptr> [[TMP2]], <16 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
+; CHECK-NEXT: [[TMP0:%.*]] = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> align 2 [[TMP3]], <16 x i1> splat (i1 true), <16 x i16> poison)
; CHECK-NEXT: store <16 x i16> [[TMP0]], ptr [[OUT0:%.*]], align 2
; CHECK-NEXT: ret void
;
>From a5a5cdbd18c6c83dfcd6156b24a811b536096569 Mon Sep 17 00:00:00 2001
From: Arun Thangamani <arun.thangamani at intel.com>
Date: Mon, 13 Apr 2026 12:01:45 +0530
Subject: [PATCH 15/36] [mlir][x86] Lower packed type vector.contract to AMX
dot-product (online-packing) (#188192)
A transform pass to lower flat layout `vector.contract` operation to (a)
amx.tile_mulf for BF16, or (b) amx.tile_muli for Int8 packed types via
`online` packing.
TODOs: On an another `patch` planned to re-factor this pass + retiring
`convert-vector-to-amx` pass.
---
.../VectorContractToAMXDotProduct.cpp | 1059 ++++++++++++++---
.../X86/AMX/vector-contract-to-tiled-dp.mlir | 500 +++++++-
2 files changed, 1373 insertions(+), 186 deletions(-)
diff --git a/mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp b/mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
index 85966a85af40e..94b94292e675f 100644
--- a/mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
+++ b/mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
@@ -189,13 +189,16 @@ static unsigned getIndexPosition(Value operand, scf::ForOp loop) {
// Creates amx.tile_loads.
static amx::TileLoadOp createTileLoads(OpBuilder &rewriter, Location loc,
Value operand, Value mat, Type ipType,
- bool rhs, unsigned int offset) {
+ bool rhs, unsigned int offset,
+ bool isVnni) {
auto srcIndx = getSrcIndxValue(rewriter, loc, operand, false);
auto [srcBuff, indices] = *srcIndx;
- indices.pop_back();
+ if (isVnni) {
+ indices.pop_back();
+ }
- if (rhs) {
+ if (rhs && isVnni) {
auto cOffset = arith::ConstantIndexOp::create(rewriter, loc, offset);
indices[indices.size() - 1] = arith::MulIOp::create(
rewriter, loc, indices[indices.size() - 1], cOffset);
@@ -205,21 +208,164 @@ static amx::TileLoadOp createTileLoads(OpBuilder &rewriter, Location loc,
return amx::TileLoadOp::create(rewriter, loc, tileType, mat, indices);
}
-// Creates tiled amx dot-products.
-static SmallVector<Value> createTiledDp(OpBuilder &rewriter, Location loc,
- SmallVector<vector::ContractionOp> ops,
- Value matA, Value matB, Type ipType,
- Type opType, ValueRange accIterArgs,
- unsigned int offset) {
+static void performShuffle(OpBuilder &rewriter, Location loc, Value matB,
+ Type ipType, unsigned int offset, Value packedBuffer,
+ Value indxToStoreInBuffer) {
+
+ Value c0 = arith::ConstantIndexOp::create(rewriter, loc, 0);
+ Value c16 = arith::ConstantIndexOp::create(rewriter, loc, 16);
+
+ auto subview = matB.getDefiningOp<mlir::memref::SubViewOp>();
+ SmallVector<Value> subviewOffset(subview.getOffsets().size(), c0);
+
+ Value cStep = arith::ConstantIndexOp::create(rewriter, loc, offset);
+ Value cBound = arith::ConstantIndexOp::create(rewriter, loc, (16 * offset));
+ Value offsetIndx =
+ arith::ConstantIndexOp::create(rewriter, loc, (offset / 2));
+
+ scf::ForOp::create(
+ rewriter, loc, c0, cBound, cStep, ValueRange{},
+ [&](OpBuilder &nestedBuilder, Location loc, Value iv,
+ ValueRange iterArgs) {
+ subviewOffset[subviewOffset.size() - 2] = iv;
+ auto vec1 = vector::LoadOp::create(
+ rewriter, loc, VectorType::get((16 * offset), ipType), matB,
+ ValueRange(subviewOffset));
+
+ // Increment the iv by 1 or 2 based on the type to load the next 32/64
+ // elements
+ Value incIV = arith::AddIOp::create(rewriter, loc, offsetIndx, iv);
+ subviewOffset[subviewOffset.size() - 2] = incIV;
+ auto vec2 = vector::LoadOp::create(
+ rewriter, loc, VectorType::get((16 * offset), ipType), matB,
+ ValueRange(subviewOffset));
+
+ vector::ShuffleOp shuffle1;
+ vector::ShuffleOp shuffle2;
+
+ if (ipType.isBF16()) {
+
+ shuffle1 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get({(16 * offset)}, ipType), vec1,
+ vec2,
+ ArrayRef<int64_t>{0, 32, 1, 33, 2, 34, 3, 35, 8, 40, 9,
+ 41, 10, 42, 11, 43, 16, 48, 17, 49, 18, 50,
+ 19, 51, 24, 56, 25, 57, 26, 58, 27, 59});
+
+ shuffle2 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get({(16 * offset)}, ipType), vec1,
+ vec2,
+ ArrayRef<int64_t>{4, 36, 5, 37, 6, 38, 7, 39, 12, 44, 13,
+ 45, 14, 46, 15, 47, 20, 52, 21, 53, 22, 54,
+ 23, 55, 28, 60, 29, 61, 30, 62, 31, 63});
+ }
+
+ if (ipType.isSignlessInteger(8)) {
+
+ shuffle1 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get({(16 * offset)}, ipType), vec1,
+ vec2,
+ ArrayRef<int64_t>{
+ 0, 32, 64, 96, 1, 33, 65, 97, 2, 34, 66, 98, 3,
+ 35, 67, 99, 8, 40, 72, 104, 9, 41, 73, 105, 10, 42,
+ 74, 106, 11, 43, 75, 107, 16, 48, 80, 112, 17, 49, 81,
+ 113, 18, 50, 82, 114, 19, 51, 83, 115, 24, 56, 88, 120,
+ 25, 57, 89, 121, 26, 58, 90, 122, 27, 59, 91, 123});
+
+ shuffle2 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get({(16 * offset)}, ipType), vec1,
+ vec2,
+ ArrayRef<int64_t>{
+ 4, 36, 68, 100, 5, 37, 69, 101, 6, 38, 70, 102, 7, 39,
+ 71, 103, 12, 44, 76, 108, 13, 45, 77, 109, 14, 46, 78, 110,
+ 15, 47, 79, 111, 20, 52, 84, 116, 21, 53, 85, 117, 22, 54,
+ 86, 118, 23, 55, 87, 119, 28, 60, 92, 124, 29, 61, 93, 125,
+ 30, 62, 94, 126, 31, 63, 95, 127});
+ }
+
+ // iv to store the shuffled elements
+ Value ivShuff1 = arith::DivUIOp::create(rewriter, loc, iv, cStep);
+ Value ivShuff2 = arith::AddIOp::create(rewriter, loc, ivShuff1, c16);
+
+ vector::StoreOp::create(rewriter, loc, shuffle1, packedBuffer,
+ ValueRange{indxToStoreInBuffer, ivShuff1, c0});
+ vector::StoreOp::create(rewriter, loc, shuffle2, packedBuffer,
+ ValueRange{indxToStoreInBuffer, ivShuff2, c0});
+
+ scf::YieldOp::create(nestedBuilder, loc);
+ });
+}
+
+static llvm::DenseMap<Operation *, amx::TileLoadOp>
+packInputs(OpBuilder &rewriter, Location loc,
+ SmallVector<vector::ContractionOp> ops, Value matB, Type ipType,
+ unsigned int offset, Value packedBuffer, bool pack,
+ Value indxToStoreInBuffer, Value indxToLoadFromMatB) {
+
+ llvm::DenseMap<Operation *, amx::TileLoadOp> readsToTileLoads;
+ Value c0 = arith::ConstantIndexOp::create(rewriter, loc, 0);
+ Value c16 = arith::ConstantIndexOp::create(rewriter, loc, 16);
+
+ for (size_t j = 0; j < ops.size(); j++) {
+ for (size_t i = 0; i < ops.size(); i++) {
+
+ if (i != j && validatePairVectorContract(ops[j], ops[i], true, 16)) {
+
+ Operation *readOpRhs = ops[j].getRhs().getDefiningOp();
+ auto itRhs = readsToTileLoads.find(readOpRhs);
+ if (itRhs != readsToTileLoads.end()) {
+ continue;
+ }
+
+ if (pack) {
+ performShuffle(rewriter, loc, matB, ipType, offset, packedBuffer,
+ indxToStoreInBuffer);
+ }
+
+ amx::TileType tileType =
+ amx::TileType::get({16, (16 * offset)}, ipType);
+ auto loadRow1 =
+ amx::TileLoadOp::create(rewriter, loc, tileType, packedBuffer,
+ ValueRange{indxToLoadFromMatB, c0, c0});
- auto subviewCollapseLhs = collapseInnerDims(rewriter, loc, matA);
- auto subviewCollapseRhs = collapseInnerDims(rewriter, loc, matB);
+ auto loadRow2 =
+ amx::TileLoadOp::create(rewriter, loc, tileType, packedBuffer,
+ ValueRange{indxToLoadFromMatB, c16, c0});
+
+ readsToTileLoads.try_emplace(readOpRhs, loadRow1);
+ readsToTileLoads.try_emplace(ops[i].getRhs().getDefiningOp(), loadRow2);
+ }
+ }
+ }
+
+ return readsToTileLoads;
+}
+
+// Creates tiled amx dot-products.
+static SmallVector<Value>
+createTiledDp(OpBuilder &rewriter, Location loc,
+ SmallVector<vector::ContractionOp> ops, Value matA, Value matB,
+ Type ipType, Type opType, ValueRange accIterArgs,
+ unsigned int offset, bool isVnni, Value packedBuffer, bool pack,
+ Value indxToStoreInBuffer, Value indxToLoadFromMatB) {
+
+ if (isVnni) {
+ matA = collapseInnerDims(rewriter, loc, matA);
+ matB = collapseInnerDims(rewriter, loc, matB);
+ }
SmallVector<Value> accumulators;
// Stores the amx.tile_load operation vs it's equivalent vector tranfer_read
// or load operations.
llvm::DenseMap<Operation *, amx::TileLoadOp> readsToTileLoads;
+ // function call to online pack the input B matrix
+ if (!isVnni) {
+ readsToTileLoads =
+ packInputs(rewriter, loc, ops, matB, ipType, offset, packedBuffer, pack,
+ indxToStoreInBuffer, indxToLoadFromMatB);
+ }
+
// Iterate over the contraction operations and compute the tiled dot-product.
for (size_t i = 0; i < ops.size(); i++) {
@@ -229,8 +375,8 @@ static SmallVector<Value> createTiledDp(OpBuilder &rewriter, Location loc,
if (itLhs != readsToTileLoads.end()) {
tilesLhs = itLhs->second;
} else {
- tilesLhs = createTileLoads(rewriter, loc, ops[i].getLhs(),
- subviewCollapseLhs, ipType, false, offset);
+ tilesLhs = createTileLoads(rewriter, loc, ops[i].getLhs(), matA, ipType,
+ false, offset, isVnni);
readsToTileLoads.try_emplace(readOpLhs, tilesLhs);
}
@@ -240,8 +386,8 @@ static SmallVector<Value> createTiledDp(OpBuilder &rewriter, Location loc,
if (itRhs != readsToTileLoads.end()) {
tilesRhs = itRhs->second;
} else {
- tilesRhs = createTileLoads(rewriter, loc, ops[i].getRhs(),
- subviewCollapseRhs, ipType, true, offset);
+ tilesRhs = createTileLoads(rewriter, loc, ops[i].getRhs(), matB, ipType,
+ true, offset, isVnni);
readsToTileLoads.try_emplace(readOpRhs, tilesRhs);
}
@@ -276,10 +422,184 @@ static SmallVector<Value> createTileZeros(OpBuilder &rewriter, Location loc,
return loopItrArgs;
}
+static Value getIndxToLoadStoreFromPckBuffer(
+ OpBuilder &rewriter, Location loc, Value ivInnerLoop, Value ivOuterLoop,
+ bool isInnerLoopUBHasOddQuot, bool isInnerLoopUBLarger, bool pack,
+ unsigned int blockingFactor) {
+
+ Value c2 = arith::ConstantIndexOp::create(rewriter, loc, 2);
+ Value packOffset =
+ arith::ConstantIndexOp::create(rewriter, loc, (16 * blockingFactor));
+
+ Value quotientInnerLoop =
+ arith::DivUIOp::create(rewriter, loc, ivInnerLoop, packOffset);
+ Value remInnerLoop = arith::RemUIOp::create(
+ rewriter, loc, rewriter.getIndexType(), quotientInnerLoop, c2);
+
+ if (!isInnerLoopUBLarger && !pack) {
+ remInnerLoop = arith::RemUIOp::create(
+ rewriter, loc, rewriter.getIndexType(), ivOuterLoop, c2);
+ }
+
+ if (isInnerLoopUBHasOddQuot) {
+ auto remOuterLoop = arith::RemUIOp::create(
+ rewriter, loc, rewriter.getIndexType(), ivOuterLoop, c2);
+ auto remAdd = arith::AddIOp::create(rewriter, loc, rewriter.getIndexType(),
+ remInnerLoop, remOuterLoop);
+ remInnerLoop = arith::RemUIOp::create(rewriter, loc,
+ rewriter.getIndexType(), remAdd, c2);
+ }
+
+ return remInnerLoop;
+}
+
+static scf::ForOp
+createLoops(OpBuilder &rewriter, Location loc, Value lowerBound,
+ Value upperBound, Value step, SmallVector<Value> loopItrArgs,
+ Type ipType, Type opType, unsigned int blockingFactor, bool isVnni,
+ Operation *vectorOpLhs, Operation *vectorOpRhs,
+ vector::ContractionOp contractOp, scf::ForOp outerLoop,
+ scf::ForOp innerLoop, SmallVector<vector::ContractionOp> ops,
+ Value ivOuterLoop, Value packedBuffer, bool pack,
+ arith::ConstantIndexOp innerLoopIndex, bool isInnerLoopUBLarger,
+ bool isInnerLoopUBHasOddQuot) {
+
+ Value c0 = arith::ConstantIndexOp::create(rewriter, loc, 0);
+ Value c1 = arith::ConstantIndexOp::create(rewriter, loc, 1);
+ Value c2 = arith::ConstantIndexOp::create(rewriter, loc, 2);
+
+ auto newLoop = scf::ForOp::create(
+ rewriter, loc, lowerBound, upperBound, step, loopItrArgs,
+ [&](OpBuilder &rewriterNewInnerLoop, Location locNewInnerLoop,
+ Value ivNewInnerLoop, ValueRange iterArgsNewInnerLoop) {
+ IRMapping mapping;
+ if (outerLoop)
+ mapping.map(vectorOpLhs->getOperand(
+ getIndexPosition(contractOp.getLhs(), outerLoop) + 1),
+ ivOuterLoop);
+
+ mapping.map(vectorOpLhs->getOperand(
+ getIndexPosition(contractOp.getLhs(), innerLoop) + 1),
+ ivNewInnerLoop);
+ auto lhsClone = rewriterNewInnerLoop.clone(*vectorOpLhs, mapping);
+
+ Value indxToStoreInBuffer = c0;
+ Value indxToLoadFromBuffer = c0;
+
+ if (!isVnni) {
+ if (outerLoop) {
+ if (innerLoopIndex.value() == 0) {
+ if (pack) {
+ ivNewInnerLoop = c0;
+ ivOuterLoop = arith::AddIOp::create(rewriter, locNewInnerLoop,
+ c1, ivOuterLoop);
+
+ if (!isInnerLoopUBLarger || isInnerLoopUBHasOddQuot) {
+ indxToStoreInBuffer = arith::RemUIOp::create(
+ rewriter, locNewInnerLoop, rewriter.getIndexType(),
+ ivOuterLoop, c2);
+ }
+
+ Value indxToLoadFromMatB = arith::AddIOp::create(
+ rewriter, loc, indxToStoreInBuffer, c1);
+ indxToLoadFromBuffer = arith::RemUIOp::create(
+ rewriter, loc, rewriter.getIndexType(), indxToLoadFromMatB,
+ c2);
+ }
+
+ } else {
+ Value nLoadIndx = arith::ConstantIndexOp::create(
+ rewriter, locNewInnerLoop, (16 * blockingFactor));
+ ivNewInnerLoop = arith::AddIOp::create(rewriter, locNewInnerLoop,
+ nLoadIndx, ivNewInnerLoop);
+ indxToStoreInBuffer = getIndxToLoadStoreFromPckBuffer(
+ rewriter, loc, ivNewInnerLoop, ivOuterLoop,
+ isInnerLoopUBHasOddQuot, isInnerLoopUBLarger, pack,
+ blockingFactor);
+ Value indxToLoadFromMatB =
+ arith::AddIOp::create(rewriter, loc, indxToStoreInBuffer, c1);
+ indxToLoadFromBuffer =
+ arith::RemUIOp::create(rewriter, loc, rewriter.getIndexType(),
+ indxToLoadFromMatB, c2);
+ }
+ } else {
+ if (pack) {
+ Value nLoadIndx = arith::ConstantIndexOp::create(
+ rewriter, locNewInnerLoop, (16 * blockingFactor));
+ ivNewInnerLoop = arith::AddIOp::create(rewriter, locNewInnerLoop,
+ nLoadIndx, ivNewInnerLoop);
+ Value quotient_K = arith::DivUIOp::create(
+ rewriter, loc, ivNewInnerLoop, nLoadIndx);
+ indxToStoreInBuffer = arith::RemUIOp::create(
+ rewriter, loc, rewriter.getIndexType(), quotient_K, c2);
+
+ Value indxToLoadFromMatB =
+ arith::AddIOp::create(rewriter, loc, indxToStoreInBuffer, c1);
+ indxToLoadFromBuffer =
+ arith::RemUIOp::create(rewriter, loc, rewriter.getIndexType(),
+ indxToLoadFromMatB, c2);
+ }
+ }
+ }
+
+ IRMapping rhsMapping;
+ if (outerLoop)
+ rhsMapping.map(
+ vectorOpRhs->getOperand(
+ getIndexPosition(contractOp.getRhs(), outerLoop) + 1),
+ ivOuterLoop);
+
+ rhsMapping.map(
+ vectorOpRhs->getOperand(
+ getIndexPosition(contractOp.getRhs(), innerLoop) + 1),
+ ivNewInnerLoop);
+ auto rhsClone = rewriterNewInnerLoop.clone(*vectorOpRhs, rhsMapping);
+
+ Value matB = rhsClone->getResult(0);
+
+ if (!isVnni) {
+ if (outerLoop) {
+ if (!pack) {
+ Value nLoadIndx = arith::ConstantIndexOp::create(
+ rewriter, locNewInnerLoop, (16 * blockingFactor));
+ matB = Value();
+ indxToLoadFromBuffer = c0;
+ indxToLoadFromBuffer = getIndxToLoadStoreFromPckBuffer(
+ rewriter, loc, nLoadIndx, ivOuterLoop,
+ isInnerLoopUBHasOddQuot, isInnerLoopUBLarger, pack,
+ blockingFactor);
+ }
+ } else {
+ if (!pack) {
+ Value nLoadIndx = arith::ConstantIndexOp::create(
+ rewriter, locNewInnerLoop, (16 * blockingFactor));
+ matB = Value();
+ Value quotient_K = arith::DivUIOp::create(
+ rewriter, loc, ivNewInnerLoop, nLoadIndx);
+ indxToLoadFromBuffer = arith::RemUIOp::create(
+ rewriter, loc, rewriter.getIndexType(), quotient_K, c2);
+ }
+ }
+ }
+
+ // compute tiled dot-product
+ SmallVector<Value> accumulators = createTiledDp(
+ rewriter, locNewInnerLoop, ops, lhsClone->getResult(0), matB,
+ ipType, opType, iterArgsNewInnerLoop, blockingFactor, isVnni,
+ packedBuffer, pack, indxToStoreInBuffer, indxToLoadFromBuffer);
+
+ scf::YieldOp::create(rewriterNewInnerLoop, locNewInnerLoop,
+ accumulators);
+ });
+
+ return newLoop;
+}
+
// Implements tiled dot-product operation for a vector.contract operation or a
// sequence of vector.contracts inside the reduction loops.
//
-// For example - for F32 type:
+// For example:
+// Case 1: register blocked vector.contract with prepacked input
// ```
// vector.transfer_read %arg0 {{.}*} : memref<16x32x4xi8>, vector<16x16x4xi8>
// vector.transfer_read %arg1 {{.}*} : memref<16x32x4xi8>, vector<16x16x4xi8>
@@ -293,6 +613,52 @@ static SmallVector<Value> createTileZeros(OpBuilder &rewriter, Location loc,
// amx.tile_muli !amx.tile<16x64xi8> -> !amx.tile<16x16xi32>
// amx.tile_store %arg2{{.}*} : memref<32x32xi32>, !amx.tile<16x16xi32>
// ```
+//
+//
+// Case2: vector.contract with register blocked
+//
+// Output IR with online packing (with s/w pipeline advantage):
+// s/w pipeline: load, pack to VNNI, and store the B sub matrix
+// of the 0th batch-reduce and K iteration.
+// scf.for (0 to 31) {
+// - load 0th and 1st vector<32xbf16>, pack into VNNI, store the
+// first shuffle in 0th and 2nd shuffle in 16th index of the
+// buffer.
+// }
+// scf.for (0 to br-2) { batch-reduce loop
+// scf.for (0 to k-2) { K loop
+// - load A matrix
+// - scf.loop for s/w pipeline: load, pack to VNNI, and store the B sub
+// matrix for the next K loop iteration (c) load VNNI pack B matrix of K
+// iteration from the buffer (d) compute the tiled dot-product
+// }
+// Last iteration of the the K Loop (k-1) {
+// - load A matrix
+// - scf.loop for s/w pipeline: load, pack to VNNI, and store the B sub
+// matrix for the next batch-reduce + K loop iteration (c) load VNNI pack B
+// matrix of K iteration from the buffer (d) compute the tiled dot-product
+// }
+// }
+// Last iteration of the batch-reduce loop (br-1) {
+// scf.for (0 to k-2) { K loop
+// - load A matrix
+// - scf.loop for s/w pipeline: load, pack to VNNI, and store the B sub
+// matrix for the next K loop iteration (c) load VNNI pack B matrix of K
+// iteration from the buffer (d) compute the tiled dot-product
+// }
+// Last iteration of the the K Loop (k-1) {
+// - load A matrix
+// - load VNNI pack B matrix of K iteration from the buffer
+// - compute the tiled dot-product
+// }
+// }
+//
+// scf.for (0 to M)
+// scf.for (0 to N)
+// - Load the ith and i+1th acc
+// - Shuffle them as we packed using vpunpack
+// - Load C matrix and do arith.add with the shuffle
+// - Store back into C matrix
struct VectorContractToAMXDotProduct
: public OpRewritePattern<vector::ContractionOp> {
using OpRewritePattern<vector::ContractionOp>::OpRewritePattern;
@@ -326,9 +692,6 @@ struct VectorContractToAMXDotProduct
return rewriter.notifyMatchFailure(contractOp,
"Only F32 for BF16 or Int32 for Int8 "
"accumulation type is supported.");
- if (!isVnni)
- return rewriter.notifyMatchFailure(
- contractOp, "Only VNNI-packed inputs are supported.");
Operation *accReadOp =
traceToVectorReadLikeParentOperation(contractOp.getAcc());
@@ -360,13 +723,21 @@ struct VectorContractToAMXDotProduct
return rewriter.notifyMatchFailure(
contractOp, "The accumulator read is in different block.");
+ unsigned int dimValue = blockingFactor;
+ if (!isVnni)
+ dimValue = 16 * blockingFactor;
+
// Case 1: For just one VC rewrite. Where all accumulator read/write
// within the same block.
if (accReadOp->getBlock() == contractOp->getBlock() &&
resultWriteOp->getBlock() == contractOp->getBlock()) {
+ bool collapse = false;
+ if (isVnni)
+ collapse = true;
+
LogicalResult validate = validateContractOps(
- rewriter, contractOp, blockingFactor, Value(), Value(), false);
+ rewriter, contractOp, dimValue, Value(), Value(), false);
if (failed(validate))
return rewriter.notifyMatchFailure(
@@ -377,18 +748,20 @@ struct VectorContractToAMXDotProduct
Location loc = contractOp.getLoc();
auto srcIndxLhs = getSrcIndxValue(rewriter, contractOp.getLoc(),
- contractOp.getLhs(), true);
+ contractOp.getLhs(), collapse);
if (failed(srcIndxLhs))
return rewriter.notifyMatchFailure(contractOp,
"The LHS src is not a MemRef type.");
auto [srcBuffLhs, indicesLhs] = *srcIndxLhs;
auto srcIndxRhs = getSrcIndxValue(rewriter, contractOp.getLoc(),
- contractOp.getRhs(), true);
+ contractOp.getRhs(), collapse);
if (failed(srcIndxRhs))
return rewriter.notifyMatchFailure(contractOp,
"The RHS src is not a MemRef type.");
- auto [srcBuffRhs, indicesRhs] = *srcIndxRhs;
+ auto rhsSrc = *srcIndxRhs;
+ auto srcBuffRhs = rhsSrc.first;
+ auto indicesRhs = rhsSrc.second;
auto srcIndxAcc = getSrcIndxValue(rewriter, contractOp.getLoc(),
contractOp.getAcc(), false);
@@ -401,8 +774,109 @@ struct VectorContractToAMXDotProduct
auto tileType = amx::TileType::get({16, (16 * blockingFactor)}, ipType);
auto loadLhs = amx::TileLoadOp::create(rewriter, loc, tileType,
srcBuffLhs, indicesLhs);
- auto loadRhs = amx::TileLoadOp::create(rewriter, loc, tileType,
- srcBuffRhs, indicesRhs);
+
+ // Create the subview and then load.
+ amx::TileLoadOp loadRhs;
+ if (!isVnni) {
+ VectorType vecTy;
+ SmallVector<OpFoldResult> indexVals;
+ llvm::TypeSwitch<Operation *>(contractOp.getRhs().getDefiningOp())
+ .Case<TransferReadOp, LoadOp>([&](auto readOp) {
+ indexVals = SmallVector<OpFoldResult>(readOp.getIndices().begin(),
+ readOp.getIndices().end());
+ vecTy = readOp.getType();
+ });
+ auto one = rewriter.getIndexAttr(1);
+ SmallVector<OpFoldResult> strides(indexVals.size(), one);
+ SmallVector<OpFoldResult> sizes = getAsIndexOpFoldResult(
+ contractOp.getRhs().getDefiningOp()->getContext(),
+ vecTy.getShape());
+ auto subview = memref::SubViewOp::create(rewriter, loc, srcBuffRhs,
+ indexVals, sizes, strides);
+ auto bufferType = MemRefType::get({16, (16 * blockingFactor)}, ipType);
+ auto packedBuffer = memref::AllocaOp::create(rewriter, loc, bufferType);
+
+ // create a loop that does online packing.
+ Value c0 = arith::ConstantIndexOp::create(rewriter, loc, 0);
+ Value step =
+ arith::ConstantIndexOp::create(rewriter, loc, blockingFactor);
+ Value uBound = arith::ConstantIndexOp::create(rewriter, loc,
+ (blockingFactor * 16));
+ Value nextLoadIndx =
+ arith::ConstantIndexOp::create(rewriter, loc, (blockingFactor / 2));
+ Value nextStoreIndx = arith::ConstantIndexOp::create(
+ rewriter, loc, 16 * (blockingFactor / 2));
+
+ scf::ForOp::create(
+ rewriter, loc, c0, uBound, step, ValueRange{},
+ [&](OpBuilder &nestedBuilder, Location loc, Value iv,
+ ValueRange iterArgs) {
+ Value i1_load =
+ arith::AddIOp::create(rewriter, loc, nextLoadIndx, iv);
+
+ indicesRhs[indicesRhs.size() - 2] = iv;
+ ValueRange range1(indicesRhs);
+ auto vec1 = vector::LoadOp::create(
+ rewriter, loc,
+ VectorType::get(16 * (blockingFactor / 2), ipType), subview,
+ range1);
+
+ indicesRhs[indicesRhs.size() - 2] = i1_load;
+ ValueRange range2(indicesRhs);
+ auto vec2 = vector::LoadOp::create(
+ rewriter, loc,
+ VectorType::get(16 * (blockingFactor / 2), ipType), subview,
+ range2);
+
+ vector::ShuffleOp shuffle1;
+ vector::ShuffleOp shuffle2;
+
+ if (blockingFactor == 2) {
+
+ shuffle1 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get({16}, ipType), vec1, vec2,
+ ArrayRef<int64_t>{0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21,
+ 6, 22, 7, 23});
+
+ shuffle2 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get({16}, ipType), vec1, vec2,
+ ArrayRef<int64_t>{8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13,
+ 29, 14, 30, 15, 31});
+ }
+
+ if (blockingFactor == 4) {
+ shuffle1 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get({32}, ipType), vec1, vec2,
+ ArrayRef<int64_t>{0, 16, 32, 48, 1, 17, 33, 49,
+ 2, 18, 34, 50, 3, 19, 35, 51,
+ 4, 20, 36, 52, 5, 21, 37, 53,
+ 6, 22, 38, 54, 7, 23, 39, 55});
+
+ shuffle2 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get({32}, ipType), vec1, vec2,
+ ArrayRef<int64_t>{8, 24, 40, 56, 9, 25, 41, 57,
+ 10, 26, 42, 58, 11, 27, 43, 59,
+ 12, 28, 44, 60, 13, 29, 45, 61,
+ 14, 30, 46, 62, 15, 31, 47, 63});
+ }
+
+ auto rem = arith::RemUIOp::create(
+ rewriter, loc, rewriter.getIndexType(), iv, step);
+
+ vector::StoreOp::create(rewriter, loc, shuffle1, packedBuffer,
+ ValueRange{rem, c0});
+ vector::StoreOp::create(rewriter, loc, shuffle2, packedBuffer,
+ ValueRange{rem, nextStoreIndx});
+
+ scf::YieldOp::create(nestedBuilder, loc);
+ });
+ loadRhs = amx::TileLoadOp::create(rewriter, loc, tileType, packedBuffer,
+ ValueRange{c0, c0});
+ } else {
+
+ loadRhs = amx::TileLoadOp::create(rewriter, loc, tileType, srcBuffRhs,
+ indicesRhs);
+ }
auto tileTypeAcc = amx::TileType::get({16, 16}, opType);
auto loadAcc = amx::TileLoadOp::create(rewriter, loc, tileTypeAcc,
@@ -427,11 +901,17 @@ struct VectorContractToAMXDotProduct
// Case 2: The acc are passed as iter args through the reduction loop.
// We support, reduction loop depth until 2. TODO: Support for n-depth
// reduction loop.
+ // TODOs: Re-factor 2a and 2b.
SmallVector<scf::ForOp> loopLists;
Operation *current = contractOp;
-
while (true) {
Operation *parent = current->getParentOfType<scf::ForOp>();
+
+ if (!parent)
+ return rewriter.notifyMatchFailure(
+ contractOp,
+ "Accumulator read and contract op not within scf.for op");
+
loopLists.push_back(dyn_cast<scf::ForOp>(parent));
if (accReadOp->getBlock() == parent->getBlock()) {
@@ -440,7 +920,6 @@ struct VectorContractToAMXDotProduct
current = parent;
}
-
if (loopLists.size() > 2 || loopLists.size() == 0)
return rewriter.notifyMatchFailure(
contractOp, "Rewrite is supported until reduction loop depth of 2.");
@@ -458,7 +937,6 @@ struct VectorContractToAMXDotProduct
return rewriter.notifyMatchFailure(contractOp,
"The RHS src is not a MemRef type.");
auto [srcBuffRhs, indicesRhs] = *srcIndxRhs;
-
Operation *vectorOpLhs;
llvm::TypeSwitch<Operation *>(contractOp.getLhs().getDefiningOp())
.Case<TransferReadOp, LoadOp>([&](auto readOp) {
@@ -478,7 +956,7 @@ struct VectorContractToAMXDotProduct
if (auto contract = llvm::dyn_cast<mlir::vector::ContractionOp>(op)) {
LogicalResult validate = validateContractOps(
- rewriter, contract, blockingFactor, srcBuffLhs, srcBuffRhs, true);
+ rewriter, contract, dimValue, srcBuffLhs, srcBuffRhs, true);
if (failed(validate))
return rewriter.notifyMatchFailure(
@@ -490,8 +968,22 @@ struct VectorContractToAMXDotProduct
}
}
- scf::ForOp outerLoop;
+ if (!isVnni) {
+ unsigned int pairCount = 0;
+ for (size_t j = 0; j < ops.size(); j++) {
+ for (size_t i = j; i < ops.size(); i++) {
+ if (i != j && validatePairVectorContract(ops[j], ops[i], true, 16))
+ pairCount = pairCount + 2;
+ }
+ }
+
+ if (pairCount != ops.size())
+ return rewriter.notifyMatchFailure(
+ contractOp, "Coudn't find the pair vector contract ");
+ }
+
scf::ForOp innerLoop;
+ scf::ForOp outerLoop;
scf::ForOp newLoop;
// Case 2a: Reduction loop depth is 2.
@@ -502,163 +994,398 @@ struct VectorContractToAMXDotProduct
SmallVector<Value> loopItrArgs = createTileZeros(
rewriter, outerLoop.getLoc(), opType, outerLoop, ops.size());
- newLoop = scf::ForOp::create(
- rewriter, outerLoop.getLoc(), outerLoop.getLowerBound(),
- outerLoop.getUpperBound(), outerLoop.getStep(), loopItrArgs,
- [&](OpBuilder &rewriterOuterLoop, Location locOuterLoop,
- Value ivOuterLoop, ValueRange iterArgsOuterLoop) {
- auto newInnerLoop = scf::ForOp::create(
- rewriter, innerLoop.getLoc(), innerLoop.getLowerBound(),
- innerLoop.getUpperBound(), innerLoop.getStep(),
- iterArgsOuterLoop,
- [&](OpBuilder &rewriterNewInnerLoop, Location locNewInnerLoop,
- Value ivNewInnerLoop, ValueRange iterArgsNewInnerLoop) {
- IRMapping mapping;
- mapping.map(
- vectorOpLhs->getOperand(
- getIndexPosition(contractOp.getLhs(), outerLoop) + 1),
- ivOuterLoop);
- mapping.map(
- vectorOpLhs->getOperand(
- getIndexPosition(contractOp.getLhs(), innerLoop) + 1),
- ivNewInnerLoop);
- auto lhsClone =
- rewriterNewInnerLoop.clone(*vectorOpLhs, mapping);
-
- IRMapping rhsMapping;
- rhsMapping.map(
- vectorOpRhs->getOperand(
- getIndexPosition(contractOp.getRhs(), outerLoop) + 1),
- ivOuterLoop);
- rhsMapping.map(
- vectorOpRhs->getOperand(
- getIndexPosition(contractOp.getRhs(), innerLoop) + 1),
- ivNewInnerLoop);
- auto rhsClone =
- rewriterNewInnerLoop.clone(*vectorOpRhs, rhsMapping);
-
- SmallVector<Value> accumulators = createTiledDp(
- rewriter, locNewInnerLoop, ops, lhsClone->getResult(0),
- rhsClone->getResult(0), ipType, opType,
- iterArgsNewInnerLoop, blockingFactor);
-
- scf::YieldOp::create(rewriterNewInnerLoop, locNewInnerLoop,
- accumulators);
- });
-
- scf::YieldOp::create(rewriterOuterLoop, locOuterLoop,
- newInnerLoop.getResults());
- });
+ if (isVnni) {
+ newLoop = scf::ForOp::create(
+ rewriter, outerLoop.getLoc(), outerLoop.getLowerBound(),
+ outerLoop.getUpperBound(), outerLoop.getStep(), loopItrArgs,
+ [&](OpBuilder &rewriterOuterLoop, Location locOuterLoop,
+ Value ivOuterLoop, ValueRange iterArgsOuterLoop) {
+ auto newInnerLoop = createLoops(
+ rewriter, innerLoop.getLoc(), innerLoop.getLowerBound(),
+ innerLoop.getUpperBound(), innerLoop.getStep(),
+ iterArgsOuterLoop, ipType, opType, blockingFactor, isVnni,
+ vectorOpLhs, vectorOpRhs, contractOp, outerLoop, innerLoop,
+ ops, ivOuterLoop, nullptr, true, nullptr, false, false);
+
+ scf::YieldOp::create(rewriterOuterLoop, locOuterLoop,
+ newInnerLoop.getResults());
+ });
+
+ } else {
+
+ bool isInnerLoopUBLarger = false;
+ bool isInnerLoopUBHasOddQuot = false;
+
+ int64_t ubVal = 16 * blockingFactor;
+ mlir::Value ub = innerLoop.getUpperBound();
+ if (auto constOp = ub.getDefiningOp<mlir::arith::ConstantOp>()) {
+ if (auto intAttr =
+ llvm::dyn_cast<mlir::IntegerAttr>(constOp.getValue())) {
+ ubVal = intAttr.getInt();
+ }
+ }
+
+ isInnerLoopUBLarger = ubVal > 16 * blockingFactor;
+ isInnerLoopUBHasOddQuot =
+ (((ubVal / (16 * blockingFactor)) % 2) == 1) && isInnerLoopUBLarger;
+
+ rewriter.setInsertionPoint(outerLoop);
+
+ auto c0 =
+ arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 0);
+ auto c1 =
+ arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 1);
+ auto spillLoopBound = arith::ConstantIndexOp::create(
+ rewriter, outerLoop.getLoc(), 16 * blockingFactor);
+
+ Value spillOuterLoop = arith::SubIOp::create(
+ rewriter, outerLoop.getLoc(), outerLoop.getUpperBound(), c1);
+ Value spillInnerLoop =
+ arith::SubIOp::create(rewriter, innerLoop.getLoc(),
+ innerLoop.getUpperBound(), spillLoopBound);
+ auto bufferType =
+ MemRefType::get({2, 32, (blockingFactor * 16)}, ipType);
+ auto packedBuffer =
+ memref::AllocaOp::create(rewriter, outerLoop.getLoc(), bufferType);
+
+ // First Shuffling outside the reduction loops
+ IRMapping rhsMapping;
+ rhsMapping.map(
+ vectorOpRhs->getOperand(
+ getIndexPosition(contractOp.getRhs(), outerLoop) + 1),
+ c0);
+ rhsMapping.map(
+ vectorOpRhs->getOperand(
+ getIndexPosition(contractOp.getRhs(), innerLoop) + 1),
+ c0);
+ auto rhsClone = rewriter.clone(*vectorOpRhs, rhsMapping);
+
+ performShuffle(rewriter, outerLoop.getLoc(), rhsClone->getResult(0),
+ ipType, blockingFactor, packedBuffer, c0);
+
+ // First Set of Loops
+ auto newLoopNonSpill = scf::ForOp::create(
+ rewriter, outerLoop.getLoc(), outerLoop.getLowerBound(),
+ spillOuterLoop, outerLoop.getStep(), loopItrArgs,
+ [&](OpBuilder &rewriterOuterLoop, Location locOuterLoop,
+ Value ivOuterLoop, ValueRange iterArgsOuterLoop) {
+ auto newInnerLoop1 = createLoops(
+ rewriter, innerLoop.getLoc(), innerLoop.getLowerBound(),
+ spillInnerLoop, innerLoop.getStep(), iterArgsOuterLoop,
+ ipType, opType, blockingFactor, isVnni, vectorOpLhs,
+ vectorOpRhs, contractOp, outerLoop, innerLoop, ops,
+ ivOuterLoop, packedBuffer, true, spillLoopBound,
+ isInnerLoopUBLarger, isInnerLoopUBHasOddQuot);
+
+ auto newInnerLoop = createLoops(
+ rewriter, innerLoop.getLoc(), spillInnerLoop,
+ innerLoop.getUpperBound(), innerLoop.getStep(),
+ newInnerLoop1.getResults(), ipType, opType, blockingFactor,
+ isVnni, vectorOpLhs, vectorOpRhs, contractOp, outerLoop,
+ innerLoop, ops, ivOuterLoop, packedBuffer, true, c0,
+ isInnerLoopUBLarger, isInnerLoopUBHasOddQuot);
+
+ scf::YieldOp::create(rewriterOuterLoop, locOuterLoop,
+ newInnerLoop.getResults());
+ });
+
+ // Last set of Loops
+ newLoop = scf::ForOp::create(
+ rewriter, outerLoop.getLoc(), spillOuterLoop,
+ outerLoop.getUpperBound(), outerLoop.getStep(),
+ newLoopNonSpill.getResults(),
+ [&](OpBuilder &rewriterOuterLoop, Location locOuterLoop,
+ Value ivOuterLoop, ValueRange iterArgsOuterLoop) {
+ auto newInnerLoop1 = createLoops(
+ rewriter, innerLoop.getLoc(), innerLoop.getLowerBound(),
+ spillInnerLoop, innerLoop.getStep(), iterArgsOuterLoop,
+ ipType, opType, blockingFactor, isVnni, vectorOpLhs,
+ vectorOpRhs, contractOp, outerLoop, innerLoop, ops,
+ ivOuterLoop, packedBuffer, true, spillLoopBound,
+ isInnerLoopUBLarger, isInnerLoopUBHasOddQuot);
+
+ auto newInnerLoop = createLoops(
+ rewriter, innerLoop.getLoc(), spillInnerLoop,
+ innerLoop.getUpperBound(), innerLoop.getStep(),
+ newInnerLoop1.getResults(), ipType, opType, blockingFactor,
+ isVnni, vectorOpLhs, vectorOpRhs, contractOp, outerLoop,
+ innerLoop, ops, ivOuterLoop, packedBuffer, false, c0,
+ isInnerLoopUBLarger, isInnerLoopUBHasOddQuot);
+
+ scf::YieldOp::create(rewriterOuterLoop, locOuterLoop,
+ newInnerLoop.getResults());
+ });
+ }
}
// Case 2b: Reduction loop depth is 1.
if (loopLists.size() == 1) {
- outerLoop = loopLists[0];
+ innerLoop = loopLists[0];
SmallVector<Value> loopItrArgs = createTileZeros(
- rewriter, outerLoop.getLoc(), opType, outerLoop, ops.size());
- newLoop = scf::ForOp::create(
- rewriter, outerLoop.getLoc(), outerLoop.getLowerBound(),
- outerLoop.getUpperBound(), outerLoop.getStep(), loopItrArgs,
- [&](OpBuilder &rewriterOuterLoop, Location locOuterLoop,
- Value ivOuterLoop, ValueRange iterArgsOuterLoop) {
- IRMapping mapping;
- mapping.map(
- vectorOpLhs->getOperand(
- getIndexPosition(contractOp.getLhs(), outerLoop) + 1),
- ivOuterLoop);
-
- auto lhsClone = rewriterOuterLoop.clone(*vectorOpLhs, mapping);
-
- IRMapping rhsMapping;
- rhsMapping.map(
- vectorOpRhs->getOperand(
- getIndexPosition(contractOp.getRhs(), outerLoop) + 1),
- ivOuterLoop);
-
- auto rhsClone = rewriterOuterLoop.clone(*vectorOpRhs, rhsMapping);
-
- SmallVector<Value> accumulators = createTiledDp(
- rewriter, locOuterLoop, ops, lhsClone->getResult(0),
- rhsClone->getResult(0), ipType, opType, iterArgsOuterLoop,
- blockingFactor);
-
- scf::YieldOp::create(rewriterOuterLoop, locOuterLoop, accumulators);
- });
+ rewriter, innerLoop.getLoc(), opType, innerLoop, ops.size());
+
+ if (isVnni) {
+
+ newLoop = createLoops(
+ rewriter, innerLoop.getLoc(), innerLoop.getLowerBound(),
+ innerLoop.getUpperBound(), innerLoop.getStep(), loopItrArgs, ipType,
+ opType, blockingFactor, isVnni, vectorOpLhs, vectorOpRhs,
+ contractOp, nullptr, innerLoop, ops, nullptr, nullptr, true,
+ nullptr, false, false);
+
+ } else {
+ bool isInnerLoopUBLarger = false;
+ bool isInnerLoopUBHasOddQuot = false;
+
+ int64_t ubVal = 16 * blockingFactor;
+ mlir::Value ub = innerLoop.getUpperBound();
+ if (auto constOp = ub.getDefiningOp<mlir::arith::ConstantOp>()) {
+ if (auto intAttr =
+ llvm::dyn_cast<mlir::IntegerAttr>(constOp.getValue())) {
+ ubVal = intAttr.getInt();
+ }
+ }
+
+ isInnerLoopUBLarger = ubVal > 16 * blockingFactor;
+ isInnerLoopUBHasOddQuot =
+ (((ubVal / (16 * blockingFactor)) % 2) == 1) && isInnerLoopUBLarger;
+
+ rewriter.setInsertionPoint(innerLoop);
+ auto c0 =
+ arith::ConstantIndexOp::create(rewriter, innerLoop.getLoc(), 0);
+ auto spillLoopBound = arith::ConstantIndexOp::create(
+ rewriter, innerLoop.getLoc(), 16 * blockingFactor);
+
+ Value spillInnerLoop =
+ arith::SubIOp::create(rewriter, innerLoop.getLoc(),
+ innerLoop.getUpperBound(), spillLoopBound);
+
+ auto bufferType =
+ MemRefType::get({2, 32, (blockingFactor * 16)}, ipType);
+ auto packedBuffer =
+ memref::AllocaOp::create(rewriter, innerLoop.getLoc(), bufferType);
+
+ // First Shuffling outside the reduction loops
+ IRMapping rhsMapping;
+ rhsMapping.map(
+ vectorOpRhs->getOperand(
+ getIndexPosition(contractOp.getRhs(), innerLoop) + 1),
+ c0);
+ auto rhsClone = rewriter.clone(*vectorOpRhs, rhsMapping);
+
+ performShuffle(rewriter, innerLoop.getLoc(), rhsClone->getResult(0),
+ ipType, blockingFactor, packedBuffer, c0);
+
+ auto newLoopNonSpill = createLoops(
+ rewriter, innerLoop.getLoc(), innerLoop.getLowerBound(),
+ spillInnerLoop, innerLoop.getStep(), loopItrArgs, ipType, opType,
+ blockingFactor, isVnni, vectorOpLhs, vectorOpRhs, contractOp,
+ nullptr, innerLoop, ops, nullptr, packedBuffer, true,
+ spillLoopBound, isInnerLoopUBLarger, isInnerLoopUBHasOddQuot);
+
+ newLoop = createLoops(rewriter, innerLoop.getLoc(), spillInnerLoop,
+ innerLoop.getUpperBound(), innerLoop.getStep(),
+ newLoopNonSpill.getResults(), ipType, opType,
+ blockingFactor, isVnni, vectorOpLhs, vectorOpRhs,
+ contractOp, nullptr, innerLoop, ops, nullptr,
+ packedBuffer, false, c0, isInnerLoopUBLarger,
+ isInnerLoopUBHasOddQuot);
+ }
+
+ // This helps the final store back to the acc uses the same code for
+ // the both reduction loop depth 1 or 2.
+ outerLoop = innerLoop;
}
- // post processing after the loop creation.
// Copy the amx tile accumulation results to a MemRef buffer, add the
// initial accumulation value, and store back to the C-Matrix
- auto bufferType = MemRefType::get({16, 16}, opType);
- auto bBuffer =
- memref::AllocaOp::create(rewriter, outerLoop.getLoc(), bufferType);
-
- SmallVector<Value> dps = newLoop.getResults();
- for (size_t i = 0; i < ops.size(); i++) {
- vector::ContractionOp contOp = ops[i];
- Operation *resultWriteOp =
- traceToVectorWriteLikeUserOperation(contOp.getResult());
- rewriter.setInsertionPoint(resultWriteOp);
- Value indexOp_0 =
- arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 0);
+ if (!isVnni) {
+ Location loc = outerLoop.getLoc();
+ Operation *accReadOp =
+ traceToVectorReadLikeParentOperation(contractOp.getAcc());
- amx::TileStoreOp::create(rewriter, outerLoop.getLoc(), bBuffer,
- ValueRange{indexOp_0, indexOp_0}, dps[i]);
-
- auto c0 = arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 0);
- auto one =
- arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 1);
- auto mBound =
- arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 16);
-
- scf::ForOp::create(
- rewriter, outerLoop.getLoc(), c0, mBound, one, ValueRange{},
- [&](OpBuilder &builder, Location loc, Value iv, ValueRange iterArgs) {
- auto resultAcc = vector::LoadOp::create(
- rewriter, loc, VectorType::get(16, opType), bBuffer,
- ValueRange{iv, c0});
+ Value srcBuffAcc;
+ SmallVector<Value> indicesAcc;
- Operation *accReadOp =
- traceToVectorReadLikeParentOperation(ops[i].getAcc());
+ llvm::TypeSwitch<Operation *>(accReadOp).Case<TransferReadOp, LoadOp>(
+ [&](auto readOp) {
+ srcBuffAcc = readOp.getOperand(0);
- Value srcBuffAcc;
- SmallVector<Value> indicesAcc;
+ auto indices = readOp.getIndices();
+ indicesAcc.reserve(indices.size());
- llvm::TypeSwitch<Operation *>(accReadOp)
- .Case<TransferReadOp, LoadOp>([&](auto readOp) {
- srcBuffAcc = readOp.getOperand(0);
-
- auto indices = readOp.getIndices();
- indicesAcc.reserve(indices.size());
-
- llvm::transform(
- indices, std::back_inserter(indicesAcc),
- [&](OpFoldResult ofr) {
- return mlir::getValueOrCreateConstantIndexOp(rewriter,
- loc, ofr);
- });
- });
+ llvm::transform(indices, std::back_inserter(indicesAcc),
+ [&](OpFoldResult ofr) {
+ return mlir::getValueOrCreateConstantIndexOp(
+ rewriter, loc, ofr);
+ });
+ });
- Value sum = arith::AddIOp::create(builder, loc, iv, indicesAcc[0]);
- indicesAcc[indicesAcc.size() - 2] = sum;
+ auto outputShapes =
+ mlir::cast<mlir::MemRefType>(srcBuffAcc.getType()).getShape();
+ unsigned int M = outputShapes[outputShapes.size() - 2];
+ unsigned int N = outputShapes[outputShapes.size() - 1];
+
+ SmallVector<Value> dps = newLoop.getResults();
+ auto bufferType = MemRefType::get({M, N}, opType);
+ auto resultBuffer = memref::AllocaOp::create(rewriter, loc, bufferType);
+
+ // Store the amx tiled-dot product output into an MxN memref.
+ for (unsigned int i = 0, k = 0; i < M; i = i + 16) {
+ for (unsigned int j = 0; j < N; j = j + 16) {
+ Value indexOp_i = arith::ConstantIndexOp::create(rewriter, loc, i);
+ Value indexOp_j = arith::ConstantIndexOp::create(rewriter, loc, j);
+ amx::TileStoreOp::create(rewriter, loc, resultBuffer,
+ ValueRange{indexOp_i, indexOp_j}, dps[k]);
+ k++;
+ }
+ }
+ auto c0 = arith::ConstantIndexOp::create(rewriter, loc, 0);
+ auto c16 = arith::ConstantIndexOp::create(rewriter, loc, 16);
+ auto one = arith::ConstantIndexOp::create(rewriter, loc, 1);
+ auto mBound = arith::ConstantIndexOp::create(rewriter, loc, N);
- auto acc = vector::LoadOp::create(rewriter, loc,
+ // Create a loop that iterates over the MxN memerf, retrives two rows +
+ // shuffle them, add up the C element values and stores them back.
+ scf::ForOp::create(
+ rewriter, loc, c0, mBound, one, ValueRange{},
+ [&](OpBuilder &nestedBuilder, Location loc, Value iv,
+ ValueRange iterArgs) {
+ auto row = vector::LoadOp::create(rewriter, loc,
VectorType::get(16, opType),
- srcBuffAcc, indicesAcc);
- Value addition;
- if (ipType.isBF16())
- addition = arith::AddFOp::create(rewriter, loc, resultAcc, acc);
-
- if (ipType.isSignlessInteger(8))
- addition = arith::AddIOp::create(rewriter, loc, resultAcc, acc);
-
- vector::StoreOp::create(builder, loc, addition, srcBuffAcc,
+ resultBuffer, ValueRange{iv, c0});
+
+ auto row2 = vector::LoadOp::create(
+ rewriter, loc, VectorType::get(16, opType), resultBuffer,
+ ValueRange{iv, c16});
+
+ auto shuffle1 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get(16, opType), row, row2,
+ ArrayRef<int64_t>{0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20,
+ 21, 22, 23});
+
+ auto shuffle2 = vector::ShuffleOp::create(
+ rewriter, loc, VectorType::get(16, opType), row, row2,
+ ArrayRef<int64_t>{8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15,
+ 28, 29, 30, 31});
+
+ indicesAcc[indicesAcc.size() - 2] = iv;
+ indicesAcc[indicesAcc.size() - 1] = c0;
+
+ Value valueCRow1 = vector::LoadOp::create(
+ rewriter, loc, VectorType::get(16, opType), srcBuffAcc,
+ indicesAcc);
+ indicesAcc[indicesAcc.size() - 1] = c16;
+
+ Value valueCRow2 = vector::LoadOp::create(
+ rewriter, loc, VectorType::get(16, opType), srcBuffAcc,
+ indicesAcc);
+
+ Value addOp;
+ Value addOp2;
+
+ if (ipType.isBF16()) {
+ addOp =
+ arith::AddFOp::create(rewriter, loc, shuffle1, valueCRow1);
+
+ addOp2 =
+ arith::AddFOp::create(rewriter, loc, shuffle2, valueCRow2);
+ }
+
+ if (ipType.isSignlessInteger(8)) {
+ addOp =
+ arith::AddIOp::create(rewriter, loc, shuffle1, valueCRow1);
+
+ addOp2 =
+ arith::AddIOp::create(rewriter, loc, shuffle2, valueCRow2);
+ }
+ indicesAcc[indicesAcc.size() - 1] = c0;
+ vector::StoreOp::create(rewriter, loc, addOp, srcBuffAcc,
+ indicesAcc);
+ indicesAcc[indicesAcc.size() - 1] = c16;
+ vector::StoreOp::create(rewriter, loc, addOp2, srcBuffAcc,
indicesAcc);
- scf::YieldOp::create(builder, outerLoop.getLoc());
+ scf::YieldOp::create(nestedBuilder, loc);
});
+ }
+
+ auto bufferType = MemRefType::get({16, 16}, opType);
+ auto resultBuffer =
+ memref::AllocaOp::create(rewriter, outerLoop.getLoc(), bufferType);
+ SmallVector<Value> dps = newLoop.getResults();
+
+ for (size_t i = 0; i < ops.size(); i++) {
+ vector::ContractionOp contOp = ops[i];
+ Operation *resultWriteOp =
+ traceToVectorWriteLikeUserOperation(contOp.getResult());
+ if (isVnni) {
+ rewriter.setInsertionPoint(resultWriteOp);
+
+ Value indexOp_0 =
+ arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 0);
+
+ amx::TileStoreOp::create(rewriter, outerLoop.getLoc(), resultBuffer,
+ ValueRange{indexOp_0, indexOp_0}, dps[i]);
+
+ auto c0 =
+ arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 0);
+ auto one =
+ arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 1);
+ auto mBound =
+ arith::ConstantIndexOp::create(rewriter, outerLoop.getLoc(), 16);
+
+ scf::ForOp::create(
+ rewriter, outerLoop.getLoc(), c0, mBound, one, ValueRange{},
+ [&](OpBuilder &builder, Location loc, Value iv,
+ ValueRange iterArgs) {
+ auto resultAcc = vector::LoadOp::create(
+ rewriter, loc, VectorType::get(16, opType), resultBuffer,
+ ValueRange{iv, c0});
+
+ Operation *accReadOp =
+ traceToVectorReadLikeParentOperation(ops[i].getAcc());
+
+ Value srcBuffAcc;
+ SmallVector<Value> indicesAcc;
+
+ llvm::TypeSwitch<Operation *>(accReadOp)
+ .Case<TransferReadOp, LoadOp>([&](auto readOp) {
+ srcBuffAcc = readOp.getOperand(0);
+
+ auto indices = readOp.getIndices();
+ indicesAcc.reserve(indices.size());
+
+ llvm::transform(
+ indices, std::back_inserter(indicesAcc),
+ [&](OpFoldResult ofr) {
+ return mlir::getValueOrCreateConstantIndexOp(
+ rewriter, loc, ofr);
+ });
+ });
+
+ Value sum =
+ arith::AddIOp::create(builder, loc, iv, indicesAcc[0]);
+ indicesAcc[indicesAcc.size() - 2] = sum;
+
+ auto acc = vector::LoadOp::create(rewriter, loc,
+ VectorType::get(16, opType),
+ srcBuffAcc, indicesAcc);
+ Value addition;
+ if (ipType.isBF16())
+ addition = arith::AddFOp::create(rewriter, loc, resultAcc, acc);
+
+ if (ipType.isSignlessInteger(8))
+ addition = arith::AddIOp::create(rewriter, loc, resultAcc, acc);
+
+ vector::StoreOp::create(builder, loc, addition, srcBuffAcc,
+ indicesAcc);
+
+ scf::YieldOp::create(builder, outerLoop.getLoc());
+ });
+ }
rewriter.eraseOp(resultWriteOp);
}
diff --git a/mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir b/mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
index cde15b680a037..1a6deed31eceb 100644
--- a/mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
+++ b/mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
@@ -216,6 +216,122 @@ module attributes {transform.with_named_sequence} {
// -----
+!vecA = vector<16x64xi8>
+!vecB = vector<64x16xi8>
+!vecC = vector<16x16xi32>
+!memrefA = memref<32x64xi8>
+!memrefB = memref<64x32xi8>
+!memrefC = memref<32x32xi32>
+#map = affine_map<(d1, d2, d3) -> (d1, d3)>
+#map1 = affine_map<(d1, d2, d3) -> (d3, d2)>
+#map2 = affine_map<(d1, d2, d3) -> (d1, d2)>
+func.func @online_packing_int8(
+ %arg0: !memrefA, %arg1: !memrefB, %arg2: !memrefC) -> !memrefC
+{
+ %c0 = arith.constant 0 : index
+ %0 = ub.poison : i8
+ %32 = ub.poison : i32
+
+ %1 = vector.transfer_read %arg0[%c0, %c0], %0 {in_bounds = [true, true]} :
+ !memrefA, !vecA
+ %2 = vector.transfer_read %arg1[%c0, %c0], %0 {in_bounds = [true, true]} :
+ !memrefB, !vecB
+
+ %3 = vector.transfer_read %arg2[%c0, %c0], %32 {in_bounds = [true, true]} : !memrefC, !vecC
+
+ %4 = vector.contract {
+ indexing_maps = [#map, #map1, #map2],
+ iterator_types = ["parallel", "parallel", "reduction"],
+ kind = #vector.kind<add>}
+ %1, %2, %3 : !vecA, !vecB into !vecC
+
+ vector.transfer_write %4, %arg2[%c0, %c0] {in_bounds = [true, true]} : !vecC, !memrefC
+
+ return %arg2 : !memrefC
+}
+
+// CHECK-LABEL: @online_packing_int8
+// CHECK: x86.amx.tile_load {{.*}} !x86.amx.tile<16x64xi8>
+// CHECK: scf.for
+// CHECK: vector.shuffle{{.*}}[0, 16, 32, 48, 1, 17, 33, 49, 2, 18, 34, 50, 3, 19, 35, 51, 4, 20, 36, 52, 5, 21, 37, 53, 6, 22, 38, 54, 7, 23, 39, 55] : vector<32xi8>, vector<32xi8>
+// CHECK-NEXT: vector.shuffle{{.*}}[8, 24, 40, 56, 9, 25, 41, 57, 10, 26, 42, 58, 11, 27, 43, 59, 12, 28, 44, 60, 13, 29, 45, 61, 14, 30, 46, 62, 15, 31, 47, 63] : vector<32xi8>, vector<32xi8>
+// CHECK: x86.amx.tile_load {{.*}} !x86.amx.tile<16x64xi8>
+// CHECK: x86.amx.tile_load {{.*}} !x86.amx.tile<16x16xi32>
+// CHECK: x86.amx.tile_muli
+// CHECK: x86.amx.tile_store {{.*}} !x86.amx.tile<16x16xi32>
+// CHECK-NOT: vector.contract
+
+
+
+module attributes {transform.with_named_sequence} {
+ transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
+ %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
+ transform.apply_patterns to %func {
+ transform.apply_patterns.x86.vector_contract_to_amx_dot_product
+ } : !transform.any_op
+ transform.yield
+ }
+}
+
+// -----
+
+!vecA = vector<1x16x32xbf16>
+!vecB = vector<1x32x16xbf16>
+!vecC = vector<16x16xf32>
+!memrefA = memref<1x32x32xbf16>
+!memrefB = memref<1x32x32xbf16>
+!memrefC = memref<32x32xf32>
+#map = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
+#map1 = affine_map<(d0, d1, d2, d3) -> (d0, d3, d2)>
+#map2 = affine_map<(d0, d1, d2, d3) -> (d1, d2)>
+func.func @online_packing_bf16(
+ %arg0: !memrefA, %arg1: !memrefB, %arg2: !memrefC) -> !memrefC
+{
+ %c0 = arith.constant 0 : index
+ %0 = ub.poison : bf16
+ %32 = ub.poison : f32
+
+ %1 = vector.transfer_read %arg0[%c0, %c0, %c0], %0 {in_bounds = [true, true, true]} :
+ !memrefA, !vecA
+ %2 = vector.transfer_read %arg1[%c0, %c0, %c0], %0 {in_bounds = [true, true, true]} :
+ !memrefB, !vecB
+
+ %3 = vector.transfer_read %arg2[%c0, %c0], %32 {in_bounds = [true, true]} : !memrefC, !vecC
+
+ %4 = vector.contract {
+ indexing_maps = [#map, #map1, #map2],
+ iterator_types = ["reduction", "parallel", "parallel", "reduction"],
+ kind = #vector.kind<add>}
+ %1, %2, %3 : !vecA, !vecB into !vecC
+
+ vector.transfer_write %4, %arg2[%c0, %c0] {in_bounds = [true, true]} : !vecC, !memrefC
+
+ return %arg2 : !memrefC
+}
+
+// CHECK-LABEL: @online_packing_bf16
+// CHECK: x86.amx.tile_load {{.*}} !x86.amx.tile<16x32xbf16>
+// CHECK: scf.for
+// CHECK: vector.shuffle{{.*}}[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] : vector<16xbf16>, vector<16xbf16>
+// CHECK-NEXT: vector.shuffle{{.*}}[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] : vector<16xbf16>, vector<16xbf16>
+// CHECK: x86.amx.tile_load {{.*}} !x86.amx.tile<16x32xbf16>
+// CHECK: x86.amx.tile_load {{.*}} !x86.amx.tile<16x16xf32>
+// CHECK: x86.amx.tile_mulf
+// CHECK: x86.amx.tile_store {{.*}} !x86.amx.tile<16x16xf32>
+// CHECK-NOT: vector.contract
+
+module attributes {transform.with_named_sequence} {
+ transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
+ %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
+ transform.apply_patterns to %func {
+ transform.apply_patterns.x86.vector_contract_to_amx_dot_product
+ } : !transform.any_op
+ transform.yield
+ }
+}
+
+// -----
+
!vecAB = vector<1x16x16x2xbf16>
!vecC = vector<16x16xf32>
!memrefA = memref<1x32x16x2xbf16, strided<[8192, 128, 2, 1], offset: ?>>
@@ -483,6 +599,199 @@ module attributes {transform.with_named_sequence} {
// -----
+!vecA = vector<1x16x32xbf16>
+!vecB = vector<1x32x16xbf16>
+!vecC = vector<16x16xf32>
+!memrefA = memref<1x32x32xbf16, strided<[6144, 96, 1], offset: ?>>
+!memrefB = memref<1x32x32xbf16, strided<[12288, 128, 1], offset: ?>>
+!memrefC = memref<32x32xf32, strided<[128, 1], offset: ?>>
+
+#map = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
+#map1 = affine_map<(d0, d1, d2, d3) -> (d0, d3, d2)>
+#map2 = affine_map<(d0, d1, d2, d3) -> (d1, d2)>
+
+func.func @online_packing_bf16_loop(%arg0: memref<16x64x96xbf16>, %arg1: memref<16x96x128xbf16>, %arg2: memref<64x128xf32>) -> memref<64x128xf32> {
+ %0 = ub.poison : f32
+ %1 = ub.poison : bf16
+ %c0 = arith.constant 0 : index
+ %c64 = arith.constant 64 : index
+ %c128 = arith.constant 128 : index
+ %c16 = arith.constant 16 : index
+ %c96 = arith.constant 96 : index
+ %c32 = arith.constant 32 : index
+ %c1 = arith.constant 1 : index
+ scf.for %arg3 = %c0 to %c64 step %c32 {
+ scf.for %arg4 = %c0 to %c128 step %c32 {
+
+ %subview = memref.subview %arg2[%arg3, %arg4] [32, 32] [1, 1] :
+ memref<64x128xf32> to !memrefC
+ %2 = vector.transfer_read %subview[%c0, %c0], %0 {in_bounds = [true, true]} :
+ !memrefC, !vecC
+ %3 = vector.transfer_read %subview[%c0, %c16], %0 {in_bounds = [true, true]} :
+ !memrefC, !vecC
+ %4 = vector.transfer_read %subview[%c16, %c0], %0 {in_bounds = [true, true]} :
+ !memrefC, !vecC
+ %5 = vector.transfer_read %subview[%c16, %c16], %0 {in_bounds = [true, true]} :
+ !memrefC, !vecC
+
+ %6:4 = scf.for %arg5 = %c0 to %c16 step %c1 iter_args(%arg6 = %2, %arg7 = %3, %arg8 = %4, %arg9 = %5) -> (!vecC, !vecC, !vecC, !vecC) {
+ %7:4 = scf.for %arg10 = %c0 to %c96 step %c32 iter_args(%arg11 = %arg6, %arg12 = %arg7, %arg13 = %arg8, %arg14 = %arg9) -> (!vecC, !vecC, !vecC, !vecC) {
+
+ %subview_0 = memref.subview %arg0[%arg5, %arg3, %arg10] [1, 32, 32] [1, 1, 1] :
+ memref<16x64x96xbf16> to !memrefA
+ %subview_1 = memref.subview %arg1[%arg5, %arg10, %arg4] [1, 32, 32] [1, 1, 1] :
+ memref<16x96x128xbf16> to !memrefB
+ %8 = vector.transfer_read %subview_0[%c0, %c0, %c0], %1 {in_bounds = [true, true, true]} :
+ !memrefA, !vecA
+ %9 = vector.transfer_read %subview_0[%c0, %c16, %c0], %1 {in_bounds = [true, true, true]} :
+ !memrefA, !vecA
+ %10 = vector.transfer_read %subview_1[%c0, %c0, %c0], %1 {in_bounds = [true, true, true]} :
+ !memrefB, !vecB
+ %11 = vector.transfer_read %subview_1[%c0, %c0, %c16], %1 {in_bounds = [true, true, true]} :
+ !memrefB, !vecB
+
+ %12 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["reduction", "parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %8, %10, %arg11 {unroll_shape = array<i64: 1, 16, 16, 32>} : !vecA, !vecB into !vecC
+ %13 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["reduction", "parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %8, %11, %arg12 {unroll_shape = array<i64: 1, 16, 16, 32>} : !vecA, !vecB into !vecC
+ %14 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["reduction", "parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %9, %10, %arg13 {unroll_shape = array<i64: 1, 16, 16, 32>} : !vecA, !vecB into !vecC
+ %15 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["reduction", "parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %9, %11, %arg14 {unroll_shape = array<i64: 1, 16, 16, 32>} : !vecA, !vecB into !vecC
+
+ scf.yield %12, %13, %14, %15 : !vecC, !vecC, !vecC, !vecC
+ }
+ scf.yield %7#0, %7#1, %7#2, %7#3 : !vecC, !vecC, !vecC, !vecC
+ }
+ vector.transfer_write %6#3, %subview[%c16, %c16] {in_bounds = [true, true]} :
+ !vecC, !memrefC
+ vector.transfer_write %6#2, %subview[%c16, %c0] {in_bounds = [true, true]} :
+ !vecC, !memrefC
+ vector.transfer_write %6#1, %subview[%c0, %c16] {in_bounds = [true, true]} :
+ !vecC, !memrefC
+ vector.transfer_write %6#0, %subview[%c0, %c0] {in_bounds = [true, true]} :
+ !vecC, !memrefC
+ }
+ }
+ %alloc = memref.alloc() : memref<64x128xf32>
+ memref.copy %arg2, %alloc : memref<64x128xf32> to memref<64x128xf32>
+ return %alloc : memref<64x128xf32>
+}
+
+// CHECK-LABEL: @online_packing_bf16_loop
+// CHECK-COUNT-4: x86.amx.tile_zero : !x86.amx.tile<16x16xf32>
+// CHECK-COUNT-4: scf.for {{.*}} -> (!x86.amx.tile<16x16xf32>, !x86.amx.tile<16x16xf32>, !x86.amx.tile<16x16xf32>, !x86.amx.tile<16x16xf32>) {
+// CHECK: vector.shuffle{{.*}}[0, 32, 1, 33, 2, 34, 3, 35, 8, 40, 9, 41, 10, 42, 11, 43, 16, 48, 17, 49, 18, 50, 19, 51, 24, 56, 25, 57, 26, 58, 27, 59] : vector<32xbf16>, vector<32xbf16>
+// CHECK-NEXT: vector.shuffle{{.*}}[4, 36, 5, 37, 6, 38, 7, 39, 12, 44, 13, 45, 14, 46, 15, 47, 20, 52, 21, 53, 22, 54, 23, 55, 28, 60, 29, 61, 30, 62, 31, 63] : vector<32xbf16>, vector<32xbf16>
+// CHECK: x86.amx.tile_load
+// CHECK: x86.amx.tile_mulf
+// CHECK: scf.yield {{.*}} : !x86.amx.tile<16x16xf32>, !x86.amx.tile<16x16xf32>, !x86.amx.tile<16x16xf32>, !x86.amx.tile<16x16xf32>
+// CHECK: vector.shuffle{{.*}}[0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23] : vector<16xf32>, vector<16xf32>
+// CHECK-NEXT: vector.shuffle{{.*}}[8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31] : vector<16xf32>, vector<16xf32>
+// CHECK-NOT: scf.for {{.*}} vector<16x16xf32>, vector<16x16xf32>, vector<16x16xf32>, vector<16x16xf32>
+// CHECK-NOT: vector.contract
+
+
+
+module attributes {transform.with_named_sequence} {
+ transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
+ %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
+ transform.apply_patterns to %func {
+ transform.apply_patterns.x86.vector_contract_to_amx_dot_product
+ } : !transform.any_op
+ transform.yield
+ }
+}
+
+// -----
+
+!vecA = vector<16x64xi8>
+!vecB = vector<64x16xi8>
+!vecC = vector<16x16xi32>
+!memrefA = memref<32x64xi8, strided<[256, 1], offset: ?>>
+!memrefB = memref<64x32xi8, strided<[128, 1], offset: ?>>
+!memrefC = memref<32x32xi32, strided<[128, 1], offset: ?>>
+
+#map = affine_map<(d0, d1, d2) -> (d0, d2)>
+#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
+#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
+func.func @online_packing_int8_matmul_loop(%arg0: memref<64x256xi8>, %arg1: memref<256x128xi8>, %arg2: memref<64x128xi32>) -> memref<64x128xi32> {
+ %c16 = arith.constant 16 : index
+ %0 = ub.poison : i32
+ %1 = ub.poison : i8
+ %c0 = arith.constant 0 : index
+ %c64 = arith.constant 64 : index
+ %c128 = arith.constant 128 : index
+ %c256 = arith.constant 256 : index
+ %c32 = arith.constant 32 : index
+ scf.for %arg3 = %c0 to %c64 step %c32 {
+ scf.for %arg4 = %c0 to %c128 step %c32 {
+ %subview = memref.subview %arg2[%arg3, %arg4] [32, 32] [1, 1] : memref<64x128xi32> to !memrefC
+ %2 = vector.transfer_read %subview[%c0, %c0], %0 {in_bounds = [true, true]} : !memrefC, !vecC
+ %3 = vector.transfer_read %subview[%c0, %c16], %0 {in_bounds = [true, true]} : !memrefC, !vecC
+ %4 = vector.transfer_read %subview[%c16, %c0], %0 {in_bounds = [true, true]} : !memrefC, !vecC
+ %5 = vector.transfer_read %subview[%c16, %c16], %0 {in_bounds = [true, true]} : !memrefC, !vecC
+ %6:4 = scf.for %arg5 = %c0 to %c256 step %c64 iter_args(%arg6 = %2, %arg7 = %3, %arg8 = %4, %arg9 = %5) -> (!vecC, !vecC, !vecC, !vecC) {
+ %subview_0 = memref.subview %arg0[%arg3, %arg5] [32, 64] [1, 1] : memref<64x256xi8> to !memrefA
+ %subview_1 = memref.subview %arg1[%arg5, %arg4] [64, 32] [1, 1] : memref<256x128xi8> to !memrefB
+ %7 = vector.transfer_read %subview_0[%c0, %c0], %1 {in_bounds = [true, true]} : !memrefA, !vecA
+ %8 = vector.transfer_read %subview_0[%c16, %c0], %1 {in_bounds = [true, true]} : !memrefA, !vecA
+ %9 = vector.transfer_read %subview_1[%c0, %c0], %1 {in_bounds = [true, true]} : !memrefB, !vecB
+ %10 = vector.transfer_read %subview_1[%c0, %c16], %1 {in_bounds = [true, true]} : !memrefB, !vecB
+ %11 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %7, %9, %arg6 {unroll_shape = array<i64: 16, 16, 64>} : !vecA, !vecB into !vecC
+ %12 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %7, %10, %arg7 {unroll_shape = array<i64: 16, 16, 64>} : !vecA, !vecB into !vecC
+ %13 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %8, %9, %arg8 {unroll_shape = array<i64: 16, 16, 64>} : !vecA, !vecB into !vecC
+ %14 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %8, %10, %arg9 {unroll_shape = array<i64: 16, 16, 64>} : !vecA, !vecB into !vecC
+ scf.yield %11, %12, %13, %14 : !vecC, !vecC, !vecC, !vecC
+ }
+ vector.transfer_write %6#3, %subview[%c16, %c16] {in_bounds = [true, true]} : !vecC, !memrefC
+ vector.transfer_write %6#2, %subview[%c16, %c0] {in_bounds = [true, true]} : !vecC, !memrefC
+ vector.transfer_write %6#1, %subview[%c0, %c16] {in_bounds = [true, true]} : !vecC, !memrefC
+ vector.transfer_write %6#0, %subview[%c0, %c0] {in_bounds = [true, true]} : !vecC, !memrefC
+ }
+ }
+ %alloc = memref.alloc() : memref<64x128xi32>
+ memref.copy %arg2, %alloc : memref<64x128xi32> to memref<64x128xi32>
+ return %alloc : memref<64x128xi32>
+}
+
+// CHECK-LABEL: @online_packing_int8_matmul_loop
+// CHECK-COUNT-4: x86.amx.tile_zero : !x86.amx.tile<16x16xi32>
+// CHECK: scf.for {{.*}} -> (!x86.amx.tile<16x16xi32>, !x86.amx.tile<16x16xi32>, !x86.amx.tile<16x16xi32>, !x86.amx.tile<16x16xi32>) {
+// CHECK: vector.shuffle{{.*}}[0, 32, 64, 96, 1, 33, 65, 97, 2, 34, 66, 98, 3, 35, 67, 99, 8, 40, 72, 104, 9, 41, 73, 105, 10, 42, 74, 106, 11, 43, 75, 107, 16, 48, 80, 112, 17, 49, 81, 113, 18, 50, 82, 114, 19, 51, 83, 115, 24, 56, 88, 120, 25, 57, 89, 121, 26, 58, 90, 122, 27, 59, 91, 123] : vector<64xi8>, vector<64xi8>
+// CHECK-NEXT: vector.shuffle{{.*}}[4, 36, 68, 100, 5, 37, 69, 101, 6, 38, 70, 102, 7, 39, 71, 103, 12, 44, 76, 108, 13, 45, 77, 109, 14, 46, 78, 110, 15, 47, 79, 111, 20, 52, 84, 116, 21, 53, 85, 117, 22, 54, 86, 118, 23, 55, 87, 119, 28, 60, 92, 124, 29, 61, 93, 125, 30, 62, 94, 126, 31, 63, 95, 127] : vector<64xi8>, vector<64xi8>
+// CHECK: x86.amx.tile_load
+// CHECK: x86.amx.tile_muli
+// CHECK: scf.yield {{.*}} !x86.amx.tile<16x16xi32>, !x86.amx.tile<16x16xi32>, !x86.amx.tile<16x16xi32>, !x86.amx.tile<16x16xi32>
+// CHECK: vector.shuffle{{.*}}[0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23] : vector<16xi32>, vector<16xi32>
+// CHECK-NEXT: vector.shuffle{{.*}}[8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31] : vector<16xi32>, vector<16xi32>
+// CHECK-NOT: scf.for {{.*}} vector<16x16xi32>, vector<16x16xi32>, vector<16x16xi32>, vector<16x16xi32>
+// CHECK-NOT: vector.contract
+
+module attributes {transform.with_named_sequence} {
+ transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
+ %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
+ transform.apply_patterns to %func {
+ transform.apply_patterns.x86.vector_contract_to_amx_dot_product
+ } : !transform.any_op
+ transform.yield
+ }
+}
+
+// -----
+
!vecA = vector<1x16x16x4xi8>
!vecB = vector<1x16x16x4xi8>
!vecC = vector<16x16xi32>
@@ -637,32 +946,32 @@ module attributes {transform.with_named_sequence} {
// -----
-!vecA = vector<16x64xi8>
-!vecB = vector<64x16xi8>
-!vecC = vector<16x16xi32>
-!memrefA = memref<32x64xi8>
-!memrefB = memref<64x32xi8>
-!memrefC = memref<32x32xi32>
-#map = affine_map<(d1, d2, d3) -> (d1, d3)>
-#map1 = affine_map<(d1, d2, d3) -> (d3, d2)>
-#map2 = affine_map<(d1, d2, d3) -> (d1, d2)>
-func.func @negative_no_vnni_packed(
+!vecA = vector<1x16x32xbf16>
+!vecB = vector<1x32x32xbf16>
+!vecC = vector<16x32xf32>
+!memrefA = memref<1x32x32xbf16>
+!memrefB = memref<1x32x32xbf16>
+!memrefC = memref<32x32xf32>
+#map = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
+#map1 = affine_map<(d0, d1, d2, d3) -> (d0, d3, d2)>
+#map2 = affine_map<(d0, d1, d2, d3) -> (d1, d2)>
+func.func @negative_wrong_dimensions_online_packing(
%arg0: !memrefA, %arg1: !memrefB, %arg2: !memrefC) -> !memrefC
{
%c0 = arith.constant 0 : index
- %0 = ub.poison : i8
- %32 = ub.poison : i32
+ %0 = ub.poison : bf16
+ %32 = ub.poison : f32
- %1 = vector.transfer_read %arg0[%c0, %c0], %0 {in_bounds = [true, true]} :
+ %1 = vector.transfer_read %arg0[%c0, %c0, %c0], %0 {in_bounds = [true, true, true]} :
!memrefA, !vecA
- %2 = vector.transfer_read %arg1[%c0, %c0], %0 {in_bounds = [true, true]} :
+ %2 = vector.transfer_read %arg1[%c0, %c0, %c0], %0 {in_bounds = [true, true, true]} :
!memrefB, !vecB
%3 = vector.transfer_read %arg2[%c0, %c0], %32 {in_bounds = [true, true]} : !memrefC, !vecC
%4 = vector.contract {
indexing_maps = [#map, #map1, #map2],
- iterator_types = ["parallel", "parallel", "reduction"],
+ iterator_types = ["reduction", "parallel", "parallel", "reduction"],
kind = #vector.kind<add>}
%1, %2, %3 : !vecA, !vecB into !vecC
@@ -671,13 +980,13 @@ func.func @negative_no_vnni_packed(
return %arg2 : !memrefC
}
-// CHECK-LABEL: @negative_no_vnni_packed
-// CHECK-NOT: x86.amx.tile_load {{.*}} !x86.amx.tile<16x64xi8>
-// CHECK-NOT: x86.amx.tile_muli
-// CHECK-NOT: x86.amx.tile_store {{.*}} !x86.amx.tile<16x16xi32>
+// CHECK-LABEL: @negative_wrong_dimensions_online_packing
+// CHECK-NOT: x86.amx.tile_load
+// CHECK-NOT: vector.shuffle
+// CHECK-NOT: x86.amx.tile_mulf
+// CHECK-NOT: x86.amx.tile_store
// CHECK: vector.contract
-
module attributes {transform.with_named_sequence} {
transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
%func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
@@ -1032,3 +1341,154 @@ module attributes {transform.with_named_sequence} {
}
}
+// -----
+
+!vecA = vector<16x64xi8>
+!vecB = vector<64x16xi8>
+!vecC = vector<16x16xi32>
+!memrefA = memref<16x64xi8, strided<[256, 1], offset: ?>>
+!memrefB = memref<64x32xi8, strided<[128, 1], offset: ?>>
+!memrefC = memref<16x32xi32, strided<[128, 1], offset: ?>>
+
+#map = affine_map<(d0, d1, d2) -> (d0, d2)>
+#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
+#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
+
+func.func @negative_vc_wrong_order_no_pair(%arg0: memref<64x256xi8>, %arg1: memref<256x128xi8>, %arg2: memref<64x128xi32>) -> memref<64x128xi32> {
+ %0 = ub.poison : i32
+ %1 = ub.poison : i8
+ %c0 = arith.constant 0 : index
+ %c64 = arith.constant 64 : index
+ %c128 = arith.constant 128 : index
+ %c256 = arith.constant 256 : index
+ %c16 = arith.constant 16 : index
+ %c32 = arith.constant 32 : index
+ scf.for %arg3 = %c0 to %c64 step %c16 {
+ scf.for %arg4 = %c0 to %c128 step %c32 {
+ %subview = memref.subview %arg2[%arg3, %arg4] [16, 32] [1, 1]
+ : memref<64x128xi32> to !memrefC
+ %2 = vector.transfer_read %subview[%c0, %c0], %0 {in_bounds = [true, true]}
+ : !memrefC, !vecC
+ %3 = vector.transfer_read %subview[%c0, %c16], %0 {in_bounds = [true, true]}
+ : !memrefC, !vecC
+ %4:2 = scf.for %arg5 = %c0 to %c256 step %c64 iter_args(%arg6 = %2, %arg7 = %3) -> (!vecC, !vecC) {
+ %subview_0 = memref.subview %arg0[%arg3, %arg5] [16, 64] [1, 1]
+ : memref<64x256xi8> to !memrefA
+ %subview_1 = memref.subview %arg1[%arg5, %arg4] [64, 32] [1, 1]
+ : memref<256x128xi8> to !memrefB
+ %5 = vector.transfer_read %subview_0[%c0, %c0], %1 {in_bounds = [true, true]}
+ : !memrefA, !vecA
+ %6 = vector.transfer_read %subview_1[%c0, %c0], %1 {in_bounds = [true, true]}
+ : !memrefB, !vecB
+ %7 = vector.transfer_read %subview_1[%c0, %c16], %1 {in_bounds = [true, true]}
+ : !memrefB, !vecB
+ %8 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %5, %7, %arg7 {unroll_shape = array<i64: 16, 16, 64>} : !vecA, !vecB into !vecC
+ %9 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %5, %6, %arg6 {unroll_shape = array<i64: 16, 16, 64>} : !vecA, !vecB into !vecC
+ scf.yield %9, %8 : !vecC, !vecC
+ }
+ vector.transfer_write %4#1, %subview[%c0, %c16] {in_bounds = [true, true]}
+ : !vecC, !memrefC
+ vector.transfer_write %4#0, %subview[%c0, %c0] {in_bounds = [true, true]}
+ : !vecC, !memrefC
+ }
+ }
+ %alloc = memref.alloc() : memref<64x128xi32>
+ memref.copy %arg2, %alloc : memref<64x128xi32> to memref<64x128xi32>
+ return %alloc : memref<64x128xi32>
+}
+
+
+// CHECK-LABEL: @negative_vc_wrong_order_no_pair
+// CHECK-NOT: x86.amx.tile_zero : !x86.amx.tile<16x16xi32>
+// CHECK-NOT: x86.amx.tile_load
+// CHECK-NOT: x86.amx.tile_muli
+// CHECK: vector.contract
+
+module attributes {transform.with_named_sequence} {
+ transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
+ %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
+ transform.apply_patterns to %func {
+ transform.apply_patterns.x86.vector_contract_to_amx_dot_product
+ } : !transform.any_op
+ transform.yield
+ }
+}
+
+// -----
+
+!vecA = vector<16x64xi8>
+!vecB = vector<64x16xi8>
+!vecC = vector<16x16xi32>
+!memrefA = memref<32x64xi8, strided<[256, 1], offset: ?>>
+!memrefB = memref<64x16xi8, strided<[128, 1], offset: ?>>
+!memrefC = memref<32x16xi32, strided<[128, 1], offset: ?>>
+
+#map = affine_map<(d0, d1, d2) -> (d0, d2)>
+#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
+#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
+
+func.func @negative_vc_no_pair(%arg0: memref<64x256xi8>, %arg1: memref<256x128xi8>, %arg2: memref<64x128xi32>) -> memref<64x128xi32> {
+ %0 = ub.poison : i32
+ %1 = ub.poison : i8
+ %c0 = arith.constant 0 : index
+ %c64 = arith.constant 64 : index
+ %c128 = arith.constant 128 : index
+ %c256 = arith.constant 256 : index
+ %c32 = arith.constant 32 : index
+ %c16 = arith.constant 16 : index
+ scf.for %arg3 = %c0 to %c64 step %c32 {
+ scf.for %arg4 = %c0 to %c128 step %c16 {
+ %subview = memref.subview %arg2[%arg3, %arg4] [32, 16] [1, 1] : memref<64x128xi32> to !memrefC
+ %2 = vector.transfer_read %subview[%c0, %c0], %0 {in_bounds = [true, true]}
+ : !memrefC, !vecC
+ %3 = vector.transfer_read %subview[%c16, %c0], %0 {in_bounds = [true, true]}
+ : !memrefC, !vecC
+ %4:2 = scf.for %arg5 = %c0 to %c256 step %c64 iter_args(%arg6 = %2, %arg7 = %3) -> (!vecC, !vecC) {
+ %subview_0 = memref.subview %arg0[%arg3, %arg5] [32, 64] [1, 1]
+ : memref<64x256xi8> to !memrefA
+ %subview_1 = memref.subview %arg1[%arg5, %arg4] [64, 16] [1, 1]
+ : memref<256x128xi8> to !memrefB
+ %5 = vector.transfer_read %subview_0[%c0, %c0], %1 {in_bounds = [true, true]}
+ : !memrefA, !vecA
+ %6 = vector.transfer_read %subview_0[%c16, %c0], %1 {in_bounds = [true, true]}
+ : !memrefA, !vecA
+ %7 = vector.transfer_read %subview_1[%c0, %c0], %1 {in_bounds = [true, true]}
+ : !memrefB, !vecB
+ %8 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %5, %7, %arg6 {unroll_shape = array<i64: 16, 16, 64>} : !vecA, !vecB into !vecC
+ %9 = vector.contract {indexing_maps = [#map, #map1, #map2], iterator_types =
+ ["parallel", "parallel", "reduction"], kind = #vector.kind<add>}
+ %6, %7, %arg7 {unroll_shape = array<i64: 16, 16, 64>} : !vecA, !vecB into !vecC
+ scf.yield %8, %9 : !vecC, !vecC
+ }
+ vector.transfer_write %4#1, %subview[%c16, %c0] {in_bounds = [true, true]}
+ : !vecC, !memrefC
+ vector.transfer_write %4#0, %subview[%c0, %c0] {in_bounds = [true, true]}
+ : !vecC, !memrefC
+ }
+ }
+ %alloc = memref.alloc() : memref<64x128xi32>
+ memref.copy %arg2, %alloc : memref<64x128xi32> to memref<64x128xi32>
+ return %alloc : memref<64x128xi32>
+}
+
+// CHECK-LABEL: @negative_vc_no_pair
+// CHECK-NOT: x86.amx.tile_zero : !x86.amx.tile<16x16xi32>
+// CHECK-NOT: x86.amx.tile_load
+// CHECK-NOT: x86.amx.tile_muli
+// CHECK: vector.contract
+
+module attributes {transform.with_named_sequence} {
+ transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
+ %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op
+ transform.apply_patterns to %func {
+ transform.apply_patterns.x86.vector_contract_to_amx_dot_product
+ } : !transform.any_op
+ transform.yield
+ }
+}
>From a4e8d63d6302c6b800284636867553e2fe718ae6 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 13 Apr 2026 09:00:45 +0200
Subject: [PATCH 16/36] [RISCV] Remove codegen for vp_{u,s}{add,sub}sat
(#191639)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off 4 intrinsics from #179622.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 11 +-
.../Target/RISCV/RISCVTargetTransformInfo.h | 4 -
.../RISCV/rvv/fixed-vectors-vsadd-vp.ll | 425 +++++------
.../RISCV/rvv/fixed-vectors-vsaddu-vp.ll | 427 +++++------
.../RISCV/rvv/fixed-vectors-vssub-vp.ll | 542 +++++++-------
.../RISCV/rvv/fixed-vectors-vssubu-vp.ll | 594 +++++++---------
.../CodeGen/RISCV/rvv/sink-splat-operands.ll | 60 +-
llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll | 525 ++++++--------
llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll | 527 ++++++--------
llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll | 673 ++++++++----------
llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll | 673 ++++++++----------
11 files changed, 1992 insertions(+), 2469 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8b70acc3e9021..f4e8bebaf2814 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -878,8 +878,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_ZERO_EXTEND, ISD::VP_TRUNCATE, ISD::VP_SMIN,
ISD::VP_SMAX, ISD::VP_UMIN, ISD::VP_UMAX,
ISD::VP_ABS, ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
- ISD::VP_SADDSAT, ISD::VP_UADDSAT, ISD::VP_SSUBSAT,
- ISD::VP_USUBSAT, ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
+ ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
static const unsigned FloatingPointVPOps[] = {
ISD::VP_FADD, ISD::VP_FSUB, ISD::VP_FMUL,
@@ -7557,10 +7556,6 @@ static unsigned getRISCVVLOp(SDValue Op) {
VP_CASE(UMAX) // VP_UMAX
VP_CASE(SETCC) // VP_SETCC
VP_CASE(BITREVERSE) // VP_BITREVERSE
- VP_CASE(SADDSAT) // VP_SADDSAT
- VP_CASE(UADDSAT) // VP_UADDSAT
- VP_CASE(SSUBSAT) // VP_SSUBSAT
- VP_CASE(USUBSAT) // VP_USUBSAT
VP_CASE(BSWAP) // VP_BSWAP
case ISD::CTLZ_ZERO_UNDEF:
return RISCVISD::CTLZ_VL;
@@ -8948,10 +8943,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_UDIV:
case ISD::VP_SREM:
case ISD::VP_UREM:
- case ISD::VP_UADDSAT:
- case ISD::VP_USUBSAT:
- case ISD::VP_SADDSAT:
- case ISD::VP_SSUBSAT:
return lowerVPOp(Op, DAG);
case ISD::VP_AND:
case ISD::VP_OR:
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index c582a678ecb16..81184ac78a569 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -414,7 +414,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_reduce_umax,
Intrinsic::vp_reduce_umin,
Intrinsic::vp_reduce_xor,
- Intrinsic::vp_sadd_sat,
Intrinsic::vp_scatter,
Intrinsic::vp_sdiv,
Intrinsic::vp_select,
@@ -424,16 +423,13 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_smin,
Intrinsic::vp_sqrt,
Intrinsic::vp_srem,
- Intrinsic::vp_ssub_sat,
Intrinsic::vp_store,
Intrinsic::vp_sub,
Intrinsic::vp_trunc,
- Intrinsic::vp_uadd_sat,
Intrinsic::vp_udiv,
Intrinsic::vp_umax,
Intrinsic::vp_umin,
Intrinsic::vp_urem,
- Intrinsic::vp_usub_sat,
Intrinsic::vp_xor,
Intrinsic::vp_zext};
if (!ST->hasVInstructions() ||
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
index e979426c007ef..9b4d4628edd5a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
@@ -10,14 +10,13 @@ define <8 x i7> @vsadd_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vv v8, v8, v8
-; CHECK-NEXT: li a1, 63
+; CHECK-NEXT: li a0, 63
; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsra.vi v8, v8, 1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vmin.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vmin.vx v8, v8, a0
; CHECK-NEXT: li a0, 192
-; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vmax.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.sadd.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
@@ -26,8 +25,8 @@ define <8 x i7> @vsadd_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
define <2 x i8> @vsadd_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -36,7 +35,7 @@ define <2 x i8> @vsadd_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroe
define <2 x i8> @vsadd_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -46,8 +45,8 @@ define <2 x i8> @vsadd_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %
define <2 x i8> @vsadd_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
@@ -58,7 +57,7 @@ define <2 x i8> @vsadd_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %ev
define <2 x i8> @vsadd_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
@@ -70,8 +69,8 @@ define <2 x i8> @vsadd_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
define <2 x i8> @vsadd_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -80,7 +79,7 @@ define <2 x i8> @vsadd_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i8> @vsadd_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
@@ -90,8 +89,8 @@ define <2 x i8> @vsadd_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
define <4 x i8> @vsadd_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -100,7 +99,7 @@ define <4 x i8> @vsadd_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroe
define <4 x i8> @vsadd_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -110,8 +109,8 @@ define <4 x i8> @vsadd_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %
define <4 x i8> @vsadd_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -122,8 +121,8 @@ define <4 x i8> @vsadd_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %ev
define <4 x i8> @vsadd_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v4i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -134,7 +133,7 @@ define <4 x i8> @vsadd_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zer
define <4 x i8> @vsadd_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
@@ -146,8 +145,8 @@ define <4 x i8> @vsadd_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
define <4 x i8> @vsadd_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -156,7 +155,7 @@ define <4 x i8> @vsadd_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i8> @vsadd_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
@@ -166,8 +165,8 @@ define <4 x i8> @vsadd_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
define <5 x i8> @vsadd_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
ret <5 x i8> %v
@@ -176,7 +175,7 @@ define <5 x i8> @vsadd_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroe
define <5 x i8> @vsadd_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
@@ -186,8 +185,8 @@ define <5 x i8> @vsadd_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %
define <5 x i8> @vsadd_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
%vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
@@ -198,7 +197,7 @@ define <5 x i8> @vsadd_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %ev
define <5 x i8> @vsadd_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
@@ -210,8 +209,8 @@ define <5 x i8> @vsadd_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
define <5 x i8> @vsadd_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
ret <5 x i8> %v
@@ -220,7 +219,7 @@ define <5 x i8> @vsadd_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
define <5 x i8> @vsadd_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
@@ -230,8 +229,8 @@ define <5 x i8> @vsadd_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
define <8 x i8> @vsadd_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -240,7 +239,7 @@ define <8 x i8> @vsadd_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroe
define <8 x i8> @vsadd_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -250,8 +249,8 @@ define <8 x i8> @vsadd_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %
define <8 x i8> @vsadd_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
@@ -262,7 +261,7 @@ define <8 x i8> @vsadd_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %ev
define <8 x i8> @vsadd_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
@@ -274,8 +273,8 @@ define <8 x i8> @vsadd_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
define <8 x i8> @vsadd_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -284,7 +283,7 @@ define <8 x i8> @vsadd_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i8> @vsadd_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
@@ -294,8 +293,8 @@ define <8 x i8> @vsadd_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
define <16 x i8> @vsadd_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -304,7 +303,7 @@ define <16 x i8> @vsadd_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32
define <16 x i8> @vsadd_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -314,8 +313,8 @@ define <16 x i8> @vsadd_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroe
define <16 x i8> @vsadd_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
%vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
@@ -326,7 +325,7 @@ define <16 x i8> @vsadd_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext
define <16 x i8> @vsadd_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
@@ -338,8 +337,8 @@ define <16 x i8> @vsadd_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl
define <16 x i8> @vsadd_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -348,7 +347,7 @@ define <16 x i8> @vsadd_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl)
define <16 x i8> @vsadd_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
@@ -358,23 +357,10 @@ define <16 x i8> @vsadd_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v258i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a0, a1, -128
-; CHECK-NEXT: sltu a3, a1, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
+; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB32_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
ret <256 x i8> %v
@@ -383,19 +369,9 @@ define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
define <256 x i8> @vsadd_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v258i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB33_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: .LBB33_2:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1
-; CHECK-NEXT: addi a1, a0, -128
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
@@ -407,14 +383,10 @@ define <256 x i8> @vsadd_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsadd_vi_v258i8_evl129:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
+; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
ret <256 x i8> %v
@@ -425,7 +397,8 @@ define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
@@ -434,8 +407,8 @@ define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
define <2 x i16> @vsadd_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -444,7 +417,7 @@ define <2 x i16> @vsadd_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 z
define <2 x i16> @vsadd_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -454,8 +427,8 @@ define <2 x i16> @vsadd_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe
define <2 x i16> @vsadd_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
%vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
@@ -466,7 +439,7 @@ define <2 x i16> @vsadd_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext
define <2 x i16> @vsadd_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
@@ -478,8 +451,8 @@ define <2 x i16> @vsadd_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev
define <2 x i16> @vsadd_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -488,7 +461,7 @@ define <2 x i16> @vsadd_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i16> @vsadd_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
@@ -498,8 +471,8 @@ define <2 x i16> @vsadd_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
define <4 x i16> @vsadd_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -508,7 +481,7 @@ define <4 x i16> @vsadd_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 z
define <4 x i16> @vsadd_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -518,8 +491,8 @@ define <4 x i16> @vsadd_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe
define <4 x i16> @vsadd_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
%vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
@@ -530,7 +503,7 @@ define <4 x i16> @vsadd_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext
define <4 x i16> @vsadd_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
@@ -542,8 +515,8 @@ define <4 x i16> @vsadd_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev
define <4 x i16> @vsadd_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -552,7 +525,7 @@ define <4 x i16> @vsadd_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i16> @vsadd_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
@@ -562,8 +535,8 @@ define <4 x i16> @vsadd_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
define <8 x i16> @vsadd_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -572,7 +545,7 @@ define <8 x i16> @vsadd_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 z
define <8 x i16> @vsadd_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -582,8 +555,8 @@ define <8 x i16> @vsadd_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroe
define <8 x i16> @vsadd_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
@@ -594,7 +567,7 @@ define <8 x i16> @vsadd_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext
define <8 x i16> @vsadd_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
@@ -606,8 +579,8 @@ define <8 x i16> @vsadd_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev
define <8 x i16> @vsadd_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -616,7 +589,7 @@ define <8 x i16> @vsadd_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i16> @vsadd_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
@@ -626,8 +599,8 @@ define <8 x i16> @vsadd_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
define <16 x i16> @vsadd_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -636,7 +609,7 @@ define <16 x i16> @vsadd_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m,
define <16 x i16> @vsadd_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -646,8 +619,8 @@ define <16 x i16> @vsadd_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 z
define <16 x i16> @vsadd_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
%vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
@@ -658,7 +631,7 @@ define <16 x i16> @vsadd_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zer
define <16 x i16> @vsadd_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
@@ -670,8 +643,8 @@ define <16 x i16> @vsadd_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext
define <16 x i16> @vsadd_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -680,7 +653,7 @@ define <16 x i16> @vsadd_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %ev
define <16 x i16> @vsadd_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
@@ -690,8 +663,8 @@ define <16 x i16> @vsadd_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
define <2 x i32> @vsadd_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -700,7 +673,7 @@ define <2 x i32> @vsadd_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 z
define <2 x i32> @vsadd_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -710,8 +683,8 @@ define <2 x i32> @vsadd_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe
define <2 x i32> @vsadd_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
@@ -722,7 +695,7 @@ define <2 x i32> @vsadd_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext
define <2 x i32> @vsadd_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
@@ -734,8 +707,8 @@ define <2 x i32> @vsadd_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev
define <2 x i32> @vsadd_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -744,7 +717,7 @@ define <2 x i32> @vsadd_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i32> @vsadd_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
@@ -754,8 +727,8 @@ define <2 x i32> @vsadd_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
define <4 x i32> @vsadd_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -764,7 +737,7 @@ define <4 x i32> @vsadd_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 z
define <4 x i32> @vsadd_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -774,8 +747,8 @@ define <4 x i32> @vsadd_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroe
define <4 x i32> @vsadd_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
%vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
@@ -786,7 +759,7 @@ define <4 x i32> @vsadd_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext
define <4 x i32> @vsadd_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
@@ -798,8 +771,8 @@ define <4 x i32> @vsadd_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev
define <4 x i32> @vsadd_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -808,7 +781,7 @@ define <4 x i32> @vsadd_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i32> @vsadd_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
@@ -818,8 +791,8 @@ define <4 x i32> @vsadd_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
define <8 x i32> @vsadd_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -828,7 +801,7 @@ define <8 x i32> @vsadd_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 z
define <8 x i32> @vsadd_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -838,8 +811,8 @@ define <8 x i32> @vsadd_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroe
define <8 x i32> @vsadd_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
%vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
@@ -850,7 +823,7 @@ define <8 x i32> @vsadd_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext
define <8 x i32> @vsadd_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
@@ -862,8 +835,8 @@ define <8 x i32> @vsadd_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev
define <8 x i32> @vsadd_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -872,7 +845,7 @@ define <8 x i32> @vsadd_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i32> @vsadd_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
@@ -882,8 +855,8 @@ define <8 x i32> @vsadd_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
define <16 x i32> @vsadd_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -892,7 +865,7 @@ define <16 x i32> @vsadd_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m,
define <16 x i32> @vsadd_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -902,8 +875,8 @@ define <16 x i32> @vsadd_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 z
define <16 x i32> @vsadd_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
@@ -914,7 +887,7 @@ define <16 x i32> @vsadd_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zer
define <16 x i32> @vsadd_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
@@ -926,8 +899,8 @@ define <16 x i32> @vsadd_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext
define <16 x i32> @vsadd_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -936,7 +909,7 @@ define <16 x i32> @vsadd_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %ev
define <16 x i32> @vsadd_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
@@ -946,8 +919,8 @@ define <16 x i32> @vsadd_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
define <2 x i64> @vsadd_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -956,7 +929,7 @@ define <2 x i64> @vsadd_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 z
define <2 x i64> @vsadd_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -973,16 +946,15 @@ define <2 x i64> @vsadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
-; RV32-NEXT: vsadd.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsadd_vx_v2i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
@@ -1000,7 +972,6 @@ define <2 x i64> @vsadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vsadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1008,7 +979,7 @@ define <2 x i64> @vsadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
;
; RV64-LABEL: vsadd_vx_v2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
@@ -1020,8 +991,8 @@ define <2 x i64> @vsadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
define <2 x i64> @vsadd_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -1030,7 +1001,7 @@ define <2 x i64> @vsadd_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i64> @vsadd_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
@@ -1040,8 +1011,8 @@ define <2 x i64> @vsadd_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
define <4 x i64> @vsadd_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1050,7 +1021,7 @@ define <4 x i64> @vsadd_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 z
define <4 x i64> @vsadd_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -1067,16 +1038,15 @@ define <4 x i64> @vsadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
-; RV32-NEXT: vsadd.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsadd_vx_v4i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
-; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
@@ -1094,7 +1064,6 @@ define <4 x i64> @vsadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
; RV32-NEXT: vsadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1102,7 +1071,7 @@ define <4 x i64> @vsadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
;
; RV64-LABEL: vsadd_vx_v4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
@@ -1114,8 +1083,8 @@ define <4 x i64> @vsadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
define <4 x i64> @vsadd_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1124,7 +1093,7 @@ define <4 x i64> @vsadd_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i64> @vsadd_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
@@ -1134,8 +1103,8 @@ define <4 x i64> @vsadd_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
define <8 x i64> @vsadd_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1144,7 +1113,7 @@ define <8 x i64> @vsadd_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 z
define <8 x i64> @vsadd_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -1161,16 +1130,15 @@ define <8 x i64> @vsadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
-; RV32-NEXT: vsadd.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsadd_vx_v8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
-; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
@@ -1188,7 +1156,6 @@ define <8 x i64> @vsadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vsadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1196,7 +1163,7 @@ define <8 x i64> @vsadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
;
; RV64-LABEL: vsadd_vx_v8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
@@ -1208,8 +1175,8 @@ define <8 x i64> @vsadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
define <8 x i64> @vsadd_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1218,7 +1185,7 @@ define <8 x i64> @vsadd_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i64> @vsadd_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
@@ -1228,8 +1195,8 @@ define <8 x i64> @vsadd_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
define <16 x i64> @vsadd_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1238,7 +1205,7 @@ define <16 x i64> @vsadd_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m,
define <16 x i64> @vsadd_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_v16i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -1255,16 +1222,15 @@ define <16 x i64> @vsadd_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zer
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vsadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsadd_vx_v16i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
@@ -1282,7 +1248,6 @@ define <16 x i64> @vsadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1290,7 +1255,7 @@ define <16 x i64> @vsadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
;
; RV64-LABEL: vsadd_vx_v16i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
@@ -1302,8 +1267,8 @@ define <16 x i64> @vsadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
define <16 x i64> @vsadd_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1312,7 +1277,7 @@ define <16 x i64> @vsadd_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
define <16 x i64> @vsadd_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v16i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
@@ -1324,23 +1289,9 @@ define <16 x i64> @vsadd_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_v32i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB108_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB108_2:
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -1349,19 +1300,8 @@ define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_v32i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB109_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB109_2:
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
@@ -1371,8 +1311,9 @@ define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsadd_vx_v32i64_evl12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
ret <32 x i64> %v
@@ -1381,13 +1322,9 @@ define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vsadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsadd_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
+; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
index fe175bd635abe..c1a534e44e617 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
@@ -7,13 +7,12 @@
define <8 x i7> @vsaddu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i7:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 127
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vand.vx v9, v9, a1
-; CHECK-NEXT: vand.vx v8, v8, a1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vminu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.uadd.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
@@ -22,8 +21,8 @@ define <8 x i7> @vsaddu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zero
define <2 x i8> @vsaddu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -32,7 +31,7 @@ define <2 x i8> @vsaddu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zero
define <2 x i8> @vsaddu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -42,8 +41,8 @@ define <2 x i8> @vsaddu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext
define <2 x i8> @vsaddu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
@@ -54,7 +53,7 @@ define <2 x i8> @vsaddu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %e
define <2 x i8> @vsaddu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
@@ -66,8 +65,8 @@ define <2 x i8> @vsaddu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl)
define <2 x i8> @vsaddu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -76,7 +75,7 @@ define <2 x i8> @vsaddu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i8> @vsaddu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
@@ -86,8 +85,8 @@ define <2 x i8> @vsaddu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
define <4 x i8> @vsaddu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -96,7 +95,7 @@ define <4 x i8> @vsaddu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zero
define <4 x i8> @vsaddu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -106,8 +105,8 @@ define <4 x i8> @vsaddu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext
define <4 x i8> @vsaddu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -118,8 +117,8 @@ define <4 x i8> @vsaddu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %e
define <4 x i8> @vsaddu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v4i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -130,7 +129,7 @@ define <4 x i8> @vsaddu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 ze
define <4 x i8> @vsaddu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
@@ -142,8 +141,8 @@ define <4 x i8> @vsaddu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl)
define <4 x i8> @vsaddu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -152,7 +151,7 @@ define <4 x i8> @vsaddu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i8> @vsaddu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
@@ -162,8 +161,8 @@ define <4 x i8> @vsaddu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
define <5 x i8> @vsaddu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
ret <5 x i8> %v
@@ -172,7 +171,7 @@ define <5 x i8> @vsaddu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zero
define <5 x i8> @vsaddu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
@@ -182,8 +181,8 @@ define <5 x i8> @vsaddu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext
define <5 x i8> @vsaddu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
%vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
@@ -194,7 +193,7 @@ define <5 x i8> @vsaddu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %e
define <5 x i8> @vsaddu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
@@ -206,8 +205,8 @@ define <5 x i8> @vsaddu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl)
define <5 x i8> @vsaddu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
ret <5 x i8> %v
@@ -216,7 +215,7 @@ define <5 x i8> @vsaddu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
define <5 x i8> @vsaddu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
@@ -226,8 +225,8 @@ define <5 x i8> @vsaddu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
define <8 x i8> @vsaddu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -236,7 +235,7 @@ define <8 x i8> @vsaddu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zero
define <8 x i8> @vsaddu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -246,8 +245,8 @@ define <8 x i8> @vsaddu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext
define <8 x i8> @vsaddu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
@@ -258,7 +257,7 @@ define <8 x i8> @vsaddu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %e
define <8 x i8> @vsaddu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
@@ -270,8 +269,8 @@ define <8 x i8> @vsaddu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl)
define <8 x i8> @vsaddu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -280,7 +279,7 @@ define <8 x i8> @vsaddu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i8> @vsaddu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
@@ -290,8 +289,8 @@ define <8 x i8> @vsaddu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
define <16 x i8> @vsaddu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -300,7 +299,7 @@ define <16 x i8> @vsaddu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32
define <16 x i8> @vsaddu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -310,8 +309,8 @@ define <16 x i8> @vsaddu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zero
define <16 x i8> @vsaddu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
%vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
@@ -322,7 +321,7 @@ define <16 x i8> @vsaddu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroex
define <16 x i8> @vsaddu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
@@ -334,8 +333,8 @@ define <16 x i8> @vsaddu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %ev
define <16 x i8> @vsaddu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -344,7 +343,7 @@ define <16 x i8> @vsaddu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl)
define <16 x i8> @vsaddu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
@@ -354,23 +353,10 @@ define <16 x i8> @vsaddu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v258i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a0, a1, -128
-; CHECK-NEXT: sltu a3, a1, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
+; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB32_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
ret <256 x i8> %v
@@ -379,19 +365,9 @@ define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
define <256 x i8> @vsaddu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v258i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB33_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: .LBB33_2:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1
-; CHECK-NEXT: addi a1, a0, -128
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
@@ -403,14 +379,10 @@ define <256 x i8> @vsaddu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsaddu_vi_v258i8_evl129:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
ret <256 x i8> %v
@@ -421,7 +393,8 @@ define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
@@ -430,8 +403,8 @@ define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
define <2 x i16> @vsaddu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -440,7 +413,7 @@ define <2 x i16> @vsaddu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32
define <2 x i16> @vsaddu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -450,8 +423,8 @@ define <2 x i16> @vsaddu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zero
define <2 x i16> @vsaddu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
%vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
@@ -462,7 +435,7 @@ define <2 x i16> @vsaddu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroex
define <2 x i16> @vsaddu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
@@ -474,8 +447,8 @@ define <2 x i16> @vsaddu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %e
define <2 x i16> @vsaddu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -484,7 +457,7 @@ define <2 x i16> @vsaddu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl)
define <2 x i16> @vsaddu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
@@ -494,8 +467,8 @@ define <2 x i16> @vsaddu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
define <4 x i16> @vsaddu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -504,7 +477,7 @@ define <4 x i16> @vsaddu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32
define <4 x i16> @vsaddu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -514,8 +487,8 @@ define <4 x i16> @vsaddu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zero
define <4 x i16> @vsaddu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
%vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
@@ -526,7 +499,7 @@ define <4 x i16> @vsaddu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroex
define <4 x i16> @vsaddu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
@@ -538,8 +511,8 @@ define <4 x i16> @vsaddu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %e
define <4 x i16> @vsaddu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -548,7 +521,7 @@ define <4 x i16> @vsaddu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl)
define <4 x i16> @vsaddu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
@@ -558,8 +531,8 @@ define <4 x i16> @vsaddu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
define <8 x i16> @vsaddu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -568,7 +541,7 @@ define <8 x i16> @vsaddu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32
define <8 x i16> @vsaddu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -578,8 +551,8 @@ define <8 x i16> @vsaddu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zero
define <8 x i16> @vsaddu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
@@ -590,7 +563,7 @@ define <8 x i16> @vsaddu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroex
define <8 x i16> @vsaddu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
@@ -602,8 +575,8 @@ define <8 x i16> @vsaddu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %e
define <8 x i16> @vsaddu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -612,7 +585,7 @@ define <8 x i16> @vsaddu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i16> @vsaddu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
@@ -622,8 +595,8 @@ define <8 x i16> @vsaddu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
define <16 x i16> @vsaddu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -632,7 +605,7 @@ define <16 x i16> @vsaddu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m,
define <16 x i16> @vsaddu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -642,8 +615,8 @@ define <16 x i16> @vsaddu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32
define <16 x i16> @vsaddu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
%vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
@@ -654,7 +627,7 @@ define <16 x i16> @vsaddu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 ze
define <16 x i16> @vsaddu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
@@ -666,8 +639,8 @@ define <16 x i16> @vsaddu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext
define <16 x i16> @vsaddu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -676,7 +649,7 @@ define <16 x i16> @vsaddu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %e
define <16 x i16> @vsaddu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
@@ -686,8 +659,8 @@ define <16 x i16> @vsaddu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
define <2 x i32> @vsaddu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -696,7 +669,7 @@ define <2 x i32> @vsaddu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32
define <2 x i32> @vsaddu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -706,8 +679,8 @@ define <2 x i32> @vsaddu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zero
define <2 x i32> @vsaddu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
@@ -718,7 +691,7 @@ define <2 x i32> @vsaddu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroex
define <2 x i32> @vsaddu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
@@ -730,8 +703,8 @@ define <2 x i32> @vsaddu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %e
define <2 x i32> @vsaddu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -740,7 +713,7 @@ define <2 x i32> @vsaddu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl)
define <2 x i32> @vsaddu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
@@ -750,8 +723,8 @@ define <2 x i32> @vsaddu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
define <4 x i32> @vsaddu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -760,7 +733,7 @@ define <4 x i32> @vsaddu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32
define <4 x i32> @vsaddu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -770,8 +743,8 @@ define <4 x i32> @vsaddu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zero
define <4 x i32> @vsaddu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
%vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
@@ -782,7 +755,7 @@ define <4 x i32> @vsaddu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroex
define <4 x i32> @vsaddu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
@@ -794,8 +767,8 @@ define <4 x i32> @vsaddu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %e
define <4 x i32> @vsaddu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -804,7 +777,7 @@ define <4 x i32> @vsaddu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl)
define <4 x i32> @vsaddu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
@@ -814,8 +787,8 @@ define <4 x i32> @vsaddu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
define <8 x i32> @vsaddu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -824,7 +797,7 @@ define <8 x i32> @vsaddu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32
define <8 x i32> @vsaddu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -834,8 +807,8 @@ define <8 x i32> @vsaddu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zero
define <8 x i32> @vsaddu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
%vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
@@ -846,7 +819,7 @@ define <8 x i32> @vsaddu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroex
define <8 x i32> @vsaddu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
@@ -858,8 +831,8 @@ define <8 x i32> @vsaddu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %e
define <8 x i32> @vsaddu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -868,7 +841,7 @@ define <8 x i32> @vsaddu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i32> @vsaddu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
@@ -878,8 +851,8 @@ define <8 x i32> @vsaddu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
define <16 x i32> @vsaddu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -888,7 +861,7 @@ define <16 x i32> @vsaddu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m,
define <16 x i32> @vsaddu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -898,8 +871,8 @@ define <16 x i32> @vsaddu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32
define <16 x i32> @vsaddu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
@@ -910,7 +883,7 @@ define <16 x i32> @vsaddu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 ze
define <16 x i32> @vsaddu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
@@ -922,8 +895,8 @@ define <16 x i32> @vsaddu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext
define <16 x i32> @vsaddu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -932,7 +905,7 @@ define <16 x i32> @vsaddu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %e
define <16 x i32> @vsaddu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
@@ -942,8 +915,8 @@ define <16 x i32> @vsaddu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
define <2 x i64> @vsaddu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -952,7 +925,7 @@ define <2 x i64> @vsaddu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32
define <2 x i64> @vsaddu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -969,16 +942,15 @@ define <2 x i64> @vsaddu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroex
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
-; RV32-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsaddu_vx_v2i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
@@ -996,7 +968,6 @@ define <2 x i64> @vsaddu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %e
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vsaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1004,7 +975,7 @@ define <2 x i64> @vsaddu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %e
;
; RV64-LABEL: vsaddu_vx_v2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
@@ -1016,8 +987,8 @@ define <2 x i64> @vsaddu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %e
define <2 x i64> @vsaddu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -1026,7 +997,7 @@ define <2 x i64> @vsaddu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl)
define <2 x i64> @vsaddu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
@@ -1036,8 +1007,8 @@ define <2 x i64> @vsaddu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
define <4 x i64> @vsaddu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1046,7 +1017,7 @@ define <4 x i64> @vsaddu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32
define <4 x i64> @vsaddu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -1063,16 +1034,15 @@ define <4 x i64> @vsaddu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroex
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
-; RV32-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsaddu_vx_v4i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
-; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
@@ -1090,7 +1060,6 @@ define <4 x i64> @vsaddu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %e
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
; RV32-NEXT: vsaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1098,7 +1067,7 @@ define <4 x i64> @vsaddu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %e
;
; RV64-LABEL: vsaddu_vx_v4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
@@ -1110,8 +1079,8 @@ define <4 x i64> @vsaddu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %e
define <4 x i64> @vsaddu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1120,7 +1089,7 @@ define <4 x i64> @vsaddu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl)
define <4 x i64> @vsaddu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
@@ -1130,8 +1099,8 @@ define <4 x i64> @vsaddu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
define <8 x i64> @vsaddu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1140,7 +1109,7 @@ define <8 x i64> @vsaddu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32
define <8 x i64> @vsaddu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -1157,16 +1126,15 @@ define <8 x i64> @vsaddu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroex
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
-; RV32-NEXT: vsaddu.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsaddu_vx_v8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
-; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
@@ -1184,7 +1152,6 @@ define <8 x i64> @vsaddu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %e
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vsaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1192,7 +1159,7 @@ define <8 x i64> @vsaddu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %e
;
; RV64-LABEL: vsaddu_vx_v8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
@@ -1204,8 +1171,8 @@ define <8 x i64> @vsaddu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %e
define <8 x i64> @vsaddu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1214,7 +1181,7 @@ define <8 x i64> @vsaddu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i64> @vsaddu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
@@ -1224,8 +1191,8 @@ define <8 x i64> @vsaddu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
define <16 x i64> @vsaddu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1234,7 +1201,7 @@ define <16 x i64> @vsaddu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m,
define <16 x i64> @vsaddu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_v16i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -1251,16 +1218,15 @@ define <16 x i64> @vsaddu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 ze
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vsaddu.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsaddu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsaddu_vx_v16i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
@@ -1278,7 +1244,6 @@ define <16 x i64> @vsaddu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsaddu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1286,7 +1251,7 @@ define <16 x i64> @vsaddu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
;
; RV64-LABEL: vsaddu_vx_v16i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
@@ -1298,8 +1263,8 @@ define <16 x i64> @vsaddu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
define <16 x i64> @vsaddu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1308,7 +1273,7 @@ define <16 x i64> @vsaddu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %e
define <16 x i64> @vsaddu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v16i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
@@ -1320,23 +1285,9 @@ define <16 x i64> @vsaddu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_v32i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB108_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB108_2:
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -1345,19 +1296,8 @@ define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_v32i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB109_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB109_2:
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
@@ -1367,8 +1307,9 @@ define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsaddu_vx_v32i64_evl12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
ret <32 x i64> %v
@@ -1377,13 +1318,9 @@ define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vsaddu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsaddu_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
index ee278da2d8699..2115f3dafae48 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
@@ -10,14 +10,13 @@ define <8 x i7> @vssub_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vv v8, v8, v8
-; CHECK-NEXT: li a1, 63
+; CHECK-NEXT: li a0, 63
; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsra.vi v8, v8, 1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vmin.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vsub.vv v8, v8, v9
+; CHECK-NEXT: vmin.vx v8, v8, a0
; CHECK-NEXT: li a0, 192
-; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vmax.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.ssub.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
@@ -26,8 +25,8 @@ define <8 x i7> @vssub_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
define <2 x i8> @vssub_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -36,7 +35,7 @@ define <2 x i8> @vssub_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroe
define <2 x i8> @vssub_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -46,8 +45,8 @@ define <2 x i8> @vssub_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %
define <2 x i8> @vssub_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
@@ -58,7 +57,7 @@ define <2 x i8> @vssub_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %ev
define <2 x i8> @vssub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
@@ -70,9 +69,9 @@ define <2 x i8> @vssub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
define <2 x i8> @vssub_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -81,9 +80,9 @@ define <2 x i8> @vssub_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i8> @vssub_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
ret <2 x i8> %v
@@ -92,8 +91,8 @@ define <2 x i8> @vssub_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
define <4 x i8> @vssub_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -102,7 +101,7 @@ define <4 x i8> @vssub_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroe
define <4 x i8> @vssub_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -112,8 +111,8 @@ define <4 x i8> @vssub_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %
define <4 x i8> @vssub_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -126,8 +125,7 @@ define <4 x i8> @vssub_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zer
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vssub.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -138,7 +136,7 @@ define <4 x i8> @vssub_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zer
define <4 x i8> @vssub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
@@ -150,9 +148,9 @@ define <4 x i8> @vssub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
define <4 x i8> @vssub_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -161,9 +159,9 @@ define <4 x i8> @vssub_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i8> @vssub_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i8> %v
@@ -172,8 +170,8 @@ define <4 x i8> @vssub_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
define <5 x i8> @vssub_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
ret <5 x i8> %v
@@ -182,7 +180,7 @@ define <5 x i8> @vssub_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroe
define <5 x i8> @vssub_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
@@ -192,8 +190,8 @@ define <5 x i8> @vssub_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %
define <5 x i8> @vssub_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
%vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
@@ -204,7 +202,7 @@ define <5 x i8> @vssub_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %ev
define <5 x i8> @vssub_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
@@ -216,9 +214,9 @@ define <5 x i8> @vssub_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
define <5 x i8> @vssub_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
ret <5 x i8> %v
@@ -227,9 +225,9 @@ define <5 x i8> @vssub_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
define <5 x i8> @vssub_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
ret <5 x i8> %v
@@ -238,8 +236,8 @@ define <5 x i8> @vssub_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
define <8 x i8> @vssub_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -248,7 +246,7 @@ define <8 x i8> @vssub_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroe
define <8 x i8> @vssub_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -258,8 +256,8 @@ define <8 x i8> @vssub_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %
define <8 x i8> @vssub_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
@@ -270,7 +268,7 @@ define <8 x i8> @vssub_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %ev
define <8 x i8> @vssub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
@@ -282,9 +280,9 @@ define <8 x i8> @vssub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
define <8 x i8> @vssub_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -293,9 +291,9 @@ define <8 x i8> @vssub_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i8> @vssub_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i8> %v
@@ -304,8 +302,8 @@ define <8 x i8> @vssub_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
define <16 x i8> @vssub_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -314,7 +312,7 @@ define <16 x i8> @vssub_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32
define <16 x i8> @vssub_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -324,8 +322,8 @@ define <16 x i8> @vssub_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroe
define <16 x i8> @vssub_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
%vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
@@ -336,7 +334,7 @@ define <16 x i8> @vssub_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext
define <16 x i8> @vssub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
@@ -348,9 +346,9 @@ define <16 x i8> @vssub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl
define <16 x i8> @vssub_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -359,9 +357,9 @@ define <16 x i8> @vssub_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl)
define <16 x i8> @vssub_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i8> %v
@@ -370,24 +368,11 @@ define <16 x i8> @vssub_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v258i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: addi a3, a1, -128
-; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB32_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: li a0, 128
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: vssub.vx v16, v16, a1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
ret <256 x i8> %v
@@ -396,21 +381,11 @@ define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
define <256 x i8> @vssub_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v258i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB33_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: .LBB33_2:
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a2
-; CHECK-NEXT: addi a1, a0, -128
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: li a0, 128
+; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a2
+; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: vssub.vx v16, v16, a1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
ret <256 x i8> %v
@@ -421,15 +396,11 @@ define <256 x i8> @vssub_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssub_vi_v258i8_evl129:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: vssub.vx v16, v16, a1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
ret <256 x i8> %v
@@ -441,7 +412,8 @@ define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: vssub.vx v16, v16, a1
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
@@ -450,8 +422,8 @@ define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
define <2 x i16> @vssub_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -460,7 +432,7 @@ define <2 x i16> @vssub_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 z
define <2 x i16> @vssub_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -470,8 +442,8 @@ define <2 x i16> @vssub_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe
define <2 x i16> @vssub_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
%vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
@@ -482,7 +454,7 @@ define <2 x i16> @vssub_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext
define <2 x i16> @vssub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
@@ -494,9 +466,9 @@ define <2 x i16> @vssub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev
define <2 x i16> @vssub_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -505,9 +477,9 @@ define <2 x i16> @vssub_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i16> @vssub_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
ret <2 x i16> %v
@@ -516,8 +488,8 @@ define <2 x i16> @vssub_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
define <4 x i16> @vssub_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -526,7 +498,7 @@ define <4 x i16> @vssub_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 z
define <4 x i16> @vssub_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -536,8 +508,8 @@ define <4 x i16> @vssub_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe
define <4 x i16> @vssub_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
%vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
@@ -548,7 +520,7 @@ define <4 x i16> @vssub_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext
define <4 x i16> @vssub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
@@ -560,9 +532,9 @@ define <4 x i16> @vssub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev
define <4 x i16> @vssub_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -571,9 +543,9 @@ define <4 x i16> @vssub_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i16> @vssub_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i16> %v
@@ -582,8 +554,8 @@ define <4 x i16> @vssub_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
define <8 x i16> @vssub_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -592,7 +564,7 @@ define <8 x i16> @vssub_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 z
define <8 x i16> @vssub_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -602,8 +574,8 @@ define <8 x i16> @vssub_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroe
define <8 x i16> @vssub_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
@@ -614,7 +586,7 @@ define <8 x i16> @vssub_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext
define <8 x i16> @vssub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
@@ -626,9 +598,9 @@ define <8 x i16> @vssub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev
define <8 x i16> @vssub_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -637,9 +609,9 @@ define <8 x i16> @vssub_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i16> @vssub_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i16> %v
@@ -648,8 +620,8 @@ define <8 x i16> @vssub_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
define <16 x i16> @vssub_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -658,7 +630,7 @@ define <16 x i16> @vssub_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m,
define <16 x i16> @vssub_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -668,8 +640,8 @@ define <16 x i16> @vssub_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 z
define <16 x i16> @vssub_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
%vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
@@ -680,7 +652,7 @@ define <16 x i16> @vssub_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zer
define <16 x i16> @vssub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
@@ -692,9 +664,9 @@ define <16 x i16> @vssub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext
define <16 x i16> @vssub_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -703,9 +675,9 @@ define <16 x i16> @vssub_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %ev
define <16 x i16> @vssub_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i16> %v
@@ -714,8 +686,8 @@ define <16 x i16> @vssub_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
define <2 x i32> @vssub_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -724,7 +696,7 @@ define <2 x i32> @vssub_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 z
define <2 x i32> @vssub_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -734,8 +706,8 @@ define <2 x i32> @vssub_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe
define <2 x i32> @vssub_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
@@ -746,7 +718,7 @@ define <2 x i32> @vssub_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext
define <2 x i32> @vssub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
@@ -758,9 +730,9 @@ define <2 x i32> @vssub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev
define <2 x i32> @vssub_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -769,9 +741,9 @@ define <2 x i32> @vssub_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i32> @vssub_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
ret <2 x i32> %v
@@ -780,8 +752,8 @@ define <2 x i32> @vssub_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
define <4 x i32> @vssub_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -790,7 +762,7 @@ define <4 x i32> @vssub_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 z
define <4 x i32> @vssub_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -800,8 +772,8 @@ define <4 x i32> @vssub_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroe
define <4 x i32> @vssub_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
%vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
@@ -812,7 +784,7 @@ define <4 x i32> @vssub_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext
define <4 x i32> @vssub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
@@ -824,9 +796,9 @@ define <4 x i32> @vssub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev
define <4 x i32> @vssub_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -835,9 +807,9 @@ define <4 x i32> @vssub_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i32> @vssub_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i32> %v
@@ -846,8 +818,8 @@ define <4 x i32> @vssub_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
define <8 x i32> @vssub_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -856,7 +828,7 @@ define <8 x i32> @vssub_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 z
define <8 x i32> @vssub_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -866,8 +838,8 @@ define <8 x i32> @vssub_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroe
define <8 x i32> @vssub_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
%vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
@@ -878,7 +850,7 @@ define <8 x i32> @vssub_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext
define <8 x i32> @vssub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
@@ -890,9 +862,9 @@ define <8 x i32> @vssub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev
define <8 x i32> @vssub_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -901,9 +873,9 @@ define <8 x i32> @vssub_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i32> @vssub_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i32> %v
@@ -912,8 +884,8 @@ define <8 x i32> @vssub_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
define <16 x i32> @vssub_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -922,7 +894,7 @@ define <16 x i32> @vssub_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m,
define <16 x i32> @vssub_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -932,8 +904,8 @@ define <16 x i32> @vssub_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 z
define <16 x i32> @vssub_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
@@ -944,7 +916,7 @@ define <16 x i32> @vssub_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zer
define <16 x i32> @vssub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
@@ -956,9 +928,9 @@ define <16 x i32> @vssub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext
define <16 x i32> @vssub_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -967,9 +939,9 @@ define <16 x i32> @vssub_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %ev
define <16 x i32> @vssub_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i32> %v
@@ -978,8 +950,8 @@ define <16 x i32> @vssub_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
define <2 x i64> @vssub_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -988,7 +960,7 @@ define <2 x i64> @vssub_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 z
define <2 x i64> @vssub_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -1005,16 +977,15 @@ define <2 x i64> @vssub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
-; RV32-NEXT: vssub.vv v8, v8, v9, v0.t
+; RV32-NEXT: vssub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssub_vx_v2i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT: vssub.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
@@ -1032,7 +1003,6 @@ define <2 x i64> @vssub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vssub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1040,7 +1010,7 @@ define <2 x i64> @vssub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
;
; RV64-LABEL: vssub_vx_v2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
@@ -1052,9 +1022,9 @@ define <2 x i64> @vssub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
define <2 x i64> @vssub_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -1063,9 +1033,9 @@ define <2 x i64> @vssub_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i64> @vssub_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
ret <2 x i64> %v
@@ -1074,8 +1044,8 @@ define <2 x i64> @vssub_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
define <4 x i64> @vssub_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1084,7 +1054,7 @@ define <4 x i64> @vssub_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 z
define <4 x i64> @vssub_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -1101,16 +1071,15 @@ define <4 x i64> @vssub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
-; RV32-NEXT: vssub.vv v8, v8, v10, v0.t
+; RV32-NEXT: vssub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssub_vx_v4i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
-; RV64-NEXT: vssub.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
@@ -1128,7 +1097,6 @@ define <4 x i64> @vssub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
; RV32-NEXT: vssub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1136,7 +1104,7 @@ define <4 x i64> @vssub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
;
; RV64-LABEL: vssub_vx_v4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
@@ -1148,9 +1116,9 @@ define <4 x i64> @vssub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
define <4 x i64> @vssub_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1159,9 +1127,9 @@ define <4 x i64> @vssub_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i64> @vssub_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i64> %v
@@ -1170,8 +1138,8 @@ define <4 x i64> @vssub_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
define <8 x i64> @vssub_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1180,7 +1148,7 @@ define <8 x i64> @vssub_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 z
define <8 x i64> @vssub_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -1197,16 +1165,15 @@ define <8 x i64> @vssub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
-; RV32-NEXT: vssub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vssub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssub_vx_v8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
-; RV64-NEXT: vssub.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
@@ -1224,7 +1191,6 @@ define <8 x i64> @vssub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vssub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1232,7 +1198,7 @@ define <8 x i64> @vssub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
;
; RV64-LABEL: vssub_vx_v8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
@@ -1244,9 +1210,9 @@ define <8 x i64> @vssub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
define <8 x i64> @vssub_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1255,9 +1221,9 @@ define <8 x i64> @vssub_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i64> @vssub_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i64> %v
@@ -1266,8 +1232,8 @@ define <8 x i64> @vssub_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
define <16 x i64> @vssub_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1276,7 +1242,7 @@ define <16 x i64> @vssub_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m,
define <16 x i64> @vssub_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_v16i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -1293,16 +1259,15 @@ define <16 x i64> @vssub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zer
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vssub.vv v8, v8, v16, v0.t
+; RV32-NEXT: vssub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssub_vx_v16i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vssub.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
@@ -1320,7 +1285,6 @@ define <16 x i64> @vssub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vssub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1328,7 +1292,7 @@ define <16 x i64> @vssub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
;
; RV64-LABEL: vssub_vx_v16i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
@@ -1340,9 +1304,9 @@ define <16 x i64> @vssub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
define <16 x i64> @vssub_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1351,9 +1315,9 @@ define <16 x i64> @vssub_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
define <16 x i64> @vssub_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v16i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i64> %v
@@ -1364,24 +1328,10 @@ define <16 x i64> @vssub_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_v32i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB108_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB108_2:
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a2, v0.t
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
+; CHECK-NEXT: vssub.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -1390,21 +1340,10 @@ define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
define <32 x i64> @vssub_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_v32i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB109_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB109_2:
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a2
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a2
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
+; CHECK-NEXT: vssub.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
ret <32 x i64> %v
@@ -1414,8 +1353,9 @@ define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssub_vx_v32i64_evl12:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
+; CHECK-NEXT: vssub.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
ret <32 x i64> %v
@@ -1424,14 +1364,10 @@ define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vssub_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssub_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vssub.vx v8, v8, a0
+; CHECK-NEXT: vssub.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
index 09657aa237827..7d6b373fe3909 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
@@ -7,12 +7,11 @@
define <8 x i7> @vssubu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i7:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 127
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vand.vx v9, v9, a1
-; CHECK-NEXT: vand.vx v8, v8, a1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.usub.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
@@ -21,8 +20,8 @@ define <8 x i7> @vssubu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zero
define <2 x i8> @vssubu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -31,7 +30,7 @@ define <2 x i8> @vssubu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zero
define <2 x i8> @vssubu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -41,8 +40,8 @@ define <2 x i8> @vssubu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext
define <2 x i8> @vssubu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
@@ -53,7 +52,7 @@ define <2 x i8> @vssubu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %e
define <2 x i8> @vssubu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
@@ -65,9 +64,9 @@ define <2 x i8> @vssubu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl)
define <2 x i8> @vssubu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -76,9 +75,9 @@ define <2 x i8> @vssubu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i8> @vssubu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
ret <2 x i8> %v
@@ -87,8 +86,8 @@ define <2 x i8> @vssubu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
define <4 x i8> @vssubu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -97,7 +96,7 @@ define <4 x i8> @vssubu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zero
define <4 x i8> @vssubu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -107,8 +106,8 @@ define <4 x i8> @vssubu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext
define <4 x i8> @vssubu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -121,8 +120,7 @@ define <4 x i8> @vssubu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 ze
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vssubu.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -133,7 +131,7 @@ define <4 x i8> @vssubu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 ze
define <4 x i8> @vssubu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
@@ -145,9 +143,9 @@ define <4 x i8> @vssubu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl)
define <4 x i8> @vssubu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -156,9 +154,9 @@ define <4 x i8> @vssubu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i8> @vssubu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i8> %v
@@ -167,8 +165,8 @@ define <4 x i8> @vssubu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
define <5 x i8> @vssubu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
ret <5 x i8> %v
@@ -177,7 +175,7 @@ define <5 x i8> @vssubu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zero
define <5 x i8> @vssubu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
@@ -187,8 +185,8 @@ define <5 x i8> @vssubu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext
define <5 x i8> @vssubu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
%vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
@@ -199,7 +197,7 @@ define <5 x i8> @vssubu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %e
define <5 x i8> @vssubu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
@@ -211,9 +209,8 @@ define <5 x i8> @vssubu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl)
define <5 x i8> @vssubu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v5i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
ret <5 x i8> %v
@@ -222,9 +219,8 @@ define <5 x i8> @vssubu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
define <5 x i8> @vssubu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v5i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret
%v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
ret <5 x i8> %v
@@ -233,8 +229,8 @@ define <5 x i8> @vssubu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
define <8 x i8> @vssubu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -243,7 +239,7 @@ define <8 x i8> @vssubu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zero
define <8 x i8> @vssubu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -253,8 +249,8 @@ define <8 x i8> @vssubu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext
define <8 x i8> @vssubu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
@@ -265,7 +261,7 @@ define <8 x i8> @vssubu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %e
define <8 x i8> @vssubu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
@@ -277,9 +273,9 @@ define <8 x i8> @vssubu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl)
define <8 x i8> @vssubu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -288,9 +284,9 @@ define <8 x i8> @vssubu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i8> @vssubu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i8> %v
@@ -299,8 +295,8 @@ define <8 x i8> @vssubu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
define <16 x i8> @vssubu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -309,7 +305,7 @@ define <16 x i8> @vssubu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32
define <16 x i8> @vssubu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -319,8 +315,8 @@ define <16 x i8> @vssubu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zero
define <16 x i8> @vssubu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
%vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
@@ -331,7 +327,7 @@ define <16 x i8> @vssubu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroex
define <16 x i8> @vssubu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
@@ -343,9 +339,9 @@ define <16 x i8> @vssubu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %ev
define <16 x i8> @vssubu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -354,9 +350,9 @@ define <16 x i8> @vssubu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl)
define <16 x i8> @vssubu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i8> %v
@@ -365,24 +361,10 @@ define <16 x i8> @vssubu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v258i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: addi a3, a1, -128
-; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB32_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: li a0, 128
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
ret <256 x i8> %v
@@ -391,21 +373,10 @@ define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
define <256 x i8> @vssubu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v258i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB33_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 128
-; CHECK-NEXT: .LBB33_2:
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a2
-; CHECK-NEXT: addi a1, a0, -128
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a2
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
ret <256 x i8> %v
@@ -416,15 +387,10 @@ define <256 x i8> @vssubu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssubu_vi_v258i8_evl129:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
ret <256 x i8> %v
@@ -434,9 +400,9 @@ define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssubu_vi_v258i8_evl128:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
@@ -445,8 +411,8 @@ define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
define <2 x i16> @vssubu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -455,7 +421,7 @@ define <2 x i16> @vssubu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32
define <2 x i16> @vssubu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -465,8 +431,8 @@ define <2 x i16> @vssubu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zero
define <2 x i16> @vssubu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
%vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
@@ -477,7 +443,7 @@ define <2 x i16> @vssubu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroex
define <2 x i16> @vssubu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
@@ -489,9 +455,9 @@ define <2 x i16> @vssubu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %e
define <2 x i16> @vssubu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -500,9 +466,9 @@ define <2 x i16> @vssubu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl)
define <2 x i16> @vssubu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
ret <2 x i16> %v
@@ -511,8 +477,8 @@ define <2 x i16> @vssubu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
define <4 x i16> @vssubu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -521,7 +487,7 @@ define <4 x i16> @vssubu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32
define <4 x i16> @vssubu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -531,8 +497,8 @@ define <4 x i16> @vssubu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zero
define <4 x i16> @vssubu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
%vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
@@ -543,7 +509,7 @@ define <4 x i16> @vssubu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroex
define <4 x i16> @vssubu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
@@ -555,9 +521,9 @@ define <4 x i16> @vssubu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %e
define <4 x i16> @vssubu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -566,9 +532,9 @@ define <4 x i16> @vssubu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl)
define <4 x i16> @vssubu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i16> %v
@@ -577,8 +543,8 @@ define <4 x i16> @vssubu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
define <8 x i16> @vssubu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -587,7 +553,7 @@ define <8 x i16> @vssubu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32
define <8 x i16> @vssubu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -597,8 +563,8 @@ define <8 x i16> @vssubu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zero
define <8 x i16> @vssubu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
@@ -609,7 +575,7 @@ define <8 x i16> @vssubu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroex
define <8 x i16> @vssubu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
@@ -621,9 +587,9 @@ define <8 x i16> @vssubu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %e
define <8 x i16> @vssubu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -632,9 +598,9 @@ define <8 x i16> @vssubu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i16> @vssubu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i16> %v
@@ -643,8 +609,8 @@ define <8 x i16> @vssubu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
define <16 x i16> @vssubu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -653,7 +619,7 @@ define <16 x i16> @vssubu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m,
define <16 x i16> @vssubu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -663,8 +629,8 @@ define <16 x i16> @vssubu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32
define <16 x i16> @vssubu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
%vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
@@ -675,7 +641,7 @@ define <16 x i16> @vssubu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 ze
define <16 x i16> @vssubu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
@@ -687,9 +653,9 @@ define <16 x i16> @vssubu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext
define <16 x i16> @vssubu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -698,9 +664,9 @@ define <16 x i16> @vssubu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %e
define <16 x i16> @vssubu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i16> %v
@@ -709,8 +675,8 @@ define <16 x i16> @vssubu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
define <2 x i32> @vssubu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -719,7 +685,7 @@ define <2 x i32> @vssubu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32
define <2 x i32> @vssubu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -729,8 +695,8 @@ define <2 x i32> @vssubu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zero
define <2 x i32> @vssubu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
@@ -741,7 +707,7 @@ define <2 x i32> @vssubu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroex
define <2 x i32> @vssubu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
@@ -753,9 +719,9 @@ define <2 x i32> @vssubu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %e
define <2 x i32> @vssubu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -764,9 +730,9 @@ define <2 x i32> @vssubu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl)
define <2 x i32> @vssubu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
ret <2 x i32> %v
@@ -775,8 +741,8 @@ define <2 x i32> @vssubu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
define <4 x i32> @vssubu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -785,7 +751,7 @@ define <4 x i32> @vssubu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32
define <4 x i32> @vssubu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -795,8 +761,8 @@ define <4 x i32> @vssubu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zero
define <4 x i32> @vssubu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
%vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
@@ -807,7 +773,7 @@ define <4 x i32> @vssubu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroex
define <4 x i32> @vssubu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
@@ -819,9 +785,9 @@ define <4 x i32> @vssubu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %e
define <4 x i32> @vssubu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -830,9 +796,9 @@ define <4 x i32> @vssubu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl)
define <4 x i32> @vssubu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i32> %v
@@ -841,8 +807,8 @@ define <4 x i32> @vssubu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
define <8 x i32> @vssubu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -851,7 +817,7 @@ define <8 x i32> @vssubu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32
define <8 x i32> @vssubu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -861,8 +827,8 @@ define <8 x i32> @vssubu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zero
define <8 x i32> @vssubu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
%vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
@@ -873,7 +839,7 @@ define <8 x i32> @vssubu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroex
define <8 x i32> @vssubu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
@@ -885,9 +851,9 @@ define <8 x i32> @vssubu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %e
define <8 x i32> @vssubu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -896,9 +862,9 @@ define <8 x i32> @vssubu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i32> @vssubu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i32> %v
@@ -907,8 +873,8 @@ define <8 x i32> @vssubu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
define <16 x i32> @vssubu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -917,7 +883,7 @@ define <16 x i32> @vssubu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m,
define <16 x i32> @vssubu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -927,8 +893,8 @@ define <16 x i32> @vssubu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32
define <16 x i32> @vssubu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
@@ -939,7 +905,7 @@ define <16 x i32> @vssubu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 ze
define <16 x i32> @vssubu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
@@ -951,9 +917,9 @@ define <16 x i32> @vssubu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext
define <16 x i32> @vssubu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -962,9 +928,9 @@ define <16 x i32> @vssubu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %e
define <16 x i32> @vssubu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i32> %v
@@ -973,8 +939,8 @@ define <16 x i32> @vssubu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
define <2 x i64> @vssubu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -983,7 +949,7 @@ define <2 x i64> @vssubu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32
define <2 x i64> @vssubu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
@@ -1000,16 +966,15 @@ define <2 x i64> @vssubu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroex
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
-; RV32-NEXT: vssubu.vv v8, v8, v9, v0.t
+; RV32-NEXT: vssubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssubu_vx_v2i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
@@ -1027,7 +992,6 @@ define <2 x i64> @vssubu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %e
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vssubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1035,7 +999,7 @@ define <2 x i64> @vssubu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %e
;
; RV64-LABEL: vssubu_vx_v2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
@@ -1047,9 +1011,9 @@ define <2 x i64> @vssubu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %e
define <2 x i64> @vssubu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -1058,9 +1022,9 @@ define <2 x i64> @vssubu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl)
define <2 x i64> @vssubu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
ret <2 x i64> %v
@@ -1069,8 +1033,8 @@ define <2 x i64> @vssubu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
define <4 x i64> @vssubu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1079,7 +1043,7 @@ define <4 x i64> @vssubu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32
define <4 x i64> @vssubu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
@@ -1096,16 +1060,15 @@ define <4 x i64> @vssubu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroex
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
-; RV32-NEXT: vssubu.vv v8, v8, v10, v0.t
+; RV32-NEXT: vssubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssubu_vx_v4i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
-; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
@@ -1123,7 +1086,6 @@ define <4 x i64> @vssubu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %e
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
; RV32-NEXT: vssubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1131,7 +1093,7 @@ define <4 x i64> @vssubu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %e
;
; RV64-LABEL: vssubu_vx_v4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
@@ -1143,9 +1105,9 @@ define <4 x i64> @vssubu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %e
define <4 x i64> @vssubu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1154,9 +1116,9 @@ define <4 x i64> @vssubu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl)
define <4 x i64> @vssubu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i64> %v
@@ -1165,8 +1127,8 @@ define <4 x i64> @vssubu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
define <8 x i64> @vssubu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1175,7 +1137,7 @@ define <8 x i64> @vssubu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32
define <8 x i64> @vssubu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
@@ -1192,16 +1154,15 @@ define <8 x i64> @vssubu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroex
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
-; RV32-NEXT: vssubu.vv v8, v8, v12, v0.t
+; RV32-NEXT: vssubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssubu_vx_v8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
-; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
@@ -1219,7 +1180,6 @@ define <8 x i64> @vssubu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %e
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vssubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1227,7 +1187,7 @@ define <8 x i64> @vssubu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %e
;
; RV64-LABEL: vssubu_vx_v8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
@@ -1239,9 +1199,9 @@ define <8 x i64> @vssubu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %e
define <8 x i64> @vssubu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1250,9 +1210,9 @@ define <8 x i64> @vssubu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i64> @vssubu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
ret <8 x i64> %v
@@ -1261,8 +1221,8 @@ define <8 x i64> @vssubu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
define <16 x i64> @vssubu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1271,7 +1231,7 @@ define <16 x i64> @vssubu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m,
define <16 x i64> @vssubu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_v16i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
@@ -1288,16 +1248,15 @@ define <16 x i64> @vssubu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 ze
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vssubu.vv v8, v8, v16, v0.t
+; RV32-NEXT: vssubu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssubu_vx_v16i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
@@ -1315,7 +1274,6 @@ define <16 x i64> @vssubu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vssubu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1323,7 +1281,7 @@ define <16 x i64> @vssubu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
;
; RV64-LABEL: vssubu_vx_v16i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
@@ -1335,9 +1293,9 @@ define <16 x i64> @vssubu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext
define <16 x i64> @vssubu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1346,9 +1304,9 @@ define <16 x i64> @vssubu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %e
define <16 x i64> @vssubu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_v16i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i64> %v
@@ -1357,77 +1315,73 @@ define <16 x i64> @vssubu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; Test that split-legalization works as expected.
define <32 x i64> @vssubu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vssubu_vx_v32i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB108_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB108_2:
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t
-; CHECK-NEXT: ret
+; RV32-LABEL: vssubu_vx_v32i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmv.v.i v16, 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vssubu_vx_v32i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmv.v.i v16, 0
+; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
}
define <32 x i64> @vssubu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
-; CHECK-LABEL: vssubu_vi_v32i64_unmasked:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB109_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB109_2:
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a2
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a2
-; CHECK-NEXT: ret
+; RV32-LABEL: vssubu_vi_v32i64_unmasked:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmv.v.i v16, 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vssubu_vi_v32i64_unmasked:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmv.v.i v16, 0
+; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
ret <32 x i64> %v
}
define <32 x i64> @vssubu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
-; CHECK-LABEL: vssubu_vx_v32i64_evl12:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
-; CHECK-NEXT: ret
+; RV32-LABEL: vssubu_vx_v32i64_evl12:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmv.v.i v16, 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vssubu_vx_v32i64_evl12:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmv.v.i v16, 0
+; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
ret <32 x i64> %v
}
define <32 x i64> @vssubu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
-; CHECK-LABEL: vssubu_vx_v32i64_evl27:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: ret
+; RV32-LABEL: vssubu_vx_v32i64_evl27:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmv.v.i v16, 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vssubu_vx_v32i64_evl27:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmv.v.i v16, 0
+; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
ret <32 x i64> %v
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
index 2adc9baaa1b6a..3f87d7779a8f3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -5133,18 +5133,16 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_vp_sadd_sat(ptr nocapture %a, i32 signext %x, <4 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: sink_splat_vp_sadd_sat:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lui a3, 1
-; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: lui a2, 1
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: .LBB111_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: bne a0, a3, .LBB111_1
+; CHECK-NEXT: bne a0, a2, .LBB111_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret
entry:
@@ -5169,18 +5167,16 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_vp_sadd_sat_commute(ptr nocapture %a, i32 signext %x, <4 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: sink_splat_vp_sadd_sat_commute:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lui a3, 1
-; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: lui a2, 1
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: .LBB112_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: bne a0, a3, .LBB112_1
+; CHECK-NEXT: bne a0, a2, .LBB112_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret
entry:
@@ -5205,18 +5201,16 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_vp_ssub_sat(ptr nocapture %a, i32 signext %x, <4 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: sink_splat_vp_ssub_sat:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a3, 1024
+; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: .LBB113_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: addi a3, a3, 4
-; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: addi a2, a2, 4
+; CHECK-NEXT: vssub.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -16
-; CHECK-NEXT: bnez a3, .LBB113_1
+; CHECK-NEXT: bnez a2, .LBB113_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret
entry:
@@ -5241,18 +5235,16 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_vp_uadd_sat(ptr nocapture %a, i32 signext %x, <4 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: sink_splat_vp_uadd_sat:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lui a3, 1
-; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: lui a2, 1
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: .LBB114_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: bne a0, a3, .LBB114_1
+; CHECK-NEXT: bne a0, a2, .LBB114_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret
entry:
@@ -5277,18 +5269,16 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_vp_uadd_sat_commute(ptr nocapture %a, i32 signext %x, <4 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: sink_splat_vp_uadd_sat_commute:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lui a3, 1
-; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: lui a2, 1
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: .LBB115_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: bne a0, a3, .LBB115_1
+; CHECK-NEXT: bne a0, a2, .LBB115_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret
entry:
@@ -5313,18 +5303,16 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_vp_usub_sat(ptr nocapture %a, i32 signext %x, <4 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: sink_splat_vp_usub_sat:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a3, 1024
+; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: .LBB116_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: addi a3, a3, 4
-; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: addi a2, a2, 4
+; CHECK-NEXT: vssubu.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, -16
-; CHECK-NEXT: bnez a3, .LBB116_1
+; CHECK-NEXT: bnez a2, .LBB116_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
index 07a9384ac4bae..d45ca7eaa20d8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
@@ -7,14 +7,12 @@
define <vscale x 8 x i7> @vsadd_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv8i7:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vadd.vv v9, v9, v9
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: vsra.vi v8, v8, 1
-; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t
-; CHECK-NEXT: li a0, 192
-; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer
@@ -25,8 +23,8 @@ define <vscale x 8 x i7> @vsadd_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <
define <vscale x 1 x i8> @vsadd_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -35,7 +33,7 @@ define <vscale x 1 x i8> @vsadd_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i
define <vscale x 1 x i8> @vsadd_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -45,8 +43,8 @@ define <vscale x 1 x i8> @vsadd_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscal
define <vscale x 1 x i8> @vsadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -57,8 +55,8 @@ define <vscale x 1 x i8> @vsadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale
define <vscale x 1 x i8> @vsadd_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv1i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -69,7 +67,7 @@ define <vscale x 1 x i8> @vsadd_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b,
define <vscale x 1 x i8> @vsadd_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
@@ -81,8 +79,8 @@ define <vscale x 1 x i8> @vsadd_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b,
define <vscale x 1 x i8> @vsadd_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -91,7 +89,7 @@ define <vscale x 1 x i8> @vsadd_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i
define <vscale x 1 x i8> @vsadd_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -101,8 +99,8 @@ define <vscale x 1 x i8> @vsadd_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 ze
define <vscale x 2 x i8> @vsadd_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -111,7 +109,7 @@ define <vscale x 2 x i8> @vsadd_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i
define <vscale x 2 x i8> @vsadd_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -121,8 +119,8 @@ define <vscale x 2 x i8> @vsadd_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscal
define <vscale x 2 x i8> @vsadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
@@ -133,7 +131,7 @@ define <vscale x 2 x i8> @vsadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale
define <vscale x 2 x i8> @vsadd_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
@@ -145,8 +143,8 @@ define <vscale x 2 x i8> @vsadd_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b,
define <vscale x 2 x i8> @vsadd_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -155,7 +153,7 @@ define <vscale x 2 x i8> @vsadd_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i
define <vscale x 2 x i8> @vsadd_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -165,8 +163,8 @@ define <vscale x 2 x i8> @vsadd_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 ze
define <vscale x 3 x i8> @vsadd_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i8> %v
@@ -175,7 +173,7 @@ define <vscale x 3 x i8> @vsadd_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i
define <vscale x 3 x i8> @vsadd_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)
@@ -185,8 +183,8 @@ define <vscale x 3 x i8> @vsadd_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscal
define <vscale x 3 x i8> @vsadd_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
@@ -197,7 +195,7 @@ define <vscale x 3 x i8> @vsadd_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale
define <vscale x 3 x i8> @vsadd_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
@@ -209,8 +207,8 @@ define <vscale x 3 x i8> @vsadd_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b,
define <vscale x 3 x i8> @vsadd_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i8> %v
@@ -219,7 +217,7 @@ define <vscale x 3 x i8> @vsadd_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i
define <vscale x 3 x i8> @vsadd_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)
@@ -229,8 +227,8 @@ define <vscale x 3 x i8> @vsadd_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 ze
define <vscale x 4 x i8> @vsadd_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -239,7 +237,7 @@ define <vscale x 4 x i8> @vsadd_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i
define <vscale x 4 x i8> @vsadd_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -249,8 +247,8 @@ define <vscale x 4 x i8> @vsadd_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscal
define <vscale x 4 x i8> @vsadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
@@ -261,7 +259,7 @@ define <vscale x 4 x i8> @vsadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale
define <vscale x 4 x i8> @vsadd_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
@@ -273,8 +271,8 @@ define <vscale x 4 x i8> @vsadd_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b,
define <vscale x 4 x i8> @vsadd_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -283,7 +281,7 @@ define <vscale x 4 x i8> @vsadd_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i
define <vscale x 4 x i8> @vsadd_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -293,8 +291,8 @@ define <vscale x 4 x i8> @vsadd_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 ze
define <vscale x 8 x i8> @vsadd_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -303,7 +301,7 @@ define <vscale x 8 x i8> @vsadd_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i
define <vscale x 8 x i8> @vsadd_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -313,8 +311,8 @@ define <vscale x 8 x i8> @vsadd_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscal
define <vscale x 8 x i8> @vsadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -325,7 +323,7 @@ define <vscale x 8 x i8> @vsadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale
define <vscale x 8 x i8> @vsadd_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
@@ -337,8 +335,8 @@ define <vscale x 8 x i8> @vsadd_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b,
define <vscale x 8 x i8> @vsadd_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -347,7 +345,7 @@ define <vscale x 8 x i8> @vsadd_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i
define <vscale x 8 x i8> @vsadd_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -357,8 +355,8 @@ define <vscale x 8 x i8> @vsadd_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 ze
define <vscale x 16 x i8> @vsadd_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -367,7 +365,7 @@ define <vscale x 16 x i8> @vsadd_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
define <vscale x 16 x i8> @vsadd_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -377,8 +375,8 @@ define <vscale x 16 x i8> @vsadd_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vs
define <vscale x 16 x i8> @vsadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
@@ -389,7 +387,7 @@ define <vscale x 16 x i8> @vsadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vsca
define <vscale x 16 x i8> @vsadd_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
@@ -401,8 +399,8 @@ define <vscale x 16 x i8> @vsadd_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8
define <vscale x 16 x i8> @vsadd_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -411,7 +409,7 @@ define <vscale x 16 x i8> @vsadd_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
define <vscale x 16 x i8> @vsadd_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -421,8 +419,8 @@ define <vscale x 16 x i8> @vsadd_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32
define <vscale x 32 x i8> @vsadd_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -431,7 +429,7 @@ define <vscale x 32 x i8> @vsadd_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
define <vscale x 32 x i8> @vsadd_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -441,8 +439,8 @@ define <vscale x 32 x i8> @vsadd_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vs
define <vscale x 32 x i8> @vsadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
@@ -453,7 +451,7 @@ define <vscale x 32 x i8> @vsadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vsca
define <vscale x 32 x i8> @vsadd_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
@@ -465,8 +463,8 @@ define <vscale x 32 x i8> @vsadd_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8
define <vscale x 32 x i8> @vsadd_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -475,7 +473,7 @@ define <vscale x 32 x i8> @vsadd_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
define <vscale x 32 x i8> @vsadd_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -485,8 +483,8 @@ define <vscale x 32 x i8> @vsadd_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32
define <vscale x 64 x i8> @vsadd_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -495,7 +493,7 @@ define <vscale x 64 x i8> @vsadd_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
define <vscale x 64 x i8> @vsadd_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)
@@ -505,8 +503,8 @@ define <vscale x 64 x i8> @vsadd_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vs
define <vscale x 64 x i8> @vsadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
@@ -517,7 +515,7 @@ define <vscale x 64 x i8> @vsadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vsca
define <vscale x 64 x i8> @vsadd_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
@@ -529,8 +527,8 @@ define <vscale x 64 x i8> @vsadd_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8
define <vscale x 64 x i8> @vsadd_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -539,7 +537,7 @@ define <vscale x 64 x i8> @vsadd_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
define <vscale x 64 x i8> @vsadd_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)
@@ -551,24 +549,9 @@ define <vscale x 64 x i8> @vsadd_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32
define <vscale x 128 x i8> @vsadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv128i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
-; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.sadd.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -577,20 +560,9 @@ define <vscale x 128 x i8> @vsadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
define <vscale x 128 x i8> @vsadd_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv128i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1
-; CHECK-NEXT: bltu a0, a1, .LBB51_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB51_2:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.sadd.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)
ret <vscale x 128 x i8> %v
@@ -599,8 +571,8 @@ define <vscale x 128 x i8> @vsadd_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va,
define <vscale x 1 x i16> @vsadd_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -609,7 +581,7 @@ define <vscale x 1 x i16> @vsadd_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vsadd_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -619,8 +591,8 @@ define <vscale x 1 x i16> @vsadd_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vs
define <vscale x 1 x i16> @vsadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -631,7 +603,7 @@ define <vscale x 1 x i16> @vsadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vsc
define <vscale x 1 x i16> @vsadd_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
@@ -643,8 +615,8 @@ define <vscale x 1 x i16> @vsadd_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16
define <vscale x 1 x i16> @vsadd_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -653,7 +625,7 @@ define <vscale x 1 x i16> @vsadd_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vsadd_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -663,8 +635,8 @@ define <vscale x 1 x i16> @vsadd_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32
define <vscale x 2 x i16> @vsadd_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -673,7 +645,7 @@ define <vscale x 2 x i16> @vsadd_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vsadd_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -683,8 +655,8 @@ define <vscale x 2 x i16> @vsadd_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vs
define <vscale x 2 x i16> @vsadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
@@ -695,7 +667,7 @@ define <vscale x 2 x i16> @vsadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vsc
define <vscale x 2 x i16> @vsadd_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
@@ -707,8 +679,8 @@ define <vscale x 2 x i16> @vsadd_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16
define <vscale x 2 x i16> @vsadd_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -717,7 +689,7 @@ define <vscale x 2 x i16> @vsadd_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vsadd_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -727,8 +699,8 @@ define <vscale x 2 x i16> @vsadd_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32
define <vscale x 4 x i16> @vsadd_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -737,7 +709,7 @@ define <vscale x 4 x i16> @vsadd_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vsadd_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -747,8 +719,8 @@ define <vscale x 4 x i16> @vsadd_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vs
define <vscale x 4 x i16> @vsadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
@@ -759,7 +731,7 @@ define <vscale x 4 x i16> @vsadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vsc
define <vscale x 4 x i16> @vsadd_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
@@ -771,8 +743,8 @@ define <vscale x 4 x i16> @vsadd_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16
define <vscale x 4 x i16> @vsadd_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -781,7 +753,7 @@ define <vscale x 4 x i16> @vsadd_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vsadd_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -791,8 +763,8 @@ define <vscale x 4 x i16> @vsadd_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32
define <vscale x 8 x i16> @vsadd_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -801,7 +773,7 @@ define <vscale x 8 x i16> @vsadd_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vsadd_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -811,8 +783,8 @@ define <vscale x 8 x i16> @vsadd_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vs
define <vscale x 8 x i16> @vsadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -823,7 +795,7 @@ define <vscale x 8 x i16> @vsadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vsc
define <vscale x 8 x i16> @vsadd_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
@@ -835,8 +807,8 @@ define <vscale x 8 x i16> @vsadd_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16
define <vscale x 8 x i16> @vsadd_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -845,7 +817,7 @@ define <vscale x 8 x i16> @vsadd_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vsadd_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -855,8 +827,8 @@ define <vscale x 8 x i16> @vsadd_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32
define <vscale x 16 x i16> @vsadd_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -865,7 +837,7 @@ define <vscale x 16 x i16> @vsadd_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x
define <vscale x 16 x i16> @vsadd_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -875,8 +847,8 @@ define <vscale x 16 x i16> @vsadd_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 16 x i16> @vsadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
@@ -887,7 +859,7 @@ define <vscale x 16 x i16> @vsadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <
define <vscale x 16 x i16> @vsadd_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
@@ -899,8 +871,8 @@ define <vscale x 16 x i16> @vsadd_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 16 x i16> @vsadd_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -909,7 +881,7 @@ define <vscale x 16 x i16> @vsadd_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x
define <vscale x 16 x i16> @vsadd_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -919,8 +891,8 @@ define <vscale x 16 x i16> @vsadd_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 32 x i16> @vsadd_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -929,7 +901,7 @@ define <vscale x 32 x i16> @vsadd_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x
define <vscale x 32 x i16> @vsadd_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -939,8 +911,8 @@ define <vscale x 32 x i16> @vsadd_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 32 x i16> @vsadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
@@ -951,7 +923,7 @@ define <vscale x 32 x i16> @vsadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <
define <vscale x 32 x i16> @vsadd_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
@@ -963,8 +935,8 @@ define <vscale x 32 x i16> @vsadd_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 32 x i16> @vsadd_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -973,7 +945,7 @@ define <vscale x 32 x i16> @vsadd_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x
define <vscale x 32 x i16> @vsadd_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -983,8 +955,8 @@ define <vscale x 32 x i16> @vsadd_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 1 x i32> @vsadd_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -993,7 +965,7 @@ define <vscale x 1 x i32> @vsadd_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vsadd_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1003,8 +975,8 @@ define <vscale x 1 x i32> @vsadd_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vs
define <vscale x 1 x i32> @vsadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1015,7 +987,7 @@ define <vscale x 1 x i32> @vsadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vsc
define <vscale x 1 x i32> @vsadd_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
@@ -1027,8 +999,8 @@ define <vscale x 1 x i32> @vsadd_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32
define <vscale x 1 x i32> @vsadd_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1037,7 +1009,7 @@ define <vscale x 1 x i32> @vsadd_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vsadd_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1047,8 +1019,8 @@ define <vscale x 1 x i32> @vsadd_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32
define <vscale x 2 x i32> @vsadd_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1057,7 +1029,7 @@ define <vscale x 2 x i32> @vsadd_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vsadd_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1067,8 +1039,8 @@ define <vscale x 2 x i32> @vsadd_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vs
define <vscale x 2 x i32> @vsadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
@@ -1079,7 +1051,7 @@ define <vscale x 2 x i32> @vsadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vsc
define <vscale x 2 x i32> @vsadd_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
@@ -1091,8 +1063,8 @@ define <vscale x 2 x i32> @vsadd_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32
define <vscale x 2 x i32> @vsadd_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1101,7 +1073,7 @@ define <vscale x 2 x i32> @vsadd_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vsadd_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1111,8 +1083,8 @@ define <vscale x 2 x i32> @vsadd_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32
define <vscale x 4 x i32> @vsadd_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1121,7 +1093,7 @@ define <vscale x 4 x i32> @vsadd_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vsadd_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1131,8 +1103,8 @@ define <vscale x 4 x i32> @vsadd_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vs
define <vscale x 4 x i32> @vsadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
@@ -1143,7 +1115,7 @@ define <vscale x 4 x i32> @vsadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vsc
define <vscale x 4 x i32> @vsadd_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
@@ -1155,8 +1127,8 @@ define <vscale x 4 x i32> @vsadd_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32
define <vscale x 4 x i32> @vsadd_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1165,7 +1137,7 @@ define <vscale x 4 x i32> @vsadd_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vsadd_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1175,8 +1147,8 @@ define <vscale x 4 x i32> @vsadd_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32
define <vscale x 8 x i32> @vsadd_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1185,7 +1157,7 @@ define <vscale x 8 x i32> @vsadd_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vsadd_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1195,8 +1167,8 @@ define <vscale x 8 x i32> @vsadd_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vs
define <vscale x 8 x i32> @vsadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1207,7 +1179,7 @@ define <vscale x 8 x i32> @vsadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vsc
define <vscale x 8 x i32> @vsadd_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
@@ -1219,8 +1191,8 @@ define <vscale x 8 x i32> @vsadd_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32
define <vscale x 8 x i32> @vsadd_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1229,7 +1201,7 @@ define <vscale x 8 x i32> @vsadd_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vsadd_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1239,8 +1211,8 @@ define <vscale x 8 x i32> @vsadd_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32
define <vscale x 16 x i32> @vsadd_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1249,7 +1221,7 @@ define <vscale x 16 x i32> @vsadd_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x
define <vscale x 16 x i32> @vsadd_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -1259,8 +1231,8 @@ define <vscale x 16 x i32> @vsadd_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 16 x i32> @vsadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
@@ -1271,7 +1243,7 @@ define <vscale x 16 x i32> @vsadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <
define <vscale x 16 x i32> @vsadd_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vx_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vsadd.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
@@ -1283,8 +1255,8 @@ define <vscale x 16 x i32> @vsadd_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 16 x i32> @vsadd_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1293,7 +1265,7 @@ define <vscale x 16 x i32> @vsadd_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x
define <vscale x 16 x i32> @vsadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -1305,25 +1277,9 @@ define <vscale x 16 x i32> @vsadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB118_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB118_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i32> @llvm.vp.sadd.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i32> %v
@@ -1332,20 +1288,9 @@ define <vscale x 32 x i32> @vsadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x
define <vscale x 32 x i32> @vsadd_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v16, v16, -1
-; CHECK-NEXT: bltu a0, a1, .LBB119_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB119_2:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
+; CHECK-NEXT: vsadd.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i32> @llvm.vp.sadd.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i32> %v
@@ -1354,8 +1299,8 @@ define <vscale x 32 x i32> @vsadd_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va,
define <vscale x 1 x i64> @vsadd_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1364,7 +1309,7 @@ define <vscale x 1 x i64> @vsadd_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
define <vscale x 1 x i64> @vsadd_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1379,17 +1324,17 @@ define <vscale x 1 x i64> @vsadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsadd_vx_nxv1i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -1405,7 +1350,7 @@ define <vscale x 1 x i64> @vsadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
@@ -1414,7 +1359,7 @@ define <vscale x 1 x i64> @vsadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
;
; RV64-LABEL: vsadd_vx_nxv1i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
@@ -1426,8 +1371,8 @@ define <vscale x 1 x i64> @vsadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
define <vscale x 1 x i64> @vsadd_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1436,7 +1381,7 @@ define <vscale x 1 x i64> @vsadd_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
define <vscale x 1 x i64> @vsadd_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1446,8 +1391,8 @@ define <vscale x 1 x i64> @vsadd_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32
define <vscale x 2 x i64> @vsadd_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1456,7 +1401,7 @@ define <vscale x 2 x i64> @vsadd_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
define <vscale x 2 x i64> @vsadd_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1471,17 +1416,17 @@ define <vscale x 2 x i64> @vsadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsadd_vx_nxv2i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
-; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
@@ -1497,7 +1442,7 @@ define <vscale x 2 x i64> @vsadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
@@ -1506,7 +1451,7 @@ define <vscale x 2 x i64> @vsadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
;
; RV64-LABEL: vsadd_vx_nxv2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
@@ -1518,8 +1463,8 @@ define <vscale x 2 x i64> @vsadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
define <vscale x 2 x i64> @vsadd_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1528,7 +1473,7 @@ define <vscale x 2 x i64> @vsadd_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
define <vscale x 2 x i64> @vsadd_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1538,8 +1483,8 @@ define <vscale x 2 x i64> @vsadd_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
define <vscale x 4 x i64> @vsadd_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1548,7 +1493,7 @@ define <vscale x 4 x i64> @vsadd_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
define <vscale x 4 x i64> @vsadd_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1563,17 +1508,17 @@ define <vscale x 4 x i64> @vsadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsadd_vx_nxv4i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
-; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
@@ -1589,7 +1534,7 @@ define <vscale x 4 x i64> @vsadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
@@ -1598,7 +1543,7 @@ define <vscale x 4 x i64> @vsadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
;
; RV64-LABEL: vsadd_vx_nxv4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
@@ -1610,8 +1555,8 @@ define <vscale x 4 x i64> @vsadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
define <vscale x 4 x i64> @vsadd_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1620,7 +1565,7 @@ define <vscale x 4 x i64> @vsadd_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
define <vscale x 4 x i64> @vsadd_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1630,8 +1575,8 @@ define <vscale x 4 x i64> @vsadd_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
define <vscale x 8 x i64> @vsadd_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1640,7 +1585,7 @@ define <vscale x 8 x i64> @vsadd_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
define <vscale x 8 x i64> @vsadd_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vv_nxv8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1655,17 +1600,17 @@ define <vscale x 8 x i64> @vsadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsadd_vx_nxv8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -1681,7 +1626,7 @@ define <vscale x 8 x i64> @vsadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
@@ -1690,7 +1635,7 @@ define <vscale x 8 x i64> @vsadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64
;
; RV64-LABEL: vsadd_vx_nxv8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsadd.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
@@ -1702,8 +1647,8 @@ define <vscale x 8 x i64> @vsadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64
define <vscale x 8 x i64> @vsadd_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1712,7 +1657,7 @@ define <vscale x 8 x i64> @vsadd_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
define <vscale x 8 x i64> @vsadd_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
index 5750daa21c6e2..9cf6e1fb5ad4d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
@@ -7,13 +7,13 @@
define <vscale x 8 x i7> @vsaddu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv8i7:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 127
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: li a1, 127
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vand.vx v8, v8, a2
-; CHECK-NEXT: vand.vx v9, v9, a2
-; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vminu.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vand.vx v9, v9, a1
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vminu.vx v8, v8, a1
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer
@@ -24,8 +24,8 @@ define <vscale x 8 x i7> @vsaddu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b,
define <vscale x 1 x i8> @vsaddu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -34,7 +34,7 @@ define <vscale x 1 x i8> @vsaddu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x
define <vscale x 1 x i8> @vsaddu_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -44,8 +44,8 @@ define <vscale x 1 x i8> @vsaddu_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vsca
define <vscale x 1 x i8> @vsaddu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -56,8 +56,8 @@ define <vscale x 1 x i8> @vsaddu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale
define <vscale x 1 x i8> @vsaddu_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv1i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -68,7 +68,7 @@ define <vscale x 1 x i8> @vsaddu_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b,
define <vscale x 1 x i8> @vsaddu_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
@@ -80,8 +80,8 @@ define <vscale x 1 x i8> @vsaddu_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b
define <vscale x 1 x i8> @vsaddu_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -90,7 +90,7 @@ define <vscale x 1 x i8> @vsaddu_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x
define <vscale x 1 x i8> @vsaddu_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -100,8 +100,8 @@ define <vscale x 1 x i8> @vsaddu_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 z
define <vscale x 2 x i8> @vsaddu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -110,7 +110,7 @@ define <vscale x 2 x i8> @vsaddu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x
define <vscale x 2 x i8> @vsaddu_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -120,8 +120,8 @@ define <vscale x 2 x i8> @vsaddu_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vsca
define <vscale x 2 x i8> @vsaddu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
@@ -132,7 +132,7 @@ define <vscale x 2 x i8> @vsaddu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale
define <vscale x 2 x i8> @vsaddu_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
@@ -144,8 +144,8 @@ define <vscale x 2 x i8> @vsaddu_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b
define <vscale x 2 x i8> @vsaddu_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -154,7 +154,7 @@ define <vscale x 2 x i8> @vsaddu_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x
define <vscale x 2 x i8> @vsaddu_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -164,8 +164,8 @@ define <vscale x 2 x i8> @vsaddu_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 z
define <vscale x 3 x i8> @vsaddu_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i8> %v
@@ -174,7 +174,7 @@ define <vscale x 3 x i8> @vsaddu_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x
define <vscale x 3 x i8> @vsaddu_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)
@@ -184,8 +184,8 @@ define <vscale x 3 x i8> @vsaddu_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vsca
define <vscale x 3 x i8> @vsaddu_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
@@ -196,7 +196,7 @@ define <vscale x 3 x i8> @vsaddu_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale
define <vscale x 3 x i8> @vsaddu_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
@@ -208,8 +208,8 @@ define <vscale x 3 x i8> @vsaddu_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b
define <vscale x 3 x i8> @vsaddu_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i8> %v
@@ -218,7 +218,7 @@ define <vscale x 3 x i8> @vsaddu_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x
define <vscale x 3 x i8> @vsaddu_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)
@@ -228,8 +228,8 @@ define <vscale x 3 x i8> @vsaddu_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 z
define <vscale x 4 x i8> @vsaddu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -238,7 +238,7 @@ define <vscale x 4 x i8> @vsaddu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x
define <vscale x 4 x i8> @vsaddu_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -248,8 +248,8 @@ define <vscale x 4 x i8> @vsaddu_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vsca
define <vscale x 4 x i8> @vsaddu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
@@ -260,7 +260,7 @@ define <vscale x 4 x i8> @vsaddu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale
define <vscale x 4 x i8> @vsaddu_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
@@ -272,8 +272,8 @@ define <vscale x 4 x i8> @vsaddu_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b
define <vscale x 4 x i8> @vsaddu_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -282,7 +282,7 @@ define <vscale x 4 x i8> @vsaddu_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x
define <vscale x 4 x i8> @vsaddu_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -292,8 +292,8 @@ define <vscale x 4 x i8> @vsaddu_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 z
define <vscale x 8 x i8> @vsaddu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -302,7 +302,7 @@ define <vscale x 8 x i8> @vsaddu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x
define <vscale x 8 x i8> @vsaddu_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -312,8 +312,8 @@ define <vscale x 8 x i8> @vsaddu_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vsca
define <vscale x 8 x i8> @vsaddu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -324,7 +324,7 @@ define <vscale x 8 x i8> @vsaddu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale
define <vscale x 8 x i8> @vsaddu_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
@@ -336,8 +336,8 @@ define <vscale x 8 x i8> @vsaddu_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b
define <vscale x 8 x i8> @vsaddu_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -346,7 +346,7 @@ define <vscale x 8 x i8> @vsaddu_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x
define <vscale x 8 x i8> @vsaddu_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -356,8 +356,8 @@ define <vscale x 8 x i8> @vsaddu_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 z
define <vscale x 16 x i8> @vsaddu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -366,7 +366,7 @@ define <vscale x 16 x i8> @vsaddu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 1
define <vscale x 16 x i8> @vsaddu_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -376,8 +376,8 @@ define <vscale x 16 x i8> @vsaddu_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <v
define <vscale x 16 x i8> @vsaddu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
@@ -388,7 +388,7 @@ define <vscale x 16 x i8> @vsaddu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vsc
define <vscale x 16 x i8> @vsaddu_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
@@ -400,8 +400,8 @@ define <vscale x 16 x i8> @vsaddu_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8
define <vscale x 16 x i8> @vsaddu_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -410,7 +410,7 @@ define <vscale x 16 x i8> @vsaddu_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 1
define <vscale x 16 x i8> @vsaddu_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -420,8 +420,8 @@ define <vscale x 16 x i8> @vsaddu_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i3
define <vscale x 32 x i8> @vsaddu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -430,7 +430,7 @@ define <vscale x 32 x i8> @vsaddu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 3
define <vscale x 32 x i8> @vsaddu_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -440,8 +440,8 @@ define <vscale x 32 x i8> @vsaddu_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <v
define <vscale x 32 x i8> @vsaddu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
@@ -452,7 +452,7 @@ define <vscale x 32 x i8> @vsaddu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vsc
define <vscale x 32 x i8> @vsaddu_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
@@ -464,8 +464,8 @@ define <vscale x 32 x i8> @vsaddu_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8
define <vscale x 32 x i8> @vsaddu_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -474,7 +474,7 @@ define <vscale x 32 x i8> @vsaddu_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 3
define <vscale x 32 x i8> @vsaddu_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -484,8 +484,8 @@ define <vscale x 32 x i8> @vsaddu_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i3
define <vscale x 64 x i8> @vsaddu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -494,7 +494,7 @@ define <vscale x 64 x i8> @vsaddu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 6
define <vscale x 64 x i8> @vsaddu_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)
@@ -504,8 +504,8 @@ define <vscale x 64 x i8> @vsaddu_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <v
define <vscale x 64 x i8> @vsaddu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
@@ -516,7 +516,7 @@ define <vscale x 64 x i8> @vsaddu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vsc
define <vscale x 64 x i8> @vsaddu_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
@@ -528,8 +528,8 @@ define <vscale x 64 x i8> @vsaddu_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8
define <vscale x 64 x i8> @vsaddu_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -538,7 +538,7 @@ define <vscale x 64 x i8> @vsaddu_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 6
define <vscale x 64 x i8> @vsaddu_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)
@@ -550,24 +550,9 @@ define <vscale x 64 x i8> @vsaddu_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i3
define <vscale x 128 x i8> @vsaddu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv128i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
-; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.uadd.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -576,20 +561,9 @@ define <vscale x 128 x i8> @vsaddu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
define <vscale x 128 x i8> @vsaddu_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv128i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1
-; CHECK-NEXT: bltu a0, a1, .LBB51_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB51_2:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.uadd.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)
ret <vscale x 128 x i8> %v
@@ -598,8 +572,8 @@ define <vscale x 128 x i8> @vsaddu_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va,
define <vscale x 1 x i16> @vsaddu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -608,7 +582,7 @@ define <vscale x 1 x i16> @vsaddu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vsaddu_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -618,8 +592,8 @@ define <vscale x 1 x i16> @vsaddu_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <v
define <vscale x 1 x i16> @vsaddu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -630,7 +604,7 @@ define <vscale x 1 x i16> @vsaddu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vs
define <vscale x 1 x i16> @vsaddu_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
@@ -642,8 +616,8 @@ define <vscale x 1 x i16> @vsaddu_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i1
define <vscale x 1 x i16> @vsaddu_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -652,7 +626,7 @@ define <vscale x 1 x i16> @vsaddu_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vsaddu_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -662,8 +636,8 @@ define <vscale x 1 x i16> @vsaddu_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i3
define <vscale x 2 x i16> @vsaddu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -672,7 +646,7 @@ define <vscale x 2 x i16> @vsaddu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vsaddu_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -682,8 +656,8 @@ define <vscale x 2 x i16> @vsaddu_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <v
define <vscale x 2 x i16> @vsaddu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
@@ -694,7 +668,7 @@ define <vscale x 2 x i16> @vsaddu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vs
define <vscale x 2 x i16> @vsaddu_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
@@ -706,8 +680,8 @@ define <vscale x 2 x i16> @vsaddu_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i1
define <vscale x 2 x i16> @vsaddu_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -716,7 +690,7 @@ define <vscale x 2 x i16> @vsaddu_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vsaddu_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -726,8 +700,8 @@ define <vscale x 2 x i16> @vsaddu_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i3
define <vscale x 4 x i16> @vsaddu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -736,7 +710,7 @@ define <vscale x 4 x i16> @vsaddu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vsaddu_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -746,8 +720,8 @@ define <vscale x 4 x i16> @vsaddu_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <v
define <vscale x 4 x i16> @vsaddu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
@@ -758,7 +732,7 @@ define <vscale x 4 x i16> @vsaddu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vs
define <vscale x 4 x i16> @vsaddu_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
@@ -770,8 +744,8 @@ define <vscale x 4 x i16> @vsaddu_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i1
define <vscale x 4 x i16> @vsaddu_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -780,7 +754,7 @@ define <vscale x 4 x i16> @vsaddu_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vsaddu_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -790,8 +764,8 @@ define <vscale x 4 x i16> @vsaddu_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i3
define <vscale x 8 x i16> @vsaddu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -800,7 +774,7 @@ define <vscale x 8 x i16> @vsaddu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vsaddu_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -810,8 +784,8 @@ define <vscale x 8 x i16> @vsaddu_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <v
define <vscale x 8 x i16> @vsaddu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -822,7 +796,7 @@ define <vscale x 8 x i16> @vsaddu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vs
define <vscale x 8 x i16> @vsaddu_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
@@ -834,8 +808,8 @@ define <vscale x 8 x i16> @vsaddu_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i1
define <vscale x 8 x i16> @vsaddu_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -844,7 +818,7 @@ define <vscale x 8 x i16> @vsaddu_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vsaddu_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -854,8 +828,8 @@ define <vscale x 8 x i16> @vsaddu_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i3
define <vscale x 16 x i16> @vsaddu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -864,7 +838,7 @@ define <vscale x 16 x i16> @vsaddu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale
define <vscale x 16 x i16> @vsaddu_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -874,8 +848,8 @@ define <vscale x 16 x i16> @vsaddu_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 16 x i16> @vsaddu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
@@ -886,7 +860,7 @@ define <vscale x 16 x i16> @vsaddu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b,
define <vscale x 16 x i16> @vsaddu_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
@@ -898,8 +872,8 @@ define <vscale x 16 x i16> @vsaddu_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 16 x i16> @vsaddu_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -908,7 +882,7 @@ define <vscale x 16 x i16> @vsaddu_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale
define <vscale x 16 x i16> @vsaddu_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -918,8 +892,8 @@ define <vscale x 16 x i16> @vsaddu_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 32 x i16> @vsaddu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -928,7 +902,7 @@ define <vscale x 32 x i16> @vsaddu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale
define <vscale x 32 x i16> @vsaddu_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -938,8 +912,8 @@ define <vscale x 32 x i16> @vsaddu_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 32 x i16> @vsaddu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
@@ -950,7 +924,7 @@ define <vscale x 32 x i16> @vsaddu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b,
define <vscale x 32 x i16> @vsaddu_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
@@ -962,8 +936,8 @@ define <vscale x 32 x i16> @vsaddu_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 32 x i16> @vsaddu_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -972,7 +946,7 @@ define <vscale x 32 x i16> @vsaddu_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale
define <vscale x 32 x i16> @vsaddu_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -982,8 +956,8 @@ define <vscale x 32 x i16> @vsaddu_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 1 x i32> @vsaddu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -992,7 +966,7 @@ define <vscale x 1 x i32> @vsaddu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vsaddu_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1002,8 +976,8 @@ define <vscale x 1 x i32> @vsaddu_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <v
define <vscale x 1 x i32> @vsaddu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1014,7 +988,7 @@ define <vscale x 1 x i32> @vsaddu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vs
define <vscale x 1 x i32> @vsaddu_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
@@ -1026,8 +1000,8 @@ define <vscale x 1 x i32> @vsaddu_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i3
define <vscale x 1 x i32> @vsaddu_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1036,7 +1010,7 @@ define <vscale x 1 x i32> @vsaddu_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vsaddu_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1046,8 +1020,8 @@ define <vscale x 1 x i32> @vsaddu_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i3
define <vscale x 2 x i32> @vsaddu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1056,7 +1030,7 @@ define <vscale x 2 x i32> @vsaddu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vsaddu_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1066,8 +1040,8 @@ define <vscale x 2 x i32> @vsaddu_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <v
define <vscale x 2 x i32> @vsaddu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
@@ -1078,7 +1052,7 @@ define <vscale x 2 x i32> @vsaddu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vs
define <vscale x 2 x i32> @vsaddu_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
@@ -1090,8 +1064,8 @@ define <vscale x 2 x i32> @vsaddu_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i3
define <vscale x 2 x i32> @vsaddu_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1100,7 +1074,7 @@ define <vscale x 2 x i32> @vsaddu_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vsaddu_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1110,8 +1084,8 @@ define <vscale x 2 x i32> @vsaddu_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i3
define <vscale x 4 x i32> @vsaddu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1120,7 +1094,7 @@ define <vscale x 4 x i32> @vsaddu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vsaddu_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1130,8 +1104,8 @@ define <vscale x 4 x i32> @vsaddu_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <v
define <vscale x 4 x i32> @vsaddu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
@@ -1142,7 +1116,7 @@ define <vscale x 4 x i32> @vsaddu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vs
define <vscale x 4 x i32> @vsaddu_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
@@ -1154,8 +1128,8 @@ define <vscale x 4 x i32> @vsaddu_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i3
define <vscale x 4 x i32> @vsaddu_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1164,7 +1138,7 @@ define <vscale x 4 x i32> @vsaddu_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vsaddu_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1174,8 +1148,8 @@ define <vscale x 4 x i32> @vsaddu_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i3
define <vscale x 8 x i32> @vsaddu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1184,7 +1158,7 @@ define <vscale x 8 x i32> @vsaddu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vsaddu_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1194,8 +1168,8 @@ define <vscale x 8 x i32> @vsaddu_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <v
define <vscale x 8 x i32> @vsaddu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1206,7 +1180,7 @@ define <vscale x 8 x i32> @vsaddu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vs
define <vscale x 8 x i32> @vsaddu_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
@@ -1218,8 +1192,8 @@ define <vscale x 8 x i32> @vsaddu_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i3
define <vscale x 8 x i32> @vsaddu_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1228,7 +1202,7 @@ define <vscale x 8 x i32> @vsaddu_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vsaddu_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1238,8 +1212,8 @@ define <vscale x 8 x i32> @vsaddu_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i3
define <vscale x 16 x i32> @vsaddu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1248,7 +1222,7 @@ define <vscale x 16 x i32> @vsaddu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale
define <vscale x 16 x i32> @vsaddu_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -1258,8 +1232,8 @@ define <vscale x 16 x i32> @vsaddu_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 16 x i32> @vsaddu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
@@ -1270,7 +1244,7 @@ define <vscale x 16 x i32> @vsaddu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b,
define <vscale x 16 x i32> @vsaddu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vx_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vsaddu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
@@ -1282,8 +1256,8 @@ define <vscale x 16 x i32> @vsaddu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 16 x i32> @vsaddu_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1292,7 +1266,7 @@ define <vscale x 16 x i32> @vsaddu_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale
define <vscale x 16 x i32> @vsaddu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -1304,25 +1278,9 @@ define <vscale x 16 x i32> @vsaddu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsaddu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB118_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB118_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i32> @llvm.vp.uadd.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i32> %v
@@ -1331,20 +1289,9 @@ define <vscale x 32 x i32> @vsaddu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale
define <vscale x 32 x i32> @vsaddu_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v16, v16, -1
-; CHECK-NEXT: bltu a0, a1, .LBB119_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB119_2:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
+; CHECK-NEXT: vsaddu.vi v16, v16, -1
; CHECK-NEXT: ret
%v = call <vscale x 32 x i32> @llvm.vp.uadd.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i32> %v
@@ -1353,8 +1300,8 @@ define <vscale x 32 x i32> @vsaddu_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va,
define <vscale x 1 x i64> @vsaddu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1363,7 +1310,7 @@ define <vscale x 1 x i64> @vsaddu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
define <vscale x 1 x i64> @vsaddu_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1378,17 +1325,17 @@ define <vscale x 1 x i64> @vsaddu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsaddu_vx_nxv1i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -1404,7 +1351,7 @@ define <vscale x 1 x i64> @vsaddu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
@@ -1413,7 +1360,7 @@ define <vscale x 1 x i64> @vsaddu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6
;
; RV64-LABEL: vsaddu_vx_nxv1i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
@@ -1425,8 +1372,8 @@ define <vscale x 1 x i64> @vsaddu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6
define <vscale x 1 x i64> @vsaddu_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1435,7 +1382,7 @@ define <vscale x 1 x i64> @vsaddu_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
define <vscale x 1 x i64> @vsaddu_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1445,8 +1392,8 @@ define <vscale x 1 x i64> @vsaddu_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i3
define <vscale x 2 x i64> @vsaddu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1455,7 +1402,7 @@ define <vscale x 2 x i64> @vsaddu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
define <vscale x 2 x i64> @vsaddu_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1470,17 +1417,17 @@ define <vscale x 2 x i64> @vsaddu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vs
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsaddu_vx_nxv2i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
-; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
@@ -1496,7 +1443,7 @@ define <vscale x 2 x i64> @vsaddu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
@@ -1505,7 +1452,7 @@ define <vscale x 2 x i64> @vsaddu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6
;
; RV64-LABEL: vsaddu_vx_nxv2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
@@ -1517,8 +1464,8 @@ define <vscale x 2 x i64> @vsaddu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6
define <vscale x 2 x i64> @vsaddu_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1527,7 +1474,7 @@ define <vscale x 2 x i64> @vsaddu_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
define <vscale x 2 x i64> @vsaddu_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1537,8 +1484,8 @@ define <vscale x 2 x i64> @vsaddu_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i3
define <vscale x 4 x i64> @vsaddu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1547,7 +1494,7 @@ define <vscale x 4 x i64> @vsaddu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
define <vscale x 4 x i64> @vsaddu_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1562,17 +1509,17 @@ define <vscale x 4 x i64> @vsaddu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vs
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsaddu_vx_nxv4i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
-; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
@@ -1588,7 +1535,7 @@ define <vscale x 4 x i64> @vsaddu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
@@ -1597,7 +1544,7 @@ define <vscale x 4 x i64> @vsaddu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6
;
; RV64-LABEL: vsaddu_vx_nxv4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
@@ -1609,8 +1556,8 @@ define <vscale x 4 x i64> @vsaddu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6
define <vscale x 4 x i64> @vsaddu_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1619,7 +1566,7 @@ define <vscale x 4 x i64> @vsaddu_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
define <vscale x 4 x i64> @vsaddu_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1629,8 +1576,8 @@ define <vscale x 4 x i64> @vsaddu_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i3
define <vscale x 8 x i64> @vsaddu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1639,7 +1586,7 @@ define <vscale x 8 x i64> @vsaddu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
define <vscale x 8 x i64> @vsaddu_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vv_nxv8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1654,17 +1601,17 @@ define <vscale x 8 x i64> @vsaddu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsaddu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vsaddu_vx_nxv8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -1680,7 +1627,7 @@ define <vscale x 8 x i64> @vsaddu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
@@ -1689,7 +1636,7 @@ define <vscale x 8 x i64> @vsaddu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6
;
; RV64-LABEL: vsaddu_vx_nxv8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsaddu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
@@ -1701,8 +1648,8 @@ define <vscale x 8 x i64> @vsaddu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6
define <vscale x 8 x i64> @vsaddu_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1711,7 +1658,7 @@ define <vscale x 8 x i64> @vsaddu_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
define <vscale x 8 x i64> @vsaddu_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
index 5b5fe3dd1c10f..c073554601c2e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
@@ -7,14 +7,12 @@
define <vscale x 8 x i7> @vssub_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv8i7:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vadd.vv v9, v9, v9
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: vsra.vi v8, v8, 1
-; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t
-; CHECK-NEXT: li a0, 192
-; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer
@@ -25,8 +23,8 @@ define <vscale x 8 x i7> @vssub_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <
define <vscale x 1 x i8> @vssub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -35,7 +33,7 @@ define <vscale x 1 x i8> @vssub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i
define <vscale x 1 x i8> @vssub_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -45,8 +43,8 @@ define <vscale x 1 x i8> @vssub_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscal
define <vscale x 1 x i8> @vssub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -57,9 +55,9 @@ define <vscale x 1 x i8> @vssub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale
define <vscale x 1 x i8> @vssub_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv1i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vssub.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vssub.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -70,7 +68,7 @@ define <vscale x 1 x i8> @vssub_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b,
define <vscale x 1 x i8> @vssub_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
@@ -82,9 +80,9 @@ define <vscale x 1 x i8> @vssub_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b,
define <vscale x 1 x i8> @vssub_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -93,9 +91,9 @@ define <vscale x 1 x i8> @vssub_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i
define <vscale x 1 x i8> @vssub_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i8> %v
@@ -104,8 +102,8 @@ define <vscale x 1 x i8> @vssub_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 ze
define <vscale x 2 x i8> @vssub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -114,7 +112,7 @@ define <vscale x 2 x i8> @vssub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i
define <vscale x 2 x i8> @vssub_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -124,8 +122,8 @@ define <vscale x 2 x i8> @vssub_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscal
define <vscale x 2 x i8> @vssub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
@@ -136,7 +134,7 @@ define <vscale x 2 x i8> @vssub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale
define <vscale x 2 x i8> @vssub_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
@@ -148,9 +146,9 @@ define <vscale x 2 x i8> @vssub_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b,
define <vscale x 2 x i8> @vssub_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -159,9 +157,9 @@ define <vscale x 2 x i8> @vssub_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i
define <vscale x 2 x i8> @vssub_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i8> %v
@@ -170,8 +168,8 @@ define <vscale x 2 x i8> @vssub_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 ze
define <vscale x 3 x i8> @vssub_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i8> %v
@@ -180,7 +178,7 @@ define <vscale x 3 x i8> @vssub_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i
define <vscale x 3 x i8> @vssub_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)
@@ -190,8 +188,8 @@ define <vscale x 3 x i8> @vssub_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscal
define <vscale x 3 x i8> @vssub_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
@@ -202,7 +200,7 @@ define <vscale x 3 x i8> @vssub_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale
define <vscale x 3 x i8> @vssub_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
@@ -214,9 +212,9 @@ define <vscale x 3 x i8> @vssub_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b,
define <vscale x 3 x i8> @vssub_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i8> %v
@@ -225,9 +223,9 @@ define <vscale x 3 x i8> @vssub_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i
define <vscale x 3 x i8> @vssub_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)
ret <vscale x 3 x i8> %v
@@ -236,8 +234,8 @@ define <vscale x 3 x i8> @vssub_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 ze
define <vscale x 4 x i8> @vssub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -246,7 +244,7 @@ define <vscale x 4 x i8> @vssub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i
define <vscale x 4 x i8> @vssub_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -256,8 +254,8 @@ define <vscale x 4 x i8> @vssub_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscal
define <vscale x 4 x i8> @vssub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
@@ -268,7 +266,7 @@ define <vscale x 4 x i8> @vssub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale
define <vscale x 4 x i8> @vssub_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
@@ -280,9 +278,9 @@ define <vscale x 4 x i8> @vssub_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b,
define <vscale x 4 x i8> @vssub_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -291,9 +289,9 @@ define <vscale x 4 x i8> @vssub_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i
define <vscale x 4 x i8> @vssub_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i8> %v
@@ -302,8 +300,8 @@ define <vscale x 4 x i8> @vssub_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 ze
define <vscale x 8 x i8> @vssub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -312,7 +310,7 @@ define <vscale x 8 x i8> @vssub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i
define <vscale x 8 x i8> @vssub_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -322,8 +320,8 @@ define <vscale x 8 x i8> @vssub_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscal
define <vscale x 8 x i8> @vssub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -334,7 +332,7 @@ define <vscale x 8 x i8> @vssub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale
define <vscale x 8 x i8> @vssub_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
@@ -346,9 +344,9 @@ define <vscale x 8 x i8> @vssub_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b,
define <vscale x 8 x i8> @vssub_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -357,9 +355,9 @@ define <vscale x 8 x i8> @vssub_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i
define <vscale x 8 x i8> @vssub_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i8> %v
@@ -368,8 +366,8 @@ define <vscale x 8 x i8> @vssub_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 ze
define <vscale x 16 x i8> @vssub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -378,7 +376,7 @@ define <vscale x 16 x i8> @vssub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
define <vscale x 16 x i8> @vssub_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -388,8 +386,8 @@ define <vscale x 16 x i8> @vssub_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vs
define <vscale x 16 x i8> @vssub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
@@ -400,7 +398,7 @@ define <vscale x 16 x i8> @vssub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vsca
define <vscale x 16 x i8> @vssub_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
@@ -412,9 +410,9 @@ define <vscale x 16 x i8> @vssub_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8
define <vscale x 16 x i8> @vssub_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -423,9 +421,9 @@ define <vscale x 16 x i8> @vssub_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
define <vscale x 16 x i8> @vssub_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i8> %v
@@ -434,8 +432,8 @@ define <vscale x 16 x i8> @vssub_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32
define <vscale x 32 x i8> @vssub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -444,7 +442,7 @@ define <vscale x 32 x i8> @vssub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
define <vscale x 32 x i8> @vssub_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -454,8 +452,8 @@ define <vscale x 32 x i8> @vssub_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vs
define <vscale x 32 x i8> @vssub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
@@ -466,7 +464,7 @@ define <vscale x 32 x i8> @vssub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vsca
define <vscale x 32 x i8> @vssub_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
@@ -478,9 +476,9 @@ define <vscale x 32 x i8> @vssub_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8
define <vscale x 32 x i8> @vssub_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -489,9 +487,9 @@ define <vscale x 32 x i8> @vssub_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
define <vscale x 32 x i8> @vssub_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i8> %v
@@ -500,8 +498,8 @@ define <vscale x 32 x i8> @vssub_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32
define <vscale x 64 x i8> @vssub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -510,7 +508,7 @@ define <vscale x 64 x i8> @vssub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
define <vscale x 64 x i8> @vssub_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)
@@ -520,8 +518,8 @@ define <vscale x 64 x i8> @vssub_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vs
define <vscale x 64 x i8> @vssub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
@@ -532,7 +530,7 @@ define <vscale x 64 x i8> @vssub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vsca
define <vscale x 64 x i8> @vssub_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
@@ -544,9 +542,9 @@ define <vscale x 64 x i8> @vssub_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8
define <vscale x 64 x i8> @vssub_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -555,9 +553,9 @@ define <vscale x 64 x i8> @vssub_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
define <vscale x 64 x i8> @vssub_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)
ret <vscale x 64 x i8> %v
@@ -568,25 +566,10 @@ define <vscale x 64 x i8> @vssub_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32
define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv128i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
-; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
+; CHECK-NEXT: vssub.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -595,21 +578,10 @@ define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
define <vscale x 128 x i8> @vssub_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv128i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a2
-; CHECK-NEXT: bltu a0, a1, .LBB51_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB51_2:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a2
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
+; CHECK-NEXT: vssub.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)
ret <vscale x 128 x i8> %v
@@ -618,8 +590,8 @@ define <vscale x 128 x i8> @vssub_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va,
define <vscale x 1 x i16> @vssub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -628,7 +600,7 @@ define <vscale x 1 x i16> @vssub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vssub_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -638,8 +610,8 @@ define <vscale x 1 x i16> @vssub_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vs
define <vscale x 1 x i16> @vssub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -650,7 +622,7 @@ define <vscale x 1 x i16> @vssub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vsc
define <vscale x 1 x i16> @vssub_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
@@ -662,9 +634,9 @@ define <vscale x 1 x i16> @vssub_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16
define <vscale x 1 x i16> @vssub_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -673,9 +645,9 @@ define <vscale x 1 x i16> @vssub_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vssub_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i16> %v
@@ -684,8 +656,8 @@ define <vscale x 1 x i16> @vssub_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32
define <vscale x 2 x i16> @vssub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -694,7 +666,7 @@ define <vscale x 2 x i16> @vssub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vssub_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -704,8 +676,8 @@ define <vscale x 2 x i16> @vssub_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vs
define <vscale x 2 x i16> @vssub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
@@ -716,7 +688,7 @@ define <vscale x 2 x i16> @vssub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vsc
define <vscale x 2 x i16> @vssub_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
@@ -728,9 +700,9 @@ define <vscale x 2 x i16> @vssub_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16
define <vscale x 2 x i16> @vssub_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -739,9 +711,9 @@ define <vscale x 2 x i16> @vssub_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vssub_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i16> %v
@@ -750,8 +722,8 @@ define <vscale x 2 x i16> @vssub_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32
define <vscale x 4 x i16> @vssub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -760,7 +732,7 @@ define <vscale x 4 x i16> @vssub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vssub_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -770,8 +742,8 @@ define <vscale x 4 x i16> @vssub_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vs
define <vscale x 4 x i16> @vssub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
@@ -782,7 +754,7 @@ define <vscale x 4 x i16> @vssub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vsc
define <vscale x 4 x i16> @vssub_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
@@ -794,9 +766,9 @@ define <vscale x 4 x i16> @vssub_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16
define <vscale x 4 x i16> @vssub_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -805,9 +777,9 @@ define <vscale x 4 x i16> @vssub_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vssub_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i16> %v
@@ -816,8 +788,8 @@ define <vscale x 4 x i16> @vssub_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32
define <vscale x 8 x i16> @vssub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -826,7 +798,7 @@ define <vscale x 8 x i16> @vssub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vssub_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -836,8 +808,8 @@ define <vscale x 8 x i16> @vssub_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vs
define <vscale x 8 x i16> @vssub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -848,7 +820,7 @@ define <vscale x 8 x i16> @vssub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vsc
define <vscale x 8 x i16> @vssub_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
@@ -860,9 +832,9 @@ define <vscale x 8 x i16> @vssub_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16
define <vscale x 8 x i16> @vssub_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -871,9 +843,9 @@ define <vscale x 8 x i16> @vssub_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vssub_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i16> %v
@@ -882,8 +854,8 @@ define <vscale x 8 x i16> @vssub_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32
define <vscale x 16 x i16> @vssub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -892,7 +864,7 @@ define <vscale x 16 x i16> @vssub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x
define <vscale x 16 x i16> @vssub_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -902,8 +874,8 @@ define <vscale x 16 x i16> @vssub_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 16 x i16> @vssub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
@@ -914,7 +886,7 @@ define <vscale x 16 x i16> @vssub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <
define <vscale x 16 x i16> @vssub_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
@@ -926,9 +898,9 @@ define <vscale x 16 x i16> @vssub_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 16 x i16> @vssub_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -937,9 +909,9 @@ define <vscale x 16 x i16> @vssub_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x
define <vscale x 16 x i16> @vssub_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i16> %v
@@ -948,8 +920,8 @@ define <vscale x 16 x i16> @vssub_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 32 x i16> @vssub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -958,7 +930,7 @@ define <vscale x 32 x i16> @vssub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x
define <vscale x 32 x i16> @vssub_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -968,8 +940,8 @@ define <vscale x 32 x i16> @vssub_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 32 x i16> @vssub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
@@ -980,7 +952,7 @@ define <vscale x 32 x i16> @vssub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <
define <vscale x 32 x i16> @vssub_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
@@ -992,9 +964,9 @@ define <vscale x 32 x i16> @vssub_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 32 x i16> @vssub_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -1003,9 +975,9 @@ define <vscale x 32 x i16> @vssub_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x
define <vscale x 32 x i16> @vssub_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i16> %v
@@ -1014,8 +986,8 @@ define <vscale x 32 x i16> @vssub_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 1 x i32> @vssub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1024,7 +996,7 @@ define <vscale x 1 x i32> @vssub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vssub_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1034,8 +1006,8 @@ define <vscale x 1 x i32> @vssub_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vs
define <vscale x 1 x i32> @vssub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1046,7 +1018,7 @@ define <vscale x 1 x i32> @vssub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vsc
define <vscale x 1 x i32> @vssub_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
@@ -1058,9 +1030,9 @@ define <vscale x 1 x i32> @vssub_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32
define <vscale x 1 x i32> @vssub_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1069,9 +1041,9 @@ define <vscale x 1 x i32> @vssub_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vssub_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1080,8 +1052,8 @@ define <vscale x 1 x i32> @vssub_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32
define <vscale x 2 x i32> @vssub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1090,7 +1062,7 @@ define <vscale x 2 x i32> @vssub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vssub_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1100,8 +1072,8 @@ define <vscale x 2 x i32> @vssub_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vs
define <vscale x 2 x i32> @vssub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
@@ -1112,7 +1084,7 @@ define <vscale x 2 x i32> @vssub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vsc
define <vscale x 2 x i32> @vssub_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
@@ -1124,9 +1096,9 @@ define <vscale x 2 x i32> @vssub_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32
define <vscale x 2 x i32> @vssub_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1135,9 +1107,9 @@ define <vscale x 2 x i32> @vssub_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vssub_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1146,8 +1118,8 @@ define <vscale x 2 x i32> @vssub_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32
define <vscale x 4 x i32> @vssub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1156,7 +1128,7 @@ define <vscale x 4 x i32> @vssub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vssub_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1166,8 +1138,8 @@ define <vscale x 4 x i32> @vssub_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vs
define <vscale x 4 x i32> @vssub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
@@ -1178,7 +1150,7 @@ define <vscale x 4 x i32> @vssub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vsc
define <vscale x 4 x i32> @vssub_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
@@ -1190,9 +1162,9 @@ define <vscale x 4 x i32> @vssub_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32
define <vscale x 4 x i32> @vssub_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1201,9 +1173,9 @@ define <vscale x 4 x i32> @vssub_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vssub_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1212,8 +1184,8 @@ define <vscale x 4 x i32> @vssub_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32
define <vscale x 8 x i32> @vssub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1222,7 +1194,7 @@ define <vscale x 8 x i32> @vssub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vssub_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1232,8 +1204,8 @@ define <vscale x 8 x i32> @vssub_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vs
define <vscale x 8 x i32> @vssub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1244,7 +1216,7 @@ define <vscale x 8 x i32> @vssub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vsc
define <vscale x 8 x i32> @vssub_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
@@ -1256,9 +1228,9 @@ define <vscale x 8 x i32> @vssub_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32
define <vscale x 8 x i32> @vssub_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1267,9 +1239,9 @@ define <vscale x 8 x i32> @vssub_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vssub_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1278,8 +1250,8 @@ define <vscale x 8 x i32> @vssub_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32
define <vscale x 16 x i32> @vssub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1288,7 +1260,7 @@ define <vscale x 16 x i32> @vssub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x
define <vscale x 16 x i32> @vssub_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -1298,8 +1270,8 @@ define <vscale x 16 x i32> @vssub_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 16 x i32> @vssub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
@@ -1310,7 +1282,7 @@ define <vscale x 16 x i32> @vssub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <
define <vscale x 16 x i32> @vssub_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vx_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
@@ -1322,9 +1294,9 @@ define <vscale x 16 x i32> @vssub_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 16 x i32> @vssub_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1333,9 +1305,9 @@ define <vscale x 16 x i32> @vssub_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x
define <vscale x 16 x i32> @vssub_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1346,26 +1318,10 @@ define <vscale x 16 x i32> @vssub_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssub_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB118_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB118_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a2, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
+; CHECK-NEXT: vssub.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i32> @llvm.vp.ssub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i32> %v
@@ -1374,21 +1330,10 @@ define <vscale x 32 x i32> @vssub_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x
define <vscale x 32 x i32> @vssub_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a2
-; CHECK-NEXT: bltu a0, a1, .LBB119_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB119_2:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a2
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
+; CHECK-NEXT: vssub.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i32> @llvm.vp.ssub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i32> %v
@@ -1397,8 +1342,8 @@ define <vscale x 32 x i32> @vssub_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va,
define <vscale x 1 x i64> @vssub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1407,7 +1352,7 @@ define <vscale x 1 x i64> @vssub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
define <vscale x 1 x i64> @vssub_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1422,17 +1367,17 @@ define <vscale x 1 x i64> @vssub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v9, v0.t
+; RV32-NEXT: vssub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssub_vx_nxv1i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT: vssub.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -1448,7 +1393,7 @@ define <vscale x 1 x i64> @vssub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
@@ -1457,7 +1402,7 @@ define <vscale x 1 x i64> @vssub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
;
; RV64-LABEL: vssub_vx_nxv1i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
@@ -1469,9 +1414,9 @@ define <vscale x 1 x i64> @vssub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
define <vscale x 1 x i64> @vssub_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1480,9 +1425,9 @@ define <vscale x 1 x i64> @vssub_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
define <vscale x 1 x i64> @vssub_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1491,8 +1436,8 @@ define <vscale x 1 x i64> @vssub_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32
define <vscale x 2 x i64> @vssub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1501,7 +1446,7 @@ define <vscale x 2 x i64> @vssub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
define <vscale x 2 x i64> @vssub_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1516,17 +1461,17 @@ define <vscale x 2 x i64> @vssub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v10, v0.t
+; RV32-NEXT: vssub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssub_vx_nxv2i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
-; RV64-NEXT: vssub.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
@@ -1542,7 +1487,7 @@ define <vscale x 2 x i64> @vssub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
@@ -1551,7 +1496,7 @@ define <vscale x 2 x i64> @vssub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
;
; RV64-LABEL: vssub_vx_nxv2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
@@ -1563,9 +1508,9 @@ define <vscale x 2 x i64> @vssub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
define <vscale x 2 x i64> @vssub_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1574,9 +1519,9 @@ define <vscale x 2 x i64> @vssub_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
define <vscale x 2 x i64> @vssub_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1585,8 +1530,8 @@ define <vscale x 2 x i64> @vssub_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
define <vscale x 4 x i64> @vssub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1595,7 +1540,7 @@ define <vscale x 4 x i64> @vssub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
define <vscale x 4 x i64> @vssub_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1610,17 +1555,17 @@ define <vscale x 4 x i64> @vssub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vssub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssub_vx_nxv4i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
-; RV64-NEXT: vssub.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
@@ -1636,7 +1581,7 @@ define <vscale x 4 x i64> @vssub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
@@ -1645,7 +1590,7 @@ define <vscale x 4 x i64> @vssub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
;
; RV64-LABEL: vssub_vx_nxv4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
@@ -1657,9 +1602,9 @@ define <vscale x 4 x i64> @vssub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
define <vscale x 4 x i64> @vssub_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1668,9 +1613,9 @@ define <vscale x 4 x i64> @vssub_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
define <vscale x 4 x i64> @vssub_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1679,8 +1624,8 @@ define <vscale x 4 x i64> @vssub_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
define <vscale x 8 x i64> @vssub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1689,7 +1634,7 @@ define <vscale x 8 x i64> @vssub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
define <vscale x 8 x i64> @vssub_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vv_nxv8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1704,17 +1649,17 @@ define <vscale x 8 x i64> @vssub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v16, v0.t
+; RV32-NEXT: vssub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssub_vx_nxv8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vssub.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -1730,7 +1675,7 @@ define <vscale x 8 x i64> @vssub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
@@ -1739,7 +1684,7 @@ define <vscale x 8 x i64> @vssub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64
;
; RV64-LABEL: vssub_vx_nxv8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vssub.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
@@ -1751,9 +1696,9 @@ define <vscale x 8 x i64> @vssub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64
define <vscale x 8 x i64> @vssub_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1762,9 +1707,9 @@ define <vscale x 8 x i64> @vssub_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
define <vscale x 8 x i64> @vssub_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT: vssub.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
index 7807b7ac43460..90bf19c457de6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
@@ -7,12 +7,12 @@
define <vscale x 8 x i7> @vssubu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv8i7:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 127
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: li a1, 127
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vand.vx v8, v8, a2
-; CHECK-NEXT: vand.vx v9, v9, a2
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vand.vx v9, v9, a1
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer
@@ -23,8 +23,8 @@ define <vscale x 8 x i7> @vssubu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b,
define <vscale x 1 x i8> @vssubu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -33,7 +33,7 @@ define <vscale x 1 x i8> @vssubu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x
define <vscale x 1 x i8> @vssubu_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -43,8 +43,8 @@ define <vscale x 1 x i8> @vssubu_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vsca
define <vscale x 1 x i8> @vssubu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -55,9 +55,9 @@ define <vscale x 1 x i8> @vssubu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale
define <vscale x 1 x i8> @vssubu_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv1i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vssubu.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vssubu.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -68,7 +68,7 @@ define <vscale x 1 x i8> @vssubu_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b,
define <vscale x 1 x i8> @vssubu_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
@@ -80,9 +80,9 @@ define <vscale x 1 x i8> @vssubu_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b
define <vscale x 1 x i8> @vssubu_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -91,9 +91,9 @@ define <vscale x 1 x i8> @vssubu_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x
define <vscale x 1 x i8> @vssubu_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i8> %v
@@ -102,8 +102,8 @@ define <vscale x 1 x i8> @vssubu_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 z
define <vscale x 2 x i8> @vssubu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -112,7 +112,7 @@ define <vscale x 2 x i8> @vssubu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x
define <vscale x 2 x i8> @vssubu_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -122,8 +122,8 @@ define <vscale x 2 x i8> @vssubu_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vsca
define <vscale x 2 x i8> @vssubu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
@@ -134,7 +134,7 @@ define <vscale x 2 x i8> @vssubu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale
define <vscale x 2 x i8> @vssubu_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
@@ -146,9 +146,9 @@ define <vscale x 2 x i8> @vssubu_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b
define <vscale x 2 x i8> @vssubu_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -157,9 +157,9 @@ define <vscale x 2 x i8> @vssubu_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x
define <vscale x 2 x i8> @vssubu_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i8> %v
@@ -168,8 +168,8 @@ define <vscale x 2 x i8> @vssubu_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 z
define <vscale x 3 x i8> @vssubu_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i8> %v
@@ -178,7 +178,7 @@ define <vscale x 3 x i8> @vssubu_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x
define <vscale x 3 x i8> @vssubu_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)
@@ -188,8 +188,8 @@ define <vscale x 3 x i8> @vssubu_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vsca
define <vscale x 3 x i8> @vssubu_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
@@ -200,7 +200,7 @@ define <vscale x 3 x i8> @vssubu_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale
define <vscale x 3 x i8> @vssubu_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
@@ -212,9 +212,9 @@ define <vscale x 3 x i8> @vssubu_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b
define <vscale x 3 x i8> @vssubu_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i8> %v
@@ -223,9 +223,9 @@ define <vscale x 3 x i8> @vssubu_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x
define <vscale x 3 x i8> @vssubu_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv3i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)
ret <vscale x 3 x i8> %v
@@ -234,8 +234,8 @@ define <vscale x 3 x i8> @vssubu_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 z
define <vscale x 4 x i8> @vssubu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -244,7 +244,7 @@ define <vscale x 4 x i8> @vssubu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x
define <vscale x 4 x i8> @vssubu_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -254,8 +254,8 @@ define <vscale x 4 x i8> @vssubu_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vsca
define <vscale x 4 x i8> @vssubu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
@@ -266,7 +266,7 @@ define <vscale x 4 x i8> @vssubu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale
define <vscale x 4 x i8> @vssubu_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
@@ -278,9 +278,9 @@ define <vscale x 4 x i8> @vssubu_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b
define <vscale x 4 x i8> @vssubu_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -289,9 +289,9 @@ define <vscale x 4 x i8> @vssubu_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x
define <vscale x 4 x i8> @vssubu_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i8> %v
@@ -300,8 +300,8 @@ define <vscale x 4 x i8> @vssubu_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 z
define <vscale x 8 x i8> @vssubu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -310,7 +310,7 @@ define <vscale x 8 x i8> @vssubu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x
define <vscale x 8 x i8> @vssubu_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -320,8 +320,8 @@ define <vscale x 8 x i8> @vssubu_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vsca
define <vscale x 8 x i8> @vssubu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -332,7 +332,7 @@ define <vscale x 8 x i8> @vssubu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale
define <vscale x 8 x i8> @vssubu_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
@@ -344,9 +344,9 @@ define <vscale x 8 x i8> @vssubu_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b
define <vscale x 8 x i8> @vssubu_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -355,9 +355,9 @@ define <vscale x 8 x i8> @vssubu_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x
define <vscale x 8 x i8> @vssubu_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i8> %v
@@ -366,8 +366,8 @@ define <vscale x 8 x i8> @vssubu_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 z
define <vscale x 16 x i8> @vssubu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -376,7 +376,7 @@ define <vscale x 16 x i8> @vssubu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 1
define <vscale x 16 x i8> @vssubu_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -386,8 +386,8 @@ define <vscale x 16 x i8> @vssubu_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <v
define <vscale x 16 x i8> @vssubu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
@@ -398,7 +398,7 @@ define <vscale x 16 x i8> @vssubu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vsc
define <vscale x 16 x i8> @vssubu_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
@@ -410,9 +410,9 @@ define <vscale x 16 x i8> @vssubu_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8
define <vscale x 16 x i8> @vssubu_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -421,9 +421,9 @@ define <vscale x 16 x i8> @vssubu_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 1
define <vscale x 16 x i8> @vssubu_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i8> %v
@@ -432,8 +432,8 @@ define <vscale x 16 x i8> @vssubu_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i3
define <vscale x 32 x i8> @vssubu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -442,7 +442,7 @@ define <vscale x 32 x i8> @vssubu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 3
define <vscale x 32 x i8> @vssubu_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -452,8 +452,8 @@ define <vscale x 32 x i8> @vssubu_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <v
define <vscale x 32 x i8> @vssubu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
@@ -464,7 +464,7 @@ define <vscale x 32 x i8> @vssubu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vsc
define <vscale x 32 x i8> @vssubu_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
@@ -476,9 +476,9 @@ define <vscale x 32 x i8> @vssubu_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8
define <vscale x 32 x i8> @vssubu_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -487,9 +487,9 @@ define <vscale x 32 x i8> @vssubu_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 3
define <vscale x 32 x i8> @vssubu_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i8> %v
@@ -498,8 +498,8 @@ define <vscale x 32 x i8> @vssubu_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i3
define <vscale x 64 x i8> @vssubu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -508,7 +508,7 @@ define <vscale x 64 x i8> @vssubu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 6
define <vscale x 64 x i8> @vssubu_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)
@@ -518,8 +518,8 @@ define <vscale x 64 x i8> @vssubu_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <v
define <vscale x 64 x i8> @vssubu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
@@ -530,7 +530,7 @@ define <vscale x 64 x i8> @vssubu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vsc
define <vscale x 64 x i8> @vssubu_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
@@ -542,9 +542,9 @@ define <vscale x 64 x i8> @vssubu_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8
define <vscale x 64 x i8> @vssubu_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -553,9 +553,9 @@ define <vscale x 64 x i8> @vssubu_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 6
define <vscale x 64 x i8> @vssubu_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)
ret <vscale x 64 x i8> %v
@@ -566,25 +566,10 @@ define <vscale x 64 x i8> @vssubu_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i3
define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv128i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
-; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
+; CHECK-NEXT: vssubu.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -593,21 +578,10 @@ define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
define <vscale x 128 x i8> @vssubu_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv128i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a2
-; CHECK-NEXT: bltu a0, a1, .LBB51_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB51_2:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a2
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
+; CHECK-NEXT: vssubu.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)
ret <vscale x 128 x i8> %v
@@ -616,8 +590,8 @@ define <vscale x 128 x i8> @vssubu_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va,
define <vscale x 1 x i16> @vssubu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -626,7 +600,7 @@ define <vscale x 1 x i16> @vssubu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vssubu_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -636,8 +610,8 @@ define <vscale x 1 x i16> @vssubu_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <v
define <vscale x 1 x i16> @vssubu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -648,7 +622,7 @@ define <vscale x 1 x i16> @vssubu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vs
define <vscale x 1 x i16> @vssubu_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
@@ -660,9 +634,9 @@ define <vscale x 1 x i16> @vssubu_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i1
define <vscale x 1 x i16> @vssubu_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -671,9 +645,9 @@ define <vscale x 1 x i16> @vssubu_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vssubu_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i16> %v
@@ -682,8 +656,8 @@ define <vscale x 1 x i16> @vssubu_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i3
define <vscale x 2 x i16> @vssubu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -692,7 +666,7 @@ define <vscale x 2 x i16> @vssubu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vssubu_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -702,8 +676,8 @@ define <vscale x 2 x i16> @vssubu_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <v
define <vscale x 2 x i16> @vssubu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
@@ -714,7 +688,7 @@ define <vscale x 2 x i16> @vssubu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vs
define <vscale x 2 x i16> @vssubu_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
@@ -726,9 +700,9 @@ define <vscale x 2 x i16> @vssubu_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i1
define <vscale x 2 x i16> @vssubu_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -737,9 +711,9 @@ define <vscale x 2 x i16> @vssubu_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vssubu_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i16> %v
@@ -748,8 +722,8 @@ define <vscale x 2 x i16> @vssubu_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i3
define <vscale x 4 x i16> @vssubu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -758,7 +732,7 @@ define <vscale x 4 x i16> @vssubu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vssubu_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -768,8 +742,8 @@ define <vscale x 4 x i16> @vssubu_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <v
define <vscale x 4 x i16> @vssubu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
@@ -780,7 +754,7 @@ define <vscale x 4 x i16> @vssubu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vs
define <vscale x 4 x i16> @vssubu_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
@@ -792,9 +766,9 @@ define <vscale x 4 x i16> @vssubu_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i1
define <vscale x 4 x i16> @vssubu_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -803,9 +777,9 @@ define <vscale x 4 x i16> @vssubu_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vssubu_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i16> %v
@@ -814,8 +788,8 @@ define <vscale x 4 x i16> @vssubu_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i3
define <vscale x 8 x i16> @vssubu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -824,7 +798,7 @@ define <vscale x 8 x i16> @vssubu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vssubu_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -834,8 +808,8 @@ define <vscale x 8 x i16> @vssubu_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <v
define <vscale x 8 x i16> @vssubu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -846,7 +820,7 @@ define <vscale x 8 x i16> @vssubu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vs
define <vscale x 8 x i16> @vssubu_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
@@ -858,9 +832,9 @@ define <vscale x 8 x i16> @vssubu_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i1
define <vscale x 8 x i16> @vssubu_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -869,9 +843,9 @@ define <vscale x 8 x i16> @vssubu_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vssubu_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i16> %v
@@ -880,8 +854,8 @@ define <vscale x 8 x i16> @vssubu_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i3
define <vscale x 16 x i16> @vssubu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -890,7 +864,7 @@ define <vscale x 16 x i16> @vssubu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale
define <vscale x 16 x i16> @vssubu_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -900,8 +874,8 @@ define <vscale x 16 x i16> @vssubu_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 16 x i16> @vssubu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
@@ -912,7 +886,7 @@ define <vscale x 16 x i16> @vssubu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b,
define <vscale x 16 x i16> @vssubu_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
@@ -924,9 +898,9 @@ define <vscale x 16 x i16> @vssubu_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 16 x i16> @vssubu_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -935,9 +909,9 @@ define <vscale x 16 x i16> @vssubu_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale
define <vscale x 16 x i16> @vssubu_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i16> %v
@@ -946,8 +920,8 @@ define <vscale x 16 x i16> @vssubu_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 32 x i16> @vssubu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -956,7 +930,7 @@ define <vscale x 32 x i16> @vssubu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale
define <vscale x 32 x i16> @vssubu_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -966,8 +940,8 @@ define <vscale x 32 x i16> @vssubu_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 32 x i16> @vssubu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
@@ -978,7 +952,7 @@ define <vscale x 32 x i16> @vssubu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b,
define <vscale x 32 x i16> @vssubu_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
@@ -990,9 +964,9 @@ define <vscale x 32 x i16> @vssubu_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 32 x i16> @vssubu_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -1001,9 +975,9 @@ define <vscale x 32 x i16> @vssubu_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale
define <vscale x 32 x i16> @vssubu_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i16> %v
@@ -1012,8 +986,8 @@ define <vscale x 32 x i16> @vssubu_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 1 x i32> @vssubu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1022,7 +996,7 @@ define <vscale x 1 x i32> @vssubu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vssubu_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1032,8 +1006,8 @@ define <vscale x 1 x i32> @vssubu_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <v
define <vscale x 1 x i32> @vssubu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1044,7 +1018,7 @@ define <vscale x 1 x i32> @vssubu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vs
define <vscale x 1 x i32> @vssubu_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
@@ -1056,9 +1030,9 @@ define <vscale x 1 x i32> @vssubu_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i3
define <vscale x 1 x i32> @vssubu_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1067,9 +1041,9 @@ define <vscale x 1 x i32> @vssubu_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vssubu_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i32> %v
@@ -1078,8 +1052,8 @@ define <vscale x 1 x i32> @vssubu_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i3
define <vscale x 2 x i32> @vssubu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1088,7 +1062,7 @@ define <vscale x 2 x i32> @vssubu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vssubu_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1098,8 +1072,8 @@ define <vscale x 2 x i32> @vssubu_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <v
define <vscale x 2 x i32> @vssubu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
@@ -1110,7 +1084,7 @@ define <vscale x 2 x i32> @vssubu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vs
define <vscale x 2 x i32> @vssubu_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
@@ -1122,9 +1096,9 @@ define <vscale x 2 x i32> @vssubu_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i3
define <vscale x 2 x i32> @vssubu_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1133,9 +1107,9 @@ define <vscale x 2 x i32> @vssubu_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vssubu_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1144,8 +1118,8 @@ define <vscale x 2 x i32> @vssubu_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i3
define <vscale x 4 x i32> @vssubu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1154,7 +1128,7 @@ define <vscale x 4 x i32> @vssubu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vssubu_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1164,8 +1138,8 @@ define <vscale x 4 x i32> @vssubu_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <v
define <vscale x 4 x i32> @vssubu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
@@ -1176,7 +1150,7 @@ define <vscale x 4 x i32> @vssubu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vs
define <vscale x 4 x i32> @vssubu_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
@@ -1188,9 +1162,9 @@ define <vscale x 4 x i32> @vssubu_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i3
define <vscale x 4 x i32> @vssubu_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1199,9 +1173,9 @@ define <vscale x 4 x i32> @vssubu_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vssubu_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1210,8 +1184,8 @@ define <vscale x 4 x i32> @vssubu_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i3
define <vscale x 8 x i32> @vssubu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1220,7 +1194,7 @@ define <vscale x 8 x i32> @vssubu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vssubu_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1230,8 +1204,8 @@ define <vscale x 8 x i32> @vssubu_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <v
define <vscale x 8 x i32> @vssubu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1242,7 +1216,7 @@ define <vscale x 8 x i32> @vssubu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vs
define <vscale x 8 x i32> @vssubu_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
@@ -1254,9 +1228,9 @@ define <vscale x 8 x i32> @vssubu_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i3
define <vscale x 8 x i32> @vssubu_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1265,9 +1239,9 @@ define <vscale x 8 x i32> @vssubu_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vssubu_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1276,8 +1250,8 @@ define <vscale x 8 x i32> @vssubu_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i3
define <vscale x 16 x i32> @vssubu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1286,7 +1260,7 @@ define <vscale x 16 x i32> @vssubu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale
define <vscale x 16 x i32> @vssubu_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -1296,8 +1270,8 @@ define <vscale x 16 x i32> @vssubu_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 16 x i32> @vssubu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
@@ -1308,7 +1282,7 @@ define <vscale x 16 x i32> @vssubu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b,
define <vscale x 16 x i32> @vssubu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vx_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
@@ -1320,9 +1294,9 @@ define <vscale x 16 x i32> @vssubu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 16 x i32> @vssubu_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1331,9 +1305,9 @@ define <vscale x 16 x i32> @vssubu_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale
define <vscale x 16 x i32> @vssubu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1344,26 +1318,10 @@ define <vscale x 16 x i32> @vssubu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssubu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB118_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB118_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
+; CHECK-NEXT: vssubu.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i32> @llvm.vp.usub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i32> %v
@@ -1372,21 +1330,10 @@ define <vscale x 32 x i32> @vssubu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale
define <vscale x 32 x i32> @vssubu_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a2
-; CHECK-NEXT: bltu a0, a1, .LBB119_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB119_2:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a2
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
+; CHECK-NEXT: vssubu.vx v16, v16, a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i32> @llvm.vp.usub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)
ret <vscale x 32 x i32> %v
@@ -1395,8 +1342,8 @@ define <vscale x 32 x i32> @vssubu_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va,
define <vscale x 1 x i64> @vssubu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1405,7 +1352,7 @@ define <vscale x 1 x i64> @vssubu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
define <vscale x 1 x i64> @vssubu_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1420,17 +1367,17 @@ define <vscale x 1 x i64> @vssubu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v9, v0.t
+; RV32-NEXT: vssubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssubu_vx_nxv1i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
-; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -1446,7 +1393,7 @@ define <vscale x 1 x i64> @vssubu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
@@ -1455,7 +1402,7 @@ define <vscale x 1 x i64> @vssubu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6
;
; RV64-LABEL: vssubu_vx_nxv1i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
@@ -1467,9 +1414,9 @@ define <vscale x 1 x i64> @vssubu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6
define <vscale x 1 x i64> @vssubu_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1478,9 +1425,9 @@ define <vscale x 1 x i64> @vssubu_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
define <vscale x 1 x i64> @vssubu_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1489,8 +1436,8 @@ define <vscale x 1 x i64> @vssubu_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i3
define <vscale x 2 x i64> @vssubu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1499,7 +1446,7 @@ define <vscale x 2 x i64> @vssubu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
define <vscale x 2 x i64> @vssubu_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1514,17 +1461,17 @@ define <vscale x 2 x i64> @vssubu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vs
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v10, v0.t
+; RV32-NEXT: vssubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssubu_vx_nxv2i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
-; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
@@ -1540,7 +1487,7 @@ define <vscale x 2 x i64> @vssubu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
@@ -1549,7 +1496,7 @@ define <vscale x 2 x i64> @vssubu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6
;
; RV64-LABEL: vssubu_vx_nxv2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
@@ -1561,9 +1508,9 @@ define <vscale x 2 x i64> @vssubu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6
define <vscale x 2 x i64> @vssubu_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1572,9 +1519,9 @@ define <vscale x 2 x i64> @vssubu_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
define <vscale x 2 x i64> @vssubu_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1583,8 +1530,8 @@ define <vscale x 2 x i64> @vssubu_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i3
define <vscale x 4 x i64> @vssubu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1593,7 +1540,7 @@ define <vscale x 4 x i64> @vssubu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
define <vscale x 4 x i64> @vssubu_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1608,17 +1555,17 @@ define <vscale x 4 x i64> @vssubu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vs
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v12, v0.t
+; RV32-NEXT: vssubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssubu_vx_nxv4i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
-; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
@@ -1634,7 +1581,7 @@ define <vscale x 4 x i64> @vssubu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
@@ -1643,7 +1590,7 @@ define <vscale x 4 x i64> @vssubu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6
;
; RV64-LABEL: vssubu_vx_nxv4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
@@ -1655,9 +1602,9 @@ define <vscale x 4 x i64> @vssubu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6
define <vscale x 4 x i64> @vssubu_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1666,9 +1613,9 @@ define <vscale x 4 x i64> @vssubu_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
define <vscale x 4 x i64> @vssubu_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv4i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)
ret <vscale x 4 x i64> %v
@@ -1677,8 +1624,8 @@ define <vscale x 4 x i64> @vssubu_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i3
define <vscale x 8 x i64> @vssubu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1687,7 +1634,7 @@ define <vscale x 8 x i64> @vssubu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
define <vscale x 8 x i64> @vssubu_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vv_nxv8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1702,17 +1649,17 @@ define <vscale x 8 x i64> @vssubu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v16, v0.t
+; RV32-NEXT: vssubu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vssubu_vx_nxv8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -1728,7 +1675,7 @@ define <vscale x 8 x i64> @vssubu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16
@@ -1737,7 +1684,7 @@ define <vscale x 8 x i64> @vssubu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6
;
; RV64-LABEL: vssubu_vx_nxv8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
@@ -1749,9 +1696,9 @@ define <vscale x 8 x i64> @vssubu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6
define <vscale x 8 x i64> @vssubu_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1760,9 +1707,9 @@ define <vscale x 8 x i64> @vssubu_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
define <vscale x 8 x i64> @vssubu_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv8i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a1
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)
ret <vscale x 8 x i64> %v
>From af7e92390dce894418860cec31b70f7cd0329020 Mon Sep 17 00:00:00 2001
From: Amit Tiwari <amtiwari at amd.com>
Date: Mon, 13 Apr 2026 12:39:40 +0530
Subject: [PATCH 17/36] [Clang][OpenMP] Implement Loop splitting `#pragma omp
split` directive (#190397)
Implement Loop-splitting #pragma omp split construct with counts clause.
Posting this PR after the revert of PR
([#183261](https://github.com/llvm/llvm-project/pull/183261))
Changes:
1. Added `openmp/runtime/test/transform/split/lit.local.cfg`
2. Enforced ICE for `counts` clause items in `SemaOpenMP.cpp` (minor
change)
3. Updated tests `split_messages.cpp`, `split_omp_fill.cpp`,
`split_diag_errors.c`.
4. Removed `nonconstant_count.cpp`
---
clang/bindings/python/clang/cindex.py | 3 +
clang/include/clang-c/Index.h | 4 +
clang/include/clang/AST/OpenMPClause.h | 101 +
clang/include/clang/AST/RecursiveASTVisitor.h | 10 +
clang/include/clang/AST/StmtOpenMP.h | 78 +
clang/include/clang/ASTMatchers/ASTMatchers.h | 20 +
.../clang/Basic/DiagnosticSemaKinds.td | 2 +
clang/include/clang/Basic/StmtNodes.td | 1 +
clang/include/clang/Parse/Parser.h | 3 +
clang/include/clang/Sema/SemaOpenMP.h | 12 +
.../include/clang/Serialization/ASTBitCodes.h | 1 +
clang/lib/AST/OpenMPClause.cpp | 35 +
clang/lib/AST/StmtOpenMP.cpp | 21 +
clang/lib/AST/StmtPrinter.cpp | 5 +
clang/lib/AST/StmtProfile.cpp | 10 +
clang/lib/ASTMatchers/ASTMatchersInternal.cpp | 4 +
clang/lib/ASTMatchers/Dynamic/Registry.cpp | 2 +
clang/lib/Basic/OpenMPKinds.cpp | 5 +-
clang/lib/CodeGen/CGStmt.cpp | 3 +
clang/lib/CodeGen/CGStmtOpenMP.cpp | 8 +
clang/lib/CodeGen/CodeGenFunction.h | 1 +
clang/lib/Parse/ParseOpenMP.cpp | 59 +
clang/lib/Sema/SemaExceptionSpec.cpp | 1 +
clang/lib/Sema/SemaOpenMP.cpp | 271 +++
clang/lib/Sema/TreeTransform.h | 44 +
clang/lib/Serialization/ASTReader.cpp | 15 +
clang/lib/Serialization/ASTReaderStmt.cpp | 11 +
clang/lib/Serialization/ASTWriter.cpp | 11 +
clang/lib/Serialization/ASTWriterStmt.cpp | 5 +
clang/lib/StaticAnalyzer/Core/ExprEngine.cpp | 1 +
clang/test/AST/ast-dump-openmp-split.c | 19 +
clang/test/Analysis/split_analyze.c | 11 +
clang/test/Index/openmp-split.c | 11 +
clang/test/OpenMP/split_ast_print.cpp | 71 +
clang/test/OpenMP/split_codegen.cpp | 1986 +++++++++++++++++
clang/test/OpenMP/split_composition.cpp | 17 +
.../test/OpenMP/split_compound_associated.cpp | 13 +
clang/test/OpenMP/split_counts_constexpr.cpp | 19 +
clang/test/OpenMP/split_counts_ice.c | 56 +
clang/test/OpenMP/split_counts_verify.c | 123 +
clang/test/OpenMP/split_diag_errors.c | 61 +
.../OpenMP/split_distribute_inner_split.cpp | 14 +
clang/test/OpenMP/split_driver_smoke.c | 12 +
clang/test/OpenMP/split_iv_types.c | 24 +
clang/test/OpenMP/split_loop_styles.cpp | 14 +
clang/test/OpenMP/split_member_ctor.cpp | 20 +
clang/test/OpenMP/split_messages.cpp | 108 +
clang/test/OpenMP/split_nested_outer_only.c | 12 +
clang/test/OpenMP/split_offload_codegen.cpp | 27 +
clang/test/OpenMP/split_omp_fill.c | 36 +
clang/test/OpenMP/split_openmp_version.cpp | 22 +
clang/test/OpenMP/split_opts_simd_debug.cpp | 30 +
clang/test/OpenMP/split_parallel_split.cpp | 15 +
clang/test/OpenMP/split_pch_codegen.cpp | 43 +
clang/test/OpenMP/split_range_for_diag.cpp | 25 +
clang/test/OpenMP/split_serialize_module.cpp | 24 +
clang/test/OpenMP/split_teams_nesting.cpp | 13 +
clang/test/OpenMP/split_template_nttp.cpp | 15 +
clang/test/OpenMP/split_templates.cpp | 30 +
clang/test/OpenMP/split_trip_volatile.c | 14 +
clang/tools/libclang/CIndex.cpp | 7 +
clang/tools/libclang/CXCursor.cpp | 3 +
.../ASTMatchers/ASTMatchersNodeTest.cpp | 62 +
clang/unittests/ASTMatchers/ASTMatchersTest.h | 14 +
llvm/include/llvm/Frontend/OpenMP/OMP.td | 21 +-
.../runtime/test/transform/split/fill_first.c | 23 +
.../runtime/test/transform/split/foreach.cpp | 24 +
openmp/runtime/test/transform/split/intfor.c | 26 +
.../test/transform/split/intfor_negstart.c | 27 +
.../runtime/test/transform/split/iterfor.cpp | 139 ++
.../runtime/test/transform/split/leq_bound.c | 22 +
.../test/transform/split/lit.local.cfg | 5 +
.../test/transform/split/negative_incr.c | 22 +
.../test/transform/split/nonconstant_incr.c | 22 +
.../transform/split/parallel-split-intfor.c | 27 +
.../test/transform/split/single_fill.c | 23 +
.../test/transform/split/three_segments.c | 26 +
.../runtime/test/transform/split/trip_one.c | 32 +
.../test/transform/split/unsigned_iv.c | 24 +
.../test/transform/split/zero_first_segment.c | 21 +
80 files changed, 4191 insertions(+), 11 deletions(-)
create mode 100644 clang/test/AST/ast-dump-openmp-split.c
create mode 100644 clang/test/Analysis/split_analyze.c
create mode 100644 clang/test/Index/openmp-split.c
create mode 100644 clang/test/OpenMP/split_ast_print.cpp
create mode 100644 clang/test/OpenMP/split_codegen.cpp
create mode 100644 clang/test/OpenMP/split_composition.cpp
create mode 100644 clang/test/OpenMP/split_compound_associated.cpp
create mode 100644 clang/test/OpenMP/split_counts_constexpr.cpp
create mode 100644 clang/test/OpenMP/split_counts_ice.c
create mode 100644 clang/test/OpenMP/split_counts_verify.c
create mode 100644 clang/test/OpenMP/split_diag_errors.c
create mode 100644 clang/test/OpenMP/split_distribute_inner_split.cpp
create mode 100644 clang/test/OpenMP/split_driver_smoke.c
create mode 100644 clang/test/OpenMP/split_iv_types.c
create mode 100644 clang/test/OpenMP/split_loop_styles.cpp
create mode 100644 clang/test/OpenMP/split_member_ctor.cpp
create mode 100644 clang/test/OpenMP/split_messages.cpp
create mode 100644 clang/test/OpenMP/split_nested_outer_only.c
create mode 100644 clang/test/OpenMP/split_offload_codegen.cpp
create mode 100644 clang/test/OpenMP/split_omp_fill.c
create mode 100644 clang/test/OpenMP/split_openmp_version.cpp
create mode 100644 clang/test/OpenMP/split_opts_simd_debug.cpp
create mode 100644 clang/test/OpenMP/split_parallel_split.cpp
create mode 100644 clang/test/OpenMP/split_pch_codegen.cpp
create mode 100644 clang/test/OpenMP/split_range_for_diag.cpp
create mode 100644 clang/test/OpenMP/split_serialize_module.cpp
create mode 100644 clang/test/OpenMP/split_teams_nesting.cpp
create mode 100644 clang/test/OpenMP/split_template_nttp.cpp
create mode 100644 clang/test/OpenMP/split_templates.cpp
create mode 100644 clang/test/OpenMP/split_trip_volatile.c
create mode 100644 openmp/runtime/test/transform/split/fill_first.c
create mode 100644 openmp/runtime/test/transform/split/foreach.cpp
create mode 100644 openmp/runtime/test/transform/split/intfor.c
create mode 100644 openmp/runtime/test/transform/split/intfor_negstart.c
create mode 100644 openmp/runtime/test/transform/split/iterfor.cpp
create mode 100644 openmp/runtime/test/transform/split/leq_bound.c
create mode 100644 openmp/runtime/test/transform/split/lit.local.cfg
create mode 100644 openmp/runtime/test/transform/split/negative_incr.c
create mode 100644 openmp/runtime/test/transform/split/nonconstant_incr.c
create mode 100644 openmp/runtime/test/transform/split/parallel-split-intfor.c
create mode 100644 openmp/runtime/test/transform/split/single_fill.c
create mode 100644 openmp/runtime/test/transform/split/three_segments.c
create mode 100644 openmp/runtime/test/transform/split/trip_one.c
create mode 100644 openmp/runtime/test/transform/split/unsigned_iv.c
create mode 100644 openmp/runtime/test/transform/split/zero_first_segment.c
diff --git a/clang/bindings/python/clang/cindex.py b/clang/bindings/python/clang/cindex.py
index b71f9ed2275e0..a90d48cf6d481 100644
--- a/clang/bindings/python/clang/cindex.py
+++ b/clang/bindings/python/clang/cindex.py
@@ -1453,6 +1453,9 @@ def is_unexposed(self):
# OpenMP fuse directive.
OMP_FUSE_DIRECTIVE = 311
+ # OpenMP split directive.
+ OMP_SPLIT_DIRECTIVE = 312
+
# OpenACC Compute Construct.
OPEN_ACC_COMPUTE_DIRECTIVE = 320
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index dcf1f4f1b4258..119bd68ff9814 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -2166,6 +2166,10 @@ enum CXCursorKind {
*/
CXCursor_OMPFuseDirective = 311,
+ /** OpenMP split directive.
+ */
+ CXCursor_OMPSplitDirective = 312,
+
/** OpenACC Compute Construct.
*/
CXCursor_OpenACCComputeConstruct = 320,
diff --git a/clang/include/clang/AST/OpenMPClause.h b/clang/include/clang/AST/OpenMPClause.h
index af5d3f4698eda..ccf2c40bc5efa 100644
--- a/clang/include/clang/AST/OpenMPClause.h
+++ b/clang/include/clang/AST/OpenMPClause.h
@@ -39,6 +39,7 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/TrailingObjects.h"
#include <cassert>
+#include <climits>
#include <cstddef>
#include <iterator>
#include <utility>
@@ -1023,6 +1024,106 @@ class OMPSizesClause final
}
};
+/// This represents the 'counts' clause in the '#pragma omp split' directive.
+///
+/// \code
+/// #pragma omp split counts(3, omp_fill, 2)
+/// for (int i = 0; i < n; ++i) { ... }
+/// \endcode
+class OMPCountsClause final
+ : public OMPClause,
+ private llvm::TrailingObjects<OMPCountsClause, Expr *> {
+ friend class OMPClauseReader;
+ friend class llvm::TrailingObjects<OMPCountsClause, Expr *>;
+
+ /// Location of '('.
+ SourceLocation LParenLoc;
+
+ /// Number of count expressions in the clause.
+ unsigned NumCounts = 0;
+
+ /// 0-based index of the omp_fill list item.
+ std::optional<unsigned> OmpFillIndex;
+
+ /// Source location of the omp_fill keyword.
+ SourceLocation OmpFillLoc;
+
+ /// Build an empty clause.
+ explicit OMPCountsClause(int NumCounts)
+ : OMPClause(llvm::omp::OMPC_counts, SourceLocation(), SourceLocation()),
+ NumCounts(NumCounts) {}
+
+ /// Sets the location of '('.
+ void setLParenLoc(SourceLocation Loc) { LParenLoc = Loc; }
+ void setOmpFillIndex(std::optional<unsigned> Idx) { OmpFillIndex = Idx; }
+ void setOmpFillLoc(SourceLocation Loc) { OmpFillLoc = Loc; }
+
+ /// Sets the count expressions.
+ void setCountsRefs(ArrayRef<Expr *> VL) {
+ assert(VL.size() == NumCounts);
+ llvm::copy(VL, getCountsRefs().begin());
+ }
+
+public:
+ /// Build a 'counts' AST node.
+ ///
+ /// \param C Context of the AST.
+ /// \param StartLoc Location of the 'counts' identifier.
+ /// \param LParenLoc Location of '('.
+ /// \param EndLoc Location of ')'.
+ /// \param Counts Content of the clause.
+ static OMPCountsClause *Create(const ASTContext &C, SourceLocation StartLoc,
+ SourceLocation LParenLoc,
+ SourceLocation EndLoc, ArrayRef<Expr *> Counts,
+ std::optional<unsigned> FillIdx,
+ SourceLocation FillLoc);
+
+ /// Build an empty 'counts' AST node for deserialization.
+ ///
+ /// \param C Context of the AST.
+ /// \param NumCounts Number of items in the clause.
+ static OMPCountsClause *CreateEmpty(const ASTContext &C, unsigned NumCounts);
+
+ /// Returns the location of '('.
+ SourceLocation getLParenLoc() const { return LParenLoc; }
+
+ /// Returns the number of list items.
+ unsigned getNumCounts() const { return NumCounts; }
+
+ std::optional<unsigned> getOmpFillIndex() const { return OmpFillIndex; }
+ SourceLocation getOmpFillLoc() const { return OmpFillLoc; }
+ bool hasOmpFill() const { return OmpFillIndex.has_value(); }
+
+ /// Returns the count expressions.
+ MutableArrayRef<Expr *> getCountsRefs() {
+ return getTrailingObjects(NumCounts);
+ }
+ ArrayRef<Expr *> getCountsRefs() const {
+ return getTrailingObjects(NumCounts);
+ }
+
+ child_range children() {
+ MutableArrayRef<Expr *> Counts = getCountsRefs();
+ return child_range(reinterpret_cast<Stmt **>(Counts.begin()),
+ reinterpret_cast<Stmt **>(Counts.end()));
+ }
+ const_child_range children() const {
+ ArrayRef<Expr *> Counts = getCountsRefs();
+ return const_child_range(reinterpret_cast<Stmt *const *>(Counts.begin()),
+ reinterpret_cast<Stmt *const *>(Counts.end()));
+ }
+ child_range used_children() {
+ return child_range(child_iterator(), child_iterator());
+ }
+ const_child_range used_children() const {
+ return const_child_range(const_child_iterator(), const_child_iterator());
+ }
+
+ static bool classof(const OMPClause *T) {
+ return T->getClauseKind() == llvm::omp::OMPC_counts;
+ }
+};
+
/// This class represents the 'permutation' clause in the
/// '#pragma omp interchange' directive.
///
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h
index ce6ad723191e0..1a14dd2c666b5 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -3202,6 +3202,9 @@ DEF_TRAVERSE_STMT(OMPFuseDirective,
DEF_TRAVERSE_STMT(OMPInterchangeDirective,
{ TRY_TO(TraverseOMPExecutableDirective(S)); })
+DEF_TRAVERSE_STMT(OMPSplitDirective,
+ { TRY_TO(TraverseOMPExecutableDirective(S)); })
+
DEF_TRAVERSE_STMT(OMPForDirective,
{ TRY_TO(TraverseOMPExecutableDirective(S)); })
@@ -3503,6 +3506,13 @@ bool RecursiveASTVisitor<Derived>::VisitOMPSizesClause(OMPSizesClause *C) {
return true;
}
+template <typename Derived>
+bool RecursiveASTVisitor<Derived>::VisitOMPCountsClause(OMPCountsClause *C) {
+ for (Expr *E : C->getCountsRefs())
+ TRY_TO(TraverseStmt(E));
+ return true;
+}
+
template <typename Derived>
bool RecursiveASTVisitor<Derived>::VisitOMPPermutationClause(
OMPPermutationClause *C) {
diff --git a/clang/include/clang/AST/StmtOpenMP.h b/clang/include/clang/AST/StmtOpenMP.h
index bc6aeaa8d143c..dbc76e7df8ecd 100644
--- a/clang/include/clang/AST/StmtOpenMP.h
+++ b/clang/include/clang/AST/StmtOpenMP.h
@@ -6065,6 +6065,84 @@ class OMPFuseDirective final
}
};
+/// Represents the '#pragma omp split' loop transformation directive.
+///
+/// \code{.c}
+/// #pragma omp split counts(3, omp_fill, 2)
+/// for (int i = 0; i < n; ++i)
+/// ...
+/// \endcode
+///
+/// This directive transforms a single loop into multiple loops based on
+/// index ranges. The transformation splits the iteration space of the loop
+/// into multiple contiguous ranges. The \c counts clause is required and
+/// exactly one list item must be \c omp_fill.
+class OMPSplitDirective final
+ : public OMPCanonicalLoopNestTransformationDirective {
+ friend class ASTStmtReader;
+ friend class OMPExecutableDirective;
+
+ /// Offsets of child members.
+ enum {
+ PreInitsOffset = 0,
+ TransformedStmtOffset,
+ };
+
+ explicit OMPSplitDirective(SourceLocation StartLoc, SourceLocation EndLoc,
+ unsigned NumLoops)
+ : OMPCanonicalLoopNestTransformationDirective(
+ OMPSplitDirectiveClass, llvm::omp::OMPD_split, StartLoc, EndLoc,
+ NumLoops) {}
+
+ void setPreInits(Stmt *PreInits) {
+ Data->getChildren()[PreInitsOffset] = PreInits;
+ }
+
+ void setTransformedStmt(Stmt *S) {
+ Data->getChildren()[TransformedStmtOffset] = S;
+ }
+
+public:
+ /// Create a new AST node representation for '#pragma omp split'.
+ ///
+ /// \param C Context of the AST.
+ /// \param StartLoc Location of the introducer (e.g. the 'omp' token).
+ /// \param EndLoc Location of the directive's end (e.g. the tok::eod).
+ /// \param Clauses The directive's clauses (e.g. the required \c counts
+ /// clause).
+ /// \param NumLoops Number of affected loops (should be 1 for split).
+ /// \param AssociatedStmt The outermost associated loop.
+ /// \param TransformedStmt The loop nest after splitting, or nullptr in
+ /// dependent contexts.
+ /// \param PreInits Helper preinits statements for the loop nest.
+ static OMPSplitDirective *Create(const ASTContext &C, SourceLocation StartLoc,
+ SourceLocation EndLoc,
+ ArrayRef<OMPClause *> Clauses,
+ unsigned NumLoops, Stmt *AssociatedStmt,
+ Stmt *TransformedStmt, Stmt *PreInits);
+
+ /// Build an empty '#pragma omp split' AST node for deserialization.
+ ///
+ /// \param C Context of the AST.
+ /// \param NumClauses Number of clauses to allocate.
+ /// \param NumLoops Number of associated loops to allocate.
+ static OMPSplitDirective *CreateEmpty(const ASTContext &C,
+ unsigned NumClauses, unsigned NumLoops);
+
+ /// Gets/sets the associated loops after the transformation, i.e. after
+ /// de-sugaring.
+ Stmt *getTransformedStmt() const {
+ return Data->getChildren()[TransformedStmtOffset];
+ }
+
+ /// Return preinits statement.
+ Stmt *getPreInits() const { return Data->getChildren()[PreInitsOffset]; }
+
+ static bool classof(const Stmt *T) {
+ return T->getStmtClass() == OMPSplitDirectiveClass;
+ }
+};
+
/// This represents '#pragma omp scan' directive.
///
/// \code
diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h b/clang/include/clang/ASTMatchers/ASTMatchers.h
index 09232ee463b51..e7e70e59dfedd 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchers.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchers.h
@@ -8807,6 +8807,26 @@ extern const internal::VariadicDynCastAllOfMatcher<Stmt,
OMPTargetUpdateDirective>
ompTargetUpdateDirective;
+/// Matches any ``#pragma omp split`` executable directive.
+///
+/// Given
+///
+/// \code
+/// #pragma omp split counts(2, omp_fill)
+/// for (int i = 0; i < n; ++i) {}
+/// \endcode
+///
+/// ``ompSplitDirective()`` matches the split directive.
+extern const internal::VariadicDynCastAllOfMatcher<Stmt, OMPSplitDirective>
+ ompSplitDirective;
+
+/// Matches OpenMP ``counts`` clause used by ``#pragma omp split``.
+///
+/// Given ``#pragma omp split counts(1, 2, omp_fill)``, ``ompCountsClause()``
+/// matches the ``counts`` clause node.
+extern const internal::VariadicDynCastAllOfMatcher<OMPClause, OMPCountsClause>
+ ompCountsClause;
+
/// Matches OpenMP ``default`` clause.
///
/// Given
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 6d2fae551566f..4cd4efc55c416 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11179,6 +11179,8 @@ def err_omp_bind_required_on_loop : Error<
"construct">;
def err_omp_loop_reduction_clause : Error<
"'reduction' clause not allowed with '#pragma omp loop bind(teams)'">;
+def err_omp_split_counts_not_one_omp_fill : Error<
+ "exactly one 'omp_fill' must appear in the 'counts' clause">;
def warn_break_binds_to_switch : Warning<
"'break' is bound to loop, GCC binds it to switch">,
InGroup<GccCompat>;
diff --git a/clang/include/clang/Basic/StmtNodes.td b/clang/include/clang/Basic/StmtNodes.td
index 61d76bafdfcde..e166894ea024b 100644
--- a/clang/include/clang/Basic/StmtNodes.td
+++ b/clang/include/clang/Basic/StmtNodes.td
@@ -244,6 +244,7 @@ def OMPTileDirective : StmtNode<OMPCanonicalLoopNestTransformationDirective>;
def OMPStripeDirective : StmtNode<OMPCanonicalLoopNestTransformationDirective>;
def OMPUnrollDirective : StmtNode<OMPCanonicalLoopNestTransformationDirective>;
def OMPReverseDirective : StmtNode<OMPCanonicalLoopNestTransformationDirective>;
+def OMPSplitDirective : StmtNode<OMPCanonicalLoopNestTransformationDirective>;
def OMPInterchangeDirective
: StmtNode<OMPCanonicalLoopNestTransformationDirective>;
def OMPCanonicalLoopSequenceTransformationDirective
diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h
index 0919525fbf117..c077671cb2407 100644
--- a/clang/include/clang/Parse/Parser.h
+++ b/clang/include/clang/Parse/Parser.h
@@ -6812,6 +6812,9 @@ class Parser : public CodeCompletionHandler {
/// Parses the 'sizes' clause of a '#pragma omp tile' directive.
OMPClause *ParseOpenMPSizesClause();
+ /// Parses the 'counts' clause of a '#pragma omp split' directive.
+ OMPClause *ParseOpenMPCountsClause();
+
/// Parses the 'permutation' clause of a '#pragma omp interchange' directive.
OMPClause *ParseOpenMPPermutationClause();
diff --git a/clang/include/clang/Sema/SemaOpenMP.h b/clang/include/clang/Sema/SemaOpenMP.h
index 7853f29f98c25..3621ce96b8724 100644
--- a/clang/include/clang/Sema/SemaOpenMP.h
+++ b/clang/include/clang/Sema/SemaOpenMP.h
@@ -42,6 +42,7 @@ class FunctionScopeInfo;
class DeclContext;
class DeclGroupRef;
+class EnumConstantDecl;
class ParsedAttr;
class Scope;
@@ -457,6 +458,11 @@ class SemaOpenMP : public SemaBase {
/// Called on well-formed '#pragma omp reverse'.
StmtResult ActOnOpenMPReverseDirective(Stmt *AStmt, SourceLocation StartLoc,
SourceLocation EndLoc);
+ /// Called on well-formed '#pragma omp split' after parsing of its
+ /// associated statement.
+ StmtResult ActOnOpenMPSplitDirective(ArrayRef<OMPClause *> Clauses,
+ Stmt *AStmt, SourceLocation StartLoc,
+ SourceLocation EndLoc);
/// Called on well-formed '#pragma omp interchange' after parsing of its
/// clauses and the associated statement.
StmtResult ActOnOpenMPInterchangeDirective(ArrayRef<OMPClause *> Clauses,
@@ -911,6 +917,12 @@ class SemaOpenMP : public SemaBase {
SourceLocation StartLoc,
SourceLocation LParenLoc,
SourceLocation EndLoc);
+ /// Called on well-formed 'counts' clause after parsing its arguments.
+ OMPClause *
+ ActOnOpenMPCountsClause(ArrayRef<Expr *> CountExprs, SourceLocation StartLoc,
+ SourceLocation LParenLoc, SourceLocation EndLoc,
+ std::optional<unsigned> FillIdx,
+ SourceLocation FillLoc, unsigned FillCount);
/// Called on well-form 'permutation' clause after parsing its arguments.
OMPClause *ActOnOpenMPPermutationClause(ArrayRef<Expr *> PermExprs,
SourceLocation StartLoc,
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h b/clang/include/clang/Serialization/ASTBitCodes.h
index 783cd82895a90..9b798ed484454 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1965,6 +1965,7 @@ enum StmtCode {
STMP_OMP_STRIPE_DIRECTIVE,
STMT_OMP_UNROLL_DIRECTIVE,
STMT_OMP_REVERSE_DIRECTIVE,
+ STMT_OMP_SPLIT_DIRECTIVE,
STMT_OMP_INTERCHANGE_DIRECTIVE,
STMT_OMP_FUSE_DIRECTIVE,
STMT_OMP_FOR_DIRECTIVE,
diff --git a/clang/lib/AST/OpenMPClause.cpp b/clang/lib/AST/OpenMPClause.cpp
index d4826c3c6edca..3a35e17aff40b 100644
--- a/clang/lib/AST/OpenMPClause.cpp
+++ b/clang/lib/AST/OpenMPClause.cpp
@@ -15,10 +15,12 @@
#include "clang/AST/Attr.h"
#include "clang/AST/Decl.h"
#include "clang/AST/DeclOpenMP.h"
+#include "clang/AST/Expr.h"
#include "clang/AST/ExprOpenMP.h"
#include "clang/Basic/LLVM.h"
#include "clang/Basic/OpenMPKinds.h"
#include "clang/Basic/TargetInfo.h"
+#include "llvm/ADT/Sequence.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/Support/ErrorHandling.h"
#include <algorithm>
@@ -986,6 +988,26 @@ OMPSizesClause *OMPSizesClause::CreateEmpty(const ASTContext &C,
return new (Mem) OMPSizesClause(NumSizes);
}
+OMPCountsClause *OMPCountsClause::Create(
+ const ASTContext &C, SourceLocation StartLoc, SourceLocation LParenLoc,
+ SourceLocation EndLoc, ArrayRef<Expr *> Counts,
+ std::optional<unsigned> FillIdx, SourceLocation FillLoc) {
+ OMPCountsClause *Clause = CreateEmpty(C, Counts.size());
+ Clause->setLocStart(StartLoc);
+ Clause->setLParenLoc(LParenLoc);
+ Clause->setLocEnd(EndLoc);
+ Clause->setCountsRefs(Counts);
+ Clause->setOmpFillIndex(FillIdx);
+ Clause->setOmpFillLoc(FillLoc);
+ return Clause;
+}
+
+OMPCountsClause *OMPCountsClause::CreateEmpty(const ASTContext &C,
+ unsigned NumCounts) {
+ void *Mem = C.Allocate(totalSizeToAlloc<Expr *>(NumCounts));
+ return new (Mem) OMPCountsClause(NumCounts);
+}
+
OMPPermutationClause *OMPPermutationClause::Create(const ASTContext &C,
SourceLocation StartLoc,
SourceLocation LParenLoc,
@@ -1984,6 +2006,19 @@ void OMPClausePrinter::VisitOMPSizesClause(OMPSizesClause *Node) {
OS << ")";
}
+void OMPClausePrinter::VisitOMPCountsClause(OMPCountsClause *Node) {
+ OS << "counts(";
+ std::optional<unsigned> FillIdx = Node->getOmpFillIndex();
+ ArrayRef<Expr *> Refs = Node->getCountsRefs();
+ llvm::interleaveComma(llvm::seq<unsigned>(Refs.size()), OS, [&](unsigned I) {
+ if (FillIdx && I == *FillIdx)
+ OS << "omp_fill";
+ else
+ Refs[I]->printPretty(OS, nullptr, Policy, 0);
+ });
+ OS << ")";
+}
+
void OMPClausePrinter::VisitOMPPermutationClause(OMPPermutationClause *Node) {
OS << "permutation(";
llvm::interleaveComma(Node->getArgsRefs(), OS, [&](const Expr *E) {
diff --git a/clang/lib/AST/StmtOpenMP.cpp b/clang/lib/AST/StmtOpenMP.cpp
index a5b0cd3786a28..9d6b315effb41 100644
--- a/clang/lib/AST/StmtOpenMP.cpp
+++ b/clang/lib/AST/StmtOpenMP.cpp
@@ -552,6 +552,27 @@ OMPInterchangeDirective::CreateEmpty(const ASTContext &C, unsigned NumClauses,
SourceLocation(), SourceLocation(), NumLoops);
}
+OMPSplitDirective *
+OMPSplitDirective::Create(const ASTContext &C, SourceLocation StartLoc,
+ SourceLocation EndLoc, ArrayRef<OMPClause *> Clauses,
+ unsigned NumLoops, Stmt *AssociatedStmt,
+ Stmt *TransformedStmt, Stmt *PreInits) {
+ OMPSplitDirective *Dir = createDirective<OMPSplitDirective>(
+ C, Clauses, AssociatedStmt, TransformedStmtOffset + 1, StartLoc, EndLoc,
+ NumLoops);
+ Dir->setTransformedStmt(TransformedStmt);
+ Dir->setPreInits(PreInits);
+ return Dir;
+}
+
+OMPSplitDirective *OMPSplitDirective::CreateEmpty(const ASTContext &C,
+ unsigned NumClauses,
+ unsigned NumLoops) {
+ return createEmptyDirective<OMPSplitDirective>(
+ C, NumClauses, /*HasAssociatedStmt=*/true, TransformedStmtOffset + 1,
+ SourceLocation(), SourceLocation(), NumLoops);
+}
+
OMPFuseDirective *OMPFuseDirective::Create(
const ASTContext &C, SourceLocation StartLoc, SourceLocation EndLoc,
ArrayRef<OMPClause *> Clauses, unsigned NumGeneratedTopLevelLoops,
diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp
index 4d364fdcd5502..e0b930ba0a21a 100644
--- a/clang/lib/AST/StmtPrinter.cpp
+++ b/clang/lib/AST/StmtPrinter.cpp
@@ -800,6 +800,11 @@ void StmtPrinter::VisitOMPInterchangeDirective(OMPInterchangeDirective *Node) {
PrintOMPExecutableDirective(Node);
}
+void StmtPrinter::VisitOMPSplitDirective(OMPSplitDirective *Node) {
+ Indent() << "#pragma omp split";
+ PrintOMPExecutableDirective(Node);
+}
+
void StmtPrinter::VisitOMPFuseDirective(OMPFuseDirective *Node) {
Indent() << "#pragma omp fuse";
PrintOMPExecutableDirective(Node);
diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp
index 37e40959e00c8..bd65f20214791 100644
--- a/clang/lib/AST/StmtProfile.cpp
+++ b/clang/lib/AST/StmtProfile.cpp
@@ -498,6 +498,12 @@ void OMPClauseProfiler::VisitOMPSizesClause(const OMPSizesClause *C) {
Profiler->VisitExpr(E);
}
+void OMPClauseProfiler::VisitOMPCountsClause(const OMPCountsClause *C) {
+ for (auto *E : C->getCountsRefs())
+ if (E)
+ Profiler->VisitExpr(E);
+}
+
void OMPClauseProfiler::VisitOMPPermutationClause(
const OMPPermutationClause *C) {
for (Expr *E : C->getArgsRefs())
@@ -1051,6 +1057,10 @@ void StmtProfiler::VisitOMPInterchangeDirective(
VisitOMPCanonicalLoopNestTransformationDirective(S);
}
+void StmtProfiler::VisitOMPSplitDirective(const OMPSplitDirective *S) {
+ VisitOMPCanonicalLoopNestTransformationDirective(S);
+}
+
void StmtProfiler::VisitOMPCanonicalLoopSequenceTransformationDirective(
const OMPCanonicalLoopSequenceTransformationDirective *S) {
VisitOMPExecutableDirective(S);
diff --git a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp
index d6860ca660987..5cbf134620e34 100644
--- a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp
+++ b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp
@@ -1139,6 +1139,10 @@ const internal::VariadicDynCastAllOfMatcher<Stmt, OMPExecutableDirective>
ompExecutableDirective;
const internal::VariadicDynCastAllOfMatcher<Stmt, OMPTargetUpdateDirective>
ompTargetUpdateDirective;
+const internal::VariadicDynCastAllOfMatcher<Stmt, OMPSplitDirective>
+ ompSplitDirective;
+const internal::VariadicDynCastAllOfMatcher<OMPClause, OMPCountsClause>
+ ompCountsClause;
const internal::VariadicDynCastAllOfMatcher<OMPClause, OMPDefaultClause>
ompDefaultClause;
const internal::VariadicDynCastAllOfMatcher<OMPClause, OMPFromClause>
diff --git a/clang/lib/ASTMatchers/Dynamic/Registry.cpp b/clang/lib/ASTMatchers/Dynamic/Registry.cpp
index f31684f93f6f3..a04070971f0eb 100644
--- a/clang/lib/ASTMatchers/Dynamic/Registry.cpp
+++ b/clang/lib/ASTMatchers/Dynamic/Registry.cpp
@@ -529,10 +529,12 @@ RegistryMaps::RegistryMaps() {
REGISTER_MATCHER(objcTryStmt);
REGISTER_MATCHER(ofClass);
REGISTER_MATCHER(ofKind);
+ REGISTER_MATCHER(ompCountsClause);
REGISTER_MATCHER(ompDefaultClause);
REGISTER_MATCHER(ompFromClause);
REGISTER_MATCHER(ompToClause);
REGISTER_MATCHER(ompExecutableDirective);
+ REGISTER_MATCHER(ompSplitDirective);
REGISTER_MATCHER(ompTargetUpdateDirective);
REGISTER_MATCHER(on);
REGISTER_MATCHER(onImplicitObjectArgument);
diff --git a/clang/lib/Basic/OpenMPKinds.cpp b/clang/lib/Basic/OpenMPKinds.cpp
index 2c693b1958ee7..287eb217ba458 100644
--- a/clang/lib/Basic/OpenMPKinds.cpp
+++ b/clang/lib/Basic/OpenMPKinds.cpp
@@ -256,6 +256,7 @@ unsigned clang::getOpenMPSimpleClauseType(OpenMPClauseKind Kind, StringRef Str,
case OMPC_safelen:
case OMPC_simdlen:
case OMPC_sizes:
+ case OMPC_counts:
case OMPC_permutation:
case OMPC_allocator:
case OMPC_collapse:
@@ -635,6 +636,7 @@ const char *clang::getOpenMPSimpleClauseTypeName(OpenMPClauseKind Kind,
case OMPC_safelen:
case OMPC_simdlen:
case OMPC_sizes:
+ case OMPC_counts:
case OMPC_permutation:
case OMPC_allocator:
case OMPC_collapse:
@@ -815,7 +817,8 @@ bool clang::isOpenMPLoopBoundSharingDirective(OpenMPDirectiveKind Kind) {
bool clang::isOpenMPCanonicalLoopNestTransformationDirective(
OpenMPDirectiveKind DKind) {
return DKind == OMPD_tile || DKind == OMPD_unroll || DKind == OMPD_reverse ||
- DKind == OMPD_interchange || DKind == OMPD_stripe;
+ DKind == OMPD_split || DKind == OMPD_interchange ||
+ DKind == OMPD_stripe;
}
bool clang::isOpenMPCanonicalLoopSequenceTransformationDirective(
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index a75d3dc64c6b4..7b6035a6968b1 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -230,6 +230,9 @@ void CodeGenFunction::EmitStmt(const Stmt *S, ArrayRef<const Attr *> Attrs) {
case Stmt::OMPReverseDirectiveClass:
EmitOMPReverseDirective(cast<OMPReverseDirective>(*S));
break;
+ case Stmt::OMPSplitDirectiveClass:
+ EmitOMPSplitDirective(cast<OMPSplitDirective>(*S));
+ break;
case Stmt::OMPInterchangeDirectiveClass:
EmitOMPInterchangeDirective(cast<OMPInterchangeDirective>(*S));
break;
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index 990ec47488465..59d0e6825a975 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -197,6 +197,8 @@ class OMPLoopScope : public CodeGenFunction::RunCleanupsScope {
PreInits = Unroll->getPreInits();
} else if (const auto *Reverse = dyn_cast<OMPReverseDirective>(&S)) {
PreInits = Reverse->getPreInits();
+ } else if (const auto *Split = dyn_cast<OMPSplitDirective>(&S)) {
+ PreInits = Split->getPreInits();
} else if (const auto *Interchange =
dyn_cast<OMPInterchangeDirective>(&S)) {
PreInits = Interchange->getPreInits();
@@ -3203,6 +3205,12 @@ void CodeGenFunction::EmitOMPReverseDirective(const OMPReverseDirective &S) {
EmitStmt(S.getTransformedStmt());
}
+void CodeGenFunction::EmitOMPSplitDirective(const OMPSplitDirective &S) {
+ // Emit the de-sugared statement (the split loops).
+ OMPTransformDirectiveScopeRAII SplitScope(*this, &S);
+ EmitStmt(S.getTransformedStmt());
+}
+
void CodeGenFunction::EmitOMPInterchangeDirective(
const OMPInterchangeDirective &S) {
// Emit the de-sugared statement.
diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h
index fd474c09044ef..f06c216e0c746 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -3930,6 +3930,7 @@ class CodeGenFunction : public CodeGenTypeCache {
void EmitOMPStripeDirective(const OMPStripeDirective &S);
void EmitOMPUnrollDirective(const OMPUnrollDirective &S);
void EmitOMPReverseDirective(const OMPReverseDirective &S);
+ void EmitOMPSplitDirective(const OMPSplitDirective &S);
void EmitOMPInterchangeDirective(const OMPInterchangeDirective &S);
void EmitOMPFuseDirective(const OMPFuseDirective &S);
void EmitOMPForDirective(const OMPForDirective &S);
diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp
index 29397d67b5bcc..0e92c3fa1b572 100644
--- a/clang/lib/Parse/ParseOpenMP.cpp
+++ b/clang/lib/Parse/ParseOpenMP.cpp
@@ -28,6 +28,7 @@
#include "llvm/Frontend/OpenMP/DirectiveNameParser.h"
#include "llvm/Frontend/OpenMP/OMPAssume.h"
#include "llvm/Frontend/OpenMP/OMPContext.h"
+#include <climits>
#include <optional>
using namespace clang;
@@ -2424,6 +2425,10 @@ StmtResult Parser::ParseOpenMPExecutableDirective(
Diag(Loc, diag::err_omp_required_clause)
<< getOpenMPDirectiveName(DKind, OMPVersion) << "sizes";
}
+ if (DKind == OMPD_split && !SeenClauses[unsigned(OMPC_counts)]) {
+ Diag(Loc, diag::err_omp_required_clause)
+ << getOpenMPDirectiveName(DKind, OMPVersion) << "counts";
+ }
StmtResult AssociatedStmt;
if (HasAssociatedStatement) {
@@ -2986,6 +2991,51 @@ OMPClause *Parser::ParseOpenMPSizesClause() {
OpenLoc, CloseLoc);
}
+OMPClause *Parser::ParseOpenMPCountsClause() {
+ SourceLocation ClauseNameLoc, OpenLoc, CloseLoc;
+ SmallVector<Expr *, 4> ValExprs;
+ std::optional<unsigned> FillIdx;
+ unsigned FillCount = 0;
+ SourceLocation FillLoc;
+
+ assert(getOpenMPClauseName(OMPC_counts) == PP.getSpelling(Tok) &&
+ "Expected parsing to start at clause name");
+ ClauseNameLoc = ConsumeToken();
+
+ BalancedDelimiterTracker T(*this, tok::l_paren, tok::annot_pragma_openmp_end);
+ if (T.consumeOpen()) {
+ Diag(Tok, diag::err_expected) << tok::l_paren;
+ return nullptr;
+ }
+
+ do {
+ if (Tok.is(tok::identifier) &&
+ Tok.getIdentifierInfo()->getName() == "omp_fill") {
+ if (FillCount == 0)
+ FillIdx = ValExprs.size();
+ ++FillCount;
+ FillLoc = Tok.getLocation();
+ ConsumeToken();
+ ValExprs.push_back(nullptr);
+ } else {
+ ExprResult Val = ParseConstantExpression();
+ if (!Val.isUsable()) {
+ T.skipToEnd();
+ return nullptr;
+ }
+ ValExprs.push_back(Val.get());
+ }
+ } while (TryConsumeToken(tok::comma));
+
+ if (T.consumeClose())
+ return nullptr;
+ OpenLoc = T.getOpenLocation();
+ CloseLoc = T.getCloseLocation();
+
+ return Actions.OpenMP().ActOnOpenMPCountsClause(
+ ValExprs, ClauseNameLoc, OpenLoc, CloseLoc, FillIdx, FillLoc, FillCount);
+}
+
OMPClause *Parser::ParseOpenMPLoopRangeClause() {
SourceLocation ClauseNameLoc = ConsumeToken();
SourceLocation FirstLoc, CountLoc;
@@ -3432,6 +3482,15 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
}
Clause = ParseOpenMPPermutationClause();
break;
+ case OMPC_counts:
+ if (!FirstClause) {
+ Diag(Tok, diag::err_omp_more_one_clause)
+ << getOpenMPDirectiveName(DKind, OMPVersion)
+ << getOpenMPClauseName(CKind) << 0;
+ ErrorFound = true;
+ }
+ Clause = ParseOpenMPCountsClause();
+ break;
case OMPC_uses_allocators:
Clause = ParseOpenMPUsesAllocatorClause(DKind);
break;
diff --git a/clang/lib/Sema/SemaExceptionSpec.cpp b/clang/lib/Sema/SemaExceptionSpec.cpp
index 56079ea8e1bf8..40d530a1f3925 100644
--- a/clang/lib/Sema/SemaExceptionSpec.cpp
+++ b/clang/lib/Sema/SemaExceptionSpec.cpp
@@ -1508,6 +1508,7 @@ CanThrowResult Sema::canThrow(const Stmt *S) {
case Stmt::OMPUnrollDirectiveClass:
case Stmt::OMPReverseDirectiveClass:
case Stmt::OMPInterchangeDirectiveClass:
+ case Stmt::OMPSplitDirectiveClass:
case Stmt::OMPFuseDirectiveClass:
case Stmt::OMPSingleDirectiveClass:
case Stmt::OMPTargetDataDirectiveClass:
diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp
index cdeca15872a95..ec9b2e68ef6cf 100644
--- a/clang/lib/Sema/SemaOpenMP.cpp
+++ b/clang/lib/Sema/SemaOpenMP.cpp
@@ -4627,6 +4627,7 @@ void SemaOpenMP::ActOnOpenMPRegionStart(OpenMPDirectiveKind DKind,
case OMPD_stripe:
case OMPD_unroll:
case OMPD_reverse:
+ case OMPD_split:
case OMPD_interchange:
case OMPD_fuse:
case OMPD_assume:
@@ -6466,6 +6467,10 @@ StmtResult SemaOpenMP::ActOnOpenMPExecutableDirective(
"reverse directive does not support any clauses");
Res = ActOnOpenMPReverseDirective(AStmt, StartLoc, EndLoc);
break;
+ case OMPD_split:
+ Res =
+ ActOnOpenMPSplitDirective(ClausesWithImplicit, AStmt, StartLoc, EndLoc);
+ break;
case OMPD_interchange:
Res = ActOnOpenMPInterchangeDirective(ClausesWithImplicit, AStmt, StartLoc,
EndLoc);
@@ -15911,6 +15916,235 @@ StmtResult SemaOpenMP::ActOnOpenMPReverseDirective(Stmt *AStmt,
buildPreInits(Context, PreInits));
}
+/// Build the AST for \#pragma omp split counts(c1, c2, ...).
+///
+/// Splits the single associated loop into N consecutive loops, where N is the
+/// number of count expressions.
+StmtResult SemaOpenMP::ActOnOpenMPSplitDirective(ArrayRef<OMPClause *> Clauses,
+ Stmt *AStmt,
+ SourceLocation StartLoc,
+ SourceLocation EndLoc) {
+ ASTContext &Context = getASTContext();
+ Scope *CurScope = SemaRef.getCurScope();
+
+ // Empty statement should only be possible if there already was an error.
+ if (!AStmt)
+ return StmtError();
+
+ const auto *CountsClause =
+ OMPExecutableDirective::getSingleClause<OMPCountsClause>(Clauses);
+ if (!CountsClause)
+ return StmtError();
+
+ // Split applies to a single loop; check it is transformable and get helpers.
+ constexpr unsigned NumLoops = 1;
+ Stmt *Body = nullptr;
+ SmallVector<OMPLoopBasedDirective::HelperExprs, NumLoops> LoopHelpers(
+ NumLoops);
+ SmallVector<SmallVector<Stmt *>, NumLoops + 1> OriginalInits;
+ if (!checkTransformableLoopNest(OMPD_split, AStmt, NumLoops, LoopHelpers,
+ Body, OriginalInits))
+ return StmtError();
+
+ // Delay applying the transformation to when template is completely
+ // instantiated.
+ if (SemaRef.CurContext->isDependentContext())
+ return OMPSplitDirective::Create(Context, StartLoc, EndLoc, Clauses,
+ NumLoops, AStmt, nullptr, nullptr);
+
+ assert(LoopHelpers.size() == NumLoops &&
+ "Expecting a single-dimensional loop iteration space");
+ assert(OriginalInits.size() == NumLoops &&
+ "Expecting a single-dimensional loop iteration space");
+ OMPLoopBasedDirective::HelperExprs &LoopHelper = LoopHelpers.front();
+
+ // Find the loop statement.
+ Stmt *LoopStmt = nullptr;
+ collectLoopStmts(AStmt, {LoopStmt});
+
+ // Determine the PreInit declarations.
+ SmallVector<Stmt *> PreInits;
+ addLoopPreInits(Context, LoopHelper, LoopStmt, OriginalInits[0], PreInits);
+
+ // Type and name of the original loop variable; we create one IV per segment
+ // and assign it to the original var so the body sees the same name.
+ auto *IterationVarRef = cast<DeclRefExpr>(LoopHelper.IterationVarRef);
+ QualType IVTy = IterationVarRef->getType();
+ uint64_t IVWidth = Context.getTypeSize(IVTy);
+ auto *OrigVar = cast<DeclRefExpr>(LoopHelper.Counters.front());
+
+ // Iteration variable SourceLocations.
+ SourceLocation OrigVarLoc = OrigVar->getExprLoc();
+ SourceLocation OrigVarLocBegin = OrigVar->getBeginLoc();
+ SourceLocation OrigVarLocEnd = OrigVar->getEndLoc();
+ // Internal variable names.
+ std::string OrigVarName = OrigVar->getNameInfo().getAsString();
+
+ if (!CountsClause->hasOmpFill())
+ return StmtError();
+ unsigned FillIdx = *CountsClause->getOmpFillIndex();
+
+ unsigned NumItems = CountsClause->getNumCounts();
+ SmallVector<uint64_t, 4> CountValues(NumItems, 0);
+ ArrayRef<Expr *> Refs = CountsClause->getCountsRefs();
+ for (unsigned I = 0; I < NumItems; ++I) {
+ if (I == FillIdx)
+ continue;
+ Expr *CountExpr = Refs[I];
+ if (!CountExpr)
+ return OMPSplitDirective::Create(Context, StartLoc, EndLoc, Clauses,
+ NumLoops, AStmt, nullptr, nullptr);
+ std::optional<llvm::APSInt> OptVal =
+ CountExpr->getIntegerConstantExpr(Context);
+ if (!OptVal || OptVal->isNegative())
+ return OMPSplitDirective::Create(Context, StartLoc, EndLoc, Clauses,
+ NumLoops, AStmt, nullptr, nullptr);
+ CountValues[I] = OptVal->getZExtValue();
+ }
+
+ Expr *NumIterExpr = LoopHelper.NumIterations;
+
+ uint64_t RightSum = 0;
+ for (unsigned I = FillIdx + 1; I < NumItems; ++I)
+ RightSum += CountValues[I];
+
+ auto MakeIntLit = [&](uint64_t Val) {
+ return IntegerLiteral::Create(Context, llvm::APInt(IVWidth, Val), IVTy,
+ OrigVarLoc);
+ };
+
+ size_t NumSegments = NumItems;
+ SmallVector<Stmt *, 4> SplitLoops;
+
+ auto *IterVarDecl = cast<VarDecl>(IterationVarRef->getDecl());
+ SplitLoops.push_back(new (Context) DeclStmt(DeclGroupRef(IterVarDecl),
+ IterationVarRef->getBeginLoc(),
+ IterationVarRef->getEndLoc()));
+
+ uint64_t LeftAccum = 0;
+ uint64_t RightRemaining = RightSum;
+
+ for (size_t Seg = 0; Seg < NumSegments; ++Seg) {
+ Expr *StartExpr = nullptr;
+ Expr *EndExpr = nullptr;
+
+ if (Seg < FillIdx) {
+ StartExpr = MakeIntLit(LeftAccum);
+ LeftAccum += CountValues[Seg];
+ EndExpr = MakeIntLit(LeftAccum);
+ } else if (Seg == FillIdx) {
+ StartExpr = MakeIntLit(LeftAccum);
+ if (RightRemaining == 0) {
+ EndExpr = NumIterExpr;
+ } else {
+ ExprResult Sub =
+ SemaRef.BuildBinOp(CurScope, OrigVarLoc, BO_Sub, NumIterExpr,
+ MakeIntLit(RightRemaining));
+ if (!Sub.isUsable())
+ return StmtError();
+ EndExpr = Sub.get();
+ }
+ } else {
+ if (RightRemaining == RightSum) {
+ if (RightSum == 0)
+ StartExpr = NumIterExpr;
+ else {
+ ExprResult Sub =
+ SemaRef.BuildBinOp(CurScope, OrigVarLoc, BO_Sub, NumIterExpr,
+ MakeIntLit(RightRemaining));
+ if (!Sub.isUsable())
+ return StmtError();
+ StartExpr = Sub.get();
+ }
+ } else {
+ ExprResult Sub =
+ SemaRef.BuildBinOp(CurScope, OrigVarLoc, BO_Sub, NumIterExpr,
+ MakeIntLit(RightRemaining));
+ if (!Sub.isUsable())
+ return StmtError();
+ StartExpr = Sub.get();
+ }
+ RightRemaining -= CountValues[Seg];
+ if (RightRemaining == 0)
+ EndExpr = NumIterExpr;
+ else {
+ ExprResult Sub =
+ SemaRef.BuildBinOp(CurScope, OrigVarLoc, BO_Sub, NumIterExpr,
+ MakeIntLit(RightRemaining));
+ if (!Sub.isUsable())
+ return StmtError();
+ EndExpr = Sub.get();
+ }
+ }
+
+ SmallString<64> IVName(".split.iv.");
+ IVName += (Twine(Seg) + "." + OrigVarName).str();
+ VarDecl *IVDecl = buildVarDecl(SemaRef, {}, IVTy, IVName, nullptr, OrigVar);
+ auto MakeIVRef = [&SemaRef = this->SemaRef, IVDecl, IVTy, OrigVarLoc]() {
+ return buildDeclRefExpr(SemaRef, IVDecl, IVTy, OrigVarLoc);
+ };
+
+ SemaRef.AddInitializerToDecl(IVDecl, StartExpr, /*DirectInit=*/false);
+ StmtResult InitStmt = new (Context)
+ DeclStmt(DeclGroupRef(IVDecl), OrigVarLocBegin, OrigVarLocEnd);
+ if (!InitStmt.isUsable())
+ return StmtError();
+
+ ExprResult CondExpr = SemaRef.BuildBinOp(
+ CurScope, LoopHelper.Cond->getExprLoc(), BO_LT, MakeIVRef(), EndExpr);
+ if (!CondExpr.isUsable())
+ return StmtError();
+
+ ExprResult IncrExpr = SemaRef.BuildUnaryOp(
+ CurScope, LoopHelper.Inc->getExprLoc(), UO_PreInc, MakeIVRef());
+ if (!IncrExpr.isUsable())
+ return StmtError();
+
+ ExprResult IVAssign = SemaRef.BuildBinOp(CurScope, OrigVarLoc, BO_Assign,
+ IterationVarRef, MakeIVRef());
+ if (!IVAssign.isUsable())
+ return StmtError();
+
+ SmallVector<Stmt *, 4> BodyStmts;
+ BodyStmts.push_back(IVAssign.get());
+ BodyStmts.append(LoopHelper.Updates.begin(), LoopHelper.Updates.end());
+ if (auto *CXXRangeFor = dyn_cast<CXXForRangeStmt>(LoopStmt)) {
+ if (Seg == 0) {
+ BodyStmts.push_back(CXXRangeFor->getLoopVarStmt());
+ } else {
+ VarDecl *LoopVar = CXXRangeFor->getLoopVariable();
+ DeclRefExpr *LVRef = buildDeclRefExpr(
+ SemaRef, LoopVar, LoopVar->getType().getNonReferenceType(),
+ OrigVarLoc);
+ ExprResult LVAssign = SemaRef.BuildBinOp(
+ CurScope, OrigVarLoc, BO_Assign, LVRef, LoopVar->getInit());
+ if (!LVAssign.isUsable())
+ return StmtError();
+ BodyStmts.push_back(LVAssign.get());
+ }
+ }
+ BodyStmts.push_back(Body);
+
+ auto *LoopBody =
+ CompoundStmt::Create(Context, BodyStmts, FPOptionsOverride(),
+ Body->getBeginLoc(), Body->getEndLoc());
+
+ auto *For = new (Context)
+ ForStmt(Context, InitStmt.get(), CondExpr.get(), nullptr,
+ IncrExpr.get(), LoopBody, LoopHelper.Init->getBeginLoc(),
+ LoopHelper.Init->getBeginLoc(), LoopHelper.Inc->getEndLoc());
+ SplitLoops.push_back(For);
+ }
+
+ auto *SplitStmt = CompoundStmt::Create(
+ Context, SplitLoops, FPOptionsOverride(),
+ SplitLoops.front()->getBeginLoc(), SplitLoops.back()->getEndLoc());
+
+ return OMPSplitDirective::Create(Context, StartLoc, EndLoc, Clauses, NumLoops,
+ AStmt, SplitStmt,
+ buildPreInits(Context, PreInits));
+}
+
StmtResult SemaOpenMP::ActOnOpenMPInterchangeDirective(
ArrayRef<OMPClause *> Clauses, Stmt *AStmt, SourceLocation StartLoc,
SourceLocation EndLoc) {
@@ -17859,6 +18093,43 @@ OMPClause *SemaOpenMP::ActOnOpenMPSizesClause(ArrayRef<Expr *> SizeExprs,
SanitizedSizeExprs);
}
+OMPClause *SemaOpenMP::ActOnOpenMPCountsClause(ArrayRef<Expr *> CountExprs,
+ SourceLocation StartLoc,
+ SourceLocation LParenLoc,
+ SourceLocation EndLoc,
+ std::optional<unsigned> FillIdx,
+ SourceLocation FillLoc,
+ unsigned FillCount) {
+ SmallVector<Expr *> SanitizedCountExprs(CountExprs);
+
+ // OpenMP 6.0: each list item in counts(...) is either the omp_fill keyword
+ // or an integral constant expression (non-negative). Runtime variables are
+ // not permitted; this matches split codegen, which needs segment sizes at
+ // compile time.
+ for (unsigned I = 0; I < SanitizedCountExprs.size(); ++I) {
+ Expr *&CountExpr = SanitizedCountExprs[I];
+ if (FillIdx && I == *FillIdx)
+ continue;
+ if (!CountExpr)
+ continue;
+
+ ExprResult Verified = VerifyPositiveIntegerConstantInClause(
+ CountExpr, OMPC_counts, /*StrictlyPositive=*/false);
+ if (Verified.isInvalid())
+ CountExpr = nullptr;
+ else
+ CountExpr = Verified.get();
+ }
+
+ if (FillCount != 1) {
+ Diag(FillCount == 0 ? StartLoc : FillLoc,
+ diag::err_omp_split_counts_not_one_omp_fill);
+ }
+
+ return OMPCountsClause::Create(getASTContext(), StartLoc, LParenLoc, EndLoc,
+ SanitizedCountExprs, FillIdx, FillLoc);
+}
+
OMPClause *SemaOpenMP::ActOnOpenMPPermutationClause(ArrayRef<Expr *> PermExprs,
SourceLocation StartLoc,
SourceLocation LParenLoc,
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index 4c941e234d78d..07499ff2cd392 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -1769,6 +1769,17 @@ class TreeTransform {
EndLoc);
}
+ OMPClause *RebuildOMPCountsClause(ArrayRef<Expr *> Counts,
+ SourceLocation StartLoc,
+ SourceLocation LParenLoc,
+ SourceLocation EndLoc,
+ std::optional<unsigned> FillIdx,
+ SourceLocation FillLoc) {
+ unsigned FillCount = FillIdx ? 1 : 0;
+ return getSema().OpenMP().ActOnOpenMPCountsClause(
+ Counts, StartLoc, LParenLoc, EndLoc, FillIdx, FillLoc, FillCount);
+ }
+
/// Build a new OpenMP 'permutation' clause.
OMPClause *RebuildOMPPermutationClause(ArrayRef<Expr *> PermExprs,
SourceLocation StartLoc,
@@ -9759,6 +9770,17 @@ StmtResult TreeTransform<Derived>::TransformOMPInterchangeDirective(
return Res;
}
+template <typename Derived>
+StmtResult
+TreeTransform<Derived>::TransformOMPSplitDirective(OMPSplitDirective *D) {
+ DeclarationNameInfo DirName;
+ getDerived().getSema().OpenMP().StartOpenMPDSABlock(
+ D->getDirectiveKind(), DirName, nullptr, D->getBeginLoc());
+ StmtResult Res = getDerived().TransformOMPExecutableDirective(D);
+ getDerived().getSema().OpenMP().EndOpenMPDSABlock(Res.get());
+ return Res;
+}
+
template <typename Derived>
StmtResult
TreeTransform<Derived>::TransformOMPFuseDirective(OMPFuseDirective *D) {
@@ -10615,6 +10637,28 @@ OMPClause *TreeTransform<Derived>::TransformOMPSizesClause(OMPSizesClause *C) {
C->getLParenLoc(), C->getEndLoc());
}
+template <typename Derived>
+OMPClause *
+TreeTransform<Derived>::TransformOMPCountsClause(OMPCountsClause *C) {
+ SmallVector<Expr *, 4> TransformedCounts;
+ TransformedCounts.reserve(C->getNumCounts());
+ for (Expr *E : C->getCountsRefs()) {
+ if (!E) {
+ TransformedCounts.push_back(nullptr);
+ continue;
+ }
+
+ ExprResult T = getDerived().TransformExpr(E);
+ if (T.isInvalid())
+ return nullptr;
+ TransformedCounts.push_back(T.get());
+ }
+
+ return RebuildOMPCountsClause(TransformedCounts, C->getBeginLoc(),
+ C->getLParenLoc(), C->getEndLoc(),
+ C->getOmpFillIndex(), C->getOmpFillLoc());
+}
+
template <typename Derived>
OMPClause *
TreeTransform<Derived>::TransformOMPPermutationClause(OMPPermutationClause *C) {
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index 2dc25133a5d1b..049dc227821cf 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -11453,6 +11453,11 @@ OMPClause *OMPClauseReader::readClause() {
C = OMPSizesClause::CreateEmpty(Context, NumSizes);
break;
}
+ case llvm::omp::OMPC_counts: {
+ unsigned NumCounts = Record.readInt();
+ C = OMPCountsClause::CreateEmpty(Context, NumCounts);
+ break;
+ }
case llvm::omp::OMPC_permutation: {
unsigned NumLoops = Record.readInt();
C = OMPPermutationClause::CreateEmpty(Context, NumLoops);
@@ -11866,6 +11871,16 @@ void OMPClauseReader::VisitOMPSizesClause(OMPSizesClause *C) {
C->setLParenLoc(Record.readSourceLocation());
}
+void OMPClauseReader::VisitOMPCountsClause(OMPCountsClause *C) {
+ bool HasFill = Record.readBool();
+ if (HasFill)
+ C->setOmpFillIndex(Record.readInt());
+ C->setOmpFillLoc(Record.readSourceLocation());
+ for (Expr *&E : C->getCountsRefs())
+ E = Record.readSubExpr();
+ C->setLParenLoc(Record.readSourceLocation());
+}
+
void OMPClauseReader::VisitOMPPermutationClause(OMPPermutationClause *C) {
for (Expr *&E : C->getArgsRefs())
E = Record.readSubExpr();
diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp
index 801eed43c2440..fb81e4fefdebb 100644
--- a/clang/lib/Serialization/ASTReaderStmt.cpp
+++ b/clang/lib/Serialization/ASTReaderStmt.cpp
@@ -2529,6 +2529,10 @@ void ASTStmtReader::VisitOMPInterchangeDirective(OMPInterchangeDirective *D) {
VisitOMPCanonicalLoopNestTransformationDirective(D);
}
+void ASTStmtReader::VisitOMPSplitDirective(OMPSplitDirective *D) {
+ VisitOMPCanonicalLoopNestTransformationDirective(D);
+}
+
void ASTStmtReader::VisitOMPFuseDirective(OMPFuseDirective *D) {
VisitOMPCanonicalLoopSequenceTransformationDirective(D);
}
@@ -3687,6 +3691,13 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
break;
}
+ case STMT_OMP_SPLIT_DIRECTIVE: {
+ unsigned NumLoops = Record[ASTStmtReader::NumStmtFields];
+ unsigned NumClauses = Record[ASTStmtReader::NumStmtFields + 1];
+ S = OMPSplitDirective::CreateEmpty(Context, NumClauses, NumLoops);
+ break;
+ }
+
case STMT_OMP_FUSE_DIRECTIVE: {
unsigned NumClauses = Record[ASTStmtReader::NumStmtFields];
S = OMPFuseDirective::CreateEmpty(Context, NumClauses);
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index f1e6ee8de1b70..632137f01d767 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -8071,6 +8071,17 @@ void OMPClauseWriter::VisitOMPSizesClause(OMPSizesClause *C) {
Record.AddSourceLocation(C->getLParenLoc());
}
+void OMPClauseWriter::VisitOMPCountsClause(OMPCountsClause *C) {
+ Record.push_back(C->getNumCounts());
+ Record.push_back(C->hasOmpFill());
+ if (C->hasOmpFill())
+ Record.push_back(*C->getOmpFillIndex());
+ Record.AddSourceLocation(C->getOmpFillLoc());
+ for (Expr *Count : C->getCountsRefs())
+ Record.AddStmt(Count);
+ Record.AddSourceLocation(C->getLParenLoc());
+}
+
void OMPClauseWriter::VisitOMPPermutationClause(OMPPermutationClause *C) {
Record.push_back(C->getNumLoops());
for (Expr *Size : C->getArgsRefs())
diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp
index 934a95df1be7e..4612cd2a7944d 100644
--- a/clang/lib/Serialization/ASTWriterStmt.cpp
+++ b/clang/lib/Serialization/ASTWriterStmt.cpp
@@ -2546,6 +2546,11 @@ void ASTStmtWriter::VisitOMPInterchangeDirective(OMPInterchangeDirective *D) {
Code = serialization::STMT_OMP_INTERCHANGE_DIRECTIVE;
}
+void ASTStmtWriter::VisitOMPSplitDirective(OMPSplitDirective *D) {
+ VisitOMPCanonicalLoopNestTransformationDirective(D);
+ Code = serialization::STMT_OMP_SPLIT_DIRECTIVE;
+}
+
void ASTStmtWriter::VisitOMPCanonicalLoopSequenceTransformationDirective(
OMPCanonicalLoopSequenceTransformationDirective *D) {
VisitStmt(D);
diff --git a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
index 995a43c7e7aaf..35abd792a5ad0 100644
--- a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+++ b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
@@ -1812,6 +1812,7 @@ void ExprEngine::Visit(const Stmt *S, ExplodedNode *Pred,
case Stmt::OMPStripeDirectiveClass:
case Stmt::OMPTileDirectiveClass:
case Stmt::OMPInterchangeDirectiveClass:
+ case Stmt::OMPSplitDirectiveClass:
case Stmt::OMPFuseDirectiveClass:
case Stmt::OMPInteropDirectiveClass:
case Stmt::OMPDispatchDirectiveClass:
diff --git a/clang/test/AST/ast-dump-openmp-split.c b/clang/test/AST/ast-dump-openmp-split.c
new file mode 100644
index 0000000000000..821badae55e66
--- /dev/null
+++ b/clang/test/AST/ast-dump-openmp-split.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fopenmp -fopenmp-version=60 -ast-dump %s | FileCheck %s
+//
+// OMPSplitDirective / OMPCountsClause;
+
+void body(int);
+
+void test(void) {
+#pragma omp split counts(3, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
+
+// CHECK: OMPSplitDirective
+// CHECK: OMPCountsClause
+// CHECK: IntegerLiteral{{.*}}3
+// CHECK: <<<NULL>>>
+// CHECK: ForStmt
+// CHECK: <<<NULL>>>
+// CHECK: CallExpr
diff --git a/clang/test/Analysis/split_analyze.c b/clang/test/Analysis/split_analyze.c
new file mode 100644
index 0000000000000..60e9be477b919
--- /dev/null
+++ b/clang/test/Analysis/split_analyze.c
@@ -0,0 +1,11 @@
+// Static analyzer invocation on split loop.
+// RUN: %clang_analyze_cc1 -triple x86_64-unknown-linux-gnu -fopenmp -fopenmp-version=60 -analyzer-checker=core.builtin -verify %s
+// expected-no-diagnostics
+
+void g(int);
+
+void f(int n) {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < n; ++i)
+ g(i);
+}
diff --git a/clang/test/Index/openmp-split.c b/clang/test/Index/openmp-split.c
new file mode 100644
index 0000000000000..0c63f12297930
--- /dev/null
+++ b/clang/test/Index/openmp-split.c
@@ -0,0 +1,11 @@
+// RUN: c-index-test -test-load-source local %s -fopenmp=libomp -fopenmp-version=60 | FileCheck %s
+
+void test(void) {
+#pragma omp split counts(3, omp_fill)
+ for (int i = 0; i < 20; i += 1)
+ ;
+}
+
+// CHECK: openmp-split.c:4:1: OMPSplitDirective= Extent=[4:1 - 4:38]
+// CHECK: openmp-split.c:4:26: IntegerLiteral= Extent=[4:26 - 4:27]
+// CHECK: openmp-split.c:5:3: ForStmt= Extent=[5:3 - 6:6]
diff --git a/clang/test/OpenMP/split_ast_print.cpp b/clang/test/OpenMP/split_ast_print.cpp
new file mode 100644
index 0000000000000..9673882bc6778
--- /dev/null
+++ b/clang/test/OpenMP/split_ast_print.cpp
@@ -0,0 +1,71 @@
+// AST dump + ast-print round-trip for omp_fill at every position in counts().
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+// expected-no-diagnostics
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -ast-dump %s | FileCheck %s --check-prefix=DUMP
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -ast-print %s | FileCheck %s --check-prefix=PRINT
+
+#ifndef HEADER
+#define HEADER
+
+extern "C" void body(...);
+
+// --- omp_fill at last position: counts(2, omp_fill) ---
+// PRINT-LABEL: void fill_last(
+// DUMP-LABEL: FunctionDecl {{.*}} fill_last
+void fill_last(int n) {
+ // PRINT: #pragma omp split counts(2, omp_fill)
+ // DUMP: OMPSplitDirective
+ // DUMP: OMPCountsClause
+ #pragma omp split counts(2, omp_fill)
+ // PRINT: for (int i = 0; i < n; ++i)
+ // DUMP: ForStmt
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+// --- omp_fill at first position: counts(omp_fill, 3) ---
+// PRINT-LABEL: void fill_first(
+// DUMP-LABEL: FunctionDecl {{.*}} fill_first
+void fill_first(int n) {
+ // PRINT: #pragma omp split counts(omp_fill, 3)
+ // DUMP: OMPSplitDirective
+ // DUMP: OMPCountsClause
+ #pragma omp split counts(omp_fill, 3)
+ // PRINT: for (int i = 0; i < n; ++i)
+ // DUMP: ForStmt
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+// --- omp_fill at middle position: counts(1, omp_fill, 1) ---
+// PRINT-LABEL: void fill_mid(
+// DUMP-LABEL: FunctionDecl {{.*}} fill_mid
+void fill_mid(int n) {
+ // PRINT: #pragma omp split counts(1, omp_fill, 1)
+ // DUMP: OMPSplitDirective
+ // DUMP: OMPCountsClause
+ #pragma omp split counts(1, omp_fill, 1)
+ // PRINT: for (int i = 0; i < n; ++i)
+ // DUMP: ForStmt
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+// --- omp_fill as sole item: counts(omp_fill) ---
+// PRINT-LABEL: void fill_only(
+// DUMP-LABEL: FunctionDecl {{.*}} fill_only
+void fill_only(int n) {
+ // PRINT: #pragma omp split counts(omp_fill)
+ // DUMP: OMPSplitDirective
+ // DUMP: OMPCountsClause
+ #pragma omp split counts(omp_fill)
+ // PRINT: for (int i = 0; i < n; ++i)
+ // DUMP: ForStmt
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+#endif
diff --git a/clang/test/OpenMP/split_codegen.cpp b/clang/test/OpenMP/split_codegen.cpp
new file mode 100644
index 0000000000000..9c739c013c2fc
--- /dev/null
+++ b/clang/test/OpenMP/split_codegen.cpp
@@ -0,0 +1,1986 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --prefix-filecheck-ir-name _ --version 4
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest -std=c++20 -fopenmp -fopenmp-version=60 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
+
+// Check same results after serialization round-trip
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest -std=c++20 -fopenmp -fopenmp-version=60 -emit-pch -o %t %s
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest -std=c++20 -fopenmp -fopenmp-version=60 -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2
+// expected-no-diagnostics
+
+#ifndef HEADER
+#define HEADER
+
+extern "C" void body(...) {}
+
+struct S {
+ int i;
+ S() {
+#pragma omp split counts(5, omp_fill)
+ for (i = 0; i < 20; i++)
+ body(i);
+ }
+} s;
+
+extern "C" void split_two_const_trip() {
+#pragma omp split counts(3, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
+
+extern "C" void split_var_trip(int n) {
+#pragma omp split counts(3, omp_fill)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+extern "C" void split_mid_fill(int n) {
+#pragma omp split counts(2, omp_fill, 3)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+extern "C" void split_first_fill(int n) {
+#pragma omp split counts(omp_fill, 4)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+extern "C" void split_only_fill(int n) {
+#pragma omp split counts(omp_fill)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+extern "C" void split_neg_start(int n) {
+#pragma omp split counts(1, omp_fill, 1)
+ for (int i = -1; i <= n; ++i)
+ body(i);
+}
+
+extern "C" void split_zero_first() {
+#pragma omp split counts(0, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
+
+extern "C" void split_three_const(int n) {
+#pragma omp split counts(2, 3, omp_fill)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+extern "C" void split_step2(int n) {
+#pragma omp split counts(3, omp_fill)
+ for (int i = 0; i < n; i += 2)
+ body(i);
+}
+
+extern "C" void split_decrement(int n) {
+#pragma omp split counts(omp_fill, 2)
+ for (int i = n; i > 0; --i)
+ body(i);
+}
+
+void split_range_for() {
+ int a[] = {10, 20, 30, 40};
+#pragma omp split counts(2, omp_fill)
+ for (int x : a)
+ body(x);
+}
+
+#endif
+// CHECK1-LABEL: define dso_local void @body(
+// CHECK1-SAME: ...) #[[ATTR0:[0-9]+]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define internal void @__cxx_global_var_init(
+// CHECK1-SAME: ) #[[ATTR1:[0-9]+]] section ".text.startup" {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @s)
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define linkonce_odr void @_ZN1SC1Ev(
+// CHECK1-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define linkonce_odr void @_ZN1SC2Ev(
+// CHECK1-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[I2:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[I:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: [[I3:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[I3]], ptr [[I2]], align 8
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 5
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP3]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i32 5, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND4:%.*]]
+// CHECK1: for.cond4:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP7]], 20
+// CHECK1-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END11:%.*]]
+// CHECK1: for.body6:
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK1-NEXT: store i32 [[ADD8]], ptr [[TMP10]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP12]])
+// CHECK1-NEXT: br label [[FOR_INC9:%.*]]
+// CHECK1: for.inc9:
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK1-NEXT: store i32 [[INC10]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK1: for.end11:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_two_const_trip(
+// CHECK1-SAME: ) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 3
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP3]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i32 3, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND1:%.*]]
+// CHECK1: for.cond1:
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP5]], 10
+// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END8:%.*]]
+// CHECK1: for.body3:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
+// CHECK1-NEXT: store i32 [[ADD5]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]])
+// CHECK1-NEXT: br label [[FOR_INC6:%.*]]
+// CHECK1: for.inc6:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1
+// CHECK1-NEXT: store i32 [[INC7]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK1: for.end8:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_var_trip(
+// CHECK1-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 3
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i32 3, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK1: for.cond3:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
+// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP7]], [[ADD4]]
+// CHECK1-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END11:%.*]]
+// CHECK1: for.body6:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]]
+// CHECK1-NEXT: store i32 [[ADD8]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP11]])
+// CHECK1-NEXT: br label [[FOR_INC9:%.*]]
+// CHECK1: for.inc9:
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK1-NEXT: store i32 [[INC10]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP10:![0-9]+]]
+// CHECK1: for.end11:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_mid_fill(
+// CHECK1-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_2_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 2
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i32 2, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK1: for.cond3:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
+// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i32 [[ADD4]], 3
+// CHECK1-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP7]], [[SUB5]]
+// CHECK1-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END12:%.*]]
+// CHECK1: for.body7:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]
+// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP11]])
+// CHECK1-NEXT: br label [[FOR_INC10:%.*]]
+// CHECK1: for.inc10:
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK1-NEXT: store i32 [[INC11]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK1: for.end12:
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK1-NEXT: [[SUB14:%.*]] = sub nsw i32 [[ADD13]], 3
+// CHECK1-NEXT: store i32 [[SUB14]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND15:%.*]]
+// CHECK1: for.cond15:
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP15]], 1
+// CHECK1-NEXT: [[CMP17:%.*]] = icmp slt i32 [[TMP14]], [[ADD16]]
+// CHECK1-NEXT: br i1 [[CMP17]], label [[FOR_BODY18:%.*]], label [[FOR_END23:%.*]]
+// CHECK1: for.body18:
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL19:%.*]] = mul nsw i32 [[TMP17]], 1
+// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 0, [[MUL19]]
+// CHECK1-NEXT: store i32 [[ADD20]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP18]])
+// CHECK1-NEXT: br label [[FOR_INC21:%.*]]
+// CHECK1: for.inc21:
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: [[INC22:%.*]] = add nsw i32 [[TMP19]], 1
+// CHECK1-NEXT: store i32 [[INC22]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP13:![0-9]+]]
+// CHECK1: for.end23:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_first_fill(
+// CHECK1-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[ADD]], 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[SUB3]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD4]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP6]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1
+// CHECK1-NEXT: [[SUB6:%.*]] = sub nsw i32 [[ADD5]], 4
+// CHECK1-NEXT: store i32 [[SUB6]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND7:%.*]]
+// CHECK1: for.cond7:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP9]], [[ADD8]]
+// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END15:%.*]]
+// CHECK1: for.body10:
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP12]], 1
+// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]]
+// CHECK1-NEXT: store i32 [[ADD12]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP13]])
+// CHECK1-NEXT: br label [[FOR_INC13:%.*]]
+// CHECK1: for.inc13:
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP14]], 1
+// CHECK1-NEXT: store i32 [[INC14]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK1: for.end15:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_only_fill(
+// CHECK1-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[ADD]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
+// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP6]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_neg_start(
+// CHECK1-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_2_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 -1, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP1]], -2
+// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[SUB]], 1
+// CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP2]], 1
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP4]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add i32 -1, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP6]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i32 1, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK1: for.cond3:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD4:%.*]] = add i32 [[TMP8]], 1
+// CHECK1-NEXT: [[SUB5:%.*]] = sub i32 [[ADD4]], 1
+// CHECK1-NEXT: [[CMP6:%.*]] = icmp ult i32 [[TMP7]], [[SUB5]]
+// CHECK1-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END12:%.*]]
+// CHECK1: for.body7:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL8:%.*]] = mul i32 [[TMP10]], 1
+// CHECK1-NEXT: [[ADD9:%.*]] = add i32 -1, [[MUL8]]
+// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP11]])
+// CHECK1-NEXT: br label [[FOR_INC10:%.*]]
+// CHECK1: for.inc10:
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC11:%.*]] = add i32 [[TMP12]], 1
+// CHECK1-NEXT: store i32 [[INC11]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP18:![0-9]+]]
+// CHECK1: for.end12:
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP13]], 1
+// CHECK1-NEXT: [[SUB14:%.*]] = sub i32 [[ADD13]], 1
+// CHECK1-NEXT: store i32 [[SUB14]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND15:%.*]]
+// CHECK1: for.cond15:
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD16:%.*]] = add i32 [[TMP15]], 1
+// CHECK1-NEXT: [[CMP17:%.*]] = icmp ult i32 [[TMP14]], [[ADD16]]
+// CHECK1-NEXT: br i1 [[CMP17]], label [[FOR_BODY18:%.*]], label [[FOR_END23:%.*]]
+// CHECK1: for.body18:
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL19:%.*]] = mul i32 [[TMP17]], 1
+// CHECK1-NEXT: [[ADD20:%.*]] = add i32 -1, [[MUL19]]
+// CHECK1-NEXT: store i32 [[ADD20]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP18]])
+// CHECK1-NEXT: br label [[FOR_INC21:%.*]]
+// CHECK1: for.inc21:
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: [[INC22:%.*]] = add i32 [[TMP19]], 1
+// CHECK1-NEXT: store i32 [[INC22]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP19:![0-9]+]]
+// CHECK1: for.end23:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_zero_first(
+// CHECK1-SAME: ) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 0
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP3]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND1:%.*]]
+// CHECK1: for.cond1:
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP5]], 10
+// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END8:%.*]]
+// CHECK1: for.body3:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
+// CHECK1-NEXT: store i32 [[ADD5]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]])
+// CHECK1-NEXT: br label [[FOR_INC6:%.*]]
+// CHECK1: for.inc6:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1
+// CHECK1-NEXT: store i32 [[INC7]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP21:![0-9]+]]
+// CHECK1: for.end8:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_three_const(
+// CHECK1-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_2_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 2
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i32 2, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK1: for.cond3:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], 5
+// CHECK1-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]]
+// CHECK1: for.body5:
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
+// CHECK1-NEXT: store i32 [[ADD7]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP10]])
+// CHECK1-NEXT: br label [[FOR_INC8:%.*]]
+// CHECK1: for.inc8:
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK1-NEXT: store i32 [[INC9]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP23:![0-9]+]]
+// CHECK1: for.end10:
+// CHECK1-NEXT: store i32 5, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND11:%.*]]
+// CHECK1: for.cond11:
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK1-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP12]], [[ADD12]]
+// CHECK1-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]]
+// CHECK1: for.body14:
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL15:%.*]] = mul nsw i32 [[TMP15]], 1
+// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL15]]
+// CHECK1-NEXT: store i32 [[ADD16]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP16]])
+// CHECK1-NEXT: br label [[FOR_INC17:%.*]]
+// CHECK1: for.inc17:
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP17]], 1
+// CHECK1-NEXT: store i32 [[INC18]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP24:![0-9]+]]
+// CHECK1: for.end19:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_step2(
+// CHECK1-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP1]], -1
+// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[SUB]], 2
+// CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP2]], 3
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP4]], 2
+// CHECK1-NEXT: [[ADD:%.*]] = add i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP6]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i32 3, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK1: for.cond3:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD4:%.*]] = add i32 [[TMP8]], 1
+// CHECK1-NEXT: [[CMP5:%.*]] = icmp ult i32 [[TMP7]], [[ADD4]]
+// CHECK1-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END11:%.*]]
+// CHECK1: for.body6:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL7:%.*]] = mul i32 [[TMP10]], 2
+// CHECK1-NEXT: [[ADD8:%.*]] = add i32 0, [[MUL7]]
+// CHECK1-NEXT: store i32 [[ADD8]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP11]])
+// CHECK1-NEXT: br label [[FOR_INC9:%.*]]
+// CHECK1: for.inc9:
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC10:%.*]] = add i32 [[TMP12]], 1
+// CHECK1-NEXT: store i32 [[INC10]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP26:![0-9]+]]
+// CHECK1: for.end11:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @split_decrement(
+// CHECK1-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[ADD]], 2
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[SUB3]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP6]], [[MUL]]
+// CHECK1-NEXT: store i32 [[SUB4]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK1-NEXT: [[SUB6:%.*]] = sub nsw i32 [[ADD5]], 2
+// CHECK1-NEXT: store i32 [[SUB6]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND7:%.*]]
+// CHECK1: for.cond7:
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP11]], [[ADD8]]
+// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END15:%.*]]
+// CHECK1: for.body10:
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP15]], 1
+// CHECK1-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP14]], [[MUL11]]
+// CHECK1-NEXT: store i32 [[SUB12]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP16]])
+// CHECK1-NEXT: br label [[FOR_INC13:%.*]]
+// CHECK1: for.inc13:
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP17]], 1
+// CHECK1-NEXT: store i32 [[INC14]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP28:![0-9]+]]
+// CHECK1: for.end15:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define dso_local void @_Z15split_range_forv(
+// CHECK1-SAME: ) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[A:%.*]] = alloca [4 x i32], align 16
+// CHECK1-NEXT: [[__RANGE1:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[__END1:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[__BEGIN1:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTSPLIT_IV_0___BEGIN1:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTSPLIT_IV_1___BEGIN1:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[A]], ptr align 16 @__const._Z15split_range_forv.a, i64 16, i1 false)
+// CHECK1-NEXT: store ptr [[A]], ptr [[__RANGE1]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP0]], i64 0, i64 0
+// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY]], i64 4
+// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END1]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP1]], i64 0, i64 0
+// CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN1]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP2]], i64 0, i64 0
+// CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END1]], align 8
+// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i64
+// CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
+// CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
+// CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
+// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 1
+// CHECK1-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK1-NEXT: store i64 0, ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP6]], 2
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK1-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP9]], 1
+// CHECK1-NEXT: [[ADD_PTR6:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 [[MUL]]
+// CHECK1-NEXT: store ptr [[ADD_PTR6]], ptr [[__BEGIN1]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__BEGIN1]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK1-NEXT: store i32 [[TMP11]], ptr [[X]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[X]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP12]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP13]], 1
+// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: store i64 2, ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK1-NEXT: br label [[FOR_COND7:%.*]]
+// CHECK1: for.cond7:
+// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP15]], 1
+// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i64 [[TMP14]], [[ADD8]]
+// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END15:%.*]]
+// CHECK1: for.body10:
+// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK1-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i64 [[TMP18]], 1
+// CHECK1-NEXT: [[ADD_PTR12:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i64 [[MUL11]]
+// CHECK1-NEXT: store ptr [[ADD_PTR12]], ptr [[__BEGIN1]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__BEGIN1]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
+// CHECK1-NEXT: store i32 [[TMP20]], ptr [[X]], align 4
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[X]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP21]])
+// CHECK1-NEXT: br label [[FOR_INC13:%.*]]
+// CHECK1: for.inc13:
+// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK1-NEXT: [[INC14:%.*]] = add nsw i64 [[TMP22]], 1
+// CHECK1-NEXT: store i64 [[INC14]], ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP30:![0-9]+]]
+// CHECK1: for.end15:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define internal void @_GLOBAL__sub_I_split_codegen.cpp(
+// CHECK1-SAME: ) #[[ATTR1]] section ".text.startup" {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: call void @__cxx_global_var_init()
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define internal void @__cxx_global_var_init(
+// CHECK2-SAME: ) #[[ATTR0:[0-9]+]] section ".text.startup" {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @s)
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define linkonce_odr void @_ZN1SC1Ev(
+// CHECK2-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK2-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define linkonce_odr void @_ZN1SC2Ev(
+// CHECK2-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[I2:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK2-NEXT: [[I:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: [[I3:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[I3]], ptr [[I2]], align 8
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 5
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[TMP3]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i32 5, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND4:%.*]]
+// CHECK2: for.cond4:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP7]], 20
+// CHECK2-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END11:%.*]]
+// CHECK2: for.body6:
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]]
+// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK2-NEXT: store i32 [[ADD8]], ptr [[TMP10]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP12]])
+// CHECK2-NEXT: br label [[FOR_INC9:%.*]]
+// CHECK2: for.inc9:
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK2-NEXT: store i32 [[INC10]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK2: for.end11:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @body(
+// CHECK2-SAME: ...) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @_Z15split_range_forv(
+// CHECK2-SAME: ) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[A:%.*]] = alloca [4 x i32], align 16
+// CHECK2-NEXT: [[__RANGE1:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[__END1:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[__BEGIN1:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTSPLIT_IV_0___BEGIN1:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1___BEGIN1:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[A]], ptr align 16 @__const._Z15split_range_forv.a, i64 16, i1 false)
+// CHECK2-NEXT: store ptr [[A]], ptr [[__RANGE1]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP0]], i64 0, i64 0
+// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY]], i64 4
+// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END1]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP1]], i64 0, i64 0
+// CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN1]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META2]], !align [[META3]]
+// CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP2]], i64 0, i64 0
+// CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END1]], align 8
+// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i64
+// CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
+// CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
+// CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
+// CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 1
+// CHECK2-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK2-NEXT: store i64 0, ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i64 [[TMP6]], 2
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK2-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP9]], 1
+// CHECK2-NEXT: [[ADD_PTR6:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 [[MUL]]
+// CHECK2-NEXT: store ptr [[ADD_PTR6]], ptr [[__BEGIN1]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__BEGIN1]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK2-NEXT: store i32 [[TMP11]], ptr [[X]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[X]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP12]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP13]], 1
+// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTSPLIT_IV_0___BEGIN1]], align 8
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i64 2, ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK2-NEXT: br label [[FOR_COND7:%.*]]
+// CHECK2: for.cond7:
+// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP15]], 1
+// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i64 [[TMP14]], [[ADD8]]
+// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END15:%.*]]
+// CHECK2: for.body10:
+// CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK2-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i64 [[TMP18]], 1
+// CHECK2-NEXT: [[ADD_PTR12:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i64 [[MUL11]]
+// CHECK2-NEXT: store ptr [[ADD_PTR12]], ptr [[__BEGIN1]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__BEGIN1]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
+// CHECK2-NEXT: store i32 [[TMP20]], ptr [[X]], align 4
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[X]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP21]])
+// CHECK2-NEXT: br label [[FOR_INC13:%.*]]
+// CHECK2: for.inc13:
+// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK2-NEXT: [[INC14:%.*]] = add nsw i64 [[TMP22]], 1
+// CHECK2-NEXT: store i64 [[INC14]], ptr [[DOTSPLIT_IV_1___BEGIN1]], align 8
+// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK2: for.end15:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_decrement(
+// CHECK2-SAME: i32 noundef [[N:%.*]]) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[ADD]], 2
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[SUB3]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP6]], [[MUL]]
+// CHECK2-NEXT: store i32 [[SUB4]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK2-NEXT: [[SUB6:%.*]] = sub nsw i32 [[ADD5]], 2
+// CHECK2-NEXT: store i32 [[SUB6]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND7:%.*]]
+// CHECK2: for.cond7:
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP11]], [[ADD8]]
+// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END15:%.*]]
+// CHECK2: for.body10:
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP15]], 1
+// CHECK2-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP14]], [[MUL11]]
+// CHECK2-NEXT: store i32 [[SUB12]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP16]])
+// CHECK2-NEXT: br label [[FOR_INC13:%.*]]
+// CHECK2: for.inc13:
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP17]], 1
+// CHECK2-NEXT: store i32 [[INC14]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP10:![0-9]+]]
+// CHECK2: for.end15:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_first_fill(
+// CHECK2-SAME: i32 noundef [[N:%.*]]) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[ADD]], 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[SUB3]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
+// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD4]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP6]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1
+// CHECK2-NEXT: [[SUB6:%.*]] = sub nsw i32 [[ADD5]], 4
+// CHECK2-NEXT: store i32 [[SUB6]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND7:%.*]]
+// CHECK2: for.cond7:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP9]], [[ADD8]]
+// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END15:%.*]]
+// CHECK2: for.body10:
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP12]], 1
+// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]]
+// CHECK2-NEXT: store i32 [[ADD12]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP13]])
+// CHECK2-NEXT: br label [[FOR_INC13:%.*]]
+// CHECK2: for.inc13:
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP14]], 1
+// CHECK2-NEXT: store i32 [[INC14]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK2: for.end15:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_mid_fill(
+// CHECK2-SAME: i32 noundef [[N:%.*]]) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_2_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 2
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i32 2, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK2: for.cond3:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
+// CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i32 [[ADD4]], 3
+// CHECK2-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP7]], [[SUB5]]
+// CHECK2-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END12:%.*]]
+// CHECK2: for.body7:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]
+// CHECK2-NEXT: store i32 [[ADD9]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP11]])
+// CHECK2-NEXT: br label [[FOR_INC10:%.*]]
+// CHECK2: for.inc10:
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC11:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK2-NEXT: store i32 [[INC11]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP14:![0-9]+]]
+// CHECK2: for.end12:
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK2-NEXT: [[SUB14:%.*]] = sub nsw i32 [[ADD13]], 3
+// CHECK2-NEXT: store i32 [[SUB14]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND15:%.*]]
+// CHECK2: for.cond15:
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP15]], 1
+// CHECK2-NEXT: [[CMP17:%.*]] = icmp slt i32 [[TMP14]], [[ADD16]]
+// CHECK2-NEXT: br i1 [[CMP17]], label [[FOR_BODY18:%.*]], label [[FOR_END23:%.*]]
+// CHECK2: for.body18:
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL19:%.*]] = mul nsw i32 [[TMP17]], 1
+// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 0, [[MUL19]]
+// CHECK2-NEXT: store i32 [[ADD20]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP18]])
+// CHECK2-NEXT: br label [[FOR_INC21:%.*]]
+// CHECK2: for.inc21:
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: [[INC22:%.*]] = add nsw i32 [[TMP19]], 1
+// CHECK2-NEXT: store i32 [[INC22]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK2: for.end23:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_neg_start(
+// CHECK2-SAME: i32 noundef [[N:%.*]]) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_2_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 -1, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP1]], -2
+// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[SUB]], 1
+// CHECK2-NEXT: [[SUB2:%.*]] = sub i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP2]], 1
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP4]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add i32 -1, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP6]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i32 1, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK2: for.cond3:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD4:%.*]] = add i32 [[TMP8]], 1
+// CHECK2-NEXT: [[SUB5:%.*]] = sub i32 [[ADD4]], 1
+// CHECK2-NEXT: [[CMP6:%.*]] = icmp ult i32 [[TMP7]], [[SUB5]]
+// CHECK2-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END12:%.*]]
+// CHECK2: for.body7:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL8:%.*]] = mul i32 [[TMP10]], 1
+// CHECK2-NEXT: [[ADD9:%.*]] = add i32 -1, [[MUL8]]
+// CHECK2-NEXT: store i32 [[ADD9]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP11]])
+// CHECK2-NEXT: br label [[FOR_INC10:%.*]]
+// CHECK2: for.inc10:
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC11:%.*]] = add i32 [[TMP12]], 1
+// CHECK2-NEXT: store i32 [[INC11]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP17:![0-9]+]]
+// CHECK2: for.end12:
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP13]], 1
+// CHECK2-NEXT: [[SUB14:%.*]] = sub i32 [[ADD13]], 1
+// CHECK2-NEXT: store i32 [[SUB14]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND15:%.*]]
+// CHECK2: for.cond15:
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD16:%.*]] = add i32 [[TMP15]], 1
+// CHECK2-NEXT: [[CMP17:%.*]] = icmp ult i32 [[TMP14]], [[ADD16]]
+// CHECK2-NEXT: br i1 [[CMP17]], label [[FOR_BODY18:%.*]], label [[FOR_END23:%.*]]
+// CHECK2: for.body18:
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL19:%.*]] = mul i32 [[TMP17]], 1
+// CHECK2-NEXT: [[ADD20:%.*]] = add i32 -1, [[MUL19]]
+// CHECK2-NEXT: store i32 [[ADD20]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP18]])
+// CHECK2-NEXT: br label [[FOR_INC21:%.*]]
+// CHECK2: for.inc21:
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: [[INC22:%.*]] = add i32 [[TMP19]], 1
+// CHECK2-NEXT: store i32 [[INC22]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP18:![0-9]+]]
+// CHECK2: for.end23:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_only_fill(
+// CHECK2-SAME: i32 noundef [[N:%.*]]) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[ADD]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD3]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP6]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_step2(
+// CHECK2-SAME: i32 noundef [[N:%.*]]) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP1]], -1
+// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[SUB]], 2
+// CHECK2-NEXT: [[SUB2:%.*]] = sub i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP2]], 3
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP4]], 2
+// CHECK2-NEXT: [[ADD:%.*]] = add i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP6]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i32 3, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK2: for.cond3:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD4:%.*]] = add i32 [[TMP8]], 1
+// CHECK2-NEXT: [[CMP5:%.*]] = icmp ult i32 [[TMP7]], [[ADD4]]
+// CHECK2-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END11:%.*]]
+// CHECK2: for.body6:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL7:%.*]] = mul i32 [[TMP10]], 2
+// CHECK2-NEXT: [[ADD8:%.*]] = add i32 0, [[MUL7]]
+// CHECK2-NEXT: store i32 [[ADD8]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP11]])
+// CHECK2-NEXT: br label [[FOR_INC9:%.*]]
+// CHECK2: for.inc9:
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC10:%.*]] = add i32 [[TMP12]], 1
+// CHECK2-NEXT: store i32 [[INC10]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP21:![0-9]+]]
+// CHECK2: for.end11:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_three_const(
+// CHECK2-SAME: i32 noundef [[N:%.*]]) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_2_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 2
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i32 2, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK2: for.cond3:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP7]], 5
+// CHECK2-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]]
+// CHECK2: for.body5:
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
+// CHECK2-NEXT: store i32 [[ADD7]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP10]])
+// CHECK2-NEXT: br label [[FOR_INC8:%.*]]
+// CHECK2: for.inc8:
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK2-NEXT: store i32 [[INC9]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP23:![0-9]+]]
+// CHECK2: for.end10:
+// CHECK2-NEXT: store i32 5, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND11:%.*]]
+// CHECK2: for.cond11:
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK2-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP12]], [[ADD12]]
+// CHECK2-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]]
+// CHECK2: for.body14:
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL15:%.*]] = mul nsw i32 [[TMP15]], 1
+// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL15]]
+// CHECK2-NEXT: store i32 [[ADD16]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP16]])
+// CHECK2-NEXT: br label [[FOR_INC17:%.*]]
+// CHECK2: for.inc17:
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP17]], 1
+// CHECK2-NEXT: store i32 [[INC18]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP24:![0-9]+]]
+// CHECK2: for.end19:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_two_const_trip(
+// CHECK2-SAME: ) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 3
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP3]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i32 3, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND1:%.*]]
+// CHECK2: for.cond1:
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP5]], 10
+// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END8:%.*]]
+// CHECK2: for.body3:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
+// CHECK2-NEXT: store i32 [[ADD5]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]])
+// CHECK2-NEXT: br label [[FOR_INC6:%.*]]
+// CHECK2: for.inc6:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1
+// CHECK2-NEXT: store i32 [[INC7]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP26:![0-9]+]]
+// CHECK2: for.end8:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_var_trip(
+// CHECK2-SAME: i32 noundef [[N:%.*]]) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 3
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP5]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i32 3, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3:%.*]]
+// CHECK2: for.cond3:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
+// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP7]], [[ADD4]]
+// CHECK2-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END11:%.*]]
+// CHECK2: for.body6:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 0, [[MUL7]]
+// CHECK2-NEXT: store i32 [[ADD8]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP11]])
+// CHECK2-NEXT: br label [[FOR_INC9:%.*]]
+// CHECK2: for.inc9:
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK2-NEXT: store i32 [[INC10]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP28:![0-9]+]]
+// CHECK2: for.end11:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define dso_local void @split_zero_first(
+// CHECK2-SAME: ) #[[ATTR1]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 0
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP3]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: store i32 0, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND1:%.*]]
+// CHECK2: for.cond1:
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP5]], 10
+// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END8:%.*]]
+// CHECK2: for.body3:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
+// CHECK2-NEXT: store i32 [[ADD5]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]])
+// CHECK2-NEXT: br label [[FOR_INC6:%.*]]
+// CHECK2: for.inc6:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1
+// CHECK2-NEXT: store i32 [[INC7]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP30:![0-9]+]]
+// CHECK2: for.end8:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define internal void @_GLOBAL__sub_I_split_codegen.cpp(
+// CHECK2-SAME: ) #[[ATTR0]] section ".text.startup" {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: call void @__cxx_global_var_init()
+// CHECK2-NEXT: ret void
+//
+//.
+// CHECK1: [[META2]] = !{}
+// CHECK1: [[META3]] = !{i64 4}
+// CHECK1: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]}
+// CHECK1: [[META5]] = !{!"llvm.loop.mustprogress"}
+// CHECK1: [[LOOP6]] = distinct !{[[LOOP6]], [[META5]]}
+// CHECK1: [[LOOP7]] = distinct !{[[LOOP7]], [[META5]]}
+// CHECK1: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]]}
+// CHECK1: [[LOOP9]] = distinct !{[[LOOP9]], [[META5]]}
+// CHECK1: [[LOOP10]] = distinct !{[[LOOP10]], [[META5]]}
+// CHECK1: [[LOOP11]] = distinct !{[[LOOP11]], [[META5]]}
+// CHECK1: [[LOOP12]] = distinct !{[[LOOP12]], [[META5]]}
+// CHECK1: [[LOOP13]] = distinct !{[[LOOP13]], [[META5]]}
+// CHECK1: [[LOOP14]] = distinct !{[[LOOP14]], [[META5]]}
+// CHECK1: [[LOOP15]] = distinct !{[[LOOP15]], [[META5]]}
+// CHECK1: [[LOOP16]] = distinct !{[[LOOP16]], [[META5]]}
+// CHECK1: [[LOOP17]] = distinct !{[[LOOP17]], [[META5]]}
+// CHECK1: [[LOOP18]] = distinct !{[[LOOP18]], [[META5]]}
+// CHECK1: [[LOOP19]] = distinct !{[[LOOP19]], [[META5]]}
+// CHECK1: [[LOOP20]] = distinct !{[[LOOP20]], [[META5]]}
+// CHECK1: [[LOOP21]] = distinct !{[[LOOP21]], [[META5]]}
+// CHECK1: [[LOOP22]] = distinct !{[[LOOP22]], [[META5]]}
+// CHECK1: [[LOOP23]] = distinct !{[[LOOP23]], [[META5]]}
+// CHECK1: [[LOOP24]] = distinct !{[[LOOP24]], [[META5]]}
+// CHECK1: [[LOOP25]] = distinct !{[[LOOP25]], [[META5]]}
+// CHECK1: [[LOOP26]] = distinct !{[[LOOP26]], [[META5]]}
+// CHECK1: [[LOOP27]] = distinct !{[[LOOP27]], [[META5]]}
+// CHECK1: [[LOOP28]] = distinct !{[[LOOP28]], [[META5]]}
+// CHECK1: [[LOOP29]] = distinct !{[[LOOP29]], [[META5]]}
+// CHECK1: [[LOOP30]] = distinct !{[[LOOP30]], [[META5]]}
+//.
+// CHECK2: [[META2]] = !{}
+// CHECK2: [[META3]] = !{i64 4}
+// CHECK2: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]}
+// CHECK2: [[META5]] = !{!"llvm.loop.mustprogress"}
+// CHECK2: [[LOOP6]] = distinct !{[[LOOP6]], [[META5]]}
+// CHECK2: [[LOOP7]] = distinct !{[[LOOP7]], [[META5]]}
+// CHECK2: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]]}
+// CHECK2: [[LOOP9]] = distinct !{[[LOOP9]], [[META5]]}
+// CHECK2: [[LOOP10]] = distinct !{[[LOOP10]], [[META5]]}
+// CHECK2: [[LOOP11]] = distinct !{[[LOOP11]], [[META5]]}
+// CHECK2: [[LOOP12]] = distinct !{[[LOOP12]], [[META5]]}
+// CHECK2: [[LOOP13]] = distinct !{[[LOOP13]], [[META5]]}
+// CHECK2: [[LOOP14]] = distinct !{[[LOOP14]], [[META5]]}
+// CHECK2: [[LOOP15]] = distinct !{[[LOOP15]], [[META5]]}
+// CHECK2: [[LOOP16]] = distinct !{[[LOOP16]], [[META5]]}
+// CHECK2: [[LOOP17]] = distinct !{[[LOOP17]], [[META5]]}
+// CHECK2: [[LOOP18]] = distinct !{[[LOOP18]], [[META5]]}
+// CHECK2: [[LOOP19]] = distinct !{[[LOOP19]], [[META5]]}
+// CHECK2: [[LOOP20]] = distinct !{[[LOOP20]], [[META5]]}
+// CHECK2: [[LOOP21]] = distinct !{[[LOOP21]], [[META5]]}
+// CHECK2: [[LOOP22]] = distinct !{[[LOOP22]], [[META5]]}
+// CHECK2: [[LOOP23]] = distinct !{[[LOOP23]], [[META5]]}
+// CHECK2: [[LOOP24]] = distinct !{[[LOOP24]], [[META5]]}
+// CHECK2: [[LOOP25]] = distinct !{[[LOOP25]], [[META5]]}
+// CHECK2: [[LOOP26]] = distinct !{[[LOOP26]], [[META5]]}
+// CHECK2: [[LOOP27]] = distinct !{[[LOOP27]], [[META5]]}
+// CHECK2: [[LOOP28]] = distinct !{[[LOOP28]], [[META5]]}
+// CHECK2: [[LOOP29]] = distinct !{[[LOOP29]], [[META5]]}
+// CHECK2: [[LOOP30]] = distinct !{[[LOOP30]], [[META5]]}
+//.
diff --git a/clang/test/OpenMP/split_composition.cpp b/clang/test/OpenMP/split_composition.cpp
new file mode 100644
index 0000000000000..eabe3f8f345f7
--- /dev/null
+++ b/clang/test/OpenMP/split_composition.cpp
@@ -0,0 +1,17 @@
+// Split nested inside `omp parallel for` outer loop.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+extern "C" void body(int, int);
+
+// CHECK: define {{.*}} @composition(
+// CHECK: .split.iv
+// CHECK: call void @body
+extern "C" void composition(void) {
+#pragma omp parallel for
+ for (int i = 0; i < 4; ++i) {
+#pragma omp split counts(2, omp_fill)
+ for (int j = 0; j < 10; ++j)
+ body(i, j);
+ }
+}
diff --git a/clang/test/OpenMP/split_compound_associated.cpp b/clang/test/OpenMP/split_compound_associated.cpp
new file mode 100644
index 0000000000000..7bbc5107ef672
--- /dev/null
+++ b/clang/test/OpenMP/split_compound_associated.cpp
@@ -0,0 +1,13 @@
+// Associated statement may be a compound `{ for (...) {} }` (split still finds the loop).
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define {{.*}} @f(
+// CHECK: .split.iv
+extern "C" void f(void) {
+#pragma omp split counts(2, omp_fill)
+ {
+ for (int i = 0; i < 10; ++i) {
+ }
+ }
+}
diff --git a/clang/test/OpenMP/split_counts_constexpr.cpp b/clang/test/OpenMP/split_counts_constexpr.cpp
new file mode 100644
index 0000000000000..d304a9ca1b5a1
--- /dev/null
+++ b/clang/test/OpenMP/split_counts_constexpr.cpp
@@ -0,0 +1,19 @@
+/* C++ `constexpr` locals as `counts` operands (distinct from NTTP in split_template_nttp.cpp). */
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -std=c++17 -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+// expected-no-diagnostics
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -std=c++17 -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+extern "C" void body(int);
+
+// CHECK-LABEL: define {{.*}} @from_constexpr
+// CHECK: .split.iv.0
+// CHECK: icmp slt i32 {{.*}}, 4
+// CHECK: .split.iv.1
+// CHECK: icmp slt i32 {{.*}}, 10
+extern "C" void from_constexpr(void) {
+ static constexpr int C0 = 4;
+#pragma omp split counts(C0, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
diff --git a/clang/test/OpenMP/split_counts_ice.c b/clang/test/OpenMP/split_counts_ice.c
new file mode 100644
index 0000000000000..c746ef417f049
--- /dev/null
+++ b/clang/test/OpenMP/split_counts_ice.c
@@ -0,0 +1,56 @@
+/* `counts` operands as ICEs: macros, enumerators, sizeof (not only raw literals). */
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+// expected-no-diagnostics
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+#define M1 2
+
+extern void body(int);
+
+// CHECK-LABEL: define {{.*}} @from_macros
+// CHECK: .split.iv.0
+// CHECK: icmp slt i32 {{.*}}, 2
+// CHECK: .split.iv.1
+// CHECK: icmp slt i32 {{.*}}, 10
+void from_macros(void) {
+#pragma omp split counts(M1, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
+
+enum { EFirst = 3 };
+
+// CHECK-LABEL: define {{.*}} @from_enum
+// CHECK: .split.iv.0
+// CHECK: icmp slt i32 {{.*}}, 3
+// CHECK: .split.iv.1
+// CHECK: icmp slt i32 {{.*}}, 10
+void from_enum(void) {
+#pragma omp split counts(EFirst, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
+
+// CHECK-LABEL: define {{.*}} @from_sizeof
+// CHECK: .split.iv.0
+// CHECK: icmp slt i32 {{.*}}, 1
+// CHECK: .split.iv.1
+// CHECK: icmp slt i32 {{.*}}, 10
+void from_sizeof(void) {
+#pragma omp split counts(sizeof(char), omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
+
+// CHECK-LABEL: define {{.*}} @from_macro_expr
+// CHECK: .split.iv.0
+// CHECK: icmp slt i32 {{.*}}, 4
+// CHECK: .split.iv.1
+// CHECK: icmp slt i32 {{.*}}, 10
+#define BASE 1
+void from_macro_expr(void) {
+#pragma omp split counts(BASE + 3, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+}
diff --git a/clang/test/OpenMP/split_counts_verify.c b/clang/test/OpenMP/split_counts_verify.c
new file mode 100644
index 0000000000000..7fec1561d8380
--- /dev/null
+++ b/clang/test/OpenMP/split_counts_verify.c
@@ -0,0 +1,123 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 5
+/*
+ * Verify #pragma omp split counts(c1, c2, ...) at syntax and IR levels.
+ * counts(3, omp_fill, 2) with n=10 splits into: [0..3), [3..8), [8..10).
+ * Sum 0+1+...+9 = 45.
+ * For end-to-end runtime tests see openmp/runtime/test/transform/split/.
+ */
+
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fopenmp -fopenmp-version=60 -emit-llvm %s -o - | FileCheck %s --check-prefix=IR
+
+int main(void) {
+ const int n = 10;
+ int sum = 0;
+
+#pragma omp split counts(3, omp_fill, 2)
+ for (int i = 0; i < n; ++i) {
+ sum += i;
+ }
+
+ return (sum == 45) ? 0 : 1;
+}
+// IR-LABEL: define dso_local i32 @main(
+// IR-SAME: ) #[[ATTR0:[0-9]+]] {
+// IR-NEXT: [[ENTRY:.*:]]
+// IR-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// IR-NEXT: [[N:%.*]] = alloca i32, align 4
+// IR-NEXT: [[SUM:%.*]] = alloca i32, align 4
+// IR-NEXT: [[I:%.*]] = alloca i32, align 4
+// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// IR-NEXT: [[DOTSPLIT_IV_0_I:%.*]] = alloca i32, align 4
+// IR-NEXT: [[DOTSPLIT_IV_1_I:%.*]] = alloca i32, align 4
+// IR-NEXT: [[DOTSPLIT_IV_2_I:%.*]] = alloca i32, align 4
+// IR-NEXT: store i32 0, ptr [[RETVAL]], align 4
+// IR-NEXT: store i32 10, ptr [[N]], align 4
+// IR-NEXT: store i32 0, ptr [[SUM]], align 4
+// IR-NEXT: store i32 0, ptr [[I]], align 4
+// IR-NEXT: store i32 0, ptr [[DOTSPLIT_IV_0_I]], align 4
+// IR-NEXT: br label %[[FOR_COND:.*]]
+// IR: [[FOR_COND]]:
+// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 3
+// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END:.*]]
+// IR: [[FOR_BODY]]:
+// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// IR-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
+// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// IR-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// IR-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
+// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[SUM]], align 4
+// IR-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]]
+// IR-NEXT: store i32 [[ADD1]], ptr [[SUM]], align 4
+// IR-NEXT: br label %[[FOR_INC:.*]]
+// IR: [[FOR_INC]]:
+// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTSPLIT_IV_0_I]], align 4
+// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1
+// IR-NEXT: store i32 [[INC]], ptr [[DOTSPLIT_IV_0_I]], align 4
+// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
+// IR: [[FOR_END]]:
+// IR-NEXT: store i32 3, ptr [[DOTSPLIT_IV_1_I]], align 4
+// IR-NEXT: br label %[[FOR_COND2:.*]]
+// IR: [[FOR_COND2]]:
+// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// IR-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], 8
+// IR-NEXT: br i1 [[CMP3]], label %[[FOR_BODY4:.*]], label %[[FOR_END10:.*]]
+// IR: [[FOR_BODY4]]:
+// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// IR-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
+// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// IR-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP8]], 1
+// IR-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
+// IR-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
+// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[SUM]], align 4
+// IR-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
+// IR-NEXT: store i32 [[ADD7]], ptr [[SUM]], align 4
+// IR-NEXT: br label %[[FOR_INC8:.*]]
+// IR: [[FOR_INC8]]:
+// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTSPLIT_IV_1_I]], align 4
+// IR-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP11]], 1
+// IR-NEXT: store i32 [[INC9]], ptr [[DOTSPLIT_IV_1_I]], align 4
+// IR-NEXT: br label %[[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]]
+// IR: [[FOR_END10]]:
+// IR-NEXT: store i32 8, ptr [[DOTSPLIT_IV_2_I]], align 4
+// IR-NEXT: br label %[[FOR_COND11:.*]]
+// IR: [[FOR_COND11]]:
+// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// IR-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], 10
+// IR-NEXT: br i1 [[CMP12]], label %[[FOR_BODY13:.*]], label %[[FOR_END19:.*]]
+// IR: [[FOR_BODY13]]:
+// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// IR-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
+// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// IR-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP14]], 1
+// IR-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
+// IR-NEXT: store i32 [[ADD15]], ptr [[I]], align 4
+// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4
+// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[SUM]], align 4
+// IR-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
+// IR-NEXT: store i32 [[ADD16]], ptr [[SUM]], align 4
+// IR-NEXT: br label %[[FOR_INC17:.*]]
+// IR: [[FOR_INC17]]:
+// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTSPLIT_IV_2_I]], align 4
+// IR-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP17]], 1
+// IR-NEXT: store i32 [[INC18]], ptr [[DOTSPLIT_IV_2_I]], align 4
+// IR-NEXT: br label %[[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
+// IR: [[FOR_END19]]:
+// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[SUM]], align 4
+// IR-NEXT: [[CMP20:%.*]] = icmp eq i32 [[TMP18]], 45
+// IR-NEXT: [[TMP19:%.*]] = zext i1 [[CMP20]] to i64
+// IR-NEXT: [[COND:%.*]] = select i1 [[CMP20]], i32 0, i32 1
+// IR-NEXT: ret i32 [[COND]]
+//
+//.
+// IR: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]}
+// IR: [[META3]] = !{!"llvm.loop.mustprogress"}
+// IR: [[LOOP4]] = distinct !{[[LOOP4]], [[META3]]}
+// IR: [[LOOP5]] = distinct !{[[LOOP5]], [[META3]]}
+//.
diff --git a/clang/test/OpenMP/split_diag_errors.c b/clang/test/OpenMP/split_diag_errors.c
new file mode 100644
index 0000000000000..98986f3200ff7
--- /dev/null
+++ b/clang/test/OpenMP/split_diag_errors.c
@@ -0,0 +1,61 @@
+/*
+ * Error and delayed-transformation cases for #pragma omp split counts(...).
+ */
+// 1) Required clause missing: err_omp_required_clause
+// RUN: not %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -DTEST_REQUIRED_CLAUSE %s 2>&1 | FileCheck %s --check-prefix=REQ
+// 2) counts(negative): non-negative diagnostic
+// RUN: not %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -DTEST_NEGATIVE %s 2>&1 | FileCheck %s --check-prefix=NEG
+// 3) counts(non-integer): integral type diagnostic
+// RUN: not %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -DTEST_FLOAT %s 2>&1 | FileCheck %s --check-prefix=FLOAT
+// 6) Loop not transformable (while): must be a for loop
+// RUN: not %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -DTEST_WHILE %s 2>&1 | FileCheck %s --check-prefix=WHILE
+// Two invalid counts — two diagnostics on the clause
+// RUN: not %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -DTEST_DOUBLE_NEGATIVE %s 2>&1 | FileCheck %s --check-prefix=DBLNEG
+
+#ifdef TEST_REQUIRED_CLAUSE
+void test_required_clause_missing(void) {
+#pragma omp split
+ for (int i = 0; i < 10; ++i) {
+ }
+}
+// REQ: error: {{.*}}requires the 'counts' clause
+#endif
+
+#ifdef TEST_NEGATIVE
+void test_negative_count(void) {
+#pragma omp split counts(-1, omp_fill)
+ for (int i = 0; i < 10; ++i) {
+ }
+}
+// NEG: error: {{.*}}counts{{.*}}non-negative integer
+#endif
+
+#ifdef TEST_FLOAT
+void test_float_count(void) {
+#pragma omp split counts(2.5, omp_fill)
+ for (int i = 0; i < 10; ++i) {
+ }
+}
+// FLOAT: error: {{.*}}integer constant expression must have integer type
+#endif
+
+#ifdef TEST_WHILE
+void test_while_not_for(void) {
+ int i = 0;
+#pragma omp split counts(5, omp_fill)
+ while (i < 10) {
+ ++i;
+ }
+}
+// WHILE: error: {{.*}}must be a for loop
+#endif
+
+#ifdef TEST_DOUBLE_NEGATIVE
+void test_two_negative_counts(void) {
+#pragma omp split counts(-1, -1, omp_fill)
+ for (int i = 0; i < 10; ++i) {
+ }
+}
+// DBLNEG: error: {{.*}}counts{{.*}}non-negative integer
+// DBLNEG: error: {{.*}}counts{{.*}}non-negative integer
+#endif
diff --git a/clang/test/OpenMP/split_distribute_inner_split.cpp b/clang/test/OpenMP/split_distribute_inner_split.cpp
new file mode 100644
index 0000000000000..290d0336f1b03
--- /dev/null
+++ b/clang/test/OpenMP/split_distribute_inner_split.cpp
@@ -0,0 +1,14 @@
+// `distribute` outer loop with inner `split` (combined-construct interop beyond host `teams` case).
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define {{.*}} @f(
+// CHECK: .split.iv
+extern "C" void f(void) {
+#pragma omp distribute
+ for (int i = 0; i < 10; ++i) {
+#pragma omp split counts(2, omp_fill)
+ for (int j = 0; j < 10; ++j) {
+ }
+ }
+}
diff --git a/clang/test/OpenMP/split_driver_smoke.c b/clang/test/OpenMP/split_driver_smoke.c
new file mode 100644
index 0000000000000..5969611c9b425
--- /dev/null
+++ b/clang/test/OpenMP/split_driver_smoke.c
@@ -0,0 +1,12 @@
+// Driver forwards `-fopenmp-version=60` with split source (`###` only — no link).
+// REQUIRES: x86-registered-target
+//
+// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp -fopenmp-version=60 -c %s -o %t.o 2>&1 | FileCheck %s --check-prefix=INVOC
+
+void f(int n) {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < n; ++i) {
+ }
+}
+
+// INVOC: -fopenmp-version=60
diff --git a/clang/test/OpenMP/split_iv_types.c b/clang/test/OpenMP/split_iv_types.c
new file mode 100644
index 0000000000000..76606f09fc427
--- /dev/null
+++ b/clang/test/OpenMP/split_iv_types.c
@@ -0,0 +1,24 @@
+/* Non-int IV types with split. */
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s --check-prefix=U32
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s --check-prefix=I64
+
+extern void body(unsigned int);
+extern void body64(long);
+
+// U32-LABEL: define {{.*}} @unsigned_iv
+// U32: .split.iv
+// U32-DAG: icmp ult i32
+void unsigned_iv(void) {
+#pragma omp split counts(2, omp_fill)
+ for (unsigned i = 0; i < 10U; ++i)
+ body(i);
+}
+
+// I64-LABEL: define {{.*}} @long_iv
+// I64: .split.iv
+// I64-DAG: icmp slt i64
+void long_iv(void) {
+#pragma omp split counts(2, omp_fill)
+ for (long i = 0; i < 10L; ++i)
+ body64(i);
+}
diff --git a/clang/test/OpenMP/split_loop_styles.cpp b/clang/test/OpenMP/split_loop_styles.cpp
new file mode 100644
index 0000000000000..0aa61b20a87bd
--- /dev/null
+++ b/clang/test/OpenMP/split_loop_styles.cpp
@@ -0,0 +1,14 @@
+// Outer-declared iteration variable + split.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+extern "C" void body(int);
+
+// CHECK-LABEL: define {{.*}} @outer_iv(
+// CHECK: .split.iv
+extern "C" void outer_iv(int n) {
+ int i;
+#pragma omp split counts(3, omp_fill)
+ for (i = 0; i < n; ++i)
+ body(i);
+}
diff --git a/clang/test/OpenMP/split_member_ctor.cpp b/clang/test/OpenMP/split_member_ctor.cpp
new file mode 100644
index 0000000000000..e869602e1a84f
--- /dev/null
+++ b/clang/test/OpenMP/split_member_ctor.cpp
@@ -0,0 +1,20 @@
+// Split on loop in constructor using member-related bound.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+extern "C" void body(int);
+
+struct S {
+ int n;
+ S() : n(10) {
+#pragma omp split counts(3, omp_fill)
+ for (int i = 0; i < n; ++i)
+ body(i);
+ }
+};
+
+// CHECK-LABEL: define {{.*}} @_ZN1SC1Ev
+// CHECK: .split.iv
+void use_s() {
+ S s;
+}
diff --git a/clang/test/OpenMP/split_messages.cpp b/clang/test/OpenMP/split_messages.cpp
new file mode 100644
index 0000000000000..b77a63ada9086
--- /dev/null
+++ b/clang/test/OpenMP/split_messages.cpp
@@ -0,0 +1,108 @@
+// OpenMP split / counts: parse and semantic diagnostics.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++17 -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+
+void body(int);
+
+void parse_and_clause_errors() {
+
+ // Malformed `counts` — missing '('
+ // expected-error at +1 {{expected '('}}
+ #pragma omp split counts
+ ;
+
+ // Empty `counts` list
+ // expected-error at +1 {{expected expression}}
+ #pragma omp split counts()
+ ;
+
+ // Truncated list / missing ')'
+ // expected-error at +1 {{expected ')'}} expected-note at +1 {{to match this '('}}
+ #pragma omp split counts(3
+ for (int i = 0; i < 7; ++i)
+ ;
+
+ // Trailing comma only
+ // expected-error at +1 {{expected expression}}
+ #pragma omp split counts(3,)
+ ;
+
+ // Expression after comma missing
+ // expected-error at +2 {{expected expression}}
+ // expected-error at +1 {{expected ')'}} expected-note at +1 {{to match this '('}}
+ #pragma omp split counts(3,
+ ;
+
+ // Incomplete arithmetic in count (like `tile_messages` sizes(5+))
+ // expected-error at +2 {{expected expression}}
+ // expected-error at +1 {{expected ')'}} expected-note at +1 {{to match this '('}}
+ #pragma omp split counts(5+
+ ;
+
+ // `for` keyword not a constant-expression operand
+ // expected-error at +1 {{expected expression}}
+ #pragma omp split counts(for)
+ ;
+
+ // Duplicate `counts` clauses
+ // expected-error at +1 {{directive '#pragma omp split' cannot contain more than one 'counts' clause}}
+ #pragma omp split counts(2, omp_fill) counts(3, omp_fill)
+ for (int i = 0; i < 7; ++i)
+ ;
+
+ // Disallowed extra clause
+ // expected-error at +1 {{unexpected OpenMP clause 'collapse' in directive '#pragma omp split'}}
+ #pragma omp split counts(2, omp_fill) collapse(2)
+ for (int i = 0; i < 7; ++i)
+ ;
+
+ // Non-relational loop condition (canonical loop check)
+ #pragma omp split counts(omp_fill)
+ // expected-error at +1 {{condition of OpenMP for loop must be a relational comparison ('<', '<=', '>', '>=', or '!=') of loop variable 'i'}}
+ for (int i = 0; i / 3 < 7; ++i)
+ ;
+
+ // More than one `omp_fill`
+ // expected-error at +1 {{exactly one 'omp_fill' must appear in the 'counts' clause}}
+ #pragma omp split counts(omp_fill, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+
+ // No `omp_fill` at all — also triggers "exactly one" diagnostic.
+ // expected-error at +1 {{exactly one 'omp_fill' must appear in the 'counts' clause}}
+ #pragma omp split counts(2, 3)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+
+ // Positive: `omp_fill` may appear at any position in `counts` (not required to be last).
+ #pragma omp split counts(omp_fill, 2)
+ for (int i = 0; i < 10; ++i)
+ body(i);
+
+ // OpenMP 6.0: non-`omp_fill` list items must be integral constant expressions.
+ {
+ int v = 3; // expected-note {{declared here}}
+ #pragma omp split counts(v, omp_fill) // expected-error {{expression is not an integral constant expression}} \
+ // expected-note {{read of non-const variable 'v' is not allowed in a constant expression}}
+ for (int i = 0; i < 10; ++i)
+ body(i);
+ }
+}
+
+void associated_statement_diagnostics() {
+ {
+ // expected-error at +2 {{expected statement}}
+ #pragma omp split counts(omp_fill)
+ }
+
+ // Not a `for` loop (contrast `split_diag_errors.c` / `while`)
+ // expected-error at +2 {{statement after '#pragma omp split' must be a for loop}}
+ #pragma omp split counts(omp_fill)
+ int b = 0;
+
+ // expected-warning at +2 {{extra tokens at the end of '#pragma omp split' are ignored}}
+ // expected-error at +1 {{directive '#pragma omp split' requires the 'counts' clause}}
+ #pragma omp split foo
+ for (int i = 0; i < 7; ++i)
+ ;
+}
diff --git a/clang/test/OpenMP/split_nested_outer_only.c b/clang/test/OpenMP/split_nested_outer_only.c
new file mode 100644
index 0000000000000..578a11212c658
--- /dev/null
+++ b/clang/test/OpenMP/split_nested_outer_only.c
@@ -0,0 +1,12 @@
+// Split attaches to the outer canonical `for`; inner loop stays unsplit.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+// Exactly one split IV — the outer loop; inner `for` uses plain `i`/`j` control flow.
+// CHECK-COUNT-1: .split.iv
+void f(void) {
+#pragma omp split counts(omp_fill)
+ for (int i = 0; i < 4; ++i)
+ for (int j = 0; j < 4; ++j) {
+ }
+}
diff --git a/clang/test/OpenMP/split_offload_codegen.cpp b/clang/test/OpenMP/split_offload_codegen.cpp
new file mode 100644
index 0000000000000..d212fdad14520
--- /dev/null
+++ b/clang/test/OpenMP/split_offload_codegen.cpp
@@ -0,0 +1,27 @@
+// Split inside `#pragma omp target` — host and device IR show `.split.iv`.
+//
+// RUN: %clang_cc1 -DCK_SPLIT -verify -fopenmp -fopenmp-version=60 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -o - 2>&1 | FileCheck -check-prefix=HOST %s
+// RUN: %clang_cc1 -DCK_SPLIT -verify -fopenmp -fopenmp-version=60 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-split-host.bc
+// RUN: %clang_cc1 -DCK_SPLIT -verify -fopenmp -fopenmp-version=60 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-split-host.bc -o - 2>&1 | FileCheck -check-prefix=DEVICE %s
+
+// expected-no-diagnostics
+
+#ifdef CK_SPLIT
+extern "C" void body(int);
+
+void host_split_in_target(int n) {
+#pragma omp target map(to : n)
+ {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < n; ++i)
+ body(i);
+ }
+}
+
+// HOST: define {{.*}}void {{.*}}host_split_in_target
+// HOST: .split.iv
+// HOST: __tgt_target_kernel
+
+// DEVICE: define {{.*}}void @__omp_offloading_
+// DEVICE: .split.iv
+#endif
diff --git a/clang/test/OpenMP/split_omp_fill.c b/clang/test/OpenMP/split_omp_fill.c
new file mode 100644
index 0000000000000..f2e9a132dcf1e
--- /dev/null
+++ b/clang/test/OpenMP/split_omp_fill.c
@@ -0,0 +1,36 @@
+/* Split + counts with omp_fill: syntax, AST dump, ast-print, IR. */
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+// expected-no-diagnostics
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -ast-dump %s | FileCheck %s --check-prefix=DUMP
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -ast-print %s | FileCheck %s --check-prefix=PRINT
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM
+
+void body(int);
+
+// PRINT-LABEL: void foo(
+// DUMP-LABEL: FunctionDecl {{.*}} foo
+void foo(int n) {
+ // PRINT: #pragma omp split counts(3, omp_fill)
+ // DUMP: OMPSplitDirective
+ // DUMP-NEXT: |-OMPCountsClause
+ // DUMP-NEXT: | |-ConstantExpr {{.*}} 'int'
+ // DUMP-NEXT: | | |-value: Int 3
+ // DUMP-NEXT: | | `-IntegerLiteral {{.*}} 'int' 3
+ // DUMP-NEXT: | `-{{.*}}
+ // DUMP-NEXT: {{.*}}`-ForStmt
+#pragma omp split counts(3, omp_fill)
+ // PRINT: for (int i = 0; i < n; ++i)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+// LLVM-LABEL: define {{.*}}void @foo(
+// LLVM: .split.iv.0.i
+// LLVM: icmp slt i32 {{.*}}, 3
+// LLVM: call void @body(
+// LLVM: store i32 3, ptr %.split.iv.1.i
+// LLVM: icmp slt i32 {{.*}}, %{{.*}}
+// LLVM: call void @body(
diff --git a/clang/test/OpenMP/split_openmp_version.cpp b/clang/test/OpenMP/split_openmp_version.cpp
new file mode 100644
index 0000000000000..d49d50970d0db
--- /dev/null
+++ b/clang/test/OpenMP/split_openmp_version.cpp
@@ -0,0 +1,22 @@
+// `#pragma omp split` / `counts` require OpenMP 6.x in this implementation.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++17 -fopenmp -fopenmp-version=60 -fsyntax-only -DONLY_OK -verify %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++17 -fopenmp -fopenmp-version=52 -fsyntax-only -DONLY_BAD52 -verify=expected52 %s
+
+#if defined(ONLY_OK)
+void ok60(void) {
+#pragma omp split counts(omp_fill)
+ for (int i = 0; i < 10; ++i) {
+ }
+}
+// expected-no-diagnostics
+#endif
+
+#if defined(ONLY_BAD52)
+// expected52-error at +2 {{unexpected OpenMP clause 'counts' in directive '#pragma omp split'}}
+void bad52(void) {
+#pragma omp split counts(omp_fill)
+ for (int i = 0; i < 10; ++i) {
+ }
+}
+#endif
diff --git a/clang/test/OpenMP/split_opts_simd_debug.cpp b/clang/test/OpenMP/split_opts_simd_debug.cpp
new file mode 100644
index 0000000000000..d378707ee66c7
--- /dev/null
+++ b/clang/test/OpenMP/split_opts_simd_debug.cpp
@@ -0,0 +1,30 @@
+// Optimized split IR at -O1; split + `-fopenmp-simd` syntax-only; -g debug-info smoke.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O1 -emit-llvm -DTEST_BODY %s -o - | FileCheck %s --check-prefix=O1
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp-simd -fopenmp-version=60 -fsyntax-only -verify -DTEST_SIMD %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm -debug-info-kind=limited -DTEST_BODY %s -o - | FileCheck %s --check-prefix=DBG
+
+extern "C" void body(int);
+
+#if defined(TEST_SIMD)
+// expected-no-diagnostics
+void simd_ok(int n) {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+#endif
+
+#if defined(TEST_BODY)
+// O1-LABEL: define {{.*}} @_Z4testi
+// O1: .split.iv
+// DBG-LABEL: define {{.*}} @_Z4testi
+// DBG: .split.iv
+// DBG: !dbg
+void test(int n) {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+#endif
+
diff --git a/clang/test/OpenMP/split_parallel_split.cpp b/clang/test/OpenMP/split_parallel_split.cpp
new file mode 100644
index 0000000000000..bf30373f9bb8c
--- /dev/null
+++ b/clang/test/OpenMP/split_parallel_split.cpp
@@ -0,0 +1,15 @@
+// Valid nesting — `split` inside `omp parallel` (contrast `teams` rejection in split_teams_nesting.cpp).
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define {{.*}} @f(
+// CHECK: __kmpc_fork_call
+// CHECK: .split.iv
+extern "C" void f(void) {
+#pragma omp parallel
+ {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < 10; ++i) {
+ }
+ }
+}
diff --git a/clang/test/OpenMP/split_pch_codegen.cpp b/clang/test/OpenMP/split_pch_codegen.cpp
new file mode 100644
index 0000000000000..c31028bebe5e0
--- /dev/null
+++ b/clang/test/OpenMP/split_pch_codegen.cpp
@@ -0,0 +1,43 @@
+// PCH round-trip for AST dump/print and host IR (split + counts).
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+// expected-no-diagnostics
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -ast-dump %s | FileCheck %s --check-prefix=DUMP
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -ast-print %s | FileCheck %s --check-prefix=PRINT
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -emit-pch -o %t %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -include-pch %t -ast-dump-all %s | FileCheck %s --check-prefix=DUMP
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -include-pch %t -ast-print %s | FileCheck %s --check-prefix=PRINT
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2
+
+#ifndef HEADER
+#define HEADER
+
+extern "C" void body(int);
+
+// PRINT-LABEL: void foo(
+// DUMP-LABEL: FunctionDecl {{.*}} foo
+void foo(int n) {
+ // PRINT: #pragma omp split counts(3, omp_fill)
+ // DUMP: OMPSplitDirective
+ // DUMP-NEXT: OMPCountsClause
+ // DUMP: IntegerLiteral {{.*}} 3
+#pragma omp split counts(3, omp_fill)
+ // DUMP: ForStmt
+ for (int i = 0; i < n; ++i)
+ body(i);
+}
+
+// CHECK1-LABEL: define {{.*}} @_Z3foo
+// CHECK1: .split.iv
+// CHECK1: icmp
+// CHECK1: call void @body
+
+// CHECK2-LABEL: define {{.*}} @_Z3foo
+// CHECK2: .split.iv
+// CHECK2: icmp
+// CHECK2: call void @body
+
+#endif /* HEADER */
diff --git a/clang/test/OpenMP/split_range_for_diag.cpp b/clang/test/OpenMP/split_range_for_diag.cpp
new file mode 100644
index 0000000000000..2c6a4b50d84bd
--- /dev/null
+++ b/clang/test/OpenMP/split_range_for_diag.cpp
@@ -0,0 +1,25 @@
+// C++ range-for + split: verify syntax, IR, and PreInits (range evaluated once).
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -std=c++17 -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+// expected-no-diagnostics
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -std=c++17 -fopenmp -fopenmp-version=60 -emit-llvm %s -o - | FileCheck %s
+
+extern "C" void body(int);
+
+// CHECK-LABEL: define dso_local void @_Z10range_fillv
+// CHECK: __range
+// CHECK: __begin
+// CHECK: __end
+// CHECK: .split.iv.0
+// CHECK: icmp slt i64 {{.*}}, 2
+// CHECK: call void @body
+// CHECK: .split.iv.1
+// CHECK: icmp slt
+// CHECK: call void @body
+void range_fill() {
+ int a[] = {10, 20, 30, 40};
+#pragma omp split counts(2, omp_fill)
+ for (int x : a)
+ body(x);
+}
diff --git a/clang/test/OpenMP/split_serialize_module.cpp b/clang/test/OpenMP/split_serialize_module.cpp
new file mode 100644
index 0000000000000..861e9a8bb8034
--- /dev/null
+++ b/clang/test/OpenMP/split_serialize_module.cpp
@@ -0,0 +1,24 @@
+// C++20 module interface with `#pragma omp split` — emit BMI + import; AST retains directive.
+//
+// RUN: rm -rf %t && split-file %s %t && cd %t
+// RUN: %clang_cc1 -std=c++20 -fopenmp -fopenmp-version=60 -triple x86_64-unknown-linux-gnu %t/SplitMod.cppm -emit-module-interface -o %t/SplitMod.pcm
+// RUN: %clang_cc1 -std=c++20 -fopenmp -fopenmp-version=60 -triple x86_64-unknown-linux-gnu %t/UseSplitMod.cpp -fmodule-file=SplitMod=%t/SplitMod.pcm -ast-dump-all | FileCheck %t/SplitMod.cppm
+
+// expected-no-diagnostics
+
+//--- SplitMod.cppm
+module;
+export module SplitMod;
+
+export void splitfoo(int n) {
+// CHECK: OMPSplitDirective
+// CHECK: OMPCountsClause
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < n; ++i) {
+ }
+}
+
+//--- UseSplitMod.cpp
+import SplitMod;
+
+void g(void) { splitfoo(10); }
diff --git a/clang/test/OpenMP/split_teams_nesting.cpp b/clang/test/OpenMP/split_teams_nesting.cpp
new file mode 100644
index 0000000000000..1120a7ccae671
--- /dev/null
+++ b/clang/test/OpenMP/split_teams_nesting.cpp
@@ -0,0 +1,13 @@
+// Split is not valid nested inside `teams` (host diagnostic).
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+
+void g(void) {
+#pragma omp teams
+ {
+// expected-error at +1 {{region cannot be closely nested inside 'teams' region}}
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < 10; ++i) {
+ }
+ }
+}
diff --git a/clang/test/OpenMP/split_template_nttp.cpp b/clang/test/OpenMP/split_template_nttp.cpp
new file mode 100644
index 0000000000000..1cf0ee39c3c73
--- /dev/null
+++ b/clang/test/OpenMP/split_template_nttp.cpp
@@ -0,0 +1,15 @@
+// Non-type template parameter as counts operand — IR after instantiation.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -std=c++17 -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define {{.*}} @_Z1fILi5EEvv
+// CHECK: .split.iv
+// CHECK: icmp slt i32{{.*}} 5
+template <int N>
+void f() {
+#pragma omp split counts(N, omp_fill)
+ for (int i = 0; i < 20; ++i) {
+ }
+}
+
+template void f<5>();
diff --git a/clang/test/OpenMP/split_templates.cpp b/clang/test/OpenMP/split_templates.cpp
new file mode 100644
index 0000000000000..f6a4dfbfdc81b
--- /dev/null
+++ b/clang/test/OpenMP/split_templates.cpp
@@ -0,0 +1,30 @@
+// Dependent template defers transformation; explicit instantiation emits IR.
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -std=c++17 -fopenmp -fopenmp-version=60 -ast-dump -DTEST_DEP %s | FileCheck %s --check-prefix=DEP
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x c++ -std=c++17 -fopenmp -fopenmp-version=60 -O0 -emit-llvm -DTEST_INST %s -o - | FileCheck %s --check-prefix=LLVM
+
+extern "C" void body(int);
+
+#if defined(TEST_DEP)
+template <typename T>
+void dep_split(T n) {
+#pragma omp split counts(2, omp_fill)
+ for (T i = 0; i < n; ++i)
+ body((int)i);
+}
+// DEP-LABEL: dep_split
+// DEP: OMPSplitDirective
+// DEP: ForStmt
+#endif
+
+#if defined(TEST_INST)
+template <typename T>
+void dep_split(T n) {
+#pragma omp split counts(2, omp_fill)
+ for (T i = 0; i < n; ++i)
+ body((int)i);
+}
+template void dep_split<int>(int);
+// LLVM: .split.iv
+// LLVM: call void @body
+#endif
diff --git a/clang/test/OpenMP/split_trip_volatile.c b/clang/test/OpenMP/split_trip_volatile.c
new file mode 100644
index 0000000000000..01b5e7f534d98
--- /dev/null
+++ b/clang/test/OpenMP/split_trip_volatile.c
@@ -0,0 +1,14 @@
+// Volatile trip count — IR shows `load volatile` of bound + split IVs (omp_fill segment).
+//
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=60 -O0 -emit-llvm %s -o - | FileCheck %s
+
+volatile int n;
+
+// CHECK-LABEL: define {{.*}} @f
+// CHECK: load volatile i32, ptr @n
+// CHECK: .split.iv
+void f(void) {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < n; ++i) {
+ }
+}
diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp
index 3ee37ed2dfc27..f1532d0b064b3 100644
--- a/clang/tools/libclang/CIndex.cpp
+++ b/clang/tools/libclang/CIndex.cpp
@@ -2362,6 +2362,11 @@ void OMPClauseEnqueue::VisitOMPSizesClause(const OMPSizesClause *C) {
Visitor->AddStmt(E);
}
+void OMPClauseEnqueue::VisitOMPCountsClause(const OMPCountsClause *C) {
+ for (auto E : C->getCountsRefs())
+ Visitor->AddStmt(E);
+}
+
void OMPClauseEnqueue::VisitOMPPermutationClause(
const OMPPermutationClause *C) {
for (auto E : C->getArgsRefs())
@@ -6326,6 +6331,8 @@ CXString clang_getCursorKindSpelling(enum CXCursorKind Kind) {
return cxstring::createRef("OMPInterchangeDirective");
case CXCursor_OMPFuseDirective:
return cxstring::createRef("OMPFuseDirective");
+ case CXCursor_OMPSplitDirective:
+ return cxstring::createRef("OMPSplitDirective");
case CXCursor_OMPForDirective:
return cxstring::createRef("OMPForDirective");
case CXCursor_OMPForSimdDirective:
diff --git a/clang/tools/libclang/CXCursor.cpp b/clang/tools/libclang/CXCursor.cpp
index d31d2c0c9bb67..242380c68c667 100644
--- a/clang/tools/libclang/CXCursor.cpp
+++ b/clang/tools/libclang/CXCursor.cpp
@@ -697,6 +697,9 @@ CXCursor cxcursor::MakeCXCursor(const Stmt *S, const Decl *Parent,
case Stmt::OMPReverseDirectiveClass:
K = CXCursor_OMPReverseDirective;
break;
+ case Stmt::OMPSplitDirectiveClass:
+ K = CXCursor_OMPSplitDirective;
+ break;
case Stmt::OMPInterchangeDirectiveClass:
K = CXCursor_OMPInterchangeDirective;
break;
diff --git a/clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp b/clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
index 7338ff5f302f6..4190d4703e37d 100644
--- a/clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
+++ b/clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
@@ -7,7 +7,9 @@
//===----------------------------------------------------------------------===//
#include "ASTMatchersTest.h"
+#include "clang/AST/OpenMPClause.h"
#include "clang/AST/PrettyPrinter.h"
+#include "clang/AST/StmtOpenMP.h"
#include "clang/ASTMatchers/ASTMatchFinder.h"
#include "clang/ASTMatchers/ASTMatchers.h"
#include "clang/Tooling/Tooling.h"
@@ -3103,6 +3105,66 @@ TEST(ASTMatchersTestOpenMP, OMPTargetUpdateDirective_CountExpression) {
}
}
+// OpenMP 6 split directive / counts clause
+TEST(ASTMatchersTestOpenMP, OMPSplitDirective) {
+ auto Matcher = stmt(ompSplitDirective(hasStructuredBlock(forStmt())));
+
+ StringRef SplitOk = R"(
+void f() {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < 10; ++i) {}
+}
+)";
+ EXPECT_TRUE(matchesWithOpenMP60(SplitOk, Matcher));
+
+ StringRef ParallelOnly = R"(
+void f() {
+#pragma omp parallel
+ ;
+}
+)";
+ EXPECT_TRUE(notMatchesWithOpenMP60(ParallelOnly, Matcher));
+}
+
+TEST(ASTMatchersTestOpenMP, OMPSplitDirective_HasCountsClause) {
+ auto Matcher = stmt(ompSplitDirective(hasAnyClause(ompCountsClause())));
+
+ StringRef Source0 = R"(
+void f() {
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i < 10; ++i) {}
+}
+)";
+ EXPECT_TRUE(matchesWithOpenMP60(Source0, Matcher));
+}
+
+TEST(ASTMatchersTestOpenMP, OMPCountsClause_OmpFillOperand) {
+ StringRef Source0 = R"(
+void f() {
+#pragma omp split counts(1, omp_fill)
+ for (int i = 0; i < 10; ++i) {}
+}
+)";
+ auto AST = tooling::buildASTFromCodeWithArgs(
+ Source0, {"-std=gnu++11", "-target", "i386-unknown-unknown",
+ "-fopenmp=libomp", "-fopenmp-version=60"});
+ ASSERT_TRUE(AST);
+ auto Results = match(ompSplitDirective().bind("split"), AST->getASTContext());
+ ASSERT_EQ(Results.size(), 1u);
+ const auto *Dir = Results[0].getNodeAs<OMPSplitDirective>("split");
+ ASSERT_TRUE(Dir);
+ const OMPCountsClause *Counts = nullptr;
+ for (OMPClause *C : Dir->clauses()) {
+ if ((Counts = dyn_cast<OMPCountsClause>(C)))
+ break;
+ }
+ ASSERT_TRUE(Counts);
+ ASSERT_EQ(Counts->getNumCounts(), 2u);
+ EXPECT_TRUE(Counts->hasOmpFill());
+ EXPECT_EQ(*Counts->getOmpFillIndex(), 1u);
+ EXPECT_FALSE(Counts->getCountsRefs()[1]);
+}
+
TEST(ASTMatchersTest, Finder_DynamicOnlyAcceptsSomeMatchers) {
MatchFinder Finder;
EXPECT_TRUE(Finder.addDynamicMatcher(decl(), nullptr));
diff --git a/clang/unittests/ASTMatchers/ASTMatchersTest.h b/clang/unittests/ASTMatchers/ASTMatchersTest.h
index c1d4daea2c9f1..932e75360405b 100644
--- a/clang/unittests/ASTMatchers/ASTMatchersTest.h
+++ b/clang/unittests/ASTMatchers/ASTMatchersTest.h
@@ -289,6 +289,20 @@ testing::AssertionResult notMatchesWithOpenMP51(const Twine &Code,
{"-fopenmp=libomp", "-fopenmp-version=51"});
}
+template <typename T>
+testing::AssertionResult matchesWithOpenMP60(const Twine &Code,
+ const T &AMatcher) {
+ return matchesConditionally(Code, AMatcher, true,
+ {"-fopenmp=libomp", "-fopenmp-version=60"});
+}
+
+template <typename T>
+testing::AssertionResult notMatchesWithOpenMP60(const Twine &Code,
+ const T &AMatcher) {
+ return matchesConditionally(Code, AMatcher, false,
+ {"-fopenmp=libomp", "-fopenmp-version=60"});
+}
+
template <typename T>
testing::AssertionResult matchesWithFixedpoint(const std::string &Code,
const T &AMatcher) {
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.td b/llvm/include/llvm/Frontend/OpenMP/OMP.td
index d1dddf76152ec..0f2074c549c83 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMP.td
+++ b/llvm/include/llvm/Frontend/OpenMP/OMP.td
@@ -142,6 +142,7 @@ def OMPC_CopyPrivate : Clause<[Spelling<"copyprivate">]> {
let flangClass = "OmpObjectList";
}
def OMPC_Counts : Clause<[Spelling<"counts">]> {
+ let clangClass = "OMPCountsClause";
}
def OMPC_Default : Clause<[Spelling<"default">]> {
let clangClass = "OMPDefaultClause";
@@ -1203,16 +1204,6 @@ def OMP_EndSingle : Directive<[Spelling<"end single">]> {
let category = OMP_Single.category;
let languages = [L_Fortran];
}
-def OMP_Split : Directive<[Spelling<"split">]> {
- let allowedClauses = [
- VersionedClause<OMPC_Apply, 60>,
- ];
- let allowedOnceClauses = [
- VersionedClause<OMPC_Counts, 60>,
- ];
- let association = AS_LoopNest;
- let category = CA_Executable;
-}
def OMP_Target : Directive<[Spelling<"target">]> {
let allowedClauses = [
VersionedClause<OMPC_Allocate>,
@@ -1435,6 +1426,16 @@ def OMP_Stripe : Directive<[Spelling<"stripe">]> {
let association = AS_LoopNest;
let category = CA_Executable;
}
+def OMP_Split : Directive<[Spelling<"split">]> {
+ let allowedOnceClauses = [
+ VersionedClause<OMPC_Counts, 60>,
+ ];
+ let requiredClauses = [
+ VersionedClause<OMPC_Counts, 60>,
+ ];
+ let association = AS_LoopNest;
+ let category = CA_Executable;
+}
def OMP_Unknown : Directive<[Spelling<"unknown">]> {
let isDefault = true;
let association = AS_None;
diff --git a/openmp/runtime/test/transform/split/fill_first.c b/openmp/runtime/test/transform/split/fill_first.c
new file mode 100644
index 0000000000000..12568f6896d18
--- /dev/null
+++ b/openmp/runtime/test/transform/split/fill_first.c
@@ -0,0 +1,23 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ printf("do\n");
+#pragma omp split counts(omp_fill, 2)
+ for (int i = 0; i < 7; ++i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=5
+// CHECK-NEXT: i=6
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/foreach.cpp b/openmp/runtime/test/transform/split/foreach.cpp
new file mode 100644
index 0000000000000..846449b9d86ca
--- /dev/null
+++ b/openmp/runtime/test/transform/split/foreach.cpp
@@ -0,0 +1,24 @@
+// RUN: %libomp-cxx-compile-and-run | FileCheck %s --match-full-lines
+
+#include <cstdlib>
+#include <cstdio>
+#include <vector>
+
+int main() {
+ std::vector<int> v = {10, 20, 30, 40, 50, 60};
+ printf("do\n");
+#pragma omp split counts(2, omp_fill)
+ for (int x : v)
+ printf("x=%d\n", x);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: x=10
+// CHECK-NEXT: x=20
+// CHECK-NEXT: x=30
+// CHECK-NEXT: x=40
+// CHECK-NEXT: x=50
+// CHECK-NEXT: x=60
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/intfor.c b/openmp/runtime/test/transform/split/intfor.c
new file mode 100644
index 0000000000000..321fa5ca51f08
--- /dev/null
+++ b/openmp/runtime/test/transform/split/intfor.c
@@ -0,0 +1,26 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ printf("do\n");
+#pragma omp split counts(3, omp_fill, 2)
+ for (int i = 0; i < 10; ++i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=5
+// CHECK-NEXT: i=6
+// CHECK-NEXT: i=7
+// CHECK-NEXT: i=8
+// CHECK-NEXT: i=9
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/intfor_negstart.c b/openmp/runtime/test/transform/split/intfor_negstart.c
new file mode 100644
index 0000000000000..1e3860bba2d53
--- /dev/null
+++ b/openmp/runtime/test/transform/split/intfor_negstart.c
@@ -0,0 +1,27 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ int n = 8;
+ printf("do\n");
+#pragma omp split counts(1, omp_fill, 1)
+ for (int i = -1; i <= n; ++i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=-1
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=5
+// CHECK-NEXT: i=6
+// CHECK-NEXT: i=7
+// CHECK-NEXT: i=8
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/iterfor.cpp b/openmp/runtime/test/transform/split/iterfor.cpp
new file mode 100644
index 0000000000000..60ecbb374f6e3
--- /dev/null
+++ b/openmp/runtime/test/transform/split/iterfor.cpp
@@ -0,0 +1,139 @@
+// RUN: %libomp-cxx20-compile-and-run | FileCheck %s --match-full-lines
+
+#include <cstdlib>
+#include <cstdarg>
+#include <cstdio>
+
+struct Reporter {
+ const char *name;
+
+ Reporter(const char *name) : name(name) { print("ctor"); }
+
+ Reporter() : name("<anon>") { print("ctor"); }
+
+ Reporter(const Reporter &that) : name(that.name) { print("copy ctor"); }
+
+ Reporter(Reporter &&that) : name(that.name) { print("move ctor"); }
+
+ ~Reporter() { print("dtor"); }
+
+ const Reporter &operator=(const Reporter &that) {
+ print("copy assign");
+ this->name = that.name;
+ return *this;
+ }
+
+ const Reporter &operator=(Reporter &&that) {
+ print("move assign");
+ this->name = that.name;
+ return *this;
+ }
+
+ struct Iterator {
+ const Reporter *owner;
+ int pos;
+
+ Iterator(const Reporter *owner, int pos) : owner(owner), pos(pos) {}
+
+ Iterator(const Iterator &that) : owner(that.owner), pos(that.pos) {
+ owner->print("iterator copy ctor");
+ }
+
+ Iterator(Iterator &&that) : owner(that.owner), pos(that.pos) {
+ owner->print("iterator move ctor");
+ }
+
+ ~Iterator() { owner->print("iterator dtor"); }
+
+ const Iterator &operator=(const Iterator &that) {
+ owner->print("iterator copy assign");
+ this->owner = that.owner;
+ this->pos = that.pos;
+ return *this;
+ }
+
+ const Iterator &operator=(Iterator &&that) {
+ owner->print("iterator move assign");
+ this->owner = that.owner;
+ this->pos = that.pos;
+ return *this;
+ }
+
+ bool operator==(const Iterator &that) const {
+ owner->print("iterator %d == %d", this->pos, that.pos);
+ return this->pos == that.pos;
+ }
+
+ bool operator!=(const Iterator &that) const {
+ owner->print("iterator %d != %d", this->pos, that.pos);
+ return this->pos != that.pos;
+ }
+
+ Iterator &operator++() {
+ owner->print("iterator prefix ++");
+ pos += 1;
+ return *this;
+ }
+
+ Iterator operator++(int) {
+ owner->print("iterator postfix ++");
+ auto result = *this;
+ pos += 1;
+ return result;
+ }
+
+ int operator*() const {
+ owner->print("iterator deref: %d", pos);
+ return pos;
+ }
+
+ size_t operator-(const Iterator &that) const {
+ int result = this->pos - that.pos;
+ owner->print("iterator distance: %d", result);
+ return result;
+ }
+
+ Iterator operator+(int steps) const {
+ owner->print("iterator advance: %d += %d", this->pos, steps);
+ return Iterator(owner, pos + steps);
+ }
+ };
+
+ Iterator begin() const {
+ print("begin()");
+ return Iterator(this, 0);
+ }
+
+ Iterator end() const {
+ print("end()");
+ return Iterator(this, 4);
+ }
+
+ void print(const char *msg, ...) const {
+ va_list args;
+ va_start(args, msg);
+ printf("[%s] ", name);
+ vprintf(msg, args);
+ printf("\n");
+ va_end(args);
+ }
+};
+
+int main() {
+ printf("do\n");
+ Reporter range("range");
+#pragma omp split counts(1, omp_fill, 1)
+ for (auto it = range.begin(); it != range.end(); ++it)
+ printf("v=%d\n", *it);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK: [range] ctor
+// CHECK: v=0
+// CHECK: v=1
+// CHECK: v=2
+// CHECK: v=3
+// CHECK: done
+// CHECK: [range] dtor
diff --git a/openmp/runtime/test/transform/split/leq_bound.c b/openmp/runtime/test/transform/split/leq_bound.c
new file mode 100644
index 0000000000000..81061fe430ae4
--- /dev/null
+++ b/openmp/runtime/test/transform/split/leq_bound.c
@@ -0,0 +1,22 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ int n = 4;
+ printf("do\n");
+#pragma omp split counts(2, omp_fill)
+ for (int i = 0; i <= n; ++i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/lit.local.cfg b/openmp/runtime/test/transform/split/lit.local.cfg
new file mode 100644
index 0000000000000..beb73ea04165d
--- /dev/null
+++ b/openmp/runtime/test/transform/split/lit.local.cfg
@@ -0,0 +1,5 @@
+# The split directive's counts clause requires OpenMP 6.0.
+for i, (pattern, replacement) in enumerate(config.substitutions):
+ if pattern == "%openmp_flags":
+ config.substitutions[i] = (pattern, replacement + " -fopenmp-version=60")
+ break
diff --git a/openmp/runtime/test/transform/split/negative_incr.c b/openmp/runtime/test/transform/split/negative_incr.c
new file mode 100644
index 0000000000000..ce537db067f06
--- /dev/null
+++ b/openmp/runtime/test/transform/split/negative_incr.c
@@ -0,0 +1,22 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ printf("do\n");
+#pragma omp split counts(1, omp_fill, 1)
+ for (int i = 5; i >= 0; --i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=5
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=0
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/nonconstant_incr.c b/openmp/runtime/test/transform/split/nonconstant_incr.c
new file mode 100644
index 0000000000000..d594a437f2ab2
--- /dev/null
+++ b/openmp/runtime/test/transform/split/nonconstant_incr.c
@@ -0,0 +1,22 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ int n = 19;
+ int c = 3;
+ printf("do\n");
+#pragma omp split counts(1, omp_fill, 1)
+ for (int i = 7; i < n; i += c)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=7
+// CHECK-NEXT: i=10
+// CHECK-NEXT: i=13
+// CHECK-NEXT: i=16
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/parallel-split-intfor.c b/openmp/runtime/test/transform/split/parallel-split-intfor.c
new file mode 100644
index 0000000000000..0b9bd7df5027e
--- /dev/null
+++ b/openmp/runtime/test/transform/split/parallel-split-intfor.c
@@ -0,0 +1,27 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ printf("do\n");
+#pragma omp parallel num_threads(1)
+ {
+#pragma omp split counts(2, omp_fill, 2)
+ for (int i = 0; i < 8; ++i)
+ printf("i=%d\n", i);
+ }
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=5
+// CHECK-NEXT: i=6
+// CHECK-NEXT: i=7
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/single_fill.c b/openmp/runtime/test/transform/split/single_fill.c
new file mode 100644
index 0000000000000..4ef10bf3b4d26
--- /dev/null
+++ b/openmp/runtime/test/transform/split/single_fill.c
@@ -0,0 +1,23 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ int n = 6;
+ printf("do\n");
+#pragma omp split counts(omp_fill)
+ for (int i = 0; i < n; ++i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=5
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/three_segments.c b/openmp/runtime/test/transform/split/three_segments.c
new file mode 100644
index 0000000000000..f34b640a86710
--- /dev/null
+++ b/openmp/runtime/test/transform/split/three_segments.c
@@ -0,0 +1,26 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ printf("do\n");
+#pragma omp split counts(2, 2, omp_fill)
+ for (int i = 0; i < 10; ++i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=5
+// CHECK-NEXT: i=6
+// CHECK-NEXT: i=7
+// CHECK-NEXT: i=8
+// CHECK-NEXT: i=9
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/trip_one.c b/openmp/runtime/test/transform/split/trip_one.c
new file mode 100644
index 0000000000000..5f00d25239685
--- /dev/null
+++ b/openmp/runtime/test/transform/split/trip_one.c
@@ -0,0 +1,32 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+// Tiny trip counts: trip=1 with counts(1, omp_fill) and trip=0.
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ int n;
+
+ n = 1;
+ printf("trip1\n");
+#pragma omp split counts(1, omp_fill)
+ for (int i = 0; i < n; ++i)
+ printf("i=%d\n", i);
+ printf("end1\n");
+
+ n = 0;
+ printf("trip0\n");
+#pragma omp split counts(omp_fill)
+ for (int i = 0; i < n; ++i)
+ printf("i=%d\n", i);
+ printf("end0\n");
+
+ return EXIT_SUCCESS;
+}
+
+// CHECK: trip1
+// CHECK-NEXT: i=0
+// CHECK-NEXT: end1
+// CHECK-NEXT: trip0
+// CHECK-NEXT: end0
diff --git a/openmp/runtime/test/transform/split/unsigned_iv.c b/openmp/runtime/test/transform/split/unsigned_iv.c
new file mode 100644
index 0000000000000..ad096122d8cea
--- /dev/null
+++ b/openmp/runtime/test/transform/split/unsigned_iv.c
@@ -0,0 +1,24 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ printf("do\n");
+#pragma omp split counts(3, omp_fill)
+ for (unsigned i = 0; i < 8; ++i)
+ printf("i=%u\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: i=5
+// CHECK-NEXT: i=6
+// CHECK-NEXT: i=7
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/split/zero_first_segment.c b/openmp/runtime/test/transform/split/zero_first_segment.c
new file mode 100644
index 0000000000000..09cc526ed81ec
--- /dev/null
+++ b/openmp/runtime/test/transform/split/zero_first_segment.c
@@ -0,0 +1,21 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ printf("do\n");
+#pragma omp split counts(0, omp_fill)
+ for (int i = 0; i < 5; ++i)
+ printf("i=%d\n", i);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+// CHECK: do
+// CHECK-NEXT: i=0
+// CHECK-NEXT: i=1
+// CHECK-NEXT: i=2
+// CHECK-NEXT: i=3
+// CHECK-NEXT: i=4
+// CHECK-NEXT: done
>From b2f18d9f6f8d349c2ba26581f8a3566ad021bc87 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 13 Apr 2026 08:36:58 +0100
Subject: [PATCH 18/36] [AArch64] Fix legalization of bf16 ldexp. (#190805)
Similar to fp16 ldexp, we cannot create illegal types for bf16 during
lowering so should promote.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 9 ++-
llvm/test/Analysis/CostModel/AArch64/ldexp.ll | 10 +--
llvm/test/CodeGen/AArch64/ldexp.ll | 72 ++++++++++++++++++-
3 files changed, 81 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 4b6b0758006af..96ccd38e34117 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2164,11 +2164,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
- // LegalizeDAG currently can't expand fp16 LDEXP/FREXP on targets where i16
- // isn't legal.
- for (ISD::NodeType Op : {ISD::FLDEXP, ISD::STRICT_FLDEXP, ISD::FFREXP})
+ // LegalizeDAG currently can't expand fp16/bf16 LDEXP/FREXP on targets where
+ // i16 isn't legal.
+ for (ISD::NodeType Op : {ISD::FLDEXP, ISD::STRICT_FLDEXP, ISD::FFREXP}) {
if (isOperationExpand(Op, MVT::f16))
setOperationAction(Op, MVT::f16, Promote);
+ if (isOperationExpand(Op, MVT::bf16))
+ setOperationAction(Op, MVT::bf16, Promote);
+ }
}
const AArch64TargetMachine &AArch64TargetLowering::getTM() const {
diff --git a/llvm/test/Analysis/CostModel/AArch64/ldexp.ll b/llvm/test/Analysis/CostModel/AArch64/ldexp.ll
index 8cc8657468930..60ab7bc964680 100644
--- a/llvm/test/Analysis/CostModel/AArch64/ldexp.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/ldexp.ll
@@ -72,11 +72,11 @@ define void @ldexp_fp16() {
define void @ldexp_bf16() {
; CHECK-BASE-LABEL: 'ldexp_bf16'
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:1 Lat:10 SizeLat:10 for: %1 = call bfloat @llvm.ldexp.bf16.i32(bfloat poison, i32 poison)
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:22 CodeSize:3 Lat:22 SizeLat:22 for: %2 = call <2 x bfloat> @llvm.ldexp.v2bf16.v2i32(<2 x bfloat> poison, <2 x i32> poison)
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:46 CodeSize:7 Lat:46 SizeLat:46 for: %3 = call <4 x bfloat> @llvm.ldexp.v4bf16.v4i32(<4 x bfloat> poison, <4 x i32> poison)
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:94 CodeSize:15 Lat:94 SizeLat:94 for: %4 = call <8 x bfloat> @llvm.ldexp.v8bf16.v8i32(<8 x bfloat> poison, <8 x i32> poison)
-; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:188 CodeSize:30 Lat:188 SizeLat:188 for: %5 = call <16 x bfloat> @llvm.ldexp.v16bf16.v16i32(<16 x bfloat> poison, <16 x i32> poison)
+; CHECK-BASE-NEXT: Cost Model: Found costs of 1 for: %1 = call bfloat @llvm.ldexp.bf16.i32(bfloat poison, i32 poison)
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:3 Lat:4 SizeLat:4 for: %2 = call <2 x bfloat> @llvm.ldexp.v2bf16.v2i32(<2 x bfloat> poison, <2 x i32> poison)
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:7 Lat:10 SizeLat:10 for: %3 = call <4 x bfloat> @llvm.ldexp.v4bf16.v4i32(<4 x bfloat> poison, <4 x i32> poison)
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:22 CodeSize:15 Lat:22 SizeLat:22 for: %4 = call <8 x bfloat> @llvm.ldexp.v8bf16.v8i32(<8 x bfloat> poison, <8 x i32> poison)
+; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:44 CodeSize:30 Lat:44 SizeLat:44 for: %5 = call <16 x bfloat> @llvm.ldexp.v16bf16.v16i32(<16 x bfloat> poison, <16 x i32> poison)
; CHECK-BASE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; CHECK-SVE-LABEL: 'ldexp_bf16'
diff --git a/llvm/test/CodeGen/AArch64/ldexp.ll b/llvm/test/CodeGen/AArch64/ldexp.ll
index 2de20c294dcb3..308e861abb6d4 100644
--- a/llvm/test/CodeGen/AArch64/ldexp.ll
+++ b/llvm/test/CodeGen/AArch64/ldexp.ll
@@ -1,9 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck -check-prefixes=SVE,SVELINUX %s
-; RUN: llc -mtriple=aarch64 -global-isel < %s -o - | FileCheck -check-prefixes=GISEL %s
+; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 < %s -o - 2>&1 | FileCheck -check-prefixes=GISEL %s
; RUN: llc -mtriple=aarch64-windows-msvc -mattr=+sve < %s -o - | FileCheck -check-prefixes=SVE,SVEWINDOWS %s
; RUN: llc -mtriple=aarch64-windows-msvc < %s -o - | FileCheck -check-prefixes=WINDOWS %s
+; GISEL: warning: Instruction selection used fallback path for testExpbf16
+
define double @testExp(double %val, i32 %a) {
; SVE-LABEL: testExp:
; SVE: // %bb.0: // %entry
@@ -263,4 +265,70 @@ entry:
ret half %0
}
-declare half @llvm.ldexp.f16.i32(half, i32) memory(none)
+define bfloat @testExpbf16(bfloat %val, i32 %a) {
+; SVE-LABEL: testExpbf16:
+; SVE: // %bb.0: // %entry
+; SVE-NEXT: // kill: def $h0 killed $h0 def $d0
+; SVE-NEXT: fmov s1, w0
+; SVE-NEXT: ptrue p0.s
+; SVE-NEXT: shll v0.4s, v0.4h, #16
+; SVE-NEXT: fscale z0.s, p0/m, z0.s, z1.s
+; SVE-NEXT: fmov w8, s0
+; SVE-NEXT: fcmp s0, s0
+; SVE-NEXT: orr w9, w8, #0x400000
+; SVE-NEXT: csel w8, w9, w8, vs
+; SVE-NEXT: lsr w8, w8, #16
+; SVE-NEXT: fmov s0, w8
+; SVE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; SVE-NEXT: ret
+;
+; GISEL-LABEL: testExpbf16:
+; GISEL: // %bb.0: // %entry
+; GISEL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; GISEL-NEXT: .cfi_def_cfa_offset 16
+; GISEL-NEXT: .cfi_offset w30, -16
+; GISEL-NEXT: // kill: def $h0 killed $h0 def $d0
+; GISEL-NEXT: shll v0.4s, v0.4h, #16
+; GISEL-NEXT: // kill: def $s0 killed $s0 killed $q0
+; GISEL-NEXT: bl ldexpf
+; GISEL-NEXT: fmov w9, s0
+; GISEL-NEXT: mov w8, #32767 // =0x7fff
+; GISEL-NEXT: ubfx w10, w9, #16, #1
+; GISEL-NEXT: add w8, w9, w8
+; GISEL-NEXT: add w8, w10, w8
+; GISEL-NEXT: lsr w8, w8, #16
+; GISEL-NEXT: fmov s0, w8
+; GISEL-NEXT: // kill: def $h0 killed $h0 killed $s0
+; GISEL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; GISEL-NEXT: ret
+;
+; WINDOWS-LABEL: testExpbf16:
+; WINDOWS: .seh_proc testExpbf16
+; WINDOWS-NEXT: // %bb.0: // %entry
+; WINDOWS-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; WINDOWS-NEXT: .seh_save_reg_x x30, 16
+; WINDOWS-NEXT: .seh_endprologue
+; WINDOWS-NEXT: // kill: def $h0 killed $h0 def $d0
+; WINDOWS-NEXT: shll v0.4s, v0.4h, #16
+; WINDOWS-NEXT: fcvt d0, s0
+; WINDOWS-NEXT: bl ldexp
+; WINDOWS-NEXT: fcvtxn s0, d0
+; WINDOWS-NEXT: mov w8, #32767 // =0x7fff
+; WINDOWS-NEXT: fmov w9, s0
+; WINDOWS-NEXT: ubfx w10, w9, #16, #1
+; WINDOWS-NEXT: add w8, w9, w8
+; WINDOWS-NEXT: add w8, w10, w8
+; WINDOWS-NEXT: lsr w8, w8, #16
+; WINDOWS-NEXT: fmov s0, w8
+; WINDOWS-NEXT: // kill: def $h0 killed $h0 killed $s0
+; WINDOWS-NEXT: .seh_startepilogue
+; WINDOWS-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; WINDOWS-NEXT: .seh_save_reg_x x30, 16
+; WINDOWS-NEXT: .seh_endepilogue
+; WINDOWS-NEXT: ret
+; WINDOWS-NEXT: .seh_endfunclet
+; WINDOWS-NEXT: .seh_endproc
+entry:
+ %0 = tail call fast bfloat @llvm.ldexp.bf16.i32(bfloat %val, i32 %a)
+ ret bfloat %0
+}
>From 0dec84ffc31a4fb3bf4c118023b191f7d0f41dd2 Mon Sep 17 00:00:00 2001
From: Chandana Mudda <quic_csinderi at quicinc.com>
Date: Mon, 13 Apr 2026 13:29:12 +0530
Subject: [PATCH 19/36] [analyzer] Refine default binding preservation in
RegionStore (#189319)
Narrow the new setImplicitDefaultValue() guard so existing default
bindings are preserved only for aggregate-like cases.
The previous change was too broad and regressed normal
zero-initialization, causing new int[10]{} to be modeled as undefined
and emit a garbage-value warning instead of the expected analyzer
reports.
---
clang/lib/StaticAnalyzer/Core/RegionStore.cpp | 11 ++++++-----
clang/test/Analysis/regionstore-zero-init.cpp | 9 +++++++++
2 files changed, 15 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Analysis/regionstore-zero-init.cpp
diff --git a/clang/lib/StaticAnalyzer/Core/RegionStore.cpp b/clang/lib/StaticAnalyzer/Core/RegionStore.cpp
index 6ec66298e8c45..e1c031e5bb90e 100644
--- a/clang/lib/StaticAnalyzer/Core/RegionStore.cpp
+++ b/clang/lib/StaticAnalyzer/Core/RegionStore.cpp
@@ -2566,11 +2566,12 @@ RegionStoreManager::setImplicitDefaultValue(LimitedRegionBindingsConstRef B,
if (B.hasExhaustedBindingLimit())
return B;
- // Prefer to keep the previous default binding if we had one; that is likely a
- // better choice than setting some arbitrary new default value.
- // This isn't ideal (more of a hack), but better than dropping the more
- // accurate default binding.
- if (B.getDefaultBinding(R).has_value()) {
+ // Preserve an existing aggregate default binding. This handles partially
+ // initialized union-containing aggregates where bindAggregate() may already
+ // have installed a more precise default value at offset 0. Still allow
+ // implicit defaults for scalars and pointers so regular zero-initialization
+ // continues to work, e.g. for `new int[10]{}`.
+ if (T->isAggregateType() && B.getDefaultBinding(R).has_value()) {
return B;
}
diff --git a/clang/test/Analysis/regionstore-zero-init.cpp b/clang/test/Analysis/regionstore-zero-init.cpp
new file mode 100644
index 0000000000000..7b9f6fe43c51b
--- /dev/null
+++ b/clang/test/Analysis/regionstore-zero-init.cpp
@@ -0,0 +1,9 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection -verify %s
+
+void clang_analyzer_eval(int);
+
+void test_zero_initialized_new_array() {
+ int *p = new int[10]{};
+ clang_analyzer_eval(*p == 0); // expected-warning{{TRUE}}
+ delete[] p;
+}
>From d0cbdf5f5c0b742f56f7ed4e0c1b519d9c3cc538 Mon Sep 17 00:00:00 2001
From: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: Mon, 13 Apr 2026 11:19:48 +0300
Subject: [PATCH 20/36] [MISched] Extract `isClustered()` method on SUnit (NFC)
(#191700)
This patch encapsulates the check for wether a `SUnit` is clustered,
rather than letting it scatter across call sites. Currently there is
only a single user, but more users can show up, and I think it provides
a cleaner API even for that single user.
---
llvm/include/llvm/CodeGen/ScheduleDAG.h | 4 ++++
llvm/lib/CodeGen/ScheduleDAG.cpp | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index aee1514581485..b84f8b99a06e2 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -481,6 +481,10 @@ class TargetRegisterInfo;
/// edge occurs first.
LLVM_ABI void biasCriticalPath();
+ LLVM_ABI bool isClustered() const {
+ return ParentClusterIdx != InvalidClusterId;
+ }
+
LLVM_ABI void dumpAttributes() const;
private:
diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp
index e630b80e33ab4..7008d93dd8aca 100644
--- a/llvm/lib/CodeGen/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -365,7 +365,7 @@ LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeName(const SUnit &SU) const {
LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeAll(const SUnit &SU) const {
dumpNode(SU);
SU.dumpAttributes();
- if (SU.ParentClusterIdx != InvalidClusterId)
+ if (SU.isClustered())
dbgs() << " Parent Cluster Index: " << SU.ParentClusterIdx << '\n';
if (SU.Preds.size() > 0) {
>From f078663771ecc680b36ccd32c40a05b0f7672a31 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 13 Apr 2026 10:20:29 +0200
Subject: [PATCH 21/36] [VPlan] Assert ComputeReductionResult isn't predicated
in middle block. NFC (#191767)
---
llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index d46f05f9ead57..b2e8b6a85a35a 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -3288,6 +3288,17 @@ static void fixupVFUsersForEVL(VPlan &Plan, VPValue &EVL) {
if (!HeaderMask)
return;
+ // Ensure that any reduction that uses a select to mask off tail lanes does so
+ // in the vector loop, not the middle block, since EVL tail folding can have
+ // tail elements in the penultimate iteration.
+ assert(all_of(*Plan.getMiddleBlock(), [&Plan, HeaderMask](VPRecipeBase &R) {
+ if (match(&R, m_ComputeReductionResult(m_Select(m_Specific(HeaderMask),
+ m_VPValue(), m_VPValue()))))
+ return R.getOperand(0)->getDefiningRecipe()->getRegion() ==
+ Plan.getVectorLoopRegion();
+ return true;
+ }));
+
// Replace header masks with a mask equivalent to predicating by EVL:
//
// icmp ule widen-canonical-iv backedge-taken-count
>From 8bfb453fc6b2a9df5519df998fc0dc6c4170016b Mon Sep 17 00:00:00 2001
From: Luke Hutton <luke.hutton at arm.com>
Date: Mon, 13 Apr 2026 09:20:44 +0100
Subject: [PATCH 22/36] [mlir][tosa] Improve matmul verifier to check shape
information (#191300)
Updates the matmul verifier to check input and output shapes are valid.
Also adds some tests for verifier failures which were previously not
covered.
---
mlir/lib/Dialect/Tosa/IR/TosaOps.cpp | 73 +++++++++-----
mlir/test/Dialect/Tosa/invalid.mlir | 40 --------
mlir/test/Dialect/Tosa/verifier.mlir | 137 +++++++++++++++++++++++++++
3 files changed, 187 insertions(+), 63 deletions(-)
diff --git a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
index 3bf878304429e..0834aa2123a9c 100644
--- a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+++ b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
@@ -1998,24 +1998,14 @@ LogicalResult tosa::MatMulOp::inferReturnTypeComponents(
}
LogicalResult MatMulOp::verify() {
- auto aType = llvm::dyn_cast<ShapedType>(getA().getType());
- auto bType = llvm::dyn_cast<ShapedType>(getB().getType());
+ const ShapeAdaptor aShape(getA().getType());
+ const ShapeAdaptor bShape(getB().getType());
+ const Type aElementType = aShape.getElementType();
+ const Type bElementType = bShape.getElementType();
- // Must be shaped tensor types
- if (!aType)
- return emitOpError("expect a shaped tensor for input a, got ")
- << getA().getType();
-
- if (!bType)
- return emitOpError("expect a shaped tensor for input b, got ")
- << getB().getType();
-
- auto aElementType = aType.getElementType();
- auto bElementType = bType.getElementType();
-
- auto aQuantizedEType =
+ const auto aQuantizedEType =
llvm::dyn_cast<quant::UniformQuantizedType>(aElementType);
- auto bQuantizedEType =
+ const auto bQuantizedEType =
llvm::dyn_cast<quant::UniformQuantizedType>(bElementType);
if (aQuantizedEType || bQuantizedEType) {
@@ -2034,21 +2024,19 @@ LogicalResult MatMulOp::verify() {
}
// check a_zp and b_zp
- auto aEType = getStorageElementTypeOrSelf(aType);
+ auto aEType = getStorageElementTypeOrSelf(aElementType);
auto aZpEType = getStorageElementTypeOrSelf(getAZp().getType());
- if (aEType != aZpEType) {
+ if (aEType != aZpEType)
return emitOpError("expect input a and a_zp have the same "
"element type, got ")
<< aEType << " and " << aZpEType;
- }
- auto bEType = getStorageElementTypeOrSelf(bType);
- auto bZpEType = getStorageElementTypeOrSelf(getBZp().getType());
- if (bEType != bZpEType) {
+ const Type bEType = getStorageElementTypeOrSelf(bElementType);
+ const Type bZpEType = getStorageElementTypeOrSelf(getBZp().getType());
+ if (bEType != bZpEType)
return emitOpError("expect input b and b_zp have the same "
"element type, got ")
<< bEType << " and " << bZpEType;
- }
FailureOr<int64_t> maybeAZp = getAZeroPoint();
if (succeeded(maybeAZp) && verifyAZeroPoint(*maybeAZp).failed())
@@ -2058,6 +2046,45 @@ LogicalResult MatMulOp::verify() {
if (succeeded(maybeBZp) && verifyBZeroPoint(*maybeBZp).failed())
return failure();
+ // Verify input/output shapes
+ int64_t N = ShapedType::kDynamic;
+ int64_t H = ShapedType::kDynamic;
+ int64_t W = ShapedType::kDynamic;
+ int64_t C = ShapedType::kDynamic;
+
+ if (aShape.hasRank()) {
+ N = aShape.getDimSize(0);
+ H = aShape.getDimSize(1);
+ C = aShape.getDimSize(2);
+ }
+
+ if (bShape.hasRank()) {
+ if (failed(tryUpdateDimOrFailure(*this, N, bShape.getDimSize(0), "b",
+ "batch")) ||
+ failed(tryUpdateDimOrFailure(*this, C, bShape.getDimSize(1), "b",
+ "channels")))
+ return failure();
+ W = bShape.getDimSize(2);
+ }
+
+ const SmallVector<int64_t, 3> expectedOutputShape = {N, H, W};
+ const auto outputType = cast<ShapedType>(getResult().getType());
+ if (outputType.hasRank() &&
+ failed(
+ verifyCompatibleShape(outputType.getShape(), expectedOutputShape))) {
+ InFlightDiagnostic opError = emitOpError("expected output shape ");
+ auto stringifyDim = [&](int64_t d) {
+ if (ShapedType::isDynamic(d))
+ opError << "?";
+ else
+ opError << d;
+ };
+ llvm::interleaveComma(outputType.getShape(), opError, stringifyDim);
+ opError << " to be compatible with expected output shape ";
+ llvm::interleaveComma(expectedOutputShape, opError, stringifyDim);
+ return opError;
+ }
+
return success();
}
diff --git a/mlir/test/Dialect/Tosa/invalid.mlir b/mlir/test/Dialect/Tosa/invalid.mlir
index 4458ffb5f3fe0..5e8111061cb3a 100644
--- a/mlir/test/Dialect/Tosa/invalid.mlir
+++ b/mlir/test/Dialect/Tosa/invalid.mlir
@@ -1698,46 +1698,6 @@ func.func @test_error_double_round_without_scale32(%arg0: tensor<1xi8>) -> tenso
return %0 : tensor<1xi16>
}
-// -----
-// CHECK-LABEL: test_matmul_a_zp_same_element_type
-func.func @test_matmul_a_zp_same_element_type(%arg0: tensor<1x14x19xf32>, %arg1: tensor<1x19x28xf32>) -> tensor<1x14x28xf32> {
-%azp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf16>}> : () -> tensor<1xf16>
-%bzp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
-// expected-error at +1 {{'tosa.matmul' op expect input a and a_zp have the same element type, got 'f32' and 'f16'}}
-%0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf32>, tensor<1x19x28xf32>, tensor<1xf16>, tensor<1xf32>) -> tensor<1x14x28xf32>
- return %0 : tensor<1x14x28xf32>
-}
-
-// -----
-// CHECK-LABEL: test_matmul_b_zp_same_element_type
-func.func @test_matmul_b_zp_same_element_type(%arg0: tensor<1x14x19xf32>, %arg1: tensor<1x19x28xf32>) -> tensor<1x14x28xf32> {
-%azp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
-%bzp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf16>}> : () -> tensor<1xf16>
-// expected-error at +1 {{'tosa.matmul' op expect input b and b_zp have the same element type, got 'f32' and 'f16'}}
-%0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf32>, tensor<1x19x28xf32>, tensor<1xf32>, tensor<1xf16>) -> tensor<1x14x28xf32>
- return %0 : tensor<1x14x28xf32>
-}
-
-// -----
-// CHECK-LABEL: test_matmul_a_zp_non_zero
-func.func @test_matmul_a_zp_non_zero(%arg0: tensor<1x14x19xf32>, %arg1: tensor<1x19x28xf32>) -> tensor<1x14x28xf32> {
-%azp0 = "tosa.const"() <{values = dense<1.0> : tensor<1xf32>}> : () -> tensor<1xf32>
-%bzp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
-// expected-error at +1 {{'tosa.matmul' op a zero point must be zero for non-int8 integer types}}
-%0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf32>, tensor<1x19x28xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x14x28xf32>
- return %0 : tensor<1x14x28xf32>
-}
-
-// -----
-// CHECK-LABEL: test_matmul_b_zp_non_zero
-func.func @test_matmul_b_zp_non_zero(%arg0: tensor<1x14x19xf32>, %arg1: tensor<1x19x28xf32>) -> tensor<1x14x28xf32> {
-%azp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
-%bzp0 = "tosa.const"() <{values = dense<-1.0> : tensor<1xf32>}> : () -> tensor<1xf32>
-// expected-error at +1 {{'tosa.matmul' op b zero point must be zero for non-int8 integer types}}
-%0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf32>, tensor<1x19x28xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x14x28xf32>
- return %0 : tensor<1x14x28xf32>
-}
-
// -----
// CHECK-LABEL: test_negate_same_element_type
diff --git a/mlir/test/Dialect/Tosa/verifier.mlir b/mlir/test/Dialect/Tosa/verifier.mlir
index 7f6d78df84489..5f3aa8764664d 100644
--- a/mlir/test/Dialect/Tosa/verifier.mlir
+++ b/mlir/test/Dialect/Tosa/verifier.mlir
@@ -1147,6 +1147,143 @@ func.func @scatter_invalid_K_W(%arg0 : tensor<2x4x5xi32>, %arg1 : tensor<2x6xi32
// -----
+func.func @test_matmul_output_batch_mismatch(%arg0: tensor<2x3x4xf32>, %arg1: tensor<5x4x6xf32>) -> tensor<2x3x6xf32> {
+ %azp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ %bzp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.matmul' op expected batch of b to match size 2, got 5}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<2x3x4xf32>, tensor<5x4x6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<2x3x6xf32>
+ return %0 : tensor<2x3x6xf32>
+}
+
+// -----
+
+func.func @test_matmul_output_channel_mismatch(%arg0: tensor<2x3x4xf32>, %arg1: tensor<2x7x6xf32>) -> tensor<2x3x6xf32> {
+ %azp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ %bzp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.matmul' op expected channels of b to match size 4, got 7}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<2x3x4xf32>, tensor<2x7x6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<2x3x6xf32>
+ return %0 : tensor<2x3x6xf32>
+}
+
+// -----
+
+func.func @test_matmul_output_shape_mismatch(%arg0: tensor<2x3x4xf32>, %arg1: tensor<2x4x6xf32>) -> tensor<2x5x6xf32> {
+ %azp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ %bzp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.matmul' op expected output shape 2, 5, 6 to be compatible with expected output shape 2, 3, 6}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<2x3x4xf32>, tensor<2x4x6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<2x5x6xf32>
+ return %0 : tensor<2x5x6xf32>
+}
+
+// -----
+
+
+func.func @test_matmul_dynamic_batch_mismatch(%arg0: tensor<2x?x4xf32>, %arg1: tensor<5x4x6xf32>) -> tensor<2x?x6xf32> {
+ %azp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ %bzp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.matmul' op expected batch of b to match size 2, got 5}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<2x?x4xf32>, tensor<5x4x6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<2x?x6xf32>
+ return %0 : tensor<2x?x6xf32>
+}
+
+// -----
+
+func.func @test_matmul_dynamic_channel_mismatch(%arg0: tensor<?x3x4xf32>, %arg1: tensor<?x7x6xf32>) -> tensor<?x3x6xf32> {
+ %azp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ %bzp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.matmul' op expected channels of b to match size 4, got 7}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<?x3x4xf32>, tensor<?x7x6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x3x6xf32>
+ return %0 : tensor<?x3x6xf32>
+}
+
+// -----
+
+func.func @test_matmul_dynamic_output_shape_mismatch(%arg0: tensor<?x3x4xf32>, %arg1: tensor<2x4x6xf32>) -> tensor<5x3x6xf32> {
+ %azp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ %bzp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.matmul' op expected output shape 5, 3, 6 to be compatible with expected output shape 2, 3, 6}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<?x3x4xf32>, tensor<2x4x6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<5x3x6xf32>
+ return %0 : tensor<5x3x6xf32>
+}
+
+// -----
+
+
+func.func @test_matmul_unranked_b_output_shape_mismatch(%arg0: tensor<2x3x4xf32>, %arg1: tensor<*xf32>) -> tensor<2x5x?xf32> {
+ %azp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ %bzp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.matmul' op expected output shape 2, 5, ? to be compatible with expected output shape 2, 3, ?}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<2x3x4xf32>, tensor<*xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<2x5x?xf32>
+ return %0 : tensor<2x5x?xf32>
+}
+
+// -----
+
+
+func.func @test_matmul_quantized_mixed_operands(%arg0: tensor<2x3x4x!quant.uniform<i8:f32, 0.125>>, %arg1: tensor<2x4x6xf32>) -> tensor<2x3x6xi32> {
+ %azp0 = "tosa.const"() {values = dense<0> : tensor<1xi8>} : () -> tensor<1xi8>
+ %bzp0 = "tosa.const"() {values = dense<0.0> : tensor<1xf32>} : () -> tensor<1xf32>
+ // expected-error at +1 {{'tosa.matmul' op expect operands to be both quantized or both not quantized, got '!quant.uniform<i8:f32, 1.250000e-01>' and 'f32'}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<2x3x4x!quant.uniform<i8:f32, 0.125>>, tensor<2x4x6xf32>, tensor<1xi8>, tensor<1xf32>) -> tensor<2x3x6xi32>
+ return %0 : tensor<2x3x6xi32>
+}
+
+// -----
+
+func.func @test_matmul_quantized_width_mismatch(%arg0: tensor<2x3x4x!quant.uniform<i8:f32, 0.125>>, %arg1: tensor<2x4x6x!quant.uniform<i16:f32, 0.125>>) -> tensor<2x3x6xi32> {
+ %azp0 = "tosa.const"() {values = dense<0> : tensor<1xi8>} : () -> tensor<1xi8>
+ %bzp0 = "tosa.const"() {values = dense<0> : tensor<1xi16>} : () -> tensor<1xi16>
+ // expected-error at +1 {{'tosa.matmul' op expect quantized operands to have same widths, got 8 and 16}}
+ %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<2x3x4x!quant.uniform<i8:f32, 0.125>>, tensor<2x4x6x!quant.uniform<i16:f32, 0.125>>, tensor<1xi8>, tensor<1xi16>) -> tensor<2x3x6xi32>
+ return %0 : tensor<2x3x6xi32>
+}
+
+// -----
+
+// CHECK-LABEL: test_matmul_a_zp_same_element_type
+func.func @test_matmul_a_zp_same_element_type(%arg0: tensor<1x14x19xf32>, %arg1: tensor<1x19x28xf32>) -> tensor<1x14x28xf32> {
+%azp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf16>}> : () -> tensor<1xf16>
+%bzp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+// expected-error at +1 {{'tosa.matmul' op expect input a and a_zp have the same element type, got 'f32' and 'f16'}}
+%0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf32>, tensor<1x19x28xf32>, tensor<1xf16>, tensor<1xf32>) -> tensor<1x14x28xf32>
+ return %0 : tensor<1x14x28xf32>
+}
+
+// -----
+
+// CHECK-LABEL: test_matmul_b_zp_same_element_type
+func.func @test_matmul_b_zp_same_element_type(%arg0: tensor<1x14x19xf32>, %arg1: tensor<1x19x28xf32>) -> tensor<1x14x28xf32> {
+%azp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+%bzp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf16>}> : () -> tensor<1xf16>
+// expected-error at +1 {{'tosa.matmul' op expect input b and b_zp have the same element type, got 'f32' and 'f16'}}
+%0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf32>, tensor<1x19x28xf32>, tensor<1xf32>, tensor<1xf16>) -> tensor<1x14x28xf32>
+ return %0 : tensor<1x14x28xf32>
+}
+
+// -----
+
+// CHECK-LABEL: test_matmul_a_zp_non_zero
+func.func @test_matmul_a_zp_non_zero(%arg0: tensor<1x14x19xf32>, %arg1: tensor<1x19x28xf32>) -> tensor<1x14x28xf32> {
+%azp0 = "tosa.const"() <{values = dense<1.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+%bzp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+// expected-error at +1 {{'tosa.matmul' op a zero point must be zero for non-int8 integer types}}
+%0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf32>, tensor<1x19x28xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x14x28xf32>
+ return %0 : tensor<1x14x28xf32>
+}
+
+// -----
+
+// CHECK-LABEL: test_matmul_b_zp_non_zero
+func.func @test_matmul_b_zp_non_zero(%arg0: tensor<1x14x19xf32>, %arg1: tensor<1x19x28xf32>) -> tensor<1x14x28xf32> {
+%azp0 = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+%bzp0 = "tosa.const"() <{values = dense<-1.0> : tensor<1xf32>}> : () -> tensor<1xf32>
+// expected-error at +1 {{'tosa.matmul' op b zero point must be zero for non-int8 integer types}}
+%0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf32>, tensor<1x19x28xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x14x28xf32>
+ return %0 : tensor<1x14x28xf32>
+}
+
+// -----
+
func.func @test_matmul_t_block_scaled_data_mismatch(%arg0: tensor<4x8x32xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf8E5M2>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> {
// expected-error at +1 {{'tosa.matmul_t_block_scaled' op expect A_data and B_data to have same element type, got 'f8E4M3FN' and 'f8E5M2'}}
%0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size<BLOCK_SIZE_32> : i32} : (tensor<4x8x32xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf8E5M2>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32>
>From b7b791a2074969bf2b0e3753bf078fa13b0947bf Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Mon, 13 Apr 2026 09:24:21 +0100
Subject: [PATCH 23/36] [VPlan] Directly check if middle block is pred of
scalar preheader. (#191768)
hasScalarTail currently returns incorrect results when queried after
runtime checks have been added. Generalize and harden by checking if the
middle block is a predecessor of the scalar preheader.
---
llvm/lib/Transforms/Vectorize/VPlan.h | 10 +-
.../tail-folding-constant-trip-counts.ll | 314 ++++++++++++++++++
2 files changed, 319 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/Transforms/LoopVectorize/tail-folding-constant-trip-counts.ll
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index cc93bb924998b..b8994b77da5fe 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -4959,12 +4959,12 @@ class VPlan {
(ExitBlocks.size() == 1 && ExitBlocks[0]->getNumPredecessors() > 1);
}
- /// Returns true if the scalar tail may execute after the vector loop. Note
- /// that this relies on unneeded branches to the scalar tail loop being
- /// removed.
+ /// Returns true if the scalar tail may execute after the vector loop, i.e.
+ /// if the middle block is a predecessor of the scalar preheader. Note that
+ /// this relies on unneeded branches to the scalar tail loop being removed.
bool hasScalarTail() const {
- return !(!getScalarPreheader()->hasPredecessors() ||
- getScalarPreheader()->getSinglePredecessor() == getEntry());
+ return is_contained(getScalarPreheader()->getPredecessors(),
+ getMiddleBlock());
}
};
diff --git a/llvm/test/Transforms/LoopVectorize/tail-folding-constant-trip-counts.ll b/llvm/test/Transforms/LoopVectorize/tail-folding-constant-trip-counts.ll
new file mode 100644
index 0000000000000..25c7d2844d097
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/tail-folding-constant-trip-counts.ll
@@ -0,0 +1,314 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-target-supports-masked-memory-ops \
+; RUN: -prefer-predicate-over-epilogue=predicate-dont-vectorize \
+; RUN: -force-tail-folding-style=data-without-lane-mask -S %s | FileCheck %s
+
+define void @tc_17_without_runtime_check(ptr noalias %A, ptr noalias %B) {
+; CHECK-LABEL: define void @tc_17_without_runtime_check(
+; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i32> [[VEC_IND]], splat (i32 16)
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[A]], i32 [[INDEX]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[VEC_IND]], ptr align 4 [[TMP1]], <4 x i1> [[TMP0]])
+; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 17)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[B]], i32 [[INDEX]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP2]], ptr align 4 [[TMP3]], <4 x i1> [[TMP0]])
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 20
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.A = getelementptr i32, ptr %A, i32 %iv
+ store i32 %iv, ptr %gep.A
+ %v = add i32 %iv, 17
+ %q = getelementptr i32, ptr %B, i32 %iv
+ store i32 %v, ptr %q
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv.next, 17
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @tc_17_with_runtime_check(ptr %A, ptr %B) {
+; CHECK-LABEL: define void @tc_17_with_runtime_check(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
+; CHECK-NEXT: [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[B1]], [[A2]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 16
+; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i32> [[VEC_IND]], splat (i32 16)
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[A]], i32 [[INDEX]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[VEC_IND]], ptr align 4 [[TMP2]], <4 x i1> [[TMP1]])
+; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 17)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[B]], i32 [[INDEX]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP3]], ptr align 4 [[TMP4]], <4 x i1> [[TMP1]])
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 20
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr i32, ptr [[A]], i32 [[IV]]
+; CHECK-NEXT: store i32 [[IV]], ptr [[GEP_A]], align 4
+; CHECK-NEXT: [[V:%.*]] = add i32 [[IV]], 17
+; CHECK-NEXT: [[Q:%.*]] = getelementptr i32, ptr [[B]], i32 [[IV]]
+; CHECK-NEXT: store i32 [[V]], ptr [[Q]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 17
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.A = getelementptr i32, ptr %A, i32 %iv
+ store i32 %iv, ptr %gep.A
+ %v = add i32 %iv, 17
+ %q = getelementptr i32, ptr %B, i32 %iv
+ store i32 %v, ptr %q
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv.next, 17
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @tc_20_without_runtime_checks(ptr noalias %A, ptr noalias %B) {
+; CHECK-LABEL: define void @tc_20_without_runtime_checks(
+; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[A]], i32 [[INDEX]]
+; CHECK-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP0]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 17)
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[B]], i32 [[INDEX]]
+; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[TMP2]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 20
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.A = getelementptr i32, ptr %A, i32 %iv
+ store i32 %iv, ptr %gep.A
+ %v = add i32 %iv, 17
+ %q = getelementptr i32, ptr %B, i32 %iv
+ store i32 %v, ptr %q
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv.next, 20
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @tc_20_with_runtime_checks(ptr %A, ptr %B) {
+; CHECK-LABEL: define void @tc_20_with_runtime_checks(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
+; CHECK-NEXT: [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[B1]], [[A2]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 16
+; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[A]], i32 [[INDEX]]
+; CHECK-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP1]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 17)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[B]], i32 [[INDEX]]
+; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[TMP3]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 20
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr i32, ptr [[A]], i32 [[IV]]
+; CHECK-NEXT: store i32 [[IV]], ptr [[GEP_A]], align 4
+; CHECK-NEXT: [[V:%.*]] = add i32 [[IV]], 17
+; CHECK-NEXT: [[Q:%.*]] = getelementptr i32, ptr [[B]], i32 [[IV]]
+; CHECK-NEXT: store i32 [[V]], ptr [[Q]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 20
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.A = getelementptr i32, ptr %A, i32 %iv
+ store i32 %iv, ptr %gep.A
+ %v = add i32 %iv, 17
+ %q = getelementptr i32, ptr %B, i32 %iv
+ store i32 %v, ptr %q
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv.next, 20
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @tc_23_without_runtime_checks(ptr noalias %A, ptr noalias %B) {
+; CHECK-LABEL: define void @tc_23_without_runtime_checks(
+; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i32> [[VEC_IND]], splat (i32 22)
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[A]], i32 [[INDEX]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[VEC_IND]], ptr align 4 [[TMP1]], <4 x i1> [[TMP0]])
+; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 17)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[B]], i32 [[INDEX]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP2]], ptr align 4 [[TMP3]], <4 x i1> [[TMP0]])
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 24
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.A = getelementptr i32, ptr %A, i32 %iv
+ store i32 %iv, ptr %gep.A
+ %v = add i32 %iv, 17
+ %q = getelementptr i32, ptr %B, i32 %iv
+ store i32 %v, ptr %q
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv.next, 23
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @tc_23_with_runtime_checks(ptr %A, ptr %B) {
+; CHECK-LABEL: define void @tc_23_with_runtime_checks(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
+; CHECK-NEXT: [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[B1]], [[A2]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 16
+; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i32> [[VEC_IND]], splat (i32 22)
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[A]], i32 [[INDEX]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[VEC_IND]], ptr align 4 [[TMP2]], <4 x i1> [[TMP1]])
+; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 17)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[B]], i32 [[INDEX]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP3]], ptr align 4 [[TMP4]], <4 x i1> [[TMP1]])
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 24
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr i32, ptr [[A]], i32 [[IV]]
+; CHECK-NEXT: store i32 [[IV]], ptr [[GEP_A]], align 4
+; CHECK-NEXT: [[V:%.*]] = add i32 [[IV]], 17
+; CHECK-NEXT: [[Q:%.*]] = getelementptr i32, ptr [[B]], i32 [[IV]]
+; CHECK-NEXT: store i32 [[V]], ptr [[Q]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 23
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.A = getelementptr i32, ptr %A, i32 %iv
+ store i32 %iv, ptr %gep.A
+ %v = add i32 %iv, 17
+ %q = getelementptr i32, ptr %B, i32 %iv
+ store i32 %v, ptr %q
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv.next, 23
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
>From b1ecf4c9f419689684b650f44e625f13ffe8726d Mon Sep 17 00:00:00 2001
From: Mao Chuanjun <10255501521 at stu.ecnu.edu.cn>
Date: Mon, 13 Apr 2026 16:36:25 +0800
Subject: [PATCH 24/36] [clang-tidy] Fix a false positive when converting a
bool to a signed integer type (#191696)
Fix #191337
---
.../clang-tidy/bugprone/NarrowingConversionsCheck.cpp | 10 +++++++++-
clang-tools-extra/docs/ReleaseNotes.rst | 4 ++++
.../checkers/bugprone/narrowing-conversions.cpp | 10 ++++++++++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/clang-tools-extra/clang-tidy/bugprone/NarrowingConversionsCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/NarrowingConversionsCheck.cpp
index f0a0f6c9b3106..934b365a07cad 100644
--- a/clang-tools-extra/clang-tidy/bugprone/NarrowingConversionsCheck.cpp
+++ b/clang-tools-extra/clang-tidy/bugprone/NarrowingConversionsCheck.cpp
@@ -593,9 +593,17 @@ void NarrowingConversionsCheck::handleImplicitCast(
case CK_IntegralToFloating:
handleIntegralToFloating(Context, SourceLoc, Lhs, Rhs);
return;
- case CK_IntegralCast:
+ case CK_IntegralCast: {
+ const BuiltinType *ToType = getBuiltinType(Lhs);
+ const BuiltinType *FromType = getBuiltinType(Rhs);
+ if (ToType && FromType && FromType->getKind() == BuiltinType::Bool &&
+ ToType->isSignedInteger()) {
+ handleBooleanToSignedIntegral(Context, SourceLoc, Lhs, Rhs);
+ return;
+ }
handleIntegralCast(Context, SourceLoc, Lhs, Rhs);
return;
+ }
case CK_FloatingToBoolean:
handleFloatingToBoolean(Context, SourceLoc, Lhs, Rhs);
return;
diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst
index d51cbc07c0b6d..6979c2cbcfff2 100644
--- a/clang-tools-extra/docs/ReleaseNotes.rst
+++ b/clang-tools-extra/docs/ReleaseNotes.rst
@@ -262,6 +262,10 @@ Changes in existing checks
<clang-tidy/checks/bugprone/macro-parentheses>` check by printing the macro
definition in the warning message if the macro is defined on command line.
+- Improved :doc:`bugprone-narrowing-conversions
+ <clang-tidy/checks/bugprone/narrowing-conversions>` check by fixing a false
+ positive when converting a ``bool`` to a signed integer type.
+
- Improved :doc:`bugprone-pointer-arithmetic-on-polymorphic-object
<clang-tidy/checks/bugprone/pointer-arithmetic-on-polymorphic-object>` check
by fixing a false positive when ``operator[]`` is used in a dependent context.
diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/narrowing-conversions.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/narrowing-conversions.cpp
index 39875264bd1e6..65750f7709f91 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/narrowing-conversions.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/narrowing-conversions.cpp
@@ -355,4 +355,14 @@ void typedef_context() {
// CHECK-MESSAGES: :[[@LINE-1]]:7: warning: narrowing conversion from 'myint64_t' (aka 'long long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
}
+void testBoolToSignedType() {
+ bool b = true;
+ auto c = char{b};
+ auto sc = (signed char){b};
+ auto s = short{b};
+ auto i = int{b};
+ auto c1 = static_cast<char>(b);
+ auto c2 = (char)b;
+}
+
} // namespace floats
>From 1efad3172194e9a88e98da5581d9c16a6c27abda Mon Sep 17 00:00:00 2001
From: Timm Baeder <tbaeder at redhat.com>
Date: Mon, 13 Apr 2026 10:37:26 +0200
Subject: [PATCH 25/36] [clang][bytecode] Fix placement new on multidimensional
array elements (#191766)
The direct base of those pointers is not a union, i.e. `getRecord()`
returns `nullptr`.
---
clang/lib/AST/ByteCode/Interp.cpp | 9 +++++++--
clang/test/AST/ByteCode/placement-new.cpp | 15 +++++++++++++++
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/clang/lib/AST/ByteCode/Interp.cpp b/clang/lib/AST/ByteCode/Interp.cpp
index 3d75d5c857cf1..f4d6ef4dc8bd6 100644
--- a/clang/lib/AST/ByteCode/Interp.cpp
+++ b/clang/lib/AST/ByteCode/Interp.cpp
@@ -1990,7 +1990,12 @@ bool CheckNewTypeMismatch(InterpState &S, CodePtr OpPC, const Expr *E,
std::optional<uint64_t> ArraySize) {
const Pointer &Ptr = S.Stk.peek<Pointer>();
- if (Ptr.inUnion() && Ptr.getBase().getRecord()->isUnion())
+ auto directBaseIsUnion = [](const Pointer &Ptr) -> bool {
+ const Record *R = Ptr.getBase().getRecord();
+ return R && R->isUnion();
+ };
+
+ if (Ptr.inUnion() && directBaseIsUnion(Ptr))
Ptr.activate();
if (Ptr.isZero()) {
@@ -2071,7 +2076,7 @@ bool CheckNewTypeMismatch(InterpState &S, CodePtr OpPC, const Expr *E,
}
// Can't activate fields in a union, unless the direct base is the union.
- if (Ptr.inUnion() && !Ptr.isActive() && !Ptr.getBase().getRecord()->isUnion())
+ if (Ptr.inUnion() && !Ptr.isActive() && !directBaseIsUnion(Ptr))
return CheckActive(S, OpPC, Ptr, AK_Construct);
return true;
diff --git a/clang/test/AST/ByteCode/placement-new.cpp b/clang/test/AST/ByteCode/placement-new.cpp
index 2c302ef7a8e7b..6091ab5602121 100644
--- a/clang/test/AST/ByteCode/placement-new.cpp
+++ b/clang/test/AST/ByteCode/placement-new.cpp
@@ -524,3 +524,18 @@ static_assert(intDestArray() == 0); // both-error {{not an integral constant exp
constexpr void invalidDest() { new (undefinedfunction()) int; } // both-error {{use of undeclared identifier 'undefinedfunction'}}
static_assert((invalidDest(), true)); // both-error {{not an integral constant expression}}
+
+namespace DirectBaseHasNoRecord {
+ constexpr int test_multidim_single_start() {
+ struct S {
+ union {
+ int storage[2][3];
+ };
+ };
+ S s;
+ new (&s.storage[0][0]) int(1); // both-note {{construction of subobject of member 'storage' of union with no active member is not allowed in a constant expression}}
+ return 13;
+ }
+ static_assert(test_multidim_single_start() == 13); // both-error {{not an integral constant expression}} \
+ // both-note {{in call to}}
+}
>From ad16fc4e60e5765c773e93fbfc47a2ba063213a7 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Mon, 13 Apr 2026 09:52:18 +0100
Subject: [PATCH 26/36] [AArch64][SME] Remove SelectionDAG SME ABI lowering
(#190950)
This patch removes the `-aarch64-new-sme-abi=<true/false>` option (which
has been defaulted to "true" since LLVM 22), and removes the Selection
DAG lowering for the SME ABI.
There should be no functional changes for the default path
(`-aarch64-new-sme-abi=true`).
---
clang/test/CodeGen/AArch64/sme-remarks.c | 16 +-
llvm/docs/AArch64SME.rst | 4 +
llvm/lib/IR/Verifier.cpp | 3 -
llvm/lib/Target/AArch64/AArch64.h | 4 +-
.../Target/AArch64/AArch64ISelLowering.cpp | 441 +-----------
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 12 -
.../AArch64/AArch64MachineFunctionInfo.h | 34 -
.../Target/AArch64/AArch64SMEAttributes.cpp | 8 +-
.../lib/Target/AArch64/AArch64SMEAttributes.h | 13 +-
.../lib/Target/AArch64/AArch64SMEInstrInfo.td | 49 +-
.../Target/AArch64/AArch64TargetMachine.cpp | 20 +-
.../lib/Target/AArch64/AArch64TargetMachine.h | 4 -
llvm/lib/Target/AArch64/CMakeLists.txt | 1 -
llvm/lib/Target/AArch64/MachineSMEABIPass.cpp | 3 +-
llvm/lib/Target/AArch64/SMEABIPass.cpp | 195 -----
.../AArch64/aarch64-sme-za-call-lowering.ll | 4 +-
.../AArch64/sme-abi-save-call-remarks.ll | 22 +-
llvm/test/CodeGen/AArch64/sme-agnostic-za.ll | 234 ++----
llvm/test/CodeGen/AArch64/sme-dynamic-tls.ll | 2 +-
.../CodeGen/AArch64/sme-lazy-save-call.ll | 480 +++----------
.../CodeGen/AArch64/sme-lazy-save-windows.ll | 1 -
.../AArch64/sme-lazy-sve-nzcv-live.mir | 2 +-
.../CodeGen/AArch64/sme-new-za-function.ll | 91 ---
.../CodeGen/AArch64/sme-new-zt0-function.ll | 14 -
.../test/CodeGen/AArch64/sme-peephole-opts.ll | 2 +-
.../AArch64/sme-shared-za-interface.ll | 51 --
.../CodeGen/AArch64/sme-za-control-flow.ll | 606 ++++------------
.../test/CodeGen/AArch64/sme-za-exceptions.ll | 548 --------------
.../sme-za-function-with-many-blocks.ll | 2 +-
.../AArch64/sme-za-lazy-save-buffer.ll | 1 -
llvm/test/CodeGen/AArch64/sme-zt0-state.ll | 329 ++-------
.../CodeGen/AArch64/sve-stack-frame-layout.ll | 674 ++++++++----------
llvm/test/Verifier/sme-attributes.ll | 3 -
.../Target/AArch64/SMEAttributesTest.cpp | 30 -
.../llvm/lib/Target/AArch64/BUILD.gn | 1 -
35 files changed, 756 insertions(+), 3148 deletions(-)
delete mode 100644 llvm/lib/Target/AArch64/SMEABIPass.cpp
delete mode 100644 llvm/test/CodeGen/AArch64/sme-new-zt0-function.ll
diff --git a/clang/test/CodeGen/AArch64/sme-remarks.c b/clang/test/CodeGen/AArch64/sme-remarks.c
index f7a1f33f3372d..d220c8e076661 100644
--- a/clang/test/CodeGen/AArch64/sme-remarks.c
+++ b/clang/test/CodeGen/AArch64/sme-remarks.c
@@ -1,6 +1,4 @@
// REQUIRES: aarch64-registered-target
-
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -mllvm -aarch64-new-sme-abi=false -Rpass-analysis=sme -verify=expected-sdag %s -S -o /dev/null
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -Rpass-analysis=sme -verify %s -S -o /dev/null %s
void private_za_callee_a();
@@ -10,32 +8,26 @@ void private_za_callee_c();
void test_za_merge_paths(int a) __arm_inout("za") {
// expected-remark at +1 {{lazy save of ZA emitted in 'test_za_merge_paths'}}
if (a != 0)
- // expected-sdag-remark at +2 {{call from 'test_za_merge_paths' to 'unknown callee' sets up a lazy save for ZA}}
// expected-remark at +1 {{call to 'private_za_callee_a' requires ZA save}}
private_za_callee_a();
else
- // expected-sdag-remark at +2 {{call from 'test_za_merge_paths' to 'unknown callee' sets up a lazy save for ZA}}
// expected-remark at +1 {{call to 'private_za_callee_b' requires ZA save}}
private_za_callee_b();
- // expected-sdag-remark at +3 {{call from 'test_za_merge_paths' to 'unknown callee' sets up a lazy save for ZA}}
- /// The new lowering won't report this call as the save is already needed due
- /// to the call to `private_za_callee_a/b()` calls on both paths to this call.
+ /// The analysis won't report this call as the save is already needed due to
+ /// the call to `private_za_callee_a/b()` calls on both paths to this call.
private_za_callee_c();
}
void test_lazy_save_multiple_paths(int a) __arm_inout("za") {
// expected-remark at +1 {{lazy save of ZA emitted in 'test_lazy_save_multiple_paths'}}
if (a != 0)
- // expected-sdag-remark at +2 {{call from 'test_lazy_save_multiple_paths' to 'unknown callee' sets up a lazy save for ZA}}
// expected-remark at +1 {{call to 'private_za_callee_a' requires ZA save}}
private_za_callee_a();
else {
- // expected-sdag-remark at +2 {{call from 'test_lazy_save_multiple_paths' to 'unknown callee' sets up a lazy save for ZA}}
// expected-remark at +1 {{call to 'private_za_callee_b' requires ZA save}}
private_za_callee_b();
- // expected-sdag-remark at +3 {{call from 'test_lazy_save_multiple_paths' to 'unknown callee' sets up a lazy save for ZA}}
- /// The new lowering won't report this call as the save is already needed
- /// due to the call to `private_za_callee_b()`.
+ /// The analysis won't report this call as the save is already needed due
+ /// to the call to `private_za_callee_b()`.
private_za_callee_c();
}
}
diff --git a/llvm/docs/AArch64SME.rst b/llvm/docs/AArch64SME.rst
index 327f9dcb232c1..d633dc2fbce2d 100644
--- a/llvm/docs/AArch64SME.rst
+++ b/llvm/docs/AArch64SME.rst
@@ -49,6 +49,10 @@ C/C++-level ACLE attributes:
``aarch64_expanded_pstate_za``
is used for functions with ``__arm_new_za``
+``aarch64_zt0_undef``
+ Deprecated. Previously used internally to prevent spills/reloads of ZT0 in
+ some cases.
+
Clang must ensure that the above attributes are added both to the
function's declaration/definition as well as to their call-sites. This is
important for calls to attributed function pointers, where no
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index a86e8fdb7d73a..d4ade9c7ce534 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -3122,9 +3122,6 @@ void Verifier::visitFunction(const Function &F) {
Check(!Attrs.hasAttrSomewhere(Attribute::ElementType),
"Attribute 'elementtype' can only be applied to a callsite.", &F);
- Check(!Attrs.hasFnAttr("aarch64_zt0_undef"),
- "Attribute 'aarch64_zt0_undef' can only be applied to a callsite.");
-
if (Attrs.hasFnAttr(Attribute::Naked))
for (const Argument &Arg : F.args())
Check(Arg.use_empty(), "cannot use argument of naked function", &Arg);
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index 3d2838291d7e8..81f766080c82a 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -66,7 +66,6 @@ FunctionPass *createAArch64PostCoalescerPass();
FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
FunctionPass *createAArch64CollectLOHPass();
-FunctionPass *createSMEABIPass();
FunctionPass *createSMEPeepholeOptPass();
FunctionPass *createMachineSMEABIPass(CodeGenOptLevel);
FunctionPass *createAArch64SRLTDefineSuperRegsPass();
@@ -145,8 +144,7 @@ void initializeAArch64StackTaggingPreRAPass(PassRegistry &);
void initializeAArch64StorePairSuppressPass(PassRegistry&);
void initializeFalkorHWPFFixPass(PassRegistry&);
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry&);
-void initializeLDTLSCleanupPass(PassRegistry&);
-void initializeSMEABIPass(PassRegistry &);
+void initializeLDTLSCleanupPass(PassRegistry &);
void initializeSMEPeepholeOptPass(PassRegistry &);
void initializeMachineSMEABIPass(PassRegistry &);
void initializeAArch64SRLTDefineSuperRegsPass(PassRegistry &);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 96ccd38e34117..ece24767bdbb9 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3260,136 +3260,6 @@ AArch64TargetLowering::EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const {
return BB;
}
-MachineBasicBlock *
-AArch64TargetLowering::EmitInitTPIDR2Object(MachineInstr &MI,
- MachineBasicBlock *BB) const {
- MachineFunction *MF = BB->getParent();
- MachineFrameInfo &MFI = MF->getFrameInfo();
- AArch64FunctionInfo *FuncInfo = MF->getInfo<AArch64FunctionInfo>();
- TPIDR2Object &TPIDR2 = FuncInfo->getTPIDR2Obj();
- if (TPIDR2.Uses > 0) {
- // Note: This case just needs to do `SVL << 48`. It is not implemented as we
- // generally don't support big-endian SVE/SME.
- if (!Subtarget->isLittleEndian())
- reportFatalInternalError(
- "TPIDR2 block initialization is not supported on big-endian targets");
-
- const TargetInstrInfo *TII = Subtarget->getInstrInfo();
- // Store buffer pointer and num_za_save_slices.
- // Bytes 10-15 are implicitly zeroed.
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::STPXi))
- .addReg(MI.getOperand(0).getReg())
- .addReg(MI.getOperand(1).getReg())
- .addFrameIndex(TPIDR2.FrameIndex)
- .addImm(0);
- } else
- MFI.RemoveStackObject(TPIDR2.FrameIndex);
-
- BB->remove_instr(&MI);
- return BB;
-}
-
-MachineBasicBlock *
-AArch64TargetLowering::EmitAllocateZABuffer(MachineInstr &MI,
- MachineBasicBlock *BB) const {
- MachineFunction *MF = BB->getParent();
- MachineFrameInfo &MFI = MF->getFrameInfo();
- AArch64FunctionInfo *FuncInfo = MF->getInfo<AArch64FunctionInfo>();
- // TODO This function grows the stack with a subtraction, which doesn't work
- // on Windows. Some refactoring to share the functionality in
- // LowerWindowsDYNAMIC_STACKALLOC will be required once the Windows ABI
- // supports SME
- assert(!MF->getSubtarget<AArch64Subtarget>().isTargetWindows() &&
- "Lazy ZA save is not yet supported on Windows");
-
- TPIDR2Object &TPIDR2 = FuncInfo->getTPIDR2Obj();
-
- if (TPIDR2.Uses > 0) {
- const TargetInstrInfo *TII = Subtarget->getInstrInfo();
- MachineRegisterInfo &MRI = MF->getRegInfo();
-
- // The SUBXrs below won't always be emitted in a form that accepts SP
- // directly
- Register SP = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY), SP)
- .addReg(AArch64::SP);
-
- // Allocate a lazy-save buffer object of the size given, normally SVL * SVL
- auto Size = MI.getOperand(1).getReg();
- auto Dest = MI.getOperand(0).getReg();
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::MSUBXrrr), Dest)
- .addReg(Size)
- .addReg(Size)
- .addReg(SP);
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
- AArch64::SP)
- .addReg(Dest);
-
- // We have just allocated a variable sized object, tell this to PEI.
- MFI.CreateVariableSizedObject(Align(16), nullptr);
- }
-
- BB->remove_instr(&MI);
- return BB;
-}
-
-// TODO: Find a way to merge this with EmitAllocateZABuffer.
-MachineBasicBlock *
-AArch64TargetLowering::EmitAllocateSMESaveBuffer(MachineInstr &MI,
- MachineBasicBlock *BB) const {
- MachineFunction *MF = BB->getParent();
- MachineFrameInfo &MFI = MF->getFrameInfo();
- AArch64FunctionInfo *FuncInfo = MF->getInfo<AArch64FunctionInfo>();
- assert(!MF->getSubtarget<AArch64Subtarget>().isTargetWindows() &&
- "Lazy ZA save is not yet supported on Windows");
-
- const TargetInstrInfo *TII = Subtarget->getInstrInfo();
- if (FuncInfo->isSMESaveBufferUsed()) {
- // Allocate a buffer object of the size given by MI.getOperand(1).
- auto Size = MI.getOperand(1).getReg();
- auto Dest = MI.getOperand(0).getReg();
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::SUBXrx64), AArch64::SP)
- .addReg(AArch64::SP)
- .addReg(Size)
- .addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 0));
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY), Dest)
- .addReg(AArch64::SP);
-
- // We have just allocated a variable sized object, tell this to PEI.
- MFI.CreateVariableSizedObject(Align(16), nullptr);
- } else
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::IMPLICIT_DEF),
- MI.getOperand(0).getReg());
-
- BB->remove_instr(&MI);
- return BB;
-}
-
-MachineBasicBlock *
-AArch64TargetLowering::EmitGetSMESaveSize(MachineInstr &MI,
- MachineBasicBlock *BB) const {
- // If the buffer is used, emit a call to __arm_sme_state_size()
- MachineFunction *MF = BB->getParent();
- AArch64FunctionInfo *FuncInfo = MF->getInfo<AArch64FunctionInfo>();
- const TargetInstrInfo *TII = Subtarget->getInstrInfo();
- if (FuncInfo->isSMESaveBufferUsed()) {
- RTLIB::Libcall LC = RTLIB::SMEABI_SME_STATE_SIZE;
- const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::BL))
- .addExternalSymbol(getLibcallName(LC))
- .addReg(AArch64::X0, RegState::ImplicitDefine)
- .addRegMask(TRI->getCallPreservedMask(*MF, getLibcallCallingConv(LC)));
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
- MI.getOperand(0).getReg())
- .addReg(AArch64::X0);
- } else
- BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
- MI.getOperand(0).getReg())
- .addReg(AArch64::XZR);
- BB->remove_instr(&MI);
- return BB;
-}
-
MachineBasicBlock *
AArch64TargetLowering::EmitEntryPStateSM(MachineInstr &MI,
MachineBasicBlock *BB) const {
@@ -3524,14 +3394,6 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
MI.dump();
#endif
llvm_unreachable("Unexpected instruction for custom inserter!");
- case AArch64::InitTPIDR2Obj:
- return EmitInitTPIDR2Object(MI, BB);
- case AArch64::AllocateZABuffer:
- return EmitAllocateZABuffer(MI, BB);
- case AArch64::AllocateSMESaveBuffer:
- return EmitAllocateSMESaveBuffer(MI, BB);
- case AArch64::GetSMESaveSize:
- return EmitGetSMESaveSize(MI, BB);
case AArch64::EntryPStateSM:
return EmitEntryPStateSM(MI, BB);
case AArch64::F128CSEL:
@@ -8748,81 +8610,6 @@ static bool isPassedInFPR(EVT VT) {
(VT.isFloatingPoint() && !VT.isScalableVector());
}
-static SDValue getZT0FrameIndex(MachineFrameInfo &MFI,
- AArch64FunctionInfo &FuncInfo,
- SelectionDAG &DAG) {
- if (!FuncInfo.hasZT0SpillSlotIndex())
- FuncInfo.setZT0SpillSlotIndex(MFI.CreateSpillStackObject(64, Align(16)));
-
- return DAG.getFrameIndex(
- FuncInfo.getZT0SpillSlotIndex(),
- DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()));
-}
-
-// Emit a call to __arm_sme_save or __arm_sme_restore.
-static SDValue emitSMEStateSaveRestore(const AArch64TargetLowering &TLI,
- SelectionDAG &DAG,
- AArch64FunctionInfo *Info, SDLoc DL,
- SDValue Chain, bool IsSave) {
- MachineFunction &MF = DAG.getMachineFunction();
- AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
- FuncInfo->setSMESaveBufferUsed();
- TargetLowering::ArgListTy Args;
- Args.emplace_back(
- DAG.getCopyFromReg(Chain, DL, Info->getSMESaveBufferAddr(), MVT::i64),
- PointerType::getUnqual(*DAG.getContext()));
-
- RTLIB::Libcall LC =
- IsSave ? RTLIB::SMEABI_SME_SAVE : RTLIB::SMEABI_SME_RESTORE;
- RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(LC);
- SDValue Callee =
- DAG.getExternalSymbol(LCImpl, TLI.getPointerTy(DAG.getDataLayout()));
- auto *RetTy = Type::getVoidTy(*DAG.getContext());
- TargetLowering::CallLoweringInfo CLI(DAG);
- CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
- DAG.getLibcalls().getLibcallImplCallingConv(LCImpl), RetTy, Callee,
- std::move(Args));
- return TLI.LowerCallTo(CLI).second;
-}
-
-static SDValue emitRestoreZALazySave(SDValue Chain, SDLoc DL,
- const AArch64TargetLowering &TLI,
- const AArch64RegisterInfo &TRI,
- AArch64FunctionInfo &FuncInfo,
- SelectionDAG &DAG) {
- // Conditionally restore the lazy save using a pseudo node.
- RTLIB::Libcall LC = RTLIB::SMEABI_TPIDR2_RESTORE;
- TPIDR2Object &TPIDR2 = FuncInfo.getTPIDR2Obj();
-
- RTLIB::LibcallImpl LibcallImpl = DAG.getLibcalls().getLibcallImpl(LC);
- SDValue RegMask = DAG.getRegisterMask(TRI.getCallPreservedMask(
- DAG.getMachineFunction(),
- DAG.getLibcalls().getLibcallImplCallingConv(LibcallImpl)));
- SDValue RestoreRoutine = DAG.getTargetExternalSymbol(
- LibcallImpl, TLI.getPointerTy(DAG.getDataLayout()));
- SDValue TPIDR2_EL0 = DAG.getNode(
- ISD::INTRINSIC_W_CHAIN, DL, MVT::i64, Chain,
- DAG.getTargetConstant(Intrinsic::aarch64_sme_get_tpidr2, DL, MVT::i32));
- // Copy the address of the TPIDR2 block into X0 before 'calling' the
- // RESTORE_ZA pseudo.
- SDValue Glue;
- SDValue TPIDR2Block = DAG.getFrameIndex(
- TPIDR2.FrameIndex,
- DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()));
- Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, TPIDR2Block, Glue);
- Chain =
- DAG.getNode(AArch64ISD::RESTORE_ZA, DL, MVT::Other,
- {Chain, TPIDR2_EL0, DAG.getRegister(AArch64::X0, MVT::i64),
- RestoreRoutine, RegMask, Chain.getValue(1)});
- // Finally reset the TPIDR2_EL0 register to 0.
- Chain = DAG.getNode(
- ISD::INTRINSIC_VOID, DL, MVT::Other, Chain,
- DAG.getTargetConstant(Intrinsic::aarch64_sme_set_tpidr2, DL, MVT::i32),
- DAG.getConstant(0, DL, MVT::i64));
- TPIDR2.Uses++;
- return Chain;
-}
-
SDValue AArch64TargetLowering::lowerEHPadEntry(SDValue Chain, SDLoc const &DL,
SelectionDAG &DAG) const {
assert(Chain.getOpcode() == ISD::EntryToken && "Unexpected Chain value");
@@ -8830,8 +8617,6 @@ SDValue AArch64TargetLowering::lowerEHPadEntry(SDValue Chain, SDLoc const &DL,
MachineFunction &MF = DAG.getMachineFunction();
auto &FuncInfo = *MF.getInfo<AArch64FunctionInfo>();
- auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
- const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
SMEAttrs SMEFnAttrs = FuncInfo.getSMEFnAttrs();
@@ -8858,34 +8643,6 @@ SDValue AArch64TargetLowering::lowerEHPadEntry(SDValue Chain, SDLoc const &DL,
else if (SMEFnAttrs.hasStreamingCompatibleInterface())
Chain = changeStreamingMode(DAG, DL, /*Enable=*/true, Chain, Glue,
AArch64SME::IfCallerIsStreaming);
-
- if (getTM().useNewSMEABILowering())
- return Chain;
-
- if (SMEFnAttrs.hasAgnosticZAInterface()) {
- // Restore full ZA
- Chain = emitSMEStateSaveRestore(*this, DAG, &FuncInfo, DL, Chain,
- /*IsSave=*/false);
- } else if (SMEFnAttrs.hasZAState() || SMEFnAttrs.hasZT0State()) {
- // SMSTART ZA
- Chain = DAG.getNode(
- AArch64ISD::SMSTART, DL, DAG.getVTList(MVT::Other, MVT::Glue), Chain,
- DAG.getTargetConstant(int32_t(AArch64SVCR::SVCRZA), DL, MVT::i32));
-
- // Restore ZT0
- if (SMEFnAttrs.hasZT0State()) {
- SDValue ZT0FrameIndex =
- getZT0FrameIndex(MF.getFrameInfo(), FuncInfo, DAG);
- Chain =
- DAG.getNode(AArch64ISD::RESTORE_ZT, DL, DAG.getVTList(MVT::Other),
- {Chain, DAG.getConstant(0, DL, MVT::i32), ZT0FrameIndex});
- }
-
- // Restore ZA
- if (SMEFnAttrs.hasZAState())
- Chain = emitRestoreZALazySave(Chain, DL, *this, TRI, FuncInfo, DAG);
- }
-
return Chain;
}
@@ -9300,91 +9057,38 @@ SDValue AArch64TargetLowering::LowerFormalArguments(
if (Subtarget->hasCustomCallingConv())
Subtarget->getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
- if (getTM().useNewSMEABILowering()) {
- if (Subtarget->isTargetWindows() || hasInlineStackProbe(MF)) {
- SDValue Size;
- if (Attrs.hasZAState()) {
- SDValue SVL = DAG.getNode(AArch64ISD::RDSVL, DL, MVT::i64,
- DAG.getConstant(1, DL, MVT::i32));
- Size = DAG.getNode(ISD::MUL, DL, MVT::i64, SVL, SVL);
- } else if (Attrs.hasAgnosticZAInterface()) {
- RTLIB::Libcall LC = RTLIB::SMEABI_SME_STATE_SIZE;
- RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(LC);
-
- SDValue Callee =
- DAG.getExternalSymbol(LCImpl, getPointerTy(DAG.getDataLayout()));
- auto *RetTy = EVT(MVT::i64).getTypeForEVT(*DAG.getContext());
- TargetLowering::CallLoweringInfo CLI(DAG);
- CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
- DAG.getLibcalls().getLibcallImplCallingConv(LCImpl), RetTy, Callee,
- {});
- std::tie(Size, Chain) = LowerCallTo(CLI);
- }
- if (Size) {
- SDValue Buffer = DAG.getNode(
- ISD::DYNAMIC_STACKALLOC, DL, DAG.getVTList(MVT::i64, MVT::Other),
- {Chain, Size, DAG.getConstant(1, DL, MVT::i64)});
- Chain = Buffer.getValue(1);
-
- Register BufferPtr =
- MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
- Chain = DAG.getCopyToReg(Chain, DL, BufferPtr, Buffer);
- Chain = DAG.getNode(AArch64ISD::SME_STATE_ALLOC, DL,
- DAG.getVTList(MVT::Other), Chain);
- FuncInfo->setEarlyAllocSMESaveBuffer(BufferPtr);
- MFI.CreateVariableSizedObject(Align(16), nullptr);
- }
- }
- } else {
- // Old SME ABI lowering (deprecated):
- // Create a 16 Byte TPIDR2 object. The dynamic buffer
- // will be expanded and stored in the static object later using a
- // pseudonode.
+ if (Subtarget->isTargetWindows() || hasInlineStackProbe(MF)) {
+ SDValue Size;
if (Attrs.hasZAState()) {
- TPIDR2Object &TPIDR2 = FuncInfo->getTPIDR2Obj();
- TPIDR2.FrameIndex = MFI.CreateStackObject(16, Align(16), false);
SDValue SVL = DAG.getNode(AArch64ISD::RDSVL, DL, MVT::i64,
DAG.getConstant(1, DL, MVT::i32));
- SDValue Buffer;
- if (!Subtarget->isTargetWindows() && !hasInlineStackProbe(MF)) {
- Buffer = DAG.getNode(AArch64ISD::ALLOCATE_ZA_BUFFER, DL,
- DAG.getVTList(MVT::i64, MVT::Other), {Chain, SVL});
- } else {
- SDValue Size = DAG.getNode(ISD::MUL, DL, MVT::i64, SVL, SVL);
- Buffer = DAG.getNode(ISD::DYNAMIC_STACKALLOC, DL,
- DAG.getVTList(MVT::i64, MVT::Other),
- {Chain, Size, DAG.getConstant(1, DL, MVT::i64)});
- MFI.CreateVariableSizedObject(Align(16), nullptr);
- }
- SDValue NumZaSaveSlices = DAG.getNode(AArch64ISD::RDSVL, DL, MVT::i64,
- DAG.getConstant(1, DL, MVT::i32));
- Chain = DAG.getNode(
- AArch64ISD::INIT_TPIDR2OBJ, DL, DAG.getVTList(MVT::Other),
- {/*Chain*/ Buffer.getValue(1), /*Buffer ptr*/ Buffer.getValue(0),
- /*Num save slices*/ NumZaSaveSlices});
+ Size = DAG.getNode(ISD::MUL, DL, MVT::i64, SVL, SVL);
} else if (Attrs.hasAgnosticZAInterface()) {
- // Call __arm_sme_state_size().
- SDValue BufferSize =
- DAG.getNode(AArch64ISD::GET_SME_SAVE_SIZE, DL,
- DAG.getVTList(MVT::i64, MVT::Other), Chain);
- Chain = BufferSize.getValue(1);
- SDValue Buffer;
- if (!Subtarget->isTargetWindows() && !hasInlineStackProbe(MF)) {
- Buffer = DAG.getNode(AArch64ISD::ALLOC_SME_SAVE_BUFFER, DL,
- DAG.getVTList(MVT::i64, MVT::Other),
- {Chain, BufferSize});
- } else {
- // Allocate space dynamically.
- Buffer = DAG.getNode(
- ISD::DYNAMIC_STACKALLOC, DL, DAG.getVTList(MVT::i64, MVT::Other),
- {Chain, BufferSize, DAG.getConstant(1, DL, MVT::i64)});
- MFI.CreateVariableSizedObject(Align(16), nullptr);
- }
- // Copy the value to a virtual register, and save that in FuncInfo.
+ RTLIB::Libcall LC = RTLIB::SMEABI_SME_STATE_SIZE;
+ RTLIB::LibcallImpl LCImpl = DAG.getLibcalls().getLibcallImpl(LC);
+
+ SDValue Callee =
+ DAG.getExternalSymbol(LCImpl, getPointerTy(DAG.getDataLayout()));
+ auto *RetTy = EVT(MVT::i64).getTypeForEVT(*DAG.getContext());
+ TargetLowering::CallLoweringInfo CLI(DAG);
+ CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
+ DAG.getLibcalls().getLibcallImplCallingConv(LCImpl), RetTy, Callee,
+ {});
+ std::tie(Size, Chain) = LowerCallTo(CLI);
+ }
+ if (Size) {
+ SDValue Buffer = DAG.getNode(
+ ISD::DYNAMIC_STACKALLOC, DL, DAG.getVTList(MVT::i64, MVT::Other),
+ {Chain, Size, DAG.getConstant(1, DL, MVT::i64)});
+ Chain = Buffer.getValue(1);
+
Register BufferPtr =
MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
- FuncInfo->setSMESaveBufferAddr(BufferPtr);
- Chain = DAG.getCopyToReg(Buffer.getValue(1), DL, BufferPtr, Buffer);
+ Chain = DAG.getCopyToReg(Chain, DL, BufferPtr, Buffer);
+ Chain = DAG.getNode(AArch64ISD::SME_STATE_ALLOC, DL,
+ DAG.getVTList(MVT::Other), Chain);
+ FuncInfo->setEarlyAllocSMESaveBuffer(BufferPtr);
+ MFI.CreateVariableSizedObject(Align(16), nullptr);
}
}
@@ -10118,18 +9822,12 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
getSMECallAttrs(MF.getFunction(), getRuntimeLibcallsInfo(), CLI);
std::optional<unsigned> ZAMarkerNode;
- bool UseNewSMEABILowering = getTM().useNewSMEABILowering();
-
- if (UseNewSMEABILowering) {
- if (CallAttrs.requiresLazySave() ||
- CallAttrs.requiresPreservingAllZAState())
- ZAMarkerNode = AArch64ISD::REQUIRES_ZA_SAVE;
- else if (CallAttrs.requiresPreservingZT0())
- ZAMarkerNode = AArch64ISD::REQUIRES_ZT0_SAVE;
- else if (CallAttrs.caller().hasZAState() ||
- CallAttrs.caller().hasZT0State())
- ZAMarkerNode = AArch64ISD::INOUT_ZA_USE;
- }
+ if (CallAttrs.requiresLazySave() || CallAttrs.requiresPreservingAllZAState())
+ ZAMarkerNode = AArch64ISD::REQUIRES_ZA_SAVE;
+ else if (CallAttrs.requiresPreservingZT0())
+ ZAMarkerNode = AArch64ISD::REQUIRES_ZT0_SAVE;
+ else if (CallAttrs.caller().hasZAState() || CallAttrs.caller().hasZT0State())
+ ZAMarkerNode = AArch64ISD::INOUT_ZA_USE;
if (IsTailCall) {
// Check if it's really possible to do a tail call.
@@ -10203,33 +9901,6 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
return R;
};
- bool RequiresLazySave = !UseNewSMEABILowering && CallAttrs.requiresLazySave();
- bool RequiresSaveAllZA =
- !UseNewSMEABILowering && CallAttrs.requiresPreservingAllZAState();
- if (RequiresLazySave) {
- TPIDR2Object &TPIDR2 = FuncInfo->getTPIDR2Obj();
- SDValue TPIDR2ObjAddr = DAG.getFrameIndex(
- TPIDR2.FrameIndex,
- DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()));
- Chain = DAG.getNode(
- ISD::INTRINSIC_VOID, DL, MVT::Other, Chain,
- DAG.getTargetConstant(Intrinsic::aarch64_sme_set_tpidr2, DL, MVT::i32),
- TPIDR2ObjAddr);
- OptimizationRemarkEmitter ORE(&MF.getFunction());
- ORE.emit([&]() {
- auto R = CLI.CB ? OptimizationRemarkAnalysis("sme", "SMELazySaveZA",
- CLI.CB)
- : OptimizationRemarkAnalysis("sme", "SMELazySaveZA",
- &MF.getFunction());
- return DescribeCallsite(R) << " sets up a lazy save for ZA";
- });
- } else if (RequiresSaveAllZA) {
- assert(!CallAttrs.callee().hasSharedZAInterface() &&
- "Cannot share state that may not exist");
- Chain = emitSMEStateSaveRestore(*this, DAG, FuncInfo, DL, Chain,
- /*IsSave=*/true);
- }
-
bool RequiresSMChange = CallAttrs.requiresSMChange();
if (RequiresSMChange) {
OptimizationRemarkEmitter ORE(&MF.getFunction());
@@ -10243,32 +9914,6 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
});
}
- SDValue ZTFrameIdx;
- MachineFrameInfo &MFI = MF.getFrameInfo();
- bool ShouldPreserveZT0 =
- !UseNewSMEABILowering && CallAttrs.requiresPreservingZT0();
-
- // If the caller has ZT0 state which will not be preserved by the callee,
- // spill ZT0 before the call.
- if (ShouldPreserveZT0) {
- ZTFrameIdx = getZT0FrameIndex(MFI, *FuncInfo, DAG);
-
- Chain = DAG.getNode(AArch64ISD::SAVE_ZT, DL, DAG.getVTList(MVT::Other),
- {Chain, DAG.getConstant(0, DL, MVT::i32), ZTFrameIdx});
- }
-
- // If caller shares ZT0 but the callee is not shared ZA, we need to stop
- // PSTATE.ZA before the call if there is no lazy-save active.
- bool DisableZA =
- !UseNewSMEABILowering && CallAttrs.requiresDisablingZABeforeCall();
- assert((!DisableZA || !RequiresLazySave) &&
- "Lazy-save should have PSTATE.SM=1 on entry to the function");
-
- if (DisableZA)
- Chain = DAG.getNode(
- AArch64ISD::SMSTOP, DL, DAG.getVTList(MVT::Other, MVT::Glue), Chain,
- DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
-
// Adjust the stack pointer for the new arguments... and mark ZA uses.
// These operations are automatically eliminated by the prolog/epilog pass
assert((!IsSibCall || !ZAMarkerNode) && "ZA markers require CALLSEQ_START");
@@ -10742,27 +10387,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
getSMToggleCondition(CallAttrs));
}
- if (!UseNewSMEABILowering &&
- (RequiresLazySave || CallAttrs.requiresEnablingZAAfterCall()))
- // Unconditionally resume ZA.
- Result = DAG.getNode(
- AArch64ISD::SMSTART, DL, DAG.getVTList(MVT::Other, MVT::Glue), Result,
- DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
-
- if (ShouldPreserveZT0)
- Result =
- DAG.getNode(AArch64ISD::RESTORE_ZT, DL, DAG.getVTList(MVT::Other),
- {Result, DAG.getConstant(0, DL, MVT::i32), ZTFrameIdx});
-
- if (RequiresLazySave) {
- Result = emitRestoreZALazySave(Result, DL, *this, *TRI, *FuncInfo, DAG);
- } else if (RequiresSaveAllZA) {
- Result = emitSMEStateSaveRestore(*this, DAG, FuncInfo, DL, Result,
- /*IsSave=*/false);
- }
-
- if (RequiresSMChange || RequiresLazySave || ShouldPreserveZT0 ||
- RequiresSaveAllZA) {
+ if (RequiresSMChange) {
for (unsigned I = 0; I < InVals.size(); ++I) {
// The smstart/smstop is chained as part of the call, but when the
// resulting chain is discarded (which happens when the call is not part
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 49ff76bb2f469..58efdd3e18fc0 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -184,18 +184,6 @@ class AArch64TargetLowering : public TargetLowering {
MachineBasicBlock *EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB,
unsigned Opcode, bool Op0IsDef) const;
MachineBasicBlock *EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const;
-
- // Note: The following group of functions are only used as part of the old SME
- // ABI lowering. They will be removed once -aarch64-new-sme-abi=true is the
- // default.
- MachineBasicBlock *EmitInitTPIDR2Object(MachineInstr &MI,
- MachineBasicBlock *BB) const;
- MachineBasicBlock *EmitAllocateZABuffer(MachineInstr &MI,
- MachineBasicBlock *BB) const;
- MachineBasicBlock *EmitAllocateSMESaveBuffer(MachineInstr &MI,
- MachineBasicBlock *BB) const;
- MachineBasicBlock *EmitGetSMESaveSize(MachineInstr &MI,
- MachineBasicBlock *BB) const;
MachineBasicBlock *EmitEntryPStateSM(MachineInstr &MI,
MachineBasicBlock *BB) const;
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
index 00e0c2511aaf0..60a5a978bb09a 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
@@ -37,11 +37,6 @@ struct AArch64FunctionInfo;
class AArch64Subtarget;
class MachineInstr;
-struct TPIDR2Object {
- int FrameIndex = std::numeric_limits<int>::max();
- unsigned Uses = 0;
-};
-
/// Condition of signing the return address in a function.
///
/// Corresponds to possible values of "sign-return-address" function attribute.
@@ -245,19 +240,6 @@ class AArch64FunctionInfo final : public MachineFunctionInfo {
// support).
Register EarlyAllocSMESaveBuffer = AArch64::NoRegister;
- // Holds the spill slot for ZT0.
- int ZT0SpillSlotIndex = std::numeric_limits<int>::max();
-
- // Note: The following properties are only used for the old SME ABI lowering:
- /// The frame-index for the TPIDR2 object used for lazy saves.
- TPIDR2Object TPIDR2;
- // Holds a pointer to a buffer that is large enough to represent
- // all SME ZA state and any additional state required by the
- // __arm_sme_save/restore support routines.
- Register SMESaveBufferAddr = MCRegister::NoRegister;
- // true if SMESaveBufferAddr is used.
- bool SMESaveBufferUsed = false;
-
public:
AArch64FunctionInfo(const Function &F, const AArch64Subtarget *STI);
@@ -274,22 +256,6 @@ class AArch64FunctionInfo final : public MachineFunctionInfo {
return EarlyAllocSMESaveBuffer;
}
- void setZT0SpillSlotIndex(int FI) { ZT0SpillSlotIndex = FI; }
- int getZT0SpillSlotIndex() const {
- assert(hasZT0SpillSlotIndex() && "ZT0 spill slot index not set!");
- return ZT0SpillSlotIndex;
- }
- bool hasZT0SpillSlotIndex() const {
- return ZT0SpillSlotIndex != std::numeric_limits<int>::max();
- }
-
- // Old SME ABI lowering state getters/setters:
- Register getSMESaveBufferAddr() const { return SMESaveBufferAddr; };
- void setSMESaveBufferAddr(Register Reg) { SMESaveBufferAddr = Reg; };
- unsigned isSMESaveBufferUsed() const { return SMESaveBufferUsed; };
- void setSMESaveBufferUsed(bool Used = true) { SMESaveBufferUsed = Used; };
- TPIDR2Object &getTPIDR2Obj() { return TPIDR2; }
-
void setPredicateRegForFillSpill(unsigned Reg) {
PredicateRegForFillSpill = Reg;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SMEAttributes.cpp b/llvm/lib/Target/AArch64/AArch64SMEAttributes.cpp
index 085c858820568..dd9f74df3609c 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEAttributes.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SMEAttributes.cpp
@@ -41,6 +41,9 @@ void SMEAttrs::validate() const {
}
SMEAttrs::SMEAttrs(const AttributeList &Attrs) {
+ // Note: 'aarch64_zt0_undef' was previously used (and subsequently removed).
+ // To avoid introducing any compatibility issues don't reuse
+ // 'aarch64_zt0_undef' for another purpose.
Bitmask = 0;
if (Attrs.hasFnAttr("aarch64_pstate_sm_enabled"))
Bitmask |= SM_Enabled;
@@ -50,8 +53,6 @@ SMEAttrs::SMEAttrs(const AttributeList &Attrs) {
Bitmask |= SM_Body;
if (Attrs.hasFnAttr("aarch64_za_state_agnostic"))
Bitmask |= ZA_State_Agnostic;
- if (Attrs.hasFnAttr("aarch64_zt0_undef"))
- Bitmask |= ZT0_Undef;
if (Attrs.hasFnAttr("aarch64_in_za"))
Bitmask |= encodeZAState(StateValue::In);
if (Attrs.hasFnAttr("aarch64_out_za"))
@@ -133,8 +134,7 @@ SMECallAttrs::SMECallAttrs(const CallBase &CB,
// FIXME: We probably should not allow SME attributes on direct calls but
// clang duplicates streaming mode attributes at each callsite.
- assert((IsIndirect ||
- ((Callsite.withoutPerCallsiteFlags() | CalledFn) == CalledFn)) &&
+ assert((IsIndirect || ((Callsite | CalledFn) == CalledFn)) &&
"SME attributes at callsite do not match declaration");
// An `invoke` of an agnostic ZA function may not return normally (it may
diff --git a/llvm/lib/Target/AArch64/AArch64SMEAttributes.h b/llvm/lib/Target/AArch64/AArch64SMEAttributes.h
index 28c397e221fdc..a01333087594a 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEAttributes.h
+++ b/llvm/lib/Target/AArch64/AArch64SMEAttributes.h
@@ -43,12 +43,10 @@ class SMEAttrs {
SM_Body = 1 << 2, // aarch64_pstate_sm_body
SME_ABI_Routine = 1 << 3, // Used for SME ABI routines to avoid lazy saves
ZA_State_Agnostic = 1 << 4,
- ZT0_Undef = 1 << 5, // Use to mark ZT0 as undef to avoid spills
ZA_Shift = 6,
ZA_Mask = 0b111 << ZA_Shift,
ZT0_Shift = 9,
- ZT0_Mask = 0b111 << ZT0_Shift,
- CallSiteFlags_Mask = ZT0_Undef
+ ZT0_Mask = 0b111 << ZT0_Shift
};
SMEAttrs() = default;
@@ -134,7 +132,6 @@ class SMEAttrs {
bool isPreservesZT0() const {
return decodeZT0State(Bitmask) == StateValue::Preserved;
}
- bool hasUndefZT0() const { return Bitmask & ZT0_Undef; }
bool sharesZT0() const {
StateValue State = decodeZT0State(Bitmask);
return State == StateValue::In || State == StateValue::Out ||
@@ -148,10 +145,6 @@ class SMEAttrs {
return Merged;
}
- SMEAttrs withoutPerCallsiteFlags() const {
- return (Bitmask & ~CallSiteFlags_Mask);
- }
-
bool operator==(SMEAttrs const &Other) const {
return Bitmask == Other.Bitmask;
}
@@ -197,8 +190,8 @@ class SMECallAttrs {
}
bool requiresPreservingZT0() const {
- return caller().hasZT0State() && !callsite().hasUndefZT0() &&
- !callee().sharesZT0() && !callee().hasAgnosticZAInterface();
+ return caller().hasZT0State() && !callee().sharesZT0() &&
+ !callee().hasAgnosticZAInterface();
}
bool requiresDisablingZABeforeCall() const {
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 905eed50dee9a..022fed6473486 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -26,10 +26,6 @@ def AArch64_cond_smstop : SDNode<"AArch64ISD::COND_SMSTOP", SDTypeProfile<0, 3,
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>,
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
SDNPOptInGlue, SDNPOutGlue]>;
-def AArch64_restore_za : SDNode<"AArch64ISD::RESTORE_ZA", SDTypeProfile<0, 3,
- [SDTCisInt<0>, SDTCisPtrTy<1>]>,
- [SDNPHasChain, SDNPSideEffect, SDNPVariadic,
- SDNPOptInGlue]>;
def AArch64_restore_zt : SDNode<"AArch64ISD::RESTORE_ZT", SDTypeProfile<0, 2,
[SDTCisInt<0>, SDTCisPtrTy<1>]>,
[SDNPHasChain, SDNPSideEffect, SDNPMayLoad]>;
@@ -60,53 +56,16 @@ def AArch64_check_matching_vl
def : Pat<(AArch64_check_matching_vl), (CHECK_MATCHING_VL_PSEUDO)>;
//===----------------------------------------------------------------------===//
-// Old SME ABI lowering ISD nodes/pseudos (deprecated)
-//===----------------------------------------------------------------------===//
-
-def AArch64AllocateZABuffer : SDNode<"AArch64ISD::ALLOCATE_ZA_BUFFER", SDTypeProfile<1, 1,
- [SDTCisInt<0>, SDTCisInt<1>]>,
- [SDNPHasChain, SDNPSideEffect]>;
-let usesCustomInserter = 1, Defs = [SP], Uses = [SP] in {
- def AllocateZABuffer : Pseudo<(outs GPR64sp:$dst), (ins GPR64:$size), []>, Sched<[WriteI]> {}
-}
-def : Pat<(i64 (AArch64AllocateZABuffer GPR64:$size)),
- (AllocateZABuffer $size)>;
-
-def AArch64InitTPIDR2Obj : SDNode<"AArch64ISD::INIT_TPIDR2OBJ", SDTypeProfile<0, 2,
- [SDTCisInt<0>, SDTCisInt<1>]>, [SDNPHasChain, SDNPMayStore]>;
-let usesCustomInserter = 1 in {
- def InitTPIDR2Obj : Pseudo<(outs), (ins GPR64:$buffer, GPR64:$save_slices), [(AArch64InitTPIDR2Obj GPR64:$buffer, GPR64:$save_slices)]>, Sched<[WriteI]> {}
-}
-
-// Nodes to allocate a save buffer for SME.
-// Needed for __arm_agnostic("sme_za_state").
-def AArch64SMESaveSize : SDNode<"AArch64ISD::GET_SME_SAVE_SIZE", SDTypeProfile<1, 0,
- [SDTCisInt<0>]>, [SDNPHasChain]>;
-let usesCustomInserter = 1, Defs = [X0] in {
- def GetSMESaveSize : Pseudo<(outs GPR64:$dst), (ins), []>, Sched<[]> {}
-}
-def : Pat<(i64 AArch64SMESaveSize), (GetSMESaveSize)>;
-
-def AArch64AllocateSMESaveBuffer : SDNode<"AArch64ISD::ALLOC_SME_SAVE_BUFFER", SDTypeProfile<1, 1,
- [SDTCisInt<0>, SDTCisInt<1>]>, [SDNPHasChain]>;
-let usesCustomInserter = 1, Defs = [SP] in {
- def AllocateSMESaveBuffer : Pseudo<(outs GPR64sp:$dst), (ins GPR64:$size), []>, Sched<[WriteI]> {}
-}
-def : Pat<(i64 (AArch64AllocateSMESaveBuffer GPR64:$size)),
- (AllocateSMESaveBuffer $size)>;
-
-//===----------------------------------------------------------------------===//
-// New SME ABI lowering ISD nodes/pseudos (-aarch64-new-sme-abi)
+// SME ABI lowering ISD nodes/pseudos
//===----------------------------------------------------------------------===//
let hasSideEffects = 1, isMeta = 1 in {
def InOutZAUsePseudo : Pseudo<(outs), (ins), []>, Sched<[]>;
def RequiresZASavePseudo : Pseudo<(outs), (ins), []>, Sched<[]>;
def RequiresZT0SavePseudo : Pseudo<(outs), (ins), []>, Sched<[]>;
+ def SMEStateAllocPseudo : Pseudo<(outs), (ins), []>, Sched<[]>;
}
-def SMEStateAllocPseudo : Pseudo<(outs), (ins), []>, Sched<[]>;
-
def CommitZASavePseudo
: Pseudo<(outs),
(ins GPR64:$tpidr2_el0, i1imm:$zero_za, i1imm:$zero_zt0,
@@ -320,10 +279,6 @@ def RestoreZAPseudo :
(ins GPR64:$tpidr2_el0, GPR64sp:$tpidr2obj, i64imm:$restore_routine, variable_ops), []>,
Sched<[]>;
-def : Pat<(AArch64_restore_za
- (i64 GPR64:$tpidr2_el0), (i64 GPR64sp:$tpidr2obj), (i64 texternalsym:$restore_routine)),
- (RestoreZAPseudo GPR64:$tpidr2_el0, GPR64sp:$tpidr2obj, texternalsym:$restore_routine)>;
-
// Read and write TPIDR2_EL0
def : Pat<(int_aarch64_sme_set_tpidr2 i64:$val),
(MSR 0xde85, GPR64:$val)>;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 37d893435ca9b..929001ed0ae6b 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -222,11 +222,6 @@ static cl::opt<bool>
cl::desc("Enable Machine Pipeliner for AArch64"),
cl::init(false), cl::Hidden);
-static cl::opt<bool>
- EnableNewSMEABILowering("aarch64-new-sme-abi",
- cl::desc("Enable new lowering for the SME ABI"),
- cl::init(true), cl::Hidden);
-
static cl::opt<bool> EnableSRLTSubregToRegMitigation(
"aarch64-srlt-mitigate-sr2r",
cl::desc("Enable SUBREG_TO_REG mitigation by adding 'implicit-def' for "
@@ -272,7 +267,6 @@ LLVMInitializeAArch64Target() {
initializeFalkorMarkStridedAccessesLegacyPass(PR);
initializeLDTLSCleanupPass(PR);
initializeKCFIPass(PR);
- initializeSMEABIPass(PR);
initializeMachineSMEABIPass(PR);
initializeAArch64SRLTDefineSuperRegsPass(PR);
initializeSMEPeepholeOptPass(PR);
@@ -357,8 +351,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
computeDefaultCPU(TT, CPU), FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
- TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian),
- UseNewSMEABILowering(EnableNewSMEABILowering) {
+ TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
initAsmInfo();
if (TT.isOSBinFormatMachO()) {
@@ -693,13 +686,6 @@ void AArch64PassConfig::addIRPasses() {
addPass(createInterleavedAccessPass());
}
- if (!EnableNewSMEABILowering) {
- // Expand any functions marked with SME attributes which require special
- // changes for the calling convention or that require the lazy-saving
- // mechanism specified in the SME ABI.
- addPass(createSMEABIPass());
- }
-
// Add Control Flow Guard checks.
if (TM->getTargetTriple().isOSWindows()) {
if (TM->getTargetTriple().isWindowsArm64EC())
@@ -802,7 +788,7 @@ bool AArch64PassConfig::addGlobalInstructionSelect() {
}
void AArch64PassConfig::addMachineSSAOptimization() {
- if (TM->getOptLevel() != CodeGenOptLevel::None && EnableNewSMEABILowering)
+ if (TM->getOptLevel() != CodeGenOptLevel::None)
addPass(createMachineSMEABIPass(TM->getOptLevel()));
if (TM->getOptLevel() != CodeGenOptLevel::None && EnableSMEPeepholeOpt)
@@ -835,7 +821,7 @@ bool AArch64PassConfig::addILPOpts() {
}
void AArch64PassConfig::addPreRegAlloc() {
- if (TM->getOptLevel() == CodeGenOptLevel::None && EnableNewSMEABILowering)
+ if (TM->getOptLevel() == CodeGenOptLevel::None)
addPass(createMachineSMEABIPass(CodeGenOptLevel::None));
// Change dead register definitions to refer to the zero register.
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index 25ab66f36f8ec..209374553d297 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -79,15 +79,11 @@ class AArch64TargetMachine : public CodeGenTargetMachineImpl {
size_t clearLinkerOptimizationHints(
const SmallPtrSetImpl<MachineInstr *> &MIs) const override;
- /// Returns true if the new SME ABI lowering should be used.
- bool useNewSMEABILowering() const { return UseNewSMEABILowering; }
-
/// Returns the optimisation level that enables GlobalISel.
unsigned getEnableGlobalISelAtO() const;
private:
bool isLittle;
- bool UseNewSMEABILowering;
};
// AArch64 little endian target machine.
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt
index 2fe554217c1ba..0c9a567278c56 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -88,7 +88,6 @@ add_llvm_target(AArch64CodeGen
AArch64TargetMachine.cpp
AArch64TargetObjectFile.cpp
AArch64TargetTransformInfo.cpp
- SMEABIPass.cpp
SMEPeepholeOpt.cpp
SVEIntrinsicOpts.cpp
MachineSMEABIPass.cpp
diff --git a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
index 406f9bdddaec0..4462af1ca306f 100644
--- a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+++ b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
@@ -1168,14 +1168,13 @@ INITIALIZE_PASS(MachineSMEABI, "aarch64-machine-sme-abi", "Machine SME ABI",
false, false)
bool MachineSMEABI::runOnMachineFunction(MachineFunction &MF) {
- Subtarget = &MF.getSubtarget<AArch64Subtarget>();
-
AFI = MF.getInfo<AArch64FunctionInfo>();
SMEAttrs SMEFnAttrs = AFI->getSMEFnAttrs();
if (!SMEFnAttrs.hasZAState() && !SMEFnAttrs.hasZT0State() &&
!SMEFnAttrs.hasAgnosticZAInterface())
return false;
+ Subtarget = &MF.getSubtarget<AArch64Subtarget>();
if (!Subtarget->hasSME() && !SMEFnAttrs.hasAgnosticZAInterface())
return false;
diff --git a/llvm/lib/Target/AArch64/SMEABIPass.cpp b/llvm/lib/Target/AArch64/SMEABIPass.cpp
deleted file mode 100644
index 4245afbbf6beb..0000000000000
--- a/llvm/lib/Target/AArch64/SMEABIPass.cpp
+++ /dev/null
@@ -1,195 +0,0 @@
-//===--------- SMEABI - SME ABI-------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass implements parts of the the SME ABI, such as:
-// * Using the lazy-save mechanism before enabling the use of ZA.
-// * Setting up the lazy-save mechanism around invokes.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AArch64.h"
-#include "AArch64SMEAttributes.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/CodeGen/TargetSubtargetInfo.h"
-#include "llvm/IR/IRBuilder.h"
-#include "llvm/IR/Instructions.h"
-#include "llvm/IR/IntrinsicsAArch64.h"
-#include "llvm/IR/LLVMContext.h"
-#include "llvm/IR/Module.h"
-#include "llvm/IR/RuntimeLibcalls.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Transforms/Utils/Cloning.h"
-
-using namespace llvm;
-
-#define DEBUG_TYPE "aarch64-sme-abi"
-
-namespace {
-struct SMEABI : public FunctionPass {
- static char ID; // Pass identification, replacement for typeid
- SMEABI() : FunctionPass(ID) {}
-
- bool runOnFunction(Function &F) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<TargetPassConfig>();
- }
-
-private:
- bool updateNewStateFunctions(Module *M, Function *F, IRBuilder<> &Builder,
- SMEAttrs FnAttrs, const TargetLowering &TLI);
-};
-} // end anonymous namespace
-
-char SMEABI::ID = 0;
-static const char *name = "SME ABI Pass";
-INITIALIZE_PASS(SMEABI, DEBUG_TYPE, name, false, false)
-
-FunctionPass *llvm::createSMEABIPass() { return new SMEABI(); }
-
-//===----------------------------------------------------------------------===//
-// Utility functions
-//===----------------------------------------------------------------------===//
-
-// Utility function to emit a call to __arm_tpidr2_save and clear TPIDR2_EL0.
-void emitTPIDR2Save(Module *M, IRBuilder<> &Builder, const TargetLowering &TLI,
- bool ZT0IsUndef = false) {
- auto &Ctx = M->getContext();
- auto *TPIDR2SaveTy =
- FunctionType::get(Builder.getVoidTy(), {}, /*IsVarArgs=*/false);
- auto Attrs =
- AttributeList().addFnAttribute(Ctx, "aarch64_pstate_sm_compatible");
- RTLIB::Libcall LC = RTLIB::SMEABI_TPIDR2_SAVE;
- FunctionCallee Callee =
- M->getOrInsertFunction(TLI.getLibcallName(LC), TPIDR2SaveTy, Attrs);
- CallInst *Call = Builder.CreateCall(Callee);
-
- // If ZT0 is undefined (i.e. we're at the entry of a "new_zt0" function), mark
- // that on the __arm_tpidr2_save call. This prevents an unnecessary spill of
- // ZT0 that can occur before ZA is enabled.
- if (ZT0IsUndef)
- Call->addFnAttr(Attribute::get(Ctx, "aarch64_zt0_undef"));
-
- Call->setCallingConv(TLI.getLibcallCallingConv(LC));
-
- // A save to TPIDR2 should be followed by clearing TPIDR2_EL0.
- Function *WriteIntr =
- Intrinsic::getOrInsertDeclaration(M, Intrinsic::aarch64_sme_set_tpidr2);
- Builder.CreateCall(WriteIntr->getFunctionType(), WriteIntr,
- Builder.getInt64(0));
-}
-
-/// This function generates code at the beginning and end of a function marked
-/// with either `aarch64_new_za` or `aarch64_new_zt0`.
-/// At the beginning of the function, the following code is generated:
-/// - Commit lazy-save if active [Private-ZA Interface*]
-/// - Enable PSTATE.ZA [Private-ZA Interface]
-/// - Zero ZA [Has New ZA State]
-/// - Zero ZT0 [Has New ZT0 State]
-///
-/// * A function with new ZT0 state will not change ZA, so committing the
-/// lazy-save is not strictly necessary. However, the lazy-save mechanism
-/// may be active on entry to the function, with PSTATE.ZA set to 1. If
-/// the new ZT0 function calls a function that does not share ZT0, we will
-/// need to conditionally SMSTOP ZA before the call, setting PSTATE.ZA to 0.
-/// For this reason, it's easier to always commit the lazy-save at the
-/// beginning of the function regardless of whether it has ZA state.
-///
-/// At the end of the function, PSTATE.ZA is disabled if the function has a
-/// Private-ZA Interface. A function is considered to have a Private-ZA
-/// interface if it does not share ZA or ZT0.
-///
-bool SMEABI::updateNewStateFunctions(Module *M, Function *F,
- IRBuilder<> &Builder, SMEAttrs FnAttrs,
- const TargetLowering &TLI) {
- LLVMContext &Context = F->getContext();
- BasicBlock *OrigBB = &F->getEntryBlock();
- Builder.SetInsertPoint(&OrigBB->front());
-
- // Commit any active lazy-saves if this is a Private-ZA function. If the
- // value read from TPIDR2_EL0 is not null on entry to the function then
- // the lazy-saving scheme is active and we should call __arm_tpidr2_save
- // to commit the lazy save.
- if (FnAttrs.hasPrivateZAInterface()) {
- // Create the new blocks for reading TPIDR2_EL0 & enabling ZA state.
- auto *SaveBB = OrigBB->splitBasicBlockBefore(OrigBB->begin(), "save.za");
- auto *PreludeBB = BasicBlock::Create(Context, "prelude", F, SaveBB);
-
- // Read TPIDR2_EL0 in PreludeBB & branch to SaveBB if not 0.
- Builder.SetInsertPoint(PreludeBB);
- Function *TPIDR2Intr =
- Intrinsic::getOrInsertDeclaration(M, Intrinsic::aarch64_sme_get_tpidr2);
- auto *TPIDR2 = Builder.CreateCall(TPIDR2Intr->getFunctionType(), TPIDR2Intr,
- {}, "tpidr2");
- auto *Cmp = Builder.CreateCmp(ICmpInst::ICMP_NE, TPIDR2,
- Builder.getInt64(0), "cmp");
- Builder.CreateCondBr(Cmp, SaveBB, OrigBB);
-
- // Create a call __arm_tpidr2_save, which commits the lazy save.
- Builder.SetInsertPoint(&SaveBB->back());
- emitTPIDR2Save(M, Builder, TLI, /*ZT0IsUndef=*/FnAttrs.isNewZT0());
-
- // Enable pstate.za at the start of the function.
- Builder.SetInsertPoint(&OrigBB->front());
- Function *EnableZAIntr =
- Intrinsic::getOrInsertDeclaration(M, Intrinsic::aarch64_sme_za_enable);
- Builder.CreateCall(EnableZAIntr->getFunctionType(), EnableZAIntr);
- }
-
- if (FnAttrs.isNewZA()) {
- Function *ZeroIntr =
- Intrinsic::getOrInsertDeclaration(M, Intrinsic::aarch64_sme_zero);
- Builder.CreateCall(ZeroIntr->getFunctionType(), ZeroIntr,
- Builder.getInt32(0xff));
- }
-
- if (FnAttrs.isNewZT0()) {
- Function *ClearZT0Intr =
- Intrinsic::getOrInsertDeclaration(M, Intrinsic::aarch64_sme_zero_zt);
- Builder.CreateCall(ClearZT0Intr->getFunctionType(), ClearZT0Intr,
- {Builder.getInt32(0)});
- }
-
- if (FnAttrs.hasPrivateZAInterface()) {
- // Before returning, disable pstate.za
- for (BasicBlock &BB : *F) {
- Instruction *T = BB.getTerminator();
- if (!T || !isa<ReturnInst>(T))
- continue;
- Builder.SetInsertPoint(T);
- Function *DisableZAIntr = Intrinsic::getOrInsertDeclaration(
- M, Intrinsic::aarch64_sme_za_disable);
- Builder.CreateCall(DisableZAIntr->getFunctionType(), DisableZAIntr);
- }
- }
-
- F->addFnAttr("aarch64_expanded_pstate_za");
- return true;
-}
-
-bool SMEABI::runOnFunction(Function &F) {
- Module *M = F.getParent();
- LLVMContext &Context = F.getContext();
- IRBuilder<> Builder(Context);
-
- if (F.isDeclaration() || F.hasFnAttribute("aarch64_expanded_pstate_za"))
- return false;
-
- const TargetMachine &TM =
- getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
- const TargetLowering &TLI = *TM.getSubtargetImpl(F)->getTargetLowering();
-
- bool Changed = false;
- SMEAttrs FnAttrs(F);
- if (FnAttrs.isNewZA() || FnAttrs.isNewZT0())
- Changed |= updateNewStateFunctions(M, &F, Builder, FnAttrs, TLI);
-
- return Changed;
-}
diff --git a/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll b/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
index 0b8645f66b5f3..d956a231ba922 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=aarch64 -aarch64-streaming-hazard-size=0 -mattr=+sme,+sve -aarch64-new-sme-abi -stop-before=aarch64-machine-sme-abi -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-BEFORE-SMEABI
-; RUN: llc -mtriple=aarch64 -aarch64-streaming-hazard-size=0 -mattr=+sme,+sve -aarch64-new-sme-abi -stop-after=aarch64-machine-sme-abi -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-AFTER-SMEABI
+; RUN: llc -mtriple=aarch64 -aarch64-streaming-hazard-size=0 -mattr=+sme,+sve -stop-before=aarch64-machine-sme-abi -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-BEFORE-SMEABI
+; RUN: llc -mtriple=aarch64 -aarch64-streaming-hazard-size=0 -mattr=+sme,+sve -stop-after=aarch64-machine-sme-abi -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-AFTER-SMEABI
declare void @private_za_callee()
declare void @shared_za_callee() "aarch64_inout_za"
diff --git a/llvm/test/CodeGen/AArch64/sme-abi-save-call-remarks.ll b/llvm/test/CodeGen/AArch64/sme-abi-save-call-remarks.ll
index c3c76e3e803d0..c7e04aaadbc6a 100644
--- a/llvm/test/CodeGen/AArch64/sme-abi-save-call-remarks.ll
+++ b/llvm/test/CodeGen/AArch64/sme-abi-save-call-remarks.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 -mattr=+sme2 --aarch64-new-sme-abi=false --pass-remarks-analysis=sme -o /dev/null < %s 2>&1 | FileCheck %s --check-prefix=CHECK-SDAG
; RUN: llc -mtriple=aarch64 -mattr=+sme2 --pass-remarks-analysis=sme -o /dev/null < %s 2>&1 | FileCheck %s
declare void @private_za_callee()
@@ -13,8 +12,6 @@ declare void @shared_za_zt0_callee() "aarch64_inout_za" "aarch64_inout_zt0"
; Note: These remarks are more useful with source debug info (which gives line numbers for `<unknown>:0:0`).
define void @test_lazy_save_1_callee() nounwind "aarch64_inout_za" {
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_1_callee' to 'private_za_callee' sets up a lazy save for ZA
-
; CHECK: remark: <unknown>:0:0: lazy save of ZA emitted in 'test_lazy_save_1_callee'
; CHECK-NEXT: remark: <unknown>:0:0: call to 'private_za_callee' requires ZA save
call void @private_za_callee()
@@ -22,9 +19,6 @@ define void @test_lazy_save_1_callee() nounwind "aarch64_inout_za" {
}
define void @test_lazy_save_2_callees() nounwind "aarch64_inout_za" {
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_2_callees' to 'private_za_callee' sets up a lazy save for ZA
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_2_callees' to 'private_za_callee' sets up a lazy save for ZA
-
; CHECK: remark: <unknown>:0:0: lazy save of ZA emitted in 'test_lazy_save_2_callees'
; CHECK-NEXT: remark: <unknown>:0:0: call to 'private_za_callee' requires ZA save
call void @private_za_callee()
@@ -33,8 +27,6 @@ define void @test_lazy_save_2_callees() nounwind "aarch64_inout_za" {
}
define float @test_lazy_save_expanded_intrinsic(float %a) nounwind "aarch64_inout_za" {
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_expanded_intrinsic' to 'cosf' sets up a lazy save for ZA
-
; CHECK: remark: <unknown>:0:0: lazy save of ZA emitted in 'test_lazy_save_expanded_intrinsic'
; CHECK-NEXT: remark: <unknown>:0:0: call to 'cosf' requires ZA save
%res = call float @llvm.cos.f32(float %a)
@@ -42,10 +34,6 @@ define float @test_lazy_save_expanded_intrinsic(float %a) nounwind "aarch64_inou
}
define void @test_lazy_save_multiple_paths(i1 %a) "aarch64_inout_za" {
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_multiple_paths' to 'private_za_callee_a' sets up a lazy save for ZA
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_multiple_paths' to 'private_za_callee_b' sets up a lazy save for ZA
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_multiple_paths' to 'private_za_callee_c' sets up a lazy save for ZA
-
; CHECK: remark: <unknown>:0:0: lazy save of ZA emitted in 'test_lazy_save_multiple_paths'
; CHECK-NEXT: remark: <unknown>:0:0: call to 'private_za_callee_b' requires ZA save
; CHECK-NEXT: remark: <unknown>:0:0: call to 'private_za_callee_a' requires ZA save
@@ -67,8 +55,6 @@ if.end:
define void @test_lazy_save_with_zt0() "aarch64_inout_za" "aarch64_inout_zt0"
{
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_with_zt0' to 'private_za_callee' sets up a lazy save for ZA
-
; CHECK: remark: <unknown>:0:0: spill of ZT0 emitted in 'test_lazy_save_with_zt0'
; CHECK-NEXT: remark: <unknown>:0:0: call to 'shared_za_callee' requires ZT0 save
; CHECK-NEXT: remark: <unknown>:0:0: lazy save of ZA emitted in 'test_lazy_save_with_zt0'
@@ -80,8 +66,6 @@ define void @test_lazy_save_with_zt0() "aarch64_inout_za" "aarch64_inout_zt0"
define void @test_lazy_save_with_zt0_reload() "aarch64_inout_za" "aarch64_inout_zt0"
{
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_with_zt0_reload' to 'private_za_callee' sets up a lazy save for ZA
-
; CHECK: remark: <unknown>:0:0: spill of ZT0 emitted in 'test_lazy_save_with_zt0_reload'
; CHECK-NEXT: remark: <unknown>:0:0: call to 'shared_za_callee' requires ZT0 save
; CHECK-NEXT: remark: <unknown>:0:0: spill of ZT0 emitted in 'test_lazy_save_with_zt0_reload'
@@ -94,8 +78,6 @@ define void @test_lazy_save_with_zt0_reload() "aarch64_inout_za" "aarch64_inout_
}
define void @test_za_merge_paths(i1 %a) "aarch64_za_state_agnostic" {
-;; Note: The old lowering does not emit any remarks for agnostic ZA saves.
-
; CHECK: remark: <unknown>:0:0: full save of ZA emitted in 'test_za_merge_paths'
; CHECK-NEXT: remark: <unknown>:0:0: call to 'private_za_callee_b' requires ZA save
; CHECK-NEXT: remark: <unknown>:0:0: call to 'private_za_callee_a' requires ZA save
@@ -111,7 +93,7 @@ if.end:
br label %exit
exit:
- ; The new lowering won't report this call as the save is already needed due to
+ ; The remarks won't report this call as the save is already needed due to
; the call to `private_za_callee_*()` calls on both paths to this BB.
call void @private_za_callee_c()
@@ -119,8 +101,6 @@ exit:
}
define void @test_lazy_save_function_ptr_callee(ptr %private_za_callee) nounwind "aarch64_inout_za" {
-; CHECK-SDAG: remark: <unknown>:0:0: call from 'test_lazy_save_function_ptr_callee' to 'unknown callee' sets up a lazy save for ZA
-
; CHECK: remark: <unknown>:0:0: lazy save of ZA emitted in 'test_lazy_save_function_ptr_callee'
; CHECK-NEXT: remark: <unknown>:0:0: call requires ZA save
call void %private_za_callee()
diff --git a/llvm/test/CodeGen/AArch64/sme-agnostic-za.ll b/llvm/test/CodeGen/AArch64/sme-agnostic-za.ll
index 7a89879625632..e9d7971560474 100644
--- a/llvm/test/CodeGen/AArch64/sme-agnostic-za.ll
+++ b/llvm/test/CodeGen/AArch64/sme-agnostic-za.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mattr=+sme2 < %s -aarch64-new-sme-abi=false | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-SDAG
-; RUN: llc -mattr=+sme2 < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK
+; RUN: llc -mattr=+sme2 < %s | FileCheck %s
target triple = "aarch64"
@@ -10,10 +9,10 @@ declare i64 @agnostic_decl(i64) "aarch64_za_state_agnostic"
; No calls. Test that no buffer is allocated.
define i64 @agnostic_caller_no_callees(ptr %ptr) nounwind "aarch64_za_state_agnostic" {
-; CHECK-COMMON-LABEL: agnostic_caller_no_callees:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: ldr x0, [x0]
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: agnostic_caller_no_callees:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x0, [x0]
+; CHECK-NEXT: ret
%v = load i64, ptr %ptr
ret i64 %v
}
@@ -24,34 +23,6 @@ define i64 @agnostic_caller_no_callees(ptr %ptr) nounwind "aarch64_za_state_agno
; inserted for calls to non-agnostic functions and that the arg/result registers are
; preserved by the register allocator.
define i64 @agnostic_caller_private_za_callee(i64 %v) nounwind "aarch64_za_state_agnostic" {
-; CHECK-SDAG-LABEL: agnostic_caller_private_za_callee:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: mov x8, x0
-; CHECK-SDAG-NEXT: bl __arm_sme_state_size
-; CHECK-SDAG-NEXT: sub sp, sp, x0
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: mov x0, x8
-; CHECK-SDAG-NEXT: bl private_za_decl
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: bl private_za_decl
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: agnostic_caller_private_za_callee:
; CHECK: // %bb.0:
@@ -84,12 +55,12 @@ define i64 @agnostic_caller_private_za_callee(i64 %v) nounwind "aarch64_za_state
;
; Should not result in save/restore code.
define i64 @agnostic_caller_agnostic_callee(i64 %v) nounwind "aarch64_za_state_agnostic" {
-; CHECK-COMMON-LABEL: agnostic_caller_agnostic_callee:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: bl agnostic_decl
-; CHECK-COMMON-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: agnostic_caller_agnostic_callee:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: bl agnostic_decl
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%res = call i64 @agnostic_decl(i64 %v)
ret i64 %res
}
@@ -98,58 +69,18 @@ define i64 @agnostic_caller_agnostic_callee(i64 %v) nounwind "aarch64_za_state_a
;
; Should not result in lazy-save or save of ZT0
define i64 @shared_caller_agnostic_callee(i64 %v) nounwind "aarch64_inout_za" "aarch64_inout_zt0" {
-; CHECK-COMMON-LABEL: shared_caller_agnostic_callee:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: bl agnostic_decl
-; CHECK-COMMON-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: shared_caller_agnostic_callee:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: bl agnostic_decl
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%res = call i64 @agnostic_decl(i64 %v)
ret i64 %res
}
; agnostic-ZA + streaming -> private-ZA + non-streaming
define i64 @streaming_agnostic_caller_nonstreaming_private_za_callee(i64 %v) nounwind "aarch64_za_state_agnostic" "aarch64_pstate_sm_enabled" {
-; CHECK-SDAG-LABEL: streaming_agnostic_caller_nonstreaming_private_za_callee:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp d15, d14, [sp, #-96]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x8, x0
-; CHECK-SDAG-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #64] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: add x29, sp, #64
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: bl __arm_sme_state_size
-; CHECK-SDAG-NEXT: sub sp, sp, x0
-; CHECK-SDAG-NEXT: mov x20, sp
-; CHECK-SDAG-NEXT: mov x0, x20
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: smstop sm
-; CHECK-SDAG-NEXT: mov x0, x8
-; CHECK-SDAG-NEXT: bl private_za_decl
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: smstart sm
-; CHECK-SDAG-NEXT: mov x0, x20
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x20
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: smstop sm
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: bl private_za_decl
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: smstart sm
-; CHECK-SDAG-NEXT: mov x0, x20
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: sub sp, x29, #64
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp, #64] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d15, d14, [sp], #96 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: streaming_agnostic_caller_nonstreaming_private_za_callee:
; CHECK: // %bb.0:
@@ -190,59 +121,6 @@ define i64 @streaming_agnostic_caller_nonstreaming_private_za_callee(i64 %v) nou
; agnostic-ZA + streaming-compatible -> private-ZA + non-streaming
define i64 @streaming_compatible_agnostic_caller_nonstreaming_private_za_callee(i64 %v) nounwind "aarch64_za_state_agnostic" "aarch64_pstate_sm_compatible" {
-; CHECK-SDAG-LABEL: streaming_compatible_agnostic_caller_nonstreaming_private_za_callee:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp d15, d14, [sp, #-96]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x8, x0
-; CHECK-SDAG-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #64] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: add x29, sp, #64
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mrs x20, SVCR
-; CHECK-SDAG-NEXT: bl __arm_sme_state_size
-; CHECK-SDAG-NEXT: sub sp, sp, x0
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: tbz w20, #0, .LBB5_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: smstop sm
-; CHECK-SDAG-NEXT: .LBB5_2:
-; CHECK-SDAG-NEXT: mov x0, x8
-; CHECK-SDAG-NEXT: bl private_za_decl
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: tbz w20, #0, .LBB5_4
-; CHECK-SDAG-NEXT: // %bb.3:
-; CHECK-SDAG-NEXT: smstart sm
-; CHECK-SDAG-NEXT: .LBB5_4:
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: tbz w20, #0, .LBB5_6
-; CHECK-SDAG-NEXT: // %bb.5:
-; CHECK-SDAG-NEXT: smstop sm
-; CHECK-SDAG-NEXT: .LBB5_6:
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: bl private_za_decl
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: tbz w20, #0, .LBB5_8
-; CHECK-SDAG-NEXT: // %bb.7:
-; CHECK-SDAG-NEXT: smstart sm
-; CHECK-SDAG-NEXT: .LBB5_8:
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: sub sp, x29, #64
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp, #64] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d15, d14, [sp], #96 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: streaming_compatible_agnostic_caller_nonstreaming_private_za_callee:
; CHECK: // %bb.0:
@@ -295,30 +173,6 @@ declare i64 @many_args_private_za_callee(
; stack pointer before the call -- in this test the call to __arm_sme_save
; should occur _before_ the stack decrement.
define i64 @test_many_callee_arguments(
-; CHECK-SDAG-LABEL: test_many_callee_arguments:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: mov x8, x0
-; CHECK-SDAG-NEXT: bl __arm_sme_state_size
-; CHECK-SDAG-NEXT: sub sp, sp, x0
-; CHECK-SDAG-NEXT: ldp x9, x10, [x29, #32]
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: stp x9, x10, [sp, #-16]!
-; CHECK-SDAG-NEXT: mov x0, x8
-; CHECK-SDAG-NEXT: bl many_args_private_za_callee
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: test_many_callee_arguments:
; CHECK: // %bb.0:
@@ -352,33 +206,33 @@ define i64 @test_many_callee_arguments(
}
define void @agnostic_za_buffer_alloc_with_stack_probes() nounwind "aarch64_za_state_agnostic" "probe-stack"="inline-asm" "stack-probe-size"="65536"{
-; CHECK-COMMON-LABEL: agnostic_za_buffer_alloc_with_stack_probes:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: bl __arm_sme_state_size
-; CHECK-COMMON-NEXT: mov x8, sp
-; CHECK-COMMON-NEXT: sub x19, x8, x0
-; CHECK-COMMON-NEXT: .LBB7_1: // =>This Inner Loop Header: Depth=1
-; CHECK-COMMON-NEXT: sub sp, sp, #16, lsl #12 // =65536
-; CHECK-COMMON-NEXT: cmp sp, x19
-; CHECK-COMMON-NEXT: b.le .LBB7_3
-; CHECK-COMMON-NEXT: // %bb.2: // in Loop: Header=BB7_1 Depth=1
-; CHECK-COMMON-NEXT: ldr xzr, [sp]
-; CHECK-COMMON-NEXT: b .LBB7_1
-; CHECK-COMMON-NEXT: .LBB7_3:
-; CHECK-COMMON-NEXT: mov sp, x19
-; CHECK-COMMON-NEXT: ldr xzr, [sp]
-; CHECK-COMMON-NEXT: mov x0, x19
-; CHECK-COMMON-NEXT: bl __arm_sme_save
-; CHECK-COMMON-NEXT: bl private_za
-; CHECK-COMMON-NEXT: mov x0, x19
-; CHECK-COMMON-NEXT: bl __arm_sme_restore
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: agnostic_za_buffer_alloc_with_stack_probes:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: bl __arm_sme_state_size
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: sub x19, x8, x0
+; CHECK-NEXT: .LBB7_1: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536
+; CHECK-NEXT: cmp sp, x19
+; CHECK-NEXT: b.le .LBB7_3
+; CHECK-NEXT: // %bb.2: // in Loop: Header=BB7_1 Depth=1
+; CHECK-NEXT: ldr xzr, [sp]
+; CHECK-NEXT: b .LBB7_1
+; CHECK-NEXT: .LBB7_3:
+; CHECK-NEXT: mov sp, x19
+; CHECK-NEXT: ldr xzr, [sp]
+; CHECK-NEXT: mov x0, x19
+; CHECK-NEXT: bl __arm_sme_save
+; CHECK-NEXT: bl private_za
+; CHECK-NEXT: mov x0, x19
+; CHECK-NEXT: bl __arm_sme_restore
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ret
call void @private_za()
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/sme-dynamic-tls.ll b/llvm/test/CodeGen/AArch64/sme-dynamic-tls.ll
index 87a63fed0546c..c5115d0ff0a60 100644
--- a/llvm/test/CodeGen/AArch64/sme-dynamic-tls.ll
+++ b/llvm/test/CodeGen/AArch64/sme-dynamic-tls.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sme -aarch64-new-sme-abi -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sme -relocation-model=pic < %s | FileCheck %s
@x = external thread_local local_unnamed_addr global i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll b/llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
index 188059baa6675..bbdda5fa8f484 100644
--- a/llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
+++ b/llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 -aarch64-streaming-hazard-size=0 -mattr=+sve -mattr=+sme -aarch64-new-sme-abi=false < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-SDAG
-; RUN: llc -mtriple=aarch64 -aarch64-streaming-hazard-size=0 -mattr=+sve -mattr=+sme < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK
+; RUN: llc -mtriple=aarch64 -aarch64-streaming-hazard-size=0 -mattr=+sve -mattr=+sme < %s | FileCheck %s
declare void @private_za_callee()
declare void @shared_za_callee() "aarch64_inout_za"
@@ -10,74 +9,38 @@ declare float @llvm.cos.f32(float)
; Test lazy-save mechanism for a single callee.
define void @test_lazy_save_1_callee() nounwind "aarch64_inout_za" {
-; CHECK-COMMON-LABEL: test_lazy_save_1_callee:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: rdsvl x8, #1
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: msub x9, x8, x8, x9
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: sub x10, x29, #16
-; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x10
-; CHECK-COMMON-NEXT: bl private_za_callee
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-COMMON-NEXT: sub x0, x29, #16
-; CHECK-COMMON-NEXT: cbnz x8, .LBB0_2
-; CHECK-COMMON-NEXT: // %bb.1:
-; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
-; CHECK-COMMON-NEXT: .LBB0_2:
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: test_lazy_save_1_callee:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: rdsvl x8, #1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: msub x9, x8, x8, x9
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: sub x10, x29, #16
+; CHECK-NEXT: stp x9, x8, [x29, #-16]
+; CHECK-NEXT: msr TPIDR2_EL0, x10
+; CHECK-NEXT: bl private_za_callee
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: mrs x8, TPIDR2_EL0
+; CHECK-NEXT: sub x0, x29, #16
+; CHECK-NEXT: cbnz x8, .LBB0_2
+; CHECK-NEXT: // %bb.1:
+; CHECK-NEXT: bl __arm_tpidr2_restore
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: msr TPIDR2_EL0, xzr
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ret
call void @private_za_callee()
ret void
}
; Test lazy-save mechanism for multiple callees.
define void @test_lazy_save_2_callees() nounwind "aarch64_inout_za" {
-; CHECK-SDAG-LABEL: test_lazy_save_2_callees:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: sub x20, x29, #16
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB1_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB1_2:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB1_4
-; CHECK-SDAG-NEXT: // %bb.3:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB1_4:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: test_lazy_save_2_callees:
; CHECK: // %bb.0:
@@ -113,81 +76,38 @@ define void @test_lazy_save_2_callees() nounwind "aarch64_inout_za" {
; Test a call of an intrinsic that gets expanded to a library call.
define float @test_lazy_save_expanded_intrinsic(float %a) nounwind "aarch64_inout_za" {
-; CHECK-COMMON-LABEL: test_lazy_save_expanded_intrinsic:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: rdsvl x8, #1
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: msub x9, x8, x8, x9
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: sub x10, x29, #16
-; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x10
-; CHECK-COMMON-NEXT: bl cosf
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-COMMON-NEXT: sub x0, x29, #16
-; CHECK-COMMON-NEXT: cbnz x8, .LBB2_2
-; CHECK-COMMON-NEXT: // %bb.1:
-; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
-; CHECK-COMMON-NEXT: .LBB2_2:
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: test_lazy_save_expanded_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: rdsvl x8, #1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: msub x9, x8, x8, x9
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: sub x10, x29, #16
+; CHECK-NEXT: stp x9, x8, [x29, #-16]
+; CHECK-NEXT: msr TPIDR2_EL0, x10
+; CHECK-NEXT: bl cosf
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: mrs x8, TPIDR2_EL0
+; CHECK-NEXT: sub x0, x29, #16
+; CHECK-NEXT: cbnz x8, .LBB2_2
+; CHECK-NEXT: // %bb.1:
+; CHECK-NEXT: bl __arm_tpidr2_restore
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: msr TPIDR2_EL0, xzr
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ret
%res = call float @llvm.cos.f32(float %a)
ret float %res
}
; Test a combination of streaming-compatible -> normal call with lazy-save.
define void @test_lazy_save_and_conditional_smstart() nounwind "aarch64_inout_za" "aarch64_pstate_sm_compatible" {
-; CHECK-SDAG-LABEL: test_lazy_save_and_conditional_smstart:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp d15, d14, [sp, #-96]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #64] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: add x29, sp, #64
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mrs x20, SVCR
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: sub x10, x29, #80
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-80]
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x10
-; CHECK-SDAG-NEXT: tbz w20, #0, .LBB3_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: smstop sm
-; CHECK-SDAG-NEXT: .LBB3_2:
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: tbz w20, #0, .LBB3_4
-; CHECK-SDAG-NEXT: // %bb.3:
-; CHECK-SDAG-NEXT: smstart sm
-; CHECK-SDAG-NEXT: .LBB3_4:
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #80
-; CHECK-SDAG-NEXT: cbnz x8, .LBB3_6
-; CHECK-SDAG-NEXT: // %bb.5:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB3_6:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: sub sp, x29, #64
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp, #64] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d15, d14, [sp], #96 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: test_lazy_save_and_conditional_smstart:
; CHECK: // %bb.0:
@@ -240,58 +160,6 @@ define void @test_lazy_save_and_conditional_smstart() nounwind "aarch64_inout_za
; restore from it (since ZA is off on return). We could improve this case
; by turning ZA off before the final private ZA call.
define void @test_lazy_save_mixed_shared_and_private_callees() "aarch64_new_za"
-; CHECK-SDAG-LABEL: test_lazy_save_mixed_shared_and_private_callees:
-; CHECK-SDAG: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 32
-; CHECK-SDAG-NEXT: .cfi_offset w19, -8
-; CHECK-SDAG-NEXT: .cfi_offset w20, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -24
-; CHECK-SDAG-NEXT: .cfi_offset w29, -32
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB4_2
-; CHECK-SDAG-NEXT: // %bb.1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .LBB4_2:
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: sub x20, x29, #16
-; CHECK-SDAG-NEXT: zero {za}
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB4_4
-; CHECK-SDAG-NEXT: // %bb.3:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB4_4:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: bl shared_za_callee
-; CHECK-SDAG-NEXT: bl preserves_za_callee
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB4_6
-; CHECK-SDAG-NEXT: // %bb.5:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB4_6:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: test_lazy_save_mixed_shared_and_private_callees:
; CHECK: // %bb.0:
@@ -347,89 +215,6 @@ define void @test_lazy_save_mixed_shared_and_private_callees() "aarch64_new_za"
}
define void @test_many_back2back_private_za_calls() "aarch64_inout_za" {
-; CHECK-SDAG-LABEL: test_many_back2back_private_za_calls:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 32
-; CHECK-SDAG-NEXT: .cfi_offset w19, -8
-; CHECK-SDAG-NEXT: .cfi_offset w20, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -24
-; CHECK-SDAG-NEXT: .cfi_offset w29, -32
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: bl shared_za_callee
-; CHECK-SDAG-NEXT: sub x20, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB5_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB5_2:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB5_4
-; CHECK-SDAG-NEXT: // %bb.3:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB5_4:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB5_6
-; CHECK-SDAG-NEXT: // %bb.5:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB5_6:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB5_8
-; CHECK-SDAG-NEXT: // %bb.7:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB5_8:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB5_10
-; CHECK-SDAG-NEXT: // %bb.9:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB5_10:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_callee
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB5_12
-; CHECK-SDAG-NEXT: // %bb.11:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB5_12:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: bl shared_za_callee
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: test_many_back2back_private_za_calls:
; CHECK: // %bb.0:
@@ -480,34 +265,34 @@ define void @test_many_back2back_private_za_calls() "aarch64_inout_za" {
}
define void @test_shared_private_shared() nounwind "aarch64_inout_za" {
-; CHECK-COMMON-LABEL: test_shared_private_shared:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: rdsvl x8, #1
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: msub x9, x8, x8, x9
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-COMMON-NEXT: bl shared_za_callee
-; CHECK-COMMON-NEXT: sub x8, x29, #16
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x8
-; CHECK-COMMON-NEXT: bl private_za_callee
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-COMMON-NEXT: sub x0, x29, #16
-; CHECK-COMMON-NEXT: cbnz x8, .LBB6_2
-; CHECK-COMMON-NEXT: // %bb.1:
-; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
-; CHECK-COMMON-NEXT: .LBB6_2:
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-COMMON-NEXT: bl shared_za_callee
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: test_shared_private_shared:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: rdsvl x8, #1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: msub x9, x8, x8, x9
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: stp x9, x8, [x29, #-16]
+; CHECK-NEXT: bl shared_za_callee
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
+; CHECK-NEXT: bl private_za_callee
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: mrs x8, TPIDR2_EL0
+; CHECK-NEXT: sub x0, x29, #16
+; CHECK-NEXT: cbnz x8, .LBB6_2
+; CHECK-NEXT: // %bb.1:
+; CHECK-NEXT: bl __arm_tpidr2_restore
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: msr TPIDR2_EL0, xzr
+; CHECK-NEXT: bl shared_za_callee
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ret
call void @shared_za_callee()
call void @private_za_callee()
call void @shared_za_callee()
@@ -515,12 +300,12 @@ define void @test_shared_private_shared() nounwind "aarch64_inout_za" {
}
define void @test_only_shared_za() nounwind "aarch64_inout_za" {
-; CHECK-COMMON-LABEL: test_only_shared_za:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: bl shared_za_callee
-; CHECK-COMMON-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: test_only_shared_za:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: bl shared_za_callee
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call void @shared_za_callee()
ret void
}
@@ -529,36 +314,36 @@ declare i64 @shared_za_callee_i64(i64) "aarch64_inout_za"
declare i64 @private_za_callee_i64(i64)
define i64 @test_shared_private_shared_i64(i64 %x) nounwind "aarch64_inout_za" {
-; CHECK-COMMON-LABEL: test_shared_private_shared_i64:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: rdsvl x8, #1
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: msub x9, x8, x8, x9
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-COMMON-NEXT: bl shared_za_callee_i64
-; CHECK-COMMON-NEXT: sub x8, x29, #16
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x8
-; CHECK-COMMON-NEXT: bl private_za_callee_i64
-; CHECK-COMMON-NEXT: mov x1, x0
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-COMMON-NEXT: sub x0, x29, #16
-; CHECK-COMMON-NEXT: cbnz x8, .LBB8_2
-; CHECK-COMMON-NEXT: // %bb.1:
-; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
-; CHECK-COMMON-NEXT: .LBB8_2:
-; CHECK-COMMON-NEXT: mov x0, x1
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-COMMON-NEXT: bl shared_za_callee_i64
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: test_shared_private_shared_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: rdsvl x8, #1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: msub x9, x8, x8, x9
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: stp x9, x8, [x29, #-16]
+; CHECK-NEXT: bl shared_za_callee_i64
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
+; CHECK-NEXT: bl private_za_callee_i64
+; CHECK-NEXT: mov x1, x0
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: mrs x8, TPIDR2_EL0
+; CHECK-NEXT: sub x0, x29, #16
+; CHECK-NEXT: cbnz x8, .LBB8_2
+; CHECK-NEXT: // %bb.1:
+; CHECK-NEXT: bl __arm_tpidr2_restore
+; CHECK-NEXT: .LBB8_2:
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: msr TPIDR2_EL0, xzr
+; CHECK-NEXT: bl shared_za_callee_i64
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ret
%a = call i64 @shared_za_callee_i64(i64 %x)
%b = call i64 @private_za_callee_i64(i64 %a)
%c = call i64 @shared_za_callee_i64(i64 %b)
@@ -572,37 +357,6 @@ declare i64 @many_args_private_za_callee(
; stack pointer before the call -- in this test the lazy save should be setup
; before the stack decrement.
define i64 @test_many_callee_arguments(
-; CHECK-SDAG-LABEL: test_many_callee_arguments:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: mov x8, sp
-; CHECK-SDAG-NEXT: rdsvl x9, #1
-; CHECK-SDAG-NEXT: msub x8, x9, x9, x8
-; CHECK-SDAG-NEXT: mov sp, x8
-; CHECK-SDAG-NEXT: ldp x10, x11, [x29, #32]
-; CHECK-SDAG-NEXT: sub x12, x29, #16
-; CHECK-SDAG-NEXT: stp x8, x9, [x29, #-16]
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x12
-; CHECK-SDAG-NEXT: stp x10, x11, [sp, #-16]!
-; CHECK-SDAG-NEXT: bl many_args_private_za_callee
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB9_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB9_2:
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
;
; CHECK-LABEL: test_many_callee_arguments:
; CHECK: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/sme-lazy-save-windows.ll b/llvm/test/CodeGen/AArch64/sme-lazy-save-windows.ll
index 648cba57b95cf..6e2d2c0269757 100644
--- a/llvm/test/CodeGen/AArch64/sme-lazy-save-windows.ll
+++ b/llvm/test/CodeGen/AArch64/sme-lazy-save-windows.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-windows-msvc -aarch64-streaming-hazard-size=0 -mattr=+sve,+sme < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-windows-msvc -aarch64-streaming-hazard-size=0 -mattr=+sve,+sme -aarch64-new-sme-abi < %s | FileCheck %s
declare void @private_za_callee()
declare void @shared_za_callee() "aarch64_inout_za"
diff --git a/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir b/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
index 9f33c0614cee0..9a2811bc1abef 100644
--- a/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
+++ b/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+sme -run-pass=aarch64-machine-sme-abi -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+sme -aarch64-new-sme-abi %s -o - | FileCheck %s --check-prefix=CHECK-ASM
+# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+sme %s -o - | FileCheck %s --check-prefix=CHECK-ASM
# This tests the unfortunate case the status flags ($nzcv) are live at the point
# we want to restore ZA. Currently, this is handled by saving them to a scratch
diff --git a/llvm/test/CodeGen/AArch64/sme-new-za-function.ll b/llvm/test/CodeGen/AArch64/sme-new-za-function.ll
index 6995cfae8e459..bc32dc26228ea 100644
--- a/llvm/test/CodeGen/AArch64/sme-new-za-function.ll
+++ b/llvm/test/CodeGen/AArch64/sme-new-za-function.ll
@@ -1,32 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs -aarch64-new-sme-abi=false < %s | FileCheck %s --check-prefix=CHECK-SDAG
; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
declare void @shared_za_callee() "aarch64_inout_za"
define void @private_za() "aarch64_new_za" {
-; CHECK-SDAG-LABEL: private_za:
-; CHECK-SDAG: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB0_2
-; CHECK-SDAG-NEXT: b .LBB0_1
-; CHECK-SDAG-NEXT: .LBB0_1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: mov x8, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: b .LBB0_2
-; CHECK-SDAG-NEXT: .LBB0_2:
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: zero {za}
-; CHECK-SDAG-NEXT: bl shared_za_callee
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: private_za:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
@@ -52,48 +29,6 @@ define void @private_za() "aarch64_new_za" {
; Note: This test must run at -O0 as otherwise the multiple exits are optimized out.
define i32 @private_za_multiple_exit(i32 %a, i32 %b, i64 %cond) "aarch64_new_za" {
-; CHECK-SDAG-LABEL: private_za_multiple_exit:
-; CHECK-SDAG: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: sub sp, sp, #32
-; CHECK-SDAG-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 32
-; CHECK-SDAG-NEXT: .cfi_offset w30, -16
-; CHECK-SDAG-NEXT: str x2, [sp] // 8-byte Spill
-; CHECK-SDAG-NEXT: str w1, [sp, #8] // 4-byte Spill
-; CHECK-SDAG-NEXT: str w0, [sp, #12] // 4-byte Spill
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB1_2
-; CHECK-SDAG-NEXT: b .LBB1_1
-; CHECK-SDAG-NEXT: .LBB1_1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: mov x8, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: b .LBB1_2
-; CHECK-SDAG-NEXT: .LBB1_2: // %entry
-; CHECK-SDAG-NEXT: ldr x8, [sp] // 8-byte Reload
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: zero {za}
-; CHECK-SDAG-NEXT: subs x8, x8, #1
-; CHECK-SDAG-NEXT: b.ne .LBB1_4
-; CHECK-SDAG-NEXT: b .LBB1_3
-; CHECK-SDAG-NEXT: .LBB1_3: // %if.else
-; CHECK-SDAG-NEXT: ldr w8, [sp, #12] // 4-byte Reload
-; CHECK-SDAG-NEXT: ldr w9, [sp, #8] // 4-byte Reload
-; CHECK-SDAG-NEXT: add w0, w8, w9
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: add sp, sp, #32
-; CHECK-SDAG-NEXT: ret
-; CHECK-SDAG-NEXT: .LBB1_4: // %if.end
-; CHECK-SDAG-NEXT: ldr w8, [sp, #12] // 4-byte Reload
-; CHECK-SDAG-NEXT: ldr w9, [sp, #8] // 4-byte Reload
-; CHECK-SDAG-NEXT: subs w0, w8, w9
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: add sp, sp, #32
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: private_za_multiple_exit:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16
@@ -130,32 +65,6 @@ if.end:
; In simple cases like this we should omit all ZA setup.
define i32 @private_za_trivially_does_not_use_za(i32 %x) "aarch64_new_za" {
-; CHECK-SDAG-LABEL: private_za_trivially_does_not_use_za:
-; CHECK-SDAG: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: sub sp, sp, #32
-; CHECK-SDAG-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 32
-; CHECK-SDAG-NEXT: .cfi_offset w30, -16
-; CHECK-SDAG-NEXT: str w0, [sp, #12] // 4-byte Spill
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB2_2
-; CHECK-SDAG-NEXT: b .LBB2_1
-; CHECK-SDAG-NEXT: .LBB2_1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: mov x8, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: b .LBB2_2
-; CHECK-SDAG-NEXT: .LBB2_2:
-; CHECK-SDAG-NEXT: ldr w8, [sp, #12] // 4-byte Reload
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: zero {za}
-; CHECK-SDAG-NEXT: add w0, w8, w8
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: add sp, sp, #32
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: private_za_trivially_does_not_use_za:
; CHECK: // %bb.0:
; CHECK-NEXT: add w0, w0, w0
diff --git a/llvm/test/CodeGen/AArch64/sme-new-zt0-function.ll b/llvm/test/CodeGen/AArch64/sme-new-zt0-function.ll
deleted file mode 100644
index 94968ab4fd9ac..0000000000000
--- a/llvm/test/CodeGen/AArch64/sme-new-zt0-function.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: opt -S -mtriple=aarch64-linux-gnu -aarch64-sme-abi %s | FileCheck %s
-
-declare void @callee();
-
-define void @private_za() "aarch64_new_zt0" {
- call void @callee()
- ret void
-}
-
-; CHECK: call aarch64_sme_preservemost_from_x0 void @__arm_tpidr2_save() #[[TPIDR2_SAVE_CALL_ATTR:[0-9]+]]
-; CHECK: declare void @__arm_tpidr2_save() #[[TPIDR2_SAVE_DECL_ATTR:[0-9]+]]
-
-; CHECK: attributes #[[TPIDR2_SAVE_DECL_ATTR]] = { "aarch64_pstate_sm_compatible" }
-; CHECK: attributes #[[TPIDR2_SAVE_CALL_ATTR]] = { "aarch64_zt0_undef" }
diff --git a/llvm/test/CodeGen/AArch64/sme-peephole-opts.ll b/llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
index ea1341186ddfa..bdfddad32ff3a 100644
--- a/llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
+++ b/llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-new-sme-abi -aarch64-streaming-hazard-size=0 -mattr=+sve,+sme2 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-streaming-hazard-size=0 -mattr=+sve,+sme2 < %s | FileCheck %s
declare void @callee()
declare void @callee_sm() "aarch64_pstate_sm_enabled"
diff --git a/llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll b/llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
index c8915aac56084..26f289e9699b3 100644
--- a/llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
+++ b/llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs -aarch64-new-sme-abi < %s | FileCheck %s --check-prefix=CHECK-NEWLOWERING
declare void @private_za_callee()
@@ -30,31 +29,6 @@ define void @disable_tailcallopt() "aarch64_inout_za" nounwind {
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
-;
-; CHECK-NEWLOWERING-LABEL: disable_tailcallopt:
-; CHECK-NEWLOWERING: // %bb.0:
-; CHECK-NEWLOWERING-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEWLOWERING-NEXT: mov x29, sp
-; CHECK-NEWLOWERING-NEXT: sub sp, sp, #16
-; CHECK-NEWLOWERING-NEXT: rdsvl x8, #1
-; CHECK-NEWLOWERING-NEXT: mov x9, sp
-; CHECK-NEWLOWERING-NEXT: msub x9, x8, x8, x9
-; CHECK-NEWLOWERING-NEXT: mov sp, x9
-; CHECK-NEWLOWERING-NEXT: sub x10, x29, #16
-; CHECK-NEWLOWERING-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-NEWLOWERING-NEXT: msr TPIDR2_EL0, x10
-; CHECK-NEWLOWERING-NEXT: bl private_za_callee
-; CHECK-NEWLOWERING-NEXT: smstart za
-; CHECK-NEWLOWERING-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-NEWLOWERING-NEXT: sub x0, x29, #16
-; CHECK-NEWLOWERING-NEXT: cbnz x8, .LBB0_2
-; CHECK-NEWLOWERING-NEXT: // %bb.1:
-; CHECK-NEWLOWERING-NEXT: bl __arm_tpidr2_restore
-; CHECK-NEWLOWERING-NEXT: .LBB0_2:
-; CHECK-NEWLOWERING-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-NEWLOWERING-NEXT: mov sp, x29
-; CHECK-NEWLOWERING-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
-; CHECK-NEWLOWERING-NEXT: ret
tail call void @private_za_callee()
ret void
}
@@ -85,31 +59,6 @@ define fp128 @f128_call_za(fp128 %a, fp128 %b) "aarch64_inout_za" nounwind {
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
-;
-; CHECK-NEWLOWERING-LABEL: f128_call_za:
-; CHECK-NEWLOWERING: // %bb.0:
-; CHECK-NEWLOWERING-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEWLOWERING-NEXT: mov x29, sp
-; CHECK-NEWLOWERING-NEXT: sub sp, sp, #16
-; CHECK-NEWLOWERING-NEXT: rdsvl x8, #1
-; CHECK-NEWLOWERING-NEXT: mov x9, sp
-; CHECK-NEWLOWERING-NEXT: msub x9, x8, x8, x9
-; CHECK-NEWLOWERING-NEXT: mov sp, x9
-; CHECK-NEWLOWERING-NEXT: sub x10, x29, #16
-; CHECK-NEWLOWERING-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-NEWLOWERING-NEXT: msr TPIDR2_EL0, x10
-; CHECK-NEWLOWERING-NEXT: bl __addtf3
-; CHECK-NEWLOWERING-NEXT: smstart za
-; CHECK-NEWLOWERING-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-NEWLOWERING-NEXT: sub x0, x29, #16
-; CHECK-NEWLOWERING-NEXT: cbnz x8, .LBB1_2
-; CHECK-NEWLOWERING-NEXT: // %bb.1:
-; CHECK-NEWLOWERING-NEXT: bl __arm_tpidr2_restore
-; CHECK-NEWLOWERING-NEXT: .LBB1_2:
-; CHECK-NEWLOWERING-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-NEWLOWERING-NEXT: mov sp, x29
-; CHECK-NEWLOWERING-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
-; CHECK-NEWLOWERING-NEXT: ret
%res = fadd fp128 %a, %b
ret fp128 %res
}
diff --git a/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll b/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll
index aae1d3b756f4e..8068e11b37a65 100644
--- a/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll
+++ b/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll
@@ -1,51 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -aarch64-new-sme-abi=false < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-SDAG
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme < %s | FileCheck %s
declare void @private_za_call()
declare void @shared_za_call() "aarch64_inout_za"
define void @private_za_loop(i32 %n) "aarch64_inout_za" nounwind {
-; CHECK-SDAG-LABEL: private_za_loop:
-; CHECK-SDAG: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: cmp w0, #1
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: b.lt .LBB0_5
-; CHECK-SDAG-NEXT: // %bb.1: // %loop.preheader
-; CHECK-SDAG-NEXT: mov w19, w0
-; CHECK-SDAG-NEXT: sub x20, x29, #16
-; CHECK-SDAG-NEXT: b .LBB0_3
-; CHECK-SDAG-NEXT: .LBB0_2: // %loop
-; CHECK-SDAG-NEXT: // in Loop: Header=BB0_3 Depth=1
-; CHECK-SDAG-NEXT: subs w19, w19, #1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: b.eq .LBB0_5
-; CHECK-SDAG-NEXT: .LBB0_3: // %loop
-; CHECK-SDAG-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB0_2
-; CHECK-SDAG-NEXT: // %bb.4: // %loop
-; CHECK-SDAG-NEXT: // in Loop: Header=BB0_3 Depth=1
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: b .LBB0_2
-; CHECK-SDAG-NEXT: .LBB0_5: // %exit
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: private_za_loop:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
@@ -102,47 +61,6 @@ exit:
; FIXME: In the new lowering we could weight edges to avoid doing the lazy save in the loop.
define void @private_za_loop_active_entry_and_exit(i32 %n) "aarch64_inout_za" nounwind {
-; CHECK-SDAG-LABEL: private_za_loop_active_entry_and_exit:
-; CHECK-SDAG: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mov w19, w0
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: cmp w19, #1
-; CHECK-SDAG-NEXT: b.lt .LBB1_5
-; CHECK-SDAG-NEXT: // %bb.1: // %loop.preheader
-; CHECK-SDAG-NEXT: sub x20, x29, #16
-; CHECK-SDAG-NEXT: b .LBB1_3
-; CHECK-SDAG-NEXT: .LBB1_2: // %loop
-; CHECK-SDAG-NEXT: // in Loop: Header=BB1_3 Depth=1
-; CHECK-SDAG-NEXT: subs w19, w19, #1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: b.eq .LBB1_5
-; CHECK-SDAG-NEXT: .LBB1_3: // %loop
-; CHECK-SDAG-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB1_2
-; CHECK-SDAG-NEXT: // %bb.4: // %loop
-; CHECK-SDAG-NEXT: // in Loop: Header=BB1_3 Depth=1
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: b .LBB1_2
-; CHECK-SDAG-NEXT: .LBB1_5: // %exit
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: b shared_za_call
-;
; CHECK-LABEL: private_za_loop_active_entry_and_exit:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
@@ -201,22 +119,22 @@ exit:
}
define void @shared_za_loop(i32 %n) "aarch64_inout_za" nounwind {
-; CHECK-COMMON-LABEL: shared_za_loop:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: cmp w0, #1
-; CHECK-COMMON-NEXT: b.lt .LBB2_4
-; CHECK-COMMON-NEXT: // %bb.1: // %loop.preheader
-; CHECK-COMMON-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov w19, w0
-; CHECK-COMMON-NEXT: .LBB2_2: // %loop
-; CHECK-COMMON-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-COMMON-NEXT: bl shared_za_call
-; CHECK-COMMON-NEXT: subs w19, w19, #1
-; CHECK-COMMON-NEXT: b.ne .LBB2_2
-; CHECK-COMMON-NEXT: // %bb.3:
-; CHECK-COMMON-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: .LBB2_4: // %exit
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: shared_za_loop:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, #1
+; CHECK-NEXT: b.lt .LBB2_4
+; CHECK-NEXT: // %bb.1: // %loop.preheader
+; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: mov w19, w0
+; CHECK-NEXT: .LBB2_2: // %loop
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: bl shared_za_call
+; CHECK-NEXT: subs w19, w19, #1
+; CHECK-NEXT: b.ne .LBB2_2
+; CHECK-NEXT: // %bb.3:
+; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: .LBB2_4: // %exit
+; CHECK-NEXT: ret
entry:
%cmpgt = icmp sgt i32 %n, 0
br i1 %cmpgt, label %loop, label %exit
@@ -233,33 +151,33 @@ exit:
}
define void @cond_private_za_call(i1 %cond) "aarch64_inout_za" nounwind {
-; CHECK-COMMON-LABEL: cond_private_za_call:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: rdsvl x8, #1
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: msub x9, x8, x8, x9
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-COMMON-NEXT: tbz w0, #0, .LBB3_4
-; CHECK-COMMON-NEXT: // %bb.1: // %private_za_call
-; CHECK-COMMON-NEXT: sub x8, x29, #16
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x8
-; CHECK-COMMON-NEXT: bl private_za_call
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-COMMON-NEXT: sub x0, x29, #16
-; CHECK-COMMON-NEXT: cbnz x8, .LBB3_3
-; CHECK-COMMON-NEXT: // %bb.2: // %private_za_call
-; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
-; CHECK-COMMON-NEXT: .LBB3_3: // %private_za_call
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-COMMON-NEXT: .LBB3_4: // %exit
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: b shared_za_call
+; CHECK-LABEL: cond_private_za_call:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: rdsvl x8, #1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: msub x9, x8, x8, x9
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: stp x9, x8, [x29, #-16]
+; CHECK-NEXT: tbz w0, #0, .LBB3_4
+; CHECK-NEXT: // %bb.1: // %private_za_call
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
+; CHECK-NEXT: bl private_za_call
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: mrs x8, TPIDR2_EL0
+; CHECK-NEXT: sub x0, x29, #16
+; CHECK-NEXT: cbnz x8, .LBB3_3
+; CHECK-NEXT: // %bb.2: // %private_za_call
+; CHECK-NEXT: bl __arm_tpidr2_restore
+; CHECK-NEXT: .LBB3_3: // %private_za_call
+; CHECK-NEXT: msr TPIDR2_EL0, xzr
+; CHECK-NEXT: .LBB3_4: // %exit
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: b shared_za_call
br i1 %cond, label %private_za_call, label %exit
private_za_call:
@@ -272,45 +190,6 @@ exit:
}
define void @mixed_shared_private_za_loop(ptr %cond) "aarch64_inout_za" nounwind {
-; CHECK-SDAG-LABEL: mixed_shared_private_za_loop:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mov x19, x0
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: sub x20, x29, #16
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: b .LBB4_2
-; CHECK-SDAG-NEXT: .LBB4_1: // %loop
-; CHECK-SDAG-NEXT: // in Loop: Header=BB4_2 Depth=1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: ldrb w8, [x19]
-; CHECK-SDAG-NEXT: tbz w8, #0, .LBB4_4
-; CHECK-SDAG-NEXT: .LBB4_2: // %loop
-; CHECK-SDAG-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB4_1
-; CHECK-SDAG-NEXT: // %bb.3: // %loop
-; CHECK-SDAG-NEXT: // in Loop: Header=BB4_2 Depth=1
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: b .LBB4_1
-; CHECK-SDAG-NEXT: .LBB4_4: // %exit
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: mixed_shared_private_za_loop:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
@@ -368,49 +247,6 @@ exit:
define void @cond_clobber_followed_by_clobber(i1 %cond) "aarch64_inout_za" nounwind {
-; CHECK-SDAG-LABEL: cond_clobber_followed_by_clobber:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mov w19, w0
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: tbz w19, #0, .LBB5_4
-; CHECK-SDAG-NEXT: // %bb.1: // %cond_clobber
-; CHECK-SDAG-NEXT: sub x8, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB5_3
-; CHECK-SDAG-NEXT: // %bb.2: // %cond_clobber
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB5_3: // %cond_clobber
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .LBB5_4: // %exit
-; CHECK-SDAG-NEXT: sub x8, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB5_6
-; CHECK-SDAG-NEXT: // %bb.5: // %exit
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB5_6: // %exit
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: b shared_za_call
-;
; CHECK-LABEL: cond_clobber_followed_by_clobber:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
@@ -457,34 +293,34 @@ exit:
}
define void @conditionally_use_za(i1 %cond) "aarch64_inout_za" nounwind {
-; CHECK-COMMON-LABEL: conditionally_use_za:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: rdsvl x8, #1
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: msub x9, x8, x8, x9
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-COMMON-NEXT: tbz w0, #0, .LBB6_4
-; CHECK-COMMON-NEXT: // %bb.1: // %use_za
-; CHECK-COMMON-NEXT: bl shared_za_call
-; CHECK-COMMON-NEXT: sub x8, x29, #16
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x8
-; CHECK-COMMON-NEXT: bl private_za_call
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-COMMON-NEXT: sub x0, x29, #16
-; CHECK-COMMON-NEXT: cbnz x8, .LBB6_3
-; CHECK-COMMON-NEXT: // %bb.2: // %use_za
-; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
-; CHECK-COMMON-NEXT: .LBB6_3: // %use_za
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-COMMON-NEXT: .LBB6_4: // %exit
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: conditionally_use_za:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: rdsvl x8, #1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: msub x9, x8, x8, x9
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: stp x9, x8, [x29, #-16]
+; CHECK-NEXT: tbz w0, #0, .LBB6_4
+; CHECK-NEXT: // %bb.1: // %use_za
+; CHECK-NEXT: bl shared_za_call
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
+; CHECK-NEXT: bl private_za_call
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: mrs x8, TPIDR2_EL0
+; CHECK-NEXT: sub x0, x29, #16
+; CHECK-NEXT: cbnz x8, .LBB6_3
+; CHECK-NEXT: // %bb.2: // %use_za
+; CHECK-NEXT: bl __arm_tpidr2_restore
+; CHECK-NEXT: .LBB6_3: // %use_za
+; CHECK-NEXT: msr TPIDR2_EL0, xzr
+; CHECK-NEXT: .LBB6_4: // %exit
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
br i1 %cond, label %use_za, label %exit
use_za:
@@ -498,37 +334,37 @@ exit:
define void @diamond_mixed_za_merge_shared(i1 %cond) "aarch64_inout_za" nounwind {
-; CHECK-COMMON-LABEL: diamond_mixed_za_merge_shared:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: rdsvl x8, #1
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: msub x9, x8, x8, x9
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-COMMON-NEXT: tbz w0, #0, .LBB7_2
-; CHECK-COMMON-NEXT: // %bb.1: // %then
-; CHECK-COMMON-NEXT: bl shared_za_call
-; CHECK-COMMON-NEXT: b .LBB7_5
-; CHECK-COMMON-NEXT: .LBB7_2: // %else
-; CHECK-COMMON-NEXT: sub x8, x29, #16
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x8
-; CHECK-COMMON-NEXT: bl private_za_call
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-COMMON-NEXT: sub x0, x29, #16
-; CHECK-COMMON-NEXT: cbnz x8, .LBB7_4
-; CHECK-COMMON-NEXT: // %bb.3: // %else
-; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
-; CHECK-COMMON-NEXT: .LBB7_4: // %else
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-COMMON-NEXT: .LBB7_5: // %merge_shared
-; CHECK-COMMON-NEXT: bl shared_za_call
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: diamond_mixed_za_merge_shared:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: rdsvl x8, #1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: msub x9, x8, x8, x9
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: stp x9, x8, [x29, #-16]
+; CHECK-NEXT: tbz w0, #0, .LBB7_2
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: bl shared_za_call
+; CHECK-NEXT: b .LBB7_5
+; CHECK-NEXT: .LBB7_2: // %else
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
+; CHECK-NEXT: bl private_za_call
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: mrs x8, TPIDR2_EL0
+; CHECK-NEXT: sub x0, x29, #16
+; CHECK-NEXT: cbnz x8, .LBB7_4
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: bl __arm_tpidr2_restore
+; CHECK-NEXT: .LBB7_4: // %else
+; CHECK-NEXT: msr TPIDR2_EL0, xzr
+; CHECK-NEXT: .LBB7_5: // %merge_shared
+; CHECK-NEXT: bl shared_za_call
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
entry:
br i1 %cond, label %then, label %else
@@ -547,48 +383,6 @@ merge_shared:
define void @diamond_mixed_za_merge_private(i1 %cond) "aarch64_inout_za" nounwind {
-; CHECK-SDAG-LABEL: diamond_mixed_za_merge_private:
-; CHECK-SDAG: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: tbz w0, #0, .LBB8_2
-; CHECK-SDAG-NEXT: // %bb.1: // %then
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: b .LBB8_5
-; CHECK-SDAG-NEXT: .LBB8_2: // %else
-; CHECK-SDAG-NEXT: sub x8, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB8_4
-; CHECK-SDAG-NEXT: // %bb.3: // %else
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB8_4: // %else
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .LBB8_5: // %merge_private_za
-; CHECK-SDAG-NEXT: sub x8, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB8_7
-; CHECK-SDAG-NEXT: // %bb.6: // %merge_private_za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB8_7: // %merge_private_za
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: diamond_mixed_za_merge_private:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
@@ -639,56 +433,6 @@ merge_private_za:
}
define void @critical_edge_mixed_za(i1 %c1, i1 %c2) "aarch64_inout_za" nounwind {
-; CHECK-SDAG-LABEL: critical_edge_mixed_za:
-; CHECK-SDAG: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mov w19, w1
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: tbz w0, #0, .LBB9_5
-; CHECK-SDAG-NEXT: // %bb.1: // %shared_path
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: tbz w19, #0, .LBB9_8
-; CHECK-SDAG-NEXT: .LBB9_2: // %exit_private
-; CHECK-SDAG-NEXT: sub x8, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB9_4
-; CHECK-SDAG-NEXT: // %bb.3: // %exit_private
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB9_4: // %exit_private
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: b .LBB9_9
-; CHECK-SDAG-NEXT: .LBB9_5: // %private_path
-; CHECK-SDAG-NEXT: sub x8, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB9_7
-; CHECK-SDAG-NEXT: // %bb.6: // %private_path
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB9_7: // %private_path
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: tbnz w19, #0, .LBB9_2
-; CHECK-SDAG-NEXT: .LBB9_8: // %exit_shared
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: .LBB9_9: // %common.ret
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: critical_edge_mixed_za:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
@@ -762,58 +506,58 @@ exit_shared:
}
define void @nested_cond_in_loop(i32 %n, i1 %cond) "aarch64_inout_za" nounwind {
-; CHECK-COMMON-LABEL: nested_cond_in_loop:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-48]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: rdsvl x8, #1
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: msub x9, x8, x8, x9
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: cmp w0, #1
-; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-COMMON-NEXT: b.lt .LBB10_8
-; CHECK-COMMON-NEXT: // %bb.1: // %loop.preheader
-; CHECK-COMMON-NEXT: mov w19, w1
-; CHECK-COMMON-NEXT: mov w20, w0
-; CHECK-COMMON-NEXT: mov w21, wzr
-; CHECK-COMMON-NEXT: sub x22, x29, #16
-; CHECK-COMMON-NEXT: b .LBB10_4
-; CHECK-COMMON-NEXT: .LBB10_2: // %use_shared
-; CHECK-COMMON-NEXT: // in Loop: Header=BB10_4 Depth=1
-; CHECK-COMMON-NEXT: bl shared_za_call
-; CHECK-COMMON-NEXT: .LBB10_3: // %latch
-; CHECK-COMMON-NEXT: // in Loop: Header=BB10_4 Depth=1
-; CHECK-COMMON-NEXT: add w21, w21, #1
-; CHECK-COMMON-NEXT: cmp w21, w20
-; CHECK-COMMON-NEXT: b.ge .LBB10_8
-; CHECK-COMMON-NEXT: .LBB10_4: // %loop
-; CHECK-COMMON-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-COMMON-NEXT: tbnz w19, #0, .LBB10_2
-; CHECK-COMMON-NEXT: // %bb.5: // %use_private
-; CHECK-COMMON-NEXT: // in Loop: Header=BB10_4 Depth=1
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x22
-; CHECK-COMMON-NEXT: bl private_za_call
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-COMMON-NEXT: sub x0, x29, #16
-; CHECK-COMMON-NEXT: cbnz x8, .LBB10_7
-; CHECK-COMMON-NEXT: // %bb.6: // %use_private
-; CHECK-COMMON-NEXT: // in Loop: Header=BB10_4 Depth=1
-; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
-; CHECK-COMMON-NEXT: .LBB10_7: // %use_private
-; CHECK-COMMON-NEXT: // in Loop: Header=BB10_4 Depth=1
-; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-COMMON-NEXT: b .LBB10_3
-; CHECK-COMMON-NEXT: .LBB10_8: // %exit
-; CHECK-COMMON-NEXT: mov sp, x29
-; CHECK-COMMON-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #48 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: nested_cond_in_loop:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-48]! // 16-byte Folded Spill
+; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: rdsvl x8, #1
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: msub x9, x8, x8, x9
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: cmp w0, #1
+; CHECK-NEXT: stp x9, x8, [x29, #-16]
+; CHECK-NEXT: b.lt .LBB10_8
+; CHECK-NEXT: // %bb.1: // %loop.preheader
+; CHECK-NEXT: mov w19, w1
+; CHECK-NEXT: mov w20, w0
+; CHECK-NEXT: mov w21, wzr
+; CHECK-NEXT: sub x22, x29, #16
+; CHECK-NEXT: b .LBB10_4
+; CHECK-NEXT: .LBB10_2: // %use_shared
+; CHECK-NEXT: // in Loop: Header=BB10_4 Depth=1
+; CHECK-NEXT: bl shared_za_call
+; CHECK-NEXT: .LBB10_3: // %latch
+; CHECK-NEXT: // in Loop: Header=BB10_4 Depth=1
+; CHECK-NEXT: add w21, w21, #1
+; CHECK-NEXT: cmp w21, w20
+; CHECK-NEXT: b.ge .LBB10_8
+; CHECK-NEXT: .LBB10_4: // %loop
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: tbnz w19, #0, .LBB10_2
+; CHECK-NEXT: // %bb.5: // %use_private
+; CHECK-NEXT: // in Loop: Header=BB10_4 Depth=1
+; CHECK-NEXT: msr TPIDR2_EL0, x22
+; CHECK-NEXT: bl private_za_call
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: mrs x8, TPIDR2_EL0
+; CHECK-NEXT: sub x0, x29, #16
+; CHECK-NEXT: cbnz x8, .LBB10_7
+; CHECK-NEXT: // %bb.6: // %use_private
+; CHECK-NEXT: // in Loop: Header=BB10_4 Depth=1
+; CHECK-NEXT: bl __arm_tpidr2_restore
+; CHECK-NEXT: .LBB10_7: // %use_private
+; CHECK-NEXT: // in Loop: Header=BB10_4 Depth=1
+; CHECK-NEXT: msr TPIDR2_EL0, xzr
+; CHECK-NEXT: b .LBB10_3
+; CHECK-NEXT: .LBB10_8: // %exit
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #48 // 16-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i32 %n, 0
br i1 %cmp, label %loop, label %exit
@@ -840,46 +584,6 @@ exit:
}
define void @loop_with_external_entry(i1 %c1, i1 %c2) "aarch64_inout_za" nounwind {
-; CHECK-SDAG-LABEL: loop_with_external_entry:
-; CHECK-SDAG: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mov w19, w1
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: tbz w0, #0, .LBB11_2
-; CHECK-SDAG-NEXT: // %bb.1: // %init
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: .LBB11_2: // %loop.preheader
-; CHECK-SDAG-NEXT: sub x20, x29, #16
-; CHECK-SDAG-NEXT: b .LBB11_4
-; CHECK-SDAG-NEXT: .LBB11_3: // %loop
-; CHECK-SDAG-NEXT: // in Loop: Header=BB11_4 Depth=1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: tbz w19, #0, .LBB11_6
-; CHECK-SDAG-NEXT: .LBB11_4: // %loop
-; CHECK-SDAG-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl private_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB11_3
-; CHECK-SDAG-NEXT: // %bb.5: // %loop
-; CHECK-SDAG-NEXT: // in Loop: Header=BB11_4 Depth=1
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: b .LBB11_3
-; CHECK-SDAG-NEXT: .LBB11_6: // %exit
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: loop_with_external_entry:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
diff --git a/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll b/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
index 19ea1e47f84ff..6eb4de449aaa6 100644
--- a/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -aarch64-new-sme-abi=false -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-SDAG
; A simple EH test case that corresponds to the following C++ source:
;
@@ -88,90 +87,6 @@ define void @za_with_raii(i1 %fail) "aarch64_inout_za" personality ptr @__gxx_pe
; CHECK-NEXT: mov x0, x19
; CHECK-NEXT: msr TPIDR2_EL0, x8
; CHECK-NEXT: bl _Unwind_Resume
-;
-; CHECK-SDAG-LABEL: za_with_raii:
-; CHECK-SDAG: .Lfunc_begin0:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception0
-; CHECK-SDAG-NEXT: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 32
-; CHECK-SDAG-NEXT: .cfi_offset w19, -8
-; CHECK-SDAG-NEXT: .cfi_offset w20, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -24
-; CHECK-SDAG-NEXT: .cfi_offset w29, -32
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: tbnz w0, #0, .LBB0_2
-; CHECK-SDAG-NEXT: // %bb.1: // %return_normally
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: b shared_za_call
-; CHECK-SDAG-NEXT: .LBB0_2: // %throw_exception
-; CHECK-SDAG-NEXT: sub x20, x29, #16
-; CHECK-SDAG-NEXT: mov w0, #8 // =0x8
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl __cxa_allocate_exception
-; CHECK-SDAG-NEXT: mov x8, x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x9, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x9, .LBB0_4
-; CHECK-SDAG-NEXT: // %bb.3: // %throw_exception
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB0_4: // %throw_exception
-; CHECK-SDAG-NEXT: adrp x9, .L.str
-; CHECK-SDAG-NEXT: add x9, x9, :lo12:.L.str
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: str x9, [x8]
-; CHECK-SDAG-NEXT: .Ltmp0: // EH_LABEL
-; CHECK-SDAG-NEXT: adrp x1, :got:typeinfo_for_char_const_ptr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: mov x0, x8
-; CHECK-SDAG-NEXT: ldr x1, [x1, :got_lo12:typeinfo_for_char_const_ptr]
-; CHECK-SDAG-NEXT: mov x2, xzr
-; CHECK-SDAG-NEXT: bl __cxa_throw
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB0_6
-; CHECK-SDAG-NEXT: // %bb.5: // %throw_exception
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB0_6: // %throw_exception
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .Ltmp1: // EH_LABEL
-; CHECK-SDAG-NEXT: // %bb.7: // %throw_fail
-; CHECK-SDAG-NEXT: .LBB0_8: // %unwind_dtors
-; CHECK-SDAG-NEXT: .Ltmp2: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x19, x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB0_10
-; CHECK-SDAG-NEXT: // %bb.9: // %unwind_dtors
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB0_10: // %unwind_dtors
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x20
-; CHECK-SDAG-NEXT: bl _Unwind_Resume
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB0_12
-; CHECK-SDAG-NEXT: // %bb.11: // %unwind_dtors
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB0_12: // %unwind_dtors
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
br i1 %fail, label %throw_exception, label %return_normally
throw_exception:
@@ -268,78 +183,6 @@ define void @try_catch() "aarch64_inout_za" personality ptr @__gxx_personality_v
; CHECK-NEXT: .LBB1_8: // %catch
; CHECK-NEXT: msr TPIDR2_EL0, xzr
; CHECK-NEXT: b .LBB1_3
-;
-; CHECK-SDAG-LABEL: try_catch:
-; CHECK-SDAG: .Lfunc_begin1:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception1
-; CHECK-SDAG-NEXT: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 32
-; CHECK-SDAG-NEXT: .cfi_offset w19, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -24
-; CHECK-SDAG-NEXT: .cfi_offset w29, -32
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: .Ltmp3: // EH_LABEL
-; CHECK-SDAG-NEXT: sub x19, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x19
-; CHECK-SDAG-NEXT: bl may_throw
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB1_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB1_2:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .Ltmp4: // EH_LABEL
-; CHECK-SDAG-NEXT: .LBB1_3: // %after_catch
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: b shared_za_call
-; CHECK-SDAG-NEXT: .LBB1_4: // %catch
-; CHECK-SDAG-NEXT: .Ltmp5: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB1_6
-; CHECK-SDAG-NEXT: // %bb.5: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB1_6: // %catch
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x19
-; CHECK-SDAG-NEXT: bl __cxa_begin_catch
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB1_8
-; CHECK-SDAG-NEXT: // %bb.7: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB1_8: // %catch
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x19
-; CHECK-SDAG-NEXT: bl __cxa_end_catch
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB1_10
-; CHECK-SDAG-NEXT: // %bb.9: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB1_10: // %catch
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: b .LBB1_3
invoke void @may_throw()
to label %after_catch unwind label %catch
@@ -426,78 +269,6 @@ define void @try_catch_shared_za_callee() "aarch64_new_za" personality ptr @__gx
; CHECK-NEXT: msr TPIDR2_EL0, xzr
; CHECK-NEXT: smstop za
; CHECK-NEXT: b .LBB2_3
-;
-; CHECK-SDAG-LABEL: try_catch_shared_za_callee:
-; CHECK-SDAG: .Lfunc_begin2:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception2
-; CHECK-SDAG-NEXT: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 32
-; CHECK-SDAG-NEXT: .cfi_offset w19, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -24
-; CHECK-SDAG-NEXT: .cfi_offset w29, -32
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB2_2
-; CHECK-SDAG-NEXT: // %bb.1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .LBB2_2:
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: zero {za}
-; CHECK-SDAG-NEXT: .Ltmp6: // EH_LABEL
-; CHECK-SDAG-NEXT: bl shared_za_call
-; CHECK-SDAG-NEXT: .Ltmp7: // EH_LABEL
-; CHECK-SDAG-NEXT: .LBB2_3: // %exit
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-; CHECK-SDAG-NEXT: .LBB2_4: // %catch
-; CHECK-SDAG-NEXT: .Ltmp8: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: sub x19, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB2_6
-; CHECK-SDAG-NEXT: // %bb.5: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB2_6: // %catch
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x19
-; CHECK-SDAG-NEXT: bl __cxa_begin_catch
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB2_8
-; CHECK-SDAG-NEXT: // %bb.7: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB2_8: // %catch
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: bl noexcept_shared_za_call
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x19
-; CHECK-SDAG-NEXT: bl __cxa_end_catch
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB2_10
-; CHECK-SDAG-NEXT: // %bb.9: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB2_10: // %catch
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: b .LBB2_3
invoke void @shared_za_call() #4
to label %exit unwind label %catch
catch:
@@ -566,46 +337,6 @@ define void @try_catch_shared_zt0_callee() "aarch64_inout_zt0" personality ptr @
; CHECK-NEXT: smstop za
; CHECK-NEXT: mov x0, x19
; CHECK-NEXT: bl _Unwind_Resume
-;
-; CHECK-SDAG-LABEL: try_catch_shared_zt0_callee:
-; CHECK-SDAG: .Lfunc_begin3:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception3
-; CHECK-SDAG-NEXT: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #96
-; CHECK-SDAG-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 96
-; CHECK-SDAG-NEXT: .cfi_offset w19, -8
-; CHECK-SDAG-NEXT: .cfi_offset w20, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -32
-; CHECK-SDAG-NEXT: .Ltmp9: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: str zt0, [x19]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: bl may_throw
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x19]
-; CHECK-SDAG-NEXT: .Ltmp10: // EH_LABEL
-; CHECK-SDAG-NEXT: // %bb.1: // %return_normally
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldr x30, [sp, #64] // 8-byte Reload
-; CHECK-SDAG-NEXT: add sp, sp, #96
-; CHECK-SDAG-NEXT: ret
-; CHECK-SDAG-NEXT: .LBB3_2: // %unwind_dtors
-; CHECK-SDAG-NEXT: .Ltmp11: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x20, sp
-; CHECK-SDAG-NEXT: mov x19, x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
-; CHECK-SDAG-NEXT: bl shared_zt0_call
-; CHECK-SDAG-NEXT: str zt0, [x20]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl _Unwind_Resume
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
invoke void @may_throw()
to label %return_normally unwind label %unwind_dtors
@@ -667,52 +398,6 @@ define void @try_catch_agnostic_za() "aarch64_za_state_agnostic" personality ptr
; CHECK-NEXT: mov x0, x19
; CHECK-NEXT: bl __arm_sme_restore
; CHECK-NEXT: b .LBB4_1
-;
-; CHECK-SDAG-LABEL: try_catch_agnostic_za:
-; CHECK-SDAG: .Lfunc_begin4:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception4
-; CHECK-SDAG-NEXT: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 32
-; CHECK-SDAG-NEXT: .cfi_offset w19, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -24
-; CHECK-SDAG-NEXT: .cfi_offset w29, -32
-; CHECK-SDAG-NEXT: bl __arm_sme_state_size
-; CHECK-SDAG-NEXT: sub sp, sp, x0
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: .Ltmp12: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: bl may_throw
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: .Ltmp13: // EH_LABEL
-; CHECK-SDAG-NEXT: .LBB4_1: // %exit
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-; CHECK-SDAG-NEXT: .LBB4_2: // %catch
-; CHECK-SDAG-NEXT: .Ltmp14: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: bl __cxa_begin_catch
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: bl __cxa_end_catch
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: b .LBB4_1
invoke void @may_throw()
to label %exit unwind label %catch
catch:
@@ -779,52 +464,6 @@ define void @try_catch_agnostic_za_invoke() "aarch64_za_state_agnostic" personal
; CHECK-NEXT: mov x0, x19
; CHECK-NEXT: bl __arm_sme_restore
; CHECK-NEXT: b .LBB5_1
-;
-; CHECK-SDAG-LABEL: try_catch_agnostic_za_invoke:
-; CHECK-SDAG: .Lfunc_begin5:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception5
-; CHECK-SDAG-NEXT: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 32
-; CHECK-SDAG-NEXT: .cfi_offset w19, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -24
-; CHECK-SDAG-NEXT: .cfi_offset w29, -32
-; CHECK-SDAG-NEXT: bl __arm_sme_state_size
-; CHECK-SDAG-NEXT: sub sp, sp, x0
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: .Ltmp15: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: bl agnostic_za_call
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: .Ltmp16: // EH_LABEL
-; CHECK-SDAG-NEXT: .LBB5_1: // %exit
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-; CHECK-SDAG-NEXT: .LBB5_2: // %catch
-; CHECK-SDAG-NEXT: .Ltmp17: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: bl __cxa_begin_catch
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_save
-; CHECK-SDAG-NEXT: bl __cxa_end_catch
-; CHECK-SDAG-NEXT: mov x0, x19
-; CHECK-SDAG-NEXT: bl __arm_sme_restore
-; CHECK-SDAG-NEXT: b .LBB5_1
entry:
invoke void @agnostic_za_call() "aarch64_za_state_agnostic"
to label %exit unwind label %catch
@@ -891,77 +530,6 @@ define void @try_catch_inout_za_agnostic_za_callee() "aarch64_inout_za" personal
; CHECK-NEXT: .LBB6_6: // %catch
; CHECK-NEXT: msr TPIDR2_EL0, xzr
; CHECK-NEXT: b .LBB6_3
-;
-; CHECK-SDAG-LABEL: try_catch_inout_za_agnostic_za_callee:
-; CHECK-SDAG: .Lfunc_begin6:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception6
-; CHECK-SDAG-NEXT: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 32
-; CHECK-SDAG-NEXT: .cfi_offset w19, -16
-; CHECK-SDAG-NEXT: .cfi_offset w30, -24
-; CHECK-SDAG-NEXT: .cfi_offset w29, -32
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: .Ltmp18: // EH_LABEL
-; CHECK-SDAG-NEXT: sub x19, x29, #16
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x19
-; CHECK-SDAG-NEXT: bl agnostic_za_call
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB6_2
-; CHECK-SDAG-NEXT: // %bb.1: // %entry
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB6_2: // %entry
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .Ltmp19: // EH_LABEL
-; CHECK-SDAG-NEXT: .LBB6_3: // %exit
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-; CHECK-SDAG-NEXT: .LBB6_4: // %catch
-; CHECK-SDAG-NEXT: .Ltmp20: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x1, x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB6_6
-; CHECK-SDAG-NEXT: // %bb.5: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB6_6: // %catch
-; CHECK-SDAG-NEXT: mov x0, x1
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x19
-; CHECK-SDAG-NEXT: bl __cxa_begin_catch
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB6_8
-; CHECK-SDAG-NEXT: // %bb.7: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB6_8: // %catch
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x19
-; CHECK-SDAG-NEXT: bl __cxa_end_catch
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB6_10
-; CHECK-SDAG-NEXT: // %bb.9: // %catch
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB6_10: // %catch
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: b .LBB6_3
entry:
invoke void @agnostic_za_call()
to label %exit unwind label %catch
@@ -1009,45 +577,6 @@ define void @try_catch_inout_zt0() "aarch64_inout_zt0" personality ptr @__gxx_pe
; CHECK-NEXT: smstart za
; CHECK-NEXT: ldr zt0, [x19]
; CHECK-NEXT: b .LBB7_1
-;
-; CHECK-SDAG-LABEL: try_catch_inout_zt0:
-; CHECK-SDAG: .Lfunc_begin7:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception7
-; CHECK-SDAG-NEXT: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: sub sp, sp, #80
-; CHECK-SDAG-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 80
-; CHECK-SDAG-NEXT: .cfi_offset w19, -8
-; CHECK-SDAG-NEXT: .cfi_offset w30, -16
-; CHECK-SDAG-NEXT: .Ltmp21: // EH_LABEL
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: str zt0, [x19]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: bl may_throw
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x19]
-; CHECK-SDAG-NEXT: .Ltmp22: // EH_LABEL
-; CHECK-SDAG-NEXT: .LBB7_1: // %exit
-; CHECK-SDAG-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: add sp, sp, #80
-; CHECK-SDAG-NEXT: ret
-; CHECK-SDAG-NEXT: .LBB7_2: // %catch
-; CHECK-SDAG-NEXT: .Ltmp23: // EH_LABEL
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x19]
-; CHECK-SDAG-NEXT: str zt0, [x19]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: bl __cxa_begin_catch
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x19]
-; CHECK-SDAG-NEXT: str zt0, [x19]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: bl __cxa_end_catch
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x19]
-; CHECK-SDAG-NEXT: b .LBB7_1
entry:
invoke void @may_throw()
to label %exit unwind label %catch
@@ -1123,83 +652,6 @@ define void @try_catch_shared_za_callee_zt0_saved(ptr %callee) "aarch64_inout_za
; CHECK-NEXT: mov x0, x20
; CHECK-NEXT: msr TPIDR2_EL0, x8
; CHECK-NEXT: bl _Unwind_Resume
-;
-; CHECK-SDAG-LABEL: try_catch_shared_za_callee_zt0_saved:
-; CHECK-SDAG: .Lfunc_begin8:
-; CHECK-SDAG-NEXT: .cfi_startproc
-; CHECK-SDAG-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
-; CHECK-SDAG-NEXT: .cfi_lsda 28, .Lexception8
-; CHECK-SDAG-NEXT: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-48]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: sub sp, sp, #80
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 48
-; CHECK-SDAG-NEXT: .cfi_offset w19, -8
-; CHECK-SDAG-NEXT: .cfi_offset w20, -16
-; CHECK-SDAG-NEXT: .cfi_offset w21, -24
-; CHECK-SDAG-NEXT: .cfi_offset w22, -32
-; CHECK-SDAG-NEXT: .cfi_offset w30, -40
-; CHECK-SDAG-NEXT: .cfi_offset w29, -48
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mov x19, x0
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: .Ltmp24: // EH_LABEL
-; CHECK-SDAG-NEXT: sub x8, x29, #16
-; CHECK-SDAG-NEXT: sub x20, x29, #80
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8
-; CHECK-SDAG-NEXT: str zt0, [x20]
-; CHECK-SDAG-NEXT: bl may_throw
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB8_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB8_2:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .Ltmp25: // EH_LABEL
-; CHECK-SDAG-NEXT: // %bb.3: // %return_normally
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #48 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-; CHECK-SDAG-NEXT: .LBB8_4: // %unwind_dtors
-; CHECK-SDAG-NEXT: .Ltmp26: // EH_LABEL
-; CHECK-SDAG-NEXT: sub x21, x29, #80
-; CHECK-SDAG-NEXT: sub x22, x29, #16
-; CHECK-SDAG-NEXT: mov x20, x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x21]
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB8_6
-; CHECK-SDAG-NEXT: // %bb.5: // %unwind_dtors
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB8_6: // %unwind_dtors
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: str zt0, [x21]
-; CHECK-SDAG-NEXT: blr x19
-; CHECK-SDAG-NEXT: ldr zt0, [x21]
-; CHECK-SDAG-NEXT: mov x0, x20
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x22
-; CHECK-SDAG-NEXT: str zt0, [x21]
-; CHECK-SDAG-NEXT: bl _Unwind_Resume
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x21]
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB8_8
-; CHECK-SDAG-NEXT: // %bb.7: // %unwind_dtors
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB8_8: // %unwind_dtors
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
invoke void @may_throw()
to label %return_normally unwind label %unwind_dtors
diff --git a/llvm/test/CodeGen/AArch64/sme-za-function-with-many-blocks.ll b/llvm/test/CodeGen/AArch64/sme-za-function-with-many-blocks.ll
index 0306b27cb17e1..01a1746866f4f 100644
--- a/llvm/test/CodeGen/AArch64/sme-za-function-with-many-blocks.ll
+++ b/llvm/test/CodeGen/AArch64/sme-za-function-with-many-blocks.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -aarch64-new-sme-abi < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s
; This test case was generated by lowering mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir to LLVM IR.
; The actual contents of the function are not that important. The main interesting quality here is that many blocks
diff --git a/llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll b/llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll
index 26fc39e271090..27082d9af93b3 100644
--- a/llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll
+++ b/llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -aarch64-new-sme-abi=false < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s
define i32 @no_tpidr2_save_required() "aarch64_inout_za" {
diff --git a/llvm/test/CodeGen/AArch64/sme-zt0-state.ll b/llvm/test/CodeGen/AArch64/sme-zt0-state.ll
index 4cbdca7d41aac..d3c3c111c205b 100644
--- a/llvm/test/CodeGen/AArch64/sme-zt0-state.ll
+++ b/llvm/test/CodeGen/AArch64/sme-zt0-state.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -start-after=simplifycfg -enable-tail-merge=false -aarch64-new-sme-abi=false -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-SDAG
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -start-after=simplifycfg -enable-tail-merge=false -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -start-after=simplifycfg -enable-tail-merge=false -verify-machineinstrs < %s | FileCheck %s
;
; Private-ZA Callee
@@ -9,19 +8,19 @@
; Expect spill & fill of ZT0 around call
; Expect smstop/smstart za around call
define void @zt0_in_caller_no_state_callee(ptr %callee) "aarch64_in_zt0" nounwind {
-; CHECK-COMMON-LABEL: zt0_in_caller_no_state_callee:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: sub sp, sp, #80
-; CHECK-COMMON-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x19, sp
-; CHECK-COMMON-NEXT: str zt0, [x19]
-; CHECK-COMMON-NEXT: smstop za
-; CHECK-COMMON-NEXT: blr x0
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: ldr zt0, [x19]
-; CHECK-COMMON-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: add sp, sp, #80
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: zt0_in_caller_no_state_callee:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: mov x19, sp
+; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: smstop za
+; CHECK-NEXT: blr x0
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: ldr zt0, [x19]
+; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ret
call void %callee();
ret void;
}
@@ -30,36 +29,6 @@ define void @zt0_in_caller_no_state_callee(ptr %callee) "aarch64_in_zt0" nounwin
; Expect setup and restore lazy-save around call
; Expect smstart za after call
define void @za_zt0_shared_caller_no_state_callee(ptr %callee) "aarch64_inout_za" "aarch64_in_zt0" nounwind {
-; CHECK-SDAG-LABEL: za_zt0_shared_caller_no_state_callee:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #80
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: sub x10, x29, #16
-; CHECK-SDAG-NEXT: sub x19, x29, #80
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x10
-; CHECK-SDAG-NEXT: str zt0, [x19]
-; CHECK-SDAG-NEXT: blr x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x19]
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB1_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB1_2:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: za_zt0_shared_caller_no_state_callee:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
@@ -99,41 +68,41 @@ define void @za_zt0_shared_caller_no_state_callee(ptr %callee) "aarch64_inout_za
; Caller and callee have shared ZT0 state, no spill/fill of ZT0 required
define void @zt0_shared_caller_zt0_shared_callee(ptr %callee) "aarch64_in_zt0" nounwind {
-; CHECK-COMMON-LABEL: zt0_shared_caller_zt0_shared_callee:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: blr x0
-; CHECK-COMMON-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: zt0_shared_caller_zt0_shared_callee:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: blr x0
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call void %callee() "aarch64_in_zt0";
ret void;
}
; Expect spill & fill of ZT0 around call
define void @za_zt0_shared_caller_za_shared_callee(ptr %callee) "aarch64_inout_za" "aarch64_in_zt0" nounwind {
-; CHECK-COMMON-LABEL: za_zt0_shared_caller_za_shared_callee:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: sub sp, sp, #80
-; CHECK-COMMON-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x19, sp
-; CHECK-COMMON-NEXT: str zt0, [x19]
-; CHECK-COMMON-NEXT: blr x0
-; CHECK-COMMON-NEXT: ldr zt0, [x19]
-; CHECK-COMMON-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: add sp, sp, #80
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: za_zt0_shared_caller_za_shared_callee:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: mov x19, sp
+; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: blr x0
+; CHECK-NEXT: ldr zt0, [x19]
+; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ret
call void %callee() "aarch64_inout_za";
ret void;
}
; Caller and callee have shared ZA & ZT0
define void @za_zt0_shared_caller_za_zt0_shared_callee(ptr %callee) "aarch64_inout_za" "aarch64_in_zt0" nounwind {
-; CHECK-COMMON-LABEL: za_zt0_shared_caller_za_zt0_shared_callee:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: blr x0
-; CHECK-COMMON-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: za_zt0_shared_caller_za_zt0_shared_callee:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: blr x0
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call void %callee() "aarch64_inout_za" "aarch64_in_zt0";
ret void;
}
@@ -143,19 +112,19 @@ define void @za_zt0_shared_caller_za_zt0_shared_callee(ptr %callee) "aarch64_ino
; Expect spill & fill of ZT0 around call
; Expect smstop/smstart za around call
define void @zt0_in_caller_zt0_new_callee(ptr %callee) "aarch64_in_zt0" nounwind {
-; CHECK-COMMON-LABEL: zt0_in_caller_zt0_new_callee:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: sub sp, sp, #80
-; CHECK-COMMON-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x19, sp
-; CHECK-COMMON-NEXT: str zt0, [x19]
-; CHECK-COMMON-NEXT: smstop za
-; CHECK-COMMON-NEXT: blr x0
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: ldr zt0, [x19]
-; CHECK-COMMON-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: add sp, sp, #80
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: zt0_in_caller_zt0_new_callee:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: mov x19, sp
+; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: smstop za
+; CHECK-NEXT: blr x0
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: ldr zt0, [x19]
+; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ret
call void %callee() "aarch64_new_zt0";
ret void;
}
@@ -167,29 +136,6 @@ define void @zt0_in_caller_zt0_new_callee(ptr %callee) "aarch64_in_zt0" nounwind
; Expect spill & fill of ZT0 around call
; Before return, expect smstop ZA
define void @zt0_new_caller_zt0_new_callee(ptr %callee) "aarch64_new_zt0" nounwind {
-; CHECK-SDAG-LABEL: zt0_new_caller_zt0_new_callee:
-; CHECK-SDAG: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: sub sp, sp, #80
-; CHECK-SDAG-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB6_2
-; CHECK-SDAG-NEXT: // %bb.1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .LBB6_2:
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: zero { zt0 }
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: str zt0, [x19]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: blr x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x19]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: add sp, sp, #80
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: zt0_new_caller_zt0_new_callee:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
@@ -219,27 +165,6 @@ define void @zt0_new_caller_zt0_new_callee(ptr %callee) "aarch64_new_zt0" nounwi
; Expect spill & fill of ZT0 around __arm_sme_state call
; Before return, expect smstop ZA
define i64 @zt0_new_caller_abi_routine_callee() "aarch64_new_zt0" nounwind {
-; CHECK-SDAG-LABEL: zt0_new_caller_abi_routine_callee:
-; CHECK-SDAG: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: sub sp, sp, #80
-; CHECK-SDAG-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB7_2
-; CHECK-SDAG-NEXT: // %bb.1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .LBB7_2:
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: zero { zt0 }
-; CHECK-SDAG-NEXT: mov x19, sp
-; CHECK-SDAG-NEXT: str zt0, [x19]
-; CHECK-SDAG-NEXT: bl __arm_sme_state
-; CHECK-SDAG-NEXT: ldr zt0, [x19]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: add sp, sp, #80
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: zt0_new_caller_abi_routine_callee:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
@@ -274,22 +199,6 @@ declare {i64, i64} @__arm_sme_state()
; Expect smstart ZA & clear ZT0
; Before return, expect smstop ZA
define void @zt0_new_caller(ptr %callee) "aarch64_new_zt0" nounwind {
-; CHECK-SDAG-LABEL: zt0_new_caller:
-; CHECK-SDAG: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB8_2
-; CHECK-SDAG-NEXT: // %bb.1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .LBB8_2:
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: zero { zt0 }
-; CHECK-SDAG-NEXT: blr x0
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: zt0_new_caller:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
@@ -313,23 +222,6 @@ define void @zt0_new_caller(ptr %callee) "aarch64_new_zt0" nounwind {
; Expect smstart ZA, clear ZA & clear ZT0
; Before return, expect smstop ZA
define void @new_za_zt0_caller(ptr %callee) "aarch64_new_za" "aarch64_new_zt0" nounwind {
-; CHECK-SDAG-LABEL: new_za_zt0_caller:
-; CHECK-SDAG: // %bb.0: // %prelude
-; CHECK-SDAG-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: cbz x8, .LBB9_2
-; CHECK-SDAG-NEXT: // %bb.1: // %save.za
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_save
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: .LBB9_2:
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: zero {za}
-; CHECK-SDAG-NEXT: zero { zt0 }
-; CHECK-SDAG-NEXT: blr x0
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: new_za_zt0_caller:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
@@ -352,64 +244,32 @@ define void @new_za_zt0_caller(ptr %callee) "aarch64_new_za" "aarch64_new_zt0" n
; Expect clear ZA on entry
define void @new_za_shared_zt0_caller(ptr %callee) "aarch64_new_za" "aarch64_in_zt0" nounwind {
-; CHECK-COMMON-LABEL: new_za_shared_zt0_caller:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: zero {za}
-; CHECK-COMMON-NEXT: blr x0
-; CHECK-COMMON-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: new_za_shared_zt0_caller:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: zero {za}
+; CHECK-NEXT: blr x0
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call void %callee() "aarch64_inout_za" "aarch64_in_zt0";
ret void;
}
; Expect clear ZT0 on entry
define void @shared_za_new_zt0(ptr %callee) "aarch64_inout_za" "aarch64_new_zt0" nounwind {
-; CHECK-COMMON-LABEL: shared_za_new_zt0:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: zero { zt0 }
-; CHECK-COMMON-NEXT: blr x0
-; CHECK-COMMON-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: shared_za_new_zt0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: zero { zt0 }
+; CHECK-NEXT: blr x0
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
call void %callee() "aarch64_inout_za" "aarch64_in_zt0";
ret void;
}
define void @zt0_multiple_private_za_calls(ptr %callee) "aarch64_in_zt0" nounwind {
-; CHECK-SDAG-LABEL: zt0_multiple_private_za_calls:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #96
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x20, sp
-; CHECK-SDAG-NEXT: mov x19, x0
-; CHECK-SDAG-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-SDAG-NEXT: str zt0, [x20]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: blr x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
-; CHECK-SDAG-NEXT: str zt0, [x20]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: blr x19
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
-; CHECK-SDAG-NEXT: str zt0, [x20]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: blr x19
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
-; CHECK-SDAG-NEXT: str zt0, [x20]
-; CHECK-SDAG-NEXT: smstop za
-; CHECK-SDAG-NEXT: blr x19
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldr x30, [sp, #64] // 8-byte Reload
-; CHECK-SDAG-NEXT: add sp, sp, #96
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: zt0_multiple_private_za_calls:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
@@ -437,62 +297,27 @@ define void @zt0_multiple_private_za_calls(ptr %callee) "aarch64_in_zt0" nounwin
}
define void @disable_tailcallopt(ptr %callee) "aarch64_inout_zt0" nounwind {
-; CHECK-COMMON-LABEL: disable_tailcallopt:
-; CHECK-COMMON: // %bb.0:
-; CHECK-COMMON-NEXT: sub sp, sp, #80
-; CHECK-COMMON-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x19, sp
-; CHECK-COMMON-NEXT: str zt0, [x19]
-; CHECK-COMMON-NEXT: smstop za
-; CHECK-COMMON-NEXT: blr x0
-; CHECK-COMMON-NEXT: smstart za
-; CHECK-COMMON-NEXT: ldr zt0, [x19]
-; CHECK-COMMON-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: add sp, sp, #80
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: disable_tailcallopt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: mov x19, sp
+; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: smstop za
+; CHECK-NEXT: blr x0
+; CHECK-NEXT: smstart za
+; CHECK-NEXT: ldr zt0, [x19]
+; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ret
tail call void %callee()
ret void
}
-; Expected new lowering (not CHECK-SDAG)
; - Lazy save and spill of ZT0 before first call
; - Restore of ZA before second call
; - Reload of ZT0 after second call
define void @za_zt0_private_za_to_shared_za(ptr %callee) "aarch64_inout_za" "aarch64_inout_zt0" nounwind {
-; CHECK-SDAG-LABEL: za_zt0_private_za_to_shared_za:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: mov x29, sp
-; CHECK-SDAG-NEXT: sub sp, sp, #80
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mov x19, x0
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: sub x10, x29, #16
-; CHECK-SDAG-NEXT: sub x20, x29, #80
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x10
-; CHECK-SDAG-NEXT: str zt0, [x20]
-; CHECK-SDAG-NEXT: blr x0
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #16
-; CHECK-SDAG-NEXT: cbnz x8, .LBB14_2
-; CHECK-SDAG-NEXT: // %bb.1:
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB14_2:
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: str zt0, [x20]
-; CHECK-SDAG-NEXT: blr x19
-; CHECK-SDAG-NEXT: ldr zt0, [x20]
-; CHECK-SDAG-NEXT: mov sp, x29
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: za_zt0_private_za_to_shared_za:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
diff --git a/llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll b/llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
index 4dec5471e689c..2cedcfec77826 100644
--- a/llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
+++ b/llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 -aarch64-streaming-hazard-size=0 -aarch64-new-sme-abi=false | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-SDAG
-; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 -aarch64-streaming-hazard-size=0 | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK
+; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 -aarch64-streaming-hazard-size=0 | FileCheck %s
; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 -aarch64-streaming-hazard-size=0 -pass-remarks-analysis=stack-frame-layout 2>&1 >/dev/null | FileCheck %s --check-prefixes=CHECK-FRAMELAYOUT
; CHECK-FRAMELAYOUT-LABEL: Function: csr_d8_allocnxv4i32i32f64
@@ -11,28 +10,28 @@
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-16 x vscale], Type: Variable, Align: 8, Size: 8
define i32 @csr_d8_allocnxv4i32i32f64(double %d) "aarch64_pstate_sm_compatible" {
-; CHECK-COMMON-LABEL: csr_d8_allocnxv4i32i32f64:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: str x29, [sp, #8] // 8-byte Spill
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: addvl sp, sp, #-1
-; CHECK-COMMON-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x20, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 32 + 8 * VG
-; CHECK-COMMON-NEXT: .cfi_offset w29, -8
-; CHECK-COMMON-NEXT: .cfi_offset b8, -16
-; CHECK-COMMON-NEXT: mov z1.s, #0 // =0x0
-; CHECK-COMMON-NEXT: add x8, sp, #16
-; CHECK-COMMON-NEXT: mov w0, wzr
-; CHECK-COMMON-NEXT: //APP
-; CHECK-COMMON-NEXT: //NO_APP
-; CHECK-COMMON-NEXT: str wzr, [sp, #12]
-; CHECK-COMMON-NEXT: str d0, [sp]
-; CHECK-COMMON-NEXT: str z1, [x8]
-; CHECK-COMMON-NEXT: addvl sp, sp, #1
-; CHECK-COMMON-NEXT: add sp, sp, #16
-; CHECK-COMMON-NEXT: ldr x29, [sp, #8] // 8-byte Reload
-; CHECK-COMMON-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: csr_d8_allocnxv4i32i32f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: str x29, [sp, #8] // 8-byte Spill
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x20, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 32 + 8 * VG
+; CHECK-NEXT: .cfi_offset w29, -8
+; CHECK-NEXT: .cfi_offset b8, -16
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: add x8, sp, #16
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: str wzr, [sp, #12]
+; CHECK-NEXT: str d0, [sp]
+; CHECK-NEXT: str z1, [x8]
+; CHECK-NEXT: addvl sp, sp, #1
+; CHECK-NEXT: add sp, sp, #16
+; CHECK-NEXT: ldr x29, [sp, #8] // 8-byte Reload
+; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
; CHECK-NE
entry:
%a = alloca <vscale x 4 x i32>
@@ -54,31 +53,31 @@ entry:
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-40-16 x vscale], Type: Variable, Align: 8, Size: 8
define i32 @csr_d8_allocnxv4i32i32f64_fp(double %d) "aarch64_pstate_sm_compatible" "frame-pointer"="all" {
-; CHECK-COMMON-LABEL: csr_d8_allocnxv4i32i32f64_fp:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #16] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: add x29, sp, #16
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: addvl sp, sp, #-1
-; CHECK-COMMON-NEXT: .cfi_def_cfa w29, 16
-; CHECK-COMMON-NEXT: .cfi_offset w30, -8
-; CHECK-COMMON-NEXT: .cfi_offset w29, -16
-; CHECK-COMMON-NEXT: .cfi_offset b8, -32
-; CHECK-COMMON-NEXT: mov z1.s, #0 // =0x0
-; CHECK-COMMON-NEXT: addvl x8, sp, #1
-; CHECK-COMMON-NEXT: //APP
-; CHECK-COMMON-NEXT: //NO_APP
-; CHECK-COMMON-NEXT: str wzr, [x8, #28]
-; CHECK-COMMON-NEXT: sub x8, x29, #16
-; CHECK-COMMON-NEXT: mov w0, wzr
-; CHECK-COMMON-NEXT: str d0, [sp, #8]
-; CHECK-COMMON-NEXT: str z1, [x8, #-1, mul vl]
-; CHECK-COMMON-NEXT: addvl sp, sp, #1
-; CHECK-COMMON-NEXT: add sp, sp, #16
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp, #16] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: csr_d8_allocnxv4i32i32f64_fp:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-NEXT: stp x29, x30, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: add x29, sp, #16
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: .cfi_offset b8, -32
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: addvl x8, sp, #1
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: str wzr, [x8, #28]
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: str d0, [sp, #8]
+; CHECK-NEXT: str z1, [x8, #-1, mul vl]
+; CHECK-NEXT: addvl sp, sp, #1
+; CHECK-NEXT: add sp, sp, #16
+; CHECK-NEXT: ldp x29, x30, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%a = alloca <vscale x 4 x i32>
%b = alloca i32
@@ -104,30 +103,30 @@ entry:
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-128-16 x vscale], Type: Variable, Align: 128, Size: 4
define i32 @csr_d8_allocnxv4i32i32f64_dynamicrealign(double %d) "aarch64_pstate_sm_compatible" {
-; CHECK-COMMON-LABEL: csr_d8_allocnxv4i32i32f64_dynamicrealign:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: sub x9, sp, #96
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #16] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: add x29, sp, #16
-; CHECK-COMMON-NEXT: addvl x9, x9, #-1
-; CHECK-COMMON-NEXT: and sp, x9, #0xffffffffffffff80
-; CHECK-COMMON-NEXT: .cfi_def_cfa w29, 16
-; CHECK-COMMON-NEXT: .cfi_offset w30, -8
-; CHECK-COMMON-NEXT: .cfi_offset w29, -16
-; CHECK-COMMON-NEXT: .cfi_offset b8, -32
-; CHECK-COMMON-NEXT: mov z1.s, #0 // =0x0
-; CHECK-COMMON-NEXT: sub x8, x29, #16
-; CHECK-COMMON-NEXT: mov w0, wzr
-; CHECK-COMMON-NEXT: //APP
-; CHECK-COMMON-NEXT: //NO_APP
-; CHECK-COMMON-NEXT: str wzr, [sp]
-; CHECK-COMMON-NEXT: stur d0, [x29, #-8]
-; CHECK-COMMON-NEXT: str z1, [x8, #-1, mul vl]
-; CHECK-COMMON-NEXT: sub sp, x29, #16
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp, #16] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: csr_d8_allocnxv4i32i32f64_dynamicrealign:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #96
+; CHECK-NEXT: stp x29, x30, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: add x29, sp, #16
+; CHECK-NEXT: addvl x9, x9, #-1
+; CHECK-NEXT: and sp, x9, #0xffffffffffffff80
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: .cfi_offset b8, -32
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: str wzr, [sp]
+; CHECK-NEXT: stur d0, [x29, #-8]
+; CHECK-NEXT: str z1, [x8, #-1, mul vl]
+; CHECK-NEXT: sub sp, x29, #16
+; CHECK-NEXT: ldp x29, x30, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%a = alloca <vscale x 4 x i32>
%b = alloca i32, align 128
@@ -153,44 +152,44 @@ entry:
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-48-16 x vscale], Type: VariableSized, Align: 1, Size: 0
define i32 @csr_d8_allocnxv4i32i32f64_vla(double %d, i32 %i) "aarch64_pstate_sm_compatible" {
-; CHECK-COMMON-LABEL: csr_d8_allocnxv4i32i32f64_vla:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #8] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: add x29, sp, #8
-; CHECK-COMMON-NEXT: str x19, [sp, #24] // 8-byte Spill
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: addvl sp, sp, #-1
-; CHECK-COMMON-NEXT: mov x19, sp
-; CHECK-COMMON-NEXT: .cfi_def_cfa w29, 24
-; CHECK-COMMON-NEXT: .cfi_offset w19, -8
-; CHECK-COMMON-NEXT: .cfi_offset w30, -16
-; CHECK-COMMON-NEXT: .cfi_offset w29, -24
-; CHECK-COMMON-NEXT: .cfi_offset b8, -32
-; CHECK-COMMON-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-COMMON-NEXT: ubfiz x8, x0, #2, #32
-; CHECK-COMMON-NEXT: mov x9, sp
-; CHECK-COMMON-NEXT: add x8, x8, #15
-; CHECK-COMMON-NEXT: and x8, x8, #0x7fffffff0
-; CHECK-COMMON-NEXT: sub x9, x9, x8
-; CHECK-COMMON-NEXT: mov sp, x9
-; CHECK-COMMON-NEXT: mov x10, sp
-; CHECK-COMMON-NEXT: sub x8, x10, x8
-; CHECK-COMMON-NEXT: mov sp, x8
-; CHECK-COMMON-NEXT: mov z1.s, #0 // =0x0
-; CHECK-COMMON-NEXT: //APP
-; CHECK-COMMON-NEXT: //NO_APP
-; CHECK-COMMON-NEXT: str wzr, [x8]
-; CHECK-COMMON-NEXT: sub x8, x29, #8
-; CHECK-COMMON-NEXT: mov w0, wzr
-; CHECK-COMMON-NEXT: str wzr, [x9]
-; CHECK-COMMON-NEXT: str d0, [x19, #8]
-; CHECK-COMMON-NEXT: str z1, [x8, #-1, mul vl]
-; CHECK-COMMON-NEXT: sub sp, x29, #8
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp, #8] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr x19, [sp, #24] // 8-byte Reload
-; CHECK-COMMON-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: csr_d8_allocnxv4i32i32f64_vla:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-NEXT: stp x29, x30, [sp, #8] // 16-byte Folded Spill
+; CHECK-NEXT: add x29, sp, #8
+; CHECK-NEXT: str x19, [sp, #24] // 8-byte Spill
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: mov x19, sp
+; CHECK-NEXT: .cfi_def_cfa w29, 24
+; CHECK-NEXT: .cfi_offset w19, -8
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: .cfi_offset w29, -24
+; CHECK-NEXT: .cfi_offset b8, -32
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: ubfiz x8, x0, #2, #32
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x8, x8, #15
+; CHECK-NEXT: and x8, x8, #0x7fffffff0
+; CHECK-NEXT: sub x9, x9, x8
+; CHECK-NEXT: mov sp, x9
+; CHECK-NEXT: mov x10, sp
+; CHECK-NEXT: sub x8, x10, x8
+; CHECK-NEXT: mov sp, x8
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: str wzr, [x8]
+; CHECK-NEXT: sub x8, x29, #8
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: str wzr, [x9]
+; CHECK-NEXT: str d0, [x19, #8]
+; CHECK-NEXT: str z1, [x8, #-1, mul vl]
+; CHECK-NEXT: sub sp, x29, #8
+; CHECK-NEXT: ldp x29, x30, [sp, #8] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x19, [sp, #24] // 8-byte Reload
+; CHECK-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%a = alloca <vscale x 4 x i32>
%0 = zext i32 %i to i64
@@ -215,28 +214,28 @@ entry:
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-16 x vscale], Type: Variable, Align: 8, Size: 8
define i32 @csr_d8_allocnxv4i32i32f64_stackargsi32f64(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) "aarch64_pstate_sm_compatible" {
-; CHECK-COMMON-LABEL: csr_d8_allocnxv4i32i32f64_stackargsi32f64:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-COMMON-NEXT: str x29, [sp, #8] // 8-byte Spill
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: addvl sp, sp, #-1
-; CHECK-COMMON-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x20, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 32 + 8 * VG
-; CHECK-COMMON-NEXT: .cfi_offset w29, -8
-; CHECK-COMMON-NEXT: .cfi_offset b8, -16
-; CHECK-COMMON-NEXT: mov z1.s, #0 // =0x0
-; CHECK-COMMON-NEXT: add x8, sp, #16
-; CHECK-COMMON-NEXT: mov w0, wzr
-; CHECK-COMMON-NEXT: //APP
-; CHECK-COMMON-NEXT: //NO_APP
-; CHECK-COMMON-NEXT: str wzr, [sp, #12]
-; CHECK-COMMON-NEXT: str d0, [sp]
-; CHECK-COMMON-NEXT: str z1, [x8]
-; CHECK-COMMON-NEXT: addvl sp, sp, #1
-; CHECK-COMMON-NEXT: add sp, sp, #16
-; CHECK-COMMON-NEXT: ldr x29, [sp, #8] // 8-byte Reload
-; CHECK-COMMON-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: csr_d8_allocnxv4i32i32f64_stackargsi32f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: str x29, [sp, #8] // 8-byte Spill
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x20, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 32 + 8 * VG
+; CHECK-NEXT: .cfi_offset w29, -8
+; CHECK-NEXT: .cfi_offset b8, -16
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: add x8, sp, #16
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: str wzr, [sp, #12]
+; CHECK-NEXT: str d0, [sp]
+; CHECK-NEXT: str z1, [x8]
+; CHECK-NEXT: addvl sp, sp, #1
+; CHECK-NEXT: add sp, sp, #16
+; CHECK-NEXT: ldr x29, [sp, #8] // 8-byte Reload
+; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%a = alloca <vscale x 4 x i32>
%b = alloca i32
@@ -257,29 +256,29 @@ entry:
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-32 x vscale], Type: Variable, Align: 8, Size: 8
define i32 @svecc_z8_allocnxv4i32i32f64_fp(double %d, <vscale x 4 x i32> %v) "aarch64_pstate_sm_compatible" "frame-pointer"="all" {
-; CHECK-COMMON-LABEL: svecc_z8_allocnxv4i32i32f64_fp:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: addvl sp, sp, #-1
-; CHECK-COMMON-NEXT: str z8, [sp] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: addvl sp, sp, #-1
-; CHECK-COMMON-NEXT: .cfi_def_cfa w29, 16
-; CHECK-COMMON-NEXT: .cfi_offset w30, -8
-; CHECK-COMMON-NEXT: .cfi_offset w29, -16
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-COMMON-NEXT: mov w0, wzr
-; CHECK-COMMON-NEXT: //APP
-; CHECK-COMMON-NEXT: //NO_APP
-; CHECK-COMMON-NEXT: str wzr, [sp, #12]
-; CHECK-COMMON-NEXT: str z1, [x29, #-2, mul vl]
-; CHECK-COMMON-NEXT: str d0, [sp], #16
-; CHECK-COMMON-NEXT: addvl sp, sp, #1
-; CHECK-COMMON-NEXT: ldr z8, [sp] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: addvl sp, sp, #1
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: svecc_z8_allocnxv4i32i32f64_fp:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: str z8, [sp] // 16-byte Folded Spill
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: str wzr, [sp, #12]
+; CHECK-NEXT: str z1, [x29, #-2, mul vl]
+; CHECK-NEXT: str d0, [sp], #16
+; CHECK-NEXT: addvl sp, sp, #1
+; CHECK-NEXT: ldr z8, [sp] // 16-byte Folded Reload
+; CHECK-NEXT: addvl sp, sp, #1
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%a = alloca <vscale x 4 x i32>
%b = alloca i32
@@ -301,29 +300,29 @@ entry:
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-32 x vscale], Type: Variable, Align: 8, Size: 8
define i32 @svecc_z8_allocnxv4i32i32f64_stackargsi32_fp(double %d, i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, <vscale x 4 x i32> %v) "aarch64_pstate_sm_compatible" "frame-pointer"="all"{
-; CHECK-COMMON-LABEL: svecc_z8_allocnxv4i32i32f64_stackargsi32_fp:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: addvl sp, sp, #-1
-; CHECK-COMMON-NEXT: str z8, [sp] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: sub sp, sp, #16
-; CHECK-COMMON-NEXT: addvl sp, sp, #-1
-; CHECK-COMMON-NEXT: .cfi_def_cfa w29, 16
-; CHECK-COMMON-NEXT: .cfi_offset w30, -8
-; CHECK-COMMON-NEXT: .cfi_offset w29, -16
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-COMMON-NEXT: mov w0, wzr
-; CHECK-COMMON-NEXT: //APP
-; CHECK-COMMON-NEXT: //NO_APP
-; CHECK-COMMON-NEXT: str wzr, [sp, #12]
-; CHECK-COMMON-NEXT: str z1, [x29, #-2, mul vl]
-; CHECK-COMMON-NEXT: str d0, [sp], #16
-; CHECK-COMMON-NEXT: addvl sp, sp, #1
-; CHECK-COMMON-NEXT: ldr z8, [sp] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: addvl sp, sp, #1
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: svecc_z8_allocnxv4i32i32f64_stackargsi32_fp:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: str z8, [sp] // 16-byte Folded Spill
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: str wzr, [sp, #12]
+; CHECK-NEXT: str z1, [x29, #-2, mul vl]
+; CHECK-NEXT: str d0, [sp], #16
+; CHECK-NEXT: addvl sp, sp, #1
+; CHECK-NEXT: ldr z8, [sp] // 16-byte Folded Reload
+; CHECK-NEXT: addvl sp, sp, #1
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%a = alloca <vscale x 4 x i32>
%b = alloca i32
@@ -373,129 +372,129 @@ entry:
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-280 x vscale], Type: Spill, Align: 2, Size: vscale x 2
define i32 @svecc_call(<4 x i16> %P0, ptr %P1, i32 %P2, <vscale x 16 x i8> %P3, i16 %P4) "aarch64_pstate_sm_compatible" {
-; CHECK-COMMON-LABEL: svecc_call:
-; CHECK-COMMON: // %bb.0: // %entry
-; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-64]! // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: .cfi_def_cfa_offset 64
-; CHECK-COMMON-NEXT: cntd x9
-; CHECK-COMMON-NEXT: stp x28, x27, [sp, #32] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str x9, [sp, #16] // 8-byte Spill
-; CHECK-COMMON-NEXT: stp x26, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: mov x29, sp
-; CHECK-COMMON-NEXT: .cfi_def_cfa w29, 64
-; CHECK-COMMON-NEXT: .cfi_offset w19, -8
-; CHECK-COMMON-NEXT: .cfi_offset w26, -16
-; CHECK-COMMON-NEXT: .cfi_offset w27, -24
-; CHECK-COMMON-NEXT: .cfi_offset w28, -32
-; CHECK-COMMON-NEXT: .cfi_offset vg, -48
-; CHECK-COMMON-NEXT: .cfi_offset w30, -56
-; CHECK-COMMON-NEXT: .cfi_offset w29, -64
-; CHECK-COMMON-NEXT: addvl sp, sp, #-18
-; CHECK-COMMON-NEXT: str p15, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p14, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p13, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-COMMON-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x48, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x78, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d8 @ cfa - 8 * IncomingVG - 64
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x49, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x70, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d9 @ cfa - 16 * IncomingVG - 64
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x4a, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x68, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d10 @ cfa - 24 * IncomingVG - 64
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x4b, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x60, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d11 @ cfa - 32 * IncomingVG - 64
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x4c, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x58, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d12 @ cfa - 40 * IncomingVG - 64
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x4d, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x50, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d13 @ cfa - 48 * IncomingVG - 64
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x4e, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x48, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d14 @ cfa - 56 * IncomingVG - 64
-; CHECK-COMMON-NEXT: .cfi_escape 0x10, 0x4f, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x40, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d15 @ cfa - 64 * IncomingVG - 64
-; CHECK-COMMON-NEXT: mov x8, x0
-; CHECK-COMMON-NEXT: bl __arm_sme_state
-; CHECK-COMMON-NEXT: mov x19, x0
-; CHECK-COMMON-NEXT: //APP
-; CHECK-COMMON-NEXT: //NO_APP
-; CHECK-COMMON-NEXT: tbz w19, #0, .LBB7_2
-; CHECK-COMMON-NEXT: // %bb.1: // %entry
-; CHECK-COMMON-NEXT: smstop sm
-; CHECK-COMMON-NEXT: .LBB7_2: // %entry
-; CHECK-COMMON-NEXT: mov x0, x8
-; CHECK-COMMON-NEXT: mov w1, #45 // =0x2d
-; CHECK-COMMON-NEXT: mov w2, #37 // =0x25
-; CHECK-COMMON-NEXT: bl memset
-; CHECK-COMMON-NEXT: tbz w19, #0, .LBB7_4
-; CHECK-COMMON-NEXT: // %bb.3: // %entry
-; CHECK-COMMON-NEXT: smstart sm
-; CHECK-COMMON-NEXT: .LBB7_4: // %entry
-; CHECK-COMMON-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: mov w0, #22647 // =0x5877
-; CHECK-COMMON-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: movk w0, #59491, lsl #16
-; CHECK-COMMON-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-COMMON-NEXT: addvl sp, sp, #18
-; CHECK-COMMON-NEXT: .cfi_restore z8
-; CHECK-COMMON-NEXT: .cfi_restore z9
-; CHECK-COMMON-NEXT: .cfi_restore z10
-; CHECK-COMMON-NEXT: .cfi_restore z11
-; CHECK-COMMON-NEXT: .cfi_restore z12
-; CHECK-COMMON-NEXT: .cfi_restore z13
-; CHECK-COMMON-NEXT: .cfi_restore z14
-; CHECK-COMMON-NEXT: .cfi_restore z15
-; CHECK-COMMON-NEXT: .cfi_def_cfa wsp, 64
-; CHECK-COMMON-NEXT: ldp x26, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldp x28, x27, [sp, #32] // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #64 // 16-byte Folded Reload
-; CHECK-COMMON-NEXT: .cfi_def_cfa_offset 0
-; CHECK-COMMON-NEXT: .cfi_restore w19
-; CHECK-COMMON-NEXT: .cfi_restore w26
-; CHECK-COMMON-NEXT: .cfi_restore w27
-; CHECK-COMMON-NEXT: .cfi_restore w28
-; CHECK-COMMON-NEXT: .cfi_restore vg
-; CHECK-COMMON-NEXT: .cfi_restore w30
-; CHECK-COMMON-NEXT: .cfi_restore w29
-; CHECK-COMMON-NEXT: ret
+; CHECK-LABEL: svecc_call:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-64]! // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 64
+; CHECK-NEXT: cntd x9
+; CHECK-NEXT: stp x28, x27, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: str x9, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: stp x26, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: .cfi_def_cfa w29, 64
+; CHECK-NEXT: .cfi_offset w19, -8
+; CHECK-NEXT: .cfi_offset w26, -16
+; CHECK-NEXT: .cfi_offset w27, -24
+; CHECK-NEXT: .cfi_offset w28, -32
+; CHECK-NEXT: .cfi_offset vg, -48
+; CHECK-NEXT: .cfi_offset w30, -56
+; CHECK-NEXT: .cfi_offset w29, -64
+; CHECK-NEXT: addvl sp, sp, #-18
+; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
+; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
+; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x78, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d8 @ cfa - 8 * IncomingVG - 64
+; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x70, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d9 @ cfa - 16 * IncomingVG - 64
+; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x68, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d10 @ cfa - 24 * IncomingVG - 64
+; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x60, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d11 @ cfa - 32 * IncomingVG - 64
+; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x58, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d12 @ cfa - 40 * IncomingVG - 64
+; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x50, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d13 @ cfa - 48 * IncomingVG - 64
+; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x48, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d14 @ cfa - 56 * IncomingVG - 64
+; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0c, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x40, 0x1e, 0x22, 0x11, 0x40, 0x22 // $d15 @ cfa - 64 * IncomingVG - 64
+; CHECK-NEXT: mov x8, x0
+; CHECK-NEXT: bl __arm_sme_state
+; CHECK-NEXT: mov x19, x0
+; CHECK-NEXT: //APP
+; CHECK-NEXT: //NO_APP
+; CHECK-NEXT: tbz w19, #0, .LBB7_2
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: smstop sm
+; CHECK-NEXT: .LBB7_2: // %entry
+; CHECK-NEXT: mov x0, x8
+; CHECK-NEXT: mov w1, #45 // =0x2d
+; CHECK-NEXT: mov w2, #37 // =0x25
+; CHECK-NEXT: bl memset
+; CHECK-NEXT: tbz w19, #0, .LBB7_4
+; CHECK-NEXT: // %bb.3: // %entry
+; CHECK-NEXT: smstart sm
+; CHECK-NEXT: .LBB7_4: // %entry
+; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: mov w0, #22647 // =0x5877
+; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: movk w0, #59491, lsl #16
+; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
+; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
+; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
+; CHECK-NEXT: addvl sp, sp, #18
+; CHECK-NEXT: .cfi_restore z8
+; CHECK-NEXT: .cfi_restore z9
+; CHECK-NEXT: .cfi_restore z10
+; CHECK-NEXT: .cfi_restore z11
+; CHECK-NEXT: .cfi_restore z12
+; CHECK-NEXT: .cfi_restore z13
+; CHECK-NEXT: .cfi_restore z14
+; CHECK-NEXT: .cfi_restore z15
+; CHECK-NEXT: .cfi_def_cfa wsp, 64
+; CHECK-NEXT: ldp x26, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x28, x27, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #64 // 16-byte Folded Reload
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: .cfi_restore w19
+; CHECK-NEXT: .cfi_restore w26
+; CHECK-NEXT: .cfi_restore w27
+; CHECK-NEXT: .cfi_restore w28
+; CHECK-NEXT: .cfi_restore vg
+; CHECK-NEXT: .cfi_restore w30
+; CHECK-NEXT: .cfi_restore w29
+; CHECK-NEXT: ret
entry:
tail call void asm sideeffect "", "~{x0},~{x28},~{x27},~{x3}"() #2
%call = call ptr @memset(ptr noundef nonnull %P1, i32 noundef 45, i32 noundef 37)
@@ -524,77 +523,6 @@ declare ptr @memset(ptr, i32, i32)
; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-128], Type: VariableSized, Align: 16, Size: 0
define i32 @vastate(i32 %x) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "target-features"="+sme" {
-; CHECK-SDAG-LABEL: vastate:
-; CHECK-SDAG: // %bb.0: // %entry
-; CHECK-SDAG-NEXT: stp d15, d14, [sp, #-112]! // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 112
-; CHECK-SDAG-NEXT: cntd x9
-; CHECK-SDAG-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: stp x29, x30, [sp, #64] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: str x9, [sp, #80] // 8-byte Spill
-; CHECK-SDAG-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-SDAG-NEXT: add x29, sp, #64
-; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 48
-; CHECK-SDAG-NEXT: .cfi_offset w19, -8
-; CHECK-SDAG-NEXT: .cfi_offset w20, -16
-; CHECK-SDAG-NEXT: .cfi_offset vg, -32
-; CHECK-SDAG-NEXT: .cfi_offset w30, -40
-; CHECK-SDAG-NEXT: .cfi_offset w29, -48
-; CHECK-SDAG-NEXT: .cfi_offset b8, -56
-; CHECK-SDAG-NEXT: .cfi_offset b9, -64
-; CHECK-SDAG-NEXT: .cfi_offset b10, -72
-; CHECK-SDAG-NEXT: .cfi_offset b11, -80
-; CHECK-SDAG-NEXT: .cfi_offset b12, -88
-; CHECK-SDAG-NEXT: .cfi_offset b13, -96
-; CHECK-SDAG-NEXT: .cfi_offset b14, -104
-; CHECK-SDAG-NEXT: .cfi_offset b15, -112
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: rdsvl x8, #1
-; CHECK-SDAG-NEXT: mov x9, sp
-; CHECK-SDAG-NEXT: mov w20, w0
-; CHECK-SDAG-NEXT: msub x9, x8, x8, x9
-; CHECK-SDAG-NEXT: mov sp, x9
-; CHECK-SDAG-NEXT: sub x10, x29, #80
-; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-80]
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x10
-; CHECK-SDAG-NEXT: smstop sm
-; CHECK-SDAG-NEXT: bl other
-; CHECK-SDAG-NEXT: smstart sm
-; CHECK-SDAG-NEXT: smstart za
-; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0
-; CHECK-SDAG-NEXT: sub x0, x29, #80
-; CHECK-SDAG-NEXT: cbnz x8, .LBB8_2
-; CHECK-SDAG-NEXT: // %bb.1: // %entry
-; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore
-; CHECK-SDAG-NEXT: .LBB8_2: // %entry
-; CHECK-SDAG-NEXT: mov w0, w20
-; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-SDAG-NEXT: sub sp, x29, #64
-; CHECK-SDAG-NEXT: .cfi_def_cfa wsp, 112
-; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp x29, x30, [sp, #64] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: ldp d15, d14, [sp], #112 // 16-byte Folded Reload
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 0
-; CHECK-SDAG-NEXT: .cfi_restore w19
-; CHECK-SDAG-NEXT: .cfi_restore w20
-; CHECK-SDAG-NEXT: .cfi_restore vg
-; CHECK-SDAG-NEXT: .cfi_restore w30
-; CHECK-SDAG-NEXT: .cfi_restore w29
-; CHECK-SDAG-NEXT: .cfi_restore b8
-; CHECK-SDAG-NEXT: .cfi_restore b9
-; CHECK-SDAG-NEXT: .cfi_restore b10
-; CHECK-SDAG-NEXT: .cfi_restore b11
-; CHECK-SDAG-NEXT: .cfi_restore b12
-; CHECK-SDAG-NEXT: .cfi_restore b13
-; CHECK-SDAG-NEXT: .cfi_restore b14
-; CHECK-SDAG-NEXT: .cfi_restore b15
-; CHECK-SDAG-NEXT: ret
-;
; CHECK-LABEL: vastate:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp d15, d14, [sp, #-112]! // 16-byte Folded Spill
diff --git a/llvm/test/Verifier/sme-attributes.ll b/llvm/test/Verifier/sme-attributes.ll
index 0ae2b9fd91f52..4bf5e813daf2f 100644
--- a/llvm/test/Verifier/sme-attributes.ll
+++ b/llvm/test/Verifier/sme-attributes.ll
@@ -68,6 +68,3 @@ declare void @zt0_inout_out() "aarch64_inout_zt0" "aarch64_out_zt0";
declare void @zt0_inout_agnostic() "aarch64_inout_zt0" "aarch64_za_state_agnostic";
; CHECK: Attributes 'aarch64_new_zt0', 'aarch64_in_zt0', 'aarch64_out_zt0', 'aarch64_inout_zt0', 'aarch64_preserves_zt0' and 'aarch64_za_state_agnostic' are mutually exclusive
-
-declare void @zt0_undef_function() "aarch64_zt0_undef";
-; CHECK: Attribute 'aarch64_zt0_undef' can only be applied to a callsite.
diff --git a/llvm/unittests/Target/AArch64/SMEAttributesTest.cpp b/llvm/unittests/Target/AArch64/SMEAttributesTest.cpp
index 595dcd2f4dcc5..f628755c4426f 100644
--- a/llvm/unittests/Target/AArch64/SMEAttributesTest.cpp
+++ b/llvm/unittests/Target/AArch64/SMEAttributesTest.cpp
@@ -72,14 +72,6 @@ TEST(SMEAttributes, Constructors) {
->getFunction("foo"))
.isNewZT0());
- auto CallModule = parseIR("declare void @callee()\n"
- "define void @foo() {"
- "call void @callee() \"aarch64_zt0_undef\"\n"
- "ret void\n}");
- CallBase &Call =
- cast<CallBase>((CallModule->getFunction("foo")->begin()->front()));
- ASSERT_TRUE(SMECallAttrs(Call, nullptr).callsite().hasUndefZT0());
-
// Invalid combinations.
EXPECT_DEBUG_DEATH(SA(SA::SM_Enabled | SA::SM_Compatible),
"SM_Enabled and SM_Compatible are mutually exclusive");
@@ -225,18 +217,6 @@ TEST(SMEAttributes, Basics) {
ASSERT_FALSE(ZT0_New.hasSharedZAInterface());
ASSERT_TRUE(ZT0_New.hasPrivateZAInterface());
- SA ZT0_Undef = SA(SA::ZT0_Undef | SA::encodeZT0State(SA::StateValue::New));
- ASSERT_TRUE(ZT0_Undef.isNewZT0());
- ASSERT_FALSE(ZT0_Undef.isInZT0());
- ASSERT_FALSE(ZT0_Undef.isOutZT0());
- ASSERT_FALSE(ZT0_Undef.isInOutZT0());
- ASSERT_FALSE(ZT0_Undef.isPreservesZT0());
- ASSERT_FALSE(ZT0_Undef.sharesZT0());
- ASSERT_TRUE(ZT0_Undef.hasZT0State());
- ASSERT_FALSE(ZT0_Undef.hasSharedZAInterface());
- ASSERT_TRUE(ZT0_Undef.hasPrivateZAInterface());
- ASSERT_TRUE(ZT0_Undef.hasUndefZT0());
-
ASSERT_FALSE(SA(SA::Normal).isInZT0());
ASSERT_FALSE(SA(SA::Normal).isOutZT0());
ASSERT_FALSE(SA(SA::Normal).isInOutZT0());
@@ -305,7 +285,6 @@ TEST(SMEAttributes, Transitions) {
SA ZT0_Shared = SA(SA::encodeZT0State(SA::StateValue::In));
SA ZA_ZT0_Shared = SA(SA::encodeZAState(SA::StateValue::In) |
SA::encodeZT0State(SA::StateValue::In));
- SA Undef_ZT0 = SA(SA::ZT0_Undef);
// Shared ZA -> Private ZA Interface
ASSERT_FALSE(CA(ZA_Shared, Private_ZA).requiresDisablingZABeforeCall());
@@ -316,15 +295,6 @@ TEST(SMEAttributes, Transitions) {
ASSERT_TRUE(CA(ZT0_Shared, Private_ZA).requiresPreservingZT0());
ASSERT_TRUE(CA(ZT0_Shared, Private_ZA).requiresEnablingZAAfterCall());
- // Shared Undef ZT0 -> Private ZA Interface
- // Note: "Undef ZT0" is a callsite attribute that means ZT0 is undefined at
- // point the of the call.
- ASSERT_TRUE(
- CA(ZT0_Shared, Private_ZA, Undef_ZT0).requiresDisablingZABeforeCall());
- ASSERT_FALSE(CA(ZT0_Shared, Private_ZA, Undef_ZT0).requiresPreservingZT0());
- ASSERT_TRUE(
- CA(ZT0_Shared, Private_ZA, Undef_ZT0).requiresEnablingZAAfterCall());
-
// Shared ZA & ZT0 -> Private ZA Interface
ASSERT_FALSE(CA(ZA_ZT0_Shared, Private_ZA).requiresDisablingZABeforeCall());
ASSERT_TRUE(CA(ZA_ZT0_Shared, Private_ZA).requiresPreservingZT0());
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
index a7e0eeb3e7d3c..0787cee98d464 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
@@ -181,7 +181,6 @@ static_library("LLVMAArch64CodeGen") {
"GISel/AArch64PreLegalizerCombiner.cpp",
"GISel/AArch64RegisterBankInfo.cpp",
"MachineSMEABIPass.cpp",
- "SMEABIPass.cpp",
"SMEPeepholeOpt.cpp",
"SVEIntrinsicOpts.cpp",
]
>From f9793013662a11d39e69469b196358f8adf4235e Mon Sep 17 00:00:00 2001
From: Zorojuro <sawantsukumar at gmail.com>
Date: Mon, 13 Apr 2026 14:27:16 +0530
Subject: [PATCH 27/36] [libc][math] Fix: add log2p1f16 to shared math
(#189179)
This PR intends to add the log2p1f16 function to shared math, along with
adding tests for it and bazel which was missed in
[f0ce26d](https://github.com/llvm/llvm-project/commit/f0ce26d06d822fd6985d227dc1be9d218977e334).
---
libc/shared/math.h | 1 +
libc/shared/math/log2p1f16.h | 29 +++++++++++++++++++
libc/test/shared/CMakeLists.txt | 1 +
libc/test/shared/shared_math_test.cpp | 1 +
.../llvm-project-overlay/libc/BUILD.bazel | 28 ++++++++++++++++++
5 files changed, 60 insertions(+)
create mode 100644 libc/shared/math/log2p1f16.h
diff --git a/libc/shared/math.h b/libc/shared/math.h
index 12a3e2cc546ba..0c126ae9ebff7 100644
--- a/libc/shared/math.h
+++ b/libc/shared/math.h
@@ -193,6 +193,7 @@
#include "math/log2.h"
#include "math/log2f.h"
#include "math/log2f16.h"
+#include "math/log2p1f16.h"
#include "math/log_bf16.h"
#include "math/logb.h"
#include "math/logbf.h"
diff --git a/libc/shared/math/log2p1f16.h b/libc/shared/math/log2p1f16.h
new file mode 100644
index 0000000000000..b5ad3fe45e1dd
--- /dev/null
+++ b/libc/shared/math/log2p1f16.h
@@ -0,0 +1,29 @@
+//===-- Shared log2p1f16 function -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SHARED_MATH_LOG2P1F16_H
+#define LLVM_LIBC_SHARED_MATH_LOG2P1F16_H
+
+#include "include/llvm-libc-macros/float16-macros.h"
+
+#ifdef LIBC_TYPES_HAS_FLOAT16
+
+#include "shared/libc_common.h"
+#include "src/__support/math/log2p1f16.h"
+
+namespace LIBC_NAMESPACE_DECL {
+namespace shared {
+
+using math::log2p1f16;
+
+} // namespace shared
+} // namespace LIBC_NAMESPACE_DECL
+
+#endif // LIBC_TYPES_HAS_FLOAT16
+
+#endif // LLVM_LIBC_SHARED_MATH_LOG2P1F16_H
diff --git a/libc/test/shared/CMakeLists.txt b/libc/test/shared/CMakeLists.txt
index 829a92be0019e..6494ceca5e90f 100644
--- a/libc/test/shared/CMakeLists.txt
+++ b/libc/test/shared/CMakeLists.txt
@@ -185,6 +185,7 @@ add_fp_unittest(
libc.src.__support.math.logb
libc.src.__support.math.log2f
libc.src.__support.math.log2f16
+ libc.src.__support.math.log2p1f16
libc.src.__support.math.logbf
libc.src.__support.math.logbf128
libc.src.__support.math.logbf16
diff --git a/libc/test/shared/shared_math_test.cpp b/libc/test/shared/shared_math_test.cpp
index 8a60bdcbad095..dedf9923fdd88 100644
--- a/libc/test/shared/shared_math_test.cpp
+++ b/libc/test/shared/shared_math_test.cpp
@@ -55,6 +55,7 @@ TEST(LlvmLibcSharedMathTest, AllFloat16) {
EXPECT_EQ(0, LIBC_NAMESPACE::shared::ilogbf16(1.0f16));
EXPECT_FP_EQ(1.0f16, LIBC_NAMESPACE::shared::log10f16(10.0f16));
EXPECT_FP_EQ(1.0f16, LIBC_NAMESPACE::shared::log2f16(2.0f16));
+ EXPECT_FP_EQ(1.0f16, LIBC_NAMESPACE::shared::log2p1f16(1.0f16));
EXPECT_FP_EQ(0.0f16, LIBC_NAMESPACE::shared::logbf16(1.0f16));
EXPECT_EQ(0L, LIBC_NAMESPACE::shared::llogbf16(1.0f16));
diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
index 692f4ebbca32b..fe0db7d76af70 100644
--- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
@@ -5293,6 +5293,27 @@ libc_support_library(
],
)
+libc_support_library(
+ name = "__support_math_log2p1f16",
+ hdrs = ["src/__support/math/log2p1f16.h"],
+ deps = [
+ ":__support_common",
+ ":__support_fputil_cast",
+ ":__support_fputil_except_value_utils",
+ ":__support_fputil_fenv_impl",
+ ":__support_fputil_fp_bits",
+ ":__support_fputil_multiply_add",
+ ":__support_fputil_poly_eval",
+ ":__support_macros_config",
+ ":__support_macros_optimization",
+ ":__support_macros_properties_cpu_features",
+ ":__support_math_expxf16_utils",
+ ":hdr_errno_macros",
+ ":hdr_fenv_macros",
+ ":llvm_libc_macros_float16_macros",
+ ],
+)
+
libc_support_library(
name = "__support_math_log2f",
hdrs = ["src/__support/math/log2f.h"],
@@ -8017,6 +8038,13 @@ libc_math_function(
],
)
+libc_math_function(
+ name = "log2p1f16",
+ additional_deps = [
+ ":__support_math_log2p1f16",
+ ],
+)
+
libc_math_function(
name = "logb",
additional_deps = [
>From a062785f9c0b5702c7c3cdf30bee41bd02d8f828 Mon Sep 17 00:00:00 2001
From: Zorojuro <sawantsukumar at gmail.com>
Date: Mon, 13 Apr 2026 14:30:03 +0530
Subject: [PATCH 28/36] [libc][math] Fix: add log10p1f16 to shared math
(#189185)
This PR intends to add the log10p1f16 function to shared math, along
with adding tests for it and Bazel which was missed in
[a7d1a87](https://github.com/llvm/llvm-project/commit/a7d1a87b30ce626678d33fe1c12e647f7ce4fb20).
---
libc/shared/math.h | 1 +
libc/shared/math/log10p1f16.h | 29 +++++++++++++++++++
libc/test/shared/CMakeLists.txt | 1 +
libc/test/shared/shared_math_test.cpp | 1 +
.../llvm-project-overlay/libc/BUILD.bazel | 29 +++++++++++++++++++
5 files changed, 61 insertions(+)
create mode 100644 libc/shared/math/log10p1f16.h
diff --git a/libc/shared/math.h b/libc/shared/math.h
index 0c126ae9ebff7..275b89db3179a 100644
--- a/libc/shared/math.h
+++ b/libc/shared/math.h
@@ -188,6 +188,7 @@
#include "math/log10.h"
#include "math/log10f.h"
#include "math/log10f16.h"
+#include "math/log10p1f16.h"
#include "math/log1p.h"
#include "math/log1pf.h"
#include "math/log2.h"
diff --git a/libc/shared/math/log10p1f16.h b/libc/shared/math/log10p1f16.h
new file mode 100644
index 0000000000000..db1ee4cd699ff
--- /dev/null
+++ b/libc/shared/math/log10p1f16.h
@@ -0,0 +1,29 @@
+//===-- Shared log10p1f16 function ------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SHARED_MATH_LOG10P1F16_H
+#define LLVM_LIBC_SHARED_MATH_LOG10P1F16_H
+
+#include "include/llvm-libc-macros/float16-macros.h"
+
+#ifdef LIBC_TYPES_HAS_FLOAT16
+
+#include "shared/libc_common.h"
+#include "src/__support/math/log10p1f16.h"
+
+namespace LIBC_NAMESPACE_DECL {
+namespace shared {
+
+using math::log10p1f16;
+
+} // namespace shared
+} // namespace LIBC_NAMESPACE_DECL
+
+#endif // LIBC_TYPES_HAS_FLOAT16
+
+#endif // LLVM_LIBC_SHARED_MATH_LOG10P1F16_H
diff --git a/libc/test/shared/CMakeLists.txt b/libc/test/shared/CMakeLists.txt
index 6494ceca5e90f..9c4b7edb377e2 100644
--- a/libc/test/shared/CMakeLists.txt
+++ b/libc/test/shared/CMakeLists.txt
@@ -178,6 +178,7 @@ add_fp_unittest(
libc.src.__support.math.log
libc.src.__support.math.log10
libc.src.__support.math.log10f16
+ libc.src.__support.math.log10p1f16
libc.src.__support.math.log10f
libc.src.__support.math.log1p
libc.src.__support.math.log1pf
diff --git a/libc/test/shared/shared_math_test.cpp b/libc/test/shared/shared_math_test.cpp
index dedf9923fdd88..4c58c834960ed 100644
--- a/libc/test/shared/shared_math_test.cpp
+++ b/libc/test/shared/shared_math_test.cpp
@@ -54,6 +54,7 @@ TEST(LlvmLibcSharedMathTest, AllFloat16) {
EXPECT_EQ(0, LIBC_NAMESPACE::shared::ilogbf16(1.0f16));
EXPECT_FP_EQ(1.0f16, LIBC_NAMESPACE::shared::log10f16(10.0f16));
+ EXPECT_FP_EQ(1.0f16, LIBC_NAMESPACE::shared::log10p1f16(9.0f16));
EXPECT_FP_EQ(1.0f16, LIBC_NAMESPACE::shared::log2f16(2.0f16));
EXPECT_FP_EQ(1.0f16, LIBC_NAMESPACE::shared::log2p1f16(1.0f16));
EXPECT_FP_EQ(0.0f16, LIBC_NAMESPACE::shared::logbf16(1.0f16));
diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
index fe0db7d76af70..3f56367efff51 100644
--- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
@@ -5254,6 +5254,28 @@ libc_support_library(
],
)
+libc_support_library(
+ name = "__support_math_log10p1f16",
+ hdrs = ["src/__support/math/log10p1f16.h"],
+ deps = [
+ ":__support_common",
+ ":__support_fputil_cast",
+ ":__support_fputil_except_value_utils",
+ ":__support_fputil_fenv_impl",
+ ":__support_fputil_fp_bits",
+ ":__support_fputil_multiply_add",
+ ":__support_fputil_poly_eval",
+ ":__support_macros_config",
+ ":__support_macros_optimization",
+ ":__support_macros_properties_cpu_features",
+ ":__support_math_exp10_float16_constants",
+ ":__support_math_expxf16_utils",
+ ":hdr_errno_macros",
+ ":hdr_fenv_macros",
+ ":llvm_libc_macros_float16_macros",
+ ],
+)
+
libc_support_library(
name = "__support_math_log10f",
hdrs = ["src/__support/math/log10f.h"],
@@ -8007,6 +8029,13 @@ libc_math_function(
],
)
+libc_math_function(
+ name = "log10p1f16",
+ additional_deps = [
+ ":__support_math_log10p1f16",
+ ],
+)
+
libc_math_function(
name = "log1p",
additional_deps = [":__support_math_log1p"],
>From 95945f40085d64dd9d87e723b2f53aab5fa98df5 Mon Sep 17 00:00:00 2001
From: Younan Zhang <zyn7109 at gmail.com>
Date: Mon, 13 Apr 2026 17:10:09 +0800
Subject: [PATCH 29/36] [Clangd] Don't traverse ConceptDecl in typeForNode
(#191654)
ConceptDecl doesn't have an associated template declaration, and it
doesn't introduce a type either.
Fixes https://github.com/llvm/llvm-project/issues/188914
---
clang-tools-extra/clangd/XRefs.cpp | 5 ++++-
clang-tools-extra/clangd/unittests/XRefsTests.cpp | 9 +++++++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/clang-tools-extra/clangd/XRefs.cpp b/clang-tools-extra/clangd/XRefs.cpp
index 4b685b7bf793e..5f64f01c1ff34 100644
--- a/clang-tools-extra/clangd/XRefs.cpp
+++ b/clang-tools-extra/clangd/XRefs.cpp
@@ -2058,7 +2058,10 @@ static QualType typeForNode(const ASTContext &Ctx, const HeuristicResolver *H,
}
// Look inside templates.
QualType VisitTemplateDecl(const TemplateDecl *D) {
- return Visit(D->getTemplatedDecl());
+ if (const auto *TD = D->getTemplatedDecl())
+ return Visit(TD);
+ // ConceptDecl doesn't have any associated templates nor types.
+ return QualType();
}
} V(Ctx);
return V.Visit(D);
diff --git a/clang-tools-extra/clangd/unittests/XRefsTests.cpp b/clang-tools-extra/clangd/unittests/XRefsTests.cpp
index 8e97db7ab17c5..00ead63050c8d 100644
--- a/clang-tools-extra/clangd/unittests/XRefsTests.cpp
+++ b/clang-tools-extra/clangd/unittests/XRefsTests.cpp
@@ -2094,14 +2094,19 @@ TEST(FindType, All) {
TEST(FindType, Definition) {
Annotations A(R"cpp(
class $decl[[X]];
- X *^x;
+ X *$x^x;
class $def[[X]] {};
+
+ template <class T>
+ concept $Concept^True = true;
)cpp");
auto TU = TestTU::withCode(A.code().str());
+ TU.ExtraArgs.push_back("-std=c++20");
ParsedAST AST = TU.build();
- EXPECT_THAT(findType(AST, A.point(), nullptr),
+ EXPECT_THAT(findType(AST, A.point("x"), nullptr),
ElementsAre(sym("X", A.range("decl"), A.range("def"))));
+ EXPECT_THAT(findType(AST, A.point("Concept"), nullptr), IsEmpty());
}
TEST(FindType, Index) {
>From aa7b7c23f067c63d9a938e53b94373df235374b2 Mon Sep 17 00:00:00 2001
From: 2elliti <forstoic724321 at gmail.com>
Date: Mon, 13 Apr 2026 15:04:59 +0530
Subject: [PATCH 30/36] update tests
---
llvm/test/CodeGen/X86/bit-manip-i256.ll | 163 +++---
llvm/test/CodeGen/X86/bit-manip-i512.ll | 549 +++++++++---------
llvm/test/CodeGen/X86/bitcnt-big-integer.ll | 455 +++++++--------
llvm/test/CodeGen/X86/bittest-big-integer.ll | 92 +--
llvm/test/CodeGen/X86/bsf.ll | 4 +-
llvm/test/CodeGen/X86/bsr.ll | 8 +-
.../CodeGen/X86/dag-update-nodetomatch.ll | 4 +-
llvm/test/CodeGen/X86/dagcombine-select.ll | 28 +-
llvm/test/CodeGen/X86/dagcombine-shifts.ll | 3 +-
llvm/test/CodeGen/X86/divrem8_ext.ll | 2 +-
.../X86/fold-int-pow2-with-fmul-or-fdiv.ll | 28 +-
llvm/test/CodeGen/X86/h-registers-1.ll | 28 +-
llvm/test/CodeGen/X86/narrow-add-i64.ll | 8 +-
llvm/test/CodeGen/X86/popcnt.ll | 168 +++---
llvm/test/CodeGen/X86/pr173924.ll | 105 +++-
.../CodeGen/X86/scheduler-backtracking.ll | 284 ++++-----
llvm/test/CodeGen/X86/vector-compress.ll | 414 +++++++------
llvm/test/CodeGen/X86/xaluo.ll | 2 +-
18 files changed, 1170 insertions(+), 1175 deletions(-)
diff --git a/llvm/test/CodeGen/X86/bit-manip-i256.ll b/llvm/test/CodeGen/X86/bit-manip-i256.ll
index 9bebab1834e41..af1327a367f3d 100644
--- a/llvm/test/CodeGen/X86/bit-manip-i256.ll
+++ b/llvm/test/CodeGen/X86/bit-manip-i256.ll
@@ -2413,22 +2413,23 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; SSE-NEXT: movq %rcx, %rax
; SSE-NEXT: movq %rdx, %r9
; SSE-NEXT: orq %r8, %r9
-; SSE-NEXT: bsrq %rsi, %rcx
-; SSE-NEXT: orq %rax, %rsi
-; SSE-NEXT: bsrq %r8, %r10
-; SSE-NEXT: xorq $63, %r10
+; SSE-NEXT: movq %rsi, %r10
+; SSE-NEXT: orq %rcx, %r10
+; SSE-NEXT: bsrq %r8, %rcx
+; SSE-NEXT: xorq $63, %rcx
; SSE-NEXT: bsrq %rax, %r11
-; SSE-NEXT: xorq $63, %r11
-; SSE-NEXT: orq $64, %r11
+; SSE-NEXT: xorl $63, %r11d
+; SSE-NEXT: orl $64, %r11d
; SSE-NEXT: testq %r8, %r8
-; SSE-NEXT: cmovneq %r10, %r11
-; SSE-NEXT: bsrq %rdx, %r10
-; SSE-NEXT: xorq $63, %r10
-; SSE-NEXT: xorq $63, %rcx
-; SSE-NEXT: orq $64, %rcx
+; SSE-NEXT: cmovneq %rcx, %r11
+; SSE-NEXT: bsrq %rdx, %rbx
+; SSE-NEXT: xorl $63, %ebx
+; SSE-NEXT: bsrq %rsi, %rcx
+; SSE-NEXT: xorl $63, %ecx
+; SSE-NEXT: orl $64, %ecx
; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovneq %r10, %rcx
-; SSE-NEXT: orq $128, %rcx
+; SSE-NEXT: cmovnel %ebx, %ecx
+; SSE-NEXT: subl $-128, %ecx
; SSE-NEXT: orq %r8, %rax
; SSE-NEXT: cmovneq %r11, %rcx
; SSE-NEXT: xorps %xmm0, %xmm0
@@ -2442,27 +2443,27 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; SSE-NEXT: movzbl %al, %eax
; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movq -40(%rsp,%rax,8), %rdx
-; SSE-NEXT: movq -48(%rsp,%rax,8), %r8
-; SSE-NEXT: movq %r8, %r10
-; SSE-NEXT: shrdq %cl, %rdx, %r10
+; SSE-NEXT: movq -48(%rsp,%rax,8), %rsi
+; SSE-NEXT: movq %rsi, %r8
+; SSE-NEXT: shrdq %cl, %rdx, %r8
; SSE-NEXT: movq -56(%rsp,%rax,8), %r11
; SSE-NEXT: movq %r11, %rbx
-; SSE-NEXT: shrdq %cl, %r8, %rbx
-; SSE-NEXT: movq -64(%rsp,%rax,8), %r8
+; SSE-NEXT: shrdq %cl, %rsi, %rbx
+; SSE-NEXT: movq -64(%rsp,%rax,8), %rsi
; SSE-NEXT: shrq %cl, %rdx
; SSE-NEXT: # kill: def $cl killed $cl killed $rcx
-; SSE-NEXT: shrdq %cl, %r11, %r8
+; SSE-NEXT: shrdq %cl, %r11, %rsi
; SSE-NEXT: xorl %ecx, %ecx
-; SSE-NEXT: orq %r9, %rsi
+; SSE-NEXT: orq %r9, %r10
; SSE-NEXT: cmoveq %rcx, %rbx
-; SSE-NEXT: cmoveq %rcx, %r10
; SSE-NEXT: cmoveq %rcx, %r8
+; SSE-NEXT: cmoveq %rcx, %rsi
; SSE-NEXT: movq %rdi, %rax
; SSE-NEXT: cmoveq %rcx, %rdx
; SSE-NEXT: movq %rdx, 24(%rdi)
-; SSE-NEXT: movq %r10, 16(%rdi)
+; SSE-NEXT: movq %r8, 16(%rdi)
; SSE-NEXT: movq %rbx, 8(%rdi)
-; SSE-NEXT: movq %r8, (%rdi)
+; SSE-NEXT: movq %rsi, (%rdi)
; SSE-NEXT: popq %rbx
; SSE-NEXT: retq
;
@@ -2477,15 +2478,15 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX2-NEXT: orq %rax, %rsi
; AVX2-NEXT: lzcntq %r8, %r10
; AVX2-NEXT: lzcntq %rax, %r11
-; AVX2-NEXT: addq $64, %r11
+; AVX2-NEXT: addl $64, %r11d
; AVX2-NEXT: testq %r8, %r8
; AVX2-NEXT: cmovneq %r10, %r11
; AVX2-NEXT: xorl %r10d, %r10d
; AVX2-NEXT: lzcntq %rdx, %r10
-; AVX2-NEXT: addq $64, %rcx
+; AVX2-NEXT: addl $64, %ecx
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
+; AVX2-NEXT: cmovnel %r10d, %ecx
+; AVX2-NEXT: subl $-128, %ecx
; AVX2-NEXT: orq %r8, %rax
; AVX2-NEXT: cmovneq %r11, %rcx
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -2530,14 +2531,14 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512F-NEXT: orq %rax, %rsi
; AVX512F-NEXT: lzcntq %r8, %r10
; AVX512F-NEXT: lzcntq %rax, %r11
-; AVX512F-NEXT: addq $64, %r11
+; AVX512F-NEXT: addl $64, %r11d
; AVX512F-NEXT: testq %r8, %r8
; AVX512F-NEXT: cmovneq %r10, %r11
; AVX512F-NEXT: lzcntq %rdx, %r10
-; AVX512F-NEXT: addq $64, %rcx
+; AVX512F-NEXT: addl $64, %ecx
; AVX512F-NEXT: testq %rdx, %rdx
-; AVX512F-NEXT: cmovneq %r10, %rcx
-; AVX512F-NEXT: subq $-128, %rcx
+; AVX512F-NEXT: cmovnel %r10d, %ecx
+; AVX512F-NEXT: subl $-128, %ecx
; AVX512F-NEXT: orq %r8, %rax
; AVX512F-NEXT: cmovneq %r11, %rcx
; AVX512F-NEXT: vmovaps {{.*#+}} zmm0 = [0,0,0,9223372036854775808,0,0,0,0]
@@ -2579,14 +2580,14 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512VL-NEXT: orq %rax, %rsi
; AVX512VL-NEXT: lzcntq %r8, %r10
; AVX512VL-NEXT: lzcntq %rax, %r11
-; AVX512VL-NEXT: addq $64, %r11
+; AVX512VL-NEXT: addl $64, %r11d
; AVX512VL-NEXT: testq %r8, %r8
; AVX512VL-NEXT: cmovneq %r10, %r11
; AVX512VL-NEXT: lzcntq %rdx, %r10
-; AVX512VL-NEXT: addq $64, %rcx
+; AVX512VL-NEXT: addl $64, %ecx
; AVX512VL-NEXT: testq %rdx, %rdx
-; AVX512VL-NEXT: cmovneq %r10, %rcx
-; AVX512VL-NEXT: subq $-128, %rcx
+; AVX512VL-NEXT: cmovnel %r10d, %ecx
+; AVX512VL-NEXT: subl $-128, %ecx
; AVX512VL-NEXT: orq %r8, %rax
; AVX512VL-NEXT: cmovneq %r11, %rcx
; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -2631,14 +2632,14 @@ define i256 @isolate_msb_i256(i256 %a0, i256 %idx) nounwind {
; AVX512VBMI-NEXT: orq %rax, %rsi
; AVX512VBMI-NEXT: lzcntq %r8, %r10
; AVX512VBMI-NEXT: lzcntq %rax, %r11
-; AVX512VBMI-NEXT: addq $64, %r11
+; AVX512VBMI-NEXT: addl $64, %r11d
; AVX512VBMI-NEXT: testq %r8, %r8
; AVX512VBMI-NEXT: cmovneq %r10, %r11
; AVX512VBMI-NEXT: lzcntq %rdx, %r10
-; AVX512VBMI-NEXT: addq $64, %rcx
+; AVX512VBMI-NEXT: addl $64, %ecx
; AVX512VBMI-NEXT: testq %rdx, %rdx
-; AVX512VBMI-NEXT: cmovneq %r10, %rcx
-; AVX512VBMI-NEXT: subq $-128, %rcx
+; AVX512VBMI-NEXT: cmovnel %r10d, %ecx
+; AVX512VBMI-NEXT: subl $-128, %ecx
; AVX512VBMI-NEXT: orq %r8, %rax
; AVX512VBMI-NEXT: cmovneq %r11, %rcx
; AVX512VBMI-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -2697,18 +2698,18 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE2-NEXT: bsrq %r8, %r9
; SSE2-NEXT: xorq $63, %r9
; SSE2-NEXT: bsrq %rsi, %rsi
-; SSE2-NEXT: xorq $63, %rsi
-; SSE2-NEXT: orq $64, %rsi
+; SSE2-NEXT: xorl $63, %esi
+; SSE2-NEXT: orl $64, %esi
; SSE2-NEXT: testq %r8, %r8
; SSE2-NEXT: cmovneq %r9, %rsi
; SSE2-NEXT: bsrq %rdx, %r8
-; SSE2-NEXT: xorq $63, %r8
+; SSE2-NEXT: xorl $63, %r8d
; SSE2-NEXT: bsrq %rcx, %rcx
-; SSE2-NEXT: xorq $63, %rcx
-; SSE2-NEXT: orq $64, %rcx
+; SSE2-NEXT: xorl $63, %ecx
+; SSE2-NEXT: orl $64, %ecx
; SSE2-NEXT: testq %rdx, %rdx
-; SSE2-NEXT: cmovneq %r8, %rcx
-; SSE2-NEXT: orq $128, %rcx
+; SSE2-NEXT: cmovnel %r8d, %ecx
+; SSE2-NEXT: subl $-128, %ecx
; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
; SSE2-NEXT: movmskps %xmm1, %edx
; SSE2-NEXT: xorl $15, %edx
@@ -2755,22 +2756,22 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; SSE42-NEXT: bsrq %rsi, %r8
; SSE42-NEXT: xorq $63, %r8
; SSE42-NEXT: bsrq %rax, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
+; SSE42-NEXT: xorl $63, %eax
+; SSE42-NEXT: orl $64, %eax
; SSE42-NEXT: testq %rsi, %rsi
; SSE42-NEXT: cmovneq %r8, %rax
; SSE42-NEXT: bsrq %rdx, %rsi
-; SSE42-NEXT: xorq $63, %rsi
+; SSE42-NEXT: xorl $63, %esi
; SSE42-NEXT: bsrq %rcx, %rcx
-; SSE42-NEXT: xorq $63, %rcx
-; SSE42-NEXT: orq $64, %rcx
+; SSE42-NEXT: xorl $63, %ecx
+; SSE42-NEXT: orl $64, %ecx
; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %rsi, %rcx
+; SSE42-NEXT: cmovnel %esi, %ecx
; SSE42-NEXT: xorps %xmm2, %xmm2
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: orq $128, %rcx
+; SSE42-NEXT: subl $-128, %ecx
; SSE42-NEXT: ptest %xmm1, %xmm1
; SSE42-NEXT: cmovneq %rax, %rcx
; SSE42-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
@@ -2813,16 +2814,16 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; AVX2-NEXT: vpextrq $1, %xmm1, %r8
; AVX2-NEXT: lzcntq %r8, %rcx
; AVX2-NEXT: lzcntq %rsi, %r9
-; AVX2-NEXT: addq $64, %r9
+; AVX2-NEXT: addl $64, %r9d
; AVX2-NEXT: testq %r8, %r8
; AVX2-NEXT: cmovneq %rcx, %r9
; AVX2-NEXT: lzcntq %rdx, %r10
; AVX2-NEXT: xorl %ecx, %ecx
; AVX2-NEXT: lzcntq %rax, %rcx
-; AVX2-NEXT: addq $64, %rcx
+; AVX2-NEXT: addl $64, %ecx
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
+; AVX2-NEXT: cmovnel %r10d, %ecx
+; AVX2-NEXT: subl $-128, %ecx
; AVX2-NEXT: orq %r8, %rsi
; AVX2-NEXT: cmovneq %r9, %rcx
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
@@ -2863,7 +2864,7 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; AVX512F-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k0
; AVX512F-NEXT: vplzcntq %zmm1, %zmm1
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vpcompressq %zmm1, %zmm1 {%k1}
@@ -2901,7 +2902,7 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; AVX512VL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
; AVX512VL-NEXT: vptestmq %ymm1, %ymm1, %k1
; AVX512VL-NEXT: vplzcntq %ymm1, %ymm1
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VL-NEXT: vpcompressq %ymm1, %ymm1 {%k1}
; AVX512VL-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512VL-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
@@ -2940,7 +2941,7 @@ define i256 @isolate_msb_i256_vector(<4 x i64> %v0, i256 %idx) nounwind {
; AVX512VBMI-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
; AVX512VBMI-NEXT: vptestmq %ymm1, %ymm1, %k1
; AVX512VBMI-NEXT: vplzcntq %ymm1, %ymm1
-; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VBMI-NEXT: vpcompressq %ymm1, %ymm1 {%k1}
; AVX512VBMI-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512VBMI-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
@@ -2997,18 +2998,18 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; SSE2-NEXT: bsrq %r8, %rcx
; SSE2-NEXT: xorq $63, %rcx
; SSE2-NEXT: bsrq %rdx, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: orl $64, %r10d
; SSE2-NEXT: testq %r8, %r8
; SSE2-NEXT: cmovneq %rcx, %r10
; SSE2-NEXT: bsrq %r9, %r11
-; SSE2-NEXT: xorq $63, %r11
+; SSE2-NEXT: xorl $63, %r11d
; SSE2-NEXT: bsrq (%rsi), %rcx
-; SSE2-NEXT: xorq $63, %rcx
-; SSE2-NEXT: orq $64, %rcx
+; SSE2-NEXT: xorl $63, %ecx
+; SSE2-NEXT: orl $64, %ecx
; SSE2-NEXT: testq %r9, %r9
-; SSE2-NEXT: cmovneq %r11, %rcx
-; SSE2-NEXT: orq $128, %rcx
+; SSE2-NEXT: cmovnel %r11d, %ecx
+; SSE2-NEXT: subl $-128, %ecx
; SSE2-NEXT: orq %r8, %rdx
; SSE2-NEXT: cmovneq %r10, %rcx
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
@@ -3053,19 +3054,19 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; SSE42-NEXT: bsrq %rdx, %rcx
; SSE42-NEXT: xorq $63, %rcx
; SSE42-NEXT: bsrq %rax, %r8
-; SSE42-NEXT: xorq $63, %r8
-; SSE42-NEXT: orq $64, %r8
+; SSE42-NEXT: xorl $63, %r8d
+; SSE42-NEXT: orl $64, %r8d
; SSE42-NEXT: testq %rdx, %rdx
; SSE42-NEXT: cmovneq %rcx, %r8
; SSE42-NEXT: movq 8(%rsi), %r9
; SSE42-NEXT: bsrq %r9, %r10
; SSE42-NEXT: bsrq (%rsi), %rcx
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: xorq $63, %rcx
-; SSE42-NEXT: orq $64, %rcx
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: xorl $63, %ecx
+; SSE42-NEXT: orl $64, %ecx
; SSE42-NEXT: testq %r9, %r9
-; SSE42-NEXT: cmovneq %r10, %rcx
-; SSE42-NEXT: orq $128, %rcx
+; SSE42-NEXT: cmovnel %r10d, %ecx
+; SSE42-NEXT: subl $-128, %ecx
; SSE42-NEXT: orq %rdx, %rax
; SSE42-NEXT: cmovneq %r8, %rcx
; SSE42-NEXT: xorps %xmm1, %xmm1
@@ -3108,17 +3109,17 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; AVX2-NEXT: movq 24(%rsi), %rdx
; AVX2-NEXT: lzcntq %rdx, %rcx
; AVX2-NEXT: lzcntq %rax, %r8
-; AVX2-NEXT: addq $64, %r8
+; AVX2-NEXT: addl $64, %r8d
; AVX2-NEXT: testq %rdx, %rdx
; AVX2-NEXT: cmovneq %rcx, %r8
; AVX2-NEXT: movq 8(%rsi), %r9
; AVX2-NEXT: lzcntq %r9, %r10
; AVX2-NEXT: xorl %ecx, %ecx
; AVX2-NEXT: lzcntq (%rsi), %rcx
-; AVX2-NEXT: addq $64, %rcx
+; AVX2-NEXT: addl $64, %ecx
; AVX2-NEXT: testq %r9, %r9
-; AVX2-NEXT: cmovneq %r10, %rcx
-; AVX2-NEXT: subq $-128, %rcx
+; AVX2-NEXT: cmovnel %r10d, %ecx
+; AVX2-NEXT: subl $-128, %ecx
; AVX2-NEXT: orq %rdx, %rax
; AVX2-NEXT: cmovneq %r8, %rcx
; AVX2-NEXT: vmovdqu (%rsi), %ymm0
@@ -3161,7 +3162,7 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; AVX512F-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k0
; AVX512F-NEXT: vplzcntq %zmm1, %zmm1
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vpcompressq %zmm1, %zmm1 {%k1} {z}
@@ -3199,7 +3200,7 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; AVX512VL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
; AVX512VL-NEXT: vptestmq %ymm1, %ymm1, %k1
; AVX512VL-NEXT: vplzcntq %ymm1, %ymm1
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VL-NEXT: vpcompressq %ymm1, %ymm1 {%k1} {z}
; AVX512VL-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512VL-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
@@ -3239,7 +3240,7 @@ define i256 @isolate_msb_i256_load(ptr %p0, i256 %idx) nounwind {
; AVX512VBMI-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0]
; AVX512VBMI-NEXT: vptestmq %ymm1, %ymm1, %k1
; AVX512VBMI-NEXT: vplzcntq %ymm1, %ymm1
-; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VBMI-NEXT: vpcompressq %ymm1, %ymm1 {%k1} {z}
; AVX512VBMI-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512VBMI-NEXT: vmovups %ymm2, -{{[0-9]+}}(%rsp)
diff --git a/llvm/test/CodeGen/X86/bit-manip-i512.ll b/llvm/test/CodeGen/X86/bit-manip-i512.ll
index 1688e97d26272..c06dc1bcfae8d 100644
--- a/llvm/test/CodeGen/X86/bit-manip-i512.ll
+++ b/llvm/test/CodeGen/X86/bit-manip-i512.ll
@@ -4127,39 +4127,39 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
; SSE-NEXT: bsrq %r14, %r15
; SSE-NEXT: xorq $63, %r15
; SSE-NEXT: bsrq %rbx, %r12
-; SSE-NEXT: xorq $63, %r12
-; SSE-NEXT: orq $64, %r12
+; SSE-NEXT: xorl $63, %r12d
+; SSE-NEXT: orl $64, %r12d
; SSE-NEXT: testq %r14, %r14
; SSE-NEXT: cmovneq %r15, %r12
; SSE-NEXT: bsrq %r11, %r13
-; SSE-NEXT: xorq $63, %r13
+; SSE-NEXT: xorl $63, %r13d
; SSE-NEXT: bsrq %r9, %r15
-; SSE-NEXT: xorq $63, %r15
-; SSE-NEXT: orq $64, %r15
+; SSE-NEXT: xorl $63, %r15d
+; SSE-NEXT: orl $64, %r15d
; SSE-NEXT: testq %r11, %r11
-; SSE-NEXT: cmovneq %r13, %r15
-; SSE-NEXT: orq $128, %r15
+; SSE-NEXT: cmovnel %r13d, %r15d
+; SSE-NEXT: subl $-128, %r15d
; SSE-NEXT: movq %rbx, %r13
; SSE-NEXT: orq %r14, %r13
; SSE-NEXT: cmovneq %r12, %r15
; SSE-NEXT: bsrq %r8, %r12
-; SSE-NEXT: xorq $63, %r12
+; SSE-NEXT: xorl $63, %r12d
; SSE-NEXT: bsrq %rcx, %r13
-; SSE-NEXT: xorq $63, %r13
-; SSE-NEXT: orq $64, %r13
+; SSE-NEXT: xorl $63, %r13d
+; SSE-NEXT: orl $64, %r13d
; SSE-NEXT: testq %r8, %r8
-; SSE-NEXT: cmovneq %r12, %r13
+; SSE-NEXT: cmovnel %r12d, %r13d
; SSE-NEXT: bsrq %rdx, %r12
-; SSE-NEXT: xorq $63, %r12
+; SSE-NEXT: xorl $63, %r12d
; SSE-NEXT: bsrq %rsi, %rsi
-; SSE-NEXT: xorq $63, %rsi
-; SSE-NEXT: orq $64, %rsi
+; SSE-NEXT: xorl $63, %esi
+; SSE-NEXT: orl $64, %esi
; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovneq %r12, %rsi
-; SSE-NEXT: orq $128, %rsi
+; SSE-NEXT: cmovnel %r12d, %esi
+; SSE-NEXT: subl $-128, %esi
; SSE-NEXT: orq %r8, %rcx
-; SSE-NEXT: cmovneq %r13, %rsi
-; SSE-NEXT: orq $256, %rsi # imm = 0x100
+; SSE-NEXT: cmovnel %r13d, %esi
+; SSE-NEXT: addl $256, %esi # imm = 0x100
; SSE-NEXT: orq %r14, %r11
; SSE-NEXT: orq %rbx, %r9
; SSE-NEXT: orq %r11, %r9
@@ -4230,124 +4230,119 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
;
; AVX2-LABEL: isolate_msb_i512:
; AVX2: # %bb.0:
-; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %r13
; AVX2-NEXT: pushq %r12
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: pushq %rax
+; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %rbx
; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r14
-; AVX2-NEXT: movq {{[0-9]+}}(%rsp), %r15
-; AVX2-NEXT: movq %r8, %rax
-; AVX2-NEXT: orq %r15, %rax
+; AVX2-NEXT: movq %r8, %r11
+; AVX2-NEXT: orq %r14, %r11
; AVX2-NEXT: movq %rdx, %r10
-; AVX2-NEXT: orq %rbx, %r10
; AVX2-NEXT: orq %rax, %r10
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: orq %r14, %rax
+; AVX2-NEXT: orq %r11, %r10
+; AVX2-NEXT: movq %rcx, %r15
+; AVX2-NEXT: orq %rbx, %r15
; AVX2-NEXT: movq %rsi, %r11
; AVX2-NEXT: orq %r9, %r11
-; AVX2-NEXT: orq %rax, %r11
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %r15, %rax
+; AVX2-NEXT: orq %r15, %r11
+; AVX2-NEXT: xorl %r15d, %r15d
+; AVX2-NEXT: lzcntq %r14, %r15
+; AVX2-NEXT: xorl %r12d, %r12d
+; AVX2-NEXT: lzcntq %rbx, %r12
+; AVX2-NEXT: addl $64, %r12d
+; AVX2-NEXT: testq %r14, %r14
+; AVX2-NEXT: cmovneq %r15, %r12
; AVX2-NEXT: xorl %r13d, %r13d
-; AVX2-NEXT: lzcntq %r14, %r13
-; AVX2-NEXT: addq $64, %r13
-; AVX2-NEXT: testq %r15, %r15
-; AVX2-NEXT: cmovneq %rax, %r13
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %rbx, %rax
+; AVX2-NEXT: lzcntq %rax, %r13
+; AVX2-NEXT: xorl %r15d, %r15d
+; AVX2-NEXT: lzcntq %r9, %r15
+; AVX2-NEXT: addl $64, %r15d
+; AVX2-NEXT: testq %rax, %rax
+; AVX2-NEXT: cmovnel %r13d, %r15d
+; AVX2-NEXT: subl $-128, %r15d
+; AVX2-NEXT: movq %rbx, %r13
+; AVX2-NEXT: orq %r14, %r13
+; AVX2-NEXT: cmovneq %r12, %r15
; AVX2-NEXT: xorl %r12d, %r12d
-; AVX2-NEXT: lzcntq %r9, %r12
-; AVX2-NEXT: addq $64, %r12
-; AVX2-NEXT: testq %rbx, %rbx
-; AVX2-NEXT: cmovneq %rax, %r12
-; AVX2-NEXT: subq $-128, %r12
-; AVX2-NEXT: movq %r14, %rax
-; AVX2-NEXT: orq %r15, %rax
-; AVX2-NEXT: cmovneq %r13, %r12
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %r8, %rax
+; AVX2-NEXT: lzcntq %r8, %r12
; AVX2-NEXT: xorl %r13d, %r13d
; AVX2-NEXT: lzcntq %rcx, %r13
-; AVX2-NEXT: addq $64, %r13
+; AVX2-NEXT: addl $64, %r13d
; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %rax, %r13
-; AVX2-NEXT: xorl %ebp, %ebp
-; AVX2-NEXT: lzcntq %rdx, %rbp
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: lzcntq %rsi, %rax
-; AVX2-NEXT: addq $64, %rax
+; AVX2-NEXT: cmovnel %r12d, %r13d
+; AVX2-NEXT: xorl %r12d, %r12d
+; AVX2-NEXT: lzcntq %rdx, %r12
+; AVX2-NEXT: lzcntq %rsi, %rsi
+; AVX2-NEXT: addl $64, %esi
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %rbp, %rax
-; AVX2-NEXT: subq $-128, %rax
+; AVX2-NEXT: cmovnel %r12d, %esi
+; AVX2-NEXT: subl $-128, %esi
; AVX2-NEXT: orq %r8, %rcx
-; AVX2-NEXT: cmovneq %r13, %rax
-; AVX2-NEXT: addq $256, %rax # imm = 0x100
-; AVX2-NEXT: orq %r15, %rbx
-; AVX2-NEXT: orq %r14, %r9
+; AVX2-NEXT: cmovnel %r13d, %esi
+; AVX2-NEXT: addl $256, %esi # imm = 0x100
+; AVX2-NEXT: orq %r14, %rax
; AVX2-NEXT: orq %rbx, %r9
-; AVX2-NEXT: cmovneq %r12, %rax
+; AVX2-NEXT: orq %rax, %r9
+; AVX2-NEXT: cmovneq %r15, %rsi
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,9223372036854775808]
; AVX2-NEXT: vmovups %ymm1, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: movl %eax, %ecx
+; AVX2-NEXT: movl %esi, %ecx
; AVX2-NEXT: andl $63, %ecx
-; AVX2-NEXT: shrl $3, %eax
-; AVX2-NEXT: andl $56, %eax
-; AVX2-NEXT: movq -72(%rsp,%rax), %rbx
-; AVX2-NEXT: movq -80(%rsp,%rax), %r8
-; AVX2-NEXT: movq %r8, %rdx
-; AVX2-NEXT: shrdq %cl, %rbx, %rdx
-; AVX2-NEXT: movq -88(%rsp,%rax), %r9
-; AVX2-NEXT: movq %r9, %rsi
-; AVX2-NEXT: shrdq %cl, %r8, %rsi
-; AVX2-NEXT: movq -96(%rsp,%rax), %r14
-; AVX2-NEXT: movq %r14, %r8
-; AVX2-NEXT: shrdq %cl, %r9, %r8
-; AVX2-NEXT: movq -104(%rsp,%rax), %r15
-; AVX2-NEXT: movq %r15, %r9
-; AVX2-NEXT: shrdq %cl, %r14, %r9
-; AVX2-NEXT: movq -112(%rsp,%rax), %r13
-; AVX2-NEXT: movq %r13, %r14
-; AVX2-NEXT: shrdq %cl, %r15, %r14
-; AVX2-NEXT: movq -128(%rsp,%rax), %r15
-; AVX2-NEXT: movq -120(%rsp,%rax), %rax
-; AVX2-NEXT: movq %rax, %r12
+; AVX2-NEXT: shrl $3, %esi
+; AVX2-NEXT: andl $56, %esi
+; AVX2-NEXT: movq -72(%rsp,%rsi), %r14
+; AVX2-NEXT: movq -80(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %rdx
+; AVX2-NEXT: shrdq %cl, %r14, %rdx
+; AVX2-NEXT: movq -88(%rsp,%rsi), %rbx
+; AVX2-NEXT: movq %rbx, %r8
+; AVX2-NEXT: shrdq %cl, %rax, %r8
+; AVX2-NEXT: movq -96(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %r9
+; AVX2-NEXT: shrdq %cl, %rbx, %r9
+; AVX2-NEXT: movq -104(%rsp,%rsi), %r12
+; AVX2-NEXT: movq %r12, %rbx
+; AVX2-NEXT: shrdq %cl, %rax, %rbx
+; AVX2-NEXT: movq -112(%rsp,%rsi), %rax
+; AVX2-NEXT: movq %rax, %r15
+; AVX2-NEXT: shrdq %cl, %r12, %r15
+; AVX2-NEXT: movq -128(%rsp,%rsi), %r12
+; AVX2-NEXT: movq -120(%rsp,%rsi), %r13
+; AVX2-NEXT: movq %r13, %rsi
+; AVX2-NEXT: shrdq %cl, %rax, %rsi
; AVX2-NEXT: shrdq %cl, %r13, %r12
-; AVX2-NEXT: shrdq %cl, %rax, %r15
; AVX2-NEXT: movq %rdi, %rax
; AVX2-NEXT: xorl %edi, %edi
; AVX2-NEXT: orq %r10, %r11
-; AVX2-NEXT: shrxq %rcx, %rbx, %rcx
-; AVX2-NEXT: cmoveq %rdi, %r12
-; AVX2-NEXT: cmoveq %rdi, %r14
+; AVX2-NEXT: shrxq %rcx, %r14, %rcx
+; AVX2-NEXT: cmoveq %rdi, %rsi
+; AVX2-NEXT: cmoveq %rdi, %r15
+; AVX2-NEXT: cmoveq %rdi, %rbx
; AVX2-NEXT: cmoveq %rdi, %r9
; AVX2-NEXT: cmoveq %rdi, %r8
-; AVX2-NEXT: cmoveq %rdi, %rsi
; AVX2-NEXT: cmoveq %rdi, %rdx
-; AVX2-NEXT: cmoveq %rdi, %r15
+; AVX2-NEXT: cmoveq %rdi, %r12
; AVX2-NEXT: cmoveq %rdi, %rcx
; AVX2-NEXT: movq %rcx, 56(%rax)
; AVX2-NEXT: movq %rdx, 48(%rax)
-; AVX2-NEXT: movq %rsi, 40(%rax)
-; AVX2-NEXT: movq %r8, 32(%rax)
-; AVX2-NEXT: movq %r9, 24(%rax)
-; AVX2-NEXT: movq %r14, 16(%rax)
-; AVX2-NEXT: movq %r12, 8(%rax)
-; AVX2-NEXT: movq %r15, (%rax)
-; AVX2-NEXT: addq $8, %rsp
+; AVX2-NEXT: movq %r8, 40(%rax)
+; AVX2-NEXT: movq %r9, 32(%rax)
+; AVX2-NEXT: movq %rbx, 24(%rax)
+; AVX2-NEXT: movq %r15, 16(%rax)
+; AVX2-NEXT: movq %rsi, 8(%rax)
+; AVX2-NEXT: movq %r12, (%rax)
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r12
; AVX2-NEXT: popq %r13
; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15
-; AVX2-NEXT: popq %rbp
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
@@ -4379,7 +4374,7 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovq %xmm0, %rcx
; AVX512F-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
@@ -4424,7 +4419,7 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
; AVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VL-NEXT: vmovq %xmm0, %rcx
; AVX512VL-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
@@ -4470,7 +4465,7 @@ define i512 @isolate_msb_i512(i512 %a0, i512 %idx) nounwind {
; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512VBMI-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VBMI-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VBMI-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VBMI-NEXT: vmovq %xmm0, %rcx
; AVX512VBMI-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
@@ -4526,43 +4521,43 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE2-NEXT: bsrq %rbx, %r14
; SSE2-NEXT: xorq $63, %r14
; SSE2-NEXT: bsrq %r10, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: orl $64, %r10d
; SSE2-NEXT: testq %rbx, %rbx
; SSE2-NEXT: cmovneq %r14, %r10
; SSE2-NEXT: bsrq %r11, %rbx
-; SSE2-NEXT: xorq $63, %rbx
+; SSE2-NEXT: xorl $63, %ebx
; SSE2-NEXT: bsrq %r9, %r9
-; SSE2-NEXT: xorq $63, %r9
-; SSE2-NEXT: orq $64, %r9
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: orl $64, %r9d
; SSE2-NEXT: testq %r11, %r11
-; SSE2-NEXT: cmovneq %rbx, %r9
-; SSE2-NEXT: orq $128, %r9
+; SSE2-NEXT: cmovnel %ebx, %r9d
+; SSE2-NEXT: subl $-128, %r9d
; SSE2-NEXT: por %xmm3, %xmm2
; SSE2-NEXT: pcmpeqd %xmm4, %xmm3
; SSE2-NEXT: movmskps %xmm3, %r11d
; SSE2-NEXT: xorl $15, %r11d
; SSE2-NEXT: cmovneq %r10, %r9
; SSE2-NEXT: bsrq %rsi, %r10
-; SSE2-NEXT: xorq $63, %r10
+; SSE2-NEXT: xorl $63, %r10d
; SSE2-NEXT: bsrq %r8, %r8
-; SSE2-NEXT: xorq $63, %r8
-; SSE2-NEXT: orq $64, %r8
+; SSE2-NEXT: xorl $63, %r8d
+; SSE2-NEXT: orl $64, %r8d
; SSE2-NEXT: testq %rsi, %rsi
-; SSE2-NEXT: cmovneq %r10, %r8
+; SSE2-NEXT: cmovnel %r10d, %r8d
; SSE2-NEXT: bsrq %rcx, %rsi
-; SSE2-NEXT: xorq $63, %rsi
+; SSE2-NEXT: xorl $63, %esi
; SSE2-NEXT: bsrq %rdx, %rdx
-; SSE2-NEXT: xorq $63, %rdx
-; SSE2-NEXT: orq $64, %rdx
+; SSE2-NEXT: xorl $63, %edx
+; SSE2-NEXT: orl $64, %edx
; SSE2-NEXT: testq %rcx, %rcx
-; SSE2-NEXT: cmovneq %rsi, %rdx
-; SSE2-NEXT: orq $128, %rdx
+; SSE2-NEXT: cmovnel %esi, %edx
+; SSE2-NEXT: subl $-128, %edx
; SSE2-NEXT: pcmpeqd %xmm4, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
-; SSE2-NEXT: cmovneq %r8, %rdx
-; SSE2-NEXT: orq $256, %rdx # imm = 0x100
+; SSE2-NEXT: cmovnel %r8d, %edx
+; SSE2-NEXT: addl $256, %edx # imm = 0x100
; SSE2-NEXT: pcmpeqd %xmm4, %xmm2
; SSE2-NEXT: movmskps %xmm2, %ecx
; SSE2-NEXT: xorl $15, %ecx
@@ -4646,39 +4641,39 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; SSE42-NEXT: bsrq %r11, %rbx
; SSE42-NEXT: xorq $63, %rbx
; SSE42-NEXT: bsrq %r10, %r10
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: orq $64, %r10
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: orl $64, %r10d
; SSE42-NEXT: testq %r11, %r11
; SSE42-NEXT: cmovneq %rbx, %r10
; SSE42-NEXT: bsrq %r9, %r11
-; SSE42-NEXT: xorq $63, %r11
+; SSE42-NEXT: xorl $63, %r11d
; SSE42-NEXT: bsrq %rsi, %rsi
-; SSE42-NEXT: xorq $63, %rsi
-; SSE42-NEXT: orq $64, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: orl $64, %esi
; SSE42-NEXT: testq %r9, %r9
-; SSE42-NEXT: cmovneq %r11, %rsi
-; SSE42-NEXT: orq $128, %rsi
+; SSE42-NEXT: cmovnel %r11d, %esi
+; SSE42-NEXT: subl $-128, %esi
; SSE42-NEXT: ptest %xmm3, %xmm3
; SSE42-NEXT: cmovneq %r10, %rsi
; SSE42-NEXT: bsrq %rdx, %r9
-; SSE42-NEXT: xorq $63, %r9
+; SSE42-NEXT: xorl $63, %r9d
; SSE42-NEXT: bsrq %r8, %r8
-; SSE42-NEXT: xorq $63, %r8
-; SSE42-NEXT: orq $64, %r8
+; SSE42-NEXT: xorl $63, %r8d
+; SSE42-NEXT: orl $64, %r8d
; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %r9, %r8
+; SSE42-NEXT: cmovnel %r9d, %r8d
; SSE42-NEXT: bsrq %rcx, %rdx
-; SSE42-NEXT: xorq $63, %rdx
+; SSE42-NEXT: xorl $63, %edx
; SSE42-NEXT: bsrq %rax, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
+; SSE42-NEXT: xorl $63, %eax
+; SSE42-NEXT: orl $64, %eax
; SSE42-NEXT: testq %rcx, %rcx
-; SSE42-NEXT: cmovneq %rdx, %rax
+; SSE42-NEXT: cmovnel %edx, %eax
; SSE42-NEXT: por %xmm2, %xmm0
-; SSE42-NEXT: orq $128, %rax
+; SSE42-NEXT: subl $-128, %eax
; SSE42-NEXT: ptest %xmm1, %xmm1
-; SSE42-NEXT: cmovneq %r8, %rax
-; SSE42-NEXT: orq $256, %rax # imm = 0x100
+; SSE42-NEXT: cmovnel %r8d, %eax
+; SSE42-NEXT: addl $256, %eax # imm = 0x100
; SSE42-NEXT: por %xmm3, %xmm2
; SSE42-NEXT: ptest %xmm2, %xmm2
; SSE42-NEXT: cmovneq %rsi, %rax
@@ -4769,35 +4764,35 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; AVX2-NEXT: lzcntq %rsi, %rbx
; AVX2-NEXT: xorl %r14d, %r14d
; AVX2-NEXT: lzcntq %rdx, %r14
-; AVX2-NEXT: addq $64, %r14
+; AVX2-NEXT: addl $64, %r14d
; AVX2-NEXT: testq %rsi, %rsi
; AVX2-NEXT: cmovneq %rbx, %r14
; AVX2-NEXT: xorl %ebx, %ebx
; AVX2-NEXT: lzcntq %r11, %rbx
; AVX2-NEXT: lzcntq %r10, %r10
-; AVX2-NEXT: addq $64, %r10
+; AVX2-NEXT: addl $64, %r10d
; AVX2-NEXT: testq %r11, %r11
-; AVX2-NEXT: cmovneq %rbx, %r10
-; AVX2-NEXT: subq $-128, %r10
+; AVX2-NEXT: cmovnel %ebx, %r10d
+; AVX2-NEXT: subl $-128, %r10d
; AVX2-NEXT: orq %rsi, %rdx
; AVX2-NEXT: cmovneq %r14, %r10
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: lzcntq %rcx, %rdx
; AVX2-NEXT: xorl %esi, %esi
; AVX2-NEXT: lzcntq %rax, %rsi
-; AVX2-NEXT: addq $64, %rsi
+; AVX2-NEXT: addl $64, %esi
; AVX2-NEXT: testq %rcx, %rcx
-; AVX2-NEXT: cmovneq %rdx, %rsi
+; AVX2-NEXT: cmovnel %edx, %esi
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: lzcntq %r9, %rdx
; AVX2-NEXT: lzcntq %r8, %r8
-; AVX2-NEXT: addq $64, %r8
+; AVX2-NEXT: addl $64, %r8d
; AVX2-NEXT: testq %r9, %r9
-; AVX2-NEXT: cmovneq %rdx, %r8
-; AVX2-NEXT: subq $-128, %r8
+; AVX2-NEXT: cmovnel %edx, %r8d
+; AVX2-NEXT: subl $-128, %r8d
; AVX2-NEXT: orq %rcx, %rax
-; AVX2-NEXT: cmovneq %rsi, %r8
-; AVX2-NEXT: addq $256, %r8 # imm = 0x100
+; AVX2-NEXT: cmovnel %esi, %r8d
+; AVX2-NEXT: addl $256, %r8d # imm = 0x100
; AVX2-NEXT: vptest %ymm1, %ymm1
; AVX2-NEXT: cmovneq %r10, %r8
; AVX2-NEXT: vmovdqu %ymm2, -{{[0-9]+}}(%rsp)
@@ -4865,7 +4860,7 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; AVX512F-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovq %xmm0, %rdx
; AVX512F-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
@@ -4893,7 +4888,7 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; AVX512VL-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VL-NEXT: vmovq %xmm0, %rdx
; AVX512VL-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
@@ -4922,7 +4917,7 @@ define i512 @isolate_msb_i512_vector(<8 x i64> %v0, i512 %idx) nounwind {
; AVX512VBMI-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512VBMI-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VBMI-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VBMI-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VBMI-NEXT: vmovq %xmm0, %rdx
; AVX512VBMI-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
@@ -4956,10 +4951,10 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE2-NEXT: pushq %r12
; SSE2-NEXT: pushq %rbx
; SSE2-NEXT: pushq %rax
-; SSE2-NEXT: movq 8(%rsi), %r9
+; SSE2-NEXT: movq 8(%rsi), %r8
; SSE2-NEXT: movq 16(%rsi), %rcx
-; SSE2-NEXT: movq 24(%rsi), %r8
-; SSE2-NEXT: movq 48(%rsi), %rdx
+; SSE2-NEXT: movq 24(%rsi), %rdx
+; SSE2-NEXT: movq 48(%rsi), %r10
; SSE2-NEXT: movq 56(%rsi), %r11
; SSE2-NEXT: movdqa 32(%rsi), %xmm1
; SSE2-NEXT: movdqa 48(%rsi), %xmm2
@@ -4972,47 +4967,47 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE2-NEXT: pcmpeqd %xmm0, %xmm3
; SSE2-NEXT: movmskps %xmm3, %eax
; SSE2-NEXT: xorl $15, %eax
-; SSE2-NEXT: bsrq %r11, %r10
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: bsrq %rdx, %rbx
-; SSE2-NEXT: xorq $63, %rbx
-; SSE2-NEXT: orq $64, %rbx
+; SSE2-NEXT: bsrq %r11, %r9
+; SSE2-NEXT: xorq $63, %r9
+; SSE2-NEXT: bsrq %r10, %rbx
+; SSE2-NEXT: xorl $63, %ebx
+; SSE2-NEXT: orl $64, %ebx
; SSE2-NEXT: testq %r11, %r11
-; SSE2-NEXT: cmovneq %r10, %rbx
+; SSE2-NEXT: cmovneq %r9, %rbx
; SSE2-NEXT: movq 40(%rsi), %r14
; SSE2-NEXT: bsrq %r14, %r15
-; SSE2-NEXT: bsrq 32(%rsi), %r10
-; SSE2-NEXT: xorq $63, %r15
-; SSE2-NEXT: xorq $63, %r10
-; SSE2-NEXT: orq $64, %r10
+; SSE2-NEXT: bsrq 32(%rsi), %r9
+; SSE2-NEXT: xorl $63, %r15d
+; SSE2-NEXT: xorl $63, %r9d
+; SSE2-NEXT: orl $64, %r9d
; SSE2-NEXT: testq %r14, %r14
-; SSE2-NEXT: cmovneq %r15, %r10
-; SSE2-NEXT: orq $128, %r10
-; SSE2-NEXT: orq %r11, %rdx
-; SSE2-NEXT: cmovneq %rbx, %r10
-; SSE2-NEXT: bsrq %r8, %rdx
-; SSE2-NEXT: xorq $63, %rdx
+; SSE2-NEXT: cmovnel %r15d, %r9d
+; SSE2-NEXT: subl $-128, %r9d
+; SSE2-NEXT: orq %r11, %r10
+; SSE2-NEXT: cmovneq %rbx, %r9
+; SSE2-NEXT: bsrq %rdx, %r10
+; SSE2-NEXT: xorl $63, %r10d
; SSE2-NEXT: bsrq %rcx, %r11
-; SSE2-NEXT: xorq $63, %r11
-; SSE2-NEXT: orq $64, %r11
+; SSE2-NEXT: xorl $63, %r11d
+; SSE2-NEXT: orl $64, %r11d
+; SSE2-NEXT: testq %rdx, %rdx
+; SSE2-NEXT: cmovnel %r10d, %r11d
+; SSE2-NEXT: bsrq %r8, %r10
+; SSE2-NEXT: xorl $63, %r10d
+; SSE2-NEXT: bsrq (%rsi), %rsi
+; SSE2-NEXT: xorl $63, %esi
+; SSE2-NEXT: orl $64, %esi
; SSE2-NEXT: testq %r8, %r8
-; SSE2-NEXT: cmovneq %rdx, %r11
-; SSE2-NEXT: bsrq %r9, %rbx
-; SSE2-NEXT: xorq $63, %rbx
-; SSE2-NEXT: bsrq (%rsi), %rdx
-; SSE2-NEXT: xorq $63, %rdx
-; SSE2-NEXT: orq $64, %rdx
-; SSE2-NEXT: testq %r9, %r9
-; SSE2-NEXT: cmovneq %rbx, %rdx
-; SSE2-NEXT: orq $128, %rdx
-; SSE2-NEXT: orq %r8, %rcx
-; SSE2-NEXT: cmovneq %r11, %rdx
-; SSE2-NEXT: orq $256, %rdx # imm = 0x100
+; SSE2-NEXT: cmovnel %r10d, %esi
+; SSE2-NEXT: subl $-128, %esi
+; SSE2-NEXT: orq %rdx, %rcx
+; SSE2-NEXT: cmovnel %r11d, %esi
+; SSE2-NEXT: addl $256, %esi # imm = 0x100
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
-; SSE2-NEXT: cmovneq %r10, %rdx
+; SSE2-NEXT: cmovneq %r9, %rsi
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
@@ -5022,34 +5017,34 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movl %edx, %ecx
+; SSE2-NEXT: movl %esi, %ecx
; SSE2-NEXT: andl $63, %ecx
-; SSE2-NEXT: shrl $3, %edx
-; SSE2-NEXT: andl $56, %edx
+; SSE2-NEXT: shrl $3, %esi
+; SSE2-NEXT: andl $56, %esi
; SSE2-NEXT: movq $0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movq -72(%rsp,%rdx), %rsi
-; SSE2-NEXT: movq -80(%rsp,%rdx), %r10
+; SSE2-NEXT: movq -72(%rsp,%rsi), %rdx
+; SSE2-NEXT: movq -80(%rsp,%rsi), %r10
; SSE2-NEXT: movq %r10, %r8
-; SSE2-NEXT: shrdq %cl, %rsi, %r8
-; SSE2-NEXT: movq -88(%rsp,%rdx), %r11
+; SSE2-NEXT: shrdq %cl, %rdx, %r8
+; SSE2-NEXT: movq -88(%rsp,%rsi), %r11
; SSE2-NEXT: movq %r11, %r9
; SSE2-NEXT: shrdq %cl, %r10, %r9
-; SSE2-NEXT: movq -96(%rsp,%rdx), %rbx
+; SSE2-NEXT: movq -96(%rsp,%rsi), %rbx
; SSE2-NEXT: movq %rbx, %r10
; SSE2-NEXT: shrdq %cl, %r11, %r10
-; SSE2-NEXT: movq -104(%rsp,%rdx), %r14
+; SSE2-NEXT: movq -104(%rsp,%rsi), %r14
; SSE2-NEXT: movq %r14, %r11
; SSE2-NEXT: shrdq %cl, %rbx, %r11
-; SSE2-NEXT: movq -112(%rsp,%rdx), %r15
+; SSE2-NEXT: movq -112(%rsp,%rsi), %r15
; SSE2-NEXT: movq %r15, %rbx
; SSE2-NEXT: shrdq %cl, %r14, %rbx
-; SSE2-NEXT: movq -120(%rsp,%rdx), %r12
+; SSE2-NEXT: movq -120(%rsp,%rsi), %r12
; SSE2-NEXT: movq %r12, %r14
; SSE2-NEXT: shrdq %cl, %r15, %r14
-; SSE2-NEXT: movq -128(%rsp,%rdx), %rdx
-; SSE2-NEXT: shrq %cl, %rsi
+; SSE2-NEXT: movq -128(%rsp,%rsi), %rsi
+; SSE2-NEXT: shrq %cl, %rdx
; SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
-; SSE2-NEXT: shrdq %cl, %r12, %rdx
+; SSE2-NEXT: shrdq %cl, %r12, %rsi
; SSE2-NEXT: xorl %ecx, %ecx
; SSE2-NEXT: testl %eax, %eax
; SSE2-NEXT: cmoveq %rcx, %r14
@@ -5058,17 +5053,17 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE2-NEXT: cmoveq %rcx, %r10
; SSE2-NEXT: cmoveq %rcx, %r9
; SSE2-NEXT: cmoveq %rcx, %r8
-; SSE2-NEXT: cmoveq %rcx, %rdx
-; SSE2-NEXT: movq %rdi, %rax
; SSE2-NEXT: cmoveq %rcx, %rsi
-; SSE2-NEXT: movq %rsi, 56(%rdi)
+; SSE2-NEXT: movq %rdi, %rax
+; SSE2-NEXT: cmoveq %rcx, %rdx
+; SSE2-NEXT: movq %rdx, 56(%rdi)
; SSE2-NEXT: movq %r8, 48(%rdi)
; SSE2-NEXT: movq %r9, 40(%rdi)
; SSE2-NEXT: movq %r10, 32(%rdi)
; SSE2-NEXT: movq %r11, 24(%rdi)
; SSE2-NEXT: movq %rbx, 16(%rdi)
; SSE2-NEXT: movq %r14, 8(%rdi)
-; SSE2-NEXT: movq %rdx, (%rdi)
+; SSE2-NEXT: movq %rsi, (%rdi)
; SSE2-NEXT: addq $8, %rsp
; SSE2-NEXT: popq %rbx
; SSE2-NEXT: popq %r12
@@ -5082,113 +5077,113 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; SSE42-NEXT: pushq %r14
; SSE42-NEXT: pushq %rbx
; SSE42-NEXT: movq 8(%rsi), %r8
-; SSE42-NEXT: movq 16(%rsi), %rcx
-; SSE42-NEXT: movq 24(%rsi), %rdx
+; SSE42-NEXT: movq 16(%rsi), %rax
+; SSE42-NEXT: movq 24(%rsi), %rcx
; SSE42-NEXT: movq 40(%rsi), %r11
-; SSE42-NEXT: movq 48(%rsi), %rax
+; SSE42-NEXT: movq 48(%rsi), %rdx
; SSE42-NEXT: movq 56(%rsi), %r10
; SSE42-NEXT: movdqa 32(%rsi), %xmm2
; SSE42-NEXT: movdqa 48(%rsi), %xmm0
; SSE42-NEXT: movdqa (%rsi), %xmm1
; SSE42-NEXT: bsrq %r10, %r9
; SSE42-NEXT: xorq $63, %r9
-; SSE42-NEXT: bsrq %rax, %rbx
-; SSE42-NEXT: xorq $63, %rbx
-; SSE42-NEXT: orq $64, %rbx
+; SSE42-NEXT: bsrq %rdx, %rbx
+; SSE42-NEXT: xorl $63, %ebx
+; SSE42-NEXT: orl $64, %ebx
; SSE42-NEXT: testq %r10, %r10
; SSE42-NEXT: cmovneq %r9, %rbx
; SSE42-NEXT: bsrq %r11, %r14
-; SSE42-NEXT: xorq $63, %r14
+; SSE42-NEXT: xorl $63, %r14d
; SSE42-NEXT: bsrq 32(%rsi), %r9
-; SSE42-NEXT: xorq $63, %r9
-; SSE42-NEXT: orq $64, %r9
+; SSE42-NEXT: xorl $63, %r9d
+; SSE42-NEXT: orl $64, %r9d
; SSE42-NEXT: testq %r11, %r11
-; SSE42-NEXT: cmovneq %r14, %r9
-; SSE42-NEXT: orq $128, %r9
-; SSE42-NEXT: orq %r10, %rax
+; SSE42-NEXT: cmovnel %r14d, %r9d
+; SSE42-NEXT: subl $-128, %r9d
+; SSE42-NEXT: orq %r10, %rdx
; SSE42-NEXT: cmovneq %rbx, %r9
-; SSE42-NEXT: bsrq %rdx, %rax
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: bsrq %rcx, %r10
-; SSE42-NEXT: xorq $63, %r10
-; SSE42-NEXT: orq $64, %r10
-; SSE42-NEXT: testq %rdx, %rdx
-; SSE42-NEXT: cmovneq %rax, %r10
+; SSE42-NEXT: bsrq %rcx, %rdx
+; SSE42-NEXT: xorl $63, %edx
+; SSE42-NEXT: bsrq %rax, %r10
+; SSE42-NEXT: xorl $63, %r10d
+; SSE42-NEXT: orl $64, %r10d
+; SSE42-NEXT: testq %rcx, %rcx
+; SSE42-NEXT: cmovnel %edx, %r10d
; SSE42-NEXT: por %xmm2, %xmm1
; SSE42-NEXT: bsrq %r8, %r11
-; SSE42-NEXT: bsrq (%rsi), %rax
-; SSE42-NEXT: xorq $63, %r11
-; SSE42-NEXT: xorq $63, %rax
-; SSE42-NEXT: orq $64, %rax
+; SSE42-NEXT: bsrq (%rsi), %rdx
+; SSE42-NEXT: xorl $63, %r11d
+; SSE42-NEXT: xorl $63, %edx
+; SSE42-NEXT: orl $64, %edx
; SSE42-NEXT: testq %r8, %r8
-; SSE42-NEXT: cmovneq %r11, %rax
-; SSE42-NEXT: orq $128, %rax
-; SSE42-NEXT: orq %rdx, %rcx
-; SSE42-NEXT: cmovneq %r10, %rax
-; SSE42-NEXT: orq $256, %rax # imm = 0x100
+; SSE42-NEXT: cmovnel %r11d, %edx
+; SSE42-NEXT: subl $-128, %edx
+; SSE42-NEXT: orq %rcx, %rax
+; SSE42-NEXT: cmovnel %r10d, %edx
+; SSE42-NEXT: addl $256, %edx # imm = 0x100
; SSE42-NEXT: por %xmm0, %xmm2
; SSE42-NEXT: ptest %xmm2, %xmm2
-; SSE42-NEXT: cmovneq %r9, %rax
+; SSE42-NEXT: cmovneq %r9, %rdx
; SSE42-NEXT: movdqa 16(%rsi), %xmm2
; SSE42-NEXT: xorps %xmm3, %xmm3
; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
-; SSE42-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
+; SSE42-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; SSE42-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
; SSE42-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movl %eax, %ecx
+; SSE42-NEXT: movl %edx, %ecx
; SSE42-NEXT: andl $63, %ecx
-; SSE42-NEXT: shrl $3, %eax
-; SSE42-NEXT: andl $56, %eax
+; SSE42-NEXT: shrl $3, %edx
+; SSE42-NEXT: andl $56, %edx
; SSE42-NEXT: movq $0, -{{[0-9]+}}(%rsp)
-; SSE42-NEXT: movq -72(%rsp,%rax), %rdx
-; SSE42-NEXT: movq -80(%rsp,%rax), %r9
-; SSE42-NEXT: movq %r9, %rsi
-; SSE42-NEXT: shrdq %cl, %rdx, %rsi
-; SSE42-NEXT: movq -88(%rsp,%rax), %r10
-; SSE42-NEXT: movq %r10, %r8
-; SSE42-NEXT: shrdq %cl, %r9, %r8
-; SSE42-NEXT: movq -96(%rsp,%rax), %r11
+; SSE42-NEXT: movq -72(%rsp,%rdx), %rsi
+; SSE42-NEXT: movq -80(%rsp,%rdx), %rax
+; SSE42-NEXT: movq %rax, %r8
+; SSE42-NEXT: shrdq %cl, %rsi, %r8
+; SSE42-NEXT: movq -88(%rsp,%rdx), %r11
; SSE42-NEXT: movq %r11, %r9
-; SSE42-NEXT: shrdq %cl, %r10, %r9
-; SSE42-NEXT: movq -104(%rsp,%rax), %rbx
-; SSE42-NEXT: movq %rbx, %r10
+; SSE42-NEXT: shrdq %cl, %rax, %r9
+; SSE42-NEXT: movq -96(%rsp,%rdx), %rax
+; SSE42-NEXT: movq %rax, %r10
; SSE42-NEXT: shrdq %cl, %r11, %r10
-; SSE42-NEXT: movq -112(%rsp,%rax), %r14
+; SSE42-NEXT: movq -104(%rsp,%rdx), %r14
; SSE42-NEXT: movq %r14, %r11
-; SSE42-NEXT: shrdq %cl, %rbx, %r11
-; SSE42-NEXT: movq -120(%rsp,%rax), %r15
-; SSE42-NEXT: movq %r15, %rbx
+; SSE42-NEXT: shrdq %cl, %rax, %r11
+; SSE42-NEXT: movq -112(%rsp,%rdx), %rax
+; SSE42-NEXT: movq %rax, %rbx
; SSE42-NEXT: shrdq %cl, %r14, %rbx
-; SSE42-NEXT: movq -128(%rsp,%rax), %r14
-; SSE42-NEXT: shrq %cl, %rdx
+; SSE42-NEXT: movq -120(%rsp,%rdx), %r15
+; SSE42-NEXT: movq %r15, %r14
+; SSE42-NEXT: shrdq %cl, %rax, %r14
+; SSE42-NEXT: movq -128(%rsp,%rdx), %rdx
+; SSE42-NEXT: shrq %cl, %rsi
; SSE42-NEXT: # kill: def $cl killed $cl killed $ecx
-; SSE42-NEXT: shrdq %cl, %r15, %r14
+; SSE42-NEXT: shrdq %cl, %r15, %rdx
; SSE42-NEXT: por %xmm0, %xmm2
; SSE42-NEXT: por %xmm2, %xmm1
; SSE42-NEXT: xorl %ecx, %ecx
; SSE42-NEXT: ptest %xmm1, %xmm1
+; SSE42-NEXT: cmoveq %rcx, %r14
; SSE42-NEXT: cmoveq %rcx, %rbx
; SSE42-NEXT: cmoveq %rcx, %r11
; SSE42-NEXT: cmoveq %rcx, %r10
; SSE42-NEXT: cmoveq %rcx, %r9
; SSE42-NEXT: cmoveq %rcx, %r8
-; SSE42-NEXT: cmoveq %rcx, %rsi
-; SSE42-NEXT: cmoveq %rcx, %r14
-; SSE42-NEXT: movq %rdi, %rax
; SSE42-NEXT: cmoveq %rcx, %rdx
-; SSE42-NEXT: movq %rdx, 56(%rdi)
-; SSE42-NEXT: movq %rsi, 48(%rdi)
-; SSE42-NEXT: movq %r8, 40(%rdi)
-; SSE42-NEXT: movq %r9, 32(%rdi)
-; SSE42-NEXT: movq %r10, 24(%rdi)
-; SSE42-NEXT: movq %r11, 16(%rdi)
-; SSE42-NEXT: movq %rbx, 8(%rdi)
-; SSE42-NEXT: movq %r14, (%rdi)
+; SSE42-NEXT: movq %rdi, %rax
+; SSE42-NEXT: cmoveq %rcx, %rsi
+; SSE42-NEXT: movq %rsi, 56(%rdi)
+; SSE42-NEXT: movq %r8, 48(%rdi)
+; SSE42-NEXT: movq %r9, 40(%rdi)
+; SSE42-NEXT: movq %r10, 32(%rdi)
+; SSE42-NEXT: movq %r11, 24(%rdi)
+; SSE42-NEXT: movq %rbx, 16(%rdi)
+; SSE42-NEXT: movq %r14, 8(%rdi)
+; SSE42-NEXT: movq %rdx, (%rdi)
; SSE42-NEXT: popq %rbx
; SSE42-NEXT: popq %r14
; SSE42-NEXT: popq %r15
@@ -5210,37 +5205,37 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; AVX2-NEXT: lzcntq %r11, %r9
; AVX2-NEXT: xorl %ebx, %ebx
; AVX2-NEXT: lzcntq %r10, %rbx
-; AVX2-NEXT: addq $64, %rbx
+; AVX2-NEXT: addl $64, %ebx
; AVX2-NEXT: testq %r11, %r11
; AVX2-NEXT: cmovneq %r9, %rbx
; AVX2-NEXT: xorl %r14d, %r14d
; AVX2-NEXT: lzcntq %rdx, %r14
; AVX2-NEXT: xorl %r9d, %r9d
; AVX2-NEXT: lzcntq 32(%rsi), %r9
-; AVX2-NEXT: addq $64, %r9
+; AVX2-NEXT: addl $64, %r9d
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %r14, %r9
-; AVX2-NEXT: subq $-128, %r9
+; AVX2-NEXT: cmovnel %r14d, %r9d
+; AVX2-NEXT: subl $-128, %r9d
; AVX2-NEXT: orq %r11, %r10
; AVX2-NEXT: cmovneq %rbx, %r9
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: lzcntq %rcx, %rdx
; AVX2-NEXT: xorl %r10d, %r10d
; AVX2-NEXT: lzcntq %rax, %r10
-; AVX2-NEXT: addq $64, %r10
+; AVX2-NEXT: addl $64, %r10d
; AVX2-NEXT: testq %rcx, %rcx
-; AVX2-NEXT: cmovneq %rdx, %r10
+; AVX2-NEXT: cmovnel %edx, %r10d
; AVX2-NEXT: xorl %r11d, %r11d
; AVX2-NEXT: lzcntq %r8, %r11
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: lzcntq (%rsi), %rdx
-; AVX2-NEXT: addq $64, %rdx
+; AVX2-NEXT: addl $64, %edx
; AVX2-NEXT: testq %r8, %r8
-; AVX2-NEXT: cmovneq %r11, %rdx
-; AVX2-NEXT: subq $-128, %rdx
+; AVX2-NEXT: cmovnel %r11d, %edx
+; AVX2-NEXT: subl $-128, %edx
; AVX2-NEXT: orq %rcx, %rax
-; AVX2-NEXT: cmovneq %r10, %rdx
-; AVX2-NEXT: addq $256, %rdx # imm = 0x100
+; AVX2-NEXT: cmovnel %r10d, %edx
+; AVX2-NEXT: addl $256, %edx # imm = 0x100
; AVX2-NEXT: vpor 48(%rsi), %xmm1, %xmm1
; AVX2-NEXT: vptest %xmm1, %xmm1
; AVX2-NEXT: cmovneq %r9, %rdx
@@ -5313,7 +5308,7 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; AVX512F-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovq %xmm0, %rdx
; AVX512F-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
@@ -5342,7 +5337,7 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; AVX512VL-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VL-NEXT: vmovq %xmm0, %rdx
; AVX512VL-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
@@ -5372,7 +5367,7 @@ define i512 @isolate_msb_i512_load(ptr %p0, i512 %idx) nounwind {
; AVX512VBMI-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512VBMI-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VBMI-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VBMI-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VBMI-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VBMI-NEXT: vmovq %xmm0, %rdx
; AVX512VBMI-NEXT: movabsq $-9223372036854775808, %rsi # imm = 0x8000000000000000
diff --git a/llvm/test/CodeGen/X86/bitcnt-big-integer.ll b/llvm/test/CodeGen/X86/bitcnt-big-integer.ll
index 5c9a9338bc32f..a0f83d8ac048a 100644
--- a/llvm/test/CodeGen/X86/bitcnt-big-integer.ll
+++ b/llvm/test/CodeGen/X86/bitcnt-big-integer.ll
@@ -123,84 +123,78 @@ define i32 @vector_ctpop_i128(<4 x i32> %v0) nounwind {
define <2 x i32> @load_ctpop_v2i128(ptr %p0) nounwind {
; SSE-LABEL: load_ctpop_v2i128:
; SSE: # %bb.0:
-; SSE-NEXT: popcntq 8(%rdi), %rax
-; SSE-NEXT: popcntq (%rdi), %rcx
-; SSE-NEXT: popcntq 24(%rdi), %rdx
+; SSE-NEXT: popcntq 24(%rdi), %rax
+; SSE-NEXT: popcntq 16(%rdi), %rcx
+; SSE-NEXT: popcntq 8(%rdi), %rdx
; SSE-NEXT: addl %eax, %ecx
; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: popcntq 16(%rdi), %rax
+; SSE-NEXT: popcntq (%rdi), %rax
; SSE-NEXT: addl %edx, %eax
-; SSE-NEXT: movd %eax, %xmm1
-; SSE-NEXT: movd %ecx, %xmm0
-; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: pinsrd $1, %ecx, %xmm0
; SSE-NEXT: retq
;
; AVX2-LABEL: load_ctpop_v2i128:
; AVX2: # %bb.0:
-; AVX2-NEXT: popcntq 8(%rdi), %rax
-; AVX2-NEXT: popcntq (%rdi), %rcx
+; AVX2-NEXT: popcntq 24(%rdi), %rax
+; AVX2-NEXT: popcntq 16(%rdi), %rcx
; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: popcntq 24(%rdi), %rax
-; AVX2-NEXT: popcntq 16(%rdi), %rdx
+; AVX2-NEXT: popcntq 8(%rdi), %rax
+; AVX2-NEXT: popcntq (%rdi), %rdx
; AVX2-NEXT: addl %eax, %edx
; AVX2-NEXT: vmovd %edx, %xmm0
-; AVX2-NEXT: vmovd %ecx, %xmm1
-; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; AVX2-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: load_ctpop_v2i128:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: popcntq 8(%rdi), %rax
-; AVX512F-NEXT: popcntq (%rdi), %rcx
-; AVX512F-NEXT: addl %eax, %ecx
; AVX512F-NEXT: popcntq 24(%rdi), %rax
-; AVX512F-NEXT: popcntq 16(%rdi), %rdx
+; AVX512F-NEXT: popcntq 16(%rdi), %rcx
+; AVX512F-NEXT: addl %eax, %ecx
+; AVX512F-NEXT: popcntq 8(%rdi), %rax
+; AVX512F-NEXT: popcntq (%rdi), %rdx
; AVX512F-NEXT: addl %eax, %edx
; AVX512F-NEXT: vmovd %edx, %xmm0
-; AVX512F-NEXT: vmovd %ecx, %xmm1
-; AVX512F-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; AVX512F-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; AVX512F-NEXT: retq
;
; AVX512POPCNT-LABEL: load_ctpop_v2i128:
; AVX512POPCNT: # %bb.0:
-; AVX512POPCNT-NEXT: popcntq 8(%rdi), %rax
-; AVX512POPCNT-NEXT: popcntq (%rdi), %rcx
-; AVX512POPCNT-NEXT: addl %eax, %ecx
; AVX512POPCNT-NEXT: popcntq 24(%rdi), %rax
-; AVX512POPCNT-NEXT: popcntq 16(%rdi), %rdx
+; AVX512POPCNT-NEXT: popcntq 16(%rdi), %rcx
+; AVX512POPCNT-NEXT: addl %eax, %ecx
+; AVX512POPCNT-NEXT: popcntq 8(%rdi), %rax
+; AVX512POPCNT-NEXT: popcntq (%rdi), %rdx
; AVX512POPCNT-NEXT: addl %eax, %edx
; AVX512POPCNT-NEXT: vmovd %edx, %xmm0
-; AVX512POPCNT-NEXT: vmovd %ecx, %xmm1
-; AVX512POPCNT-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; AVX512POPCNT-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; AVX512POPCNT-NEXT: retq
;
; AVX512VL-LABEL: load_ctpop_v2i128:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: popcntq 8(%rdi), %rax
-; AVX512VL-NEXT: popcntq (%rdi), %rcx
+; AVX512VL-NEXT: popcntq 24(%rdi), %rax
+; AVX512VL-NEXT: popcntq 16(%rdi), %rcx
; AVX512VL-NEXT: addl %eax, %ecx
; AVX512VL-NEXT: xorl %eax, %eax
-; AVX512VL-NEXT: popcntq 24(%rdi), %rax
-; AVX512VL-NEXT: popcntq 16(%rdi), %rdx
+; AVX512VL-NEXT: popcntq 8(%rdi), %rax
+; AVX512VL-NEXT: popcntq (%rdi), %rdx
; AVX512VL-NEXT: addl %eax, %edx
; AVX512VL-NEXT: vmovd %edx, %xmm0
-; AVX512VL-NEXT: vmovd %ecx, %xmm1
-; AVX512VL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; AVX512VL-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512VLPOPCNT-LABEL: load_ctpop_v2i128:
; AVX512VLPOPCNT: # %bb.0:
-; AVX512VLPOPCNT-NEXT: popcntq 8(%rdi), %rax
-; AVX512VLPOPCNT-NEXT: popcntq (%rdi), %rcx
+; AVX512VLPOPCNT-NEXT: popcntq 24(%rdi), %rax
+; AVX512VLPOPCNT-NEXT: popcntq 16(%rdi), %rcx
; AVX512VLPOPCNT-NEXT: addl %eax, %ecx
; AVX512VLPOPCNT-NEXT: xorl %eax, %eax
-; AVX512VLPOPCNT-NEXT: popcntq 24(%rdi), %rax
-; AVX512VLPOPCNT-NEXT: popcntq 16(%rdi), %rdx
+; AVX512VLPOPCNT-NEXT: popcntq 8(%rdi), %rax
+; AVX512VLPOPCNT-NEXT: popcntq (%rdi), %rdx
; AVX512VLPOPCNT-NEXT: addl %eax, %edx
; AVX512VLPOPCNT-NEXT: vmovd %edx, %xmm0
-; AVX512VLPOPCNT-NEXT: vmovd %ecx, %xmm1
-; AVX512VLPOPCNT-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; AVX512VLPOPCNT-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; AVX512VLPOPCNT-NEXT: retq
%a0 = load <2 x i128>, ptr %p0
%cnt = call <2 x i128> @llvm.ctpop.v2i128(<2 x i128> %a0)
@@ -211,28 +205,25 @@ define <2 x i32> @load_ctpop_v2i128(ptr %p0) nounwind {
define <4 x i32> @load_ctpop_v4i128(ptr %p0) nounwind {
; SSE-LABEL: load_ctpop_v4i128:
; SSE: # %bb.0:
-; SSE-NEXT: popcntq 8(%rdi), %rax
-; SSE-NEXT: popcntq (%rdi), %rcx
-; SSE-NEXT: popcntq 24(%rdi), %rdx
-; SSE-NEXT: popcntq 16(%rdi), %rsi
-; SSE-NEXT: addl %eax, %ecx
-; SSE-NEXT: addl %edx, %esi
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: popcntq 40(%rdi), %rax
-; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: popcntq 56(%rdi), %rax
+; SSE-NEXT: popcntq 40(%rdi), %rcx
; SSE-NEXT: popcntq 32(%rdi), %rdx
-; SSE-NEXT: popcntq 56(%rdi), %r8
-; SSE-NEXT: addl %eax, %edx
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: popcntq 48(%rdi), %rax
-; SSE-NEXT: addl %r8d, %eax
-; SSE-NEXT: movd %eax, %xmm0
-; SSE-NEXT: movd %edx, %xmm1
-; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; SSE-NEXT: movd %esi, %xmm2
-; SSE-NEXT: movd %ecx, %xmm0
-; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE-NEXT: popcntq 24(%rdi), %rsi
+; SSE-NEXT: addl %ecx, %edx
+; SSE-NEXT: xorl %ecx, %ecx
+; SSE-NEXT: popcntq 16(%rdi), %rcx
+; SSE-NEXT: addl %esi, %ecx
+; SSE-NEXT: xorl %esi, %esi
+; SSE-NEXT: popcntq 8(%rdi), %rsi
+; SSE-NEXT: popcntq (%rdi), %r8
+; SSE-NEXT: addl %esi, %r8d
+; SSE-NEXT: xorl %esi, %esi
+; SSE-NEXT: popcntq 48(%rdi), %rsi
+; SSE-NEXT: movd %r8d, %xmm0
+; SSE-NEXT: pinsrd $1, %ecx, %xmm0
+; SSE-NEXT: pinsrd $2, %edx, %xmm0
+; SSE-NEXT: addl %eax, %esi
+; SSE-NEXT: pinsrd $3, %esi, %xmm0
; SSE-NEXT: retq
;
; AVX2-LABEL: load_ctpop_v4i128:
@@ -243,137 +234,105 @@ define <4 x i32> @load_ctpop_v4i128(ptr %p0) nounwind {
; AVX2-NEXT: xorl %eax, %eax
; AVX2-NEXT: popcntq 40(%rdi), %rax
; AVX2-NEXT: popcntq 32(%rdi), %rdx
-; AVX2-NEXT: popcntq 8(%rdi), %rsi
-; AVX2-NEXT: popcntq (%rdi), %r8
+; AVX2-NEXT: popcntq 24(%rdi), %rsi
; AVX2-NEXT: addl %eax, %edx
-; AVX2-NEXT: addl %esi, %r8d
; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: popcntq 24(%rdi), %rax
+; AVX2-NEXT: popcntq 16(%rdi), %rax
+; AVX2-NEXT: addl %esi, %eax
; AVX2-NEXT: xorl %esi, %esi
-; AVX2-NEXT: popcntq 16(%rdi), %rsi
-; AVX2-NEXT: addl %eax, %esi
-; AVX2-NEXT: vmovd %esi, %xmm0
-; AVX2-NEXT: vmovd %r8d, %xmm1
-; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; AVX2-NEXT: vmovd %edx, %xmm1
-; AVX2-NEXT: vmovd %ecx, %xmm2
-; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
-; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [0,4,0,4]
-; AVX2-NEXT: vpermd %ymm1, %ymm2, %ymm1
-; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
-; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: popcntq 8(%rdi), %rsi
+; AVX2-NEXT: popcntq (%rdi), %rdi
+; AVX2-NEXT: addl %esi, %edi
+; AVX2-NEXT: vmovd %edi, %xmm0
+; AVX2-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: load_ctpop_v4i128:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: popcntq 24(%rdi), %rcx
+; AVX512F-NEXT: popcntq 56(%rdi), %rax
+; AVX512F-NEXT: popcntq 48(%rdi), %rcx
+; AVX512F-NEXT: addl %eax, %ecx
+; AVX512F-NEXT: popcntq 40(%rdi), %rax
+; AVX512F-NEXT: popcntq 32(%rdi), %rdx
+; AVX512F-NEXT: popcntq 24(%rdi), %rsi
+; AVX512F-NEXT: addl %eax, %edx
; AVX512F-NEXT: popcntq 16(%rdi), %rax
-; AVX512F-NEXT: addl %ecx, %eax
-; AVX512F-NEXT: popcntq 8(%rdi), %rcx
-; AVX512F-NEXT: popcntq (%rdi), %rdx
-; AVX512F-NEXT: popcntq 40(%rdi), %rsi
-; AVX512F-NEXT: popcntq 32(%rdi), %r8
-; AVX512F-NEXT: addl %ecx, %edx
-; AVX512F-NEXT: addl %esi, %r8d
-; AVX512F-NEXT: popcntq 56(%rdi), %rcx
-; AVX512F-NEXT: popcntq 48(%rdi), %rsi
-; AVX512F-NEXT: addl %ecx, %esi
-; AVX512F-NEXT: vpbroadcastq {{.*#+}} xmm0 = [0,16,0,16]
-; AVX512F-NEXT: vmovd %esi, %xmm1
-; AVX512F-NEXT: vmovd %r8d, %xmm2
-; AVX512F-NEXT: vpermt2d %zmm1, %zmm0, %zmm2
-; AVX512F-NEXT: vmovd %edx, %xmm0
-; AVX512F-NEXT: vmovd %eax, %xmm1
-; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
-; AVX512F-NEXT: vmovdqa {{.*#+}} xmm0 = [0,4,18,19]
-; AVX512F-NEXT: vpermi2d %zmm2, %zmm1, %zmm0
-; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
+; AVX512F-NEXT: addl %esi, %eax
+; AVX512F-NEXT: popcntq 8(%rdi), %rsi
+; AVX512F-NEXT: popcntq (%rdi), %rdi
+; AVX512F-NEXT: addl %esi, %edi
+; AVX512F-NEXT: vmovd %edi, %xmm0
+; AVX512F-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
+; AVX512F-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
+; AVX512F-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
; AVX512F-NEXT: retq
;
; AVX512POPCNT-LABEL: load_ctpop_v4i128:
; AVX512POPCNT: # %bb.0:
-; AVX512POPCNT-NEXT: popcntq 24(%rdi), %rcx
+; AVX512POPCNT-NEXT: popcntq 56(%rdi), %rax
+; AVX512POPCNT-NEXT: popcntq 48(%rdi), %rcx
+; AVX512POPCNT-NEXT: addl %eax, %ecx
+; AVX512POPCNT-NEXT: popcntq 40(%rdi), %rax
+; AVX512POPCNT-NEXT: popcntq 32(%rdi), %rdx
+; AVX512POPCNT-NEXT: popcntq 24(%rdi), %rsi
+; AVX512POPCNT-NEXT: addl %eax, %edx
; AVX512POPCNT-NEXT: popcntq 16(%rdi), %rax
-; AVX512POPCNT-NEXT: addl %ecx, %eax
-; AVX512POPCNT-NEXT: popcntq 8(%rdi), %rcx
-; AVX512POPCNT-NEXT: popcntq (%rdi), %rdx
-; AVX512POPCNT-NEXT: popcntq 40(%rdi), %rsi
-; AVX512POPCNT-NEXT: popcntq 32(%rdi), %r8
-; AVX512POPCNT-NEXT: addl %ecx, %edx
-; AVX512POPCNT-NEXT: addl %esi, %r8d
-; AVX512POPCNT-NEXT: popcntq 56(%rdi), %rcx
-; AVX512POPCNT-NEXT: popcntq 48(%rdi), %rsi
-; AVX512POPCNT-NEXT: addl %ecx, %esi
-; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} xmm0 = [0,16,0,16]
-; AVX512POPCNT-NEXT: vmovd %esi, %xmm1
-; AVX512POPCNT-NEXT: vmovd %r8d, %xmm2
-; AVX512POPCNT-NEXT: vpermt2d %zmm1, %zmm0, %zmm2
-; AVX512POPCNT-NEXT: vmovd %edx, %xmm0
-; AVX512POPCNT-NEXT: vmovd %eax, %xmm1
-; AVX512POPCNT-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
-; AVX512POPCNT-NEXT: vmovdqa {{.*#+}} xmm0 = [0,4,18,19]
-; AVX512POPCNT-NEXT: vpermi2d %zmm2, %zmm1, %zmm0
-; AVX512POPCNT-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
+; AVX512POPCNT-NEXT: addl %esi, %eax
+; AVX512POPCNT-NEXT: popcntq 8(%rdi), %rsi
+; AVX512POPCNT-NEXT: popcntq (%rdi), %rdi
+; AVX512POPCNT-NEXT: addl %esi, %edi
+; AVX512POPCNT-NEXT: vmovd %edi, %xmm0
+; AVX512POPCNT-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
+; AVX512POPCNT-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
+; AVX512POPCNT-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
; AVX512POPCNT-NEXT: retq
;
; AVX512VL-LABEL: load_ctpop_v4i128:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: popcntq 24(%rdi), %rcx
-; AVX512VL-NEXT: popcntq 16(%rdi), %rax
-; AVX512VL-NEXT: addl %ecx, %eax
-; AVX512VL-NEXT: xorl %ecx, %ecx
-; AVX512VL-NEXT: popcntq 8(%rdi), %rcx
-; AVX512VL-NEXT: popcntq (%rdi), %rdx
-; AVX512VL-NEXT: popcntq 40(%rdi), %rsi
-; AVX512VL-NEXT: popcntq 32(%rdi), %r8
-; AVX512VL-NEXT: addl %ecx, %edx
-; AVX512VL-NEXT: addl %esi, %r8d
-; AVX512VL-NEXT: xorl %ecx, %ecx
-; AVX512VL-NEXT: popcntq 56(%rdi), %rcx
-; AVX512VL-NEXT: xorl %esi, %esi
-; AVX512VL-NEXT: popcntq 48(%rdi), %rsi
-; AVX512VL-NEXT: addl %ecx, %esi
-; AVX512VL-NEXT: vmovd %esi, %xmm0
-; AVX512VL-NEXT: vmovd %r8d, %xmm1
-; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm2 = [0,4,0,4]
-; AVX512VL-NEXT: vpermi2d %xmm0, %xmm1, %xmm2
-; AVX512VL-NEXT: vmovd %edx, %xmm0
-; AVX512VL-NEXT: vmovd %eax, %xmm1
-; AVX512VL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
-; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm0 = [0,4,10,11]
-; AVX512VL-NEXT: vpermi2d %ymm2, %ymm1, %ymm0
-; AVX512VL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
-; AVX512VL-NEXT: vzeroupper
+; AVX512VL-NEXT: popcntq 56(%rdi), %rax
+; AVX512VL-NEXT: popcntq 48(%rdi), %rcx
+; AVX512VL-NEXT: addl %eax, %ecx
+; AVX512VL-NEXT: xorl %eax, %eax
+; AVX512VL-NEXT: popcntq 40(%rdi), %rax
+; AVX512VL-NEXT: popcntq 32(%rdi), %rdx
+; AVX512VL-NEXT: addl %eax, %edx
+; AVX512VL-NEXT: xorl %eax, %eax
+; AVX512VL-NEXT: popcntq 24(%rdi), %rax
+; AVX512VL-NEXT: popcntq 16(%rdi), %rsi
+; AVX512VL-NEXT: addl %eax, %esi
+; AVX512VL-NEXT: xorl %eax, %eax
+; AVX512VL-NEXT: popcntq 8(%rdi), %rax
+; AVX512VL-NEXT: popcntq (%rdi), %rdi
+; AVX512VL-NEXT: addl %eax, %edi
+; AVX512VL-NEXT: vmovd %edi, %xmm0
+; AVX512VL-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
+; AVX512VL-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
+; AVX512VL-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512VLPOPCNT-LABEL: load_ctpop_v4i128:
; AVX512VLPOPCNT: # %bb.0:
-; AVX512VLPOPCNT-NEXT: popcntq 24(%rdi), %rcx
-; AVX512VLPOPCNT-NEXT: popcntq 16(%rdi), %rax
-; AVX512VLPOPCNT-NEXT: addl %ecx, %eax
-; AVX512VLPOPCNT-NEXT: xorl %ecx, %ecx
-; AVX512VLPOPCNT-NEXT: popcntq 8(%rdi), %rcx
-; AVX512VLPOPCNT-NEXT: popcntq (%rdi), %rdx
-; AVX512VLPOPCNT-NEXT: popcntq 40(%rdi), %rsi
-; AVX512VLPOPCNT-NEXT: popcntq 32(%rdi), %r8
-; AVX512VLPOPCNT-NEXT: addl %ecx, %edx
-; AVX512VLPOPCNT-NEXT: addl %esi, %r8d
-; AVX512VLPOPCNT-NEXT: xorl %ecx, %ecx
-; AVX512VLPOPCNT-NEXT: popcntq 56(%rdi), %rcx
-; AVX512VLPOPCNT-NEXT: xorl %esi, %esi
-; AVX512VLPOPCNT-NEXT: popcntq 48(%rdi), %rsi
-; AVX512VLPOPCNT-NEXT: addl %ecx, %esi
-; AVX512VLPOPCNT-NEXT: vmovd %esi, %xmm0
-; AVX512VLPOPCNT-NEXT: vmovd %r8d, %xmm1
-; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} xmm2 = [0,4,0,4]
-; AVX512VLPOPCNT-NEXT: vpermi2d %xmm0, %xmm1, %xmm2
-; AVX512VLPOPCNT-NEXT: vmovd %edx, %xmm0
-; AVX512VLPOPCNT-NEXT: vmovd %eax, %xmm1
-; AVX512VLPOPCNT-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
-; AVX512VLPOPCNT-NEXT: vmovdqa {{.*#+}} xmm0 = [0,4,10,11]
-; AVX512VLPOPCNT-NEXT: vpermi2d %ymm2, %ymm1, %ymm0
-; AVX512VLPOPCNT-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
-; AVX512VLPOPCNT-NEXT: vzeroupper
+; AVX512VLPOPCNT-NEXT: popcntq 56(%rdi), %rax
+; AVX512VLPOPCNT-NEXT: popcntq 48(%rdi), %rcx
+; AVX512VLPOPCNT-NEXT: addl %eax, %ecx
+; AVX512VLPOPCNT-NEXT: xorl %eax, %eax
+; AVX512VLPOPCNT-NEXT: popcntq 40(%rdi), %rax
+; AVX512VLPOPCNT-NEXT: popcntq 32(%rdi), %rdx
+; AVX512VLPOPCNT-NEXT: addl %eax, %edx
+; AVX512VLPOPCNT-NEXT: xorl %eax, %eax
+; AVX512VLPOPCNT-NEXT: popcntq 24(%rdi), %rax
+; AVX512VLPOPCNT-NEXT: popcntq 16(%rdi), %rsi
+; AVX512VLPOPCNT-NEXT: addl %eax, %esi
+; AVX512VLPOPCNT-NEXT: xorl %eax, %eax
+; AVX512VLPOPCNT-NEXT: popcntq 8(%rdi), %rax
+; AVX512VLPOPCNT-NEXT: popcntq (%rdi), %rdi
+; AVX512VLPOPCNT-NEXT: addl %eax, %edi
+; AVX512VLPOPCNT-NEXT: vmovd %edi, %xmm0
+; AVX512VLPOPCNT-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
+; AVX512VLPOPCNT-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
+; AVX512VLPOPCNT-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
; AVX512VLPOPCNT-NEXT: retq
%a0 = load <4 x i128>, ptr %p0
%cnt = call <4 x i128> @llvm.ctpop.v4i128(<4 x i128> %a0)
@@ -635,52 +594,50 @@ define i32 @vector_ctpop_i256(<8 x i32> %v0) nounwind {
define <2 x i32> @load_ctpop_v2i256_v2i32(ptr %p0) nounwind {
; SSE-LABEL: load_ctpop_v2i256_v2i32:
; SSE: # %bb.0:
-; SSE-NEXT: popcntq 24(%rdi), %rax
-; SSE-NEXT: popcntq 16(%rdi), %rcx
-; SSE-NEXT: popcntq 8(%rdi), %rdx
+; SSE-NEXT: popcntq 56(%rdi), %rax
+; SSE-NEXT: popcntq 48(%rdi), %rcx
+; SSE-NEXT: popcntq 40(%rdi), %rdx
; SSE-NEXT: addl %eax, %ecx
; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: popcntq (%rdi), %rax
+; SSE-NEXT: popcntq 32(%rdi), %rax
; SSE-NEXT: addl %edx, %eax
; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: popcntq 56(%rdi), %rdx
-; SSE-NEXT: popcntq 48(%rdi), %rsi
+; SSE-NEXT: popcntq 24(%rdi), %rdx
+; SSE-NEXT: popcntq 16(%rdi), %rsi
; SSE-NEXT: addl %ecx, %eax
; SSE-NEXT: addl %edx, %esi
; SSE-NEXT: xorl %ecx, %ecx
-; SSE-NEXT: popcntq 40(%rdi), %rcx
+; SSE-NEXT: popcntq 8(%rdi), %rcx
; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: popcntq 32(%rdi), %rdx
+; SSE-NEXT: popcntq (%rdi), %rdx
; SSE-NEXT: addl %ecx, %edx
; SSE-NEXT: addl %esi, %edx
-; SSE-NEXT: movd %edx, %xmm1
-; SSE-NEXT: movd %eax, %xmm0
-; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE-NEXT: movd %edx, %xmm0
+; SSE-NEXT: pinsrd $1, %eax, %xmm0
; SSE-NEXT: retq
;
; AVX2-LABEL: load_ctpop_v2i256_v2i32:
; AVX2: # %bb.0:
-; AVX2-NEXT: popcntq 24(%rdi), %rax
-; AVX2-NEXT: popcntq 16(%rdi), %rcx
+; AVX2-NEXT: popcntq 56(%rdi), %rax
+; AVX2-NEXT: popcntq 48(%rdi), %rcx
; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: popcntq 8(%rdi), %rax
-; AVX2-NEXT: popcntq (%rdi), %rdx
+; AVX2-NEXT: popcntq 40(%rdi), %rax
+; AVX2-NEXT: popcntq 32(%rdi), %rdx
; AVX2-NEXT: addl %eax, %edx
; AVX2-NEXT: addl %ecx, %edx
; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: popcntq 56(%rdi), %rax
+; AVX2-NEXT: popcntq 24(%rdi), %rax
; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: popcntq 48(%rdi), %rcx
-; AVX2-NEXT: popcntq 40(%rdi), %rsi
+; AVX2-NEXT: popcntq 16(%rdi), %rcx
+; AVX2-NEXT: popcntq 8(%rdi), %rsi
; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: popcntq 32(%rdi), %rax
+; AVX2-NEXT: popcntq (%rdi), %rax
; AVX2-NEXT: addl %esi, %eax
; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: vmovd %eax, %xmm0
-; AVX2-NEXT: vmovd %edx, %xmm1
-; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; AVX2-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: load_ctpop_v2i256_v2i32:
@@ -2018,7 +1975,7 @@ define i32 @load_ctlz_i256(ptr %p0) nounwind {
; AVX512F-NEXT: vpbroadcastq {{.*#+}} ymm0 = [256,256,256,256]
; AVX512F-NEXT: vpermq {{.*#+}} ymm1 = mem[3,2,1,0]
; AVX512F-NEXT: vplzcntq %zmm1, %zmm2
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [0,64,128,192]
; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
@@ -2031,7 +1988,7 @@ define i32 @load_ctlz_i256(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} ymm0 = [256,256,256,256]
; AVX512POPCNT-NEXT: vpermq {{.*#+}} ymm1 = mem[3,2,1,0]
; AVX512POPCNT-NEXT: vplzcntq %zmm1, %zmm2
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [0,64,128,192]
; AVX512POPCNT-NEXT: vptestmq %zmm1, %zmm1, %k0
; AVX512POPCNT-NEXT: kshiftlw $12, %k0, %k0
; AVX512POPCNT-NEXT: kshiftrw $12, %k0, %k1
@@ -2043,7 +2000,7 @@ define i32 @load_ctlz_i256(ptr %p0) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512VL-NEXT: vplzcntq %ymm0, %ymm1
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VL-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm0 = [256,256,256,256]
; AVX512VL-NEXT: vpcompressq %ymm1, %ymm0 {%k1}
@@ -2055,7 +2012,7 @@ define i32 @load_ctlz_i256(ptr %p0) nounwind {
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512VLPOPCNT-NEXT: vplzcntq %ymm0, %ymm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} ymm0 = [256,256,256,256]
; AVX512VLPOPCNT-NEXT: vpcompressq %ymm1, %ymm0 {%k1}
@@ -2126,7 +2083,7 @@ define i32 @vector_ctlz_i256(<8 x i32> %v0) nounwind {
; AVX512F-NEXT: vpbroadcastq {{.*#+}} ymm1 = [256,256,256,256]
; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512F-NEXT: vplzcntq %zmm0, %zmm2
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [0,64,128,192]
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
@@ -2139,7 +2096,7 @@ define i32 @vector_ctlz_i256(<8 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} ymm1 = [256,256,256,256]
; AVX512POPCNT-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm2
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [0,64,128,192]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512POPCNT-NEXT: kshiftlw $12, %k0, %k0
; AVX512POPCNT-NEXT: kshiftrw $12, %k0, %k1
@@ -2151,7 +2108,7 @@ define i32 @vector_ctlz_i256(<8 x i32> %v0) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512VL-NEXT: vplzcntq %ymm0, %ymm1
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VL-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm0 = [256,256,256,256]
; AVX512VL-NEXT: vpcompressq %ymm1, %ymm0 {%k1}
@@ -2163,7 +2120,7 @@ define i32 @vector_ctlz_i256(<8 x i32> %v0) nounwind {
; AVX512VLPOPCNT: # %bb.0:
; AVX512VLPOPCNT-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512VLPOPCNT-NEXT: vplzcntq %ymm0, %ymm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} ymm0 = [256,256,256,256]
; AVX512VLPOPCNT-NEXT: vpcompressq %ymm1, %ymm0 {%k1}
@@ -2300,7 +2257,7 @@ define i32 @test_ctlz_i512(i512 %a0) nounwind {
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpbroadcastq {{.*#+}} zmm1 = [512,512,512,512,512,512,512,512]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm1 {%k1}
; AVX512F-NEXT: vmovd %xmm1, %eax
@@ -2323,7 +2280,7 @@ define i32 @test_ctlz_i512(i512 %a0) nounwind {
; AVX512POPCNT-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} zmm1 = [512,512,512,512,512,512,512,512]
; AVX512POPCNT-NEXT: vpcompressq %zmm0, %zmm1 {%k1}
; AVX512POPCNT-NEXT: vmovd %xmm1, %eax
@@ -2345,7 +2302,7 @@ define i32 @test_ctlz_i512(i512 %a0) nounwind {
; AVX512VL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VL-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -2369,7 +2326,7 @@ define i32 @test_ctlz_i512(i512 %a0) nounwind {
; AVX512VLPOPCNT-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX512VLPOPCNT-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512VLPOPCNT-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -2486,7 +2443,7 @@ define i32 @load_ctlz_i512(ptr %p0) nounwind {
; AVX512F-NEXT: vpermq (%rdi), %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpbroadcastq {{.*#+}} zmm1 = [512,512,512,512,512,512,512,512]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm1 {%k1}
; AVX512F-NEXT: vmovd %xmm1, %eax
@@ -2498,7 +2455,7 @@ define i32 @load_ctlz_i512(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vpermq (%rdi), %zmm0, %zmm0
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} zmm1 = [512,512,512,512,512,512,512,512]
; AVX512POPCNT-NEXT: vpcompressq %zmm0, %zmm1 {%k1}
; AVX512POPCNT-NEXT: vmovd %xmm1, %eax
@@ -2509,7 +2466,7 @@ define i32 @load_ctlz_i512(ptr %p0) nounwind {
; AVX512VL-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,6,5,4,3,2,1,0]
; AVX512VL-NEXT: vpermq (%rdi), %zmm0, %zmm0
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VL-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -2522,7 +2479,7 @@ define i32 @load_ctlz_i512(ptr %p0) nounwind {
; AVX512VLPOPCNT-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,6,5,4,3,2,1,0]
; AVX512VLPOPCNT-NEXT: vpermq (%rdi), %zmm0, %zmm0
; AVX512VLPOPCNT-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -2643,7 +2600,7 @@ define i32 @vector_ctlz_i512(<16 x i32> %v0) nounwind {
; AVX512F-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpbroadcastq {{.*#+}} zmm1 = [512,512,512,512,512,512,512,512]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm1 {%k1}
; AVX512F-NEXT: vmovd %xmm1, %eax
@@ -2655,7 +2612,7 @@ define i32 @vector_ctlz_i512(<16 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} zmm1 = [512,512,512,512,512,512,512,512]
; AVX512POPCNT-NEXT: vpcompressq %zmm0, %zmm1 {%k1}
; AVX512POPCNT-NEXT: vmovd %xmm1, %eax
@@ -2666,7 +2623,7 @@ define i32 @vector_ctlz_i512(<16 x i32> %v0) nounwind {
; AVX512VL-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; AVX512VL-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VL-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -2679,7 +2636,7 @@ define i32 @vector_ctlz_i512(<16 x i32> %v0) nounwind {
; AVX512VLPOPCNT-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; AVX512VLPOPCNT-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512VLPOPCNT-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -3643,7 +3600,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512F-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
@@ -3655,7 +3612,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512POPCNT-NEXT: kshiftlw $12, %k0, %k0
; AVX512POPCNT-NEXT: kshiftrw $12, %k0, %k1
@@ -3668,7 +3625,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512VL-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VL-NEXT: vplzcntq %ymm0, %ymm0
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [0,64,128,192]
; AVX512VL-NEXT: vpcompressq %ymm0, %ymm0 {%k1} {z}
; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
@@ -3679,7 +3636,7 @@ define i32 @load_ctlz_undef_i256(ptr %p0) nounwind {
; AVX512VLPOPCNT-NEXT: vpermq {{.*#+}} ymm0 = mem[3,2,1,0]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VLPOPCNT-NEXT: vplzcntq %ymm0, %ymm0
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [0,64,128,192]
; AVX512VLPOPCNT-NEXT: vpcompressq %ymm0, %ymm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VLPOPCNT-NEXT: vzeroupper
@@ -3746,7 +3703,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512F-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
@@ -3758,7 +3715,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512POPCNT: # %bb.0:
; AVX512POPCNT-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512POPCNT-NEXT: kshiftlw $12, %k0, %k0
; AVX512POPCNT-NEXT: kshiftrw $12, %k0, %k1
@@ -3771,7 +3728,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512VL-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VL-NEXT: vplzcntq %ymm0, %ymm0
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [0,64,128,192]
; AVX512VL-NEXT: vpcompressq %ymm0, %ymm0 {%k1} {z}
; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
@@ -3782,7 +3739,7 @@ define i32 @vector_ctlz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512VLPOPCNT-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VLPOPCNT-NEXT: vplzcntq %ymm0, %ymm0
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [0,64,128,192]
; AVX512VLPOPCNT-NEXT: vpcompressq %ymm0, %ymm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VLPOPCNT-NEXT: vzeroupper
@@ -3916,7 +3873,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
@@ -3938,7 +3895,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; AVX512POPCNT-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
@@ -3960,7 +3917,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; AVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
@@ -3983,7 +3940,7 @@ define i32 @test_ctlz_undef_i512(i512 %a0) nounwind {
; AVX512VLPOPCNT-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VLPOPCNT-NEXT: vzeroupper
@@ -4099,7 +4056,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; AVX512F-NEXT: vpermq (%rdi), %zmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
@@ -4110,7 +4067,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vpermq (%rdi), %zmm0, %zmm0
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
@@ -4121,7 +4078,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; AVX512VL-NEXT: vpermq (%rdi), %zmm0, %zmm0
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
@@ -4133,7 +4090,7 @@ define i32 @load_ctlz_undef_i512(ptr %p0) nounwind {
; AVX512VLPOPCNT-NEXT: vpermq (%rdi), %zmm0, %zmm0
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VLPOPCNT-NEXT: vzeroupper
@@ -4251,7 +4208,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512F-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512F-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
@@ -4262,7 +4219,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
; AVX512POPCNT-NEXT: retq
@@ -4273,7 +4230,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512VL-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VL-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VL-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
@@ -4285,7 +4242,7 @@ define i32 @vector_ctlz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512VLPOPCNT-NEXT: vpermq %zmm0, %zmm1, %zmm0
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vplzcntq %zmm0, %zmm0
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm0, %zmm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VLPOPCNT-NEXT: vzeroupper
@@ -5211,7 +5168,7 @@ define i32 @load_cttz_i256(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %ymm2, %ymm0, %ymm2
; AVX512POPCNT-NEXT: vpandn %ymm2, %ymm0, %ymm2
; AVX512POPCNT-NEXT: vpopcntq %zmm2, %zmm2
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [0,64,128,192]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512POPCNT-NEXT: kshiftlw $12, %k0, %k0
; AVX512POPCNT-NEXT: kshiftrw $12, %k0, %k1
@@ -5242,7 +5199,7 @@ define i32 @load_cttz_i256(ptr %p0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %ymm1, %ymm0, %ymm1
; AVX512VLPOPCNT-NEXT: vpandn %ymm1, %ymm0, %ymm1
; AVX512VLPOPCNT-NEXT: vpopcntq %ymm1, %ymm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} ymm0 = [256,256,256,256]
; AVX512VLPOPCNT-NEXT: vpcompressq %ymm1, %ymm0 {%k1}
@@ -5329,7 +5286,7 @@ define i32 @vector_cttz_i256(<8 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %ymm2, %ymm0, %ymm2
; AVX512POPCNT-NEXT: vpandn %ymm2, %ymm0, %ymm2
; AVX512POPCNT-NEXT: vpopcntq %zmm2, %zmm2
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [0,64,128,192]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512POPCNT-NEXT: kshiftlw $12, %k0, %k0
; AVX512POPCNT-NEXT: kshiftrw $12, %k0, %k1
@@ -5358,7 +5315,7 @@ define i32 @vector_cttz_i256(<8 x i32> %v0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %ymm1, %ymm0, %ymm1
; AVX512VLPOPCNT-NEXT: vpandn %ymm1, %ymm0, %ymm1
; AVX512VLPOPCNT-NEXT: vpopcntq %ymm1, %ymm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} ymm0 = [256,256,256,256]
; AVX512VLPOPCNT-NEXT: vpcompressq %ymm1, %ymm0 {%k1}
@@ -5506,7 +5463,7 @@ define i32 @test_cttz_i512(i512 %a0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512POPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -5558,7 +5515,7 @@ define i32 @test_cttz_i512(i512 %a0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -5683,7 +5640,7 @@ define i32 @load_cttz_i512(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512POPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -5713,7 +5670,7 @@ define i32 @load_cttz_i512(ptr %p0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -5840,7 +5797,7 @@ define i32 @vector_cttz_i512(<16 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512POPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -5868,7 +5825,7 @@ define i32 @vector_cttz_i512(<16 x i32> %v0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpbroadcastq {{.*#+}} zmm0 = [512,512,512,512,512,512,512,512]
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1}
@@ -6834,7 +6791,7 @@ define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %ymm1, %ymm0, %ymm1
; AVX512POPCNT-NEXT: vpandn %ymm1, %ymm0, %ymm1
; AVX512POPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512POPCNT-NEXT: kshiftlw $12, %k0, %k0
; AVX512POPCNT-NEXT: kshiftrw $12, %k0, %k1
@@ -6864,7 +6821,7 @@ define i32 @load_cttz_undef_i256(ptr %p0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %ymm1, %ymm0, %ymm1
; AVX512VLPOPCNT-NEXT: vpandn %ymm1, %ymm0, %ymm1
; AVX512VLPOPCNT-NEXT: vpopcntq %ymm1, %ymm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VLPOPCNT-NEXT: vpcompressq %ymm1, %ymm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
@@ -6947,7 +6904,7 @@ define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %ymm1, %ymm0, %ymm1
; AVX512POPCNT-NEXT: vpandn %ymm1, %ymm0, %ymm1
; AVX512POPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512POPCNT-NEXT: kshiftlw $12, %k0, %k0
; AVX512POPCNT-NEXT: kshiftrw $12, %k0, %k1
@@ -6975,7 +6932,7 @@ define i32 @vector_cttz_undef_i256(<8 x i32> %v0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %ymm1, %ymm0, %ymm1
; AVX512VLPOPCNT-NEXT: vpandn %ymm1, %ymm0, %ymm1
; AVX512VLPOPCNT-NEXT: vpopcntq %ymm1, %ymm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,64,128,192]
; AVX512VLPOPCNT-NEXT: vptestmq %ymm0, %ymm0, %k1
; AVX512VLPOPCNT-NEXT: vpcompressq %ymm1, %ymm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
@@ -7120,7 +7077,7 @@ define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1} {z}
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
@@ -7170,7 +7127,7 @@ define i32 @test_cttz_undef_i512(i512 %a0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
@@ -7294,7 +7251,7 @@ define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1} {z}
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
@@ -7322,7 +7279,7 @@ define i32 @load_cttz_undef_i512(ptr %p0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
@@ -7446,7 +7403,7 @@ define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512POPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512POPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512POPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512POPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512POPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1} {z}
; AVX512POPCNT-NEXT: vmovd %xmm0, %eax
@@ -7472,7 +7429,7 @@ define i32 @vector_cttz_undef_i512(<16 x i32> %v0) nounwind {
; AVX512VLPOPCNT-NEXT: vpaddq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpandnq %zmm1, %zmm0, %zmm1
; AVX512VLPOPCNT-NEXT: vpopcntq %zmm1, %zmm1
-; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512VLPOPCNT-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,64,128,192,256,320,384,448]
; AVX512VLPOPCNT-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512VLPOPCNT-NEXT: vpcompressq %zmm1, %zmm0 {%k1} {z}
; AVX512VLPOPCNT-NEXT: vmovd %xmm0, %eax
diff --git a/llvm/test/CodeGen/X86/bittest-big-integer.ll b/llvm/test/CodeGen/X86/bittest-big-integer.ll
index 96ccc7b0f7527..03bc9046fe9b8 100644
--- a/llvm/test/CodeGen/X86/bittest-big-integer.ll
+++ b/llvm/test/CodeGen/X86/bittest-big-integer.ll
@@ -1897,45 +1897,45 @@ define i32 @blsr_u512(ptr %word) nounwind {
; SSE2-NEXT: pushq %rbx
; SSE2-NEXT: movdqa (%rdi), %xmm0
; SSE2-NEXT: movq 48(%rdi), %r8
-; SSE2-NEXT: movq 40(%rdi), %rdx
-; SSE2-NEXT: movq 32(%rdi), %rsi
+; SSE2-NEXT: movq 40(%rdi), %rcx
+; SSE2-NEXT: movq 32(%rdi), %rdx
; SSE2-NEXT: movq (%rdi), %rax
; SSE2-NEXT: movq 8(%rdi), %r9
-; SSE2-NEXT: rep bsfq %rax, %rcx
+; SSE2-NEXT: rep bsfq %rax, %rsi
; SSE2-NEXT: rep bsfq %r9, %r10
-; SSE2-NEXT: addq $64, %r10
+; SSE2-NEXT: addl $64, %r10d
; SSE2-NEXT: testq %rax, %rax
-; SSE2-NEXT: cmovneq %rcx, %r10
+; SSE2-NEXT: cmovneq %rsi, %r10
; SSE2-NEXT: movq 16(%rdi), %r11
; SSE2-NEXT: rep bsfq %r11, %rbx
-; SSE2-NEXT: rep bsfq 24(%rdi), %rcx
-; SSE2-NEXT: addq $64, %rcx
+; SSE2-NEXT: rep bsfq 24(%rdi), %rsi
+; SSE2-NEXT: addl $64, %esi
; SSE2-NEXT: testq %r11, %r11
-; SSE2-NEXT: cmovneq %rbx, %rcx
-; SSE2-NEXT: subq $-128, %rcx
+; SSE2-NEXT: cmovnel %ebx, %esi
+; SSE2-NEXT: subl $-128, %esi
; SSE2-NEXT: orq %r9, %rax
-; SSE2-NEXT: cmovneq %r10, %rcx
-; SSE2-NEXT: rep bsfq %rsi, %rax
-; SSE2-NEXT: rep bsfq %rdx, %r9
-; SSE2-NEXT: addq $64, %r9
-; SSE2-NEXT: testq %rsi, %rsi
-; SSE2-NEXT: cmovneq %rax, %r9
+; SSE2-NEXT: cmovneq %r10, %rsi
+; SSE2-NEXT: rep bsfq %rdx, %rax
+; SSE2-NEXT: rep bsfq %rcx, %r9
+; SSE2-NEXT: addl $64, %r9d
+; SSE2-NEXT: testq %rdx, %rdx
+; SSE2-NEXT: cmovnel %eax, %r9d
; SSE2-NEXT: rep bsfq %r8, %r10
; SSE2-NEXT: movl $64, %eax
; SSE2-NEXT: rep bsfq 56(%rdi), %rax
-; SSE2-NEXT: addq $64, %rax
+; SSE2-NEXT: addl $64, %eax
; SSE2-NEXT: testq %r8, %r8
-; SSE2-NEXT: cmovneq %r10, %rax
-; SSE2-NEXT: subq $-128, %rax
-; SSE2-NEXT: orq %rdx, %rsi
-; SSE2-NEXT: cmovneq %r9, %rax
+; SSE2-NEXT: cmovnel %r10d, %eax
+; SSE2-NEXT: subl $-128, %eax
+; SSE2-NEXT: orq %rcx, %rdx
+; SSE2-NEXT: cmovnel %r9d, %eax
; SSE2-NEXT: por 16(%rdi), %xmm0
-; SSE2-NEXT: addq $256, %rax # imm = 0x100
+; SSE2-NEXT: addl $256, %eax # imm = 0x100
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
-; SSE2-NEXT: movmskps %xmm1, %edx
-; SSE2-NEXT: xorl $15, %edx
-; SSE2-NEXT: cmovneq %rcx, %rax
+; SSE2-NEXT: movmskps %xmm1, %ecx
+; SSE2-NEXT: xorl $15, %ecx
+; SSE2-NEXT: cmovneq %rsi, %rax
; SSE2-NEXT: movl $-2, %edx
; SSE2-NEXT: movl %eax, %ecx
; SSE2-NEXT: roll %cl, %edx
@@ -1956,34 +1956,34 @@ define i32 @blsr_u512(ptr %word) nounwind {
; SSE4-NEXT: movq 8(%rdi), %r8
; SSE4-NEXT: rep bsfq %rax, %rsi
; SSE4-NEXT: rep bsfq %r8, %r9
-; SSE4-NEXT: addq $64, %r9
+; SSE4-NEXT: addl $64, %r9d
; SSE4-NEXT: testq %rax, %rax
; SSE4-NEXT: cmovneq %rsi, %r9
; SSE4-NEXT: movq 16(%rdi), %r10
; SSE4-NEXT: rep bsfq %r10, %r11
; SSE4-NEXT: rep bsfq 24(%rdi), %rsi
-; SSE4-NEXT: addq $64, %rsi
+; SSE4-NEXT: addl $64, %esi
; SSE4-NEXT: testq %r10, %r10
-; SSE4-NEXT: cmovneq %r11, %rsi
-; SSE4-NEXT: subq $-128, %rsi
+; SSE4-NEXT: cmovnel %r11d, %esi
+; SSE4-NEXT: subl $-128, %esi
; SSE4-NEXT: orq %r8, %rax
; SSE4-NEXT: cmovneq %r9, %rsi
; SSE4-NEXT: movq 32(%rdi), %r8
; SSE4-NEXT: rep bsfq %r8, %rax
; SSE4-NEXT: rep bsfq %rcx, %r9
-; SSE4-NEXT: addq $64, %r9
+; SSE4-NEXT: addl $64, %r9d
; SSE4-NEXT: testq %r8, %r8
-; SSE4-NEXT: cmovneq %rax, %r9
+; SSE4-NEXT: cmovnel %eax, %r9d
; SSE4-NEXT: rep bsfq %rdx, %r10
; SSE4-NEXT: movl $64, %eax
; SSE4-NEXT: rep bsfq 56(%rdi), %rax
-; SSE4-NEXT: addq $64, %rax
+; SSE4-NEXT: addl $64, %eax
; SSE4-NEXT: testq %rdx, %rdx
-; SSE4-NEXT: cmovneq %r10, %rax
-; SSE4-NEXT: subq $-128, %rax
+; SSE4-NEXT: cmovnel %r10d, %eax
+; SSE4-NEXT: subl $-128, %eax
; SSE4-NEXT: orq %rcx, %r8
-; SSE4-NEXT: cmovneq %r9, %rax
-; SSE4-NEXT: addq $256, %rax # imm = 0x100
+; SSE4-NEXT: cmovnel %r9d, %eax
+; SSE4-NEXT: addl $256, %eax # imm = 0x100
; SSE4-NEXT: por 16(%rdi), %xmm0
; SSE4-NEXT: ptest %xmm0, %xmm0
; SSE4-NEXT: cmovneq %rsi, %rax
@@ -2009,37 +2009,37 @@ define i32 @blsr_u512(ptr %word) nounwind {
; AVX2-NEXT: movq 8(%rdi), %r10
; AVX2-NEXT: tzcntq %r9, %r8
; AVX2-NEXT: tzcntq %r10, %r11
-; AVX2-NEXT: addq $64, %r11
+; AVX2-NEXT: addl $64, %r11d
; AVX2-NEXT: testq %r9, %r9
; AVX2-NEXT: cmovneq %r8, %r11
; AVX2-NEXT: xorl %ebx, %ebx
; AVX2-NEXT: tzcntq %rax, %rbx
; AVX2-NEXT: xorl %r8d, %r8d
; AVX2-NEXT: tzcntq 24(%rdi), %r8
-; AVX2-NEXT: addq $64, %r8
+; AVX2-NEXT: addl $64, %r8d
; AVX2-NEXT: testq %rax, %rax
-; AVX2-NEXT: cmovneq %rbx, %r8
-; AVX2-NEXT: subq $-128, %r8
+; AVX2-NEXT: cmovnel %ebx, %r8d
+; AVX2-NEXT: subl $-128, %r8d
; AVX2-NEXT: orq %r10, %r9
; AVX2-NEXT: cmovneq %r11, %r8
; AVX2-NEXT: xorl %eax, %eax
; AVX2-NEXT: tzcntq %rdx, %rax
; AVX2-NEXT: xorl %r9d, %r9d
; AVX2-NEXT: tzcntq %rcx, %r9
-; AVX2-NEXT: addq $64, %r9
+; AVX2-NEXT: addl $64, %r9d
; AVX2-NEXT: testq %rdx, %rdx
-; AVX2-NEXT: cmovneq %rax, %r9
+; AVX2-NEXT: cmovnel %eax, %r9d
; AVX2-NEXT: xorl %r10d, %r10d
; AVX2-NEXT: tzcntq %rsi, %r10
; AVX2-NEXT: xorl %eax, %eax
; AVX2-NEXT: tzcntq 56(%rdi), %rax
-; AVX2-NEXT: addq $64, %rax
+; AVX2-NEXT: addl $64, %eax
; AVX2-NEXT: testq %rsi, %rsi
-; AVX2-NEXT: cmovneq %r10, %rax
-; AVX2-NEXT: subq $-128, %rax
+; AVX2-NEXT: cmovnel %r10d, %eax
+; AVX2-NEXT: subl $-128, %eax
; AVX2-NEXT: orq %rcx, %rdx
-; AVX2-NEXT: cmovneq %r9, %rax
-; AVX2-NEXT: addq $256, %rax # imm = 0x100
+; AVX2-NEXT: cmovnel %r9d, %eax
+; AVX2-NEXT: addl $256, %eax # imm = 0x100
; AVX2-NEXT: vpor 16(%rdi), %xmm0, %xmm0
; AVX2-NEXT: vptest %xmm0, %xmm0
; AVX2-NEXT: cmovneq %r8, %rax
diff --git a/llvm/test/CodeGen/X86/bsf.ll b/llvm/test/CodeGen/X86/bsf.ll
index f780f0172647f..8109bedd988af 100644
--- a/llvm/test/CodeGen/X86/bsf.ll
+++ b/llvm/test/CodeGen/X86/bsf.ll
@@ -342,7 +342,7 @@ define i128 @cmov_bsf128(i128 %x, i128 %y) nounwind {
; X64-NEXT: rep bsfq %rdi, %rcx
; X64-NEXT: movl $64, %eax
; X64-NEXT: rep bsfq %rsi, %rax
-; X64-NEXT: addq $64, %rax
+; X64-NEXT: addl $64, %eax
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: cmovneq %rcx, %rax
; X64-NEXT: xorl %edx, %edx
@@ -434,7 +434,7 @@ define i128 @cmov_bsf128_undef(i128 %x, i128 %y) nounwind {
; X64-NEXT: # %bb.1: # %select.true.sink
; X64-NEXT: rep bsfq %rdi, %rcx
; X64-NEXT: rep bsfq %rsi, %rax
-; X64-NEXT: addq $64, %rax
+; X64-NEXT: addl $64, %eax
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: cmovneq %rcx, %rax
; X64-NEXT: xorl %edx, %edx
diff --git a/llvm/test/CodeGen/X86/bsr.ll b/llvm/test/CodeGen/X86/bsr.ll
index affacc5ee6487..0a8d71e7e7738 100644
--- a/llvm/test/CodeGen/X86/bsr.ll
+++ b/llvm/test/CodeGen/X86/bsr.ll
@@ -376,8 +376,8 @@ define i128 @cmov_bsr128(i128 %x, i128 %y) nounwind {
; X64-NEXT: xorq $63, %r8
; X64-NEXT: movl $127, %eax
; X64-NEXT: bsrq %rdi, %rax
-; X64-NEXT: xorq $63, %rax
-; X64-NEXT: addq $64, %rax
+; X64-NEXT: xorl $63, %eax
+; X64-NEXT: addl $64, %eax
; X64-NEXT: testq %rsi, %rsi
; X64-NEXT: cmovneq %r8, %rax
; X64-NEXT: xorq $127, %rax
@@ -470,8 +470,8 @@ define i128 @cmov_bsr128_undef(i128 %x, i128 %y) nounwind {
; X64-NEXT: bsrq %rsi, %r8
; X64-NEXT: xorq $63, %r8
; X64-NEXT: bsrq %rdi, %rax
-; X64-NEXT: xorq $63, %rax
-; X64-NEXT: orq $64, %rax
+; X64-NEXT: xorl $63, %eax
+; X64-NEXT: orl $64, %eax
; X64-NEXT: testq %rsi, %rsi
; X64-NEXT: cmovneq %r8, %rax
; X64-NEXT: xorq $127, %rax
diff --git a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
index 71ad598abe683..2d66c0efc995b 100644
--- a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
+++ b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
@@ -99,7 +99,7 @@ define void @_Z2x6v() local_unnamed_addr {
; CHECK-NEXT: movq x1 at GOTPCREL(%rip), %rax
; CHECK-NEXT: movl (%rax), %edx
; CHECK-NEXT: andl $511, %edx # imm = 0x1FF
-; CHECK-NEXT: leaq 1(%rdx), %rax
+; CHECK-NEXT: leal 1(%rdx), %eax
; CHECK-NEXT: movq x4 at GOTPCREL(%rip), %rcx
; CHECK-NEXT: movl %eax, (%rcx)
; CHECK-NEXT: movq x3 at GOTPCREL(%rip), %rcx
@@ -137,7 +137,7 @@ define void @_Z2x6v() local_unnamed_addr {
; CHECK-NEXT: leal 8(,%rdx,8), %eax
; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: leaq 32(%rsi), %rbx
-; CHECK-NEXT: leaq 8(,%rdx,8), %r14
+; CHECK-NEXT: leal 8(,%rdx,8), %r14d
; CHECK-NEXT: xorl %r15d, %r15d
; CHECK-NEXT: movq x0 at GOTPCREL(%rip), %r12
; CHECK-NEXT: movq %rsi, %r13
diff --git a/llvm/test/CodeGen/X86/dagcombine-select.ll b/llvm/test/CodeGen/X86/dagcombine-select.ll
index 1380c02663ee0..58e6c46327e9f 100644
--- a/llvm/test/CodeGen/X86/dagcombine-select.ll
+++ b/llvm/test/CodeGen/X86/dagcombine-select.ll
@@ -325,18 +325,20 @@ declare i64 @llvm.cttz.i64(i64, i1)
define i64 @cttz_64_eq_select(i64 %v) nounwind {
; NOBMI-LABEL: cttz_64_eq_select:
; NOBMI: # %bb.0:
-; NOBMI-NEXT: bsfq %rdi, %rcx
-; NOBMI-NEXT: movq $-1, %rax
+; NOBMI-NEXT: rep bsfq %rdi, %rcx
+; NOBMI-NEXT: addl $6, %ecx
+; NOBMI-NEXT: testq %rdi, %rdi
+; NOBMI-NEXT: movl $5, %eax
; NOBMI-NEXT: cmovneq %rcx, %rax
-; NOBMI-NEXT: addq $6, %rax
; NOBMI-NEXT: retq
;
; BMI-LABEL: cttz_64_eq_select:
; BMI: # %bb.0:
; BMI-NEXT: tzcntq %rdi, %rcx
-; BMI-NEXT: movq $-1, %rax
-; BMI-NEXT: cmovaeq %rcx, %rax
-; BMI-NEXT: addq $6, %rax
+; BMI-NEXT: addl $6, %ecx
+; BMI-NEXT: testq %rdi, %rdi
+; BMI-NEXT: movl $5, %eax
+; BMI-NEXT: cmovneq %rcx, %rax
; BMI-NEXT: retq
%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
@@ -349,18 +351,20 @@ define i64 @cttz_64_eq_select(i64 %v) nounwind {
define i64 @cttz_64_ne_select(i64 %v) nounwind {
; NOBMI-LABEL: cttz_64_ne_select:
; NOBMI: # %bb.0:
-; NOBMI-NEXT: bsfq %rdi, %rcx
-; NOBMI-NEXT: movq $-1, %rax
+; NOBMI-NEXT: rep bsfq %rdi, %rcx
+; NOBMI-NEXT: addl $6, %ecx
+; NOBMI-NEXT: testq %rdi, %rdi
+; NOBMI-NEXT: movl $5, %eax
; NOBMI-NEXT: cmovneq %rcx, %rax
-; NOBMI-NEXT: addq $6, %rax
; NOBMI-NEXT: retq
;
; BMI-LABEL: cttz_64_ne_select:
; BMI: # %bb.0:
; BMI-NEXT: tzcntq %rdi, %rcx
-; BMI-NEXT: movq $-1, %rax
-; BMI-NEXT: cmovaeq %rcx, %rax
-; BMI-NEXT: addq $6, %rax
+; BMI-NEXT: addl $6, %ecx
+; BMI-NEXT: testq %rdi, %rdi
+; BMI-NEXT: movl $5, %eax
+; BMI-NEXT: cmovneq %rcx, %rax
; BMI-NEXT: retq
%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
diff --git a/llvm/test/CodeGen/X86/dagcombine-shifts.ll b/llvm/test/CodeGen/X86/dagcombine-shifts.ll
index e9a1e8ed728a4..e8a1da31b3f82 100644
--- a/llvm/test/CodeGen/X86/dagcombine-shifts.ll
+++ b/llvm/test/CodeGen/X86/dagcombine-shifts.ll
@@ -243,11 +243,10 @@ define i64 @fun11(i16 zeroext %v) {
;
; X64-LABEL: fun11:
; X64: # %bb.0: # %entry
-; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: shrl $4, %eax
; X64-NEXT: andl $-16, %edi
-; X64-NEXT: addq %rdi, %rax
+; X64-NEXT: addl %edi, %eax
; X64-NEXT: retq
entry:
%shr = lshr i16 %v, 4
diff --git a/llvm/test/CodeGen/X86/divrem8_ext.ll b/llvm/test/CodeGen/X86/divrem8_ext.ll
index bfc982d2def5d..6fb25d8a2443d 100644
--- a/llvm/test/CodeGen/X86/divrem8_ext.ll
+++ b/llvm/test/CodeGen/X86/divrem8_ext.ll
@@ -197,7 +197,7 @@ define i64 @pr25754(i8 %a, i8 %c) {
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %ecx
; X64-NEXT: movzbl %al, %eax
-; X64-NEXT: addq %rcx, %rax
+; X64-NEXT: addl %ecx, %eax
; X64-NEXT: retq
%r1 = urem i8 %a, %c
%d1 = udiv i8 %a, %c
diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
index a8a6786d97ea0..58bd4e4ff5abb 100644
--- a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -13,7 +13,7 @@ define <4 x float> @fmul_pow2_4xfloat(<4 x i32> %i) {
; CHECK-SSE-LABEL: fmul_pow2_4xfloat:
; CHECK-SSE: # %bb.0:
; CHECK-SSE-NEXT: pslld $23, %xmm0
-; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1091567616,1091567616,1091567616,1091567616]
; CHECK-SSE-NEXT: retq
;
; CHECK-AVX2-LABEL: fmul_pow2_4xfloat:
@@ -772,7 +772,8 @@ define double @fmul_pow_mul_max_pow2(i16 %cnt) nounwind {
; CHECK-SSE-LABEL: fmul_pow_mul_max_pow2:
; CHECK-SSE: # %bb.0:
; CHECK-SSE-NEXT: movzbl %dil, %eax
-; CHECK-SSE-NEXT: leaq 1(%rax), %rcx
+; CHECK-SSE-NEXT: movl %eax, %ecx
+; CHECK-SSE-NEXT: incl %ecx
; CHECK-SSE-NEXT: cmpq %rcx, %rax
; CHECK-SSE-NEXT: cmovaq %rax, %rcx
; CHECK-SSE-NEXT: shlq $52, %rcx
@@ -784,7 +785,8 @@ define double @fmul_pow_mul_max_pow2(i16 %cnt) nounwind {
; CHECK-AVX-LABEL: fmul_pow_mul_max_pow2:
; CHECK-AVX: # %bb.0:
; CHECK-AVX-NEXT: movzbl %dil, %eax
-; CHECK-AVX-NEXT: leaq 1(%rax), %rcx
+; CHECK-AVX-NEXT: movl %eax, %ecx
+; CHECK-AVX-NEXT: incl %ecx
; CHECK-AVX-NEXT: cmpq %rcx, %rax
; CHECK-AVX-NEXT: cmovaq %rax, %rcx
; CHECK-AVX-NEXT: shlq $52, %rcx
@@ -911,19 +913,19 @@ define <2 x double> @fmul_pow_shl_cnt_vec(<2 x i64> %cnt) nounwind {
; CHECK-SSE-LABEL: fmul_pow_shl_cnt_vec:
; CHECK-SSE: # %bb.0:
; CHECK-SSE-NEXT: psllq $52, %xmm0
-; CHECK-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4629137466983448576,4629137466983448576]
; CHECK-SSE-NEXT: retq
;
; CHECK-AVX2-LABEL: fmul_pow_shl_cnt_vec:
; CHECK-AVX2: # %bb.0:
; CHECK-AVX2-NEXT: vpsllq $52, %xmm0, %xmm0
-; CHECK-AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4629137466983448576,4629137466983448576]
; CHECK-AVX2-NEXT: retq
;
; CHECK-ONLY-AVX512F-LABEL: fmul_pow_shl_cnt_vec:
; CHECK-ONLY-AVX512F: # %bb.0:
; CHECK-ONLY-AVX512F-NEXT: vpsllq $52, %xmm0, %xmm0
-; CHECK-ONLY-AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-ONLY-AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4629137466983448576,4629137466983448576]
; CHECK-ONLY-AVX512F-NEXT: retq
;
; CHECK-SKX-LABEL: fmul_pow_shl_cnt_vec:
@@ -941,7 +943,7 @@ define <4 x float> @fmul_pow_shl_cnt_vec_preserve_fma(<4 x i32> %cnt, <4 x float
; CHECK-SSE-LABEL: fmul_pow_shl_cnt_vec_preserve_fma:
; CHECK-SSE: # %bb.0:
; CHECK-SSE-NEXT: pslld $23, %xmm0
-; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1092616192,1092616192,1092616192,1092616192]
; CHECK-SSE-NEXT: addps %xmm1, %xmm0
; CHECK-SSE-NEXT: retq
;
@@ -980,7 +982,7 @@ define <4 x float> @fmul_pow_shl_cnt_vec_no_fma(<4 x i32> %cnt, <4 x float> %add
; CHECK-SSE-LABEL: fmul_pow_shl_cnt_vec_no_fma:
; CHECK-SSE: # %bb.0:
; CHECK-SSE-NEXT: pslld $23, %xmm0
-; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1092616192,1092616192,1092616192,1092616192]
; CHECK-SSE-NEXT: addps %xmm1, %xmm0
; CHECK-SSE-NEXT: retq
;
@@ -1017,13 +1019,13 @@ define <2 x double> @fmul_pow_shl_cnt_vec_non_splat_todo(<2 x i64> %cnt) nounwin
; CHECK-SSE-LABEL: fmul_pow_shl_cnt_vec_non_splat_todo:
; CHECK-SSE: # %bb.0:
; CHECK-SSE-NEXT: psllq $52, %xmm0
-; CHECK-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4629137466983448576,4628574517030027264]
; CHECK-SSE-NEXT: retq
;
; CHECK-AVX-LABEL: fmul_pow_shl_cnt_vec_non_splat_todo:
; CHECK-AVX: # %bb.0:
; CHECK-AVX-NEXT: vpsllq $52, %xmm0, %xmm0
-; CHECK-AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4629137466983448576,4628574517030027264]
; CHECK-AVX-NEXT: retq
%shl = shl nsw nuw <2 x i64> <i64 2, i64 2>, %cnt
%conv = uitofp <2 x i64> %shl to <2 x double>
@@ -1035,13 +1037,13 @@ define <2 x double> @fmul_pow_shl_cnt_vec_non_splat2_todo(<2 x i64> %cnt) nounwi
; CHECK-SSE-LABEL: fmul_pow_shl_cnt_vec_non_splat2_todo:
; CHECK-SSE: # %bb.0:
; CHECK-SSE-NEXT: psllq $52, %xmm0
-; CHECK-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4629137466983448576,4624633867356078080]
; CHECK-SSE-NEXT: retq
;
; CHECK-AVX-LABEL: fmul_pow_shl_cnt_vec_non_splat2_todo:
; CHECK-AVX: # %bb.0:
; CHECK-AVX-NEXT: vpsllq $52, %xmm0, %xmm0
-; CHECK-AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4629137466983448576,4624633867356078080]
; CHECK-AVX-NEXT: retq
%shl = shl nsw nuw <2 x i64> <i64 2, i64 1>, %cnt
%conv = uitofp <2 x i64> %shl to <2 x double>
@@ -1056,7 +1058,7 @@ define <2 x half> @fmul_pow_shl_cnt_vec_fail_to_large(<2 x i16> %cnt) nounwind {
; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; CHECK-SSE-NEXT: pslld $23, %xmm0
-; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1065353216,1065353216,1065353216,1065353216]
; CHECK-SSE-NEXT: cvttps2dq %xmm0, %xmm0
; CHECK-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; CHECK-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,2,u,u,u,u,u,u]
diff --git a/llvm/test/CodeGen/X86/h-registers-1.ll b/llvm/test/CodeGen/X86/h-registers-1.ll
index 07d85d260a37a..db8fb569f3fcd 100644
--- a/llvm/test/CodeGen/X86/h-registers-1.ll
+++ b/llvm/test/CodeGen/X86/h-registers-1.ll
@@ -28,13 +28,13 @@ define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h)
; CHECK-NEXT: movzbl %ah, %ebx
; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %r8d
-; CHECK-NEXT: addq %rdi, %rsi
-; CHECK-NEXT: addq %rbp, %rdx
-; CHECK-NEXT: addq %rsi, %rdx
-; CHECK-NEXT: addq %rbx, %rcx
-; CHECK-NEXT: addq %r8, %rax
-; CHECK-NEXT: addq %rcx, %rax
-; CHECK-NEXT: addq %rdx, %rax
+; CHECK-NEXT: addl %edi, %esi
+; CHECK-NEXT: addl %ebp, %edx
+; CHECK-NEXT: addl %esi, %edx
+; CHECK-NEXT: addl %ebx, %ecx
+; CHECK-NEXT: addl %r8d, %eax
+; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popq %rbp
@@ -61,13 +61,13 @@ define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h)
; GNUX32-NEXT: movzbl %ah, %ebx
; GNUX32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GNUX32-NEXT: movzbl {{[0-9]+}}(%esp), %r8d
-; GNUX32-NEXT: addq %rdi, %rsi
-; GNUX32-NEXT: addq %rbp, %rdx
-; GNUX32-NEXT: addq %rsi, %rdx
-; GNUX32-NEXT: addq %rbx, %rcx
-; GNUX32-NEXT: addq %r8, %rax
-; GNUX32-NEXT: addq %rcx, %rax
-; GNUX32-NEXT: addq %rdx, %rax
+; GNUX32-NEXT: addl %edi, %esi
+; GNUX32-NEXT: addl %ebp, %edx
+; GNUX32-NEXT: addl %esi, %edx
+; GNUX32-NEXT: addl %ebx, %ecx
+; GNUX32-NEXT: addl %r8d, %eax
+; GNUX32-NEXT: addl %ecx, %eax
+; GNUX32-NEXT: addl %edx, %eax
; GNUX32-NEXT: popq %rbx
; GNUX32-NEXT: .cfi_def_cfa_offset 16
; GNUX32-NEXT: popq %rbp
diff --git a/llvm/test/CodeGen/X86/narrow-add-i64.ll b/llvm/test/CodeGen/X86/narrow-add-i64.ll
index a7a54fd57413b..3d05395085d7f 100644
--- a/llvm/test/CodeGen/X86/narrow-add-i64.ll
+++ b/llvm/test/CodeGen/X86/narrow-add-i64.ll
@@ -13,7 +13,7 @@ define i64 @test_add_i64_i16_const(i16 %a) nounwind {
; X64-LABEL: test_add_i64_i16_const:
; X64: # %bb.0:
; X64-NEXT: movzwl %di, %eax
-; X64-NEXT: addq $42, %rax
+; X64-NEXT: addl $42, %eax
; X64-NEXT: retq
%zext_a = zext i16 %a to i64
%sum = add nuw nsw i64 %zext_a, 42
@@ -32,9 +32,9 @@ define i64 @test_add_i64_i16_zext(i16 %a, i16 %b) nounwind {
;
; X64-LABEL: test_add_i64_i16_zext:
; X64: # %bb.0:
-; X64-NEXT: movzwl %di, %ecx
-; X64-NEXT: movzwl %si, %eax
-; X64-NEXT: addq %rcx, %rax
+; X64-NEXT: movzwl %si, %ecx
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: addl %ecx, %eax
; X64-NEXT: retq
%zext_a = zext i16 %a to i64
%zext_b = zext i16 %b to i64
diff --git a/llvm/test/CodeGen/X86/popcnt.ll b/llvm/test/CodeGen/X86/popcnt.ll
index 3004b8b72fcc5..e9398b788a7b6 100644
--- a/llvm/test/CodeGen/X86/popcnt.ll
+++ b/llvm/test/CodeGen/X86/popcnt.ll
@@ -427,39 +427,39 @@ define i128 @cnt128(i128 %x) nounwind readnone {
; X64-BASE: # %bb.0:
; X64-BASE-NEXT: movq %rsi, %rax
; X64-BASE-NEXT: shrq %rax
-; X64-BASE-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555
-; X64-BASE-NEXT: andq %r8, %rax
+; X64-BASE-NEXT: movabsq $6148914691236517205, %rdx # imm = 0x5555555555555555
+; X64-BASE-NEXT: andq %rdx, %rax
; X64-BASE-NEXT: subq %rax, %rsi
-; X64-BASE-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333
-; X64-BASE-NEXT: movq %rsi, %rax
-; X64-BASE-NEXT: andq %rcx, %rax
+; X64-BASE-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
+; X64-BASE-NEXT: movq %rsi, %r8
+; X64-BASE-NEXT: andq %rax, %r8
; X64-BASE-NEXT: shrq $2, %rsi
-; X64-BASE-NEXT: andq %rcx, %rsi
-; X64-BASE-NEXT: addq %rsi, %rax
-; X64-BASE-NEXT: movq %rax, %rdx
-; X64-BASE-NEXT: shrq $4, %rdx
-; X64-BASE-NEXT: addq %rax, %rdx
+; X64-BASE-NEXT: andq %rax, %rsi
+; X64-BASE-NEXT: addq %rsi, %r8
+; X64-BASE-NEXT: movq %r8, %rcx
+; X64-BASE-NEXT: shrq $4, %rcx
+; X64-BASE-NEXT: addq %r8, %rcx
; X64-BASE-NEXT: movabsq $1085102592571150095, %rsi # imm = 0xF0F0F0F0F0F0F0F
-; X64-BASE-NEXT: andq %rsi, %rdx
-; X64-BASE-NEXT: movabsq $72340172838076673, %r9 # imm = 0x101010101010101
-; X64-BASE-NEXT: imulq %r9, %rdx
-; X64-BASE-NEXT: shrq $56, %rdx
-; X64-BASE-NEXT: movq %rdi, %rax
-; X64-BASE-NEXT: shrq %rax
-; X64-BASE-NEXT: andq %r8, %rax
-; X64-BASE-NEXT: subq %rax, %rdi
-; X64-BASE-NEXT: movq %rdi, %rax
-; X64-BASE-NEXT: andq %rcx, %rax
+; X64-BASE-NEXT: andq %rsi, %rcx
+; X64-BASE-NEXT: movabsq $72340172838076673, %r8 # imm = 0x101010101010101
+; X64-BASE-NEXT: imulq %r8, %rcx
+; X64-BASE-NEXT: shrq $56, %rcx
+; X64-BASE-NEXT: movq %rdi, %r9
+; X64-BASE-NEXT: shrq %r9
+; X64-BASE-NEXT: andq %rdx, %r9
+; X64-BASE-NEXT: subq %r9, %rdi
+; X64-BASE-NEXT: movq %rdi, %rdx
+; X64-BASE-NEXT: andq %rax, %rdx
; X64-BASE-NEXT: shrq $2, %rdi
-; X64-BASE-NEXT: andq %rdi, %rcx
-; X64-BASE-NEXT: addq %rax, %rcx
-; X64-BASE-NEXT: movq %rcx, %rax
+; X64-BASE-NEXT: andq %rax, %rdi
+; X64-BASE-NEXT: addq %rdx, %rdi
+; X64-BASE-NEXT: movq %rdi, %rax
; X64-BASE-NEXT: shrq $4, %rax
-; X64-BASE-NEXT: addq %rcx, %rax
+; X64-BASE-NEXT: addq %rdi, %rax
; X64-BASE-NEXT: andq %rsi, %rax
-; X64-BASE-NEXT: imulq %r9, %rax
+; X64-BASE-NEXT: imulq %r8, %rax
; X64-BASE-NEXT: shrq $56, %rax
-; X64-BASE-NEXT: addq %rdx, %rax
+; X64-BASE-NEXT: addl %ecx, %eax
; X64-BASE-NEXT: xorl %edx, %edx
; X64-BASE-NEXT: retq
;
@@ -491,7 +491,7 @@ define i128 @cnt128(i128 %x) nounwind readnone {
; X64-POPCNT: # %bb.0:
; X64-POPCNT-NEXT: popcntq %rsi, %rcx
; X64-POPCNT-NEXT: popcntq %rdi, %rax
-; X64-POPCNT-NEXT: addq %rcx, %rax
+; X64-POPCNT-NEXT: addl %ecx, %eax
; X64-POPCNT-NEXT: xorl %edx, %edx
; X64-POPCNT-NEXT: retq
;
@@ -525,7 +525,7 @@ define i128 @cnt128(i128 %x) nounwind readnone {
; X64-NDD-NEXT: andq %rsi, %rax
; X64-NDD-NEXT: imulq %r8, %rax
; X64-NDD-NEXT: shrq $56, %rax
-; X64-NDD-NEXT: addq %rdx, %rax
+; X64-NDD-NEXT: addl %edx, %eax
; X64-NDD-NEXT: xorl %edx, %edx
; X64-NDD-NEXT: retq
;
@@ -1045,39 +1045,39 @@ define i128 @cnt128_optsize(i128 %x) nounwind readnone optsize {
; X64-BASE: # %bb.0:
; X64-BASE-NEXT: movq %rsi, %rax
; X64-BASE-NEXT: shrq %rax
-; X64-BASE-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555
-; X64-BASE-NEXT: andq %r8, %rax
+; X64-BASE-NEXT: movabsq $6148914691236517205, %rdx # imm = 0x5555555555555555
+; X64-BASE-NEXT: andq %rdx, %rax
; X64-BASE-NEXT: subq %rax, %rsi
-; X64-BASE-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333
-; X64-BASE-NEXT: movq %rsi, %rax
-; X64-BASE-NEXT: andq %rcx, %rax
+; X64-BASE-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
+; X64-BASE-NEXT: movq %rsi, %r8
+; X64-BASE-NEXT: andq %rax, %r8
; X64-BASE-NEXT: shrq $2, %rsi
-; X64-BASE-NEXT: andq %rcx, %rsi
-; X64-BASE-NEXT: addq %rsi, %rax
-; X64-BASE-NEXT: movq %rax, %rdx
-; X64-BASE-NEXT: shrq $4, %rdx
-; X64-BASE-NEXT: addq %rax, %rdx
+; X64-BASE-NEXT: andq %rax, %rsi
+; X64-BASE-NEXT: addq %rsi, %r8
+; X64-BASE-NEXT: movq %r8, %rcx
+; X64-BASE-NEXT: shrq $4, %rcx
+; X64-BASE-NEXT: addq %r8, %rcx
; X64-BASE-NEXT: movabsq $1085102592571150095, %rsi # imm = 0xF0F0F0F0F0F0F0F
-; X64-BASE-NEXT: andq %rsi, %rdx
-; X64-BASE-NEXT: movabsq $72340172838076673, %r9 # imm = 0x101010101010101
-; X64-BASE-NEXT: imulq %r9, %rdx
-; X64-BASE-NEXT: shrq $56, %rdx
-; X64-BASE-NEXT: movq %rdi, %rax
-; X64-BASE-NEXT: shrq %rax
-; X64-BASE-NEXT: andq %r8, %rax
-; X64-BASE-NEXT: subq %rax, %rdi
-; X64-BASE-NEXT: movq %rdi, %rax
-; X64-BASE-NEXT: andq %rcx, %rax
+; X64-BASE-NEXT: andq %rsi, %rcx
+; X64-BASE-NEXT: movabsq $72340172838076673, %r8 # imm = 0x101010101010101
+; X64-BASE-NEXT: imulq %r8, %rcx
+; X64-BASE-NEXT: shrq $56, %rcx
+; X64-BASE-NEXT: movq %rdi, %r9
+; X64-BASE-NEXT: shrq %r9
+; X64-BASE-NEXT: andq %rdx, %r9
+; X64-BASE-NEXT: subq %r9, %rdi
+; X64-BASE-NEXT: movq %rdi, %rdx
+; X64-BASE-NEXT: andq %rax, %rdx
; X64-BASE-NEXT: shrq $2, %rdi
-; X64-BASE-NEXT: andq %rdi, %rcx
-; X64-BASE-NEXT: addq %rax, %rcx
-; X64-BASE-NEXT: movq %rcx, %rax
+; X64-BASE-NEXT: andq %rax, %rdi
+; X64-BASE-NEXT: addq %rdx, %rdi
+; X64-BASE-NEXT: movq %rdi, %rax
; X64-BASE-NEXT: shrq $4, %rax
-; X64-BASE-NEXT: addq %rcx, %rax
+; X64-BASE-NEXT: addq %rdi, %rax
; X64-BASE-NEXT: andq %rsi, %rax
-; X64-BASE-NEXT: imulq %r9, %rax
+; X64-BASE-NEXT: imulq %r8, %rax
; X64-BASE-NEXT: shrq $56, %rax
-; X64-BASE-NEXT: addq %rdx, %rax
+; X64-BASE-NEXT: addl %ecx, %eax
; X64-BASE-NEXT: xorl %edx, %edx
; X64-BASE-NEXT: retq
;
@@ -1110,7 +1110,7 @@ define i128 @cnt128_optsize(i128 %x) nounwind readnone optsize {
; X64-POPCNT: # %bb.0:
; X64-POPCNT-NEXT: popcntq %rsi, %rcx
; X64-POPCNT-NEXT: popcntq %rdi, %rax
-; X64-POPCNT-NEXT: addq %rcx, %rax
+; X64-POPCNT-NEXT: addl %ecx, %eax
; X64-POPCNT-NEXT: xorl %edx, %edx
; X64-POPCNT-NEXT: retq
;
@@ -1144,7 +1144,7 @@ define i128 @cnt128_optsize(i128 %x) nounwind readnone optsize {
; X64-NDD-NEXT: andq %rsi, %rax
; X64-NDD-NEXT: imulq %r8, %rax
; X64-NDD-NEXT: shrq $56, %rax
-; X64-NDD-NEXT: addq %rdx, %rax
+; X64-NDD-NEXT: addl %edx, %eax
; X64-NDD-NEXT: xorl %edx, %edx
; X64-NDD-NEXT: retq
;
@@ -1547,39 +1547,39 @@ define i128 @cnt128_pgso(i128 %x) nounwind readnone !prof !14 {
; X64-BASE: # %bb.0:
; X64-BASE-NEXT: movq %rsi, %rax
; X64-BASE-NEXT: shrq %rax
-; X64-BASE-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555
-; X64-BASE-NEXT: andq %r8, %rax
+; X64-BASE-NEXT: movabsq $6148914691236517205, %rdx # imm = 0x5555555555555555
+; X64-BASE-NEXT: andq %rdx, %rax
; X64-BASE-NEXT: subq %rax, %rsi
-; X64-BASE-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333
-; X64-BASE-NEXT: movq %rsi, %rax
-; X64-BASE-NEXT: andq %rcx, %rax
+; X64-BASE-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
+; X64-BASE-NEXT: movq %rsi, %r8
+; X64-BASE-NEXT: andq %rax, %r8
; X64-BASE-NEXT: shrq $2, %rsi
-; X64-BASE-NEXT: andq %rcx, %rsi
-; X64-BASE-NEXT: addq %rsi, %rax
-; X64-BASE-NEXT: movq %rax, %rdx
-; X64-BASE-NEXT: shrq $4, %rdx
-; X64-BASE-NEXT: addq %rax, %rdx
+; X64-BASE-NEXT: andq %rax, %rsi
+; X64-BASE-NEXT: addq %rsi, %r8
+; X64-BASE-NEXT: movq %r8, %rcx
+; X64-BASE-NEXT: shrq $4, %rcx
+; X64-BASE-NEXT: addq %r8, %rcx
; X64-BASE-NEXT: movabsq $1085102592571150095, %rsi # imm = 0xF0F0F0F0F0F0F0F
-; X64-BASE-NEXT: andq %rsi, %rdx
-; X64-BASE-NEXT: movabsq $72340172838076673, %r9 # imm = 0x101010101010101
-; X64-BASE-NEXT: imulq %r9, %rdx
-; X64-BASE-NEXT: shrq $56, %rdx
-; X64-BASE-NEXT: movq %rdi, %rax
-; X64-BASE-NEXT: shrq %rax
-; X64-BASE-NEXT: andq %r8, %rax
-; X64-BASE-NEXT: subq %rax, %rdi
-; X64-BASE-NEXT: movq %rdi, %rax
-; X64-BASE-NEXT: andq %rcx, %rax
+; X64-BASE-NEXT: andq %rsi, %rcx
+; X64-BASE-NEXT: movabsq $72340172838076673, %r8 # imm = 0x101010101010101
+; X64-BASE-NEXT: imulq %r8, %rcx
+; X64-BASE-NEXT: shrq $56, %rcx
+; X64-BASE-NEXT: movq %rdi, %r9
+; X64-BASE-NEXT: shrq %r9
+; X64-BASE-NEXT: andq %rdx, %r9
+; X64-BASE-NEXT: subq %r9, %rdi
+; X64-BASE-NEXT: movq %rdi, %rdx
+; X64-BASE-NEXT: andq %rax, %rdx
; X64-BASE-NEXT: shrq $2, %rdi
-; X64-BASE-NEXT: andq %rdi, %rcx
-; X64-BASE-NEXT: addq %rax, %rcx
-; X64-BASE-NEXT: movq %rcx, %rax
+; X64-BASE-NEXT: andq %rax, %rdi
+; X64-BASE-NEXT: addq %rdx, %rdi
+; X64-BASE-NEXT: movq %rdi, %rax
; X64-BASE-NEXT: shrq $4, %rax
-; X64-BASE-NEXT: addq %rcx, %rax
+; X64-BASE-NEXT: addq %rdi, %rax
; X64-BASE-NEXT: andq %rsi, %rax
-; X64-BASE-NEXT: imulq %r9, %rax
+; X64-BASE-NEXT: imulq %r8, %rax
; X64-BASE-NEXT: shrq $56, %rax
-; X64-BASE-NEXT: addq %rdx, %rax
+; X64-BASE-NEXT: addl %ecx, %eax
; X64-BASE-NEXT: xorl %edx, %edx
; X64-BASE-NEXT: retq
;
@@ -1612,7 +1612,7 @@ define i128 @cnt128_pgso(i128 %x) nounwind readnone !prof !14 {
; X64-POPCNT: # %bb.0:
; X64-POPCNT-NEXT: popcntq %rsi, %rcx
; X64-POPCNT-NEXT: popcntq %rdi, %rax
-; X64-POPCNT-NEXT: addq %rcx, %rax
+; X64-POPCNT-NEXT: addl %ecx, %eax
; X64-POPCNT-NEXT: xorl %edx, %edx
; X64-POPCNT-NEXT: retq
;
@@ -1646,7 +1646,7 @@ define i128 @cnt128_pgso(i128 %x) nounwind readnone !prof !14 {
; X64-NDD-NEXT: andq %rsi, %rax
; X64-NDD-NEXT: imulq %r8, %rax
; X64-NDD-NEXT: shrq $56, %rax
-; X64-NDD-NEXT: addq %rdx, %rax
+; X64-NDD-NEXT: addl %edx, %eax
; X64-NDD-NEXT: xorl %edx, %edx
; X64-NDD-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/pr173924.ll b/llvm/test/CodeGen/X86/pr173924.ll
index a25f62a0ab071..60e5b03d3e6dd 100644
--- a/llvm/test/CodeGen/X86/pr173924.ll
+++ b/llvm/test/CodeGen/X86/pr173924.ll
@@ -1,38 +1,81 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,V3
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,V4
define i256 @PR173924(<8 x i256> %a0) {
-; CHECK-LABEL: PR173924:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movq %rdi, %rax
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdi
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r8
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
-; CHECK-NEXT: vmovd {{.*#+}} xmm0 = [1,0,0,0]
-; CHECK-NEXT: vpand {{[0-9]+}}(%rsp), %ymm0, %ymm0
-; CHECK-NEXT: vmovq %xmm0, %r11
-; CHECK-NEXT: andl $1, %r10d
-; CHECK-NEXT: andl $1, %esi
-; CHECK-NEXT: addq %r10, %rsi
-; CHECK-NEXT: andl $1, %r8d
-; CHECK-NEXT: andl $1, %ecx
-; CHECK-NEXT: addq %r8, %rcx
-; CHECK-NEXT: addq %rsi, %rcx
-; CHECK-NEXT: andl $1, %edx
-; CHECK-NEXT: addq %r11, %rdx
-; CHECK-NEXT: andl $1, %edi
-; CHECK-NEXT: andl $1, %r9d
-; CHECK-NEXT: addq %rdi, %r9
-; CHECK-NEXT: addq %rdx, %r9
-; CHECK-NEXT: addq %rcx, %r9
-; CHECK-NEXT: vmovq %r9, %xmm0
-; CHECK-NEXT: vmovdqu %ymm0, (%rax)
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
+; V3-LABEL: PR173924:
+; V3: # %bb.0:
+; V3-NEXT: movq %rdi, %rax
+; V3-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; V3-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; V3-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; V3-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
+; V3-NEXT: vmovq {{.*#+}} xmm4 = mem[0],zero
+; V3-NEXT: vmovq {{.*#+}} xmm5 = mem[0],zero
+; V3-NEXT: andl $1, %r9d
+; V3-NEXT: andl $1, %esi
+; V3-NEXT: vmovd {{.*#+}} xmm6 = [1,0,0,0]
+; V3-NEXT: vpand %xmm6, %xmm5, %xmm5
+; V3-NEXT: vmovd %xmm5, %ecx
+; V3-NEXT: vpand %xmm6, %xmm4, %xmm4
+; V3-NEXT: vmovd %xmm4, %edx
+; V3-NEXT: addl %ecx, %edx
+; V3-NEXT: vpand %xmm6, %xmm3, %xmm3
+; V3-NEXT: vmovd %xmm3, %ecx
+; V3-NEXT: vpand %xmm6, %xmm2, %xmm2
+; V3-NEXT: vmovd %xmm2, %edi
+; V3-NEXT: addl %ecx, %edi
+; V3-NEXT: vpand %xmm6, %xmm1, %xmm1
+; V3-NEXT: vmovd %xmm1, %ecx
+; V3-NEXT: addl %esi, %ecx
+; V3-NEXT: addl %edx, %ecx
+; V3-NEXT: vpand %xmm6, %xmm0, %xmm0
+; V3-NEXT: vmovd %xmm0, %edx
+; V3-NEXT: addl %r9d, %edx
+; V3-NEXT: addl %edi, %edx
+; V3-NEXT: addl %ecx, %edx
+; V3-NEXT: vmovd %edx, %xmm0
+; V3-NEXT: vmovdqu %ymm0, (%rax)
+; V3-NEXT: vzeroupper
+; V3-NEXT: retq
+;
+; V4-LABEL: PR173924:
+; V4: # %bb.0:
+; V4-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; V4-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
+; V4-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; V4-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
+; V4-NEXT: vmovq {{.*#+}} xmm4 = mem[0],zero
+; V4-NEXT: vmovd {{.*#+}} xmm5 = [1,0,0,0]
+; V4-NEXT: vpand {{[0-9]+}}(%rsp), %ymm5, %ymm6
+; V4-NEXT: movq %rdi, %rax
+; V4-NEXT: andl $1, %esi
+; V4-NEXT: andl $1, %r9d
+; V4-NEXT: vpand %xmm5, %xmm4, %xmm4
+; V4-NEXT: vmovd %xmm4, %ecx
+; V4-NEXT: vmovd %xmm6, %edx
+; V4-NEXT: addl %ecx, %edx
+; V4-NEXT: vpand %xmm5, %xmm3, %xmm3
+; V4-NEXT: vmovd %xmm3, %ecx
+; V4-NEXT: vpand %xmm5, %xmm2, %xmm2
+; V4-NEXT: vmovd %xmm2, %edi
+; V4-NEXT: addl %ecx, %edi
+; V4-NEXT: vpand %xmm5, %xmm1, %xmm1
+; V4-NEXT: vmovd %xmm1, %ecx
+; V4-NEXT: addl %r9d, %ecx
+; V4-NEXT: addl %edx, %ecx
+; V4-NEXT: vpand %xmm5, %xmm0, %xmm0
+; V4-NEXT: vmovd %xmm0, %edx
+; V4-NEXT: addl %esi, %edx
+; V4-NEXT: addl %edi, %edx
+; V4-NEXT: addl %ecx, %edx
+; V4-NEXT: vmovd %edx, %xmm0
+; V4-NEXT: vmovdqu %ymm0, (%rax)
+; V4-NEXT: vzeroupper
+; V4-NEXT: retq
%m = and <8 x i256> %a0, splat (i256 1)
%r = call i256 @llvm.vector.reduce.add.v8i256(<8 x i256> %m)
ret i256 %r
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/X86/scheduler-backtracking.ll b/llvm/test/CodeGen/X86/scheduler-backtracking.ll
index 28029793211f0..fade8cbd21685 100644
--- a/llvm/test/CodeGen/X86/scheduler-backtracking.ll
+++ b/llvm/test/CodeGen/X86/scheduler-backtracking.ll
@@ -220,30 +220,30 @@ define i256 @test2(i256 %a) nounwind {
; ILP-NEXT: movl $0, %r9d
; ILP-NEXT: sbbq %rcx, %r9
; ILP-NEXT: sbbq %r8, %rdi
+; ILP-NEXT: andq %rcx, %r9
; ILP-NEXT: andq %r8, %rdi
; ILP-NEXT: bsrq %rdi, %r8
; ILP-NEXT: andq %rdx, %r10
; ILP-NEXT: bsrq %r10, %rdx
; ILP-NEXT: xorq $63, %r8
-; ILP-NEXT: andq %rcx, %r9
; ILP-NEXT: bsrq %r9, %rcx
-; ILP-NEXT: xorq $63, %rcx
-; ILP-NEXT: orq $64, %rcx
+; ILP-NEXT: xorl $63, %ecx
+; ILP-NEXT: orl $64, %ecx
; ILP-NEXT: testq %rdi, %rdi
+; ILP-NEXT: movq $0, 8(%rax)
; ILP-NEXT: cmovneq %r8, %rcx
-; ILP-NEXT: xorq $63, %rdx
+; ILP-NEXT: xorl $63, %edx
; ILP-NEXT: andq %rsi, %r11
; ILP-NEXT: movl $127, %esi
; ILP-NEXT: bsrq %r11, %rsi
-; ILP-NEXT: xorq $63, %rsi
-; ILP-NEXT: addq $64, %rsi
+; ILP-NEXT: xorl $63, %esi
+; ILP-NEXT: addl $64, %esi
; ILP-NEXT: testq %r10, %r10
-; ILP-NEXT: cmovneq %rdx, %rsi
-; ILP-NEXT: subq $-128, %rsi
-; ILP-NEXT: orq %rdi, %r9
+; ILP-NEXT: cmovnel %edx, %esi
+; ILP-NEXT: subl $-128, %esi
+; ILP-NEXT: orq %r9, %rdi
; ILP-NEXT: cmovneq %rcx, %rsi
; ILP-NEXT: movq %rsi, (%rax)
-; ILP-NEXT: movq $0, 8(%rax)
; ILP-NEXT: retq
;
; HYBRID-LABEL: test2:
@@ -264,21 +264,21 @@ define i256 @test2(i256 %a) nounwind {
; HYBRID-NEXT: xorq $63, %r8
; HYBRID-NEXT: andq %rcx, %r9
; HYBRID-NEXT: bsrq %r9, %rcx
-; HYBRID-NEXT: xorq $63, %rcx
-; HYBRID-NEXT: orq $64, %rcx
+; HYBRID-NEXT: xorl $63, %ecx
+; HYBRID-NEXT: orl $64, %ecx
; HYBRID-NEXT: testq %rdi, %rdi
; HYBRID-NEXT: cmovneq %r8, %rcx
; HYBRID-NEXT: andq %rdx, %r10
; HYBRID-NEXT: bsrq %r10, %rdx
-; HYBRID-NEXT: xorq $63, %rdx
+; HYBRID-NEXT: xorl $63, %edx
; HYBRID-NEXT: andq %rsi, %r11
; HYBRID-NEXT: movl $127, %esi
; HYBRID-NEXT: bsrq %r11, %rsi
-; HYBRID-NEXT: xorq $63, %rsi
-; HYBRID-NEXT: addq $64, %rsi
+; HYBRID-NEXT: xorl $63, %esi
+; HYBRID-NEXT: addl $64, %esi
; HYBRID-NEXT: testq %r10, %r10
-; HYBRID-NEXT: cmovneq %rdx, %rsi
-; HYBRID-NEXT: subq $-128, %rsi
+; HYBRID-NEXT: cmovnel %edx, %esi
+; HYBRID-NEXT: subl $-128, %esi
; HYBRID-NEXT: orq %rdi, %r9
; HYBRID-NEXT: cmovneq %rcx, %rsi
; HYBRID-NEXT: movq %rsi, (%rax)
@@ -303,21 +303,21 @@ define i256 @test2(i256 %a) nounwind {
; BURR-NEXT: xorq $63, %r8
; BURR-NEXT: andq %rcx, %r9
; BURR-NEXT: bsrq %r9, %rcx
-; BURR-NEXT: xorq $63, %rcx
-; BURR-NEXT: orq $64, %rcx
+; BURR-NEXT: xorl $63, %ecx
+; BURR-NEXT: orl $64, %ecx
; BURR-NEXT: testq %rdi, %rdi
; BURR-NEXT: cmovneq %r8, %rcx
; BURR-NEXT: andq %rdx, %r10
; BURR-NEXT: bsrq %r10, %rdx
-; BURR-NEXT: xorq $63, %rdx
+; BURR-NEXT: xorl $63, %edx
; BURR-NEXT: andq %rsi, %r11
; BURR-NEXT: movl $127, %esi
; BURR-NEXT: bsrq %r11, %rsi
-; BURR-NEXT: xorq $63, %rsi
-; BURR-NEXT: addq $64, %rsi
+; BURR-NEXT: xorl $63, %esi
+; BURR-NEXT: addl $64, %esi
; BURR-NEXT: testq %r10, %r10
-; BURR-NEXT: cmovneq %rdx, %rsi
-; BURR-NEXT: subq $-128, %rsi
+; BURR-NEXT: cmovnel %edx, %esi
+; BURR-NEXT: subl $-128, %esi
; BURR-NEXT: orq %rdi, %r9
; BURR-NEXT: cmovneq %rcx, %rsi
; BURR-NEXT: movq %rsi, (%rax)
@@ -339,24 +339,24 @@ define i256 @test2(i256 %a) nounwind {
; SRC-NEXT: andq %rcx, %r9
; SRC-NEXT: andq %r8, %rdi
; SRC-NEXT: andq %rsi, %r11
-; SRC-NEXT: bsrq %rdi, %rcx
-; SRC-NEXT: xorq $63, %rcx
-; SRC-NEXT: bsrq %r9, %rdx
+; SRC-NEXT: bsrq %rdi, %rdx
; SRC-NEXT: xorq $63, %rdx
-; SRC-NEXT: orq $64, %rdx
+; SRC-NEXT: bsrq %r9, %rcx
+; SRC-NEXT: xorl $63, %ecx
+; SRC-NEXT: orl $64, %ecx
; SRC-NEXT: testq %rdi, %rdi
-; SRC-NEXT: cmovneq %rcx, %rdx
-; SRC-NEXT: bsrq %r10, %rcx
-; SRC-NEXT: xorq $63, %rcx
+; SRC-NEXT: cmovneq %rdx, %rcx
+; SRC-NEXT: bsrq %r10, %rdx
+; SRC-NEXT: xorl $63, %edx
; SRC-NEXT: movl $127, %esi
; SRC-NEXT: bsrq %r11, %rsi
-; SRC-NEXT: xorq $63, %rsi
-; SRC-NEXT: addq $64, %rsi
+; SRC-NEXT: xorl $63, %esi
+; SRC-NEXT: addl $64, %esi
; SRC-NEXT: testq %r10, %r10
-; SRC-NEXT: cmovneq %rcx, %rsi
-; SRC-NEXT: subq $-128, %rsi
+; SRC-NEXT: cmovnel %edx, %esi
+; SRC-NEXT: subl $-128, %esi
; SRC-NEXT: orq %r9, %rdi
-; SRC-NEXT: cmovneq %rdx, %rsi
+; SRC-NEXT: cmovneq %rcx, %rsi
; SRC-NEXT: xorps %xmm0, %xmm0
; SRC-NEXT: movaps %xmm0, 16(%rax)
; SRC-NEXT: movq %rsi, (%rax)
@@ -373,23 +373,23 @@ define i256 @test2(i256 %a) nounwind {
; LIN-NEXT: negq %r9
; LIN-NEXT: andq %rsi, %r9
; LIN-NEXT: bsrq %r9, %rdi
-; LIN-NEXT: xorq $63, %rdi
-; LIN-NEXT: addq $64, %rdi
+; LIN-NEXT: xorl $63, %edi
+; LIN-NEXT: addl $64, %edi
; LIN-NEXT: xorl %esi, %esi
; LIN-NEXT: movl $0, %r9d
; LIN-NEXT: sbbq %rdx, %r9
; LIN-NEXT: andq %rdx, %r9
; LIN-NEXT: bsrq %r9, %rdx
-; LIN-NEXT: xorq $63, %rdx
+; LIN-NEXT: xorl $63, %edx
; LIN-NEXT: testq %r9, %r9
-; LIN-NEXT: cmoveq %rdi, %rdx
-; LIN-NEXT: subq $-128, %rdx
+; LIN-NEXT: cmovel %edi, %edx
+; LIN-NEXT: subl $-128, %edx
; LIN-NEXT: movl $0, %edi
; LIN-NEXT: sbbq %rcx, %rdi
; LIN-NEXT: andq %rcx, %rdi
; LIN-NEXT: bsrq %rdi, %rcx
-; LIN-NEXT: xorq $63, %rcx
-; LIN-NEXT: orq $64, %rcx
+; LIN-NEXT: xorl $63, %ecx
+; LIN-NEXT: orl $64, %ecx
; LIN-NEXT: sbbq %r8, %rsi
; LIN-NEXT: andq %r8, %rsi
; LIN-NEXT: bsrq %rsi, %r8
@@ -413,42 +413,42 @@ define i256 @test3(i256 %n) nounwind {
; ILP-NEXT: movq %rdi, %rax
; ILP-NEXT: xorps %xmm0, %xmm0
; ILP-NEXT: movaps %xmm0, 16(%rdi)
-; ILP-NEXT: xorl %r9d, %r9d
-; ILP-NEXT: movq %rsi, %rdi
-; ILP-NEXT: negq %rdi
+; ILP-NEXT: xorl %edi, %edi
+; ILP-NEXT: movq %rsi, %r9
+; ILP-NEXT: negq %r9
; ILP-NEXT: movl $0, %r10d
; ILP-NEXT: sbbq %rdx, %r10
; ILP-NEXT: movl $0, %r11d
; ILP-NEXT: sbbq %rcx, %r11
-; ILP-NEXT: sbbq %r8, %r9
+; ILP-NEXT: sbbq %r8, %rdi
+; ILP-NEXT: notq %rcx
+; ILP-NEXT: andq %r11, %rcx
; ILP-NEXT: notq %r8
-; ILP-NEXT: andq %r9, %r8
-; ILP-NEXT: bsrq %r8, %r9
+; ILP-NEXT: andq %rdi, %r8
+; ILP-NEXT: bsrq %rcx, %rdi
+; ILP-NEXT: bsrq %r8, %r11
; ILP-NEXT: notq %rdx
; ILP-NEXT: andq %r10, %rdx
; ILP-NEXT: bsrq %rdx, %r10
-; ILP-NEXT: xorq $63, %r9
-; ILP-NEXT: notq %rcx
-; ILP-NEXT: andq %r11, %rcx
-; ILP-NEXT: bsrq %rcx, %r11
; ILP-NEXT: xorq $63, %r11
-; ILP-NEXT: orq $64, %r11
-; ILP-NEXT: testq %r8, %r8
-; ILP-NEXT: cmovneq %r9, %r11
-; ILP-NEXT: xorq $63, %r10
+; ILP-NEXT: xorl $63, %edi
; ILP-NEXT: notq %rsi
-; ILP-NEXT: andq %rdi, %rsi
-; ILP-NEXT: movl $127, %edi
-; ILP-NEXT: bsrq %rsi, %rdi
-; ILP-NEXT: xorq $63, %rdi
-; ILP-NEXT: addq $64, %rdi
-; ILP-NEXT: testq %rdx, %rdx
-; ILP-NEXT: cmovneq %r10, %rdi
-; ILP-NEXT: subq $-128, %rdi
-; ILP-NEXT: orq %r8, %rcx
-; ILP-NEXT: cmovneq %r11, %rdi
-; ILP-NEXT: movq %rdi, (%rax)
+; ILP-NEXT: orl $64, %edi
+; ILP-NEXT: testq %r8, %r8
; ILP-NEXT: movq $0, 8(%rax)
+; ILP-NEXT: cmovneq %r11, %rdi
+; ILP-NEXT: xorl $63, %r10d
+; ILP-NEXT: andq %r9, %rsi
+; ILP-NEXT: movl $127, %r9d
+; ILP-NEXT: bsrq %rsi, %r9
+; ILP-NEXT: xorl $63, %r9d
+; ILP-NEXT: addl $64, %r9d
+; ILP-NEXT: testq %rdx, %rdx
+; ILP-NEXT: cmovnel %r10d, %r9d
+; ILP-NEXT: subl $-128, %r9d
+; ILP-NEXT: orq %rcx, %r8
+; ILP-NEXT: cmovneq %rdi, %r9
+; ILP-NEXT: movq %r9, (%rax)
; ILP-NEXT: retq
;
; HYBRID-LABEL: test3:
@@ -472,23 +472,23 @@ define i256 @test3(i256 %n) nounwind {
; HYBRID-NEXT: notq %rcx
; HYBRID-NEXT: andq %r11, %rcx
; HYBRID-NEXT: bsrq %rcx, %r9
-; HYBRID-NEXT: xorq $63, %r9
-; HYBRID-NEXT: orq $64, %r9
+; HYBRID-NEXT: xorl $63, %r9d
+; HYBRID-NEXT: orl $64, %r9d
; HYBRID-NEXT: testq %r8, %r8
; HYBRID-NEXT: cmovneq %rbx, %r9
; HYBRID-NEXT: notq %rdx
; HYBRID-NEXT: andq %r10, %rdx
; HYBRID-NEXT: bsrq %rdx, %r10
-; HYBRID-NEXT: xorq $63, %r10
+; HYBRID-NEXT: xorl $63, %r10d
; HYBRID-NEXT: notq %rsi
; HYBRID-NEXT: andq %rdi, %rsi
; HYBRID-NEXT: movl $127, %edi
; HYBRID-NEXT: bsrq %rsi, %rdi
-; HYBRID-NEXT: xorq $63, %rdi
-; HYBRID-NEXT: addq $64, %rdi
+; HYBRID-NEXT: xorl $63, %edi
+; HYBRID-NEXT: addl $64, %edi
; HYBRID-NEXT: testq %rdx, %rdx
-; HYBRID-NEXT: cmovneq %r10, %rdi
-; HYBRID-NEXT: subq $-128, %rdi
+; HYBRID-NEXT: cmovnel %r10d, %edi
+; HYBRID-NEXT: subl $-128, %edi
; HYBRID-NEXT: orq %r8, %rcx
; HYBRID-NEXT: cmovneq %r9, %rdi
; HYBRID-NEXT: movq %rdi, (%rax)
@@ -517,23 +517,23 @@ define i256 @test3(i256 %n) nounwind {
; BURR-NEXT: notq %rcx
; BURR-NEXT: andq %r11, %rcx
; BURR-NEXT: bsrq %rcx, %r9
-; BURR-NEXT: xorq $63, %r9
-; BURR-NEXT: orq $64, %r9
+; BURR-NEXT: xorl $63, %r9d
+; BURR-NEXT: orl $64, %r9d
; BURR-NEXT: testq %r8, %r8
; BURR-NEXT: cmovneq %rbx, %r9
; BURR-NEXT: notq %rdx
; BURR-NEXT: andq %r10, %rdx
; BURR-NEXT: bsrq %rdx, %r10
-; BURR-NEXT: xorq $63, %r10
+; BURR-NEXT: xorl $63, %r10d
; BURR-NEXT: notq %rsi
; BURR-NEXT: andq %rdi, %rsi
; BURR-NEXT: movl $127, %edi
; BURR-NEXT: bsrq %rsi, %rdi
-; BURR-NEXT: xorq $63, %rdi
-; BURR-NEXT: addq $64, %rdi
+; BURR-NEXT: xorl $63, %edi
+; BURR-NEXT: addl $64, %edi
; BURR-NEXT: testq %rdx, %rdx
-; BURR-NEXT: cmovneq %r10, %rdi
-; BURR-NEXT: subq $-128, %rdi
+; BURR-NEXT: cmovnel %r10d, %edi
+; BURR-NEXT: subl $-128, %edi
; BURR-NEXT: orq %r8, %rcx
; BURR-NEXT: cmovneq %r9, %rdi
; BURR-NEXT: movq %rdi, (%rax)
@@ -560,24 +560,24 @@ define i256 @test3(i256 %n) nounwind {
; SRC-NEXT: andq %r11, %rcx
; SRC-NEXT: andq %r9, %r8
; SRC-NEXT: andq %rdi, %rsi
-; SRC-NEXT: bsrq %r8, %rdi
-; SRC-NEXT: xorq $63, %rdi
-; SRC-NEXT: bsrq %rcx, %r9
+; SRC-NEXT: bsrq %r8, %r9
; SRC-NEXT: xorq $63, %r9
-; SRC-NEXT: orq $64, %r9
+; SRC-NEXT: bsrq %rcx, %rdi
+; SRC-NEXT: xorl $63, %edi
+; SRC-NEXT: orl $64, %edi
; SRC-NEXT: testq %r8, %r8
-; SRC-NEXT: cmovneq %rdi, %r9
-; SRC-NEXT: bsrq %rdx, %rdi
-; SRC-NEXT: xorq $63, %rdi
+; SRC-NEXT: cmovneq %r9, %rdi
+; SRC-NEXT: bsrq %rdx, %r9
+; SRC-NEXT: xorl $63, %r9d
; SRC-NEXT: movl $127, %r10d
; SRC-NEXT: bsrq %rsi, %r10
-; SRC-NEXT: xorq $63, %r10
-; SRC-NEXT: addq $64, %r10
+; SRC-NEXT: xorl $63, %r10d
+; SRC-NEXT: addl $64, %r10d
; SRC-NEXT: testq %rdx, %rdx
-; SRC-NEXT: cmovneq %rdi, %r10
-; SRC-NEXT: subq $-128, %r10
+; SRC-NEXT: cmovnel %r9d, %r10d
+; SRC-NEXT: subl $-128, %r10d
; SRC-NEXT: orq %rcx, %r8
-; SRC-NEXT: cmovneq %r9, %r10
+; SRC-NEXT: cmovneq %rdi, %r10
; SRC-NEXT: xorps %xmm0, %xmm0
; SRC-NEXT: movaps %xmm0, 16(%rax)
; SRC-NEXT: movq %r10, (%rax)
@@ -595,25 +595,25 @@ define i256 @test3(i256 %n) nounwind {
; LIN-NEXT: notq %rsi
; LIN-NEXT: andq %rdi, %rsi
; LIN-NEXT: bsrq %rsi, %r9
-; LIN-NEXT: xorq $63, %r9
-; LIN-NEXT: addq $64, %r9
+; LIN-NEXT: xorl $63, %r9d
+; LIN-NEXT: addl $64, %r9d
; LIN-NEXT: xorl %edi, %edi
; LIN-NEXT: movl $0, %esi
; LIN-NEXT: sbbq %rdx, %rsi
; LIN-NEXT: notq %rdx
; LIN-NEXT: andq %rsi, %rdx
; LIN-NEXT: bsrq %rdx, %rsi
-; LIN-NEXT: xorq $63, %rsi
+; LIN-NEXT: xorl $63, %esi
; LIN-NEXT: testq %rdx, %rdx
-; LIN-NEXT: cmoveq %r9, %rsi
-; LIN-NEXT: subq $-128, %rsi
+; LIN-NEXT: cmovel %r9d, %esi
+; LIN-NEXT: subl $-128, %esi
; LIN-NEXT: movl $0, %edx
; LIN-NEXT: sbbq %rcx, %rdx
; LIN-NEXT: notq %rcx
; LIN-NEXT: andq %rdx, %rcx
; LIN-NEXT: bsrq %rcx, %rdx
-; LIN-NEXT: xorq $63, %rdx
-; LIN-NEXT: orq $64, %rdx
+; LIN-NEXT: xorl $63, %edx
+; LIN-NEXT: orl $64, %edx
; LIN-NEXT: sbbq %r8, %rdi
; LIN-NEXT: notq %r8
; LIN-NEXT: andq %rdi, %r8
@@ -738,22 +738,22 @@ define i256 @PR25498(i256 %a) nounwind {
; ILP-NEXT: je .LBB4_1
; ILP-NEXT: # %bb.2: # %cond.false
; ILP-NEXT: bsrq %r10, %rdx
-; ILP-NEXT: bsrq %rdi, %rcx
-; ILP-NEXT: xorq $63, %rcx
-; ILP-NEXT: bsrq %r9, %rsi
-; ILP-NEXT: xorq $63, %rsi
-; ILP-NEXT: orq $64, %rsi
-; ILP-NEXT: testq %rdi, %rdi
-; ILP-NEXT: cmovneq %rcx, %rsi
-; ILP-NEXT: xorq $63, %rdx
+; ILP-NEXT: bsrq %rdi, %rsi
+; ILP-NEXT: xorl $63, %edx
; ILP-NEXT: bsrq %r11, %rcx
-; ILP-NEXT: xorq $63, %rcx
-; ILP-NEXT: orq $64, %rcx
+; ILP-NEXT: xorl $63, %ecx
+; ILP-NEXT: orl $64, %ecx
; ILP-NEXT: testq %r10, %r10
-; ILP-NEXT: cmovneq %rdx, %rcx
-; ILP-NEXT: orq $128, %rcx
+; ILP-NEXT: cmovnel %edx, %ecx
+; ILP-NEXT: xorq $63, %rsi
+; ILP-NEXT: bsrq %r9, %rdx
+; ILP-NEXT: xorl $63, %edx
+; ILP-NEXT: orl $64, %edx
+; ILP-NEXT: testq %rdi, %rdi
+; ILP-NEXT: cmovneq %rsi, %rdx
+; ILP-NEXT: subl $-128, %ecx
; ILP-NEXT: orq %rdi, %r9
-; ILP-NEXT: cmovneq %rsi, %rcx
+; ILP-NEXT: cmovneq %rdx, %rcx
; ILP-NEXT: jmp .LBB4_3
; ILP-NEXT: .LBB4_1:
; ILP-NEXT: movl $256, %ecx # imm = 0x100
@@ -783,18 +783,18 @@ define i256 @PR25498(i256 %a) nounwind {
; HYBRID-NEXT: bsrq %rdi, %rcx
; HYBRID-NEXT: xorq $63, %rcx
; HYBRID-NEXT: bsrq %r9, %rdx
-; HYBRID-NEXT: xorq $63, %rdx
-; HYBRID-NEXT: orq $64, %rdx
+; HYBRID-NEXT: xorl $63, %edx
+; HYBRID-NEXT: orl $64, %edx
; HYBRID-NEXT: testq %rdi, %rdi
; HYBRID-NEXT: cmovneq %rcx, %rdx
; HYBRID-NEXT: bsrq %r10, %rsi
-; HYBRID-NEXT: xorq $63, %rsi
+; HYBRID-NEXT: xorl $63, %esi
; HYBRID-NEXT: bsrq %r11, %rcx
-; HYBRID-NEXT: xorq $63, %rcx
-; HYBRID-NEXT: orq $64, %rcx
+; HYBRID-NEXT: xorl $63, %ecx
+; HYBRID-NEXT: orl $64, %ecx
; HYBRID-NEXT: testq %r10, %r10
-; HYBRID-NEXT: cmovneq %rsi, %rcx
-; HYBRID-NEXT: orq $128, %rcx
+; HYBRID-NEXT: cmovnel %esi, %ecx
+; HYBRID-NEXT: subl $-128, %ecx
; HYBRID-NEXT: orq %rdi, %r9
; HYBRID-NEXT: cmovneq %rdx, %rcx
; HYBRID-NEXT: jmp .LBB4_3
@@ -826,18 +826,18 @@ define i256 @PR25498(i256 %a) nounwind {
; BURR-NEXT: bsrq %rdi, %rcx
; BURR-NEXT: xorq $63, %rcx
; BURR-NEXT: bsrq %r9, %rdx
-; BURR-NEXT: xorq $63, %rdx
-; BURR-NEXT: orq $64, %rdx
+; BURR-NEXT: xorl $63, %edx
+; BURR-NEXT: orl $64, %edx
; BURR-NEXT: testq %rdi, %rdi
; BURR-NEXT: cmovneq %rcx, %rdx
; BURR-NEXT: bsrq %r10, %rsi
-; BURR-NEXT: xorq $63, %rsi
+; BURR-NEXT: xorl $63, %esi
; BURR-NEXT: bsrq %r11, %rcx
-; BURR-NEXT: xorq $63, %rcx
-; BURR-NEXT: orq $64, %rcx
+; BURR-NEXT: xorl $63, %ecx
+; BURR-NEXT: orl $64, %ecx
; BURR-NEXT: testq %r10, %r10
-; BURR-NEXT: cmovneq %rsi, %rcx
-; BURR-NEXT: orq $128, %rcx
+; BURR-NEXT: cmovnel %esi, %ecx
+; BURR-NEXT: subl $-128, %ecx
; BURR-NEXT: orq %rdi, %r9
; BURR-NEXT: cmovneq %rdx, %rcx
; BURR-NEXT: jmp .LBB4_3
@@ -869,18 +869,18 @@ define i256 @PR25498(i256 %a) nounwind {
; SRC-NEXT: bsrq %rdi, %rcx
; SRC-NEXT: xorq $63, %rcx
; SRC-NEXT: bsrq %r9, %rdx
-; SRC-NEXT: xorq $63, %rdx
-; SRC-NEXT: orq $64, %rdx
+; SRC-NEXT: xorl $63, %edx
+; SRC-NEXT: orl $64, %edx
; SRC-NEXT: testq %rdi, %rdi
; SRC-NEXT: cmovneq %rcx, %rdx
; SRC-NEXT: bsrq %r10, %rsi
-; SRC-NEXT: xorq $63, %rsi
+; SRC-NEXT: xorl $63, %esi
; SRC-NEXT: bsrq %r11, %rcx
-; SRC-NEXT: xorq $63, %rcx
-; SRC-NEXT: orq $64, %rcx
+; SRC-NEXT: xorl $63, %ecx
+; SRC-NEXT: orl $64, %ecx
; SRC-NEXT: testq %r10, %r10
-; SRC-NEXT: cmovneq %rsi, %rcx
-; SRC-NEXT: orq $128, %rcx
+; SRC-NEXT: cmovnel %esi, %ecx
+; SRC-NEXT: subl $-128, %ecx
; SRC-NEXT: orq %rdi, %r9
; SRC-NEXT: cmovneq %rdx, %rcx
; SRC-NEXT: jmp .LBB4_3
@@ -910,16 +910,16 @@ define i256 @PR25498(i256 %a) nounwind {
; LIN-NEXT: je .LBB4_1
; LIN-NEXT: # %bb.2: # %cond.false
; LIN-NEXT: bsrq %r11, %rcx
-; LIN-NEXT: xorq $63, %rcx
-; LIN-NEXT: orq $64, %rcx
+; LIN-NEXT: xorl $63, %ecx
+; LIN-NEXT: orl $64, %ecx
; LIN-NEXT: bsrq %r10, %rdx
-; LIN-NEXT: xorq $63, %rdx
+; LIN-NEXT: xorl $63, %edx
; LIN-NEXT: testq %r10, %r10
-; LIN-NEXT: cmoveq %rcx, %rdx
-; LIN-NEXT: orq $128, %rdx
+; LIN-NEXT: cmovel %ecx, %edx
+; LIN-NEXT: subl $-128, %edx
; LIN-NEXT: bsrq %r9, %rsi
-; LIN-NEXT: xorq $63, %rsi
-; LIN-NEXT: orq $64, %rsi
+; LIN-NEXT: xorl $63, %esi
+; LIN-NEXT: orl $64, %esi
; LIN-NEXT: bsrq %rdi, %rcx
; LIN-NEXT: xorq $63, %rcx
; LIN-NEXT: testq %rdi, %rdi
diff --git a/llvm/test/CodeGen/X86/vector-compress.ll b/llvm/test/CodeGen/X86/vector-compress.ll
index 01bdf0a098e7a..15c27e5d02783 100644
--- a/llvm/test/CodeGen/X86/vector-compress.ll
+++ b/llvm/test/CodeGen/X86/vector-compress.ll
@@ -10,32 +10,30 @@ define <4 x i32> @test_compress_v4i32(<4 x i32> %vec, <4 x i1> %mask, <4 x i32>
; AVX2-NEXT: vpsrad $31, %xmm1, %xmm1
; AVX2-NEXT: vmovaps %xmm2, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vpextrd $1, %xmm1, %eax
-; AVX2-NEXT: vmovd %xmm1, %esi
-; AVX2-NEXT: andl $1, %esi
+; AVX2-NEXT: vmovd %xmm1, %ecx
+; AVX2-NEXT: andl $1, %ecx
+; AVX2-NEXT: movl %ecx, %edx
+; AVX2-NEXT: subl %eax, %edx
+; AVX2-NEXT: vpextrd $2, %xmm1, %eax
+; AVX2-NEXT: movl %edx, %esi
+; AVX2-NEXT: subl %eax, %esi
+; AVX2-NEXT: vpextrd $3, %xmm1, %eax
; AVX2-NEXT: movl %esi, %edi
; AVX2-NEXT: subl %eax, %edi
-; AVX2-NEXT: vpextrd $2, %xmm1, %edx
-; AVX2-NEXT: subl %edx, %edi
-; AVX2-NEXT: vpextrd $3, %xmm1, %ecx
-; AVX2-NEXT: subl %ecx, %edi
-; AVX2-NEXT: andl $3, %edi
-; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rsi, %rax
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rdx, %rcx
+; AVX2-NEXT: movl %edi, %eax
+; AVX2-NEXT: andl $3, %eax
; AVX2-NEXT: vextractps $3, %xmm0, %r8d
-; AVX2-NEXT: cmpq $4, %rcx
-; AVX2-NEXT: cmovbl -24(%rsp,%rdi,4), %r8d
+; AVX2-NEXT: cmpq $4, %rdi
+; AVX2-NEXT: cmovbl -24(%rsp,%rax,4), %r8d
; AVX2-NEXT: vmovss %xmm0, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vextractps $1, %xmm0, -24(%rsp,%rsi,4)
-; AVX2-NEXT: vextractps $2, %xmm0, -24(%rsp,%rax,4)
-; AVX2-NEXT: andl $3, %edx
-; AVX2-NEXT: vextractps $3, %xmm0, -24(%rsp,%rdx,4)
-; AVX2-NEXT: cmpq $3, %rcx
+; AVX2-NEXT: vextractps $1, %xmm0, -24(%rsp,%rcx,4)
+; AVX2-NEXT: shll $2, %edx
+; AVX2-NEXT: vextractps $2, %xmm0, -24(%rsp,%rdx)
+; AVX2-NEXT: andl $3, %esi
+; AVX2-NEXT: vextractps $3, %xmm0, -24(%rsp,%rsi,4)
+; AVX2-NEXT: cmpq $3, %rdi
; AVX2-NEXT: movl $3, %eax
-; AVX2-NEXT: cmovbq %rcx, %rax
+; AVX2-NEXT: cmovbq %rdi, %rax
; AVX2-NEXT: movl %r8d, -24(%rsp,%rax,4)
; AVX2-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX2-NEXT: retq
@@ -70,38 +68,35 @@ define <4 x float> @test_compress_v4f32(<4 x float> %vec, <4 x i1> %mask, <4 x f
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
; AVX2-NEXT: vpsrad $31, %xmm1, %xmm1
; AVX2-NEXT: vmovaps %xmm2, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vpextrd $1, %xmm1, %edx
-; AVX2-NEXT: vmovd %xmm1, %esi
-; AVX2-NEXT: andl $1, %esi
-; AVX2-NEXT: movl %esi, %edi
-; AVX2-NEXT: subl %edx, %edi
-; AVX2-NEXT: vpextrd $2, %xmm1, %ecx
-; AVX2-NEXT: subl %ecx, %edi
+; AVX2-NEXT: vpextrd $1, %xmm1, %eax
+; AVX2-NEXT: vmovd %xmm1, %ecx
+; AVX2-NEXT: andl $1, %ecx
+; AVX2-NEXT: movl %ecx, %edx
+; AVX2-NEXT: subl %eax, %edx
+; AVX2-NEXT: vpextrd $2, %xmm1, %eax
+; AVX2-NEXT: movl %edx, %esi
+; AVX2-NEXT: subl %eax, %esi
; AVX2-NEXT: vpextrd $3, %xmm1, %eax
+; AVX2-NEXT: movl %esi, %edi
; AVX2-NEXT: subl %eax, %edi
-; AVX2-NEXT: andl $3, %edi
+; AVX2-NEXT: movl %edi, %eax
+; AVX2-NEXT: andl $3, %eax
; AVX2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX2-NEXT: vmovss %xmm0, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vextractps $1, %xmm0, -24(%rsp,%rsi,4)
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rsi, %rdx
-; AVX2-NEXT: vextractps $2, %xmm0, -24(%rsp,%rdx,4)
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: # kill: def $ecx killed $ecx killed $rcx def $rcx
-; AVX2-NEXT: andl $3, %ecx
+; AVX2-NEXT: vextractps $1, %xmm0, -24(%rsp,%rcx,4)
+; AVX2-NEXT: shll $2, %edx
+; AVX2-NEXT: vextractps $2, %xmm0, -24(%rsp,%rdx)
+; AVX2-NEXT: andl $3, %esi
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX2-NEXT: vmovss %xmm0, -24(%rsp,%rcx,4)
-; AVX2-NEXT: cmpq $3, %rax
-; AVX2-NEXT: movl $3, %ecx
-; AVX2-NEXT: cmovbq %rax, %rcx
+; AVX2-NEXT: vmovss %xmm0, -24(%rsp,%rsi,4)
+; AVX2-NEXT: cmpq $3, %rdi
+; AVX2-NEXT: movl $3, %eax
+; AVX2-NEXT: cmovbq %rdi, %rax
; AVX2-NEXT: ja .LBB1_2
; AVX2-NEXT: # %bb.1:
; AVX2-NEXT: vmovaps %xmm1, %xmm0
; AVX2-NEXT: .LBB1_2:
-; AVX2-NEXT: vmovss %xmm0, -24(%rsp,%rcx,4)
+; AVX2-NEXT: vmovss %xmm0, -24(%rsp,%rax,4)
; AVX2-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX2-NEXT: retq
;
@@ -265,19 +260,19 @@ define <8 x i32> @test_compress_v8i32(<8 x i32> %vec, <8 x i1> %mask, <8 x i32>
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: vmovd %xmm3, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rdx, %rcx
+; AVX2-NEXT: addl %edx, %ecx
; AVX2-NEXT: vpextrd $2, %xmm3, %esi
; AVX2-NEXT: andl $1, %esi
-; AVX2-NEXT: addq %rcx, %rsi
+; AVX2-NEXT: addl %ecx, %esi
; AVX2-NEXT: vpextrd $3, %xmm3, %edi
; AVX2-NEXT: andl $1, %edi
-; AVX2-NEXT: addq %rsi, %rdi
+; AVX2-NEXT: addl %esi, %edi
; AVX2-NEXT: vmovd %xmm1, %r8d
; AVX2-NEXT: andl $1, %r8d
-; AVX2-NEXT: addq %rdi, %r8
+; AVX2-NEXT: addl %edi, %r8d
; AVX2-NEXT: vpextrd $1, %xmm1, %r9d
; AVX2-NEXT: andl $1, %r9d
-; AVX2-NEXT: addq %r8, %r9
+; AVX2-NEXT: addl %r8d, %r9d
; AVX2-NEXT: vpextrd $2, %xmm1, %r10d
; AVX2-NEXT: andl $1, %r10d
; AVX2-NEXT: addq %r9, %r10
@@ -366,26 +361,26 @@ define <8 x float> @test_compress_v8f32(<8 x float> %vec, <8 x i1> %mask, <8 x f
; AVX2-NEXT: vextractps $1, %xmm0, (%rsp,%rax,4)
; AVX2-NEXT: vpextrd $1, %xmm3, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: vextractps $2, %xmm0, (%rsp,%rcx,4)
; AVX2-NEXT: vpextrd $2, %xmm3, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: vextractps $3, %xmm0, (%rsp,%rax,4)
; AVX2-NEXT: vpextrd $3, %xmm3, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: vmovd %xmm1, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: # kill: def $ecx killed $ecx killed $rcx def $rcx
+; AVX2-NEXT: addl %ecx, %eax
+; AVX2-NEXT: # kill: def $ecx killed $ecx def $rcx
; AVX2-NEXT: andl $7, %ecx
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovss %xmm0, (%rsp,%rcx,4)
; AVX2-NEXT: vpextrd $1, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
-; AVX2-NEXT: # kill: def $eax killed $eax killed $rax def $rax
+; AVX2-NEXT: addl %eax, %ecx
+; AVX2-NEXT: # kill: def $eax killed $eax def $rax
; AVX2-NEXT: andl $7, %eax
; AVX2-NEXT: vextractps $1, %xmm0, (%rsp,%rax,4)
; AVX2-NEXT: vpextrd $2, %xmm1, %edx
@@ -610,35 +605,34 @@ define <16 x i32> @test_compress_v16i32(<16 x i32> %vec, <16 x i1> %mask, <16 x
; AVX2-NEXT: vmovd %xmm3, %ecx
; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: vpextrd $2, %xmm3, %eax
-; AVX2-NEXT: vpextrd $3, %xmm3, %edx
-; AVX2-NEXT: addl %eax, %edx
-; AVX2-NEXT: addl %ecx, %edx
-; AVX2-NEXT: andl $15, %edx
-; AVX2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; AVX2-NEXT: vpextrd $3, %xmm3, %esi
+; AVX2-NEXT: addl %eax, %esi
+; AVX2-NEXT: addl %ecx, %esi
+; AVX2-NEXT: andl $15, %esi
; AVX2-NEXT: vpextrb $1, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: vmovd %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $2, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $3, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $4, %xmm2, %r8d
; AVX2-NEXT: andl $1, %r8d
-; AVX2-NEXT: addq %rax, %r8
+; AVX2-NEXT: addl %eax, %r8d
; AVX2-NEXT: vpextrb $5, %xmm2, %r9d
; AVX2-NEXT: andl $1, %r9d
-; AVX2-NEXT: addq %r8, %r9
+; AVX2-NEXT: addl %r8d, %r9d
; AVX2-NEXT: vpextrb $6, %xmm2, %r10d
; AVX2-NEXT: andl $1, %r10d
-; AVX2-NEXT: addq %r9, %r10
+; AVX2-NEXT: addl %r9d, %r10d
; AVX2-NEXT: vpextrb $7, %xmm2, %r11d
; AVX2-NEXT: andl $1, %r11d
; AVX2-NEXT: addq %r10, %r11
@@ -668,10 +662,8 @@ define <16 x i32> @test_compress_v16i32(<16 x i32> %vec, <16 x i1> %mask, <16 x
; AVX2-NEXT: addq %rax, %rdx
; AVX2-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX2-NEXT: cmpq $16, %rdx
-; AVX2-NEXT: vextractps $3, %xmm2, %esi
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
-; AVX2-NEXT: cmovbl (%rsp,%rdi,4), %esi
-; AVX2-NEXT: movl %esi, %edi
+; AVX2-NEXT: vextractps $3, %xmm2, %edi
+; AVX2-NEXT: cmovbl (%rsp,%rsi,4), %edi
; AVX2-NEXT: vmovss %xmm0, (%rsp)
; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
; AVX2-NEXT: vextractps $1, %xmm0, (%rsp,%rsi,4)
@@ -771,30 +763,30 @@ define <16 x float> @test_compress_v16f32(<16 x float> %vec, <16 x i1> %mask, <1
; AVX2-NEXT: vextractps $1, %xmm0, (%rsp,%rax,4)
; AVX2-NEXT: vpextrb $1, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: vextractps $2, %xmm0, (%rsp,%rcx,4)
; AVX2-NEXT: vpextrb $2, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: vextractps $3, %xmm0, (%rsp,%rax,4)
; AVX2-NEXT: vpextrb $3, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovss %xmm0, (%rsp,%rcx,4)
; AVX2-NEXT: vpextrb $4, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: vpextrb $5, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
-; AVX2-NEXT: # kill: def $eax killed $eax killed $rax def $rax
+; AVX2-NEXT: addl %eax, %ecx
+; AVX2-NEXT: # kill: def $eax killed $eax def $rax
; AVX2-NEXT: andl $15, %eax
; AVX2-NEXT: vextractps $1, %xmm0, (%rsp,%rax,4)
; AVX2-NEXT: vpextrb $6, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: # kill: def $ecx killed $ecx killed $rcx def $rcx
+; AVX2-NEXT: addl %ecx, %eax
+; AVX2-NEXT: # kill: def $ecx killed $ecx def $rcx
; AVX2-NEXT: andl $15, %ecx
; AVX2-NEXT: vextractps $2, %xmm0, (%rsp,%rcx,4)
; AVX2-NEXT: vpextrb $7, %xmm2, %ecx
@@ -914,22 +906,22 @@ define <8 x i64> @test_compress_v8i64(<8 x i64> %vec, <8 x i1> %mask, <8 x i64>
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: vmovd %xmm2, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rdx, %rcx
+; AVX2-NEXT: addl %edx, %ecx
; AVX2-NEXT: vpextrw $2, %xmm2, %esi
; AVX2-NEXT: andl $1, %esi
-; AVX2-NEXT: addq %rcx, %rsi
+; AVX2-NEXT: addl %ecx, %esi
; AVX2-NEXT: vpextrw $3, %xmm2, %edi
; AVX2-NEXT: andl $1, %edi
-; AVX2-NEXT: addq %rsi, %rdi
+; AVX2-NEXT: addl %esi, %edi
; AVX2-NEXT: vpextrw $4, %xmm2, %r8d
; AVX2-NEXT: andl $1, %r8d
-; AVX2-NEXT: addq %rdi, %r8
+; AVX2-NEXT: addl %edi, %r8d
; AVX2-NEXT: vpextrw $5, %xmm2, %r9d
; AVX2-NEXT: andl $1, %r9d
-; AVX2-NEXT: addq %r8, %r9
+; AVX2-NEXT: addl %r8d, %r9d
; AVX2-NEXT: vpextrw $6, %xmm2, %r10d
; AVX2-NEXT: andl $1, %r10d
-; AVX2-NEXT: addq %r9, %r10
+; AVX2-NEXT: addl %r9d, %r10d
; AVX2-NEXT: vpextrw $7, %xmm2, %r11d
; AVX2-NEXT: andl $1, %r11d
; AVX2-NEXT: addq %r10, %r11
@@ -1009,35 +1001,35 @@ define <8 x double> @test_compress_v8f64(<8 x double> %vec, <8 x i1> %mask, <8 x
; AVX2-NEXT: vmovhps %xmm0, (%rsp,%rax,8)
; AVX2-NEXT: vpextrw $1, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovlps %xmm0, (%rsp,%rcx,8)
; AVX2-NEXT: vpextrw $2, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: vmovhps %xmm0, (%rsp,%rax,8)
; AVX2-NEXT: vpextrw $3, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: vpextrw $4, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: # kill: def $ecx killed $ecx killed $rcx def $rcx
+; AVX2-NEXT: addl %ecx, %eax
+; AVX2-NEXT: # kill: def $ecx killed $ecx def $rcx
; AVX2-NEXT: andl $7, %ecx
; AVX2-NEXT: vmovlpd %xmm1, (%rsp,%rcx,8)
; AVX2-NEXT: vpextrw $5, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
-; AVX2-NEXT: # kill: def $eax killed $eax killed $rax def $rax
+; AVX2-NEXT: addl %eax, %ecx
+; AVX2-NEXT: # kill: def $eax killed $eax def $rax
; AVX2-NEXT: andl $7, %eax
; AVX2-NEXT: vmovhpd %xmm1, (%rsp,%rax,8)
; AVX2-NEXT: vpextrw $6, %xmm2, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: # kill: def $ecx killed $ecx killed $rcx def $rcx
-; AVX2-NEXT: andl $7, %ecx
+; AVX2-NEXT: addl %ecx, %edx
+; AVX2-NEXT: movl %ecx, %eax
+; AVX2-NEXT: andl $7, %eax
; AVX2-NEXT: vextractf128 $1, %ymm1, %xmm0
-; AVX2-NEXT: vmovlpd %xmm0, (%rsp,%rcx,8)
+; AVX2-NEXT: vmovlpd %xmm0, (%rsp,%rax,8)
; AVX2-NEXT: vpextrw $7, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: addq %rdx, %rax
@@ -1093,19 +1085,19 @@ define <16 x i8> @test_compress_v16i8(<16 x i8> %vec, <16 x i1> %mask, <16 x i8>
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpcmpgtb %xmm1, %xmm3, %xmm1
; AVX2-NEXT: vmovaps %xmm2, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vpextrb $1, %xmm1, %r13d
+; AVX2-NEXT: vpextrb $1, %xmm1, %r12d
; AVX2-NEXT: vmovd %xmm1, %esi
; AVX2-NEXT: movl %esi, %eax
; AVX2-NEXT: andb $1, %al
-; AVX2-NEXT: subb %r13b, %al
+; AVX2-NEXT: subb %r12b, %al
; AVX2-NEXT: vpextrb $2, %xmm1, %edx
; AVX2-NEXT: subb %dl, %al
-; AVX2-NEXT: vpextrb $3, %xmm1, %ebp
-; AVX2-NEXT: subb %bpl, %al
-; AVX2-NEXT: vpextrb $4, %xmm1, %r12d
-; AVX2-NEXT: subb %r12b, %al
-; AVX2-NEXT: vpextrb $5, %xmm1, %r15d
+; AVX2-NEXT: vpextrb $3, %xmm1, %r13d
+; AVX2-NEXT: subb %r13b, %al
+; AVX2-NEXT: vpextrb $4, %xmm1, %r15d
; AVX2-NEXT: subb %r15b, %al
+; AVX2-NEXT: vpextrb $5, %xmm1, %ebp
+; AVX2-NEXT: subb %bpl, %al
; AVX2-NEXT: vpextrb $6, %xmm1, %r14d
; AVX2-NEXT: subb %r14b, %al
; AVX2-NEXT: vpextrb $7, %xmm1, %ebx
@@ -1135,27 +1127,27 @@ define <16 x i8> @test_compress_v16i8(<16 x i8> %vec, <16 x i1> %mask, <16 x i8>
; AVX2-NEXT: vpextrb $0, %xmm0, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: andl $1, %esi
; AVX2-NEXT: vpextrb $1, %xmm0, -40(%rsp,%rsi)
-; AVX2-NEXT: andl $1, %r13d
-; AVX2-NEXT: addq %rsi, %r13
-; AVX2-NEXT: vpextrb $2, %xmm0, -40(%rsp,%r13)
+; AVX2-NEXT: andl $1, %r12d
+; AVX2-NEXT: addl %esi, %r12d
+; AVX2-NEXT: vpextrb $2, %xmm0, -40(%rsp,%r12)
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %r13, %rdx
+; AVX2-NEXT: addl %r12d, %edx
; AVX2-NEXT: vpextrb $3, %xmm0, -40(%rsp,%rdx)
-; AVX2-NEXT: andl $1, %ebp
-; AVX2-NEXT: addq %rdx, %rbp
-; AVX2-NEXT: vpextrb $4, %xmm0, -40(%rsp,%rbp)
-; AVX2-NEXT: andl $1, %r12d
-; AVX2-NEXT: addq %rbp, %r12
+; AVX2-NEXT: andl $1, %r13d
+; AVX2-NEXT: addl %edx, %r13d
+; AVX2-NEXT: vpextrb $4, %xmm0, -40(%rsp,%r13)
; AVX2-NEXT: andl $1, %r15d
-; AVX2-NEXT: addq %r12, %r15
-; AVX2-NEXT: # kill: def $r12d killed $r12d killed $r12 def $r12
-; AVX2-NEXT: andl $15, %r12d
-; AVX2-NEXT: vpextrb $5, %xmm0, -40(%rsp,%r12)
+; AVX2-NEXT: addl %r13d, %r15d
+; AVX2-NEXT: andl $1, %ebp
+; AVX2-NEXT: addl %r15d, %ebp
+; AVX2-NEXT: movl %r15d, %eax
+; AVX2-NEXT: andl $15, %eax
+; AVX2-NEXT: vpextrb $5, %xmm0, -40(%rsp,%rax)
; AVX2-NEXT: andl $1, %r14d
-; AVX2-NEXT: addq %r15, %r14
-; AVX2-NEXT: # kill: def $r15d killed $r15d killed $r15 def $r15
-; AVX2-NEXT: andl $15, %r15d
-; AVX2-NEXT: vpextrb $6, %xmm0, -40(%rsp,%r15)
+; AVX2-NEXT: addl %ebp, %r14d
+; AVX2-NEXT: movl %ebp, %eax
+; AVX2-NEXT: andl $15, %eax
+; AVX2-NEXT: vpextrb $6, %xmm0, -40(%rsp,%rax)
; AVX2-NEXT: andl $1, %ebx
; AVX2-NEXT: addq %r14, %rbx
; AVX2-NEXT: # kill: def $r14d killed $r14d killed $r14 def $r14
@@ -1252,53 +1244,47 @@ define <8 x i16> @test_compress_v8i16(<8 x i16> %vec, <8 x i1> %mask, <8 x i16>
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: vmovd %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: leal (%rcx,%rax), %esi
-; AVX2-NEXT: vpextrw $2, %xmm1, %edi
-; AVX2-NEXT: andl $1, %edi
-; AVX2-NEXT: vpextrw $3, %xmm1, %edx
+; AVX2-NEXT: addl %ecx, %eax
+; AVX2-NEXT: vpextrw $2, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: leal (%rdi,%rdx), %r10d
-; AVX2-NEXT: addl %esi, %r10d
-; AVX2-NEXT: vpextrw $4, %xmm1, %r9d
-; AVX2-NEXT: andl $1, %r9d
-; AVX2-NEXT: vpextrw $5, %xmm1, %esi
+; AVX2-NEXT: addl %eax, %edx
+; AVX2-NEXT: vpextrw $3, %xmm1, %esi
; AVX2-NEXT: andl $1, %esi
-; AVX2-NEXT: leal (%r9,%rsi), %r11d
-; AVX2-NEXT: vpextrw $6, %xmm1, %r8d
+; AVX2-NEXT: addl %edx, %esi
+; AVX2-NEXT: vpextrw $4, %xmm1, %edi
+; AVX2-NEXT: andl $1, %edi
+; AVX2-NEXT: addl %esi, %edi
+; AVX2-NEXT: vpextrw $5, %xmm1, %r8d
; AVX2-NEXT: andl $1, %r8d
-; AVX2-NEXT: addl %r8d, %r11d
-; AVX2-NEXT: addl %r10d, %r11d
+; AVX2-NEXT: addl %edi, %r8d
+; AVX2-NEXT: vpextrw $6, %xmm1, %r9d
+; AVX2-NEXT: andl $1, %r9d
+; AVX2-NEXT: addl %r8d, %r9d
; AVX2-NEXT: vpextrw $7, %xmm1, %r10d
; AVX2-NEXT: andl $1, %r10d
-; AVX2-NEXT: addl %r10d, %r11d
-; AVX2-NEXT: andl $7, %r11d
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: addq %rax, %rdi
-; AVX2-NEXT: addq %rdi, %rdx
-; AVX2-NEXT: addq %rdx, %r9
-; AVX2-NEXT: addq %r9, %rsi
-; AVX2-NEXT: addq %rsi, %r8
-; AVX2-NEXT: addq %r8, %r10
-; AVX2-NEXT: vpextrw $7, %xmm0, %ebx
+; AVX2-NEXT: leal (%r9,%r10), %ebx
+; AVX2-NEXT: andl $7, %ebx
+; AVX2-NEXT: addq %r9, %r10
+; AVX2-NEXT: vpextrw $7, %xmm0, %r11d
; AVX2-NEXT: cmpq $8, %r10
-; AVX2-NEXT: cmovbw -16(%rsp,%r11,2), %bx
+; AVX2-NEXT: cmovbw -16(%rsp,%rbx,2), %r11w
; AVX2-NEXT: vpextrw $0, %xmm0, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vpextrw $1, %xmm0, -16(%rsp,%rcx,2)
; AVX2-NEXT: vpextrw $2, %xmm0, -16(%rsp,%rax,2)
-; AVX2-NEXT: vpextrw $3, %xmm0, -16(%rsp,%rdi,2)
-; AVX2-NEXT: andl $7, %edx
-; AVX2-NEXT: vpextrw $4, %xmm0, -16(%rsp,%rdx,2)
-; AVX2-NEXT: andl $7, %r9d
-; AVX2-NEXT: vpextrw $5, %xmm0, -16(%rsp,%r9,2)
+; AVX2-NEXT: vpextrw $3, %xmm0, -16(%rsp,%rdx,2)
; AVX2-NEXT: andl $7, %esi
-; AVX2-NEXT: vpextrw $6, %xmm0, -16(%rsp,%rsi,2)
+; AVX2-NEXT: vpextrw $4, %xmm0, -16(%rsp,%rsi,2)
+; AVX2-NEXT: andl $7, %edi
+; AVX2-NEXT: vpextrw $5, %xmm0, -16(%rsp,%rdi,2)
; AVX2-NEXT: andl $7, %r8d
-; AVX2-NEXT: vpextrw $7, %xmm0, -16(%rsp,%r8,2)
+; AVX2-NEXT: vpextrw $6, %xmm0, -16(%rsp,%r8,2)
+; AVX2-NEXT: andl $7, %r9d
+; AVX2-NEXT: vpextrw $7, %xmm0, -16(%rsp,%r9,2)
; AVX2-NEXT: cmpq $7, %r10
; AVX2-NEXT: movl $7, %eax
; AVX2-NEXT: cmovbq %r10, %rax
; AVX2-NEXT: movl %eax, %eax
-; AVX2-NEXT: movw %bx, -16(%rsp,%rax,2)
+; AVX2-NEXT: movw %r11w, -16(%rsp,%rax,2)
; AVX2-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: retq
@@ -1382,27 +1368,27 @@ define <32 x i8> @test_compress_v32i8(<32 x i8> %vec, <32 x i1> %mask, <32 x i8>
; AVX2-NEXT: vpextrb $1, %xmm0, (%rsp,%rcx)
; AVX2-NEXT: vpextrb $1, %xmm3, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: addl %ecx, %edx
; AVX2-NEXT: vpextrb $2, %xmm0, (%rsp,%rdx)
; AVX2-NEXT: vpextrb $2, %xmm3, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rdx, %rcx
+; AVX2-NEXT: addl %edx, %ecx
; AVX2-NEXT: vpextrb $3, %xmm0, (%rsp,%rcx)
; AVX2-NEXT: vpextrb $3, %xmm3, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: addl %ecx, %edx
; AVX2-NEXT: vpextrb $4, %xmm0, (%rsp,%rdx)
; AVX2-NEXT: vpextrb $4, %xmm3, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rdx, %rcx
+; AVX2-NEXT: addl %edx, %ecx
; AVX2-NEXT: vpextrb $5, %xmm0, (%rsp,%rcx)
; AVX2-NEXT: vpextrb $5, %xmm3, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: addl %ecx, %edx
; AVX2-NEXT: vpextrb $6, %xmm3, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: # kill: def $edx killed $edx killed $rdx def $rdx
+; AVX2-NEXT: addl %edx, %ecx
+; AVX2-NEXT: # kill: def $edx killed $edx def $rdx
; AVX2-NEXT: andl $31, %edx
; AVX2-NEXT: vpextrb $6, %xmm0, (%rsp,%rdx)
; AVX2-NEXT: vpextrb $7, %xmm3, %edx
@@ -1659,25 +1645,25 @@ define <16 x i16> @test_compress_v16i16(<16 x i16> %vec, <16 x i1> %mask, <16 x
; AVX2-NEXT: vmovd %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrw $2, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrw $3, %xmm1, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrw $4, %xmm1, %r8d
; AVX2-NEXT: andl $1, %r8d
-; AVX2-NEXT: addq %rax, %r8
+; AVX2-NEXT: addl %eax, %r8d
; AVX2-NEXT: vpextrw $5, %xmm1, %r9d
; AVX2-NEXT: andl $1, %r9d
-; AVX2-NEXT: addq %r8, %r9
+; AVX2-NEXT: addl %r8d, %r9d
; AVX2-NEXT: vpextrw $6, %xmm1, %r10d
; AVX2-NEXT: andl $1, %r10d
-; AVX2-NEXT: addq %r9, %r10
+; AVX2-NEXT: addl %r9d, %r10d
; AVX2-NEXT: vpextrw $7, %xmm1, %r11d
; AVX2-NEXT: andl $1, %r11d
; AVX2-NEXT: addq %r10, %r11
@@ -1969,20 +1955,19 @@ define <64 x i8> @test_compress_v64i8(<64 x i8> %vec, <64 x i1> %mask, <64 x i8>
; AVX2-NEXT: andl $1, %edi
; AVX2-NEXT: vpextrb $1, %xmm0, (%rsp,%rdi)
; AVX2-NEXT: andl $1, %esi
-; AVX2-NEXT: addq %rdi, %rsi
+; AVX2-NEXT: addl %edi, %esi
; AVX2-NEXT: vpextrb $2, %xmm0, (%rsp,%rsi)
; AVX2-NEXT: andl $1, %r8d
-; AVX2-NEXT: addq %rsi, %r8
+; AVX2-NEXT: addl %esi, %r8d
; AVX2-NEXT: vpextrb $3, %xmm0, (%rsp,%r8)
; AVX2-NEXT: andl $1, %r9d
-; AVX2-NEXT: addq %r8, %r9
+; AVX2-NEXT: addl %r8d, %r9d
; AVX2-NEXT: vpextrb $4, %xmm0, (%rsp,%r9)
; AVX2-NEXT: andl $1, %r10d
-; AVX2-NEXT: addq %r9, %r10
-; AVX2-NEXT: movl %r10d, %eax
-; AVX2-NEXT: vpextrb $5, %xmm0, (%rsp,%rax)
+; AVX2-NEXT: addl %r9d, %r10d
+; AVX2-NEXT: vpextrb $5, %xmm0, (%rsp,%r10)
; AVX2-NEXT: andl $1, %r11d
-; AVX2-NEXT: addq %r10, %r11
+; AVX2-NEXT: addl %r10d, %r11d
; AVX2-NEXT: movzbl %bl, %eax
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: addq %r11, %rax
@@ -2972,27 +2957,27 @@ define <32 x i16> @test_compress_v32i16(<32 x i16> %vec, <32 x i1> %mask, <32 x
; AVX2-NEXT: vmovd %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $2, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $3, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $4, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $5, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $6, %xmm2, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX2-NEXT: vpextrb $7, %xmm2, %eax
; AVX2-NEXT: andl $1, %eax
@@ -4317,22 +4302,22 @@ define <8 x i64> @test_compress_knownbits_zext_v8i16_8i64(<8 x i16> %vec, <8 x
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: vmovd %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rdx, %rcx
+; AVX2-NEXT: addl %edx, %ecx
; AVX2-NEXT: vpextrw $2, %xmm1, %esi
; AVX2-NEXT: andl $1, %esi
-; AVX2-NEXT: addq %rcx, %rsi
+; AVX2-NEXT: addl %ecx, %esi
; AVX2-NEXT: vpextrw $3, %xmm1, %edi
; AVX2-NEXT: andl $1, %edi
-; AVX2-NEXT: addq %rsi, %rdi
+; AVX2-NEXT: addl %esi, %edi
; AVX2-NEXT: vpextrw $4, %xmm1, %r8d
; AVX2-NEXT: andl $1, %r8d
-; AVX2-NEXT: addq %rdi, %r8
+; AVX2-NEXT: addl %edi, %r8d
; AVX2-NEXT: vpextrw $5, %xmm1, %r9d
; AVX2-NEXT: andl $1, %r9d
-; AVX2-NEXT: addq %r8, %r9
+; AVX2-NEXT: addl %r8d, %r9d
; AVX2-NEXT: vpextrw $6, %xmm1, %r10d
; AVX2-NEXT: andl $1, %r10d
-; AVX2-NEXT: addq %r9, %r10
+; AVX2-NEXT: addl %r9d, %r10d
; AVX2-NEXT: vpextrw $7, %xmm1, %r11d
; AVX2-NEXT: andl $1, %r11d
; AVX2-NEXT: addq %r10, %r11
@@ -4421,22 +4406,22 @@ define <8 x i64> @test_compress_knownbits_sext_v8i16_8i64(<8 x i16> %vec, <8 x i
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: vmovd %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: addq %rdx, %rcx
+; AVX2-NEXT: addl %edx, %ecx
; AVX2-NEXT: vpextrw $2, %xmm1, %esi
; AVX2-NEXT: andl $1, %esi
-; AVX2-NEXT: addq %rcx, %rsi
+; AVX2-NEXT: addl %ecx, %esi
; AVX2-NEXT: vpextrw $3, %xmm1, %edi
; AVX2-NEXT: andl $1, %edi
-; AVX2-NEXT: addq %rsi, %rdi
+; AVX2-NEXT: addl %esi, %edi
; AVX2-NEXT: vpextrw $4, %xmm1, %r8d
; AVX2-NEXT: andl $1, %r8d
-; AVX2-NEXT: addq %rdi, %r8
+; AVX2-NEXT: addl %edi, %r8d
; AVX2-NEXT: vpextrw $5, %xmm1, %r9d
; AVX2-NEXT: andl $1, %r9d
-; AVX2-NEXT: addq %r8, %r9
+; AVX2-NEXT: addl %r8d, %r9d
; AVX2-NEXT: vpextrw $6, %xmm1, %r10d
; AVX2-NEXT: andl $1, %r10d
-; AVX2-NEXT: addq %r9, %r10
+; AVX2-NEXT: addl %r9d, %r10d
; AVX2-NEXT: vpextrw $7, %xmm1, %r11d
; AVX2-NEXT: andl $1, %r11d
; AVX2-NEXT: addq %r10, %r11
@@ -4600,15 +4585,26 @@ define <4 x i8> @test_compress_small(<4 x i8> %vec, <4 x i1> %mask) nounwind {
; AVX2-NEXT: vpextrb $1, %xmm0, -24(%rsp,%rax)
; AVX2-NEXT: vpextrb $1, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: vpextrb $2, %xmm0, -24(%rsp,%rcx)
; AVX2-NEXT: vpextrb $2, %xmm1, %eax
; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: vpextrb $3, %xmm0, -24(%rsp,%rax)
; AVX2-NEXT: vpextrb $3, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
+; AVX2-NEXT: addl %eax, %ecx
+; AVX2-NEXT: vpextrb $4, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $5, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $6, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $7, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $8, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $9, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $10, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $11, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $12, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $13, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrb $14, %xmm0, -24(%rsp,%rcx)
; AVX2-NEXT: vpextrb $15, %xmm0, -24(%rsp,%rcx)
; AVX2-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX2-NEXT: retq
@@ -4852,25 +4848,23 @@ define <4 x i32> @test_compress_v4i32_zero_passthru(<4 x i32> %vec, <4 x i1> %ma
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: vextractps $1, %xmm0, -24(%rsp,%rax,4)
; AVX2-NEXT: vpextrd $1, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
-; AVX2-NEXT: vextractps $2, %xmm0, -24(%rsp,%rcx,4)
-; AVX2-NEXT: vpextrd $2, %xmm1, %eax
-; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: addq %rcx, %rax
+; AVX2-NEXT: subl %ecx, %eax
+; AVX2-NEXT: leal (,%rax,4), %ecx
+; AVX2-NEXT: vextractps $2, %xmm0, -24(%rsp,%rcx)
+; AVX2-NEXT: vpextrd $2, %xmm1, %ecx
+; AVX2-NEXT: subl %ecx, %eax
+; AVX2-NEXT: movl %eax, %ecx
+; AVX2-NEXT: andl $3, %ecx
+; AVX2-NEXT: vextractps $3, %xmm0, -24(%rsp,%rcx,4)
; AVX2-NEXT: vpextrd $3, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: addq %rax, %rcx
-; AVX2-NEXT: # kill: def $eax killed $eax killed $rax def $rax
-; AVX2-NEXT: andl $3, %eax
-; AVX2-NEXT: vextractps $3, %xmm0, -24(%rsp,%rax,4)
-; AVX2-NEXT: xorl %eax, %eax
-; AVX2-NEXT: cmpq $3, %rcx
+; AVX2-NEXT: subl %ecx, %eax
+; AVX2-NEXT: xorl %ecx, %ecx
+; AVX2-NEXT: cmpq $3, %rax
; AVX2-NEXT: movl $3, %edx
-; AVX2-NEXT: cmovbq %rcx, %rdx
-; AVX2-NEXT: vextractps $3, %xmm0, %ecx
-; AVX2-NEXT: cmovbel %eax, %ecx
-; AVX2-NEXT: movl %ecx, -24(%rsp,%rdx,4)
+; AVX2-NEXT: cmovbq %rax, %rdx
+; AVX2-NEXT: vextractps $3, %xmm0, %eax
+; AVX2-NEXT: cmovbel %ecx, %eax
+; AVX2-NEXT: movl %eax, -24(%rsp,%rdx,4)
; AVX2-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX2-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/xaluo.ll b/llvm/test/CodeGen/X86/xaluo.ll
index c2a8002c949ce..fb6f4590d9736 100644
--- a/llvm/test/CodeGen/X86/xaluo.ll
+++ b/llvm/test/CodeGen/X86/xaluo.ll
@@ -966,7 +966,7 @@ define {i64, i1} @uaddoovf(i64 %a, i64 %b) {
; CHECK: ## %bb.0:
; CHECK-NEXT: movzbl %dil, %ecx
; CHECK-NEXT: movzbl %sil, %eax
-; CHECK-NEXT: addq %rcx, %rax
+; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: retq
%1 = and i64 %a, 255
>From 651e64107909c2c36420e7e1fa0d02c939300809 Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames at gmail.com>
Date: Mon, 13 Apr 2026 10:11:43 +0100
Subject: [PATCH 31/36] [ORC] Forward declare DylibManager in
ExecutorProcessControl.h. (#191771)
---
.../ExecutionEngine/Orc/EPCGenericDylibManager.h | 1 +
.../ExecutionEngine/Orc/ExecutorProcessControl.h | 2 +-
.../Orc/SelfExecutorProcessControl.h | 12 +-----------
.../Orc/SelfExecutorProcessControl.cpp | 13 +++++++++++++
4 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/EPCGenericDylibManager.h b/llvm/include/llvm/ExecutionEngine/Orc/EPCGenericDylibManager.h
index 12394e85ff2c9..2836467f07df3 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/EPCGenericDylibManager.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/EPCGenericDylibManager.h
@@ -18,6 +18,7 @@
#ifndef LLVM_EXECUTIONENGINE_ORC_EPCGENERICDYLIBMANAGER_H
#define LLVM_EXECUTIONENGINE_ORC_EPCGENERICDYLIBMANAGER_H
+#include "llvm/ExecutionEngine/Orc/DylibManager.h"
#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h"
#include "llvm/ExecutionEngine/Orc/Shared/ExecutorSymbolDef.h"
#include "llvm/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.h"
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h b/llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
index f0479bfc0ef9e..78d39fcb11581 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
@@ -15,7 +15,6 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/ExecutionEngine/JITLink/JITLinkMemoryManager.h"
-#include "llvm/ExecutionEngine/Orc/DylibManager.h"
#include "llvm/ExecutionEngine/Orc/MemoryAccess.h"
#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h"
#include "llvm/ExecutionEngine/Orc/Shared/TargetProcessControlTypes.h"
@@ -32,6 +31,7 @@
namespace llvm::orc {
+class DylibManager;
class ExecutionSession;
/// ExecutorProcessControl supports interaction with a JIT target process.
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/SelfExecutorProcessControl.h b/llvm/include/llvm/ExecutionEngine/Orc/SelfExecutorProcessControl.h
index d09998328d48c..f741d665c2421 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/SelfExecutorProcessControl.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/SelfExecutorProcessControl.h
@@ -56,17 +56,7 @@ class LLVM_ABI SelfExecutorProcessControl : public ExecutorProcessControl {
Error disconnect() override;
private:
- class InProcessDylibManager : public DylibManager {
- public:
- InProcessDylibManager(char GlobalManglingPrefix);
- Expected<tpctypes::DylibHandle> loadDylib(const char *DylibPath) override;
- void
- lookupSymbolsAsync(ArrayRef<LookupRequest> Request,
- DylibManager::SymbolLookupCompleteFn Complete) override;
-
- private:
- char GlobalManglingPrefix;
- };
+ class InProcessDylibManager;
static shared::CWrapperFunctionBuffer
jitDispatchViaWrapperFunctionManager(void *Ctx, const void *FnTag,
diff --git a/llvm/lib/ExecutionEngine/Orc/SelfExecutorProcessControl.cpp b/llvm/lib/ExecutionEngine/Orc/SelfExecutorProcessControl.cpp
index 4c15ab82857a4..b24abafa82895 100644
--- a/llvm/lib/ExecutionEngine/Orc/SelfExecutorProcessControl.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/SelfExecutorProcessControl.cpp
@@ -9,6 +9,7 @@
#include "llvm/ExecutionEngine/Orc/SelfExecutorProcessControl.h"
#include "llvm/ExecutionEngine/Orc/Core.h"
+#include "llvm/ExecutionEngine/Orc/DylibManager.h"
#include "llvm/ExecutionEngine/Orc/InProcessMemoryAccess.h"
#include "llvm/ExecutionEngine/Orc/TargetProcess/DefaultHostBootstrapValues.h"
#include "llvm/ExecutionEngine/Orc/TargetProcess/TargetExecutionUtils.h"
@@ -20,6 +21,18 @@
namespace llvm::orc {
+class SelfExecutorProcessControl::InProcessDylibManager : public DylibManager {
+public:
+ InProcessDylibManager(char GlobalManglingPrefix);
+ Expected<tpctypes::DylibHandle> loadDylib(const char *DylibPath) override;
+ void
+ lookupSymbolsAsync(ArrayRef<LookupRequest> Request,
+ DylibManager::SymbolLookupCompleteFn Complete) override;
+
+private:
+ char GlobalManglingPrefix;
+};
+
SelfExecutorProcessControl::SelfExecutorProcessControl(
std::shared_ptr<SymbolStringPool> SSP, std::unique_ptr<TaskDispatcher> D,
Triple TargetTriple, unsigned PageSize,
>From d4c4a98582d148f99f0c0a7656d6af8b58a29ea9 Mon Sep 17 00:00:00 2001
From: eiytoq <eiytoq at outlook.com>
Date: Mon, 13 Apr 2026 17:16:44 +0800
Subject: [PATCH 32/36] [libc++] Fix the mdspan ElementType complete object
type mandate (#191703)
Fixes: #191688
---
libcxx/include/__mdspan/mdspan.h | 4 ++
.../mdspan/mdspan/element_type.verify.cpp | 46 +++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/libcxx/include/__mdspan/mdspan.h b/libcxx/include/__mdspan/mdspan.h
index 7f222733cc4c5..024c1002b1a09 100644
--- a/libcxx/include/__mdspan/mdspan.h
+++ b/libcxx/include/__mdspan/mdspan.h
@@ -30,6 +30,7 @@
#include <__type_traits/is_constructible.h>
#include <__type_traits/is_convertible.h>
#include <__type_traits/is_nothrow_constructible.h>
+#include <__type_traits/is_object.h>
#include <__type_traits/is_pointer.h>
#include <__type_traits/is_same.h>
#include <__type_traits/rank.h>
@@ -66,6 +67,9 @@ class mdspan {
private:
static_assert(__mdspan_detail::__is_extents_v<_Extents>,
"mdspan: Extents template parameter must be a specialization of extents.");
+ static_assert(
+ is_object_v<_ElementType> && requires { sizeof(_ElementType); },
+ "mdspan: ElementType template parameter must be a complete object type");
static_assert(!is_array_v<_ElementType>, "mdspan: ElementType template parameter may not be an array type");
static_assert(!is_abstract_v<_ElementType>, "mdspan: ElementType template parameter may not be an abstract class");
static_assert(is_same_v<_ElementType, typename _AccessorPolicy::element_type>,
diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/element_type.verify.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/element_type.verify.cpp
index 9f2730262d953..4fd96cde837ab 100644
--- a/libcxx/test/std/containers/views/mdspan/mdspan/element_type.verify.cpp
+++ b/libcxx/test/std/containers/views/mdspan/mdspan/element_type.verify.cpp
@@ -18,11 +18,57 @@
#include <mdspan>
+struct Incomplete;
+
class AbstractClass {
public:
virtual void method() = 0;
};
+struct VoidAccessor {
+ using offset_policy = VoidAccessor;
+ using element_type = void;
+ using reference = void;
+ using data_handle_type = element_type*;
+ reference access(data_handle_type, std::size_t) const;
+};
+
+struct RefAccessor {
+ using offset_policy = RefAccessor;
+ using element_type = int&;
+ using reference = int&;
+ using data_handle_type = int*;
+ reference access(data_handle_type p, std::size_t i) const { return p[i]; }
+};
+
+struct FuncAccessor {
+ using offset_policy = FuncAccessor;
+ using element_type = int();
+ using reference = int (&)();
+ using data_handle_type = int (*)();
+ reference access(data_handle_type, std::size_t) const;
+};
+
+void incomplete_object_type() {
+ // expected-error-re@*:* {{static assertion failed {{.*}}mdspan: ElementType template parameter must be a complete object type}}
+ [[maybe_unused]] std::mdspan<Incomplete, std::dextents<std::size_t, 2>> m;
+}
+
+void void_type() {
+ // expected-error-re@*:* {{static assertion failed {{.*}}mdspan: ElementType template parameter must be a complete object type}}
+ [[maybe_unused]] std::mdspan<void, std::dextents<std::size_t, 2>, std::layout_right, VoidAccessor> m;
+}
+
+void reference_type() {
+ // expected-error-re@*:* {{static assertion failed {{.*}}mdspan: ElementType template parameter must be a complete object type}}
+ [[maybe_unused]] std::mdspan<int&, std::dextents<std::size_t, 2>, std::layout_right, RefAccessor> m;
+}
+
+void function_type() {
+ // expected-error-re@*:* {{static assertion failed {{.*}}mdspan: ElementType template parameter must be a complete object type}}
+ [[maybe_unused]] std::mdspan<int(), std::dextents<std::size_t, 2>, std::layout_right, FuncAccessor> m;
+}
+
void not_abstract_class() {
// expected-error-re@*:* {{static assertion failed {{.*}}mdspan: ElementType template parameter may not be an abstract class}}
[[maybe_unused]] std::mdspan<AbstractClass, std::extents<int>> m;
>From f04deb889cba76a92618a277f165196cb27d1ed2 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Mon, 13 Apr 2026 11:43:32 +0200
Subject: [PATCH 33/36] [AArch64] Don't forcefully add ORE to O0 pipeline
(#191476)
Construct the OptimizationRemarkEmitter in AArch64StackTagging on demand
if not available and requires, this avoids computing several analysis in
all pipelines.
---
llvm/lib/Target/AArch64/AArch64StackTagging.cpp | 16 ++++++++++++----
llvm/test/CodeGen/AArch64/O0-pipeline.ll | 7 +------
llvm/test/CodeGen/AArch64/O3-pipeline.ll | 4 ----
3 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64StackTagging.cpp b/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
index 787928246eaed..7ef18fa18255d 100644
--- a/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
@@ -333,7 +333,7 @@ class AArch64StackTagging : public FunctionPass {
AU.addRequired<StackSafetyGlobalInfoWrapperPass>();
if (MergeInit)
AU.addRequired<AAResultsWrapperPass>();
- AU.addRequired<OptimizationRemarkEmitterWrapperPass>();
+ AU.addUsedIfAvailable<OptimizationRemarkEmitterWrapperPass>();
}
};
@@ -518,12 +518,20 @@ bool AArch64StackTagging::runOnFunction(Function &Fn) {
DL = &Fn.getDataLayout();
if (MergeInit)
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
- OptimizationRemarkEmitter &ORE =
- getAnalysis<OptimizationRemarkEmitterWrapperPass>().getORE();
+
+ std::unique_ptr<OptimizationRemarkEmitter> DeleteORE;
+ OptimizationRemarkEmitter *ORE = nullptr;
+ if (auto *P = getAnalysisIfAvailable<OptimizationRemarkEmitterWrapperPass>())
+ ORE = &P->getORE();
+
+ if (ORE == nullptr) {
+ DeleteORE = std::make_unique<OptimizationRemarkEmitter>(F);
+ ORE = DeleteORE.get();
+ }
memtag::StackInfoBuilder SIB(SSI, DEBUG_TYPE);
for (Instruction &I : instructions(F))
- SIB.visit(ORE, I);
+ SIB.visit(*ORE, I);
memtag::StackInfo &SInfo = SIB.get();
if (SInfo.AllocasToInstrument.empty())
diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
index 32dbe49df0c1d..c0918a1949499 100644
--- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
@@ -11,8 +11,8 @@
; CHECK-NEXT: Target Transform Information
; CHECK-NEXT: Library Function Lowering Analysis
; CHECK-NEXT: Create Garbage Collector Module Metadata
-; CHECK-NEXT: Profile summary info
; CHECK-NEXT: Assumption Cache Tracker
+; CHECK-NEXT: Profile summary info
; CHECK-NEXT: Machine Branch Probability Analysis
; CHECK-NEXT: ModulePass Manager
; CHECK-NEXT: Pre-ISel Intrinsic Lowering
@@ -26,11 +26,6 @@
; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
; CHECK-NEXT: Scalarize Masked Memory Intrinsics
; CHECK-NEXT: Expand reduction intrinsics
-; CHECK-NEXT: Dominator Tree Construction
-; CHECK-NEXT: Natural Loop Information
-; CHECK-NEXT: Lazy Branch Probability Analysis
-; CHECK-NEXT: Lazy Block Frequency Analysis
-; CHECK-NEXT: Optimization Remark Emitter
; CHECK-NEXT: AArch64 Stack Tagging
; CHECK-NEXT: Exception handling preparation
; CHECK-NEXT: Prepare inline asm insts
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index ff4f28a3a50c1..546949aa4e209 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -83,10 +83,6 @@
; CHECK-NEXT: Dominator Tree Construction
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results
-; CHECK-NEXT: Natural Loop Information
-; CHECK-NEXT: Lazy Branch Probability Analysis
-; CHECK-NEXT: Lazy Block Frequency Analysis
-; CHECK-NEXT: Optimization Remark Emitter
; CHECK-NEXT: AArch64 Stack Tagging
; CHECK-NEXT: Complex Deinterleaving Pass
; CHECK-NEXT: Function Alias Analysis Results
>From e1bf7214468ea66b3a2b7386875ebacf20bcc2d3 Mon Sep 17 00:00:00 2001
From: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: Mon, 13 Apr 2026 12:00:36 +0200
Subject: [PATCH 34/36] [libc][bazel][math][NFC] Fix deps (#191785)
---
utils/bazel/llvm-project-overlay/libc/BUILD.bazel | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
index 3f56367efff51..d97d65e4ee43a 100644
--- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel
@@ -5264,7 +5264,7 @@ libc_support_library(
":__support_fputil_fenv_impl",
":__support_fputil_fp_bits",
":__support_fputil_multiply_add",
- ":__support_fputil_poly_eval",
+ ":__support_fputil_polyeval",
":__support_macros_config",
":__support_macros_optimization",
":__support_macros_properties_cpu_features",
@@ -5325,7 +5325,7 @@ libc_support_library(
":__support_fputil_fenv_impl",
":__support_fputil_fp_bits",
":__support_fputil_multiply_add",
- ":__support_fputil_poly_eval",
+ ":__support_fputil_polyeval",
":__support_macros_config",
":__support_macros_optimization",
":__support_macros_properties_cpu_features",
>From 4e245a433ddf9df533a72534c2dada54b02f39bc Mon Sep 17 00:00:00 2001
From: Matthew Nagy <matthew.nagy at sony.com>
Date: Mon, 13 Apr 2026 11:03:02 +0100
Subject: [PATCH 35/36] =?UTF-8?q?[TySan][Sanitizer=20Common]=20Make=20TySa?=
=?UTF-8?q?n=20compatible=20with=20sanitizer=20common=E2=80=A6=20(#183310)?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
… features and test suite
This involved:
- Implementing the `__sanitizer_print_stack_trace` interface
- Adding the common signal handlers
- Correctly set the tool name
- Cache the binary name before running
---
compiler-rt/lib/tysan/tysan.cpp | 40 ++++++++++++++++----
compiler-rt/lib/tysan/tysan_interceptors.cpp | 34 ++++++++++++++++-
2 files changed, 66 insertions(+), 8 deletions(-)
diff --git a/compiler-rt/lib/tysan/tysan.cpp b/compiler-rt/lib/tysan/tysan.cpp
index 52f941180b8eb..c02e80dfea441 100644
--- a/compiler-rt/lib/tysan/tysan.cpp
+++ b/compiler-rt/lib/tysan/tysan.cpp
@@ -15,6 +15,7 @@
#include "sanitizer_common/sanitizer_common.h"
#include "sanitizer_common/sanitizer_flag_parser.h"
#include "sanitizer_common/sanitizer_flags.h"
+#include "sanitizer_common/sanitizer_interface_internal.h"
#include "sanitizer_common/sanitizer_libc.h"
#include "sanitizer_common/sanitizer_report_decorator.h"
#include "sanitizer_common/sanitizer_stacktrace.h"
@@ -40,6 +41,30 @@ tysan_copy_types(const void *daddr, const void *saddr, uptr size) {
internal_memmove(shadow_for(daddr), shadow_for(saddr), size * sizeof(uptr));
}
+static void getStackTrace(bool fullStacktrace, uptr pc, uptr bp,
+ BufferedStackTrace *ST) {
+ uptr top = 0;
+ uptr bottom = 0;
+ if (fullStacktrace)
+ GetThreadStackTopAndBottom(false, &top, &bottom);
+ bool request_fast = StackTrace::WillUseFastUnwind(true);
+ ST->Unwind(kStackTraceMax, pc, bp, 0, top, bottom, request_fast);
+}
+
+namespace __tysan {
+void OnStackUnwind(const SignalContext &sig, const void *,
+ BufferedStackTrace *stack) {
+ getStackTrace(true, StackTrace::GetNextInstructionPc(sig.pc), sig.bp, stack);
+}
+} // namespace __tysan
+
+extern "C" SANITIZER_INTERFACE_ATTRIBUTE void __sanitizer_print_stack_trace() {
+ GET_CURRENT_PC_BP;
+ UNINITIALIZED BufferedStackTrace stack;
+ getStackTrace(true, pc, bp, &stack);
+ stack.Print();
+}
+
static const char *getDisplayName(const char *Name) {
if (Name[0] == '\0')
return "<anonymous type>";
@@ -241,14 +266,8 @@ static void reportError(void *Addr, int Size, tysan_type_descriptor *TD,
Printf("\n");
if (pc) {
- uptr top = 0;
- uptr bottom = 0;
- if (flags().print_stacktrace)
- GetThreadStackTopAndBottom(false, &top, &bottom);
-
- bool request_fast = StackTrace::WillUseFastUnwind(true);
BufferedStackTrace ST;
- ST.Unwind(kStackTraceMax, pc, bp, 0, top, bottom, request_fast);
+ getStackTrace(flags().print_stacktrace, pc, bp, &ST);
ST.Print();
} else {
Printf("\n");
@@ -465,6 +484,8 @@ static void InitializeFlags() {
ReportUnrecognizedFlags();
if (common_flags()->help)
parser.PrintFlagDescriptions();
+
+ __sanitizer_set_report_path(common_flags()->log_path);
}
static void TySanInitializePlatformEarly() {
@@ -489,9 +510,13 @@ static void TySanInitializePlatformEarly() {
namespace __tysan {
bool tysan_inited = false;
bool tysan_init_is_running;
+void InitializeDeadlySignals();
} // namespace __tysan
extern "C" SANITIZER_INTERFACE_ATTRIBUTE void __tysan_init() {
+ SanitizerToolName = "TypeSanitizer";
+ CacheBinaryName();
+
CHECK(!tysan_init_is_running);
if (tysan_inited)
return;
@@ -501,6 +526,7 @@ extern "C" SANITIZER_INTERFACE_ATTRIBUTE void __tysan_init() {
TySanInitializePlatformEarly();
InitializeInterceptors();
+ InitializeDeadlySignals();
if (!MmapFixedNoReserve(ShadowAddr(), AppAddr() - ShadowAddr()))
Die();
diff --git a/compiler-rt/lib/tysan/tysan_interceptors.cpp b/compiler-rt/lib/tysan/tysan_interceptors.cpp
index a9c55a3ae0cf0..0361c794cb10f 100644
--- a/compiler-rt/lib/tysan/tysan_interceptors.cpp
+++ b/compiler-rt/lib/tysan/tysan_interceptors.cpp
@@ -22,12 +22,44 @@
#define TYSAN_INTERCEPT___STRDUP 0
#endif
+#define TYSAN_INTERCEPT_FUNC(name) \
+ do { \
+ if (!INTERCEPT_FUNCTION(name)) \
+ VReport(1, "TypeSanitizer: failed to intercept '%s'\n", #name); \
+ } while (0)
+
#if SANITIZER_LINUX
extern "C" int mallopt(int param, int value);
#endif
using namespace __sanitizer;
using namespace __tysan;
+namespace __tysan {
+// Defined in tysan.cpp
+void OnStackUnwind(const SignalContext &sig, const void *,
+ BufferedStackTrace *stack);
+
+static void TysanOnDeadlySignal(int signo, void *siginfo, void *context) {
+ HandleDeadlySignal(siginfo, context, GetTid(), &OnStackUnwind, nullptr);
+}
+
+static bool tysanSignalsInitialized = false;
+void InitializeDeadlySignals();
+} // namespace __tysan
+
+#define SIGNAL_INTERCEPTOR_ENTER() __tysan::InitializeDeadlySignals()
+#define COMMON_INTERCEPT_FUNCTION(name) TYSAN_INTERCEPT_FUNC(name)
+#include "sanitizer_common/sanitizer_signal_interceptors.inc"
+
+namespace __tysan {
+void InitializeDeadlySignals() {
+ if (tysanSignalsInitialized)
+ return;
+ InitializeSignalInterceptors();
+ InstallDeadlySignalHandlers(&TysanOnDeadlySignal);
+ tysanSignalsInitialized = true;
+}
+} // namespace __tysan
namespace {
struct DlsymAlloc : public DlSymAllocator<DlsymAlloc> {
@@ -233,7 +265,7 @@ void InitializeInterceptors() {
TYSAN_MAYBE_INTERCEPT_MEMALIGN;
TYSAN_MAYBE_INTERCEPT___LIBC_MEMALIGN;
TYSAN_MAYBE_INTERCEPT_PVALLOC;
- TYSAN_MAYBE_INTERCEPT_ALIGNED_ALLOC
+ TYSAN_MAYBE_INTERCEPT_ALIGNED_ALLOC;
INTERCEPT_FUNCTION(posix_memalign);
INTERCEPT_FUNCTION(memset);
>From 45932f4cfcb0476b240e9613eb50fd6f4e80c682 Mon Sep 17 00:00:00 2001
From: 2elliti <forstoic724321 at gmail.com>
Date: Mon, 13 Apr 2026 15:49:37 +0530
Subject: [PATCH 36/36] Address review feedback: capitalize variable name
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 15c7264f61249..3bc873cd61ff9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -59404,15 +59404,15 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
// If upper 33 bits of operands are 0, truncates opcode from i64 to i32.
if (VT == MVT::i64) {
- APInt mask = APInt::getHighBitsSet(64, 33);
- if (DAG.MaskedValueIsZero(Op0, mask) && DAG.MaskedValueIsZero(Op1, mask)) {
+ APInt Mask = APInt::getHighBitsSet(64, 33);
+ if (DAG.MaskedValueIsZero(Op0, Mask) && DAG.MaskedValueIsZero(Op1, Mask)) {
// Truncate operands MVT::i64 -> MVT::i32
SDValue X = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op0);
SDValue Y = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
// now check for NUW and NSW
SDNodeFlags Flags;
- // No unsigned wrap, both operands has their upper 33bits 0, making their
+ // No unsigned wrap, both operands have their upper 33bits 0, making their
// sum lower then max unsigned int32.
Flags.setNoUnsignedWrap(true);
Flags.setNoSignedWrap(DAG.willNotOverflowAdd(true, X, Y));
More information about the Mlir-commits
mailing list