[Mlir-commits] [mlir] [XeVM] Refactor the SPIR-V generation to use SPIR-V backend API. (PR #189494)

[Md Abdullah Shahneous Bari]

================
@@ -375,6 +327,27 @@ SPIRVSerializer::moduleToObject(llvm::Module &llvmModule) {
 
   StringRef spirvBin(serializedSPIRVBinary.c_str(),
                      serializedSPIRVBinary.size());
+
+  // Return SPIRV binary if the compilation target is `assembly`. Optimization
+  // and SPIR-V extensions are enabled for SPIR-V binary output in both paths
+  // (assembly and binary) as of now. SPIR-V binary
+  // is generated directly using the SPIR-V backends `SPIRVTranslate` API.
----------------
mshahneo wrote:

Thanks, @silee2 for the suggestions. Actually the comment is to specify that when handling 
```
targetOptions.getCompilationTarget() ==
      gpu::CompilationTarget::Assembly
```
we return SPIR-V binary as opposed to textual ISA returned by other targets (Rocm, nvvm).
The next line is added to added to clarify how we generate this.

But added a comment before `SPIRVTranslateModule` API for clarification as well.

https://github.com/llvm/llvm-project/pull/189494