[Mlir-commits] [mlir] Enable printing newlines and indents in attribute and type printers (PR #87948)

[Jacenty Andruszkiewicz]

Jacenty-And-Intel wrote:

Example of usage can be found in our public [codebase](https://github.com/openvinotoolkit/npu_compiler/blob/develop/tests/lit/NPU/dialect/VPURegMapped/reg_mapped_test.mlir). Newlines and nesting of attributes is used for operation [descriptors](https://github.com/openvinotoolkit/npu_compiler/blob/develop/src/vpux_compiler/include/vpux/compiler/dialect/VPURegMapped/descriptors.hpp#L500-L522). Here is a small snippet from IR with an operation that have implemented custom pretty printers and is using nested attributes:
```
NPUReg40XX.DPUInvariant descriptor = <
  DpuInvariantRegister {
    cmx_slice0_low_addr = UINT 0x4000000,
    cmx_slice1_low_addr = UINT 0x4000000,
    cmx_slice2_low_addr = UINT 0x4000000,
    cmx_slice3_low_addr = UINT 0x4000000,
    cmx_slice_size = UINT 0x18000,
    se_addr = UINT 0,
    sparsity_addr = UINT 0,
    se_size = UINT 0,
    z_config {
      UINT se_z_split = 0,
      UINT num_ses_in_z_dir = 0,
      UINT cm_sp_pattern = 0,
      UINT npo2_se_z_split_en = 0,
      UINT reserved = 0,
      UINT addr_format_sel = 1,
    }
  } requires 11:4:10
>
```
When printing descriptor as a regular attribute it looses readability and it's hard to analyze:
```
NPUReg40XX.DPUInvariant descriptor = < DpuInvariantRegister { cmx_slice0_low_addr = UINT 0x4000000, cmx_slice1_low_addr = UINT 0x4000000, cmx_slice2_low_addr = UINT 0x4000000, cmx_slice3_low_addr = UINT 0x4000000, cmx_slice_size = UINT 0x18000, se_addr = UINT 0, sparsity_addr = UINT 0, se_size = UINT 0, z_config { UINT se_z_split = 0, UINT num_ses_in_z_dir = 0, UINT cm_sp_pattern = 0, UINT npo2_se_z_split_en = 0, UINT reserved = 0, UINT addr_format_sel = 1, } } requires 11:4:10 >
```
The example above only presents small part of real operation. In real world scenario operations have hundreds of nested attributes what makes them completely unreadable when printed in one line. Here is an [example of full operation](https://gist.github.com/Jacenty-And-Intel/98fe1fcd983670f83bb088a4a38e4e67) with and without formatting of the nested attributes.

https://github.com/llvm/llvm-project/pull/87948