[Mlir-commits] [mlir] [MLIR][XeVM] Add xevm blockload and blockstore op definition. (PR #158118)

[Sang Ik Lee]

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@@ -306,6 +307,36 @@ LogicalResult BlockPrefetch2dOp::verify() {
   return success();
 }
 
+template <typename OpType, typename = std::enable_if_t<llvm::is_one_of<
+                               OpType, BlockLoadOp, BlockStoreOp>::value>>
+LogicalResult verify1DBlockArg(OpType op) {
+  VectorType vTy;
+  if constexpr (std::is_same_v<OpType, BlockLoadOp>)
+    vTy = op.getResult().getType();
+  else
+    vTy = op.getVal().getType();
+  int elemTySize = vTy.getElementType().getIntOrFloatBitWidth() / 8;
+  if (elemTySize == 1) {
+    llvm::SmallSet<int, 5> validSizes{1, 2, 4, 8, 16};
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silee2 wrote:

Not target arch or chip specific but the restrictions are OpenCL / SPIR-V Intel extensions specific.
In that sense, it applies to all Intel HW and not target specific.

https://github.com/llvm/llvm-project/pull/158118