[Mlir-commits] [mlir] [MLIR][NVVM][Refactor] Refactor intrinsic lowering for NVVM Ops (PR #157079)
Srinivasa Ravi
llvmlistbot at llvm.org
Tue Sep 16 10:11:38 PDT 2025
================
@@ -1641,46 +1644,115 @@ CpAsyncBulkTensorSharedCTAToGlobalOp::getIntrinsicIDAndArgs(
is_im2col ? CP_ASYNC_BULK_TENSOR_REDUCE_MODE(op, dim, im2col) \
: CP_ASYNC_BULK_TENSOR_REDUCE_MODE(op, dim, tile)
-#define GET_CP_ASYNC_BULK_TENSOR_ID(op, dims, is_im2col) \
- [&]() -> auto { \
- switch (dims) { \
- case 1: \
- return CP_ASYNC_BULK_TENSOR_REDUCE_MODE(op, 1, tile); \
- case 2: \
- return CP_ASYNC_BULK_TENSOR_REDUCE_MODE(op, 2, tile); \
- case 3: \
- return CP_ASYNC_BULK_TENSOR_REDUCE(op, 3, is_im2col); \
- case 4: \
- return CP_ASYNC_BULK_TENSOR_REDUCE(op, 4, is_im2col); \
- case 5: \
- return CP_ASYNC_BULK_TENSOR_REDUCE(op, 5, is_im2col); \
- default: \
- llvm_unreachable("Invalid TensorDim in CpAsyncBulkTensorReduceOp."); \
- } \
- }()
+#define GET_CP_ASYNC_BULK_TENSOR_ID(iid, op, dims, is_im2col) \
+ switch (dims) { \
+ case 1: \
+ iid = CP_ASYNC_BULK_TENSOR_REDUCE_MODE(op, 1, tile); \
----------------
Wolfram70 wrote:
We are actually removing the macros from here in https://github.com/llvm/llvm-project/pull/157423 and changing this function. This PR will be rebased when that is merged.
https://github.com/llvm/llvm-project/pull/157079
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