[Mlir-commits] [clang] [llvm] [mlir] [AArch64][SME] Improve codegen for aarch64.sme.cnts* when not in streaming mode (PR #154761)

[Benjamin Maxwell]

================
@@ -937,6 +940,23 @@ bool AArch64DAGToDAGISel::SelectRDVLImm(SDValue N, SDValue &Imm) {
   return false;
 }
 
+template <signed Low, signed High>
+bool AArch64DAGToDAGISel::SelectRDSVLShiftImm(SDValue N, SDValue &Imm) {
+  if (!isa<ConstantSDNode>(N))
+    return false;
+
----------------
MacDue wrote:

Could you add a comment like:
```
cntsd = (rdvl, #1) >> 3

So, if we have (cntsd << #ShlImm), where ShlImm >= 3, attempt to fold into:

rdvl, #(ShlImm - 3) 
```

https://github.com/llvm/llvm-project/pull/154761